1 /* 2 * Core routines and tables shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2002 Justin T. Gibbs. 5 * Copyright (c) 2000-2002 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $ 41 */ 42 43 #ifdef __linux__ 44 #include "aic7xxx_osm.h" 45 #include "aic7xxx_inline.h" 46 #include "aicasm/aicasm_insformat.h" 47 #else 48 #include <sys/cdefs.h> 49 __FBSDID("$FreeBSD$"); 50 #include <dev/aic7xxx/aic7xxx_osm.h> 51 #include <dev/aic7xxx/aic7xxx_inline.h> 52 #include <dev/aic7xxx/aicasm/aicasm_insformat.h> 53 #endif 54 55 /****************************** Softc Data ************************************/ 56 struct ahc_softc_tailq ahc_tailq = TAILQ_HEAD_INITIALIZER(ahc_tailq); 57 58 /***************************** Lookup Tables **********************************/ 59 char *ahc_chip_names[] = 60 { 61 "NONE", 62 "aic7770", 63 "aic7850", 64 "aic7855", 65 "aic7859", 66 "aic7860", 67 "aic7870", 68 "aic7880", 69 "aic7895", 70 "aic7895C", 71 "aic7890/91", 72 "aic7896/97", 73 "aic7892", 74 "aic7899" 75 }; 76 static const u_int num_chip_names = NUM_ELEMENTS(ahc_chip_names); 77 78 /* 79 * Hardware error codes. 80 */ 81 struct ahc_hard_error_entry { 82 uint8_t errno; 83 char *errmesg; 84 }; 85 86 static struct ahc_hard_error_entry ahc_hard_errors[] = { 87 { ILLHADDR, "Illegal Host Access" }, 88 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 89 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 90 { SQPARERR, "Sequencer Parity Error" }, 91 { DPARERR, "Data-path Parity Error" }, 92 { MPARERR, "Scratch or SCB Memory Parity Error" }, 93 { PCIERRSTAT, "PCI Error detected" }, 94 { CIOPARERR, "CIOBUS Parity Error" }, 95 }; 96 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors); 97 98 static struct ahc_phase_table_entry ahc_phase_table[] = 99 { 100 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 101 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 102 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 103 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 104 { P_COMMAND, MSG_NOOP, "in Command phase" }, 105 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 106 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 107 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 108 { P_BUSFREE, MSG_NOOP, "while idle" }, 109 { 0, MSG_NOOP, "in unknown phase" } 110 }; 111 112 /* 113 * In most cases we only wish to itterate over real phases, so 114 * exclude the last element from the count. 115 */ 116 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1; 117 118 /* 119 * Valid SCSIRATE values. (p. 3-17) 120 * Provides a mapping of tranfer periods in ns to the proper value to 121 * stick in the scsixfer reg. 122 */ 123 static struct ahc_syncrate ahc_syncrates[] = 124 { 125 /* ultra2 fast/ultra period rate */ 126 { 0x42, 0x000, 9, "80.0" }, 127 { 0x03, 0x000, 10, "40.0" }, 128 { 0x04, 0x000, 11, "33.0" }, 129 { 0x05, 0x100, 12, "20.0" }, 130 { 0x06, 0x110, 15, "16.0" }, 131 { 0x07, 0x120, 18, "13.4" }, 132 { 0x08, 0x000, 25, "10.0" }, 133 { 0x19, 0x010, 31, "8.0" }, 134 { 0x1a, 0x020, 37, "6.67" }, 135 { 0x1b, 0x030, 43, "5.7" }, 136 { 0x1c, 0x040, 50, "5.0" }, 137 { 0x00, 0x050, 56, "4.4" }, 138 { 0x00, 0x060, 62, "4.0" }, 139 { 0x00, 0x070, 68, "3.6" }, 140 { 0x00, 0x000, 0, NULL } 141 }; 142 143 /* Our Sequencer Program */ 144 #include "aic7xxx_seq.h" 145 146 /**************************** Function Declarations ***************************/ 147 static void ahc_force_renegotiation(struct ahc_softc *ahc, 148 struct ahc_devinfo *devinfo); 149 static struct ahc_tmode_tstate* 150 ahc_alloc_tstate(struct ahc_softc *ahc, 151 u_int scsi_id, char channel); 152 #ifdef AHC_TARGET_MODE 153 static void ahc_free_tstate(struct ahc_softc *ahc, 154 u_int scsi_id, char channel, int force); 155 #endif 156 static struct ahc_syncrate* 157 ahc_devlimited_syncrate(struct ahc_softc *ahc, 158 struct ahc_initiator_tinfo *, 159 u_int *period, 160 u_int *ppr_options, 161 role_t role); 162 static void ahc_update_pending_scbs(struct ahc_softc *ahc); 163 static void ahc_fetch_devinfo(struct ahc_softc *ahc, 164 struct ahc_devinfo *devinfo); 165 static void ahc_scb_devinfo(struct ahc_softc *ahc, 166 struct ahc_devinfo *devinfo, 167 struct scb *scb); 168 static void ahc_assert_atn(struct ahc_softc *ahc); 169 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc, 170 struct ahc_devinfo *devinfo, 171 struct scb *scb); 172 static void ahc_build_transfer_msg(struct ahc_softc *ahc, 173 struct ahc_devinfo *devinfo); 174 static void ahc_construct_sdtr(struct ahc_softc *ahc, 175 struct ahc_devinfo *devinfo, 176 u_int period, u_int offset); 177 static void ahc_construct_wdtr(struct ahc_softc *ahc, 178 struct ahc_devinfo *devinfo, 179 u_int bus_width); 180 static void ahc_construct_ppr(struct ahc_softc *ahc, 181 struct ahc_devinfo *devinfo, 182 u_int period, u_int offset, 183 u_int bus_width, u_int ppr_options); 184 static void ahc_clear_msg_state(struct ahc_softc *ahc); 185 static void ahc_handle_proto_violation(struct ahc_softc *ahc); 186 static void ahc_handle_message_phase(struct ahc_softc *ahc); 187 typedef enum { 188 AHCMSG_1B, 189 AHCMSG_2B, 190 AHCMSG_EXT 191 } ahc_msgtype; 192 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, 193 u_int msgval, int full); 194 static int ahc_parse_msg(struct ahc_softc *ahc, 195 struct ahc_devinfo *devinfo); 196 static int ahc_handle_msg_reject(struct ahc_softc *ahc, 197 struct ahc_devinfo *devinfo); 198 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc, 199 struct ahc_devinfo *devinfo); 200 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc); 201 static void ahc_handle_devreset(struct ahc_softc *ahc, 202 struct ahc_devinfo *devinfo, 203 cam_status status, char *message, 204 int verbose_level); 205 #ifdef AHC_TARGET_MODE 206 static void ahc_setup_target_msgin(struct ahc_softc *ahc, 207 struct ahc_devinfo *devinfo, 208 struct scb *scb); 209 #endif 210 211 static bus_dmamap_callback_t ahc_dmamap_cb; 212 static void ahc_build_free_scb_list(struct ahc_softc *ahc); 213 static int ahc_init_scbdata(struct ahc_softc *ahc); 214 static void ahc_fini_scbdata(struct ahc_softc *ahc); 215 static void ahc_qinfifo_requeue(struct ahc_softc *ahc, 216 struct scb *prev_scb, 217 struct scb *scb); 218 static int ahc_qinfifo_count(struct ahc_softc *ahc); 219 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, 220 u_int prev, u_int scbptr); 221 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc); 222 static u_int ahc_rem_wscb(struct ahc_softc *ahc, 223 u_int scbpos, u_int prev); 224 static void ahc_reset_current_bus(struct ahc_softc *ahc); 225 #ifdef AHC_DUMP_SEQ 226 static void ahc_dumpseq(struct ahc_softc *ahc); 227 #endif 228 static int ahc_loadseq(struct ahc_softc *ahc); 229 static int ahc_check_patch(struct ahc_softc *ahc, 230 struct patch **start_patch, 231 u_int start_instr, u_int *skip_addr); 232 static void ahc_download_instr(struct ahc_softc *ahc, 233 u_int instrptr, uint8_t *dconsts); 234 static int ahc_other_scb_timeout(struct ahc_softc *ahc, 235 struct scb *scb, 236 struct scb *other_scb); 237 #ifdef AHC_TARGET_MODE 238 static void ahc_queue_lstate_event(struct ahc_softc *ahc, 239 struct ahc_tmode_lstate *lstate, 240 u_int initiator_id, 241 u_int event_type, 242 u_int event_arg); 243 static void ahc_update_scsiid(struct ahc_softc *ahc, 244 u_int targid_mask); 245 static int ahc_handle_target_cmd(struct ahc_softc *ahc, 246 struct target_cmd *cmd); 247 #endif 248 /************************* Sequencer Execution Control ************************/ 249 /* 250 * Restart the sequencer program from address zero 251 */ 252 void 253 ahc_restart(struct ahc_softc *ahc) 254 { 255 256 ahc_pause(ahc); 257 258 /* No more pending messages. */ 259 ahc_clear_msg_state(ahc); 260 261 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */ 262 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */ 263 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 264 ahc_outb(ahc, LASTPHASE, P_BUSFREE); 265 ahc_outb(ahc, SAVED_SCSIID, 0xFF); 266 ahc_outb(ahc, SAVED_LUN, 0xFF); 267 268 /* 269 * Ensure that the sequencer's idea of TQINPOS 270 * matches our own. The sequencer increments TQINPOS 271 * only after it sees a DMA complete and a reset could 272 * occur before the increment leaving the kernel to believe 273 * the command arrived but the sequencer to not. 274 */ 275 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 276 277 /* Always allow reselection */ 278 ahc_outb(ahc, SCSISEQ, 279 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 280 if ((ahc->features & AHC_CMD_CHAN) != 0) { 281 /* Ensure that no DMA operations are in progress */ 282 ahc_outb(ahc, CCSCBCNT, 0); 283 ahc_outb(ahc, CCSGCTL, 0); 284 ahc_outb(ahc, CCSCBCTL, 0); 285 } 286 /* 287 * If we were in the process of DMA'ing SCB data into 288 * an SCB, replace that SCB on the free list. This prevents 289 * an SCB leak. 290 */ 291 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) { 292 ahc_add_curscb_to_free_list(ahc); 293 ahc_outb(ahc, SEQ_FLAGS2, 294 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA); 295 } 296 297 /* 298 * Clear any pending sequencer interrupt. It is no 299 * longer relevant since we're resetting the Program 300 * Counter. 301 */ 302 ahc_outb(ahc, CLRINT, CLRSEQINT); 303 304 ahc_outb(ahc, MWI_RESIDUAL, 0); 305 ahc_outb(ahc, SEQCTL, ahc->seqctl); 306 ahc_outb(ahc, SEQADDR0, 0); 307 ahc_outb(ahc, SEQADDR1, 0); 308 309 ahc_unpause(ahc); 310 } 311 312 /************************* Input/Output Queues ********************************/ 313 void 314 ahc_run_qoutfifo(struct ahc_softc *ahc) 315 { 316 struct scb *scb; 317 u_int scb_index; 318 319 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 320 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 321 322 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 323 if ((ahc->qoutfifonext & 0x03) == 0x03) { 324 u_int modnext; 325 326 /* 327 * Clear 32bits of QOUTFIFO at a time 328 * so that we don't clobber an incoming 329 * byte DMA to the array on architectures 330 * that only support 32bit load and store 331 * operations. 332 */ 333 modnext = ahc->qoutfifonext & ~0x3; 334 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL; 335 aic_dmamap_sync(ahc, ahc->shared_data_dmat, 336 ahc->shared_data_dmamap, 337 /*offset*/modnext, /*len*/4, 338 BUS_DMASYNC_PREREAD); 339 } 340 ahc->qoutfifonext++; 341 342 scb = ahc_lookup_scb(ahc, scb_index); 343 if (scb == NULL) { 344 printf("%s: WARNING no command for scb %d " 345 "(cmdcmplt)\nQOUTPOS = %d\n", 346 ahc_name(ahc), scb_index, 347 (ahc->qoutfifonext - 1) & 0xFF); 348 continue; 349 } 350 351 /* 352 * Save off the residual 353 * if there is one. 354 */ 355 ahc_update_residual(ahc, scb); 356 ahc_done(ahc, scb); 357 } 358 } 359 360 void 361 ahc_run_untagged_queues(struct ahc_softc *ahc) 362 { 363 int i; 364 365 for (i = 0; i < 16; i++) 366 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]); 367 } 368 369 void 370 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue) 371 { 372 struct scb *scb; 373 374 if (ahc->untagged_queue_lock != 0) 375 return; 376 377 if ((scb = TAILQ_FIRST(queue)) != NULL 378 && (scb->flags & SCB_ACTIVE) == 0) { 379 scb->flags |= SCB_ACTIVE; 380 aic_scb_timer_start(scb); 381 ahc_queue_scb(ahc, scb); 382 } 383 } 384 385 /************************* Interrupt Handling *********************************/ 386 void 387 ahc_handle_brkadrint(struct ahc_softc *ahc) 388 { 389 /* 390 * We upset the sequencer :-( 391 * Lookup the error message 392 */ 393 int i; 394 int error; 395 396 error = ahc_inb(ahc, ERROR); 397 for (i = 0; error != 1 && i < num_errors; i++) 398 error >>= 1; 399 printf("%s: brkadrint, %s at seqaddr = 0x%x\n", 400 ahc_name(ahc), ahc_hard_errors[i].errmesg, 401 ahc_inb(ahc, SEQADDR0) | 402 (ahc_inb(ahc, SEQADDR1) << 8)); 403 404 ahc_dump_card_state(ahc); 405 406 /* Tell everyone that this HBA is no longer available */ 407 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS, 408 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 409 CAM_NO_HBA); 410 411 /* Disable all interrupt sources by resetting the controller */ 412 ahc_shutdown(ahc); 413 } 414 415 void 416 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 417 { 418 struct scb *scb; 419 struct ahc_devinfo devinfo; 420 421 ahc_fetch_devinfo(ahc, &devinfo); 422 423 /* 424 * Clear the upper byte that holds SEQINT status 425 * codes and clear the SEQINT bit. We will unpause 426 * the sequencer, if appropriate, after servicing 427 * the request. 428 */ 429 ahc_outb(ahc, CLRINT, CLRSEQINT); 430 switch (intstat & SEQINT_MASK) { 431 case BAD_STATUS: 432 { 433 u_int scb_index; 434 struct hardware_scb *hscb; 435 436 /* 437 * Set the default return value to 0 (don't 438 * send sense). The sense code will change 439 * this if needed. 440 */ 441 ahc_outb(ahc, RETURN_1, 0); 442 443 /* 444 * The sequencer will notify us when a command 445 * has an error that would be of interest to 446 * the kernel. This allows us to leave the sequencer 447 * running in the common case of command completes 448 * without error. The sequencer will already have 449 * dma'd the SCB back up to us, so we can reference 450 * the in kernel copy directly. 451 */ 452 scb_index = ahc_inb(ahc, SCB_TAG); 453 scb = ahc_lookup_scb(ahc, scb_index); 454 if (scb == NULL) { 455 ahc_print_devinfo(ahc, &devinfo); 456 printf("ahc_intr - referenced scb " 457 "not valid during seqint 0x%x scb(%d)\n", 458 intstat, scb_index); 459 ahc_dump_card_state(ahc); 460 panic("for safety"); 461 goto unpause; 462 } 463 464 hscb = scb->hscb; 465 466 /* Don't want to clobber the original sense code */ 467 if ((scb->flags & SCB_SENSE) != 0) { 468 /* 469 * Clear the SCB_SENSE Flag and have 470 * the sequencer do a normal command 471 * complete. 472 */ 473 scb->flags &= ~SCB_SENSE; 474 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 475 break; 476 } 477 aic_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR); 478 /* Freeze the queue until the client sees the error. */ 479 ahc_freeze_devq(ahc, scb); 480 aic_freeze_scb(scb); 481 aic_set_scsi_status(scb, hscb->shared_data.status.scsi_status); 482 switch (hscb->shared_data.status.scsi_status) { 483 case SCSI_STATUS_OK: 484 printf("%s: Interrupted for staus of 0???\n", 485 ahc_name(ahc)); 486 break; 487 case SCSI_STATUS_CMD_TERMINATED: 488 case SCSI_STATUS_CHECK_COND: 489 { 490 struct ahc_dma_seg *sg; 491 struct scsi_sense *sc; 492 struct ahc_initiator_tinfo *targ_info; 493 struct ahc_tmode_tstate *tstate; 494 struct ahc_transinfo *tinfo; 495 #ifdef AHC_DEBUG 496 if (ahc_debug & AHC_SHOW_SENSE) { 497 ahc_print_path(ahc, scb); 498 printf("SCB %d: requests Check Status\n", 499 scb->hscb->tag); 500 } 501 #endif 502 503 if (aic_perform_autosense(scb) == 0) 504 break; 505 506 targ_info = ahc_fetch_transinfo(ahc, 507 devinfo.channel, 508 devinfo.our_scsiid, 509 devinfo.target, 510 &tstate); 511 tinfo = &targ_info->curr; 512 sg = scb->sg_list; 513 sc = (struct scsi_sense *)(&hscb->shared_data.cdb); 514 /* 515 * Save off the residual if there is one. 516 */ 517 ahc_update_residual(ahc, scb); 518 #ifdef AHC_DEBUG 519 if (ahc_debug & AHC_SHOW_SENSE) { 520 ahc_print_path(ahc, scb); 521 printf("Sending Sense\n"); 522 } 523 #endif 524 sg->addr = ahc_get_sense_bufaddr(ahc, scb); 525 sg->len = aic_get_sense_bufsize(ahc, scb); 526 sg->len |= AHC_DMA_LAST_SEG; 527 528 /* Fixup byte order */ 529 sg->addr = aic_htole32(sg->addr); 530 sg->len = aic_htole32(sg->len); 531 532 sc->opcode = REQUEST_SENSE; 533 sc->byte2 = 0; 534 if (tinfo->protocol_version <= SCSI_REV_2 535 && SCB_GET_LUN(scb) < 8) 536 sc->byte2 = SCB_GET_LUN(scb) << 5; 537 sc->unused[0] = 0; 538 sc->unused[1] = 0; 539 sc->length = sg->len; 540 sc->control = 0; 541 542 /* 543 * We can't allow the target to disconnect. 544 * This will be an untagged transaction and 545 * having the target disconnect will make this 546 * transaction indestinguishable from outstanding 547 * tagged transactions. 548 */ 549 hscb->control = 0; 550 551 /* 552 * This request sense could be because the 553 * the device lost power or in some other 554 * way has lost our transfer negotiations. 555 * Renegotiate if appropriate. Unit attention 556 * errors will be reported before any data 557 * phases occur. 558 */ 559 if (aic_get_residual(scb) 560 == aic_get_transfer_length(scb)) { 561 ahc_update_neg_request(ahc, &devinfo, 562 tstate, targ_info, 563 AHC_NEG_IF_NON_ASYNC); 564 } 565 if (tstate->auto_negotiate & devinfo.target_mask) { 566 hscb->control |= MK_MESSAGE; 567 scb->flags &= ~SCB_NEGOTIATE; 568 scb->flags |= SCB_AUTO_NEGOTIATE; 569 } 570 hscb->cdb_len = sizeof(*sc); 571 hscb->dataptr = sg->addr; 572 hscb->datacnt = sg->len; 573 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID; 574 hscb->sgptr = aic_htole32(hscb->sgptr); 575 scb->sg_count = 1; 576 scb->flags |= SCB_SENSE; 577 ahc_qinfifo_requeue_tail(ahc, scb); 578 ahc_outb(ahc, RETURN_1, SEND_SENSE); 579 /* 580 * Ensure we have enough time to actually 581 * retrieve the sense. 582 */ 583 aic_scb_timer_reset(scb, 5 * 1000000); 584 break; 585 } 586 default: 587 break; 588 } 589 break; 590 } 591 case NO_MATCH: 592 { 593 /* Ensure we don't leave the selection hardware on */ 594 ahc_outb(ahc, SCSISEQ, 595 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 596 597 printf("%s:%c:%d: no active SCB for reconnecting " 598 "target - issuing BUS DEVICE RESET\n", 599 ahc_name(ahc), devinfo.channel, devinfo.target); 600 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 601 "ARG_1 == 0x%x ACCUM = 0x%x\n", 602 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 603 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 604 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 605 "SINDEX == 0x%x\n", 606 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 607 ahc_index_busy_tcl(ahc, 608 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 609 ahc_inb(ahc, SAVED_LUN))), 610 ahc_inb(ahc, SINDEX)); 611 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 612 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 613 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 614 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 615 ahc_inb(ahc, SCB_CONTROL)); 616 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 617 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 618 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0)); 619 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL)); 620 ahc_dump_card_state(ahc); 621 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 622 ahc->msgout_len = 1; 623 ahc->msgout_index = 0; 624 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 625 ahc_outb(ahc, MSG_OUT, HOST_MSG); 626 ahc_assert_atn(ahc); 627 break; 628 } 629 case SEND_REJECT: 630 { 631 u_int rejbyte = ahc_inb(ahc, ACCUM); 632 printf("%s:%c:%d: Warning - unknown message received from " 633 "target (0x%x). Rejecting\n", 634 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 635 break; 636 } 637 case PROTO_VIOLATION: 638 { 639 ahc_handle_proto_violation(ahc); 640 break; 641 } 642 case IGN_WIDE_RES: 643 ahc_handle_ign_wide_residue(ahc, &devinfo); 644 break; 645 case PDATA_REINIT: 646 ahc_reinitialize_dataptrs(ahc); 647 break; 648 case BAD_PHASE: 649 { 650 u_int lastphase; 651 652 lastphase = ahc_inb(ahc, LASTPHASE); 653 printf("%s:%c:%d: unknown scsi bus phase %x, " 654 "lastphase = 0x%x. Attempting to continue\n", 655 ahc_name(ahc), devinfo.channel, devinfo.target, 656 lastphase, ahc_inb(ahc, SCSISIGI)); 657 break; 658 } 659 case MISSED_BUSFREE: 660 { 661 u_int lastphase; 662 663 lastphase = ahc_inb(ahc, LASTPHASE); 664 printf("%s:%c:%d: Missed busfree. " 665 "Lastphase = 0x%x, Curphase = 0x%x\n", 666 ahc_name(ahc), devinfo.channel, devinfo.target, 667 lastphase, ahc_inb(ahc, SCSISIGI)); 668 ahc_restart(ahc); 669 return; 670 } 671 case HOST_MSG_LOOP: 672 { 673 /* 674 * The sequencer has encountered a message phase 675 * that requires host assistance for completion. 676 * While handling the message phase(s), we will be 677 * notified by the sequencer after each byte is 678 * transfered so we can track bus phase changes. 679 * 680 * If this is the first time we've seen a HOST_MSG_LOOP 681 * interrupt, initialize the state of the host message 682 * loop. 683 */ 684 if (ahc->msg_type == MSG_TYPE_NONE) { 685 struct scb *scb; 686 u_int scb_index; 687 u_int bus_phase; 688 689 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 690 if (bus_phase != P_MESGIN 691 && bus_phase != P_MESGOUT) { 692 printf("ahc_intr: HOST_MSG_LOOP bad " 693 "phase 0x%x\n", 694 bus_phase); 695 /* 696 * Probably transitioned to bus free before 697 * we got here. Just punt the message. 698 */ 699 ahc_clear_intstat(ahc); 700 ahc_restart(ahc); 701 return; 702 } 703 704 scb_index = ahc_inb(ahc, SCB_TAG); 705 scb = ahc_lookup_scb(ahc, scb_index); 706 if (devinfo.role == ROLE_INITIATOR) { 707 if (scb == NULL) 708 panic("HOST_MSG_LOOP with " 709 "invalid SCB %x\n", scb_index); 710 711 if (bus_phase == P_MESGOUT) 712 ahc_setup_initiator_msgout(ahc, 713 &devinfo, 714 scb); 715 else { 716 ahc->msg_type = 717 MSG_TYPE_INITIATOR_MSGIN; 718 ahc->msgin_index = 0; 719 } 720 } 721 #ifdef AHC_TARGET_MODE 722 else { 723 if (bus_phase == P_MESGOUT) { 724 ahc->msg_type = 725 MSG_TYPE_TARGET_MSGOUT; 726 ahc->msgin_index = 0; 727 } 728 else 729 ahc_setup_target_msgin(ahc, 730 &devinfo, 731 scb); 732 } 733 #endif 734 } 735 736 ahc_handle_message_phase(ahc); 737 break; 738 } 739 case PERR_DETECTED: 740 { 741 /* 742 * If we've cleared the parity error interrupt 743 * but the sequencer still believes that SCSIPERR 744 * is true, it must be that the parity error is 745 * for the currently presented byte on the bus, 746 * and we are not in a phase (data-in) where we will 747 * eventually ack this byte. Ack the byte and 748 * throw it away in the hope that the target will 749 * take us to message out to deliver the appropriate 750 * error message. 751 */ 752 if ((intstat & SCSIINT) == 0 753 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 754 755 if ((ahc->features & AHC_DT) == 0) { 756 u_int curphase; 757 758 /* 759 * The hardware will only let you ack bytes 760 * if the expected phase in SCSISIGO matches 761 * the current phase. Make sure this is 762 * currently the case. 763 */ 764 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 765 ahc_outb(ahc, LASTPHASE, curphase); 766 ahc_outb(ahc, SCSISIGO, curphase); 767 } 768 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) { 769 int wait; 770 771 /* 772 * In a data phase. Faster to bitbucket 773 * the data than to individually ack each 774 * byte. This is also the only strategy 775 * that will work with AUTOACK enabled. 776 */ 777 ahc_outb(ahc, SXFRCTL1, 778 ahc_inb(ahc, SXFRCTL1) | BITBUCKET); 779 wait = 5000; 780 while (--wait != 0) { 781 if ((ahc_inb(ahc, SCSISIGI) 782 & (CDI|MSGI)) != 0) 783 break; 784 aic_delay(100); 785 } 786 ahc_outb(ahc, SXFRCTL1, 787 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 788 if (wait == 0) { 789 struct scb *scb; 790 u_int scb_index; 791 792 ahc_print_devinfo(ahc, &devinfo); 793 printf("Unable to clear parity error. " 794 "Resetting bus.\n"); 795 scb_index = ahc_inb(ahc, SCB_TAG); 796 scb = ahc_lookup_scb(ahc, scb_index); 797 if (scb != NULL) 798 aic_set_transaction_status(scb, 799 CAM_UNCOR_PARITY); 800 ahc_reset_channel(ahc, devinfo.channel, 801 /*init reset*/TRUE); 802 } 803 } else { 804 ahc_inb(ahc, SCSIDATL); 805 } 806 } 807 break; 808 } 809 case DATA_OVERRUN: 810 { 811 /* 812 * When the sequencer detects an overrun, it 813 * places the controller in "BITBUCKET" mode 814 * and allows the target to complete its transfer. 815 * Unfortunately, none of the counters get updated 816 * when the controller is in this mode, so we have 817 * no way of knowing how large the overrun was. 818 */ 819 u_int scbindex = ahc_inb(ahc, SCB_TAG); 820 u_int lastphase = ahc_inb(ahc, LASTPHASE); 821 u_int i; 822 823 scb = ahc_lookup_scb(ahc, scbindex); 824 for (i = 0; i < num_phases; i++) { 825 if (lastphase == ahc_phase_table[i].phase) 826 break; 827 } 828 ahc_print_path(ahc, scb); 829 printf("data overrun detected %s." 830 " Tag == 0x%x.\n", 831 ahc_phase_table[i].phasemsg, 832 scb->hscb->tag); 833 ahc_print_path(ahc, scb); 834 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n", 835 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 836 aic_get_transfer_length(scb), scb->sg_count); 837 if (scb->sg_count > 0) { 838 for (i = 0; i < scb->sg_count; i++) { 839 840 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 841 i, 842 (aic_le32toh(scb->sg_list[i].len) >> 24 843 & SG_HIGH_ADDR_BITS), 844 aic_le32toh(scb->sg_list[i].addr), 845 aic_le32toh(scb->sg_list[i].len) 846 & AHC_SG_LEN_MASK); 847 } 848 } 849 /* 850 * Set this and it will take effect when the 851 * target does a command complete. 852 */ 853 ahc_freeze_devq(ahc, scb); 854 if ((scb->flags & SCB_SENSE) == 0) { 855 aic_set_transaction_status(scb, CAM_DATA_RUN_ERR); 856 } else { 857 scb->flags &= ~SCB_SENSE; 858 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 859 } 860 aic_freeze_scb(scb); 861 862 if ((ahc->features & AHC_ULTRA2) != 0) { 863 /* 864 * Clear the channel in case we return 865 * to data phase later. 866 */ 867 ahc_outb(ahc, SXFRCTL0, 868 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 869 ahc_outb(ahc, SXFRCTL0, 870 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 871 } 872 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 873 u_int dscommand1; 874 875 /* Ensure HHADDR is 0 for future DMA operations. */ 876 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 877 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 878 ahc_outb(ahc, HADDR, 0); 879 ahc_outb(ahc, DSCOMMAND1, dscommand1); 880 } 881 break; 882 } 883 case MKMSG_FAILED: 884 { 885 u_int scbindex; 886 887 printf("%s:%c:%d:%d: Attempt to issue message failed\n", 888 ahc_name(ahc), devinfo.channel, devinfo.target, 889 devinfo.lun); 890 scbindex = ahc_inb(ahc, SCB_TAG); 891 scb = ahc_lookup_scb(ahc, scbindex); 892 if (scb != NULL 893 && (scb->flags & SCB_RECOVERY_SCB) != 0) 894 /* 895 * Ensure that we didn't put a second instance of this 896 * SCB into the QINFIFO. 897 */ 898 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 899 SCB_GET_CHANNEL(ahc, scb), 900 SCB_GET_LUN(scb), scb->hscb->tag, 901 ROLE_INITIATOR, /*status*/0, 902 SEARCH_REMOVE); 903 break; 904 } 905 case NO_FREE_SCB: 906 { 907 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc)); 908 ahc_dump_card_state(ahc); 909 panic("for safety"); 910 break; 911 } 912 case SCB_MISMATCH: 913 { 914 u_int scbptr; 915 916 scbptr = ahc_inb(ahc, SCBPTR); 917 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n", 918 scbptr, ahc_inb(ahc, ARG_1), 919 ahc->scb_data->hscbs[scbptr].tag); 920 ahc_dump_card_state(ahc); 921 panic("for saftey"); 922 break; 923 } 924 case OUT_OF_RANGE: 925 { 926 printf("%s: BTT calculation out of range\n", ahc_name(ahc)); 927 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 928 "ARG_1 == 0x%x ACCUM = 0x%x\n", 929 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 930 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 931 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 932 "SINDEX == 0x%x\n, A == 0x%x\n", 933 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 934 ahc_index_busy_tcl(ahc, 935 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 936 ahc_inb(ahc, SAVED_LUN))), 937 ahc_inb(ahc, SINDEX), 938 ahc_inb(ahc, ACCUM)); 939 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 940 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 941 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 942 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 943 ahc_inb(ahc, SCB_CONTROL)); 944 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 945 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 946 ahc_dump_card_state(ahc); 947 panic("for safety"); 948 break; 949 } 950 default: 951 printf("ahc_intr: seqint, " 952 "intstat == 0x%x, scsisigi = 0x%x\n", 953 intstat, ahc_inb(ahc, SCSISIGI)); 954 break; 955 } 956 unpause: 957 /* 958 * The sequencer is paused immediately on 959 * a SEQINT, so we should restart it when 960 * we're done. 961 */ 962 ahc_unpause(ahc); 963 } 964 965 void 966 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 967 { 968 u_int scb_index; 969 u_int status0; 970 u_int status; 971 struct scb *scb; 972 char cur_channel; 973 char intr_channel; 974 975 if ((ahc->features & AHC_TWIN) != 0 976 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 977 cur_channel = 'B'; 978 else 979 cur_channel = 'A'; 980 intr_channel = cur_channel; 981 982 if ((ahc->features & AHC_ULTRA2) != 0) 983 status0 = ahc_inb(ahc, SSTAT0) & IOERR; 984 else 985 status0 = 0; 986 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 987 if (status == 0 && status0 == 0) { 988 if ((ahc->features & AHC_TWIN) != 0) { 989 /* Try the other channel */ 990 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 991 status = ahc_inb(ahc, SSTAT1) 992 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 993 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 994 } 995 if (status == 0) { 996 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 997 ahc_outb(ahc, CLRINT, CLRSCSIINT); 998 ahc_unpause(ahc); 999 return; 1000 } 1001 } 1002 1003 /* Make sure the sequencer is in a safe location. */ 1004 ahc_clear_critical_section(ahc); 1005 1006 scb_index = ahc_inb(ahc, SCB_TAG); 1007 scb = ahc_lookup_scb(ahc, scb_index); 1008 if (scb != NULL 1009 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1010 scb = NULL; 1011 1012 if ((ahc->features & AHC_ULTRA2) != 0 1013 && (status0 & IOERR) != 0) { 1014 int now_lvd; 1015 1016 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40; 1017 printf("%s: Transceiver State Has Changed to %s mode\n", 1018 ahc_name(ahc), now_lvd ? "LVD" : "SE"); 1019 ahc_outb(ahc, CLRSINT0, CLRIOERR); 1020 /* 1021 * When transitioning to SE mode, the reset line 1022 * glitches, triggering an arbitration bug in some 1023 * Ultra2 controllers. This bug is cleared when we 1024 * assert the reset line. Since a reset glitch has 1025 * already occurred with this transition and a 1026 * transceiver state change is handled just like 1027 * a bus reset anyway, asserting the reset line 1028 * ourselves is safe. 1029 */ 1030 ahc_reset_channel(ahc, intr_channel, 1031 /*Initiate Reset*/now_lvd == 0); 1032 } else if ((status & SCSIRSTI) != 0) { 1033 printf("%s: Someone reset channel %c\n", 1034 ahc_name(ahc), intr_channel); 1035 if (intr_channel != cur_channel) 1036 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 1037 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE); 1038 } else if ((status & SCSIPERR) != 0) { 1039 /* 1040 * Determine the bus phase and queue an appropriate message. 1041 * SCSIPERR is latched true as soon as a parity error 1042 * occurs. If the sequencer acked the transfer that 1043 * caused the parity error and the currently presented 1044 * transfer on the bus has correct parity, SCSIPERR will 1045 * be cleared by CLRSCSIPERR. Use this to determine if 1046 * we should look at the last phase the sequencer recorded, 1047 * or the current phase presented on the bus. 1048 */ 1049 struct ahc_devinfo devinfo; 1050 u_int mesg_out; 1051 u_int curphase; 1052 u_int errorphase; 1053 u_int lastphase; 1054 u_int scsirate; 1055 u_int i; 1056 u_int sstat2; 1057 int silent; 1058 1059 lastphase = ahc_inb(ahc, LASTPHASE); 1060 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1061 sstat2 = ahc_inb(ahc, SSTAT2); 1062 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 1063 /* 1064 * For all phases save DATA, the sequencer won't 1065 * automatically ack a byte that has a parity error 1066 * in it. So the only way that the current phase 1067 * could be 'data-in' is if the parity error is for 1068 * an already acked byte in the data phase. During 1069 * synchronous data-in transfers, we may actually 1070 * ack bytes before latching the current phase in 1071 * LASTPHASE, leading to the discrepancy between 1072 * curphase and lastphase. 1073 */ 1074 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 1075 || curphase == P_DATAIN || curphase == P_DATAIN_DT) 1076 errorphase = curphase; 1077 else 1078 errorphase = lastphase; 1079 1080 for (i = 0; i < num_phases; i++) { 1081 if (errorphase == ahc_phase_table[i].phase) 1082 break; 1083 } 1084 mesg_out = ahc_phase_table[i].mesg_out; 1085 silent = FALSE; 1086 if (scb != NULL) { 1087 if (SCB_IS_SILENT(scb)) 1088 silent = TRUE; 1089 else 1090 ahc_print_path(ahc, scb); 1091 scb->flags |= SCB_TRANSMISSION_ERROR; 1092 } else 1093 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel, 1094 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID))); 1095 scsirate = ahc_inb(ahc, SCSIRATE); 1096 if (silent == FALSE) { 1097 printf("parity error detected %s. " 1098 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 1099 ahc_phase_table[i].phasemsg, 1100 ahc_inw(ahc, SEQADDR0), 1101 scsirate); 1102 if ((ahc->features & AHC_DT) != 0) { 1103 if ((sstat2 & CRCVALERR) != 0) 1104 printf("\tCRC Value Mismatch\n"); 1105 if ((sstat2 & CRCENDERR) != 0) 1106 printf("\tNo terminal CRC packet " 1107 "recevied\n"); 1108 if ((sstat2 & CRCREQERR) != 0) 1109 printf("\tIllegal CRC packet " 1110 "request\n"); 1111 if ((sstat2 & DUAL_EDGE_ERR) != 0) 1112 printf("\tUnexpected %sDT Data Phase\n", 1113 (scsirate & SINGLE_EDGE) 1114 ? "" : "non-"); 1115 } 1116 } 1117 1118 if ((ahc->features & AHC_DT) != 0 1119 && (sstat2 & DUAL_EDGE_ERR) != 0) { 1120 /* 1121 * This error applies regardless of 1122 * data direction, so ignore the value 1123 * in the phase table. 1124 */ 1125 mesg_out = MSG_INITIATOR_DET_ERR; 1126 } 1127 1128 /* 1129 * We've set the hardware to assert ATN if we 1130 * get a parity error on "in" phases, so all we 1131 * need to do is stuff the message buffer with 1132 * the appropriate message. "In" phases have set 1133 * mesg_out to something other than MSG_NOP. 1134 */ 1135 if (mesg_out != MSG_NOOP) { 1136 if (ahc->msg_type != MSG_TYPE_NONE) 1137 ahc->send_msg_perror = TRUE; 1138 else 1139 ahc_outb(ahc, MSG_OUT, mesg_out); 1140 } 1141 /* 1142 * Force a renegotiation with this target just in 1143 * case we are out of sync for some external reason 1144 * unknown (or unreported) by the target. 1145 */ 1146 ahc_fetch_devinfo(ahc, &devinfo); 1147 ahc_force_renegotiation(ahc, &devinfo); 1148 1149 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1150 ahc_unpause(ahc); 1151 } else if ((status & SELTO) != 0) { 1152 u_int scbptr; 1153 1154 /* Stop the selection */ 1155 ahc_outb(ahc, SCSISEQ, 0); 1156 1157 /* No more pending messages */ 1158 ahc_clear_msg_state(ahc); 1159 1160 /* Clear interrupt state */ 1161 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1162 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1163 1164 /* 1165 * Although the driver does not care about the 1166 * 'Selection in Progress' status bit, the busy 1167 * LED does. SELINGO is only cleared by a sucessfull 1168 * selection, so we must manually clear it to insure 1169 * the LED turns off just incase no future successful 1170 * selections occur (e.g. no devices on the bus). 1171 */ 1172 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 1173 1174 scbptr = ahc_inb(ahc, WAITING_SCBH); 1175 ahc_outb(ahc, SCBPTR, scbptr); 1176 scb_index = ahc_inb(ahc, SCB_TAG); 1177 1178 scb = ahc_lookup_scb(ahc, scb_index); 1179 if (scb == NULL) { 1180 printf("%s: ahc_intr - referenced scb not " 1181 "valid during SELTO scb(%d, %d)\n", 1182 ahc_name(ahc), scbptr, scb_index); 1183 ahc_dump_card_state(ahc); 1184 } else { 1185 struct ahc_devinfo devinfo; 1186 #ifdef AHC_DEBUG 1187 if ((ahc_debug & AHC_SHOW_SELTO) != 0) { 1188 ahc_print_path(ahc, scb); 1189 printf("Saw Selection Timeout for SCB 0x%x\n", 1190 scb_index); 1191 } 1192 #endif 1193 ahc_scb_devinfo(ahc, &devinfo, scb); 1194 aic_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1195 ahc_freeze_devq(ahc, scb); 1196 1197 /* 1198 * Cancel any pending transactions on the device 1199 * now that it seems to be missing. This will 1200 * also revert us to async/narrow transfers until 1201 * we can renegotiate with the device. 1202 */ 1203 ahc_handle_devreset(ahc, &devinfo, 1204 CAM_SEL_TIMEOUT, 1205 "Selection Timeout", 1206 /*verbose_level*/1); 1207 } 1208 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1209 ahc_restart(ahc); 1210 } else if ((status & BUSFREE) != 0 1211 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 1212 struct ahc_devinfo devinfo; 1213 u_int lastphase; 1214 u_int saved_scsiid; 1215 u_int saved_lun; 1216 u_int target; 1217 u_int initiator_role_id; 1218 char channel; 1219 int printerror; 1220 1221 /* 1222 * Clear our selection hardware as soon as possible. 1223 * We may have an entry in the waiting Q for this target, 1224 * that is affected by this busfree and we don't want to 1225 * go about selecting the target while we handle the event. 1226 */ 1227 ahc_outb(ahc, SCSISEQ, 1228 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1229 1230 /* 1231 * Disable busfree interrupts and clear the busfree 1232 * interrupt status. We do this here so that several 1233 * bus transactions occur prior to clearing the SCSIINT 1234 * latch. It can take a bit for the clearing to take effect. 1235 */ 1236 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1237 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 1238 1239 /* 1240 * Look at what phase we were last in. 1241 * If its message out, chances are pretty good 1242 * that the busfree was in response to one of 1243 * our abort requests. 1244 */ 1245 lastphase = ahc_inb(ahc, LASTPHASE); 1246 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 1247 saved_lun = ahc_inb(ahc, SAVED_LUN); 1248 target = SCSIID_TARGET(ahc, saved_scsiid); 1249 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 1250 channel = SCSIID_CHANNEL(ahc, saved_scsiid); 1251 ahc_compile_devinfo(&devinfo, initiator_role_id, 1252 target, saved_lun, channel, ROLE_INITIATOR); 1253 printerror = 1; 1254 1255 if (lastphase == P_MESGOUT) { 1256 u_int tag; 1257 1258 tag = SCB_LIST_NULL; 1259 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE) 1260 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) { 1261 if (ahc->msgout_buf[ahc->msgout_index - 1] 1262 == MSG_ABORT_TAG) 1263 tag = scb->hscb->tag; 1264 ahc_print_path(ahc, scb); 1265 printf("SCB %d - Abort%s Completed.\n", 1266 scb->hscb->tag, tag == SCB_LIST_NULL ? 1267 "" : " Tag"); 1268 ahc_abort_scbs(ahc, target, channel, 1269 saved_lun, tag, 1270 ROLE_INITIATOR, 1271 CAM_REQ_ABORTED); 1272 printerror = 0; 1273 } else if (ahc_sent_msg(ahc, AHCMSG_1B, 1274 MSG_BUS_DEV_RESET, TRUE)) { 1275 #ifdef __FreeBSD__ 1276 /* 1277 * Don't mark the user's request for this BDR 1278 * as completing with CAM_BDR_SENT. CAM3 1279 * specifies CAM_REQ_CMP. 1280 */ 1281 if (scb != NULL 1282 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 1283 && ahc_match_scb(ahc, scb, target, channel, 1284 CAM_LUN_WILDCARD, 1285 SCB_LIST_NULL, 1286 ROLE_INITIATOR)) { 1287 aic_set_transaction_status(scb, CAM_REQ_CMP); 1288 } 1289 #endif 1290 ahc_compile_devinfo(&devinfo, 1291 initiator_role_id, 1292 target, 1293 CAM_LUN_WILDCARD, 1294 channel, 1295 ROLE_INITIATOR); 1296 ahc_handle_devreset(ahc, &devinfo, 1297 CAM_BDR_SENT, 1298 "Bus Device Reset", 1299 /*verbose_level*/0); 1300 printerror = 0; 1301 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1302 MSG_EXT_PPR, FALSE)) { 1303 struct ahc_initiator_tinfo *tinfo; 1304 struct ahc_tmode_tstate *tstate; 1305 1306 /* 1307 * PPR Rejected. Try non-ppr negotiation 1308 * and retry command. 1309 */ 1310 tinfo = ahc_fetch_transinfo(ahc, 1311 devinfo.channel, 1312 devinfo.our_scsiid, 1313 devinfo.target, 1314 &tstate); 1315 tinfo->curr.transport_version = 2; 1316 tinfo->goal.transport_version = 2; 1317 tinfo->goal.ppr_options = 0; 1318 ahc_qinfifo_requeue_tail(ahc, scb); 1319 printerror = 0; 1320 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1321 MSG_EXT_WDTR, FALSE)) { 1322 /* 1323 * Negotiation Rejected. Go-narrow and 1324 * retry command. 1325 */ 1326 ahc_set_width(ahc, &devinfo, 1327 MSG_EXT_WDTR_BUS_8_BIT, 1328 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1329 /*paused*/TRUE); 1330 ahc_qinfifo_requeue_tail(ahc, scb); 1331 printerror = 0; 1332 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1333 MSG_EXT_SDTR, FALSE)) { 1334 /* 1335 * Negotiation Rejected. Go-async and 1336 * retry command. 1337 */ 1338 ahc_set_syncrate(ahc, &devinfo, 1339 /*syncrate*/NULL, 1340 /*period*/0, /*offset*/0, 1341 /*ppr_options*/0, 1342 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1343 /*paused*/TRUE); 1344 ahc_qinfifo_requeue_tail(ahc, scb); 1345 printerror = 0; 1346 } 1347 } 1348 if (printerror != 0) { 1349 u_int i; 1350 1351 if (scb != NULL) { 1352 u_int tag; 1353 1354 if ((scb->hscb->control & TAG_ENB) != 0) 1355 tag = scb->hscb->tag; 1356 else 1357 tag = SCB_LIST_NULL; 1358 ahc_print_path(ahc, scb); 1359 ahc_abort_scbs(ahc, target, channel, 1360 SCB_GET_LUN(scb), tag, 1361 ROLE_INITIATOR, 1362 CAM_UNEXP_BUSFREE); 1363 } else { 1364 /* 1365 * We had not fully identified this connection, 1366 * so we cannot abort anything. 1367 */ 1368 printf("%s: ", ahc_name(ahc)); 1369 } 1370 for (i = 0; i < num_phases; i++) { 1371 if (lastphase == ahc_phase_table[i].phase) 1372 break; 1373 } 1374 if (lastphase != P_BUSFREE) { 1375 /* 1376 * Renegotiate with this device at the 1377 * next oportunity just in case this busfree 1378 * is due to a negotiation mismatch with the 1379 * device. 1380 */ 1381 ahc_force_renegotiation(ahc, &devinfo); 1382 } 1383 printf("Unexpected busfree %s\n" 1384 "SEQADDR == 0x%x\n", 1385 ahc_phase_table[i].phasemsg, 1386 ahc_inb(ahc, SEQADDR0) 1387 | (ahc_inb(ahc, SEQADDR1) << 8)); 1388 } 1389 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1390 ahc_restart(ahc); 1391 } else { 1392 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n", 1393 ahc_name(ahc), status); 1394 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1395 } 1396 } 1397 1398 /* 1399 * Force renegotiation to occur the next time we initiate 1400 * a command to the current device. 1401 */ 1402 static void 1403 ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1404 { 1405 struct ahc_initiator_tinfo *targ_info; 1406 struct ahc_tmode_tstate *tstate; 1407 1408 targ_info = ahc_fetch_transinfo(ahc, 1409 devinfo->channel, 1410 devinfo->our_scsiid, 1411 devinfo->target, 1412 &tstate); 1413 ahc_update_neg_request(ahc, devinfo, tstate, 1414 targ_info, AHC_NEG_IF_NON_ASYNC); 1415 } 1416 1417 #define AHC_MAX_STEPS 2000 1418 void 1419 ahc_clear_critical_section(struct ahc_softc *ahc) 1420 { 1421 int stepping; 1422 int steps; 1423 u_int simode0; 1424 u_int simode1; 1425 1426 if (ahc->num_critical_sections == 0) 1427 return; 1428 1429 stepping = FALSE; 1430 steps = 0; 1431 simode0 = 0; 1432 simode1 = 0; 1433 for (;;) { 1434 struct cs *cs; 1435 u_int seqaddr; 1436 u_int i; 1437 1438 seqaddr = ahc_inb(ahc, SEQADDR0) 1439 | (ahc_inb(ahc, SEQADDR1) << 8); 1440 1441 /* 1442 * Seqaddr represents the next instruction to execute, 1443 * so we are really executing the instruction just 1444 * before it. 1445 */ 1446 if (seqaddr != 0) 1447 seqaddr -= 1; 1448 cs = ahc->critical_sections; 1449 for (i = 0; i < ahc->num_critical_sections; i++, cs++) { 1450 1451 if (cs->begin < seqaddr && cs->end >= seqaddr) 1452 break; 1453 } 1454 1455 if (i == ahc->num_critical_sections) 1456 break; 1457 1458 if (steps > AHC_MAX_STEPS) { 1459 printf("%s: Infinite loop in critical section\n", 1460 ahc_name(ahc)); 1461 ahc_dump_card_state(ahc); 1462 panic("critical section loop"); 1463 } 1464 1465 steps++; 1466 if (stepping == FALSE) { 1467 1468 /* 1469 * Disable all interrupt sources so that the 1470 * sequencer will not be stuck by a pausing 1471 * interrupt condition while we attempt to 1472 * leave a critical section. 1473 */ 1474 simode0 = ahc_inb(ahc, SIMODE0); 1475 ahc_outb(ahc, SIMODE0, 0); 1476 simode1 = ahc_inb(ahc, SIMODE1); 1477 if ((ahc->features & AHC_DT) != 0) 1478 /* 1479 * On DT class controllers, we 1480 * use the enhanced busfree logic. 1481 * Unfortunately we cannot re-enable 1482 * busfree detection within the 1483 * current connection, so we must 1484 * leave it on while single stepping. 1485 */ 1486 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE); 1487 else 1488 ahc_outb(ahc, SIMODE1, 0); 1489 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1490 ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP); 1491 stepping = TRUE; 1492 } 1493 if ((ahc->features & AHC_DT) != 0) { 1494 ahc_outb(ahc, CLRSINT1, CLRBUSFREE); 1495 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1496 } 1497 ahc_outb(ahc, HCNTRL, ahc->unpause); 1498 while (!ahc_is_paused(ahc)) 1499 aic_delay(200); 1500 } 1501 if (stepping) { 1502 ahc_outb(ahc, SIMODE0, simode0); 1503 ahc_outb(ahc, SIMODE1, simode1); 1504 ahc_outb(ahc, SEQCTL, ahc->seqctl); 1505 } 1506 } 1507 1508 /* 1509 * Clear any pending interrupt status. 1510 */ 1511 void 1512 ahc_clear_intstat(struct ahc_softc *ahc) 1513 { 1514 /* Clear any interrupt conditions this may have caused */ 1515 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 1516 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 1517 CLRREQINIT); 1518 ahc_flush_device_writes(ahc); 1519 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 1520 ahc_flush_device_writes(ahc); 1521 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1522 ahc_flush_device_writes(ahc); 1523 } 1524 1525 /**************************** Debugging Routines ******************************/ 1526 #ifdef AHC_DEBUG 1527 uint32_t ahc_debug = AHC_DEBUG_OPTS; 1528 #endif 1529 1530 void 1531 ahc_print_scb(struct scb *scb) 1532 { 1533 int i; 1534 1535 struct hardware_scb *hscb = scb->hscb; 1536 1537 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 1538 (void *)scb, 1539 hscb->control, 1540 hscb->scsiid, 1541 hscb->lun, 1542 hscb->cdb_len); 1543 printf("Shared Data: "); 1544 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++) 1545 printf("%#02x", hscb->shared_data.cdb[i]); 1546 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n", 1547 aic_le32toh(hscb->dataptr), 1548 aic_le32toh(hscb->datacnt), 1549 aic_le32toh(hscb->sgptr), 1550 hscb->tag); 1551 if (scb->sg_count > 0) { 1552 for (i = 0; i < scb->sg_count; i++) { 1553 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 1554 i, 1555 (aic_le32toh(scb->sg_list[i].len) >> 24 1556 & SG_HIGH_ADDR_BITS), 1557 aic_le32toh(scb->sg_list[i].addr), 1558 aic_le32toh(scb->sg_list[i].len)); 1559 } 1560 } 1561 } 1562 1563 /************************* Transfer Negotiation *******************************/ 1564 /* 1565 * Allocate per target mode instance (ID we respond to as a target) 1566 * transfer negotiation data structures. 1567 */ 1568 static struct ahc_tmode_tstate * 1569 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1570 { 1571 struct ahc_tmode_tstate *master_tstate; 1572 struct ahc_tmode_tstate *tstate; 1573 int i; 1574 1575 master_tstate = ahc->enabled_targets[ahc->our_id]; 1576 if (channel == 'B') { 1577 scsi_id += 8; 1578 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1579 } 1580 if (ahc->enabled_targets[scsi_id] != NULL 1581 && ahc->enabled_targets[scsi_id] != master_tstate) 1582 panic("%s: ahc_alloc_tstate - Target already allocated", 1583 ahc_name(ahc)); 1584 tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate), 1585 M_DEVBUF, M_NOWAIT); 1586 if (tstate == NULL) 1587 return (NULL); 1588 1589 /* 1590 * If we have allocated a master tstate, copy user settings from 1591 * the master tstate (taken from SRAM or the EEPROM) for this 1592 * channel, but reset our current and goal settings to async/narrow 1593 * until an initiator talks to us. 1594 */ 1595 if (master_tstate != NULL) { 1596 memcpy(tstate, master_tstate, sizeof(*tstate)); 1597 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 1598 tstate->ultraenb = 0; 1599 for (i = 0; i < AHC_NUM_TARGETS; i++) { 1600 memset(&tstate->transinfo[i].curr, 0, 1601 sizeof(tstate->transinfo[i].curr)); 1602 memset(&tstate->transinfo[i].goal, 0, 1603 sizeof(tstate->transinfo[i].goal)); 1604 } 1605 } else 1606 memset(tstate, 0, sizeof(*tstate)); 1607 ahc->enabled_targets[scsi_id] = tstate; 1608 return (tstate); 1609 } 1610 1611 #ifdef AHC_TARGET_MODE 1612 /* 1613 * Free per target mode instance (ID we respond to as a target) 1614 * transfer negotiation data structures. 1615 */ 1616 static void 1617 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1618 { 1619 struct ahc_tmode_tstate *tstate; 1620 1621 /* 1622 * Don't clean up our "master" tstate. 1623 * It has our default user settings. 1624 */ 1625 if (((channel == 'B' && scsi_id == ahc->our_id_b) 1626 || (channel == 'A' && scsi_id == ahc->our_id)) 1627 && force == FALSE) 1628 return; 1629 1630 if (channel == 'B') 1631 scsi_id += 8; 1632 tstate = ahc->enabled_targets[scsi_id]; 1633 if (tstate != NULL) 1634 free(tstate, M_DEVBUF); 1635 ahc->enabled_targets[scsi_id] = NULL; 1636 } 1637 #endif 1638 1639 /* 1640 * Called when we have an active connection to a target on the bus, 1641 * this function finds the nearest syncrate to the input period limited 1642 * by the capabilities of the bus connectivity of and sync settings for 1643 * the target. 1644 */ 1645 struct ahc_syncrate * 1646 ahc_devlimited_syncrate(struct ahc_softc *ahc, 1647 struct ahc_initiator_tinfo *tinfo, 1648 u_int *period, u_int *ppr_options, role_t role) 1649 { 1650 struct ahc_transinfo *transinfo; 1651 u_int maxsync; 1652 1653 if ((ahc->features & AHC_ULTRA2) != 0) { 1654 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1655 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1656 maxsync = AHC_SYNCRATE_DT; 1657 } else { 1658 maxsync = AHC_SYNCRATE_ULTRA; 1659 /* Can't do DT on an SE bus */ 1660 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1661 } 1662 } else if ((ahc->features & AHC_ULTRA) != 0) { 1663 maxsync = AHC_SYNCRATE_ULTRA; 1664 } else { 1665 maxsync = AHC_SYNCRATE_FAST; 1666 } 1667 /* 1668 * Never allow a value higher than our current goal 1669 * period otherwise we may allow a target initiated 1670 * negotiation to go above the limit as set by the 1671 * user. In the case of an initiator initiated 1672 * sync negotiation, we limit based on the user 1673 * setting. This allows the system to still accept 1674 * incoming negotiations even if target initiated 1675 * negotiation is not performed. 1676 */ 1677 if (role == ROLE_TARGET) 1678 transinfo = &tinfo->user; 1679 else 1680 transinfo = &tinfo->goal; 1681 *ppr_options &= transinfo->ppr_options; 1682 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 1683 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2); 1684 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1685 } 1686 if (transinfo->period == 0) { 1687 *period = 0; 1688 *ppr_options = 0; 1689 return (NULL); 1690 } 1691 *period = MAX(*period, transinfo->period); 1692 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync)); 1693 } 1694 1695 /* 1696 * Look up the valid period to SCSIRATE conversion in our table. 1697 * Return the period and offset that should be sent to the target 1698 * if this was the beginning of an SDTR. 1699 */ 1700 struct ahc_syncrate * 1701 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1702 u_int *ppr_options, u_int maxsync) 1703 { 1704 struct ahc_syncrate *syncrate; 1705 1706 if ((ahc->features & AHC_DT) == 0) 1707 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1708 1709 /* Skip all DT only entries if DT is not available */ 1710 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 1711 && maxsync < AHC_SYNCRATE_ULTRA2) 1712 maxsync = AHC_SYNCRATE_ULTRA2; 1713 1714 for (syncrate = &ahc_syncrates[maxsync]; 1715 syncrate->rate != NULL; 1716 syncrate++) { 1717 1718 /* 1719 * The Ultra2 table doesn't go as low 1720 * as for the Fast/Ultra cards. 1721 */ 1722 if ((ahc->features & AHC_ULTRA2) != 0 1723 && (syncrate->sxfr_u2 == 0)) 1724 break; 1725 1726 if (*period <= syncrate->period) { 1727 /* 1728 * When responding to a target that requests 1729 * sync, the requested rate may fall between 1730 * two rates that we can output, but still be 1731 * a rate that we can receive. Because of this, 1732 * we want to respond to the target with 1733 * the same rate that it sent to us even 1734 * if the period we use to send data to it 1735 * is lower. Only lower the response period 1736 * if we must. 1737 */ 1738 if (syncrate == &ahc_syncrates[maxsync]) 1739 *period = syncrate->period; 1740 1741 /* 1742 * At some speeds, we only support 1743 * ST transfers. 1744 */ 1745 if ((syncrate->sxfr_u2 & ST_SXFR) != 0) 1746 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1747 break; 1748 } 1749 } 1750 1751 if ((*period == 0) 1752 || (syncrate->rate == NULL) 1753 || ((ahc->features & AHC_ULTRA2) != 0 1754 && (syncrate->sxfr_u2 == 0))) { 1755 /* Use asynchronous transfers. */ 1756 *period = 0; 1757 syncrate = NULL; 1758 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1759 } 1760 return (syncrate); 1761 } 1762 1763 /* 1764 * Convert from an entry in our syncrate table to the SCSI equivalent 1765 * sync "period" factor. 1766 */ 1767 u_int 1768 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1769 { 1770 struct ahc_syncrate *syncrate; 1771 1772 if ((ahc->features & AHC_ULTRA2) != 0) 1773 scsirate &= SXFR_ULTRA2; 1774 else 1775 scsirate &= SXFR; 1776 1777 syncrate = &ahc_syncrates[maxsync]; 1778 while (syncrate->rate != NULL) { 1779 1780 if ((ahc->features & AHC_ULTRA2) != 0) { 1781 if (syncrate->sxfr_u2 == 0) 1782 break; 1783 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1784 return (syncrate->period); 1785 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1786 return (syncrate->period); 1787 } 1788 syncrate++; 1789 } 1790 return (0); /* async */ 1791 } 1792 1793 /* 1794 * Truncate the given synchronous offset to a value the 1795 * current adapter type and syncrate are capable of. 1796 */ 1797 void 1798 ahc_validate_offset(struct ahc_softc *ahc, 1799 struct ahc_initiator_tinfo *tinfo, 1800 struct ahc_syncrate *syncrate, 1801 u_int *offset, int wide, role_t role) 1802 { 1803 u_int maxoffset; 1804 1805 /* Limit offset to what we can do */ 1806 if (syncrate == NULL) { 1807 maxoffset = 0; 1808 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1809 maxoffset = MAX_OFFSET_ULTRA2; 1810 } else { 1811 if (wide) 1812 maxoffset = MAX_OFFSET_16BIT; 1813 else 1814 maxoffset = MAX_OFFSET_8BIT; 1815 } 1816 *offset = MIN(*offset, maxoffset); 1817 if (tinfo != NULL) { 1818 if (role == ROLE_TARGET) 1819 *offset = MIN(*offset, tinfo->user.offset); 1820 else 1821 *offset = MIN(*offset, tinfo->goal.offset); 1822 } 1823 } 1824 1825 /* 1826 * Truncate the given transfer width parameter to a value the 1827 * current adapter type is capable of. 1828 */ 1829 void 1830 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo, 1831 u_int *bus_width, role_t role) 1832 { 1833 switch (*bus_width) { 1834 default: 1835 if (ahc->features & AHC_WIDE) { 1836 /* Respond Wide */ 1837 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 1838 break; 1839 } 1840 /* FALLTHROUGH */ 1841 case MSG_EXT_WDTR_BUS_8_BIT: 1842 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 1843 break; 1844 } 1845 if (tinfo != NULL) { 1846 if (role == ROLE_TARGET) 1847 *bus_width = MIN(tinfo->user.width, *bus_width); 1848 else 1849 *bus_width = MIN(tinfo->goal.width, *bus_width); 1850 } 1851 } 1852 1853 /* 1854 * Update the bitmask of targets for which the controller should 1855 * negotiate with at the next convenient oportunity. This currently 1856 * means the next time we send the initial identify messages for 1857 * a new transaction. 1858 */ 1859 int 1860 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1861 struct ahc_tmode_tstate *tstate, 1862 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type) 1863 { 1864 u_int auto_negotiate_orig; 1865 1866 auto_negotiate_orig = tstate->auto_negotiate; 1867 if (neg_type == AHC_NEG_ALWAYS) { 1868 /* 1869 * Force our "current" settings to be 1870 * unknown so that unless a bus reset 1871 * occurs the need to renegotiate is 1872 * recorded persistently. 1873 */ 1874 if ((ahc->features & AHC_WIDE) != 0) 1875 tinfo->curr.width = AHC_WIDTH_UNKNOWN; 1876 tinfo->curr.period = AHC_PERIOD_UNKNOWN; 1877 tinfo->curr.offset = AHC_OFFSET_UNKNOWN; 1878 } 1879 if (tinfo->curr.period != tinfo->goal.period 1880 || tinfo->curr.width != tinfo->goal.width 1881 || tinfo->curr.offset != tinfo->goal.offset 1882 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 1883 || (neg_type == AHC_NEG_IF_NON_ASYNC 1884 && (tinfo->goal.offset != 0 1885 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 1886 || tinfo->goal.ppr_options != 0))) 1887 tstate->auto_negotiate |= devinfo->target_mask; 1888 else 1889 tstate->auto_negotiate &= ~devinfo->target_mask; 1890 1891 return (auto_negotiate_orig != tstate->auto_negotiate); 1892 } 1893 1894 /* 1895 * Update the user/goal/curr tables of synchronous negotiation 1896 * parameters as well as, in the case of a current or active update, 1897 * any data structures on the host controller. In the case of an 1898 * active update, the specified target is currently talking to us on 1899 * the bus, so the transfer parameter update must take effect 1900 * immediately. 1901 */ 1902 void 1903 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1904 struct ahc_syncrate *syncrate, u_int period, 1905 u_int offset, u_int ppr_options, u_int type, int paused) 1906 { 1907 struct ahc_initiator_tinfo *tinfo; 1908 struct ahc_tmode_tstate *tstate; 1909 u_int old_period; 1910 u_int old_offset; 1911 u_int old_ppr; 1912 int active; 1913 int update_needed; 1914 1915 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1916 update_needed = 0; 1917 1918 if (syncrate == NULL) { 1919 period = 0; 1920 offset = 0; 1921 } 1922 1923 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1924 devinfo->target, &tstate); 1925 1926 if ((type & AHC_TRANS_USER) != 0) { 1927 tinfo->user.period = period; 1928 tinfo->user.offset = offset; 1929 tinfo->user.ppr_options = ppr_options; 1930 } 1931 1932 if ((type & AHC_TRANS_GOAL) != 0) { 1933 tinfo->goal.period = period; 1934 tinfo->goal.offset = offset; 1935 tinfo->goal.ppr_options = ppr_options; 1936 } 1937 1938 old_period = tinfo->curr.period; 1939 old_offset = tinfo->curr.offset; 1940 old_ppr = tinfo->curr.ppr_options; 1941 1942 if ((type & AHC_TRANS_CUR) != 0 1943 && (old_period != period 1944 || old_offset != offset 1945 || old_ppr != ppr_options)) { 1946 u_int scsirate; 1947 1948 update_needed++; 1949 scsirate = tinfo->scsirate; 1950 if ((ahc->features & AHC_ULTRA2) != 0) { 1951 1952 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1953 if (syncrate != NULL) { 1954 scsirate |= syncrate->sxfr_u2; 1955 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) 1956 scsirate |= ENABLE_CRC; 1957 else 1958 scsirate |= SINGLE_EDGE; 1959 } 1960 } else { 1961 1962 scsirate &= ~(SXFR|SOFS); 1963 /* 1964 * Ensure Ultra mode is set properly for 1965 * this target. 1966 */ 1967 tstate->ultraenb &= ~devinfo->target_mask; 1968 if (syncrate != NULL) { 1969 if (syncrate->sxfr & ULTRA_SXFR) { 1970 tstate->ultraenb |= 1971 devinfo->target_mask; 1972 } 1973 scsirate |= syncrate->sxfr & SXFR; 1974 scsirate |= offset & SOFS; 1975 } 1976 if (active) { 1977 u_int sxfrctl0; 1978 1979 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1980 sxfrctl0 &= ~FAST20; 1981 if (tstate->ultraenb & devinfo->target_mask) 1982 sxfrctl0 |= FAST20; 1983 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1984 } 1985 } 1986 if (active) { 1987 ahc_outb(ahc, SCSIRATE, scsirate); 1988 if ((ahc->features & AHC_ULTRA2) != 0) 1989 ahc_outb(ahc, SCSIOFFSET, offset); 1990 } 1991 1992 tinfo->scsirate = scsirate; 1993 tinfo->curr.period = period; 1994 tinfo->curr.offset = offset; 1995 tinfo->curr.ppr_options = ppr_options; 1996 1997 ahc_send_async(ahc, devinfo->channel, devinfo->target, 1998 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 1999 if (bootverbose) { 2000 if (offset != 0) { 2001 printf("%s: target %d synchronous at %sMHz%s, " 2002 "offset = 0x%x\n", ahc_name(ahc), 2003 devinfo->target, syncrate->rate, 2004 (ppr_options & MSG_EXT_PPR_DT_REQ) 2005 ? " DT" : "", offset); 2006 } else { 2007 printf("%s: target %d using " 2008 "asynchronous transfers\n", 2009 ahc_name(ahc), devinfo->target); 2010 } 2011 } 2012 } 2013 2014 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2015 tinfo, AHC_NEG_TO_GOAL); 2016 2017 if (update_needed) 2018 ahc_update_pending_scbs(ahc); 2019 } 2020 2021 /* 2022 * Update the user/goal/curr tables of wide negotiation 2023 * parameters as well as, in the case of a current or active update, 2024 * any data structures on the host controller. In the case of an 2025 * active update, the specified target is currently talking to us on 2026 * the bus, so the transfer parameter update must take effect 2027 * immediately. 2028 */ 2029 void 2030 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2031 u_int width, u_int type, int paused) 2032 { 2033 struct ahc_initiator_tinfo *tinfo; 2034 struct ahc_tmode_tstate *tstate; 2035 u_int oldwidth; 2036 int active; 2037 int update_needed; 2038 2039 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 2040 update_needed = 0; 2041 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2042 devinfo->target, &tstate); 2043 2044 if ((type & AHC_TRANS_USER) != 0) 2045 tinfo->user.width = width; 2046 2047 if ((type & AHC_TRANS_GOAL) != 0) 2048 tinfo->goal.width = width; 2049 2050 oldwidth = tinfo->curr.width; 2051 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 2052 u_int scsirate; 2053 2054 update_needed++; 2055 scsirate = tinfo->scsirate; 2056 scsirate &= ~WIDEXFER; 2057 if (width == MSG_EXT_WDTR_BUS_16_BIT) 2058 scsirate |= WIDEXFER; 2059 2060 tinfo->scsirate = scsirate; 2061 2062 if (active) 2063 ahc_outb(ahc, SCSIRATE, scsirate); 2064 2065 tinfo->curr.width = width; 2066 2067 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2068 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2069 if (bootverbose) { 2070 printf("%s: target %d using %dbit transfers\n", 2071 ahc_name(ahc), devinfo->target, 2072 8 * (0x01 << width)); 2073 } 2074 } 2075 2076 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2077 tinfo, AHC_NEG_TO_GOAL); 2078 if (update_needed) 2079 ahc_update_pending_scbs(ahc); 2080 } 2081 2082 /* 2083 * Update the current state of tagged queuing for a given target. 2084 */ 2085 void 2086 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2087 ahc_queue_alg alg) 2088 { 2089 ahc_platform_set_tags(ahc, devinfo, alg); 2090 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2091 devinfo->lun, AC_TRANSFER_NEG, &alg); 2092 } 2093 2094 /* 2095 * When the transfer settings for a connection change, update any 2096 * in-transit SCBs to contain the new data so the hardware will 2097 * be set correctly during future (re)selections. 2098 */ 2099 static void 2100 ahc_update_pending_scbs(struct ahc_softc *ahc) 2101 { 2102 struct scb *pending_scb; 2103 int pending_scb_count; 2104 int i; 2105 int paused; 2106 u_int saved_scbptr; 2107 2108 /* 2109 * Traverse the pending SCB list and ensure that all of the 2110 * SCBs there have the proper settings. 2111 */ 2112 pending_scb_count = 0; 2113 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) { 2114 struct ahc_devinfo devinfo; 2115 struct hardware_scb *pending_hscb; 2116 struct ahc_initiator_tinfo *tinfo; 2117 struct ahc_tmode_tstate *tstate; 2118 2119 ahc_scb_devinfo(ahc, &devinfo, pending_scb); 2120 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 2121 devinfo.our_scsiid, 2122 devinfo.target, &tstate); 2123 pending_hscb = pending_scb->hscb; 2124 pending_hscb->control &= ~ULTRAENB; 2125 if ((tstate->ultraenb & devinfo.target_mask) != 0) 2126 pending_hscb->control |= ULTRAENB; 2127 pending_hscb->scsirate = tinfo->scsirate; 2128 pending_hscb->scsioffset = tinfo->curr.offset; 2129 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 2130 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 2131 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 2132 pending_hscb->control &= ~MK_MESSAGE; 2133 } 2134 ahc_sync_scb(ahc, pending_scb, 2135 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2136 pending_scb_count++; 2137 } 2138 2139 if (pending_scb_count == 0) 2140 return; 2141 2142 if (ahc_is_paused(ahc)) { 2143 paused = 1; 2144 } else { 2145 paused = 0; 2146 ahc_pause(ahc); 2147 } 2148 2149 saved_scbptr = ahc_inb(ahc, SCBPTR); 2150 /* Ensure that the hscbs down on the card match the new information */ 2151 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 2152 struct hardware_scb *pending_hscb; 2153 u_int control; 2154 u_int scb_tag; 2155 2156 ahc_outb(ahc, SCBPTR, i); 2157 scb_tag = ahc_inb(ahc, SCB_TAG); 2158 pending_scb = ahc_lookup_scb(ahc, scb_tag); 2159 if (pending_scb == NULL) 2160 continue; 2161 2162 pending_hscb = pending_scb->hscb; 2163 control = ahc_inb(ahc, SCB_CONTROL); 2164 control &= ~(ULTRAENB|MK_MESSAGE); 2165 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE); 2166 ahc_outb(ahc, SCB_CONTROL, control); 2167 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate); 2168 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset); 2169 } 2170 ahc_outb(ahc, SCBPTR, saved_scbptr); 2171 2172 if (paused == 0) 2173 ahc_unpause(ahc); 2174 } 2175 2176 /**************************** Pathing Information *****************************/ 2177 static void 2178 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2179 { 2180 u_int saved_scsiid; 2181 role_t role; 2182 int our_id; 2183 2184 if (ahc_inb(ahc, SSTAT0) & TARGET) 2185 role = ROLE_TARGET; 2186 else 2187 role = ROLE_INITIATOR; 2188 2189 if (role == ROLE_TARGET 2190 && (ahc->features & AHC_MULTI_TID) != 0 2191 && (ahc_inb(ahc, SEQ_FLAGS) 2192 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) { 2193 /* We were selected, so pull our id from TARGIDIN */ 2194 our_id = ahc_inb(ahc, TARGIDIN) & OID; 2195 } else if ((ahc->features & AHC_ULTRA2) != 0) 2196 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 2197 else 2198 our_id = ahc_inb(ahc, SCSIID) & OID; 2199 2200 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 2201 ahc_compile_devinfo(devinfo, 2202 our_id, 2203 SCSIID_TARGET(ahc, saved_scsiid), 2204 ahc_inb(ahc, SAVED_LUN), 2205 SCSIID_CHANNEL(ahc, saved_scsiid), 2206 role); 2207 } 2208 2209 struct ahc_phase_table_entry* 2210 ahc_lookup_phase_entry(int phase) 2211 { 2212 struct ahc_phase_table_entry *entry; 2213 struct ahc_phase_table_entry *last_entry; 2214 2215 /* 2216 * num_phases doesn't include the default entry which 2217 * will be returned if the phase doesn't match. 2218 */ 2219 last_entry = &ahc_phase_table[num_phases]; 2220 for (entry = ahc_phase_table; entry < last_entry; entry++) { 2221 if (phase == entry->phase) 2222 break; 2223 } 2224 return (entry); 2225 } 2226 2227 void 2228 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 2229 u_int lun, char channel, role_t role) 2230 { 2231 devinfo->our_scsiid = our_id; 2232 devinfo->target = target; 2233 devinfo->lun = lun; 2234 devinfo->target_offset = target; 2235 devinfo->channel = channel; 2236 devinfo->role = role; 2237 if (channel == 'B') 2238 devinfo->target_offset += 8; 2239 devinfo->target_mask = (0x01 << devinfo->target_offset); 2240 } 2241 2242 void 2243 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2244 { 2245 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel, 2246 devinfo->target, devinfo->lun); 2247 } 2248 2249 static void 2250 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2251 struct scb *scb) 2252 { 2253 role_t role; 2254 int our_id; 2255 2256 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 2257 role = ROLE_INITIATOR; 2258 if ((scb->flags & SCB_TARGET_SCB) != 0) 2259 role = ROLE_TARGET; 2260 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb), 2261 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role); 2262 } 2263 2264 2265 /************************ Message Phase Processing ****************************/ 2266 static void 2267 ahc_assert_atn(struct ahc_softc *ahc) 2268 { 2269 u_int scsisigo; 2270 2271 scsisigo = ATNO; 2272 if ((ahc->features & AHC_DT) == 0) 2273 scsisigo |= ahc_inb(ahc, SCSISIGI); 2274 ahc_outb(ahc, SCSISIGO, scsisigo); 2275 } 2276 2277 /* 2278 * When an initiator transaction with the MK_MESSAGE flag either reconnects 2279 * or enters the initial message out phase, we are interrupted. Fill our 2280 * outgoing message buffer with the appropriate message and beging handing 2281 * the message phase(s) manually. 2282 */ 2283 static void 2284 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2285 struct scb *scb) 2286 { 2287 /* 2288 * To facilitate adding multiple messages together, 2289 * each routine should increment the index and len 2290 * variables instead of setting them explicitly. 2291 */ 2292 ahc->msgout_index = 0; 2293 ahc->msgout_len = 0; 2294 2295 if ((scb->flags & SCB_DEVICE_RESET) == 0 2296 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2297 u_int identify_msg; 2298 2299 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 2300 if ((scb->hscb->control & DISCENB) != 0) 2301 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2302 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2303 ahc->msgout_len++; 2304 2305 if ((scb->hscb->control & TAG_ENB) != 0) { 2306 ahc->msgout_buf[ahc->msgout_index++] = 2307 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 2308 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2309 ahc->msgout_len += 2; 2310 } 2311 } 2312 2313 if (scb->flags & SCB_DEVICE_RESET) { 2314 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2315 ahc->msgout_len++; 2316 ahc_print_path(ahc, scb); 2317 printf("Bus Device Reset Message Sent\n"); 2318 /* 2319 * Clear our selection hardware in advance of 2320 * the busfree. We may have an entry in the waiting 2321 * Q for this target, and we don't want to go about 2322 * selecting while we handle the busfree and blow it 2323 * away. 2324 */ 2325 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2326 } else if ((scb->flags & SCB_ABORT) != 0) { 2327 if ((scb->hscb->control & TAG_ENB) != 0) 2328 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2329 else 2330 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2331 ahc->msgout_len++; 2332 ahc_print_path(ahc, scb); 2333 printf("Abort%s Message Sent\n", 2334 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 2335 /* 2336 * Clear our selection hardware in advance of 2337 * the busfree. We may have an entry in the waiting 2338 * Q for this target, and we don't want to go about 2339 * selecting while we handle the busfree and blow it 2340 * away. 2341 */ 2342 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2343 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 2344 ahc_build_transfer_msg(ahc, devinfo); 2345 } else { 2346 printf("ahc_intr: AWAITING_MSG for an SCB that " 2347 "does not have a waiting message\n"); 2348 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 2349 devinfo->target_mask); 2350 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2351 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2352 ahc_inb(ahc, MSG_OUT), scb->flags); 2353 } 2354 2355 /* 2356 * Clear the MK_MESSAGE flag from the SCB so we aren't 2357 * asked to send this message again. 2358 */ 2359 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2360 scb->hscb->control &= ~MK_MESSAGE; 2361 ahc->msgout_index = 0; 2362 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2363 } 2364 2365 /* 2366 * Build an appropriate transfer negotiation message for the 2367 * currently active target. 2368 */ 2369 static void 2370 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2371 { 2372 /* 2373 * We need to initiate transfer negotiations. 2374 * If our current and goal settings are identical, 2375 * we want to renegotiate due to a check condition. 2376 */ 2377 struct ahc_initiator_tinfo *tinfo; 2378 struct ahc_tmode_tstate *tstate; 2379 struct ahc_syncrate *rate; 2380 int dowide; 2381 int dosync; 2382 int doppr; 2383 u_int period; 2384 u_int ppr_options; 2385 u_int offset; 2386 2387 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2388 devinfo->target, &tstate); 2389 /* 2390 * Filter our period based on the current connection. 2391 * If we can't perform DT transfers on this segment (not in LVD 2392 * mode for instance), then our decision to issue a PPR message 2393 * may change. 2394 */ 2395 period = tinfo->goal.period; 2396 offset = tinfo->goal.offset; 2397 ppr_options = tinfo->goal.ppr_options; 2398 /* Target initiated PPR is not allowed in the SCSI spec */ 2399 if (devinfo->role == ROLE_TARGET) 2400 ppr_options = 0; 2401 rate = ahc_devlimited_syncrate(ahc, tinfo, &period, 2402 &ppr_options, devinfo->role); 2403 dowide = tinfo->curr.width != tinfo->goal.width; 2404 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period; 2405 /* 2406 * Only use PPR if we have options that need it, even if the device 2407 * claims to support it. There might be an expander in the way 2408 * that doesn't. 2409 */ 2410 doppr = ppr_options != 0; 2411 2412 if (!dowide && !dosync && !doppr) { 2413 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2414 dosync = tinfo->goal.offset != 0; 2415 } 2416 2417 if (!dowide && !dosync && !doppr) { 2418 /* 2419 * Force async with a WDTR message if we have a wide bus, 2420 * or just issue an SDTR with a 0 offset. 2421 */ 2422 if ((ahc->features & AHC_WIDE) != 0) 2423 dowide = 1; 2424 else 2425 dosync = 1; 2426 2427 if (bootverbose) { 2428 ahc_print_devinfo(ahc, devinfo); 2429 printf("Ensuring async\n"); 2430 } 2431 } 2432 2433 /* Target initiated PPR is not allowed in the SCSI spec */ 2434 if (devinfo->role == ROLE_TARGET) 2435 doppr = 0; 2436 2437 /* 2438 * Both the PPR message and SDTR message require the 2439 * goal syncrate to be limited to what the target device 2440 * is capable of handling (based on whether an LVD->SE 2441 * expander is on the bus), so combine these two cases. 2442 * Regardless, guarantee that if we are using WDTR and SDTR 2443 * messages that WDTR comes first. 2444 */ 2445 if (doppr || (dosync && !dowide)) { 2446 2447 offset = tinfo->goal.offset; 2448 ahc_validate_offset(ahc, tinfo, rate, &offset, 2449 doppr ? tinfo->goal.width 2450 : tinfo->curr.width, 2451 devinfo->role); 2452 if (doppr) { 2453 ahc_construct_ppr(ahc, devinfo, period, offset, 2454 tinfo->goal.width, ppr_options); 2455 } else { 2456 ahc_construct_sdtr(ahc, devinfo, period, offset); 2457 } 2458 } else { 2459 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width); 2460 } 2461 } 2462 2463 /* 2464 * Build a synchronous negotiation message in our message 2465 * buffer based on the input parameters. 2466 */ 2467 static void 2468 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2469 u_int period, u_int offset) 2470 { 2471 if (offset == 0) 2472 period = AHC_ASYNC_XFER_PERIOD; 2473 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2474 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN; 2475 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR; 2476 ahc->msgout_buf[ahc->msgout_index++] = period; 2477 ahc->msgout_buf[ahc->msgout_index++] = offset; 2478 ahc->msgout_len += 5; 2479 if (bootverbose) { 2480 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 2481 ahc_name(ahc), devinfo->channel, devinfo->target, 2482 devinfo->lun, period, offset); 2483 } 2484 } 2485 2486 /* 2487 * Build a wide negotiation message in our message 2488 * buffer based on the input parameters. 2489 */ 2490 static void 2491 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2492 u_int bus_width) 2493 { 2494 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2495 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN; 2496 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR; 2497 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 2498 ahc->msgout_len += 4; 2499 if (bootverbose) { 2500 printf("(%s:%c:%d:%d): Sending WDTR %x\n", 2501 ahc_name(ahc), devinfo->channel, devinfo->target, 2502 devinfo->lun, bus_width); 2503 } 2504 } 2505 2506 /* 2507 * Build a parallel protocol request message in our message 2508 * buffer based on the input parameters. 2509 */ 2510 static void 2511 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2512 u_int period, u_int offset, u_int bus_width, 2513 u_int ppr_options) 2514 { 2515 if (offset == 0) 2516 period = AHC_ASYNC_XFER_PERIOD; 2517 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED; 2518 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN; 2519 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR; 2520 ahc->msgout_buf[ahc->msgout_index++] = period; 2521 ahc->msgout_buf[ahc->msgout_index++] = 0; 2522 ahc->msgout_buf[ahc->msgout_index++] = offset; 2523 ahc->msgout_buf[ahc->msgout_index++] = bus_width; 2524 ahc->msgout_buf[ahc->msgout_index++] = ppr_options; 2525 ahc->msgout_len += 8; 2526 if (bootverbose) { 2527 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, " 2528 "offset %x, ppr_options %x\n", ahc_name(ahc), 2529 devinfo->channel, devinfo->target, devinfo->lun, 2530 bus_width, period, offset, ppr_options); 2531 } 2532 } 2533 2534 /* 2535 * Clear any active message state. 2536 */ 2537 static void 2538 ahc_clear_msg_state(struct ahc_softc *ahc) 2539 { 2540 ahc->msgout_len = 0; 2541 ahc->msgin_index = 0; 2542 ahc->msg_type = MSG_TYPE_NONE; 2543 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) { 2544 /* 2545 * The target didn't care to respond to our 2546 * message request, so clear ATN. 2547 */ 2548 ahc_outb(ahc, CLRSINT1, CLRATNO); 2549 } 2550 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2551 ahc_outb(ahc, SEQ_FLAGS2, 2552 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 2553 } 2554 2555 static void 2556 ahc_handle_proto_violation(struct ahc_softc *ahc) 2557 { 2558 struct ahc_devinfo devinfo; 2559 struct scb *scb; 2560 u_int scbid; 2561 u_int seq_flags; 2562 u_int curphase; 2563 u_int lastphase; 2564 int found; 2565 2566 ahc_fetch_devinfo(ahc, &devinfo); 2567 scbid = ahc_inb(ahc, SCB_TAG); 2568 scb = ahc_lookup_scb(ahc, scbid); 2569 seq_flags = ahc_inb(ahc, SEQ_FLAGS); 2570 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2571 lastphase = ahc_inb(ahc, LASTPHASE); 2572 if ((seq_flags & NOT_IDENTIFIED) != 0) { 2573 2574 /* 2575 * The reconnecting target either did not send an 2576 * identify message, or did, but we didn't find an SCB 2577 * to match. 2578 */ 2579 ahc_print_devinfo(ahc, &devinfo); 2580 printf("Target did not send an IDENTIFY message. " 2581 "LASTPHASE = 0x%x.\n", lastphase); 2582 scb = NULL; 2583 } else if (scb == NULL) { 2584 /* 2585 * We don't seem to have an SCB active for this 2586 * transaction. Print an error and reset the bus. 2587 */ 2588 ahc_print_devinfo(ahc, &devinfo); 2589 printf("No SCB found during protocol violation\n"); 2590 goto proto_violation_reset; 2591 } else { 2592 aic_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 2593 if ((seq_flags & NO_CDB_SENT) != 0) { 2594 ahc_print_path(ahc, scb); 2595 printf("No or incomplete CDB sent to device.\n"); 2596 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) { 2597 /* 2598 * The target never bothered to provide status to 2599 * us prior to completing the command. Since we don't 2600 * know the disposition of this command, we must attempt 2601 * to abort it. Assert ATN and prepare to send an abort 2602 * message. 2603 */ 2604 ahc_print_path(ahc, scb); 2605 printf("Completed command without status.\n"); 2606 } else { 2607 ahc_print_path(ahc, scb); 2608 printf("Unknown protocol violation.\n"); 2609 ahc_dump_card_state(ahc); 2610 } 2611 } 2612 if ((lastphase & ~P_DATAIN_DT) == 0 2613 || lastphase == P_COMMAND) { 2614 proto_violation_reset: 2615 /* 2616 * Target either went directly to data/command 2617 * phase or didn't respond to our ATN. 2618 * The only safe thing to do is to blow 2619 * it away with a bus reset. 2620 */ 2621 found = ahc_reset_channel(ahc, 'A', TRUE); 2622 printf("%s: Issued Channel %c Bus Reset. " 2623 "%d SCBs aborted\n", ahc_name(ahc), 'A', found); 2624 } else { 2625 /* 2626 * Leave the selection hardware off in case 2627 * this abort attempt will affect yet to 2628 * be sent commands. 2629 */ 2630 ahc_outb(ahc, SCSISEQ, 2631 ahc_inb(ahc, SCSISEQ) & ~ENSELO); 2632 ahc_assert_atn(ahc); 2633 ahc_outb(ahc, MSG_OUT, HOST_MSG); 2634 if (scb == NULL) { 2635 ahc_print_devinfo(ahc, &devinfo); 2636 ahc->msgout_buf[0] = MSG_ABORT_TASK; 2637 ahc->msgout_len = 1; 2638 ahc->msgout_index = 0; 2639 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2640 } else { 2641 ahc_print_path(ahc, scb); 2642 scb->flags |= SCB_ABORT; 2643 } 2644 printf("Protocol violation %s. Attempting to abort.\n", 2645 ahc_lookup_phase_entry(curphase)->phasemsg); 2646 } 2647 } 2648 2649 /* 2650 * Manual message loop handler. 2651 */ 2652 static void 2653 ahc_handle_message_phase(struct ahc_softc *ahc) 2654 { 2655 struct ahc_devinfo devinfo; 2656 u_int bus_phase; 2657 int end_session; 2658 2659 ahc_fetch_devinfo(ahc, &devinfo); 2660 end_session = FALSE; 2661 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2662 2663 reswitch: 2664 switch (ahc->msg_type) { 2665 case MSG_TYPE_INITIATOR_MSGOUT: 2666 { 2667 int lastbyte; 2668 int phasemis; 2669 int msgdone; 2670 2671 if (ahc->msgout_len == 0) 2672 panic("HOST_MSG_LOOP interrupt with no active message"); 2673 2674 #ifdef AHC_DEBUG 2675 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2676 ahc_print_devinfo(ahc, &devinfo); 2677 printf("INITIATOR_MSG_OUT"); 2678 } 2679 #endif 2680 phasemis = bus_phase != P_MESGOUT; 2681 if (phasemis) { 2682 #ifdef AHC_DEBUG 2683 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2684 printf(" PHASEMIS %s\n", 2685 ahc_lookup_phase_entry(bus_phase) 2686 ->phasemsg); 2687 } 2688 #endif 2689 if (bus_phase == P_MESGIN) { 2690 /* 2691 * Change gears and see if 2692 * this messages is of interest to 2693 * us or should be passed back to 2694 * the sequencer. 2695 */ 2696 ahc_outb(ahc, CLRSINT1, CLRATNO); 2697 ahc->send_msg_perror = FALSE; 2698 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2699 ahc->msgin_index = 0; 2700 goto reswitch; 2701 } 2702 end_session = TRUE; 2703 break; 2704 } 2705 2706 if (ahc->send_msg_perror) { 2707 ahc_outb(ahc, CLRSINT1, CLRATNO); 2708 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2709 #ifdef AHC_DEBUG 2710 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2711 printf(" byte 0x%x\n", ahc->send_msg_perror); 2712 #endif 2713 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2714 break; 2715 } 2716 2717 msgdone = ahc->msgout_index == ahc->msgout_len; 2718 if (msgdone) { 2719 /* 2720 * The target has requested a retry. 2721 * Re-assert ATN, reset our message index to 2722 * 0, and try again. 2723 */ 2724 ahc->msgout_index = 0; 2725 ahc_assert_atn(ahc); 2726 } 2727 2728 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2729 if (lastbyte) { 2730 /* Last byte is signified by dropping ATN */ 2731 ahc_outb(ahc, CLRSINT1, CLRATNO); 2732 } 2733 2734 /* 2735 * Clear our interrupt status and present 2736 * the next byte on the bus. 2737 */ 2738 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2739 #ifdef AHC_DEBUG 2740 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2741 printf(" byte 0x%x\n", 2742 ahc->msgout_buf[ahc->msgout_index]); 2743 #endif 2744 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2745 break; 2746 } 2747 case MSG_TYPE_INITIATOR_MSGIN: 2748 { 2749 int phasemis; 2750 int message_done; 2751 2752 #ifdef AHC_DEBUG 2753 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2754 ahc_print_devinfo(ahc, &devinfo); 2755 printf("INITIATOR_MSG_IN"); 2756 } 2757 #endif 2758 phasemis = bus_phase != P_MESGIN; 2759 if (phasemis) { 2760 #ifdef AHC_DEBUG 2761 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2762 printf(" PHASEMIS %s\n", 2763 ahc_lookup_phase_entry(bus_phase) 2764 ->phasemsg); 2765 } 2766 #endif 2767 ahc->msgin_index = 0; 2768 if (bus_phase == P_MESGOUT 2769 && (ahc->send_msg_perror == TRUE 2770 || (ahc->msgout_len != 0 2771 && ahc->msgout_index == 0))) { 2772 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2773 goto reswitch; 2774 } 2775 end_session = TRUE; 2776 break; 2777 } 2778 2779 /* Pull the byte in without acking it */ 2780 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2781 #ifdef AHC_DEBUG 2782 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2783 printf(" byte 0x%x\n", 2784 ahc->msgin_buf[ahc->msgin_index]); 2785 #endif 2786 2787 message_done = ahc_parse_msg(ahc, &devinfo); 2788 2789 if (message_done) { 2790 /* 2791 * Clear our incoming message buffer in case there 2792 * is another message following this one. 2793 */ 2794 ahc->msgin_index = 0; 2795 2796 /* 2797 * If this message illicited a response, 2798 * assert ATN so the target takes us to the 2799 * message out phase. 2800 */ 2801 if (ahc->msgout_len != 0) { 2802 #ifdef AHC_DEBUG 2803 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2804 ahc_print_devinfo(ahc, &devinfo); 2805 printf("Asserting ATN for response\n"); 2806 } 2807 #endif 2808 ahc_assert_atn(ahc); 2809 } 2810 } else 2811 ahc->msgin_index++; 2812 2813 if (message_done == MSGLOOP_TERMINATED) { 2814 end_session = TRUE; 2815 } else { 2816 /* Ack the byte */ 2817 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2818 ahc_inb(ahc, SCSIDATL); 2819 } 2820 break; 2821 } 2822 case MSG_TYPE_TARGET_MSGIN: 2823 { 2824 int msgdone; 2825 int msgout_request; 2826 2827 if (ahc->msgout_len == 0) 2828 panic("Target MSGIN with no active message"); 2829 2830 /* 2831 * If we interrupted a mesgout session, the initiator 2832 * will not know this until our first REQ. So, we 2833 * only honor mesgout requests after we've sent our 2834 * first byte. 2835 */ 2836 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2837 && ahc->msgout_index > 0) 2838 msgout_request = TRUE; 2839 else 2840 msgout_request = FALSE; 2841 2842 if (msgout_request) { 2843 2844 /* 2845 * Change gears and see if 2846 * this messages is of interest to 2847 * us or should be passed back to 2848 * the sequencer. 2849 */ 2850 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2851 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2852 ahc->msgin_index = 0; 2853 /* Dummy read to REQ for first byte */ 2854 ahc_inb(ahc, SCSIDATL); 2855 ahc_outb(ahc, SXFRCTL0, 2856 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2857 break; 2858 } 2859 2860 msgdone = ahc->msgout_index == ahc->msgout_len; 2861 if (msgdone) { 2862 ahc_outb(ahc, SXFRCTL0, 2863 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2864 end_session = TRUE; 2865 break; 2866 } 2867 2868 /* 2869 * Present the next byte on the bus. 2870 */ 2871 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2872 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2873 break; 2874 } 2875 case MSG_TYPE_TARGET_MSGOUT: 2876 { 2877 int lastbyte; 2878 int msgdone; 2879 2880 /* 2881 * The initiator signals that this is 2882 * the last byte by dropping ATN. 2883 */ 2884 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2885 2886 /* 2887 * Read the latched byte, but turn off SPIOEN first 2888 * so that we don't inadvertently cause a REQ for the 2889 * next byte. 2890 */ 2891 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2892 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2893 msgdone = ahc_parse_msg(ahc, &devinfo); 2894 if (msgdone == MSGLOOP_TERMINATED) { 2895 /* 2896 * The message is *really* done in that it caused 2897 * us to go to bus free. The sequencer has already 2898 * been reset at this point, so pull the ejection 2899 * handle. 2900 */ 2901 return; 2902 } 2903 2904 ahc->msgin_index++; 2905 2906 /* 2907 * XXX Read spec about initiator dropping ATN too soon 2908 * and use msgdone to detect it. 2909 */ 2910 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2911 ahc->msgin_index = 0; 2912 2913 /* 2914 * If this message illicited a response, transition 2915 * to the Message in phase and send it. 2916 */ 2917 if (ahc->msgout_len != 0) { 2918 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2919 ahc_outb(ahc, SXFRCTL0, 2920 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2921 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2922 ahc->msgin_index = 0; 2923 break; 2924 } 2925 } 2926 2927 if (lastbyte) 2928 end_session = TRUE; 2929 else { 2930 /* Ask for the next byte. */ 2931 ahc_outb(ahc, SXFRCTL0, 2932 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2933 } 2934 2935 break; 2936 } 2937 default: 2938 panic("Unknown REQINIT message type"); 2939 } 2940 2941 if (end_session) { 2942 ahc_clear_msg_state(ahc); 2943 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2944 } else 2945 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2946 } 2947 2948 /* 2949 * See if we sent a particular extended message to the target. 2950 * If "full" is true, return true only if the target saw the full 2951 * message. If "full" is false, return true if the target saw at 2952 * least the first byte of the message. 2953 */ 2954 static int 2955 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full) 2956 { 2957 int found; 2958 u_int index; 2959 2960 found = FALSE; 2961 index = 0; 2962 2963 while (index < ahc->msgout_len) { 2964 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2965 u_int end_index; 2966 2967 end_index = index + 1 + ahc->msgout_buf[index + 1]; 2968 if (ahc->msgout_buf[index+2] == msgval 2969 && type == AHCMSG_EXT) { 2970 2971 if (full) { 2972 if (ahc->msgout_index > end_index) 2973 found = TRUE; 2974 } else if (ahc->msgout_index > index) 2975 found = TRUE; 2976 } 2977 index = end_index; 2978 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK 2979 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2980 2981 /* Skip tag type and tag id or residue param*/ 2982 index += 2; 2983 } else { 2984 /* Single byte message */ 2985 if (type == AHCMSG_1B 2986 && ahc->msgout_buf[index] == msgval 2987 && ahc->msgout_index > index) 2988 found = TRUE; 2989 index++; 2990 } 2991 2992 if (found) 2993 break; 2994 } 2995 return (found); 2996 } 2997 2998 /* 2999 * Wait for a complete incoming message, parse it, and respond accordingly. 3000 */ 3001 static int 3002 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3003 { 3004 struct ahc_initiator_tinfo *tinfo; 3005 struct ahc_tmode_tstate *tstate; 3006 int reject; 3007 int done; 3008 int response; 3009 u_int targ_scsirate; 3010 3011 done = MSGLOOP_IN_PROG; 3012 response = FALSE; 3013 reject = FALSE; 3014 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 3015 devinfo->target, &tstate); 3016 targ_scsirate = tinfo->scsirate; 3017 3018 /* 3019 * Parse as much of the message as is available, 3020 * rejecting it if we don't support it. When 3021 * the entire message is available and has been 3022 * handled, return MSGLOOP_MSGCOMPLETE, indicating 3023 * that we have parsed an entire message. 3024 * 3025 * In the case of extended messages, we accept the length 3026 * byte outright and perform more checking once we know the 3027 * extended message type. 3028 */ 3029 switch (ahc->msgin_buf[0]) { 3030 case MSG_DISCONNECT: 3031 case MSG_SAVEDATAPOINTER: 3032 case MSG_CMDCOMPLETE: 3033 case MSG_RESTOREPOINTERS: 3034 case MSG_IGN_WIDE_RESIDUE: 3035 /* 3036 * End our message loop as these are messages 3037 * the sequencer handles on its own. 3038 */ 3039 done = MSGLOOP_TERMINATED; 3040 break; 3041 case MSG_MESSAGE_REJECT: 3042 response = ahc_handle_msg_reject(ahc, devinfo); 3043 /* FALLTHROUGH */ 3044 case MSG_NOOP: 3045 done = MSGLOOP_MSGCOMPLETE; 3046 break; 3047 case MSG_EXTENDED: 3048 { 3049 /* Wait for enough of the message to begin validation */ 3050 if (ahc->msgin_index < 2) 3051 break; 3052 switch (ahc->msgin_buf[2]) { 3053 case MSG_EXT_SDTR: 3054 { 3055 struct ahc_syncrate *syncrate; 3056 u_int period; 3057 u_int ppr_options; 3058 u_int offset; 3059 u_int saved_offset; 3060 3061 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 3062 reject = TRUE; 3063 break; 3064 } 3065 3066 /* 3067 * Wait until we have both args before validating 3068 * and acting on this message. 3069 * 3070 * Add one to MSG_EXT_SDTR_LEN to account for 3071 * the extended message preamble. 3072 */ 3073 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 3074 break; 3075 3076 period = ahc->msgin_buf[3]; 3077 ppr_options = 0; 3078 saved_offset = offset = ahc->msgin_buf[4]; 3079 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3080 &ppr_options, 3081 devinfo->role); 3082 ahc_validate_offset(ahc, tinfo, syncrate, &offset, 3083 targ_scsirate & WIDEXFER, 3084 devinfo->role); 3085 if (bootverbose) { 3086 printf("(%s:%c:%d:%d): Received " 3087 "SDTR period %x, offset %x\n\t" 3088 "Filtered to period %x, offset %x\n", 3089 ahc_name(ahc), devinfo->channel, 3090 devinfo->target, devinfo->lun, 3091 ahc->msgin_buf[3], saved_offset, 3092 period, offset); 3093 } 3094 ahc_set_syncrate(ahc, devinfo, 3095 syncrate, period, 3096 offset, ppr_options, 3097 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3098 /*paused*/TRUE); 3099 3100 /* 3101 * See if we initiated Sync Negotiation 3102 * and didn't have to fall down to async 3103 * transfers. 3104 */ 3105 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) { 3106 /* We started it */ 3107 if (saved_offset != offset) { 3108 /* Went too low - force async */ 3109 reject = TRUE; 3110 } 3111 } else { 3112 /* 3113 * Send our own SDTR in reply 3114 */ 3115 if (bootverbose 3116 && devinfo->role == ROLE_INITIATOR) { 3117 printf("(%s:%c:%d:%d): Target " 3118 "Initiated SDTR\n", 3119 ahc_name(ahc), devinfo->channel, 3120 devinfo->target, devinfo->lun); 3121 } 3122 ahc->msgout_index = 0; 3123 ahc->msgout_len = 0; 3124 ahc_construct_sdtr(ahc, devinfo, 3125 period, offset); 3126 ahc->msgout_index = 0; 3127 response = TRUE; 3128 } 3129 done = MSGLOOP_MSGCOMPLETE; 3130 break; 3131 } 3132 case MSG_EXT_WDTR: 3133 { 3134 u_int bus_width; 3135 u_int saved_width; 3136 u_int sending_reply; 3137 3138 sending_reply = FALSE; 3139 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3140 reject = TRUE; 3141 break; 3142 } 3143 3144 /* 3145 * Wait until we have our arg before validating 3146 * and acting on this message. 3147 * 3148 * Add one to MSG_EXT_WDTR_LEN to account for 3149 * the extended message preamble. 3150 */ 3151 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3152 break; 3153 3154 bus_width = ahc->msgin_buf[3]; 3155 saved_width = bus_width; 3156 ahc_validate_width(ahc, tinfo, &bus_width, 3157 devinfo->role); 3158 if (bootverbose) { 3159 printf("(%s:%c:%d:%d): Received WDTR " 3160 "%x filtered to %x\n", 3161 ahc_name(ahc), devinfo->channel, 3162 devinfo->target, devinfo->lun, 3163 saved_width, bus_width); 3164 } 3165 3166 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) { 3167 /* 3168 * Don't send a WDTR back to the 3169 * target, since we asked first. 3170 * If the width went higher than our 3171 * request, reject it. 3172 */ 3173 if (saved_width > bus_width) { 3174 reject = TRUE; 3175 printf("(%s:%c:%d:%d): requested %dBit " 3176 "transfers. Rejecting...\n", 3177 ahc_name(ahc), devinfo->channel, 3178 devinfo->target, devinfo->lun, 3179 8 * (0x01 << bus_width)); 3180 bus_width = 0; 3181 } 3182 } else { 3183 /* 3184 * Send our own WDTR in reply 3185 */ 3186 if (bootverbose 3187 && devinfo->role == ROLE_INITIATOR) { 3188 printf("(%s:%c:%d:%d): Target " 3189 "Initiated WDTR\n", 3190 ahc_name(ahc), devinfo->channel, 3191 devinfo->target, devinfo->lun); 3192 } 3193 ahc->msgout_index = 0; 3194 ahc->msgout_len = 0; 3195 ahc_construct_wdtr(ahc, devinfo, bus_width); 3196 ahc->msgout_index = 0; 3197 response = TRUE; 3198 sending_reply = TRUE; 3199 } 3200 /* 3201 * After a wide message, we are async, but 3202 * some devices don't seem to honor this portion 3203 * of the spec. Force a renegotiation of the 3204 * sync component of our transfer agreement even 3205 * if our goal is async. By updating our width 3206 * after forcing the negotiation, we avoid 3207 * renegotiating for width. 3208 */ 3209 ahc_update_neg_request(ahc, devinfo, tstate, 3210 tinfo, AHC_NEG_ALWAYS); 3211 ahc_set_width(ahc, devinfo, bus_width, 3212 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3213 /*paused*/TRUE); 3214 if (sending_reply == FALSE && reject == FALSE) { 3215 3216 /* 3217 * We will always have an SDTR to send. 3218 */ 3219 ahc->msgout_index = 0; 3220 ahc->msgout_len = 0; 3221 ahc_build_transfer_msg(ahc, devinfo); 3222 ahc->msgout_index = 0; 3223 response = TRUE; 3224 } 3225 done = MSGLOOP_MSGCOMPLETE; 3226 break; 3227 } 3228 case MSG_EXT_PPR: 3229 { 3230 struct ahc_syncrate *syncrate; 3231 u_int period; 3232 u_int offset; 3233 u_int bus_width; 3234 u_int ppr_options; 3235 u_int saved_width; 3236 u_int saved_offset; 3237 u_int saved_ppr_options; 3238 3239 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) { 3240 reject = TRUE; 3241 break; 3242 } 3243 3244 /* 3245 * Wait until we have all args before validating 3246 * and acting on this message. 3247 * 3248 * Add one to MSG_EXT_PPR_LEN to account for 3249 * the extended message preamble. 3250 */ 3251 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1)) 3252 break; 3253 3254 period = ahc->msgin_buf[3]; 3255 offset = ahc->msgin_buf[5]; 3256 bus_width = ahc->msgin_buf[6]; 3257 saved_width = bus_width; 3258 ppr_options = ahc->msgin_buf[7]; 3259 /* 3260 * According to the spec, a DT only 3261 * period factor with no DT option 3262 * set implies async. 3263 */ 3264 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 3265 && period == 9) 3266 offset = 0; 3267 saved_ppr_options = ppr_options; 3268 saved_offset = offset; 3269 3270 /* 3271 * Mask out any options we don't support 3272 * on any controller. Transfer options are 3273 * only available if we are negotiating wide. 3274 */ 3275 ppr_options &= MSG_EXT_PPR_DT_REQ; 3276 if (bus_width == 0) 3277 ppr_options = 0; 3278 3279 ahc_validate_width(ahc, tinfo, &bus_width, 3280 devinfo->role); 3281 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3282 &ppr_options, 3283 devinfo->role); 3284 ahc_validate_offset(ahc, tinfo, syncrate, 3285 &offset, bus_width, 3286 devinfo->role); 3287 3288 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) { 3289 /* 3290 * If we are unable to do any of the 3291 * requested options (we went too low), 3292 * then we'll have to reject the message. 3293 */ 3294 if (saved_width > bus_width 3295 || saved_offset != offset 3296 || saved_ppr_options != ppr_options) { 3297 reject = TRUE; 3298 period = 0; 3299 offset = 0; 3300 bus_width = 0; 3301 ppr_options = 0; 3302 syncrate = NULL; 3303 } 3304 } else { 3305 if (devinfo->role != ROLE_TARGET) 3306 printf("(%s:%c:%d:%d): Target " 3307 "Initiated PPR\n", 3308 ahc_name(ahc), devinfo->channel, 3309 devinfo->target, devinfo->lun); 3310 else 3311 printf("(%s:%c:%d:%d): Initiator " 3312 "Initiated PPR\n", 3313 ahc_name(ahc), devinfo->channel, 3314 devinfo->target, devinfo->lun); 3315 ahc->msgout_index = 0; 3316 ahc->msgout_len = 0; 3317 ahc_construct_ppr(ahc, devinfo, period, offset, 3318 bus_width, ppr_options); 3319 ahc->msgout_index = 0; 3320 response = TRUE; 3321 } 3322 if (bootverbose) { 3323 printf("(%s:%c:%d:%d): Received PPR width %x, " 3324 "period %x, offset %x,options %x\n" 3325 "\tFiltered to width %x, period %x, " 3326 "offset %x, options %x\n", 3327 ahc_name(ahc), devinfo->channel, 3328 devinfo->target, devinfo->lun, 3329 saved_width, ahc->msgin_buf[3], 3330 saved_offset, saved_ppr_options, 3331 bus_width, period, offset, ppr_options); 3332 } 3333 ahc_set_width(ahc, devinfo, bus_width, 3334 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3335 /*paused*/TRUE); 3336 ahc_set_syncrate(ahc, devinfo, 3337 syncrate, period, 3338 offset, ppr_options, 3339 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3340 /*paused*/TRUE); 3341 done = MSGLOOP_MSGCOMPLETE; 3342 break; 3343 } 3344 default: 3345 /* Unknown extended message. Reject it. */ 3346 reject = TRUE; 3347 break; 3348 } 3349 break; 3350 } 3351 #ifdef AHC_TARGET_MODE 3352 case MSG_BUS_DEV_RESET: 3353 ahc_handle_devreset(ahc, devinfo, 3354 CAM_BDR_SENT, 3355 "Bus Device Reset Received", 3356 /*verbose_level*/0); 3357 ahc_restart(ahc); 3358 done = MSGLOOP_TERMINATED; 3359 break; 3360 case MSG_ABORT_TAG: 3361 case MSG_ABORT: 3362 case MSG_CLEAR_QUEUE: 3363 { 3364 int tag; 3365 3366 /* Target mode messages */ 3367 if (devinfo->role != ROLE_TARGET) { 3368 reject = TRUE; 3369 break; 3370 } 3371 tag = SCB_LIST_NULL; 3372 if (ahc->msgin_buf[0] == MSG_ABORT_TAG) 3373 tag = ahc_inb(ahc, INITIATOR_TAG); 3374 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3375 devinfo->lun, tag, ROLE_TARGET, 3376 CAM_REQ_ABORTED); 3377 3378 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3379 if (tstate != NULL) { 3380 struct ahc_tmode_lstate* lstate; 3381 3382 lstate = tstate->enabled_luns[devinfo->lun]; 3383 if (lstate != NULL) { 3384 ahc_queue_lstate_event(ahc, lstate, 3385 devinfo->our_scsiid, 3386 ahc->msgin_buf[0], 3387 /*arg*/tag); 3388 ahc_send_lstate_events(ahc, lstate); 3389 } 3390 } 3391 ahc_restart(ahc); 3392 done = MSGLOOP_TERMINATED; 3393 break; 3394 } 3395 #endif 3396 case MSG_TERM_IO_PROC: 3397 default: 3398 reject = TRUE; 3399 break; 3400 } 3401 3402 if (reject) { 3403 /* 3404 * Setup to reject the message. 3405 */ 3406 ahc->msgout_index = 0; 3407 ahc->msgout_len = 1; 3408 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3409 done = MSGLOOP_MSGCOMPLETE; 3410 response = TRUE; 3411 } 3412 3413 if (done != MSGLOOP_IN_PROG && !response) 3414 /* Clear the outgoing message buffer */ 3415 ahc->msgout_len = 0; 3416 3417 return (done); 3418 } 3419 3420 /* 3421 * Process a message reject message. 3422 */ 3423 static int 3424 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3425 { 3426 /* 3427 * What we care about here is if we had an 3428 * outstanding SDTR or WDTR message for this 3429 * target. If we did, this is a signal that 3430 * the target is refusing negotiation. 3431 */ 3432 struct scb *scb; 3433 struct ahc_initiator_tinfo *tinfo; 3434 struct ahc_tmode_tstate *tstate; 3435 u_int scb_index; 3436 u_int last_msg; 3437 int response = 0; 3438 3439 scb_index = ahc_inb(ahc, SCB_TAG); 3440 scb = ahc_lookup_scb(ahc, scb_index); 3441 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 3442 devinfo->our_scsiid, 3443 devinfo->target, &tstate); 3444 /* Might be necessary */ 3445 last_msg = ahc_inb(ahc, LAST_MSG); 3446 3447 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 3448 /* 3449 * Target does not support the PPR message. 3450 * Attempt to negotiate SPI-2 style. 3451 */ 3452 if (bootverbose) { 3453 printf("(%s:%c:%d:%d): PPR Rejected. " 3454 "Trying WDTR/SDTR\n", 3455 ahc_name(ahc), devinfo->channel, 3456 devinfo->target, devinfo->lun); 3457 } 3458 tinfo->goal.ppr_options = 0; 3459 tinfo->curr.transport_version = 2; 3460 tinfo->goal.transport_version = 2; 3461 ahc->msgout_index = 0; 3462 ahc->msgout_len = 0; 3463 ahc_build_transfer_msg(ahc, devinfo); 3464 ahc->msgout_index = 0; 3465 response = 1; 3466 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 3467 3468 /* note 8bit xfers */ 3469 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 3470 "8bit transfers\n", ahc_name(ahc), 3471 devinfo->channel, devinfo->target, devinfo->lun); 3472 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3473 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3474 /*paused*/TRUE); 3475 /* 3476 * No need to clear the sync rate. If the target 3477 * did not accept the command, our syncrate is 3478 * unaffected. If the target started the negotiation, 3479 * but rejected our response, we already cleared the 3480 * sync rate before sending our WDTR. 3481 */ 3482 if (tinfo->goal.offset != tinfo->curr.offset) { 3483 3484 /* Start the sync negotiation */ 3485 ahc->msgout_index = 0; 3486 ahc->msgout_len = 0; 3487 ahc_build_transfer_msg(ahc, devinfo); 3488 ahc->msgout_index = 0; 3489 response = 1; 3490 } 3491 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 3492 /* note asynch xfers and clear flag */ 3493 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 3494 /*offset*/0, /*ppr_options*/0, 3495 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3496 /*paused*/TRUE); 3497 printf("(%s:%c:%d:%d): refuses synchronous negotiation. " 3498 "Using asynchronous transfers\n", 3499 ahc_name(ahc), devinfo->channel, 3500 devinfo->target, devinfo->lun); 3501 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 3502 int tag_type; 3503 int mask; 3504 3505 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 3506 3507 if (tag_type == MSG_SIMPLE_TASK) { 3508 printf("(%s:%c:%d:%d): refuses tagged commands. " 3509 "Performing non-tagged I/O\n", ahc_name(ahc), 3510 devinfo->channel, devinfo->target, devinfo->lun); 3511 ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE); 3512 mask = ~0x23; 3513 } else { 3514 printf("(%s:%c:%d:%d): refuses %s tagged commands. " 3515 "Performing simple queue tagged I/O only\n", 3516 ahc_name(ahc), devinfo->channel, devinfo->target, 3517 devinfo->lun, tag_type == MSG_ORDERED_TASK 3518 ? "ordered" : "head of queue"); 3519 ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC); 3520 mask = ~0x03; 3521 } 3522 3523 /* 3524 * Resend the identify for this CCB as the target 3525 * may believe that the selection is invalid otherwise. 3526 */ 3527 ahc_outb(ahc, SCB_CONTROL, 3528 ahc_inb(ahc, SCB_CONTROL) & mask); 3529 scb->hscb->control &= mask; 3530 aic_set_transaction_tag(scb, /*enabled*/FALSE, 3531 /*type*/MSG_SIMPLE_TASK); 3532 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 3533 ahc_assert_atn(ahc); 3534 3535 /* 3536 * This transaction is now at the head of 3537 * the untagged queue for this target. 3538 */ 3539 if ((ahc->flags & AHC_SCB_BTT) == 0) { 3540 struct scb_tailq *untagged_q; 3541 3542 untagged_q = 3543 &(ahc->untagged_queues[devinfo->target_offset]); 3544 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe); 3545 scb->flags |= SCB_UNTAGGEDQ; 3546 } 3547 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 3548 scb->hscb->tag); 3549 3550 /* 3551 * Requeue all tagged commands for this target 3552 * currently in our posession so they can be 3553 * converted to untagged commands. 3554 */ 3555 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 3556 SCB_GET_CHANNEL(ahc, scb), 3557 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 3558 ROLE_INITIATOR, CAM_REQUEUE_REQ, 3559 SEARCH_COMPLETE); 3560 } else { 3561 /* 3562 * Otherwise, we ignore it. 3563 */ 3564 printf("%s:%c:%d: Message reject for %x -- ignored\n", 3565 ahc_name(ahc), devinfo->channel, devinfo->target, 3566 last_msg); 3567 } 3568 return (response); 3569 } 3570 3571 /* 3572 * Process an ingnore wide residue message. 3573 */ 3574 static void 3575 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3576 { 3577 u_int scb_index; 3578 struct scb *scb; 3579 3580 scb_index = ahc_inb(ahc, SCB_TAG); 3581 scb = ahc_lookup_scb(ahc, scb_index); 3582 /* 3583 * XXX Actually check data direction in the sequencer? 3584 * Perhaps add datadir to some spare bits in the hscb? 3585 */ 3586 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3587 || aic_get_transfer_dir(scb) != CAM_DIR_IN) { 3588 /* 3589 * Ignore the message if we haven't 3590 * seen an appropriate data phase yet. 3591 */ 3592 } else { 3593 /* 3594 * If the residual occurred on the last 3595 * transfer and the transfer request was 3596 * expected to end on an odd count, do 3597 * nothing. Otherwise, subtract a byte 3598 * and update the residual count accordingly. 3599 */ 3600 uint32_t sgptr; 3601 3602 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3603 if ((sgptr & SG_LIST_NULL) != 0 3604 && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) { 3605 /* 3606 * If the residual occurred on the last 3607 * transfer and the transfer request was 3608 * expected to end on an odd count, do 3609 * nothing. 3610 */ 3611 } else { 3612 struct ahc_dma_seg *sg; 3613 uint32_t data_cnt; 3614 uint32_t data_addr; 3615 uint32_t sglen; 3616 3617 /* Pull in all of the sgptr */ 3618 sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR); 3619 data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT); 3620 3621 if ((sgptr & SG_LIST_NULL) != 0) { 3622 /* 3623 * The residual data count is not updated 3624 * for the command run to completion case. 3625 * Explicitly zero the count. 3626 */ 3627 data_cnt &= ~AHC_SG_LEN_MASK; 3628 } 3629 3630 data_addr = ahc_inl(ahc, SHADDR); 3631 3632 data_cnt += 1; 3633 data_addr -= 1; 3634 sgptr &= SG_PTR_MASK; 3635 3636 sg = ahc_sg_bus_to_virt(scb, sgptr); 3637 3638 /* 3639 * The residual sg ptr points to the next S/G 3640 * to load so we must go back one. 3641 */ 3642 sg--; 3643 sglen = aic_le32toh(sg->len) & AHC_SG_LEN_MASK; 3644 if (sg != scb->sg_list 3645 && sglen < (data_cnt & AHC_SG_LEN_MASK)) { 3646 3647 sg--; 3648 sglen = aic_le32toh(sg->len); 3649 /* 3650 * Preserve High Address and SG_LIST bits 3651 * while setting the count to 1. 3652 */ 3653 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK)); 3654 data_addr = aic_le32toh(sg->addr) 3655 + (sglen & AHC_SG_LEN_MASK) - 1; 3656 3657 /* 3658 * Increment sg so it points to the 3659 * "next" sg. 3660 */ 3661 sg++; 3662 sgptr = ahc_sg_virt_to_bus(scb, sg); 3663 } 3664 ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr); 3665 ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt); 3666 /* 3667 * Toggle the "oddness" of the transfer length 3668 * to handle this mid-transfer ignore wide 3669 * residue. This ensures that the oddness is 3670 * correct for subsequent data transfers. 3671 */ 3672 ahc_outb(ahc, SCB_LUN, 3673 ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD); 3674 } 3675 } 3676 } 3677 3678 3679 /* 3680 * Reinitialize the data pointers for the active transfer 3681 * based on its current residual. 3682 */ 3683 static void 3684 ahc_reinitialize_dataptrs(struct ahc_softc *ahc) 3685 { 3686 struct scb *scb; 3687 struct ahc_dma_seg *sg; 3688 u_int scb_index; 3689 uint32_t sgptr; 3690 uint32_t resid; 3691 uint32_t dataptr; 3692 3693 scb_index = ahc_inb(ahc, SCB_TAG); 3694 scb = ahc_lookup_scb(ahc, scb_index); 3695 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24) 3696 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16) 3697 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8) 3698 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3699 3700 sgptr &= SG_PTR_MASK; 3701 sg = ahc_sg_bus_to_virt(scb, sgptr); 3702 3703 /* The residual sg_ptr always points to the next sg */ 3704 sg--; 3705 3706 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16) 3707 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8) 3708 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT); 3709 3710 dataptr = aic_le32toh(sg->addr) 3711 + (aic_le32toh(sg->len) & AHC_SG_LEN_MASK) 3712 - resid; 3713 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 3714 u_int dscommand1; 3715 3716 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 3717 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 3718 ahc_outb(ahc, HADDR, 3719 (aic_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS); 3720 ahc_outb(ahc, DSCOMMAND1, dscommand1); 3721 } 3722 ahc_outb(ahc, HADDR + 3, dataptr >> 24); 3723 ahc_outb(ahc, HADDR + 2, dataptr >> 16); 3724 ahc_outb(ahc, HADDR + 1, dataptr >> 8); 3725 ahc_outb(ahc, HADDR, dataptr); 3726 ahc_outb(ahc, HCNT + 2, resid >> 16); 3727 ahc_outb(ahc, HCNT + 1, resid >> 8); 3728 ahc_outb(ahc, HCNT, resid); 3729 if ((ahc->features & AHC_ULTRA2) == 0) { 3730 ahc_outb(ahc, STCNT + 2, resid >> 16); 3731 ahc_outb(ahc, STCNT + 1, resid >> 8); 3732 ahc_outb(ahc, STCNT, resid); 3733 } 3734 } 3735 3736 /* 3737 * Handle the effects of issuing a bus device reset message. 3738 */ 3739 static void 3740 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3741 cam_status status, char *message, int verbose_level) 3742 { 3743 #ifdef AHC_TARGET_MODE 3744 struct ahc_tmode_tstate* tstate; 3745 u_int lun; 3746 #endif 3747 int found; 3748 3749 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3750 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3751 status); 3752 3753 #ifdef AHC_TARGET_MODE 3754 /* 3755 * Send an immediate notify ccb to all target mord peripheral 3756 * drivers affected by this action. 3757 */ 3758 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3759 if (tstate != NULL) { 3760 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 3761 struct ahc_tmode_lstate* lstate; 3762 3763 lstate = tstate->enabled_luns[lun]; 3764 if (lstate == NULL) 3765 continue; 3766 3767 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid, 3768 MSG_BUS_DEV_RESET, /*arg*/0); 3769 ahc_send_lstate_events(ahc, lstate); 3770 } 3771 } 3772 #endif 3773 3774 /* 3775 * Go back to async/narrow transfers and renegotiate. 3776 */ 3777 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3778 AHC_TRANS_CUR, /*paused*/TRUE); 3779 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3780 /*period*/0, /*offset*/0, /*ppr_options*/0, 3781 AHC_TRANS_CUR, /*paused*/TRUE); 3782 3783 if (status != CAM_SEL_TIMEOUT) 3784 ahc_send_async(ahc, devinfo->channel, devinfo->target, 3785 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL); 3786 3787 if (message != NULL 3788 && (verbose_level <= bootverbose)) 3789 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3790 message, devinfo->channel, devinfo->target, found); 3791 } 3792 3793 #ifdef AHC_TARGET_MODE 3794 static void 3795 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3796 struct scb *scb) 3797 { 3798 3799 /* 3800 * To facilitate adding multiple messages together, 3801 * each routine should increment the index and len 3802 * variables instead of setting them explicitly. 3803 */ 3804 ahc->msgout_index = 0; 3805 ahc->msgout_len = 0; 3806 3807 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 3808 ahc_build_transfer_msg(ahc, devinfo); 3809 else 3810 panic("ahc_intr: AWAITING target message with no message"); 3811 3812 ahc->msgout_index = 0; 3813 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 3814 } 3815 #endif 3816 /**************************** Initialization **********************************/ 3817 /* 3818 * Allocate a controller structure for a new device 3819 * and perform initial initializion. 3820 */ 3821 struct ahc_softc * 3822 ahc_alloc(void *platform_arg, char *name) 3823 { 3824 struct ahc_softc *ahc; 3825 int i; 3826 3827 #ifndef __FreeBSD__ 3828 ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT); 3829 if (!ahc) { 3830 printf("aic7xxx: cannot malloc softc!\n"); 3831 free(name, M_DEVBUF); 3832 return NULL; 3833 } 3834 #else 3835 ahc = device_get_softc((device_t)platform_arg); 3836 #endif 3837 memset(ahc, 0, sizeof(*ahc)); 3838 ahc->seep_config = malloc(sizeof(*ahc->seep_config), 3839 M_DEVBUF, M_NOWAIT); 3840 if (ahc->seep_config == NULL) { 3841 #ifndef __FreeBSD__ 3842 free(ahc, M_DEVBUF); 3843 #endif 3844 free(name, M_DEVBUF); 3845 return (NULL); 3846 } 3847 LIST_INIT(&ahc->pending_scbs); 3848 /* We don't know our unit number until the OSM sets it */ 3849 ahc->name = name; 3850 ahc->unit = -1; 3851 ahc->description = NULL; 3852 ahc->channel = 'A'; 3853 ahc->channel_b = 'B'; 3854 ahc->chip = AHC_NONE; 3855 ahc->features = AHC_FENONE; 3856 ahc->bugs = AHC_BUGNONE; 3857 ahc->flags = AHC_FNONE; 3858 /* 3859 * Default to all error reporting enabled with the 3860 * sequencer operating at its fastest speed. 3861 * The bus attach code may modify this. 3862 */ 3863 ahc->seqctl = FASTMODE; 3864 3865 for (i = 0; i < AHC_NUM_TARGETS; i++) 3866 TAILQ_INIT(&ahc->untagged_queues[i]); 3867 if (ahc_platform_alloc(ahc, platform_arg) != 0) { 3868 ahc_free(ahc); 3869 ahc = NULL; 3870 } 3871 return (ahc); 3872 } 3873 3874 int 3875 ahc_softc_init(struct ahc_softc *ahc) 3876 { 3877 3878 /* The IRQMS bit is only valid on VL and EISA chips */ 3879 if ((ahc->chip & AHC_PCI) == 0) 3880 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS; 3881 else 3882 ahc->unpause = 0; 3883 ahc->pause = ahc->unpause | PAUSE; 3884 /* XXX The shared scb data stuff should be deprecated */ 3885 if (ahc->scb_data == NULL) { 3886 ahc->scb_data = malloc(sizeof(*ahc->scb_data), 3887 M_DEVBUF, M_NOWAIT); 3888 if (ahc->scb_data == NULL) 3889 return (ENOMEM); 3890 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data)); 3891 } 3892 3893 return (0); 3894 } 3895 3896 void 3897 ahc_softc_insert(struct ahc_softc *ahc) 3898 { 3899 struct ahc_softc *list_ahc; 3900 3901 #if AIC_PCI_CONFIG > 0 3902 /* 3903 * Second Function PCI devices need to inherit some 3904 * settings from function 0. 3905 */ 3906 if ((ahc->chip & AHC_BUS_MASK) == AHC_PCI 3907 && (ahc->features & AHC_MULTI_FUNC) != 0) { 3908 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) { 3909 aic_dev_softc_t list_pci; 3910 aic_dev_softc_t pci; 3911 3912 list_pci = list_ahc->dev_softc; 3913 pci = ahc->dev_softc; 3914 if (aic_get_pci_slot(list_pci) == aic_get_pci_slot(pci) 3915 && aic_get_pci_bus(list_pci) == aic_get_pci_bus(pci)) { 3916 struct ahc_softc *master; 3917 struct ahc_softc *slave; 3918 3919 if (aic_get_pci_function(list_pci) == 0) { 3920 master = list_ahc; 3921 slave = ahc; 3922 } else { 3923 master = ahc; 3924 slave = list_ahc; 3925 } 3926 slave->flags &= ~AHC_BIOS_ENABLED; 3927 slave->flags |= 3928 master->flags & AHC_BIOS_ENABLED; 3929 slave->flags &= ~AHC_PRIMARY_CHANNEL; 3930 slave->flags |= 3931 master->flags & AHC_PRIMARY_CHANNEL; 3932 break; 3933 } 3934 } 3935 } 3936 #endif 3937 3938 /* 3939 * Insertion sort into our list of softcs. 3940 */ 3941 list_ahc = TAILQ_FIRST(&ahc_tailq); 3942 while (list_ahc != NULL 3943 && ahc_softc_comp(ahc, list_ahc) <= 0) 3944 list_ahc = TAILQ_NEXT(list_ahc, links); 3945 if (list_ahc != NULL) 3946 TAILQ_INSERT_BEFORE(list_ahc, ahc, links); 3947 else 3948 TAILQ_INSERT_TAIL(&ahc_tailq, ahc, links); 3949 ahc->init_level++; 3950 } 3951 3952 /* 3953 * Verify that the passed in softc pointer is for a 3954 * controller that is still configured. 3955 */ 3956 struct ahc_softc * 3957 ahc_find_softc(struct ahc_softc *ahc) 3958 { 3959 struct ahc_softc *list_ahc; 3960 3961 TAILQ_FOREACH(list_ahc, &ahc_tailq, links) { 3962 if (list_ahc == ahc) 3963 return (ahc); 3964 } 3965 return (NULL); 3966 } 3967 3968 void 3969 ahc_set_unit(struct ahc_softc *ahc, int unit) 3970 { 3971 ahc->unit = unit; 3972 } 3973 3974 void 3975 ahc_set_name(struct ahc_softc *ahc, char *name) 3976 { 3977 if (ahc->name != NULL) 3978 free(ahc->name, M_DEVBUF); 3979 ahc->name = name; 3980 } 3981 3982 void 3983 ahc_free(struct ahc_softc *ahc) 3984 { 3985 int i; 3986 3987 ahc_terminate_recovery_thread(ahc); 3988 switch (ahc->init_level) { 3989 default: 3990 case 5: 3991 ahc_shutdown(ahc); 3992 /* FALLTHROUGH */ 3993 case 4: 3994 aic_dmamap_unload(ahc, ahc->shared_data_dmat, 3995 ahc->shared_data_dmamap); 3996 /* FALLTHROUGH */ 3997 case 3: 3998 aic_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo, 3999 ahc->shared_data_dmamap); 4000 aic_dmamap_destroy(ahc, ahc->shared_data_dmat, 4001 ahc->shared_data_dmamap); 4002 /* FALLTHROUGH */ 4003 case 2: 4004 aic_dma_tag_destroy(ahc, ahc->shared_data_dmat); 4005 case 1: 4006 #ifndef __linux__ 4007 aic_dma_tag_destroy(ahc, ahc->buffer_dmat); 4008 #endif 4009 break; 4010 case 0: 4011 break; 4012 } 4013 4014 #ifndef __linux__ 4015 aic_dma_tag_destroy(ahc, ahc->parent_dmat); 4016 #endif 4017 ahc_platform_free(ahc); 4018 ahc_fini_scbdata(ahc); 4019 for (i = 0; i < AHC_NUM_TARGETS; i++) { 4020 struct ahc_tmode_tstate *tstate; 4021 4022 tstate = ahc->enabled_targets[i]; 4023 if (tstate != NULL) { 4024 #ifdef AHC_TARGET_MODE 4025 int j; 4026 4027 for (j = 0; j < AHC_NUM_LUNS; j++) { 4028 struct ahc_tmode_lstate *lstate; 4029 4030 lstate = tstate->enabled_luns[j]; 4031 if (lstate != NULL) { 4032 xpt_free_path(lstate->path); 4033 free(lstate, M_DEVBUF); 4034 } 4035 } 4036 #endif 4037 free(tstate, M_DEVBUF); 4038 } 4039 } 4040 #ifdef AHC_TARGET_MODE 4041 if (ahc->black_hole != NULL) { 4042 xpt_free_path(ahc->black_hole->path); 4043 free(ahc->black_hole, M_DEVBUF); 4044 } 4045 #endif 4046 if (ahc->name != NULL) 4047 free(ahc->name, M_DEVBUF); 4048 if (ahc->seep_config != NULL) 4049 free(ahc->seep_config, M_DEVBUF); 4050 #ifndef __FreeBSD__ 4051 free(ahc, M_DEVBUF); 4052 #endif 4053 return; 4054 } 4055 4056 void 4057 ahc_shutdown(void *arg) 4058 { 4059 struct ahc_softc *ahc; 4060 int i; 4061 4062 ahc = (struct ahc_softc *)arg; 4063 4064 /* This will reset most registers to 0, but not all */ 4065 ahc_reset(ahc, /*reinit*/FALSE); 4066 ahc_outb(ahc, SCSISEQ, 0); 4067 ahc_outb(ahc, SXFRCTL0, 0); 4068 ahc_outb(ahc, DSPCISTATUS, 0); 4069 4070 for (i = TARG_SCSIRATE; i < SCSICONF; i++) 4071 ahc_outb(ahc, i, 0); 4072 } 4073 4074 /* 4075 * Reset the controller and record some information about it 4076 * that is only available just after a reset. If "reinit" is 4077 * non-zero, this reset occured after initial configuration 4078 * and the caller requests that the chip be fully reinitialized 4079 * to a runable state. Chip interrupts are *not* enabled after 4080 * a reinitialization. The caller must enable interrupts via 4081 * ahc_intr_enable(). 4082 */ 4083 int 4084 ahc_reset(struct ahc_softc *ahc, int reinit) 4085 { 4086 u_int sblkctl; 4087 u_int sxfrctl1_a, sxfrctl1_b; 4088 int error; 4089 int wait; 4090 4091 /* 4092 * Preserve the value of the SXFRCTL1 register for all channels. 4093 * It contains settings that affect termination and we don't want 4094 * to disturb the integrity of the bus. 4095 */ 4096 ahc_pause(ahc); 4097 sxfrctl1_b = 0; 4098 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) { 4099 u_int sblkctl; 4100 4101 /* 4102 * Save channel B's settings in case this chip 4103 * is setup for TWIN channel operation. 4104 */ 4105 sblkctl = ahc_inb(ahc, SBLKCTL); 4106 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4107 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 4108 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4109 } 4110 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 4111 4112 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 4113 4114 /* 4115 * Ensure that the reset has finished. We delay 1000us 4116 * prior to reading the register to make sure the chip 4117 * has sufficiently completed its reset to handle register 4118 * accesses. 4119 */ 4120 wait = 1000; 4121 do { 4122 aic_delay(1000); 4123 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 4124 4125 if (wait == 0) { 4126 printf("%s: WARNING - Failed chip reset! " 4127 "Trying to initialize anyway.\n", ahc_name(ahc)); 4128 } 4129 ahc_outb(ahc, HCNTRL, ahc->pause); 4130 4131 /* Determine channel configuration */ 4132 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 4133 /* No Twin Channel PCI cards */ 4134 if ((ahc->chip & AHC_PCI) != 0) 4135 sblkctl &= ~SELBUSB; 4136 switch (sblkctl) { 4137 case 0: 4138 /* Single Narrow Channel */ 4139 break; 4140 case 2: 4141 /* Wide Channel */ 4142 ahc->features |= AHC_WIDE; 4143 break; 4144 case 8: 4145 /* Twin Channel */ 4146 ahc->features |= AHC_TWIN; 4147 break; 4148 default: 4149 printf(" Unsupported adapter type. Ignoring\n"); 4150 return(-1); 4151 } 4152 4153 /* 4154 * Reload sxfrctl1. 4155 * 4156 * We must always initialize STPWEN to 1 before we 4157 * restore the saved values. STPWEN is initialized 4158 * to a tri-state condition which can only be cleared 4159 * by turning it on. 4160 */ 4161 if ((ahc->features & AHC_TWIN) != 0) { 4162 u_int sblkctl; 4163 4164 sblkctl = ahc_inb(ahc, SBLKCTL); 4165 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4166 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 4167 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4168 } 4169 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 4170 4171 error = 0; 4172 if (reinit != 0) 4173 /* 4174 * If a recovery action has forced a chip reset, 4175 * re-initialize the chip to our liking. 4176 */ 4177 error = ahc->bus_chip_init(ahc); 4178 #ifdef AHC_DUMP_SEQ 4179 else 4180 ahc_dumpseq(ahc); 4181 #endif 4182 4183 return (error); 4184 } 4185 4186 /* 4187 * Determine the number of SCBs available on the controller 4188 */ 4189 int 4190 ahc_probe_scbs(struct ahc_softc *ahc) { 4191 int i; 4192 4193 for (i = 0; i < AHC_SCB_MAX; i++) { 4194 4195 ahc_outb(ahc, SCBPTR, i); 4196 ahc_outb(ahc, SCB_BASE, i); 4197 if (ahc_inb(ahc, SCB_BASE) != i) 4198 break; 4199 ahc_outb(ahc, SCBPTR, 0); 4200 if (ahc_inb(ahc, SCB_BASE) != 0) 4201 break; 4202 } 4203 return (i); 4204 } 4205 4206 static void 4207 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4208 { 4209 bus_addr_t *baddr; 4210 4211 baddr = (bus_addr_t *)arg; 4212 *baddr = segs->ds_addr; 4213 } 4214 4215 static void 4216 ahc_build_free_scb_list(struct ahc_softc *ahc) 4217 { 4218 int scbsize; 4219 int i; 4220 4221 scbsize = 32; 4222 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0) 4223 scbsize = 64; 4224 4225 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 4226 int j; 4227 4228 ahc_outb(ahc, SCBPTR, i); 4229 4230 /* 4231 * Touch all SCB bytes to avoid parity errors 4232 * should one of our debugging routines read 4233 * an otherwise uninitiatlized byte. 4234 */ 4235 for (j = 0; j < scbsize; j++) 4236 ahc_outb(ahc, SCB_BASE+j, 0xFF); 4237 4238 /* Clear the control byte. */ 4239 ahc_outb(ahc, SCB_CONTROL, 0); 4240 4241 /* Set the next pointer */ 4242 if ((ahc->flags & AHC_PAGESCBS) != 0) 4243 ahc_outb(ahc, SCB_NEXT, i+1); 4244 else 4245 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4246 4247 /* Make the tag number, SCSIID, and lun invalid */ 4248 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 4249 ahc_outb(ahc, SCB_SCSIID, 0xFF); 4250 ahc_outb(ahc, SCB_LUN, 0xFF); 4251 } 4252 4253 if ((ahc->flags & AHC_PAGESCBS) != 0) { 4254 /* SCB 0 heads the free list. */ 4255 ahc_outb(ahc, FREE_SCBH, 0); 4256 } else { 4257 /* No free list. */ 4258 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 4259 } 4260 4261 /* Make sure that the last SCB terminates the free list */ 4262 ahc_outb(ahc, SCBPTR, i-1); 4263 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4264 } 4265 4266 static int 4267 ahc_init_scbdata(struct ahc_softc *ahc) 4268 { 4269 struct scb_data *scb_data; 4270 4271 scb_data = ahc->scb_data; 4272 SLIST_INIT(&scb_data->free_scbs); 4273 SLIST_INIT(&scb_data->sg_maps); 4274 4275 /* Allocate SCB resources */ 4276 scb_data->scbarray = 4277 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC, 4278 M_DEVBUF, M_NOWAIT); 4279 if (scb_data->scbarray == NULL) 4280 return (ENOMEM); 4281 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC); 4282 4283 /* Determine the number of hardware SCBs and initialize them */ 4284 4285 scb_data->maxhscbs = ahc_probe_scbs(ahc); 4286 if (ahc->scb_data->maxhscbs == 0) { 4287 printf("%s: No SCB space found\n", ahc_name(ahc)); 4288 return (ENXIO); 4289 } 4290 4291 /* 4292 * Create our DMA tags. These tags define the kinds of device 4293 * accessible memory allocations and memory mappings we will 4294 * need to perform during normal operation. 4295 * 4296 * Unless we need to further restrict the allocation, we rely 4297 * on the restrictions of the parent dmat, hence the common 4298 * use of MAXADDR and MAXSIZE. 4299 */ 4300 4301 /* DMA tag for our hardware scb structures */ 4302 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4303 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4304 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4305 /*highaddr*/BUS_SPACE_MAXADDR, 4306 /*filter*/NULL, /*filterarg*/NULL, 4307 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb), 4308 /*nsegments*/1, 4309 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4310 /*flags*/0, &scb_data->hscb_dmat) != 0) { 4311 goto error_exit; 4312 } 4313 4314 scb_data->init_level++; 4315 4316 /* Allocation for our hscbs */ 4317 if (aic_dmamem_alloc(ahc, scb_data->hscb_dmat, 4318 (void **)&scb_data->hscbs, 4319 BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) { 4320 goto error_exit; 4321 } 4322 4323 scb_data->init_level++; 4324 4325 /* And permanently map them */ 4326 aic_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap, 4327 scb_data->hscbs, 4328 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb), 4329 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0); 4330 4331 scb_data->init_level++; 4332 4333 /* DMA tag for our sense buffers */ 4334 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4335 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4336 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4337 /*highaddr*/BUS_SPACE_MAXADDR, 4338 /*filter*/NULL, /*filterarg*/NULL, 4339 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data), 4340 /*nsegments*/1, 4341 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4342 /*flags*/0, &scb_data->sense_dmat) != 0) { 4343 goto error_exit; 4344 } 4345 4346 scb_data->init_level++; 4347 4348 /* Allocate them */ 4349 if (aic_dmamem_alloc(ahc, scb_data->sense_dmat, 4350 (void **)&scb_data->sense, 4351 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) { 4352 goto error_exit; 4353 } 4354 4355 scb_data->init_level++; 4356 4357 /* And permanently map them */ 4358 aic_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap, 4359 scb_data->sense, 4360 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data), 4361 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0); 4362 4363 scb_data->init_level++; 4364 4365 /* DMA tag for our S/G structures. We allocate in page sized chunks */ 4366 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8, 4367 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4368 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4369 /*highaddr*/BUS_SPACE_MAXADDR, 4370 /*filter*/NULL, /*filterarg*/NULL, 4371 PAGE_SIZE, /*nsegments*/1, 4372 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4373 /*flags*/0, &scb_data->sg_dmat) != 0) { 4374 goto error_exit; 4375 } 4376 4377 scb_data->init_level++; 4378 4379 /* Perform initial CCB allocation */ 4380 memset(scb_data->hscbs, 0, 4381 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb)); 4382 ahc_alloc_scbs(ahc); 4383 4384 if (scb_data->numscbs == 0) { 4385 printf("%s: ahc_init_scbdata - " 4386 "Unable to allocate initial scbs\n", 4387 ahc_name(ahc)); 4388 goto error_exit; 4389 } 4390 4391 /* 4392 * Reserve the next queued SCB. 4393 */ 4394 ahc->next_queued_scb = ahc_get_scb(ahc); 4395 4396 /* 4397 * Note that we were successfull 4398 */ 4399 return (0); 4400 4401 error_exit: 4402 4403 return (ENOMEM); 4404 } 4405 4406 static void 4407 ahc_fini_scbdata(struct ahc_softc *ahc) 4408 { 4409 struct scb_data *scb_data; 4410 4411 scb_data = ahc->scb_data; 4412 if (scb_data == NULL) 4413 return; 4414 4415 switch (scb_data->init_level) { 4416 default: 4417 case 7: 4418 { 4419 struct sg_map_node *sg_map; 4420 4421 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 4422 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 4423 aic_dmamap_unload(ahc, scb_data->sg_dmat, 4424 sg_map->sg_dmamap); 4425 aic_dmamem_free(ahc, scb_data->sg_dmat, 4426 sg_map->sg_vaddr, 4427 sg_map->sg_dmamap); 4428 free(sg_map, M_DEVBUF); 4429 } 4430 aic_dma_tag_destroy(ahc, scb_data->sg_dmat); 4431 } 4432 case 6: 4433 aic_dmamap_unload(ahc, scb_data->sense_dmat, 4434 scb_data->sense_dmamap); 4435 case 5: 4436 aic_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense, 4437 scb_data->sense_dmamap); 4438 aic_dmamap_destroy(ahc, scb_data->sense_dmat, 4439 scb_data->sense_dmamap); 4440 case 4: 4441 aic_dma_tag_destroy(ahc, scb_data->sense_dmat); 4442 case 3: 4443 aic_dmamap_unload(ahc, scb_data->hscb_dmat, 4444 scb_data->hscb_dmamap); 4445 case 2: 4446 aic_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs, 4447 scb_data->hscb_dmamap); 4448 aic_dmamap_destroy(ahc, scb_data->hscb_dmat, 4449 scb_data->hscb_dmamap); 4450 case 1: 4451 aic_dma_tag_destroy(ahc, scb_data->hscb_dmat); 4452 break; 4453 case 0: 4454 break; 4455 } 4456 if (scb_data->scbarray != NULL) 4457 free(scb_data->scbarray, M_DEVBUF); 4458 } 4459 4460 void 4461 ahc_alloc_scbs(struct ahc_softc *ahc) 4462 { 4463 struct scb_data *scb_data; 4464 struct scb *next_scb; 4465 struct sg_map_node *sg_map; 4466 bus_addr_t physaddr; 4467 struct ahc_dma_seg *segs; 4468 int newcount; 4469 int i; 4470 4471 scb_data = ahc->scb_data; 4472 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC) 4473 /* Can't allocate any more */ 4474 return; 4475 4476 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4477 4478 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4479 4480 if (sg_map == NULL) 4481 return; 4482 4483 /* Allocate S/G space for the next batch of SCBS */ 4484 if (aic_dmamem_alloc(ahc, scb_data->sg_dmat, 4485 (void **)&sg_map->sg_vaddr, 4486 BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) { 4487 free(sg_map, M_DEVBUF); 4488 return; 4489 } 4490 4491 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4492 4493 aic_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap, 4494 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb, 4495 &sg_map->sg_physaddr, /*flags*/0); 4496 4497 segs = sg_map->sg_vaddr; 4498 physaddr = sg_map->sg_physaddr; 4499 4500 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4501 newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs)); 4502 for (i = 0; i < newcount; i++) { 4503 struct scb_platform_data *pdata; 4504 #ifndef __linux__ 4505 int error; 4506 #endif 4507 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), 4508 M_DEVBUF, M_NOWAIT); 4509 if (pdata == NULL) 4510 break; 4511 next_scb->platform_data = pdata; 4512 next_scb->sg_map = sg_map; 4513 next_scb->sg_list = segs; 4514 /* 4515 * The sequencer always starts with the second entry. 4516 * The first entry is embedded in the scb. 4517 */ 4518 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4519 next_scb->ahc_softc = ahc; 4520 next_scb->flags = SCB_FLAG_NONE; 4521 #ifndef __linux__ 4522 error = aic_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0, 4523 &next_scb->dmamap); 4524 if (error != 0) 4525 break; 4526 #endif 4527 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4528 next_scb->hscb->tag = ahc->scb_data->numscbs; 4529 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, 4530 next_scb, links.sle); 4531 segs += AHC_NSEG; 4532 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4533 next_scb++; 4534 ahc->scb_data->numscbs++; 4535 } 4536 } 4537 4538 void 4539 ahc_controller_info(struct ahc_softc *ahc, char *buf) 4540 { 4541 int len; 4542 4543 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 4544 buf += len; 4545 if ((ahc->features & AHC_TWIN) != 0) 4546 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, " 4547 "B SCSI Id=%d, primary %c, ", 4548 ahc->our_id, ahc->our_id_b, 4549 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A'); 4550 else { 4551 const char *speed; 4552 const char *type; 4553 4554 speed = ""; 4555 if ((ahc->features & AHC_ULTRA) != 0) { 4556 speed = "Ultra "; 4557 } else if ((ahc->features & AHC_DT) != 0) { 4558 speed = "Ultra160 "; 4559 } else if ((ahc->features & AHC_ULTRA2) != 0) { 4560 speed = "Ultra2 "; 4561 } 4562 if ((ahc->features & AHC_WIDE) != 0) { 4563 type = "Wide"; 4564 } else { 4565 type = "Single"; 4566 } 4567 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ", 4568 speed, type, ahc->channel, ahc->our_id); 4569 } 4570 buf += len; 4571 4572 if ((ahc->flags & AHC_PAGESCBS) != 0) 4573 sprintf(buf, "%d/%d SCBs", 4574 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE); 4575 else 4576 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs); 4577 } 4578 4579 int 4580 ahc_chip_init(struct ahc_softc *ahc) 4581 { 4582 int term; 4583 int error; 4584 u_int i; 4585 u_int scsi_conf; 4586 u_int scsiseq_template; 4587 uint32_t physaddr; 4588 4589 ahc_outb(ahc, SEQ_FLAGS, 0); 4590 ahc_outb(ahc, SEQ_FLAGS2, 0); 4591 4592 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 4593 if (ahc->features & AHC_TWIN) { 4594 4595 /* 4596 * Setup Channel B first. 4597 */ 4598 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 4599 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 4600 ahc_outb(ahc, SCSIID, ahc->our_id_b); 4601 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 4602 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4603 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN); 4604 if ((ahc->features & AHC_ULTRA2) != 0) 4605 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4606 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4607 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4608 4609 /* Select Channel A */ 4610 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 4611 } 4612 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 4613 if ((ahc->features & AHC_ULTRA2) != 0) 4614 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 4615 else 4616 ahc_outb(ahc, SCSIID, ahc->our_id); 4617 scsi_conf = ahc_inb(ahc, SCSICONF); 4618 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4619 |term|ahc->seltime 4620 |ENSTIMER|ACTNEGEN); 4621 if ((ahc->features & AHC_ULTRA2) != 0) 4622 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4623 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4624 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4625 4626 /* There are no untagged SCBs active yet. */ 4627 for (i = 0; i < 16; i++) { 4628 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0)); 4629 if ((ahc->flags & AHC_SCB_BTT) != 0) { 4630 int lun; 4631 4632 /* 4633 * The SCB based BTT allows an entry per 4634 * target and lun pair. 4635 */ 4636 for (lun = 1; lun < AHC_NUM_LUNS; lun++) 4637 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun)); 4638 } 4639 } 4640 4641 /* All of our queues are empty */ 4642 for (i = 0; i < 256; i++) 4643 ahc->qoutfifo[i] = SCB_LIST_NULL; 4644 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD); 4645 4646 for (i = 0; i < 256; i++) 4647 ahc->qinfifo[i] = SCB_LIST_NULL; 4648 4649 if ((ahc->features & AHC_MULTI_TID) != 0) { 4650 ahc_outb(ahc, TARGID, 0); 4651 ahc_outb(ahc, TARGID + 1, 0); 4652 } 4653 4654 /* 4655 * Tell the sequencer where it can find our arrays in memory. 4656 */ 4657 physaddr = ahc->scb_data->hscb_busaddr; 4658 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 4659 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 4660 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 4661 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 4662 4663 physaddr = ahc->shared_data_busaddr; 4664 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF); 4665 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF); 4666 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF); 4667 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF); 4668 4669 /* 4670 * Initialize the group code to command length table. 4671 * This overrides the values in TARG_SCSIRATE, so only 4672 * setup the table after we have processed that information. 4673 */ 4674 ahc_outb(ahc, CMDSIZE_TABLE, 5); 4675 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 4676 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 4677 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 4678 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 4679 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 4680 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 4681 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 4682 4683 if ((ahc->features & AHC_HS_MAILBOX) != 0) 4684 ahc_outb(ahc, HS_MAILBOX, 0); 4685 4686 /* Tell the sequencer of our initial queue positions */ 4687 if ((ahc->features & AHC_TARGETMODE) != 0) { 4688 ahc->tqinfifonext = 1; 4689 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1); 4690 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 4691 } 4692 ahc->qinfifonext = 0; 4693 ahc->qoutfifonext = 0; 4694 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4695 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 4696 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4697 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext); 4698 ahc_outb(ahc, SDSCB_QOFF, 0); 4699 } else { 4700 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4701 ahc_outb(ahc, QINPOS, ahc->qinfifonext); 4702 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext); 4703 } 4704 4705 /* We don't have any waiting selections */ 4706 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 4707 4708 /* Our disconnection list is empty too */ 4709 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 4710 4711 /* Message out buffer starts empty */ 4712 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 4713 4714 /* 4715 * Setup the allowed SCSI Sequences based on operational mode. 4716 * If we are a target, we'll enalbe select in operations once 4717 * we've had a lun enabled. 4718 */ 4719 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 4720 if ((ahc->flags & AHC_INITIATORROLE) != 0) 4721 scsiseq_template |= ENRSELI; 4722 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 4723 4724 /* Initialize our list of free SCBs. */ 4725 ahc_build_free_scb_list(ahc); 4726 4727 /* 4728 * Tell the sequencer which SCB will be the next one it receives. 4729 */ 4730 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 4731 4732 /* 4733 * Load the Sequencer program and Enable the adapter 4734 * in "fast" mode. 4735 */ 4736 if (bootverbose) 4737 printf("%s: Downloading Sequencer Program...", 4738 ahc_name(ahc)); 4739 4740 error = ahc_loadseq(ahc); 4741 if (error != 0) 4742 return (error); 4743 4744 if ((ahc->features & AHC_ULTRA2) != 0) { 4745 int wait; 4746 4747 /* 4748 * Wait for up to 500ms for our transceivers 4749 * to settle. If the adapter does not have 4750 * a cable attached, the transceivers may 4751 * never settle, so don't complain if we 4752 * fail here. 4753 */ 4754 for (wait = 5000; 4755 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 4756 wait--) 4757 aic_delay(100); 4758 } 4759 ahc_restart(ahc); 4760 return (0); 4761 } 4762 4763 /* 4764 * Start the board, ready for normal operation 4765 */ 4766 int 4767 ahc_init(struct ahc_softc *ahc) 4768 { 4769 int max_targ; 4770 int error; 4771 u_int i; 4772 u_int scsi_conf; 4773 u_int ultraenb; 4774 u_int discenable; 4775 u_int tagenable; 4776 size_t driver_data_size; 4777 4778 #ifdef AHC_DEBUG 4779 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0) 4780 ahc->flags |= AHC_SEQUENCER_DEBUG; 4781 #endif 4782 4783 #ifdef AHC_PRINT_SRAM 4784 printf("Scratch Ram:"); 4785 for (i = 0x20; i < 0x5f; i++) { 4786 if (((i % 8) == 0) && (i != 0)) { 4787 printf ("\n "); 4788 } 4789 printf (" 0x%x", ahc_inb(ahc, i)); 4790 } 4791 if ((ahc->features & AHC_MORE_SRAM) != 0) { 4792 for (i = 0x70; i < 0x7f; i++) { 4793 if (((i % 8) == 0) && (i != 0)) { 4794 printf ("\n "); 4795 } 4796 printf (" 0x%x", ahc_inb(ahc, i)); 4797 } 4798 } 4799 printf ("\n"); 4800 /* 4801 * Reading uninitialized scratch ram may 4802 * generate parity errors. 4803 */ 4804 ahc_outb(ahc, CLRINT, CLRPARERR); 4805 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 4806 #endif 4807 max_targ = 15; 4808 4809 /* 4810 * Assume we have a board at this stage and it has been reset. 4811 */ 4812 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 4813 ahc->our_id = ahc->our_id_b = 7; 4814 4815 /* 4816 * Default to allowing initiator operations. 4817 */ 4818 ahc->flags |= AHC_INITIATORROLE; 4819 4820 /* 4821 * Only allow target mode features if this unit has them enabled. 4822 */ 4823 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0) 4824 ahc->features &= ~AHC_TARGETMODE; 4825 4826 #ifndef __linux__ 4827 /* DMA tag for mapping buffers into device visible space. */ 4828 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4829 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4830 /*lowaddr*/ahc->flags & AHC_39BIT_ADDRESSING 4831 ? (bus_addr_t)0x7FFFFFFFFFULL 4832 : BUS_SPACE_MAXADDR_32BIT, 4833 /*highaddr*/BUS_SPACE_MAXADDR, 4834 /*filter*/NULL, /*filterarg*/NULL, 4835 /*maxsize*/(AHC_NSEG - 1) * PAGE_SIZE, 4836 /*nsegments*/AHC_NSEG, 4837 /*maxsegsz*/AHC_MAXTRANSFER_SIZE, 4838 /*flags*/BUS_DMA_ALLOCNOW, 4839 &ahc->buffer_dmat) != 0) { 4840 return (ENOMEM); 4841 } 4842 #endif 4843 4844 ahc->init_level++; 4845 4846 /* 4847 * DMA tag for our command fifos and other data in system memory 4848 * the card's sequencer must be able to access. For initiator 4849 * roles, we need to allocate space for the qinfifo and qoutfifo. 4850 * The qinfifo and qoutfifo are composed of 256 1 byte elements. 4851 * When providing for the target mode role, we must additionally 4852 * provide space for the incoming target command fifo and an extra 4853 * byte to deal with a dma bug in some chip versions. 4854 */ 4855 driver_data_size = 2 * 256 * sizeof(uint8_t); 4856 if ((ahc->features & AHC_TARGETMODE) != 0) 4857 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd) 4858 + /*DMA WideOdd Bug Buffer*/1; 4859 if (aic_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4860 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4861 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4862 /*highaddr*/BUS_SPACE_MAXADDR, 4863 /*filter*/NULL, /*filterarg*/NULL, 4864 driver_data_size, 4865 /*nsegments*/1, 4866 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4867 /*flags*/0, &ahc->shared_data_dmat) != 0) { 4868 return (ENOMEM); 4869 } 4870 4871 ahc->init_level++; 4872 4873 /* Allocation of driver data */ 4874 if (aic_dmamem_alloc(ahc, ahc->shared_data_dmat, 4875 (void **)&ahc->qoutfifo, 4876 BUS_DMA_NOWAIT, &ahc->shared_data_dmamap) != 0) { 4877 return (ENOMEM); 4878 } 4879 4880 ahc->init_level++; 4881 4882 /* And permanently map it in */ 4883 aic_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap, 4884 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb, 4885 &ahc->shared_data_busaddr, /*flags*/0); 4886 4887 if ((ahc->features & AHC_TARGETMODE) != 0) { 4888 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo; 4889 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS]; 4890 ahc->dma_bug_buf = ahc->shared_data_busaddr 4891 + driver_data_size - 1; 4892 /* All target command blocks start out invalid. */ 4893 for (i = 0; i < AHC_TMODE_CMDS; i++) 4894 ahc->targetcmds[i].cmd_valid = 0; 4895 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD); 4896 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256]; 4897 } 4898 ahc->qinfifo = &ahc->qoutfifo[256]; 4899 4900 ahc->init_level++; 4901 4902 /* Allocate SCB data now that buffer_dmat is initialized */ 4903 if (ahc->scb_data->maxhscbs == 0) 4904 if (ahc_init_scbdata(ahc) != 0) 4905 return (ENOMEM); 4906 4907 /* 4908 * Allocate a tstate to house information for our 4909 * initiator presence on the bus as well as the user 4910 * data for any target mode initiator. 4911 */ 4912 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 4913 printf("%s: unable to allocate ahc_tmode_tstate. " 4914 "Failing attach\n", ahc_name(ahc)); 4915 return (ENOMEM); 4916 } 4917 4918 if ((ahc->features & AHC_TWIN) != 0) { 4919 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 4920 printf("%s: unable to allocate ahc_tmode_tstate. " 4921 "Failing attach\n", ahc_name(ahc)); 4922 return (ENOMEM); 4923 } 4924 } 4925 4926 /* 4927 * Fire up a recovery thread for this controller. 4928 */ 4929 error = ahc_spawn_recovery_thread(ahc); 4930 if (error != 0) 4931 return (error); 4932 4933 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) { 4934 ahc->flags |= AHC_PAGESCBS; 4935 } else { 4936 ahc->flags &= ~AHC_PAGESCBS; 4937 } 4938 4939 #ifdef AHC_DEBUG 4940 if (ahc_debug & AHC_SHOW_MISC) { 4941 printf("%s: hardware scb %u bytes; kernel scb %u bytes; " 4942 "ahc_dma %u bytes\n", 4943 ahc_name(ahc), 4944 (u_int)sizeof(struct hardware_scb), 4945 (u_int)sizeof(struct scb), 4946 (u_int)sizeof(struct ahc_dma_seg)); 4947 } 4948 #endif /* AHC_DEBUG */ 4949 4950 /* 4951 * Look at the information that board initialization or 4952 * the board bios has left us. 4953 */ 4954 if (ahc->features & AHC_TWIN) { 4955 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 4956 if ((scsi_conf & RESET_SCSI) != 0 4957 && (ahc->flags & AHC_INITIATORROLE) != 0) 4958 ahc->flags |= AHC_RESET_BUS_B; 4959 } 4960 4961 scsi_conf = ahc_inb(ahc, SCSICONF); 4962 if ((scsi_conf & RESET_SCSI) != 0 4963 && (ahc->flags & AHC_INITIATORROLE) != 0) 4964 ahc->flags |= AHC_RESET_BUS_A; 4965 4966 ultraenb = 0; 4967 tagenable = ALL_TARGETS_MASK; 4968 4969 /* Grab the disconnection disable table and invert it for our needs */ 4970 if ((ahc->flags & AHC_USEDEFAULTS) != 0) { 4971 printf("%s: Host Adapter Bios disabled. Using default SCSI " 4972 "device parameters\n", ahc_name(ahc)); 4973 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 4974 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 4975 discenable = ALL_TARGETS_MASK; 4976 if ((ahc->features & AHC_ULTRA) != 0) 4977 ultraenb = ALL_TARGETS_MASK; 4978 } else { 4979 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 4980 | ahc_inb(ahc, DISC_DSB)); 4981 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 4982 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 4983 | ahc_inb(ahc, ULTRA_ENB); 4984 } 4985 4986 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 4987 max_targ = 7; 4988 4989 for (i = 0; i <= max_targ; i++) { 4990 struct ahc_initiator_tinfo *tinfo; 4991 struct ahc_tmode_tstate *tstate; 4992 u_int our_id; 4993 u_int target_id; 4994 char channel; 4995 4996 channel = 'A'; 4997 our_id = ahc->our_id; 4998 target_id = i; 4999 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 5000 channel = 'B'; 5001 our_id = ahc->our_id_b; 5002 target_id = i % 8; 5003 } 5004 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 5005 target_id, &tstate); 5006 /* Default to async narrow across the board */ 5007 memset(tinfo, 0, sizeof(*tinfo)); 5008 if (ahc->flags & AHC_USEDEFAULTS) { 5009 if ((ahc->features & AHC_WIDE) != 0) 5010 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 5011 5012 /* 5013 * These will be truncated when we determine the 5014 * connection type we have with the target. 5015 */ 5016 tinfo->user.period = ahc_syncrates->period; 5017 tinfo->user.offset = MAX_OFFSET; 5018 } else { 5019 u_int scsirate; 5020 uint16_t mask; 5021 5022 /* Take the settings leftover in scratch RAM. */ 5023 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 5024 mask = (0x01 << i); 5025 if ((ahc->features & AHC_ULTRA2) != 0) { 5026 u_int offset; 5027 u_int maxsync; 5028 5029 if ((scsirate & SOFS) == 0x0F) { 5030 /* 5031 * Haven't negotiated yet, 5032 * so the format is different. 5033 */ 5034 scsirate = (scsirate & SXFR) >> 4 5035 | (ultraenb & mask) 5036 ? 0x08 : 0x0 5037 | (scsirate & WIDEXFER); 5038 offset = MAX_OFFSET_ULTRA2; 5039 } else 5040 offset = ahc_inb(ahc, TARG_OFFSET + i); 5041 if ((scsirate & ~WIDEXFER) == 0 && offset != 0) 5042 /* Set to the lowest sync rate, 5MHz */ 5043 scsirate |= 0x1c; 5044 maxsync = AHC_SYNCRATE_ULTRA2; 5045 if ((ahc->features & AHC_DT) != 0) 5046 maxsync = AHC_SYNCRATE_DT; 5047 tinfo->user.period = 5048 ahc_find_period(ahc, scsirate, maxsync); 5049 if (offset == 0) 5050 tinfo->user.period = 0; 5051 else 5052 tinfo->user.offset = MAX_OFFSET; 5053 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/ 5054 && (ahc->features & AHC_DT) != 0) 5055 tinfo->user.ppr_options = 5056 MSG_EXT_PPR_DT_REQ; 5057 } else if ((scsirate & SOFS) != 0) { 5058 if ((scsirate & SXFR) == 0x40 5059 && (ultraenb & mask) != 0) { 5060 /* Treat 10MHz as a non-ultra speed */ 5061 scsirate &= ~SXFR; 5062 ultraenb &= ~mask; 5063 } 5064 tinfo->user.period = 5065 ahc_find_period(ahc, scsirate, 5066 (ultraenb & mask) 5067 ? AHC_SYNCRATE_ULTRA 5068 : AHC_SYNCRATE_FAST); 5069 if (tinfo->user.period != 0) 5070 tinfo->user.offset = MAX_OFFSET; 5071 } 5072 if (tinfo->user.period == 0) 5073 tinfo->user.offset = 0; 5074 if ((scsirate & WIDEXFER) != 0 5075 && (ahc->features & AHC_WIDE) != 0) 5076 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 5077 tinfo->user.protocol_version = 4; 5078 if ((ahc->features & AHC_DT) != 0) 5079 tinfo->user.transport_version = 3; 5080 else 5081 tinfo->user.transport_version = 2; 5082 tinfo->goal.protocol_version = 2; 5083 tinfo->goal.transport_version = 2; 5084 tinfo->curr.protocol_version = 2; 5085 tinfo->curr.transport_version = 2; 5086 } 5087 tstate->ultraenb = 0; 5088 } 5089 ahc->user_discenable = discenable; 5090 ahc->user_tagenable = tagenable; 5091 5092 return (ahc->bus_chip_init(ahc)); 5093 } 5094 5095 void 5096 ahc_intr_enable(struct ahc_softc *ahc, int enable) 5097 { 5098 u_int hcntrl; 5099 5100 hcntrl = ahc_inb(ahc, HCNTRL); 5101 hcntrl &= ~INTEN; 5102 ahc->pause &= ~INTEN; 5103 ahc->unpause &= ~INTEN; 5104 if (enable) { 5105 hcntrl |= INTEN; 5106 ahc->pause |= INTEN; 5107 ahc->unpause |= INTEN; 5108 } 5109 ahc_outb(ahc, HCNTRL, hcntrl); 5110 } 5111 5112 /* 5113 * Ensure that the card is paused in a location 5114 * outside of all critical sections and that all 5115 * pending work is completed prior to returning. 5116 * This routine should only be called from outside 5117 * an interrupt context. 5118 */ 5119 void 5120 ahc_pause_and_flushwork(struct ahc_softc *ahc) 5121 { 5122 int intstat; 5123 int maxloops; 5124 int paused; 5125 5126 maxloops = 1000; 5127 ahc->flags |= AHC_ALL_INTERRUPTS; 5128 paused = FALSE; 5129 do { 5130 if (paused) { 5131 ahc_unpause(ahc); 5132 /* 5133 * Give the sequencer some time to service 5134 * any active selections. 5135 */ 5136 aic_delay(500); 5137 } 5138 ahc_intr(ahc); 5139 ahc_pause(ahc); 5140 paused = TRUE; 5141 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO); 5142 intstat = ahc_inb(ahc, INTSTAT); 5143 if ((intstat & INT_PEND) == 0) { 5144 ahc_clear_critical_section(ahc); 5145 intstat = ahc_inb(ahc, INTSTAT); 5146 } 5147 } while (--maxloops 5148 && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0) 5149 && ((intstat & INT_PEND) != 0 5150 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0)); 5151 if (maxloops == 0) { 5152 printf("Infinite interrupt loop, INTSTAT = %x", 5153 ahc_inb(ahc, INTSTAT)); 5154 } 5155 ahc_platform_flushwork(ahc); 5156 ahc->flags &= ~AHC_ALL_INTERRUPTS; 5157 } 5158 5159 int 5160 ahc_suspend(struct ahc_softc *ahc) 5161 { 5162 5163 ahc_pause_and_flushwork(ahc); 5164 5165 if (LIST_FIRST(&ahc->pending_scbs) != NULL) { 5166 ahc_unpause(ahc); 5167 return (EBUSY); 5168 } 5169 5170 #ifdef AHC_TARGET_MODE 5171 /* 5172 * XXX What about ATIOs that have not yet been serviced? 5173 * Perhaps we should just refuse to be suspended if we 5174 * are acting in a target role. 5175 */ 5176 if (ahc->pending_device != NULL) { 5177 ahc_unpause(ahc); 5178 return (EBUSY); 5179 } 5180 #endif 5181 ahc_shutdown(ahc); 5182 return (0); 5183 } 5184 5185 int 5186 ahc_resume(struct ahc_softc *ahc) 5187 { 5188 5189 ahc_reset(ahc, /*reinit*/TRUE); 5190 ahc_intr_enable(ahc, TRUE); 5191 ahc_restart(ahc); 5192 return (0); 5193 } 5194 5195 /************************** Busy Target Table *********************************/ 5196 /* 5197 * Return the untagged transaction id for a given target/channel lun. 5198 * Optionally, clear the entry. 5199 */ 5200 u_int 5201 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl) 5202 { 5203 u_int scbid; 5204 u_int target_offset; 5205 5206 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5207 u_int saved_scbptr; 5208 5209 saved_scbptr = ahc_inb(ahc, SCBPTR); 5210 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5211 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl)); 5212 ahc_outb(ahc, SCBPTR, saved_scbptr); 5213 } else { 5214 target_offset = TCL_TARGET_OFFSET(tcl); 5215 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset); 5216 } 5217 5218 return (scbid); 5219 } 5220 5221 void 5222 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl) 5223 { 5224 u_int target_offset; 5225 5226 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5227 u_int saved_scbptr; 5228 5229 saved_scbptr = ahc_inb(ahc, SCBPTR); 5230 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5231 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL); 5232 ahc_outb(ahc, SCBPTR, saved_scbptr); 5233 } else { 5234 target_offset = TCL_TARGET_OFFSET(tcl); 5235 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL); 5236 } 5237 } 5238 5239 void 5240 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid) 5241 { 5242 u_int target_offset; 5243 5244 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5245 u_int saved_scbptr; 5246 5247 saved_scbptr = ahc_inb(ahc, SCBPTR); 5248 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5249 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid); 5250 ahc_outb(ahc, SCBPTR, saved_scbptr); 5251 } else { 5252 target_offset = TCL_TARGET_OFFSET(tcl); 5253 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid); 5254 } 5255 } 5256 5257 /************************** SCB and SCB queue management **********************/ 5258 int 5259 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target, 5260 char channel, int lun, u_int tag, role_t role) 5261 { 5262 int targ = SCB_GET_TARGET(ahc, scb); 5263 char chan = SCB_GET_CHANNEL(ahc, scb); 5264 int slun = SCB_GET_LUN(scb); 5265 int match; 5266 5267 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5268 if (match != 0) 5269 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 5270 if (match != 0) 5271 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 5272 if (match != 0) { 5273 #ifdef AHC_TARGET_MODE 5274 int group; 5275 5276 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 5277 if (role == ROLE_INITIATOR) { 5278 match = (group != XPT_FC_GROUP_TMODE) 5279 && ((tag == scb->hscb->tag) 5280 || (tag == SCB_LIST_NULL)); 5281 } else if (role == ROLE_TARGET) { 5282 match = (group == XPT_FC_GROUP_TMODE) 5283 && ((tag == scb->io_ctx->csio.tag_id) 5284 || (tag == SCB_LIST_NULL)); 5285 } 5286 #else /* !AHC_TARGET_MODE */ 5287 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL)); 5288 #endif /* AHC_TARGET_MODE */ 5289 } 5290 5291 return match; 5292 } 5293 5294 void 5295 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb) 5296 { 5297 int target; 5298 char channel; 5299 int lun; 5300 5301 target = SCB_GET_TARGET(ahc, scb); 5302 lun = SCB_GET_LUN(scb); 5303 channel = SCB_GET_CHANNEL(ahc, scb); 5304 5305 ahc_search_qinfifo(ahc, target, channel, lun, 5306 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 5307 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5308 5309 ahc_platform_freeze_devq(ahc, scb); 5310 } 5311 5312 void 5313 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb) 5314 { 5315 struct scb *prev_scb; 5316 5317 prev_scb = NULL; 5318 if (ahc_qinfifo_count(ahc) != 0) { 5319 u_int prev_tag; 5320 uint8_t prev_pos; 5321 5322 prev_pos = ahc->qinfifonext - 1; 5323 prev_tag = ahc->qinfifo[prev_pos]; 5324 prev_scb = ahc_lookup_scb(ahc, prev_tag); 5325 } 5326 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5327 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5328 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5329 } else { 5330 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5331 } 5332 } 5333 5334 static void 5335 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb, 5336 struct scb *scb) 5337 { 5338 if (prev_scb == NULL) { 5339 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5340 } else { 5341 prev_scb->hscb->next = scb->hscb->tag; 5342 ahc_sync_scb(ahc, prev_scb, 5343 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5344 } 5345 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 5346 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5347 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5348 } 5349 5350 static int 5351 ahc_qinfifo_count(struct ahc_softc *ahc) 5352 { 5353 uint8_t qinpos; 5354 uint8_t diff; 5355 5356 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5357 qinpos = ahc_inb(ahc, SNSCB_QOFF); 5358 ahc_outb(ahc, SNSCB_QOFF, qinpos); 5359 } else 5360 qinpos = ahc_inb(ahc, QINPOS); 5361 diff = ahc->qinfifonext - qinpos; 5362 return (diff); 5363 } 5364 5365 int 5366 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 5367 int lun, u_int tag, role_t role, uint32_t status, 5368 ahc_search_action action) 5369 { 5370 struct scb *scb; 5371 struct scb *prev_scb; 5372 uint8_t qinstart; 5373 uint8_t qinpos; 5374 uint8_t qintail; 5375 uint8_t next; 5376 uint8_t prev; 5377 uint8_t curscbptr; 5378 int found; 5379 int have_qregs; 5380 5381 qintail = ahc->qinfifonext; 5382 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0; 5383 if (have_qregs) { 5384 qinstart = ahc_inb(ahc, SNSCB_QOFF); 5385 ahc_outb(ahc, SNSCB_QOFF, qinstart); 5386 } else 5387 qinstart = ahc_inb(ahc, QINPOS); 5388 qinpos = qinstart; 5389 found = 0; 5390 prev_scb = NULL; 5391 5392 if (action == SEARCH_COMPLETE) { 5393 /* 5394 * Don't attempt to run any queued untagged transactions 5395 * until we are done with the abort process. 5396 */ 5397 ahc_freeze_untagged_queues(ahc); 5398 } 5399 5400 /* 5401 * Start with an empty queue. Entries that are not chosen 5402 * for removal will be re-added to the queue as we go. 5403 */ 5404 ahc->qinfifonext = qinpos; 5405 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 5406 5407 while (qinpos != qintail) { 5408 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]); 5409 if (scb == NULL) { 5410 printf("qinpos = %d, SCB index = %d\n", 5411 qinpos, ahc->qinfifo[qinpos]); 5412 panic("Loop 1\n"); 5413 } 5414 5415 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) { 5416 /* 5417 * We found an scb that needs to be acted on. 5418 */ 5419 found++; 5420 switch (action) { 5421 case SEARCH_COMPLETE: 5422 { 5423 cam_status ostat; 5424 cam_status cstat; 5425 5426 ostat = aic_get_transaction_status(scb); 5427 if (ostat == CAM_REQ_INPROG) 5428 aic_set_transaction_status(scb, status); 5429 cstat = aic_get_transaction_status(scb); 5430 if (cstat != CAM_REQ_CMP) 5431 aic_freeze_scb(scb); 5432 if ((scb->flags & SCB_ACTIVE) == 0) 5433 printf("Inactive SCB in qinfifo\n"); 5434 ahc_done(ahc, scb); 5435 5436 /* FALLTHROUGH */ 5437 } 5438 case SEARCH_REMOVE: 5439 break; 5440 case SEARCH_COUNT: 5441 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5442 prev_scb = scb; 5443 break; 5444 } 5445 } else { 5446 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5447 prev_scb = scb; 5448 } 5449 qinpos++; 5450 } 5451 5452 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5453 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5454 } else { 5455 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5456 } 5457 5458 if (action != SEARCH_COUNT 5459 && (found != 0) 5460 && (qinstart != ahc->qinfifonext)) { 5461 /* 5462 * The sequencer may be in the process of dmaing 5463 * down the SCB at the beginning of the queue. 5464 * This could be problematic if either the first, 5465 * or the second SCB is removed from the queue 5466 * (the first SCB includes a pointer to the "next" 5467 * SCB to dma). If we have removed any entries, swap 5468 * the first element in the queue with the next HSCB 5469 * so the sequencer will notice that NEXT_QUEUED_SCB 5470 * has changed during its dma attempt and will retry 5471 * the DMA. 5472 */ 5473 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]); 5474 5475 if (scb == NULL) { 5476 printf("found = %d, qinstart = %d, qinfifionext = %d\n", 5477 found, qinstart, ahc->qinfifonext); 5478 panic("First/Second Qinfifo fixup\n"); 5479 } 5480 /* 5481 * ahc_swap_with_next_hscb forces our next pointer to 5482 * point to the reserved SCB for future commands. Save 5483 * and restore our original next pointer to maintain 5484 * queue integrity. 5485 */ 5486 next = scb->hscb->next; 5487 ahc->scb_data->scbindex[scb->hscb->tag] = NULL; 5488 ahc_swap_with_next_hscb(ahc, scb); 5489 scb->hscb->next = next; 5490 ahc->qinfifo[qinstart] = scb->hscb->tag; 5491 5492 /* Tell the card about the new head of the qinfifo. */ 5493 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5494 5495 /* Fixup the tail "next" pointer. */ 5496 qintail = ahc->qinfifonext - 1; 5497 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]); 5498 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5499 } 5500 5501 /* 5502 * Search waiting for selection list. 5503 */ 5504 curscbptr = ahc_inb(ahc, SCBPTR); 5505 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 5506 prev = SCB_LIST_NULL; 5507 5508 while (next != SCB_LIST_NULL) { 5509 uint8_t scb_index; 5510 5511 ahc_outb(ahc, SCBPTR, next); 5512 scb_index = ahc_inb(ahc, SCB_TAG); 5513 if (scb_index >= ahc->scb_data->numscbs) { 5514 printf("Waiting List inconsistency. " 5515 "SCB index == %d, yet numscbs == %d.", 5516 scb_index, ahc->scb_data->numscbs); 5517 ahc_dump_card_state(ahc); 5518 panic("for safety"); 5519 } 5520 scb = ahc_lookup_scb(ahc, scb_index); 5521 if (scb == NULL) { 5522 printf("scb_index = %d, next = %d\n", 5523 scb_index, next); 5524 panic("Waiting List traversal\n"); 5525 } 5526 if (ahc_match_scb(ahc, scb, target, channel, 5527 lun, SCB_LIST_NULL, role)) { 5528 /* 5529 * We found an scb that needs to be acted on. 5530 */ 5531 found++; 5532 switch (action) { 5533 case SEARCH_COMPLETE: 5534 { 5535 cam_status ostat; 5536 cam_status cstat; 5537 5538 ostat = aic_get_transaction_status(scb); 5539 if (ostat == CAM_REQ_INPROG) 5540 aic_set_transaction_status(scb, 5541 status); 5542 cstat = aic_get_transaction_status(scb); 5543 if (cstat != CAM_REQ_CMP) 5544 aic_freeze_scb(scb); 5545 if ((scb->flags & SCB_ACTIVE) == 0) 5546 printf("Inactive SCB in Wait List\n"); 5547 ahc_done(ahc, scb); 5548 /* FALLTHROUGH */ 5549 } 5550 case SEARCH_REMOVE: 5551 next = ahc_rem_wscb(ahc, next, prev); 5552 break; 5553 case SEARCH_COUNT: 5554 prev = next; 5555 next = ahc_inb(ahc, SCB_NEXT); 5556 break; 5557 } 5558 } else { 5559 5560 prev = next; 5561 next = ahc_inb(ahc, SCB_NEXT); 5562 } 5563 } 5564 ahc_outb(ahc, SCBPTR, curscbptr); 5565 5566 found += ahc_search_untagged_queues(ahc, /*aic_io_ctx_t*/NULL, target, 5567 channel, lun, status, action); 5568 5569 if (action == SEARCH_COMPLETE) 5570 ahc_release_untagged_queues(ahc); 5571 return (found); 5572 } 5573 5574 int 5575 ahc_search_untagged_queues(struct ahc_softc *ahc, aic_io_ctx_t ctx, 5576 int target, char channel, int lun, uint32_t status, 5577 ahc_search_action action) 5578 { 5579 struct scb *scb; 5580 int maxtarget; 5581 int found; 5582 int i; 5583 5584 if (action == SEARCH_COMPLETE) { 5585 /* 5586 * Don't attempt to run any queued untagged transactions 5587 * until we are done with the abort process. 5588 */ 5589 ahc_freeze_untagged_queues(ahc); 5590 } 5591 5592 found = 0; 5593 i = 0; 5594 if ((ahc->flags & AHC_SCB_BTT) == 0) { 5595 5596 maxtarget = 16; 5597 if (target != CAM_TARGET_WILDCARD) { 5598 5599 i = target; 5600 if (channel == 'B') 5601 i += 8; 5602 maxtarget = i + 1; 5603 } 5604 } else { 5605 maxtarget = 0; 5606 } 5607 5608 for (; i < maxtarget; i++) { 5609 struct scb_tailq *untagged_q; 5610 struct scb *next_scb; 5611 5612 untagged_q = &(ahc->untagged_queues[i]); 5613 next_scb = TAILQ_FIRST(untagged_q); 5614 while (next_scb != NULL) { 5615 5616 scb = next_scb; 5617 next_scb = TAILQ_NEXT(scb, links.tqe); 5618 5619 /* 5620 * The head of the list may be the currently 5621 * active untagged command for a device. 5622 * We're only searching for commands that 5623 * have not been started. A transaction 5624 * marked active but still in the qinfifo 5625 * is removed by the qinfifo scanning code 5626 * above. 5627 */ 5628 if ((scb->flags & SCB_ACTIVE) != 0) 5629 continue; 5630 5631 if (ahc_match_scb(ahc, scb, target, channel, lun, 5632 SCB_LIST_NULL, ROLE_INITIATOR) == 0 5633 || (ctx != NULL && ctx != scb->io_ctx)) 5634 continue; 5635 5636 /* 5637 * We found an scb that needs to be acted on. 5638 */ 5639 found++; 5640 switch (action) { 5641 case SEARCH_COMPLETE: 5642 { 5643 cam_status ostat; 5644 cam_status cstat; 5645 5646 ostat = aic_get_transaction_status(scb); 5647 if (ostat == CAM_REQ_INPROG) 5648 aic_set_transaction_status(scb, status); 5649 cstat = aic_get_transaction_status(scb); 5650 if (cstat != CAM_REQ_CMP) 5651 aic_freeze_scb(scb); 5652 ahc_done(ahc, scb); 5653 break; 5654 } 5655 case SEARCH_REMOVE: 5656 scb->flags &= ~SCB_UNTAGGEDQ; 5657 TAILQ_REMOVE(untagged_q, scb, links.tqe); 5658 break; 5659 case SEARCH_COUNT: 5660 break; 5661 } 5662 } 5663 } 5664 5665 if (action == SEARCH_COMPLETE) 5666 ahc_release_untagged_queues(ahc); 5667 return (found); 5668 } 5669 5670 int 5671 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5672 int lun, u_int tag, int stop_on_first, int remove, 5673 int save_state) 5674 { 5675 struct scb *scbp; 5676 u_int next; 5677 u_int prev; 5678 u_int count; 5679 u_int active_scb; 5680 5681 count = 0; 5682 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5683 prev = SCB_LIST_NULL; 5684 5685 if (save_state) { 5686 /* restore this when we're done */ 5687 active_scb = ahc_inb(ahc, SCBPTR); 5688 } else 5689 /* Silence compiler */ 5690 active_scb = SCB_LIST_NULL; 5691 5692 while (next != SCB_LIST_NULL) { 5693 u_int scb_index; 5694 5695 ahc_outb(ahc, SCBPTR, next); 5696 scb_index = ahc_inb(ahc, SCB_TAG); 5697 if (scb_index >= ahc->scb_data->numscbs) { 5698 printf("Disconnected List inconsistency. " 5699 "SCB index == %d, yet numscbs == %d.", 5700 scb_index, ahc->scb_data->numscbs); 5701 ahc_dump_card_state(ahc); 5702 panic("for safety"); 5703 } 5704 5705 if (next == prev) { 5706 panic("Disconnected List Loop. " 5707 "cur SCBPTR == %x, prev SCBPTR == %x.", 5708 next, prev); 5709 } 5710 scbp = ahc_lookup_scb(ahc, scb_index); 5711 if (ahc_match_scb(ahc, scbp, target, channel, lun, 5712 tag, ROLE_INITIATOR)) { 5713 count++; 5714 if (remove) { 5715 next = 5716 ahc_rem_scb_from_disc_list(ahc, prev, next); 5717 } else { 5718 prev = next; 5719 next = ahc_inb(ahc, SCB_NEXT); 5720 } 5721 if (stop_on_first) 5722 break; 5723 } else { 5724 prev = next; 5725 next = ahc_inb(ahc, SCB_NEXT); 5726 } 5727 } 5728 if (save_state) 5729 ahc_outb(ahc, SCBPTR, active_scb); 5730 return (count); 5731 } 5732 5733 /* 5734 * Remove an SCB from the on chip list of disconnected transactions. 5735 * This is empty/unused if we are not performing SCB paging. 5736 */ 5737 static u_int 5738 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5739 { 5740 u_int next; 5741 5742 ahc_outb(ahc, SCBPTR, scbptr); 5743 next = ahc_inb(ahc, SCB_NEXT); 5744 5745 ahc_outb(ahc, SCB_CONTROL, 0); 5746 5747 ahc_add_curscb_to_free_list(ahc); 5748 5749 if (prev != SCB_LIST_NULL) { 5750 ahc_outb(ahc, SCBPTR, prev); 5751 ahc_outb(ahc, SCB_NEXT, next); 5752 } else 5753 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5754 5755 return (next); 5756 } 5757 5758 /* 5759 * Add the SCB as selected by SCBPTR onto the on chip list of 5760 * free hardware SCBs. This list is empty/unused if we are not 5761 * performing SCB paging. 5762 */ 5763 static void 5764 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5765 { 5766 /* 5767 * Invalidate the tag so that our abort 5768 * routines don't think it's active. 5769 */ 5770 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5771 5772 if ((ahc->flags & AHC_PAGESCBS) != 0) { 5773 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5774 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5775 } 5776 } 5777 5778 /* 5779 * Manipulate the waiting for selection list and return the 5780 * scb that follows the one that we remove. 5781 */ 5782 static u_int 5783 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5784 { 5785 u_int curscb, next; 5786 5787 /* 5788 * Select the SCB we want to abort and 5789 * pull the next pointer out of it. 5790 */ 5791 curscb = ahc_inb(ahc, SCBPTR); 5792 ahc_outb(ahc, SCBPTR, scbpos); 5793 next = ahc_inb(ahc, SCB_NEXT); 5794 5795 /* Clear the necessary fields */ 5796 ahc_outb(ahc, SCB_CONTROL, 0); 5797 5798 ahc_add_curscb_to_free_list(ahc); 5799 5800 /* update the waiting list */ 5801 if (prev == SCB_LIST_NULL) { 5802 /* First in the list */ 5803 ahc_outb(ahc, WAITING_SCBH, next); 5804 5805 /* 5806 * Ensure we aren't attempting to perform 5807 * selection for this entry. 5808 */ 5809 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5810 } else { 5811 /* 5812 * Select the scb that pointed to us 5813 * and update its next pointer. 5814 */ 5815 ahc_outb(ahc, SCBPTR, prev); 5816 ahc_outb(ahc, SCB_NEXT, next); 5817 } 5818 5819 /* 5820 * Point us back at the original scb position. 5821 */ 5822 ahc_outb(ahc, SCBPTR, curscb); 5823 return next; 5824 } 5825 5826 /******************************** Error Handling ******************************/ 5827 /* 5828 * Abort all SCBs that match the given description (target/channel/lun/tag), 5829 * setting their status to the passed in status if the status has not already 5830 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 5831 * is paused before it is called. 5832 */ 5833 int 5834 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 5835 int lun, u_int tag, role_t role, uint32_t status) 5836 { 5837 struct scb *scbp; 5838 struct scb *scbp_next; 5839 u_int active_scb; 5840 int i, j; 5841 int maxtarget; 5842 int minlun; 5843 int maxlun; 5844 5845 int found; 5846 5847 /* 5848 * Don't attempt to run any queued untagged transactions 5849 * until we are done with the abort process. 5850 */ 5851 ahc_freeze_untagged_queues(ahc); 5852 5853 /* restore this when we're done */ 5854 active_scb = ahc_inb(ahc, SCBPTR); 5855 5856 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 5857 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5858 5859 /* 5860 * Clean out the busy target table for any untagged commands. 5861 */ 5862 i = 0; 5863 maxtarget = 16; 5864 if (target != CAM_TARGET_WILDCARD) { 5865 i = target; 5866 if (channel == 'B') 5867 i += 8; 5868 maxtarget = i + 1; 5869 } 5870 5871 if (lun == CAM_LUN_WILDCARD) { 5872 5873 /* 5874 * Unless we are using an SCB based 5875 * busy targets table, there is only 5876 * one table entry for all luns of 5877 * a target. 5878 */ 5879 minlun = 0; 5880 maxlun = 1; 5881 if ((ahc->flags & AHC_SCB_BTT) != 0) 5882 maxlun = AHC_NUM_LUNS; 5883 } else { 5884 minlun = lun; 5885 maxlun = lun + 1; 5886 } 5887 5888 if (role != ROLE_TARGET) { 5889 for (;i < maxtarget; i++) { 5890 for (j = minlun;j < maxlun; j++) { 5891 u_int scbid; 5892 u_int tcl; 5893 5894 tcl = BUILD_TCL(i << 4, j); 5895 scbid = ahc_index_busy_tcl(ahc, tcl); 5896 scbp = ahc_lookup_scb(ahc, scbid); 5897 if (scbp == NULL 5898 || ahc_match_scb(ahc, scbp, target, channel, 5899 lun, tag, role) == 0) 5900 continue; 5901 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j)); 5902 } 5903 } 5904 5905 /* 5906 * Go through the disconnected list and remove any entries we 5907 * have queued for completion, 0'ing their control byte too. 5908 * We save the active SCB and restore it ourselves, so there 5909 * is no reason for this search to restore it too. 5910 */ 5911 ahc_search_disc_list(ahc, target, channel, lun, tag, 5912 /*stop_on_first*/FALSE, /*remove*/TRUE, 5913 /*save_state*/FALSE); 5914 } 5915 5916 /* 5917 * Go through the hardware SCB array looking for commands that 5918 * were active but not on any list. In some cases, these remnants 5919 * might not still have mappings in the scbindex array (e.g. unexpected 5920 * bus free with the same scb queued for an abort). Don't hold this 5921 * against them. 5922 */ 5923 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5924 u_int scbid; 5925 5926 ahc_outb(ahc, SCBPTR, i); 5927 scbid = ahc_inb(ahc, SCB_TAG); 5928 scbp = ahc_lookup_scb(ahc, scbid); 5929 if ((scbp == NULL && scbid != SCB_LIST_NULL) 5930 || (scbp != NULL 5931 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role))) 5932 ahc_add_curscb_to_free_list(ahc); 5933 } 5934 5935 /* 5936 * Go through the pending CCB list and look for 5937 * commands for this target that are still active. 5938 * These are other tagged commands that were 5939 * disconnected when the reset occurred. 5940 */ 5941 scbp_next = LIST_FIRST(&ahc->pending_scbs); 5942 while (scbp_next != NULL) { 5943 scbp = scbp_next; 5944 scbp_next = LIST_NEXT(scbp, pending_links); 5945 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) { 5946 cam_status ostat; 5947 5948 ostat = aic_get_transaction_status(scbp); 5949 if (ostat == CAM_REQ_INPROG) 5950 aic_set_transaction_status(scbp, status); 5951 if (aic_get_transaction_status(scbp) != CAM_REQ_CMP) 5952 aic_freeze_scb(scbp); 5953 if ((scbp->flags & SCB_ACTIVE) == 0) 5954 printf("Inactive SCB on pending list\n"); 5955 ahc_done(ahc, scbp); 5956 found++; 5957 } 5958 } 5959 ahc_outb(ahc, SCBPTR, active_scb); 5960 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status); 5961 ahc_release_untagged_queues(ahc); 5962 return found; 5963 } 5964 5965 static void 5966 ahc_reset_current_bus(struct ahc_softc *ahc) 5967 { 5968 uint8_t scsiseq; 5969 5970 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5971 scsiseq = ahc_inb(ahc, SCSISEQ); 5972 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5973 ahc_flush_device_writes(ahc); 5974 aic_delay(AHC_BUSRESET_DELAY); 5975 /* Turn off the bus reset */ 5976 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5977 5978 ahc_clear_intstat(ahc); 5979 5980 /* Re-enable reset interrupts */ 5981 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5982 } 5983 5984 int 5985 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5986 { 5987 struct ahc_devinfo devinfo; 5988 u_int initiator, target, max_scsiid; 5989 u_int sblkctl; 5990 u_int scsiseq; 5991 u_int simode1; 5992 int found; 5993 int restart_needed; 5994 char cur_channel; 5995 5996 ahc->pending_device = NULL; 5997 5998 ahc_compile_devinfo(&devinfo, 5999 CAM_TARGET_WILDCARD, 6000 CAM_TARGET_WILDCARD, 6001 CAM_LUN_WILDCARD, 6002 channel, ROLE_UNKNOWN); 6003 ahc_pause(ahc); 6004 6005 /* Make sure the sequencer is in a safe location. */ 6006 ahc_clear_critical_section(ahc); 6007 6008 /* 6009 * Run our command complete fifos to ensure that we perform 6010 * completion processing on any commands that 'completed' 6011 * before the reset occurred. 6012 */ 6013 ahc_run_qoutfifo(ahc); 6014 #ifdef AHC_TARGET_MODE 6015 /* 6016 * XXX - In Twin mode, the tqinfifo may have commands 6017 * for an unaffected channel in it. However, if 6018 * we have run out of ATIO resources to drain that 6019 * queue, we may not get them all out here. Further, 6020 * the blocked transactions for the reset channel 6021 * should just be killed off, irrespecitve of whether 6022 * we are blocked on ATIO resources. Write a routine 6023 * to compact the tqinfifo appropriately. 6024 */ 6025 if ((ahc->flags & AHC_TARGETROLE) != 0) { 6026 ahc_run_tqinfifo(ahc, /*paused*/TRUE); 6027 } 6028 #endif 6029 6030 /* 6031 * Reset the bus if we are initiating this reset 6032 */ 6033 sblkctl = ahc_inb(ahc, SBLKCTL); 6034 cur_channel = 'A'; 6035 if ((ahc->features & AHC_TWIN) != 0 6036 && ((sblkctl & SELBUSB) != 0)) 6037 cur_channel = 'B'; 6038 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 6039 if (cur_channel != channel) { 6040 /* Case 1: Command for another bus is active 6041 * Stealthily reset the other bus without 6042 * upsetting the current bus. 6043 */ 6044 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 6045 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 6046 #ifdef AHC_TARGET_MODE 6047 /* 6048 * Bus resets clear ENSELI, so we cannot 6049 * defer re-enabling bus reset interrupts 6050 * if we are in target mode. 6051 */ 6052 if ((ahc->flags & AHC_TARGETROLE) != 0) 6053 simode1 |= ENSCSIRST; 6054 #endif 6055 ahc_outb(ahc, SIMODE1, simode1); 6056 if (initiate_reset) 6057 ahc_reset_current_bus(ahc); 6058 ahc_clear_intstat(ahc); 6059 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 6060 ahc_outb(ahc, SBLKCTL, sblkctl); 6061 restart_needed = FALSE; 6062 } else { 6063 /* Case 2: A command from this bus is active or we're idle */ 6064 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 6065 #ifdef AHC_TARGET_MODE 6066 /* 6067 * Bus resets clear ENSELI, so we cannot 6068 * defer re-enabling bus reset interrupts 6069 * if we are in target mode. 6070 */ 6071 if ((ahc->flags & AHC_TARGETROLE) != 0) 6072 simode1 |= ENSCSIRST; 6073 #endif 6074 ahc_outb(ahc, SIMODE1, simode1); 6075 if (initiate_reset) 6076 ahc_reset_current_bus(ahc); 6077 ahc_clear_intstat(ahc); 6078 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 6079 restart_needed = TRUE; 6080 } 6081 6082 /* 6083 * Clean up all the state information for the 6084 * pending transactions on this bus. 6085 */ 6086 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel, 6087 CAM_LUN_WILDCARD, SCB_LIST_NULL, 6088 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 6089 6090 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 6091 6092 #ifdef AHC_TARGET_MODE 6093 /* 6094 * Send an immediate notify ccb to all target more peripheral 6095 * drivers affected by this action. 6096 */ 6097 for (target = 0; target <= max_scsiid; target++) { 6098 struct ahc_tmode_tstate* tstate; 6099 u_int lun; 6100 6101 tstate = ahc->enabled_targets[target]; 6102 if (tstate == NULL) 6103 continue; 6104 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 6105 struct ahc_tmode_lstate* lstate; 6106 6107 lstate = tstate->enabled_luns[lun]; 6108 if (lstate == NULL) 6109 continue; 6110 6111 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD, 6112 EVENT_TYPE_BUS_RESET, /*arg*/0); 6113 ahc_send_lstate_events(ahc, lstate); 6114 } 6115 } 6116 #endif 6117 /* Notify the XPT that a bus reset occurred */ 6118 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD, 6119 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL); 6120 6121 /* 6122 * Revert to async/narrow transfers until we renegotiate. 6123 */ 6124 for (target = 0; target <= max_scsiid; target++) { 6125 6126 if (ahc->enabled_targets[target] == NULL) 6127 continue; 6128 for (initiator = 0; initiator <= max_scsiid; initiator++) { 6129 struct ahc_devinfo devinfo; 6130 6131 ahc_compile_devinfo(&devinfo, target, initiator, 6132 CAM_LUN_WILDCARD, 6133 channel, ROLE_UNKNOWN); 6134 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6135 AHC_TRANS_CUR, /*paused*/TRUE); 6136 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL, 6137 /*period*/0, /*offset*/0, 6138 /*ppr_options*/0, AHC_TRANS_CUR, 6139 /*paused*/TRUE); 6140 } 6141 } 6142 6143 if (restart_needed) 6144 ahc_restart(ahc); 6145 else 6146 ahc_unpause(ahc); 6147 return found; 6148 } 6149 6150 6151 /***************************** Residual Processing ****************************/ 6152 /* 6153 * Calculate the residual for a just completed SCB. 6154 */ 6155 void 6156 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb) 6157 { 6158 struct hardware_scb *hscb; 6159 struct status_pkt *spkt; 6160 uint32_t sgptr; 6161 uint32_t resid_sgptr; 6162 uint32_t resid; 6163 6164 /* 6165 * 5 cases. 6166 * 1) No residual. 6167 * SG_RESID_VALID clear in sgptr. 6168 * 2) Transferless command 6169 * 3) Never performed any transfers. 6170 * sgptr has SG_FULL_RESID set. 6171 * 4) No residual but target did not 6172 * save data pointers after the 6173 * last transfer, so sgptr was 6174 * never updated. 6175 * 5) We have a partial residual. 6176 * Use residual_sgptr to determine 6177 * where we are. 6178 */ 6179 6180 hscb = scb->hscb; 6181 sgptr = aic_le32toh(hscb->sgptr); 6182 if ((sgptr & SG_RESID_VALID) == 0) 6183 /* Case 1 */ 6184 return; 6185 sgptr &= ~SG_RESID_VALID; 6186 6187 if ((sgptr & SG_LIST_NULL) != 0) 6188 /* Case 2 */ 6189 return; 6190 6191 spkt = &hscb->shared_data.status; 6192 resid_sgptr = aic_le32toh(spkt->residual_sg_ptr); 6193 if ((sgptr & SG_FULL_RESID) != 0) { 6194 /* Case 3 */ 6195 resid = aic_get_transfer_length(scb); 6196 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 6197 /* Case 4 */ 6198 return; 6199 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 6200 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 6201 } else { 6202 struct ahc_dma_seg *sg; 6203 6204 /* 6205 * Remainder of the SG where the transfer 6206 * stopped. 6207 */ 6208 resid = aic_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK; 6209 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK); 6210 6211 /* The residual sg_ptr always points to the next sg */ 6212 sg--; 6213 6214 /* 6215 * Add up the contents of all residual 6216 * SG segments that are after the SG where 6217 * the transfer stopped. 6218 */ 6219 while ((aic_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) { 6220 sg++; 6221 resid += aic_le32toh(sg->len) & AHC_SG_LEN_MASK; 6222 } 6223 } 6224 if ((scb->flags & SCB_SENSE) == 0) 6225 aic_set_residual(scb, resid); 6226 else 6227 aic_set_sense_residual(scb, resid); 6228 6229 #ifdef AHC_DEBUG 6230 if ((ahc_debug & AHC_SHOW_MISC) != 0) { 6231 ahc_print_path(ahc, scb); 6232 printf("Handled %sResidual of %d bytes\n", 6233 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 6234 } 6235 #endif 6236 } 6237 6238 /******************************* Target Mode **********************************/ 6239 #ifdef AHC_TARGET_MODE 6240 /* 6241 * Add a target mode event to this lun's queue 6242 */ 6243 static void 6244 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate, 6245 u_int initiator_id, u_int event_type, u_int event_arg) 6246 { 6247 struct ahc_tmode_event *event; 6248 int pending; 6249 6250 xpt_freeze_devq(lstate->path, /*count*/1); 6251 if (lstate->event_w_idx >= lstate->event_r_idx) 6252 pending = lstate->event_w_idx - lstate->event_r_idx; 6253 else 6254 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1 6255 - (lstate->event_r_idx - lstate->event_w_idx); 6256 6257 if (event_type == EVENT_TYPE_BUS_RESET 6258 || event_type == MSG_BUS_DEV_RESET) { 6259 /* 6260 * Any earlier events are irrelevant, so reset our buffer. 6261 * This has the effect of allowing us to deal with reset 6262 * floods (an external device holding down the reset line) 6263 * without losing the event that is really interesting. 6264 */ 6265 lstate->event_r_idx = 0; 6266 lstate->event_w_idx = 0; 6267 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 6268 } 6269 6270 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) { 6271 xpt_print_path(lstate->path); 6272 printf("immediate event %x:%x lost\n", 6273 lstate->event_buffer[lstate->event_r_idx].event_type, 6274 lstate->event_buffer[lstate->event_r_idx].event_arg); 6275 lstate->event_r_idx++; 6276 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6277 lstate->event_r_idx = 0; 6278 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 6279 } 6280 6281 event = &lstate->event_buffer[lstate->event_w_idx]; 6282 event->initiator_id = initiator_id; 6283 event->event_type = event_type; 6284 event->event_arg = event_arg; 6285 lstate->event_w_idx++; 6286 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6287 lstate->event_w_idx = 0; 6288 } 6289 6290 /* 6291 * Send any target mode events queued up waiting 6292 * for immediate notify resources. 6293 */ 6294 void 6295 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate) 6296 { 6297 struct ccb_hdr *ccbh; 6298 struct ccb_immed_notify *inot; 6299 6300 while (lstate->event_r_idx != lstate->event_w_idx 6301 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 6302 struct ahc_tmode_event *event; 6303 6304 event = &lstate->event_buffer[lstate->event_r_idx]; 6305 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 6306 inot = (struct ccb_immed_notify *)ccbh; 6307 switch (event->event_type) { 6308 case EVENT_TYPE_BUS_RESET: 6309 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 6310 break; 6311 default: 6312 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 6313 inot->message_args[0] = event->event_type; 6314 inot->message_args[1] = event->event_arg; 6315 break; 6316 } 6317 inot->initiator_id = event->initiator_id; 6318 inot->sense_len = 0; 6319 xpt_done((union ccb *)inot); 6320 lstate->event_r_idx++; 6321 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6322 lstate->event_r_idx = 0; 6323 } 6324 } 6325 #endif 6326 6327 /******************** Sequencer Program Patching/Download *********************/ 6328 6329 #ifdef AHC_DUMP_SEQ 6330 void 6331 ahc_dumpseq(struct ahc_softc* ahc) 6332 { 6333 int i; 6334 6335 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6336 ahc_outb(ahc, SEQADDR0, 0); 6337 ahc_outb(ahc, SEQADDR1, 0); 6338 for (i = 0; i < ahc->instruction_ram_size; i++) { 6339 uint8_t ins_bytes[4]; 6340 6341 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 6342 printf("0x%08x\n", ins_bytes[0] << 24 6343 | ins_bytes[1] << 16 6344 | ins_bytes[2] << 8 6345 | ins_bytes[3]); 6346 } 6347 } 6348 #endif 6349 6350 static int 6351 ahc_loadseq(struct ahc_softc *ahc) 6352 { 6353 struct cs cs_table[num_critical_sections]; 6354 u_int begin_set[num_critical_sections]; 6355 u_int end_set[num_critical_sections]; 6356 struct patch *cur_patch; 6357 u_int cs_count; 6358 u_int cur_cs; 6359 u_int i; 6360 u_int skip_addr; 6361 u_int sg_prefetch_cnt; 6362 int downloaded; 6363 uint8_t download_consts[7]; 6364 6365 /* 6366 * Start out with 0 critical sections 6367 * that apply to this firmware load. 6368 */ 6369 cs_count = 0; 6370 cur_cs = 0; 6371 memset(begin_set, 0, sizeof(begin_set)); 6372 memset(end_set, 0, sizeof(end_set)); 6373 6374 /* Setup downloadable constant table */ 6375 download_consts[QOUTFIFO_OFFSET] = 0; 6376 if (ahc->targetcmds != NULL) 6377 download_consts[QOUTFIFO_OFFSET] += 32; 6378 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1; 6379 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1; 6380 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1); 6381 sg_prefetch_cnt = ahc->pci_cachesize; 6382 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg))) 6383 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg); 6384 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 6385 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1); 6386 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1); 6387 6388 cur_patch = patches; 6389 downloaded = 0; 6390 skip_addr = 0; 6391 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6392 ahc_outb(ahc, SEQADDR0, 0); 6393 ahc_outb(ahc, SEQADDR1, 0); 6394 6395 for (i = 0; i < sizeof(seqprog)/4; i++) { 6396 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 6397 /* 6398 * Don't download this instruction as it 6399 * is in a patch that was removed. 6400 */ 6401 continue; 6402 } 6403 6404 if (downloaded == ahc->instruction_ram_size) { 6405 /* 6406 * We're about to exceed the instruction 6407 * storage capacity for this chip. Fail 6408 * the load. 6409 */ 6410 printf("\n%s: Program too large for instruction memory " 6411 "size of %d!\n", ahc_name(ahc), 6412 ahc->instruction_ram_size); 6413 return (ENOMEM); 6414 } 6415 6416 /* 6417 * Move through the CS table until we find a CS 6418 * that might apply to this instruction. 6419 */ 6420 for (; cur_cs < num_critical_sections; cur_cs++) { 6421 if (critical_sections[cur_cs].end <= i) { 6422 if (begin_set[cs_count] == TRUE 6423 && end_set[cs_count] == FALSE) { 6424 cs_table[cs_count].end = downloaded; 6425 end_set[cs_count] = TRUE; 6426 cs_count++; 6427 } 6428 continue; 6429 } 6430 if (critical_sections[cur_cs].begin <= i 6431 && begin_set[cs_count] == FALSE) { 6432 cs_table[cs_count].begin = downloaded; 6433 begin_set[cs_count] = TRUE; 6434 } 6435 break; 6436 } 6437 ahc_download_instr(ahc, i, download_consts); 6438 downloaded++; 6439 } 6440 6441 ahc->num_critical_sections = cs_count; 6442 if (cs_count != 0) { 6443 6444 cs_count *= sizeof(struct cs); 6445 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 6446 if (ahc->critical_sections == NULL) 6447 panic("ahc_loadseq: Could not malloc"); 6448 memcpy(ahc->critical_sections, cs_table, cs_count); 6449 } 6450 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 6451 6452 if (bootverbose) { 6453 printf(" %d instructions downloaded\n", downloaded); 6454 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 6455 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags); 6456 } 6457 return (0); 6458 } 6459 6460 static int 6461 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 6462 u_int start_instr, u_int *skip_addr) 6463 { 6464 struct patch *cur_patch; 6465 struct patch *last_patch; 6466 u_int num_patches; 6467 6468 num_patches = sizeof(patches)/sizeof(struct patch); 6469 last_patch = &patches[num_patches]; 6470 cur_patch = *start_patch; 6471 6472 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 6473 6474 if (cur_patch->patch_func(ahc) == 0) { 6475 6476 /* Start rejecting code */ 6477 *skip_addr = start_instr + cur_patch->skip_instr; 6478 cur_patch += cur_patch->skip_patch; 6479 } else { 6480 /* Accepted this patch. Advance to the next 6481 * one and wait for our intruction pointer to 6482 * hit this point. 6483 */ 6484 cur_patch++; 6485 } 6486 } 6487 6488 *start_patch = cur_patch; 6489 if (start_instr < *skip_addr) 6490 /* Still skipping */ 6491 return (0); 6492 6493 return (1); 6494 } 6495 6496 static void 6497 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts) 6498 { 6499 union ins_formats instr; 6500 struct ins_format1 *fmt1_ins; 6501 struct ins_format3 *fmt3_ins; 6502 u_int opcode; 6503 6504 /* 6505 * The firmware is always compiled into a little endian format. 6506 */ 6507 instr.integer = aic_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 6508 6509 fmt1_ins = &instr.format1; 6510 fmt3_ins = NULL; 6511 6512 /* Pull the opcode */ 6513 opcode = instr.format1.opcode; 6514 switch (opcode) { 6515 case AIC_OP_JMP: 6516 case AIC_OP_JC: 6517 case AIC_OP_JNC: 6518 case AIC_OP_CALL: 6519 case AIC_OP_JNE: 6520 case AIC_OP_JNZ: 6521 case AIC_OP_JE: 6522 case AIC_OP_JZ: 6523 { 6524 struct patch *cur_patch; 6525 int address_offset; 6526 u_int address; 6527 u_int skip_addr; 6528 u_int i; 6529 6530 fmt3_ins = &instr.format3; 6531 address_offset = 0; 6532 address = fmt3_ins->address; 6533 cur_patch = patches; 6534 skip_addr = 0; 6535 6536 for (i = 0; i < address;) { 6537 6538 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 6539 6540 if (skip_addr > i) { 6541 int end_addr; 6542 6543 end_addr = MIN(address, skip_addr); 6544 address_offset += end_addr - i; 6545 i = skip_addr; 6546 } else { 6547 i++; 6548 } 6549 } 6550 address -= address_offset; 6551 fmt3_ins->address = address; 6552 /* FALLTHROUGH */ 6553 } 6554 case AIC_OP_OR: 6555 case AIC_OP_AND: 6556 case AIC_OP_XOR: 6557 case AIC_OP_ADD: 6558 case AIC_OP_ADC: 6559 case AIC_OP_BMOV: 6560 if (fmt1_ins->parity != 0) { 6561 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 6562 } 6563 fmt1_ins->parity = 0; 6564 if ((ahc->features & AHC_CMD_CHAN) == 0 6565 && opcode == AIC_OP_BMOV) { 6566 /* 6567 * Block move was added at the same time 6568 * as the command channel. Verify that 6569 * this is only a move of a single element 6570 * and convert the BMOV to a MOV 6571 * (AND with an immediate of FF). 6572 */ 6573 if (fmt1_ins->immediate != 1) 6574 panic("%s: BMOV not supported\n", 6575 ahc_name(ahc)); 6576 fmt1_ins->opcode = AIC_OP_AND; 6577 fmt1_ins->immediate = 0xff; 6578 } 6579 /* FALLTHROUGH */ 6580 case AIC_OP_ROL: 6581 if ((ahc->features & AHC_ULTRA2) != 0) { 6582 int i, count; 6583 6584 /* Calculate odd parity for the instruction */ 6585 for (i = 0, count = 0; i < 31; i++) { 6586 uint32_t mask; 6587 6588 mask = 0x01 << i; 6589 if ((instr.integer & mask) != 0) 6590 count++; 6591 } 6592 if ((count & 0x01) == 0) 6593 instr.format1.parity = 1; 6594 } else { 6595 /* Compress the instruction for older sequencers */ 6596 if (fmt3_ins != NULL) { 6597 instr.integer = 6598 fmt3_ins->immediate 6599 | (fmt3_ins->source << 8) 6600 | (fmt3_ins->address << 16) 6601 | (fmt3_ins->opcode << 25); 6602 } else { 6603 instr.integer = 6604 fmt1_ins->immediate 6605 | (fmt1_ins->source << 8) 6606 | (fmt1_ins->destination << 16) 6607 | (fmt1_ins->ret << 24) 6608 | (fmt1_ins->opcode << 25); 6609 } 6610 } 6611 /* The sequencer is a little endian cpu */ 6612 instr.integer = aic_htole32(instr.integer); 6613 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 6614 break; 6615 default: 6616 panic("Unknown opcode encountered in seq program"); 6617 break; 6618 } 6619 } 6620 6621 int 6622 ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries, 6623 const char *name, u_int address, u_int value, 6624 u_int *cur_column, u_int wrap_point) 6625 { 6626 int printed; 6627 u_int printed_mask; 6628 6629 if (cur_column != NULL && *cur_column >= wrap_point) { 6630 printf("\n"); 6631 *cur_column = 0; 6632 } 6633 printed = printf("%s[0x%x]", name, value); 6634 if (table == NULL) { 6635 printed += printf(" "); 6636 *cur_column += printed; 6637 return (printed); 6638 } 6639 printed_mask = 0; 6640 while (printed_mask != 0xFF) { 6641 int entry; 6642 6643 for (entry = 0; entry < num_entries; entry++) { 6644 if (((value & table[entry].mask) 6645 != table[entry].value) 6646 || ((printed_mask & table[entry].mask) 6647 == table[entry].mask)) 6648 continue; 6649 6650 printed += printf("%s%s", 6651 printed_mask == 0 ? ":(" : "|", 6652 table[entry].name); 6653 printed_mask |= table[entry].mask; 6654 6655 break; 6656 } 6657 if (entry >= num_entries) 6658 break; 6659 } 6660 if (printed_mask != 0) 6661 printed += printf(") "); 6662 else 6663 printed += printf(" "); 6664 if (cur_column != NULL) 6665 *cur_column += printed; 6666 return (printed); 6667 } 6668 6669 void 6670 ahc_dump_card_state(struct ahc_softc *ahc) 6671 { 6672 struct scb *scb; 6673 struct scb_tailq *untagged_q; 6674 u_int cur_col; 6675 int paused; 6676 int target; 6677 int maxtarget; 6678 int i; 6679 uint8_t last_phase; 6680 uint8_t qinpos; 6681 uint8_t qintail; 6682 uint8_t qoutpos; 6683 uint8_t scb_index; 6684 uint8_t saved_scbptr; 6685 6686 if (ahc_is_paused(ahc)) { 6687 paused = 1; 6688 } else { 6689 paused = 0; 6690 ahc_pause(ahc); 6691 } 6692 6693 saved_scbptr = ahc_inb(ahc, SCBPTR); 6694 last_phase = ahc_inb(ahc, LASTPHASE); 6695 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 6696 "%s: Dumping Card State %s, at SEQADDR 0x%x\n", 6697 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg, 6698 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 6699 if (paused) 6700 printf("Card was paused\n"); 6701 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n", 6702 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX), 6703 ahc_inb(ahc, ARG_2)); 6704 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT), 6705 ahc_inb(ahc, SCBPTR)); 6706 cur_col = 0; 6707 if ((ahc->features & AHC_DT) != 0) 6708 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50); 6709 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50); 6710 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50); 6711 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50); 6712 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50); 6713 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50); 6714 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50); 6715 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50); 6716 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50); 6717 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50); 6718 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50); 6719 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50); 6720 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50); 6721 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50); 6722 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50); 6723 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50); 6724 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50); 6725 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50); 6726 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50); 6727 if (cur_col != 0) 6728 printf("\n"); 6729 printf("STACK:"); 6730 for (i = 0; i < STACK_SIZE; i++) 6731 printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8)); 6732 printf("\nSCB count = %d\n", ahc->scb_data->numscbs); 6733 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag); 6734 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB)); 6735 /* QINFIFO */ 6736 printf("QINFIFO entries: "); 6737 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 6738 qinpos = ahc_inb(ahc, SNSCB_QOFF); 6739 ahc_outb(ahc, SNSCB_QOFF, qinpos); 6740 } else 6741 qinpos = ahc_inb(ahc, QINPOS); 6742 qintail = ahc->qinfifonext; 6743 while (qinpos != qintail) { 6744 printf("%d ", ahc->qinfifo[qinpos]); 6745 qinpos++; 6746 } 6747 printf("\n"); 6748 6749 printf("Waiting Queue entries: "); 6750 scb_index = ahc_inb(ahc, WAITING_SCBH); 6751 i = 0; 6752 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6753 ahc_outb(ahc, SCBPTR, scb_index); 6754 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6755 scb_index = ahc_inb(ahc, SCB_NEXT); 6756 } 6757 printf("\n"); 6758 6759 printf("Disconnected Queue entries: "); 6760 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH); 6761 i = 0; 6762 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6763 ahc_outb(ahc, SCBPTR, scb_index); 6764 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6765 scb_index = ahc_inb(ahc, SCB_NEXT); 6766 } 6767 printf("\n"); 6768 6769 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 6770 printf("QOUTFIFO entries: "); 6771 qoutpos = ahc->qoutfifonext; 6772 i = 0; 6773 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) { 6774 printf("%d ", ahc->qoutfifo[qoutpos]); 6775 qoutpos++; 6776 } 6777 printf("\n"); 6778 6779 printf("Sequencer Free SCB List: "); 6780 scb_index = ahc_inb(ahc, FREE_SCBH); 6781 i = 0; 6782 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6783 ahc_outb(ahc, SCBPTR, scb_index); 6784 printf("%d ", scb_index); 6785 scb_index = ahc_inb(ahc, SCB_NEXT); 6786 } 6787 printf("\n"); 6788 6789 printf("Sequencer SCB Info: "); 6790 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 6791 ahc_outb(ahc, SCBPTR, i); 6792 cur_col = printf("\n%3d ", i); 6793 6794 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60); 6795 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60); 6796 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60); 6797 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6798 } 6799 printf("\n"); 6800 6801 printf("Pending list: "); 6802 i = 0; 6803 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 6804 if (i++ > 256) 6805 break; 6806 cur_col = printf("\n%3d ", scb->hscb->tag); 6807 ahc_scb_control_print(scb->hscb->control, &cur_col, 60); 6808 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60); 6809 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60); 6810 if ((ahc->flags & AHC_PAGESCBS) == 0) { 6811 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 6812 printf("("); 6813 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), 6814 &cur_col, 60); 6815 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6816 printf(")"); 6817 } 6818 } 6819 printf("\n"); 6820 6821 printf("Kernel Free SCB list: "); 6822 i = 0; 6823 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) { 6824 if (i++ > 256) 6825 break; 6826 printf("%d ", scb->hscb->tag); 6827 } 6828 printf("\n"); 6829 6830 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7; 6831 for (target = 0; target <= maxtarget; target++) { 6832 untagged_q = &ahc->untagged_queues[target]; 6833 if (TAILQ_FIRST(untagged_q) == NULL) 6834 continue; 6835 printf("Untagged Q(%d): ", target); 6836 i = 0; 6837 TAILQ_FOREACH(scb, untagged_q, links.tqe) { 6838 if (i++ > 256) 6839 break; 6840 printf("%d ", scb->hscb->tag); 6841 } 6842 printf("\n"); 6843 } 6844 6845 ahc_platform_dump_card_state(ahc); 6846 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 6847 ahc_outb(ahc, SCBPTR, saved_scbptr); 6848 if (paused == 0) 6849 ahc_unpause(ahc); 6850 } 6851 6852 /*************************** Timeout Handling *********************************/ 6853 void 6854 ahc_timeout(struct scb *scb) 6855 { 6856 struct ahc_softc *ahc; 6857 6858 ahc = scb->ahc_softc; 6859 if ((scb->flags & SCB_ACTIVE) != 0) { 6860 if ((scb->flags & SCB_TIMEDOUT) == 0) { 6861 LIST_INSERT_HEAD(&ahc->timedout_scbs, scb, 6862 timedout_links); 6863 scb->flags |= SCB_TIMEDOUT; 6864 } 6865 ahc_wakeup_recovery_thread(ahc); 6866 } 6867 } 6868 6869 /* 6870 * Re-schedule a timeout for the passed in SCB if we determine that some 6871 * other SCB is in the process of recovery or an SCB with a longer 6872 * timeout is still pending. Limit our search to just "other_scb" 6873 * if it is non-NULL. 6874 */ 6875 static int 6876 ahc_other_scb_timeout(struct ahc_softc *ahc, struct scb *scb, 6877 struct scb *other_scb) 6878 { 6879 u_int newtimeout; 6880 int found; 6881 6882 ahc_print_path(ahc, scb); 6883 printf("Other SCB Timeout%s", 6884 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 6885 ? " again\n" : "\n"); 6886 6887 newtimeout = aic_get_timeout(scb); 6888 scb->flags |= SCB_OTHERTCL_TIMEOUT; 6889 found = 0; 6890 if (other_scb != NULL) { 6891 if ((other_scb->flags 6892 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0 6893 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) { 6894 found++; 6895 newtimeout = MAX(aic_get_timeout(other_scb), 6896 newtimeout); 6897 } 6898 } else { 6899 LIST_FOREACH(other_scb, &ahc->pending_scbs, pending_links) { 6900 if ((other_scb->flags 6901 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0 6902 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) { 6903 found++; 6904 newtimeout = 6905 MAX(aic_get_timeout(other_scb), 6906 newtimeout); 6907 } 6908 } 6909 } 6910 6911 if (found != 0) 6912 aic_scb_timer_reset(scb, newtimeout); 6913 else { 6914 ahc_print_path(ahc, scb); 6915 printf("No other SCB worth waiting for...\n"); 6916 } 6917 6918 return (found != 0); 6919 } 6920 6921 /* 6922 * ahc_recover_commands determines if any of the commands that have currently 6923 * timedout are the root cause for this timeout. Innocent commands are given 6924 * a new timeout while we wait for the command executing on the bus to timeout. 6925 * This routine is invoked from a thread context so we are allowed to sleep. 6926 * Our lock is not held on entry. 6927 */ 6928 void 6929 ahc_recover_commands(struct ahc_softc *ahc) 6930 { 6931 struct scb *scb; 6932 long s; 6933 int found; 6934 int restart_needed; 6935 u_int last_phase; 6936 6937 ahc_lock(ahc, &s); 6938 6939 /* 6940 * Pause the controller and manually flush any 6941 * commands that have just completed but that our 6942 * interrupt handler has yet to see. 6943 */ 6944 ahc_pause_and_flushwork(ahc); 6945 6946 if (LIST_EMPTY(&ahc->timedout_scbs) != 0) { 6947 /* 6948 * The timedout commands have already 6949 * completed. This typically means 6950 * that either the timeout value was on 6951 * the hairy edge of what the device 6952 * requires or - more likely - interrupts 6953 * are not happening. 6954 */ 6955 printf("%s: Timedout SCBs already complete. " 6956 "Interrupts may not be functioning.\n", ahc_name(ahc)); 6957 ahc_unpause(ahc); 6958 ahc_unlock(ahc, &s); 6959 return; 6960 } 6961 6962 restart_needed = 0; 6963 printf("%s: Recovery Initiated\n", ahc_name(ahc)); 6964 ahc_dump_card_state(ahc); 6965 6966 last_phase = ahc_inb(ahc, LASTPHASE); 6967 while ((scb = LIST_FIRST(&ahc->timedout_scbs)) != NULL) { 6968 u_int active_scb_index; 6969 u_int saved_scbptr; 6970 int target; 6971 int lun; 6972 int i; 6973 char channel; 6974 6975 target = SCB_GET_TARGET(ahc, scb); 6976 channel = SCB_GET_CHANNEL(ahc, scb); 6977 lun = SCB_GET_LUN(scb); 6978 6979 ahc_print_path(ahc, scb); 6980 printf("SCB 0x%x - timed out\n", scb->hscb->tag); 6981 if (scb->sg_count > 0) { 6982 for (i = 0; i < scb->sg_count; i++) { 6983 printf("sg[%d] - Addr 0x%x : Length %d\n", 6984 i, 6985 scb->sg_list[i].addr, 6986 scb->sg_list[i].len & AHC_SG_LEN_MASK); 6987 } 6988 } 6989 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { 6990 /* 6991 * Been down this road before. 6992 * Do a full bus reset. 6993 */ 6994 aic_set_transaction_status(scb, CAM_CMD_TIMEOUT); 6995 bus_reset: 6996 found = ahc_reset_channel(ahc, channel, 6997 /*Initiate Reset*/TRUE); 6998 printf("%s: Issued Channel %c Bus Reset. " 6999 "%d SCBs aborted\n", ahc_name(ahc), channel, 7000 found); 7001 continue; 7002 } 7003 7004 /* 7005 * Remove the command from the timedout list in 7006 * preparation for requeing it. 7007 */ 7008 LIST_REMOVE(scb, timedout_links); 7009 scb->flags &= ~SCB_TIMEDOUT; 7010 7011 /* 7012 * If we are a target, transition to bus free and report 7013 * the timeout. 7014 * 7015 * The target/initiator that is holding up the bus may not 7016 * be the same as the one that triggered this timeout 7017 * (different commands have different timeout lengths). 7018 * If the bus is idle and we are actiing as the initiator 7019 * for this request, queue a BDR message to the timed out 7020 * target. Otherwise, if the timed out transaction is 7021 * active: 7022 * Initiator transaction: 7023 * Stuff the message buffer with a BDR message and assert 7024 * ATN in the hopes that the target will let go of the bus 7025 * and go to the mesgout phase. If this fails, we'll 7026 * get another timeout 2 seconds later which will attempt 7027 * a bus reset. 7028 * 7029 * Target transaction: 7030 * Transition to BUS FREE and report the error. 7031 * It's good to be the target! 7032 */ 7033 saved_scbptr = ahc_inb(ahc, SCBPTR); 7034 active_scb_index = ahc_inb(ahc, SCB_TAG); 7035 7036 if ((ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) == 0 7037 && (active_scb_index < ahc->scb_data->numscbs)) { 7038 struct scb *active_scb; 7039 7040 /* 7041 * If the active SCB is not us, assume that 7042 * the active SCB has a longer timeout than 7043 * the timedout SCB, and wait for the active 7044 * SCB to timeout. 7045 */ 7046 active_scb = ahc_lookup_scb(ahc, active_scb_index); 7047 if (active_scb != scb) { 7048 if (ahc_other_scb_timeout(ahc, scb, 7049 active_scb) != 0) 7050 goto bus_reset; 7051 continue; 7052 } 7053 7054 /* It's us */ 7055 if ((scb->flags & SCB_TARGET_SCB) != 0) { 7056 7057 /* 7058 * Send back any queued up transactions 7059 * and properly record the error condition. 7060 */ 7061 ahc_abort_scbs(ahc, SCB_GET_TARGET(ahc, scb), 7062 SCB_GET_CHANNEL(ahc, scb), 7063 SCB_GET_LUN(scb), 7064 scb->hscb->tag, 7065 ROLE_TARGET, 7066 CAM_CMD_TIMEOUT); 7067 7068 /* Will clear us from the bus */ 7069 restart_needed = 1; 7070 break; 7071 } 7072 7073 ahc_set_recoveryscb(ahc, active_scb); 7074 ahc_outb(ahc, MSG_OUT, HOST_MSG); 7075 ahc_outb(ahc, SCSISIGO, last_phase|ATNO); 7076 ahc_print_path(ahc, active_scb); 7077 printf("BDR message in message buffer\n"); 7078 active_scb->flags |= SCB_DEVICE_RESET; 7079 aic_scb_timer_reset(scb, 2 * 1000000); 7080 } else if (last_phase != P_BUSFREE 7081 && (ahc_inb(ahc, SSTAT1) & REQINIT) == 0) { 7082 /* 7083 * SCB is not identified, there 7084 * is no pending REQ, and the sequencer 7085 * has not seen a busfree. Looks like 7086 * a stuck connection waiting to 7087 * go busfree. Reset the bus. 7088 */ 7089 printf("%s: Connection stuck awaiting busfree or " 7090 "Identify Msg.\n", ahc_name(ahc)); 7091 goto bus_reset; 7092 } else { 7093 int disconnected; 7094 7095 if (last_phase != P_BUSFREE 7096 && (ahc_inb(ahc, SSTAT0) & TARGET) != 0) { 7097 /* Hung target selection. Goto busfree */ 7098 printf("%s: Hung target selection\n", 7099 ahc_name(ahc)); 7100 restart_needed = 1; 7101 break; 7102 } 7103 7104 /* XXX Shouldn't panic. Just punt instead? */ 7105 if ((scb->flags & SCB_TARGET_SCB) != 0) 7106 panic("Timed-out target SCB but bus idle"); 7107 7108 if (ahc_search_qinfifo(ahc, target, channel, lun, 7109 scb->hscb->tag, ROLE_INITIATOR, 7110 /*status*/0, SEARCH_COUNT) > 0) { 7111 disconnected = FALSE; 7112 } else { 7113 disconnected = TRUE; 7114 } 7115 7116 if (disconnected) { 7117 7118 ahc_set_recoveryscb(ahc, scb); 7119 /* 7120 * Actually re-queue this SCB in an attempt 7121 * to select the device before it reconnects. 7122 * In either case (selection or reselection), 7123 * we will now issue a target reset to the 7124 * timed-out device. 7125 * 7126 * Set the MK_MESSAGE control bit indicating 7127 * that we desire to send a message. We 7128 * also set the disconnected flag since 7129 * in the paging case there is no guarantee 7130 * that our SCB control byte matches the 7131 * version on the card. We don't want the 7132 * sequencer to abort the command thinking 7133 * an unsolicited reselection occurred. 7134 */ 7135 scb->hscb->control |= MK_MESSAGE|DISCONNECTED; 7136 scb->flags |= SCB_DEVICE_RESET; 7137 7138 /* 7139 * Remove any cached copy of this SCB in the 7140 * disconnected list in preparation for the 7141 * queuing of our abort SCB. We use the 7142 * same element in the SCB, SCB_NEXT, for 7143 * both the qinfifo and the disconnected list. 7144 */ 7145 ahc_search_disc_list(ahc, target, channel, 7146 lun, scb->hscb->tag, 7147 /*stop_on_first*/TRUE, 7148 /*remove*/TRUE, 7149 /*save_state*/FALSE); 7150 7151 /* 7152 * In the non-paging case, the sequencer will 7153 * never re-reference the in-core SCB. 7154 * To make sure we are notified during 7155 * reslection, set the MK_MESSAGE flag in 7156 * the card's copy of the SCB. 7157 */ 7158 if ((ahc->flags & AHC_PAGESCBS) == 0) { 7159 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 7160 ahc_outb(ahc, SCB_CONTROL, 7161 ahc_inb(ahc, SCB_CONTROL) 7162 | MK_MESSAGE); 7163 } 7164 7165 /* 7166 * Clear out any entries in the QINFIFO first 7167 * so we are the next SCB for this target 7168 * to run. 7169 */ 7170 ahc_search_qinfifo(ahc, 7171 SCB_GET_TARGET(ahc, scb), 7172 channel, SCB_GET_LUN(scb), 7173 SCB_LIST_NULL, 7174 ROLE_INITIATOR, 7175 CAM_REQUEUE_REQ, 7176 SEARCH_COMPLETE); 7177 ahc_print_path(ahc, scb); 7178 printf("Queuing a BDR SCB\n"); 7179 ahc_qinfifo_requeue_tail(ahc, scb); 7180 ahc_outb(ahc, SCBPTR, saved_scbptr); 7181 aic_scb_timer_reset(scb, 2 * 1000000); 7182 } else { 7183 /* Go "immediatly" to the bus reset */ 7184 /* This shouldn't happen */ 7185 ahc_set_recoveryscb(ahc, scb); 7186 ahc_print_path(ahc, scb); 7187 printf("SCB %d: Immediate reset. " 7188 "Flags = 0x%x\n", scb->hscb->tag, 7189 scb->flags); 7190 goto bus_reset; 7191 } 7192 } 7193 break; 7194 } 7195 7196 /* 7197 * Any remaining SCBs were not the "culprit", so remove 7198 * them from the timeout list. The timer for these commands 7199 * will be reset once the recovery SCB completes. 7200 */ 7201 while ((scb = LIST_FIRST(&ahc->timedout_scbs)) != NULL) { 7202 7203 LIST_REMOVE(scb, timedout_links); 7204 scb->flags &= ~SCB_TIMEDOUT; 7205 } 7206 7207 if (restart_needed) 7208 ahc_restart(ahc); 7209 else 7210 ahc_unpause(ahc); 7211 ahc_unlock(ahc, &s); 7212 } 7213 7214 /************************* Target Mode ****************************************/ 7215 #ifdef AHC_TARGET_MODE 7216 cam_status 7217 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb, 7218 struct ahc_tmode_tstate **tstate, 7219 struct ahc_tmode_lstate **lstate, 7220 int notfound_failure) 7221 { 7222 7223 if ((ahc->features & AHC_TARGETMODE) == 0) 7224 return (CAM_REQ_INVALID); 7225 7226 /* 7227 * Handle the 'black hole' device that sucks up 7228 * requests to unattached luns on enabled targets. 7229 */ 7230 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 7231 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 7232 *tstate = NULL; 7233 *lstate = ahc->black_hole; 7234 } else { 7235 u_int max_id; 7236 7237 max_id = (ahc->features & AHC_WIDE) ? 15 : 7; 7238 if (ccb->ccb_h.target_id > max_id) 7239 return (CAM_TID_INVALID); 7240 7241 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS) 7242 return (CAM_LUN_INVALID); 7243 7244 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id]; 7245 *lstate = NULL; 7246 if (*tstate != NULL) 7247 *lstate = 7248 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 7249 } 7250 7251 if (notfound_failure != 0 && *lstate == NULL) 7252 return (CAM_PATH_INVALID); 7253 7254 return (CAM_REQ_CMP); 7255 } 7256 7257 void 7258 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb) 7259 { 7260 struct ahc_tmode_tstate *tstate; 7261 struct ahc_tmode_lstate *lstate; 7262 struct ccb_en_lun *cel; 7263 cam_status status; 7264 u_long s; 7265 u_int target; 7266 u_int lun; 7267 u_int target_mask; 7268 u_int our_id; 7269 int error; 7270 char channel; 7271 7272 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate, 7273 /*notfound_failure*/FALSE); 7274 7275 if (status != CAM_REQ_CMP) { 7276 ccb->ccb_h.status = status; 7277 return; 7278 } 7279 7280 if (cam_sim_bus(sim) == 0) 7281 our_id = ahc->our_id; 7282 else 7283 our_id = ahc->our_id_b; 7284 7285 if (ccb->ccb_h.target_id != our_id) { 7286 /* 7287 * our_id represents our initiator ID, or 7288 * the ID of the first target to have an 7289 * enabled lun in target mode. There are 7290 * two cases that may preclude enabling a 7291 * target id other than our_id. 7292 * 7293 * o our_id is for an active initiator role. 7294 * Since the hardware does not support 7295 * reselections to the initiator role at 7296 * anything other than our_id, and our_id 7297 * is used by the hardware to indicate the 7298 * ID to use for both select-out and 7299 * reselect-out operations, the only target 7300 * ID we can support in this mode is our_id. 7301 * 7302 * o The MULTARGID feature is not available and 7303 * a previous target mode ID has been enabled. 7304 */ 7305 if ((ahc->features & AHC_MULTIROLE) != 0) { 7306 7307 if ((ahc->features & AHC_MULTI_TID) != 0 7308 && (ahc->flags & AHC_INITIATORROLE) != 0) { 7309 /* 7310 * Only allow additional targets if 7311 * the initiator role is disabled. 7312 * The hardware cannot handle a re-select-in 7313 * on the initiator id during a re-select-out 7314 * on a different target id. 7315 */ 7316 status = CAM_TID_INVALID; 7317 } else if ((ahc->flags & AHC_INITIATORROLE) != 0 7318 || ahc->enabled_luns > 0) { 7319 /* 7320 * Only allow our target id to change 7321 * if the initiator role is not configured 7322 * and there are no enabled luns which 7323 * are attached to the currently registered 7324 * scsi id. 7325 */ 7326 status = CAM_TID_INVALID; 7327 } 7328 } else if ((ahc->features & AHC_MULTI_TID) == 0 7329 && ahc->enabled_luns > 0) { 7330 7331 status = CAM_TID_INVALID; 7332 } 7333 } 7334 7335 if (status != CAM_REQ_CMP) { 7336 ccb->ccb_h.status = status; 7337 return; 7338 } 7339 7340 /* 7341 * We now have an id that is valid. 7342 * If we aren't in target mode, switch modes. 7343 */ 7344 if ((ahc->flags & AHC_TARGETROLE) == 0 7345 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 7346 u_long s; 7347 ahc_flag saved_flags; 7348 7349 printf("Configuring Target Mode\n"); 7350 ahc_lock(ahc, &s); 7351 if (LIST_FIRST(&ahc->pending_scbs) != NULL) { 7352 ccb->ccb_h.status = CAM_BUSY; 7353 ahc_unlock(ahc, &s); 7354 return; 7355 } 7356 saved_flags = ahc->flags; 7357 ahc->flags |= AHC_TARGETROLE; 7358 if ((ahc->features & AHC_MULTIROLE) == 0) 7359 ahc->flags &= ~AHC_INITIATORROLE; 7360 ahc_pause(ahc); 7361 error = ahc_loadseq(ahc); 7362 if (error != 0) { 7363 /* 7364 * Restore original configuration and notify 7365 * the caller that we cannot support target mode. 7366 * Since the adapter started out in this 7367 * configuration, the firmware load will succeed, 7368 * so there is no point in checking ahc_loadseq's 7369 * return value. 7370 */ 7371 ahc->flags = saved_flags; 7372 (void)ahc_loadseq(ahc); 7373 ahc_restart(ahc); 7374 ahc_unlock(ahc, &s); 7375 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 7376 return; 7377 } 7378 ahc_restart(ahc); 7379 ahc_unlock(ahc, &s); 7380 } 7381 cel = &ccb->cel; 7382 target = ccb->ccb_h.target_id; 7383 lun = ccb->ccb_h.target_lun; 7384 channel = SIM_CHANNEL(ahc, sim); 7385 target_mask = 0x01 << target; 7386 if (channel == 'B') 7387 target_mask <<= 8; 7388 7389 if (cel->enable != 0) { 7390 u_int scsiseq; 7391 7392 /* Are we already enabled?? */ 7393 if (lstate != NULL) { 7394 xpt_print_path(ccb->ccb_h.path); 7395 printf("Lun already enabled\n"); 7396 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 7397 return; 7398 } 7399 7400 if (cel->grp6_len != 0 7401 || cel->grp7_len != 0) { 7402 /* 7403 * Don't (yet?) support vendor 7404 * specific commands. 7405 */ 7406 ccb->ccb_h.status = CAM_REQ_INVALID; 7407 printf("Non-zero Group Codes\n"); 7408 return; 7409 } 7410 7411 /* 7412 * Seems to be okay. 7413 * Setup our data structures. 7414 */ 7415 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 7416 tstate = ahc_alloc_tstate(ahc, target, channel); 7417 if (tstate == NULL) { 7418 xpt_print_path(ccb->ccb_h.path); 7419 printf("Couldn't allocate tstate\n"); 7420 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 7421 return; 7422 } 7423 } 7424 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 7425 if (lstate == NULL) { 7426 xpt_print_path(ccb->ccb_h.path); 7427 printf("Couldn't allocate lstate\n"); 7428 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 7429 return; 7430 } 7431 memset(lstate, 0, sizeof(*lstate)); 7432 status = xpt_create_path(&lstate->path, /*periph*/NULL, 7433 xpt_path_path_id(ccb->ccb_h.path), 7434 xpt_path_target_id(ccb->ccb_h.path), 7435 xpt_path_lun_id(ccb->ccb_h.path)); 7436 if (status != CAM_REQ_CMP) { 7437 free(lstate, M_DEVBUF); 7438 xpt_print_path(ccb->ccb_h.path); 7439 printf("Couldn't allocate path\n"); 7440 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 7441 return; 7442 } 7443 SLIST_INIT(&lstate->accept_tios); 7444 SLIST_INIT(&lstate->immed_notifies); 7445 ahc_lock(ahc, &s); 7446 ahc_pause(ahc); 7447 if (target != CAM_TARGET_WILDCARD) { 7448 tstate->enabled_luns[lun] = lstate; 7449 ahc->enabled_luns++; 7450 7451 if ((ahc->features & AHC_MULTI_TID) != 0) { 7452 u_int targid_mask; 7453 7454 targid_mask = ahc_inb(ahc, TARGID) 7455 | (ahc_inb(ahc, TARGID + 1) << 8); 7456 7457 targid_mask |= target_mask; 7458 ahc_outb(ahc, TARGID, targid_mask); 7459 ahc_outb(ahc, TARGID+1, (targid_mask >> 8)); 7460 7461 ahc_update_scsiid(ahc, targid_mask); 7462 } else { 7463 u_int our_id; 7464 char channel; 7465 7466 channel = SIM_CHANNEL(ahc, sim); 7467 our_id = SIM_SCSI_ID(ahc, sim); 7468 7469 /* 7470 * This can only happen if selections 7471 * are not enabled 7472 */ 7473 if (target != our_id) { 7474 u_int sblkctl; 7475 char cur_channel; 7476 int swap; 7477 7478 sblkctl = ahc_inb(ahc, SBLKCTL); 7479 cur_channel = (sblkctl & SELBUSB) 7480 ? 'B' : 'A'; 7481 if ((ahc->features & AHC_TWIN) == 0) 7482 cur_channel = 'A'; 7483 swap = cur_channel != channel; 7484 if (channel == 'A') 7485 ahc->our_id = target; 7486 else 7487 ahc->our_id_b = target; 7488 7489 if (swap) 7490 ahc_outb(ahc, SBLKCTL, 7491 sblkctl ^ SELBUSB); 7492 7493 ahc_outb(ahc, SCSIID, target); 7494 7495 if (swap) 7496 ahc_outb(ahc, SBLKCTL, sblkctl); 7497 } 7498 } 7499 } else 7500 ahc->black_hole = lstate; 7501 /* Allow select-in operations */ 7502 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) { 7503 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7504 scsiseq |= ENSELI; 7505 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7506 scsiseq = ahc_inb(ahc, SCSISEQ); 7507 scsiseq |= ENSELI; 7508 ahc_outb(ahc, SCSISEQ, scsiseq); 7509 } 7510 ahc_unpause(ahc); 7511 ahc_unlock(ahc, &s); 7512 ccb->ccb_h.status = CAM_REQ_CMP; 7513 xpt_print_path(ccb->ccb_h.path); 7514 printf("Lun now enabled for target mode\n"); 7515 } else { 7516 struct scb *scb; 7517 int i, empty; 7518 7519 if (lstate == NULL) { 7520 ccb->ccb_h.status = CAM_LUN_INVALID; 7521 return; 7522 } 7523 7524 ahc_lock(ahc, &s); 7525 7526 ccb->ccb_h.status = CAM_REQ_CMP; 7527 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 7528 struct ccb_hdr *ccbh; 7529 7530 ccbh = &scb->io_ctx->ccb_h; 7531 if (ccbh->func_code == XPT_CONT_TARGET_IO 7532 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 7533 printf("CTIO pending\n"); 7534 ccb->ccb_h.status = CAM_REQ_INVALID; 7535 ahc_unlock(ahc, &s); 7536 return; 7537 } 7538 } 7539 7540 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 7541 printf("ATIOs pending\n"); 7542 ccb->ccb_h.status = CAM_REQ_INVALID; 7543 } 7544 7545 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 7546 printf("INOTs pending\n"); 7547 ccb->ccb_h.status = CAM_REQ_INVALID; 7548 } 7549 7550 if (ccb->ccb_h.status != CAM_REQ_CMP) { 7551 ahc_unlock(ahc, &s); 7552 return; 7553 } 7554 7555 xpt_print_path(ccb->ccb_h.path); 7556 printf("Target mode disabled\n"); 7557 xpt_free_path(lstate->path); 7558 free(lstate, M_DEVBUF); 7559 7560 ahc_pause(ahc); 7561 /* Can we clean up the target too? */ 7562 if (target != CAM_TARGET_WILDCARD) { 7563 tstate->enabled_luns[lun] = NULL; 7564 ahc->enabled_luns--; 7565 for (empty = 1, i = 0; i < 8; i++) 7566 if (tstate->enabled_luns[i] != NULL) { 7567 empty = 0; 7568 break; 7569 } 7570 7571 if (empty) { 7572 ahc_free_tstate(ahc, target, channel, 7573 /*force*/FALSE); 7574 if (ahc->features & AHC_MULTI_TID) { 7575 u_int targid_mask; 7576 7577 targid_mask = ahc_inb(ahc, TARGID) 7578 | (ahc_inb(ahc, TARGID + 1) 7579 << 8); 7580 7581 targid_mask &= ~target_mask; 7582 ahc_outb(ahc, TARGID, targid_mask); 7583 ahc_outb(ahc, TARGID+1, 7584 (targid_mask >> 8)); 7585 ahc_update_scsiid(ahc, targid_mask); 7586 } 7587 } 7588 } else { 7589 7590 ahc->black_hole = NULL; 7591 7592 /* 7593 * We can't allow selections without 7594 * our black hole device. 7595 */ 7596 empty = TRUE; 7597 } 7598 if (ahc->enabled_luns == 0) { 7599 /* Disallow select-in */ 7600 u_int scsiseq; 7601 7602 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7603 scsiseq &= ~ENSELI; 7604 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7605 scsiseq = ahc_inb(ahc, SCSISEQ); 7606 scsiseq &= ~ENSELI; 7607 ahc_outb(ahc, SCSISEQ, scsiseq); 7608 7609 if ((ahc->features & AHC_MULTIROLE) == 0) { 7610 printf("Configuring Initiator Mode\n"); 7611 ahc->flags &= ~AHC_TARGETROLE; 7612 ahc->flags |= AHC_INITIATORROLE; 7613 /* 7614 * Returning to a configuration that 7615 * fit previously will always succeed. 7616 */ 7617 (void)ahc_loadseq(ahc); 7618 ahc_restart(ahc); 7619 /* 7620 * Unpaused. The extra unpause 7621 * that follows is harmless. 7622 */ 7623 } 7624 } 7625 ahc_unpause(ahc); 7626 ahc_unlock(ahc, &s); 7627 } 7628 } 7629 7630 static void 7631 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask) 7632 { 7633 u_int scsiid_mask; 7634 u_int scsiid; 7635 7636 if ((ahc->features & AHC_MULTI_TID) == 0) 7637 panic("ahc_update_scsiid called on non-multitid unit\n"); 7638 7639 /* 7640 * Since we will rely on the TARGID mask 7641 * for selection enables, ensure that OID 7642 * in SCSIID is not set to some other ID 7643 * that we don't want to allow selections on. 7644 */ 7645 if ((ahc->features & AHC_ULTRA2) != 0) 7646 scsiid = ahc_inb(ahc, SCSIID_ULTRA2); 7647 else 7648 scsiid = ahc_inb(ahc, SCSIID); 7649 scsiid_mask = 0x1 << (scsiid & OID); 7650 if ((targid_mask & scsiid_mask) == 0) { 7651 u_int our_id; 7652 7653 /* ffs counts from 1 */ 7654 our_id = ffs(targid_mask); 7655 if (our_id == 0) 7656 our_id = ahc->our_id; 7657 else 7658 our_id--; 7659 scsiid &= TID; 7660 scsiid |= our_id; 7661 } 7662 if ((ahc->features & AHC_ULTRA2) != 0) 7663 ahc_outb(ahc, SCSIID_ULTRA2, scsiid); 7664 else 7665 ahc_outb(ahc, SCSIID, scsiid); 7666 } 7667 7668 void 7669 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused) 7670 { 7671 struct target_cmd *cmd; 7672 7673 /* 7674 * If the card supports auto-access pause, 7675 * we can access the card directly regardless 7676 * of whether it is paused or not. 7677 */ 7678 if ((ahc->features & AHC_AUTOPAUSE) != 0) 7679 paused = TRUE; 7680 7681 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD); 7682 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) { 7683 7684 /* 7685 * Only advance through the queue if we 7686 * have the resources to process the command. 7687 */ 7688 if (ahc_handle_target_cmd(ahc, cmd) != 0) 7689 break; 7690 7691 cmd->cmd_valid = 0; 7692 aic_dmamap_sync(ahc, ahc->shared_data_dmat, 7693 ahc->shared_data_dmamap, 7694 ahc_targetcmd_offset(ahc, ahc->tqinfifonext), 7695 sizeof(struct target_cmd), 7696 BUS_DMASYNC_PREREAD); 7697 ahc->tqinfifonext++; 7698 7699 /* 7700 * Lazily update our position in the target mode incoming 7701 * command queue as seen by the sequencer. 7702 */ 7703 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 7704 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 7705 u_int hs_mailbox; 7706 7707 hs_mailbox = ahc_inb(ahc, HS_MAILBOX); 7708 hs_mailbox &= ~HOST_TQINPOS; 7709 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS; 7710 ahc_outb(ahc, HS_MAILBOX, hs_mailbox); 7711 } else { 7712 if (!paused) 7713 ahc_pause(ahc); 7714 ahc_outb(ahc, KERNEL_TQINPOS, 7715 ahc->tqinfifonext & HOST_TQINPOS); 7716 if (!paused) 7717 ahc_unpause(ahc); 7718 } 7719 } 7720 } 7721 } 7722 7723 static int 7724 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd) 7725 { 7726 struct ahc_tmode_tstate *tstate; 7727 struct ahc_tmode_lstate *lstate; 7728 struct ccb_accept_tio *atio; 7729 uint8_t *byte; 7730 int initiator; 7731 int target; 7732 int lun; 7733 7734 initiator = SCSIID_TARGET(ahc, cmd->scsiid); 7735 target = SCSIID_OUR_ID(cmd->scsiid); 7736 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 7737 7738 byte = cmd->bytes; 7739 tstate = ahc->enabled_targets[target]; 7740 lstate = NULL; 7741 if (tstate != NULL) 7742 lstate = tstate->enabled_luns[lun]; 7743 7744 /* 7745 * Commands for disabled luns go to the black hole driver. 7746 */ 7747 if (lstate == NULL) 7748 lstate = ahc->black_hole; 7749 7750 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 7751 if (atio == NULL) { 7752 ahc->flags |= AHC_TQINFIFO_BLOCKED; 7753 /* 7754 * Wait for more ATIOs from the peripheral driver for this lun. 7755 */ 7756 if (bootverbose) 7757 printf("%s: ATIOs exhausted\n", ahc_name(ahc)); 7758 return (1); 7759 } else 7760 ahc->flags &= ~AHC_TQINFIFO_BLOCKED; 7761 #if 0 7762 printf("Incoming command from %d for %d:%d%s\n", 7763 initiator, target, lun, 7764 lstate == ahc->black_hole ? "(Black Holed)" : ""); 7765 #endif 7766 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 7767 7768 if (lstate == ahc->black_hole) { 7769 /* Fill in the wildcards */ 7770 atio->ccb_h.target_id = target; 7771 atio->ccb_h.target_lun = lun; 7772 } 7773 7774 /* 7775 * Package it up and send it off to 7776 * whomever has this lun enabled. 7777 */ 7778 atio->sense_len = 0; 7779 atio->init_id = initiator; 7780 if (byte[0] != 0xFF) { 7781 /* Tag was included */ 7782 atio->tag_action = *byte++; 7783 atio->tag_id = *byte++; 7784 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 7785 } else { 7786 atio->ccb_h.flags = 0; 7787 } 7788 byte++; 7789 7790 /* Okay. Now determine the cdb size based on the command code */ 7791 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 7792 case 0: 7793 atio->cdb_len = 6; 7794 break; 7795 case 1: 7796 case 2: 7797 atio->cdb_len = 10; 7798 break; 7799 case 4: 7800 atio->cdb_len = 16; 7801 break; 7802 case 5: 7803 atio->cdb_len = 12; 7804 break; 7805 case 3: 7806 default: 7807 /* Only copy the opcode. */ 7808 atio->cdb_len = 1; 7809 printf("Reserved or VU command code type encountered\n"); 7810 break; 7811 } 7812 7813 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 7814 7815 atio->ccb_h.status |= CAM_CDB_RECVD; 7816 7817 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 7818 /* 7819 * We weren't allowed to disconnect. 7820 * We're hanging on the bus until a 7821 * continue target I/O comes in response 7822 * to this accept tio. 7823 */ 7824 #if 0 7825 printf("Received Immediate Command %d:%d:%d - %p\n", 7826 initiator, target, lun, ahc->pending_device); 7827 #endif 7828 ahc->pending_device = lstate; 7829 aic_freeze_ccb((union ccb *)atio); 7830 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 7831 } 7832 xpt_done((union ccb*)atio); 7833 return (0); 7834 } 7835 7836 #endif 7837