1 /* 2 * DO NOT EDIT - This file is automatically generated 3 * from the following source files: 4 * 5 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#119 $ 6 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#76 $ 7 */ 8 9 #include <sys/cdefs.h> 10 #include <dev/aic7xxx/aic79xx_osm.h> 11 12 static ahd_reg_parse_entry_t MODE_PTR_parse_table[] = { 13 { "SRC_MODE", 0x07, 0x07 }, 14 { "DST_MODE", 0x70, 0x70 } 15 }; 16 17 int 18 ahd_mode_ptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 19 { 20 return (ahd_print_register(MODE_PTR_parse_table, 2, "MODE_PTR", 21 0x00, regvalue, cur_col, wrap)); 22 } 23 24 static ahd_reg_parse_entry_t INTSTAT_parse_table[] = { 25 { "SPLTINT", 0x01, 0x01 }, 26 { "CMDCMPLT", 0x02, 0x02 }, 27 { "SEQINT", 0x04, 0x04 }, 28 { "SCSIINT", 0x08, 0x08 }, 29 { "PCIINT", 0x10, 0x10 }, 30 { "SWTMINT", 0x20, 0x20 }, 31 { "BRKADRINT", 0x40, 0x40 }, 32 { "HWERRINT", 0x80, 0x80 }, 33 { "INT_PEND", 0xff, 0xff } 34 }; 35 36 int 37 ahd_intstat_print(u_int regvalue, u_int *cur_col, u_int wrap) 38 { 39 return (ahd_print_register(INTSTAT_parse_table, 9, "INTSTAT", 40 0x01, regvalue, cur_col, wrap)); 41 } 42 43 static ahd_reg_parse_entry_t SEQINTCODE_parse_table[] = { 44 { "NO_SEQINT", 0x00, 0xff }, 45 { "BAD_PHASE", 0x01, 0xff }, 46 { "SEND_REJECT", 0x02, 0xff }, 47 { "PROTO_VIOLATION", 0x03, 0xff }, 48 { "NO_MATCH", 0x04, 0xff }, 49 { "IGN_WIDE_RES", 0x05, 0xff }, 50 { "PDATA_REINIT", 0x06, 0xff }, 51 { "HOST_MSG_LOOP", 0x07, 0xff }, 52 { "BAD_STATUS", 0x08, 0xff }, 53 { "DATA_OVERRUN", 0x09, 0xff }, 54 { "MKMSG_FAILED", 0x0a, 0xff }, 55 { "MISSED_BUSFREE", 0x0b, 0xff }, 56 { "DUMP_CARD_STATE", 0x0c, 0xff }, 57 { "ILLEGAL_PHASE", 0x0d, 0xff }, 58 { "INVALID_SEQINT", 0x0e, 0xff }, 59 { "CFG4ISTAT_INTR", 0x0f, 0xff }, 60 { "STATUS_OVERRUN", 0x10, 0xff }, 61 { "CFG4OVERRUN", 0x11, 0xff }, 62 { "ENTERING_NONPACK", 0x12, 0xff }, 63 { "TASKMGMT_FUNC_COMPLETE",0x13, 0xff }, 64 { "TASKMGMT_CMD_CMPLT_OKAY",0x14, 0xff }, 65 { "TRACEPOINT0", 0x15, 0xff }, 66 { "TRACEPOINT1", 0x16, 0xff }, 67 { "TRACEPOINT2", 0x17, 0xff }, 68 { "TRACEPOINT3", 0x18, 0xff }, 69 { "SAW_HWERR", 0x19, 0xff }, 70 { "BAD_SCB_STATUS", 0x1a, 0xff } 71 }; 72 73 int 74 ahd_seqintcode_print(u_int regvalue, u_int *cur_col, u_int wrap) 75 { 76 return (ahd_print_register(SEQINTCODE_parse_table, 27, "SEQINTCODE", 77 0x02, regvalue, cur_col, wrap)); 78 } 79 80 static ahd_reg_parse_entry_t CLRINT_parse_table[] = { 81 { "CLRSPLTINT", 0x01, 0x01 }, 82 { "CLRCMDINT", 0x02, 0x02 }, 83 { "CLRSEQINT", 0x04, 0x04 }, 84 { "CLRSCSIINT", 0x08, 0x08 }, 85 { "CLRPCIINT", 0x10, 0x10 }, 86 { "CLRSWTMINT", 0x20, 0x20 }, 87 { "CLRBRKADRINT", 0x40, 0x40 }, 88 { "CLRHWERRINT", 0x80, 0x80 } 89 }; 90 91 int 92 ahd_clrint_print(u_int regvalue, u_int *cur_col, u_int wrap) 93 { 94 return (ahd_print_register(CLRINT_parse_table, 8, "CLRINT", 95 0x03, regvalue, cur_col, wrap)); 96 } 97 98 static ahd_reg_parse_entry_t ERROR_parse_table[] = { 99 { "DSCTMOUT", 0x02, 0x02 }, 100 { "ILLOPCODE", 0x04, 0x04 }, 101 { "SQPARERR", 0x08, 0x08 }, 102 { "DPARERR", 0x10, 0x10 }, 103 { "MPARERR", 0x20, 0x20 }, 104 { "CIOACCESFAIL", 0x40, 0x40 }, 105 { "CIOPARERR", 0x80, 0x80 } 106 }; 107 108 int 109 ahd_error_print(u_int regvalue, u_int *cur_col, u_int wrap) 110 { 111 return (ahd_print_register(ERROR_parse_table, 7, "ERROR", 112 0x04, regvalue, cur_col, wrap)); 113 } 114 115 static ahd_reg_parse_entry_t CLRERR_parse_table[] = { 116 { "CLRDSCTMOUT", 0x02, 0x02 }, 117 { "CLRILLOPCODE", 0x04, 0x04 }, 118 { "CLRSQPARERR", 0x08, 0x08 }, 119 { "CLRDPARERR", 0x10, 0x10 }, 120 { "CLRMPARERR", 0x20, 0x20 }, 121 { "CLRCIOACCESFAIL", 0x40, 0x40 }, 122 { "CLRCIOPARERR", 0x80, 0x80 } 123 }; 124 125 int 126 ahd_clrerr_print(u_int regvalue, u_int *cur_col, u_int wrap) 127 { 128 return (ahd_print_register(CLRERR_parse_table, 7, "CLRERR", 129 0x04, regvalue, cur_col, wrap)); 130 } 131 132 static ahd_reg_parse_entry_t HCNTRL_parse_table[] = { 133 { "CHIPRST", 0x01, 0x01 }, 134 { "CHIPRSTACK", 0x01, 0x01 }, 135 { "INTEN", 0x02, 0x02 }, 136 { "PAUSE", 0x04, 0x04 }, 137 { "SWTIMER_START_B", 0x08, 0x08 }, 138 { "SWINT", 0x10, 0x10 }, 139 { "POWRDN", 0x40, 0x40 }, 140 { "SEQ_RESET", 0x80, 0x80 } 141 }; 142 143 int 144 ahd_hcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap) 145 { 146 return (ahd_print_register(HCNTRL_parse_table, 8, "HCNTRL", 147 0x05, regvalue, cur_col, wrap)); 148 } 149 150 int 151 ahd_hnscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap) 152 { 153 return (ahd_print_register(NULL, 0, "HNSCB_QOFF", 154 0x06, regvalue, cur_col, wrap)); 155 } 156 157 int 158 ahd_hescb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap) 159 { 160 return (ahd_print_register(NULL, 0, "HESCB_QOFF", 161 0x08, regvalue, cur_col, wrap)); 162 } 163 164 static ahd_reg_parse_entry_t HS_MAILBOX_parse_table[] = { 165 { "ENINT_COALESCE", 0x40, 0x40 }, 166 { "HOST_TQINPOS", 0x80, 0x80 } 167 }; 168 169 int 170 ahd_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap) 171 { 172 return (ahd_print_register(HS_MAILBOX_parse_table, 2, "HS_MAILBOX", 173 0x0b, regvalue, cur_col, wrap)); 174 } 175 176 static ahd_reg_parse_entry_t SEQINTSTAT_parse_table[] = { 177 { "SEQ_SPLTINT", 0x01, 0x01 }, 178 { "SEQ_PCIINT", 0x02, 0x02 }, 179 { "SEQ_SCSIINT", 0x04, 0x04 }, 180 { "SEQ_SEQINT", 0x08, 0x08 }, 181 { "SEQ_SWTMRTO", 0x10, 0x10 } 182 }; 183 184 int 185 ahd_seqintstat_print(u_int regvalue, u_int *cur_col, u_int wrap) 186 { 187 return (ahd_print_register(SEQINTSTAT_parse_table, 5, "SEQINTSTAT", 188 0x0c, regvalue, cur_col, wrap)); 189 } 190 191 static ahd_reg_parse_entry_t CLRSEQINTSTAT_parse_table[] = { 192 { "CLRSEQ_SPLTINT", 0x01, 0x01 }, 193 { "CLRSEQ_PCIINT", 0x02, 0x02 }, 194 { "CLRSEQ_SCSIINT", 0x04, 0x04 }, 195 { "CLRSEQ_SEQINT", 0x08, 0x08 }, 196 { "CLRSEQ_SWTMRTO", 0x10, 0x10 } 197 }; 198 199 int 200 ahd_clrseqintstat_print(u_int regvalue, u_int *cur_col, u_int wrap) 201 { 202 return (ahd_print_register(CLRSEQINTSTAT_parse_table, 5, "CLRSEQINTSTAT", 203 0x0c, regvalue, cur_col, wrap)); 204 } 205 206 int 207 ahd_swtimer_print(u_int regvalue, u_int *cur_col, u_int wrap) 208 { 209 return (ahd_print_register(NULL, 0, "SWTIMER", 210 0x0e, regvalue, cur_col, wrap)); 211 } 212 213 int 214 ahd_snscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap) 215 { 216 return (ahd_print_register(NULL, 0, "SNSCB_QOFF", 217 0x10, regvalue, cur_col, wrap)); 218 } 219 220 int 221 ahd_sescb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap) 222 { 223 return (ahd_print_register(NULL, 0, "SESCB_QOFF", 224 0x12, regvalue, cur_col, wrap)); 225 } 226 227 int 228 ahd_sdscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap) 229 { 230 return (ahd_print_register(NULL, 0, "SDSCB_QOFF", 231 0x14, regvalue, cur_col, wrap)); 232 } 233 234 static ahd_reg_parse_entry_t QOFF_CTLSTA_parse_table[] = { 235 { "SCB_QSIZE_4", 0x00, 0x0f }, 236 { "SCB_QSIZE_8", 0x01, 0x0f }, 237 { "SCB_QSIZE_16", 0x02, 0x0f }, 238 { "SCB_QSIZE_32", 0x03, 0x0f }, 239 { "SCB_QSIZE_64", 0x04, 0x0f }, 240 { "SCB_QSIZE_128", 0x05, 0x0f }, 241 { "SCB_QSIZE_256", 0x06, 0x0f }, 242 { "SCB_QSIZE_512", 0x07, 0x0f }, 243 { "SCB_QSIZE_1024", 0x08, 0x0f }, 244 { "SCB_QSIZE_2048", 0x09, 0x0f }, 245 { "SCB_QSIZE_4096", 0x0a, 0x0f }, 246 { "SCB_QSIZE_8192", 0x0b, 0x0f }, 247 { "SCB_QSIZE_16384", 0x0c, 0x0f }, 248 { "SCB_QSIZE", 0x0f, 0x0f }, 249 { "HS_MAILBOX_ACT", 0x10, 0x10 }, 250 { "SDSCB_ROLLOVR", 0x20, 0x20 }, 251 { "NEW_SCB_AVAIL", 0x40, 0x40 }, 252 { "EMPTY_SCB_AVAIL", 0x80, 0x80 } 253 }; 254 255 int 256 ahd_qoff_ctlsta_print(u_int regvalue, u_int *cur_col, u_int wrap) 257 { 258 return (ahd_print_register(QOFF_CTLSTA_parse_table, 18, "QOFF_CTLSTA", 259 0x16, regvalue, cur_col, wrap)); 260 } 261 262 static ahd_reg_parse_entry_t INTCTL_parse_table[] = { 263 { "SPLTINTEN", 0x01, 0x01 }, 264 { "SEQINTEN", 0x02, 0x02 }, 265 { "SCSIINTEN", 0x04, 0x04 }, 266 { "PCIINTEN", 0x08, 0x08 }, 267 { "AUTOCLRCMDINT", 0x10, 0x10 }, 268 { "SWTIMER_START", 0x20, 0x20 }, 269 { "SWTMINTEN", 0x40, 0x40 }, 270 { "SWTMINTMASK", 0x80, 0x80 } 271 }; 272 273 int 274 ahd_intctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 275 { 276 return (ahd_print_register(INTCTL_parse_table, 8, "INTCTL", 277 0x18, regvalue, cur_col, wrap)); 278 } 279 280 static ahd_reg_parse_entry_t DFCNTRL_parse_table[] = { 281 { "DIRECTIONEN", 0x01, 0x01 }, 282 { "FIFOFLUSH", 0x02, 0x02 }, 283 { "FIFOFLUSHACK", 0x02, 0x02 }, 284 { "DIRECTION", 0x04, 0x04 }, 285 { "DIRECTIONACK", 0x04, 0x04 }, 286 { "HDMAEN", 0x08, 0x08 }, 287 { "HDMAENACK", 0x08, 0x08 }, 288 { "SCSIEN", 0x20, 0x20 }, 289 { "SCSIENACK", 0x20, 0x20 }, 290 { "SCSIENWRDIS", 0x40, 0x40 }, 291 { "PRELOADEN", 0x80, 0x80 } 292 }; 293 294 int 295 ahd_dfcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap) 296 { 297 return (ahd_print_register(DFCNTRL_parse_table, 11, "DFCNTRL", 298 0x19, regvalue, cur_col, wrap)); 299 } 300 301 static ahd_reg_parse_entry_t DSCOMMAND0_parse_table[] = { 302 { "CIOPARCKEN", 0x01, 0x01 }, 303 { "DISABLE_TWATE", 0x02, 0x02 }, 304 { "EXTREQLCK", 0x10, 0x10 }, 305 { "MPARCKEN", 0x20, 0x20 }, 306 { "DPARCKEN", 0x40, 0x40 }, 307 { "CACHETHEN", 0x80, 0x80 } 308 }; 309 310 int 311 ahd_dscommand0_print(u_int regvalue, u_int *cur_col, u_int wrap) 312 { 313 return (ahd_print_register(DSCOMMAND0_parse_table, 6, "DSCOMMAND0", 314 0x19, regvalue, cur_col, wrap)); 315 } 316 317 static ahd_reg_parse_entry_t DFSTATUS_parse_table[] = { 318 { "FIFOEMP", 0x01, 0x01 }, 319 { "FIFOFULL", 0x02, 0x02 }, 320 { "DFTHRESH", 0x04, 0x04 }, 321 { "HDONE", 0x08, 0x08 }, 322 { "MREQPEND", 0x10, 0x10 }, 323 { "PKT_PRELOAD_AVAIL", 0x40, 0x40 }, 324 { "PRELOAD_AVAIL", 0x80, 0x80 } 325 }; 326 327 int 328 ahd_dfstatus_print(u_int regvalue, u_int *cur_col, u_int wrap) 329 { 330 return (ahd_print_register(DFSTATUS_parse_table, 7, "DFSTATUS", 331 0x1a, regvalue, cur_col, wrap)); 332 } 333 334 static ahd_reg_parse_entry_t SG_CACHE_SHADOW_parse_table[] = { 335 { "LAST_SEG_DONE", 0x01, 0x01 }, 336 { "LAST_SEG", 0x02, 0x02 }, 337 { "ODD_SEG", 0x04, 0x04 }, 338 { "SG_ADDR_MASK", 0xf8, 0xf8 } 339 }; 340 341 int 342 ahd_sg_cache_shadow_print(u_int regvalue, u_int *cur_col, u_int wrap) 343 { 344 return (ahd_print_register(SG_CACHE_SHADOW_parse_table, 4, "SG_CACHE_SHADOW", 345 0x1b, regvalue, cur_col, wrap)); 346 } 347 348 static ahd_reg_parse_entry_t SG_CACHE_PRE_parse_table[] = { 349 { "LAST_SEG", 0x02, 0x02 }, 350 { "ODD_SEG", 0x04, 0x04 }, 351 { "SG_ADDR_MASK", 0xf8, 0xf8 } 352 }; 353 354 int 355 ahd_sg_cache_pre_print(u_int regvalue, u_int *cur_col, u_int wrap) 356 { 357 return (ahd_print_register(SG_CACHE_PRE_parse_table, 3, "SG_CACHE_PRE", 358 0x1b, regvalue, cur_col, wrap)); 359 } 360 361 static ahd_reg_parse_entry_t ARBCTL_parse_table[] = { 362 { "USE_TIME", 0x07, 0x07 }, 363 { "RETRY_SWEN", 0x08, 0x08 }, 364 { "RESET_HARB", 0x80, 0x80 } 365 }; 366 367 int 368 ahd_arbctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 369 { 370 return (ahd_print_register(ARBCTL_parse_table, 3, "ARBCTL", 371 0x1b, regvalue, cur_col, wrap)); 372 } 373 374 int 375 ahd_lqin_print(u_int regvalue, u_int *cur_col, u_int wrap) 376 { 377 return (ahd_print_register(NULL, 0, "LQIN", 378 0x20, regvalue, cur_col, wrap)); 379 } 380 381 int 382 ahd_typeptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 383 { 384 return (ahd_print_register(NULL, 0, "TYPEPTR", 385 0x20, regvalue, cur_col, wrap)); 386 } 387 388 int 389 ahd_tagptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 390 { 391 return (ahd_print_register(NULL, 0, "TAGPTR", 392 0x21, regvalue, cur_col, wrap)); 393 } 394 395 int 396 ahd_lunptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 397 { 398 return (ahd_print_register(NULL, 0, "LUNPTR", 399 0x22, regvalue, cur_col, wrap)); 400 } 401 402 int 403 ahd_datalenptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 404 { 405 return (ahd_print_register(NULL, 0, "DATALENPTR", 406 0x23, regvalue, cur_col, wrap)); 407 } 408 409 int 410 ahd_statlenptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 411 { 412 return (ahd_print_register(NULL, 0, "STATLENPTR", 413 0x24, regvalue, cur_col, wrap)); 414 } 415 416 int 417 ahd_cmdlenptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 418 { 419 return (ahd_print_register(NULL, 0, "CMDLENPTR", 420 0x25, regvalue, cur_col, wrap)); 421 } 422 423 int 424 ahd_attrptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 425 { 426 return (ahd_print_register(NULL, 0, "ATTRPTR", 427 0x26, regvalue, cur_col, wrap)); 428 } 429 430 int 431 ahd_flagptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 432 { 433 return (ahd_print_register(NULL, 0, "FLAGPTR", 434 0x27, regvalue, cur_col, wrap)); 435 } 436 437 int 438 ahd_cmdptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 439 { 440 return (ahd_print_register(NULL, 0, "CMDPTR", 441 0x28, regvalue, cur_col, wrap)); 442 } 443 444 int 445 ahd_qnextptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 446 { 447 return (ahd_print_register(NULL, 0, "QNEXTPTR", 448 0x29, regvalue, cur_col, wrap)); 449 } 450 451 int 452 ahd_idptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 453 { 454 return (ahd_print_register(NULL, 0, "IDPTR", 455 0x2a, regvalue, cur_col, wrap)); 456 } 457 458 int 459 ahd_abrtbyteptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 460 { 461 return (ahd_print_register(NULL, 0, "ABRTBYTEPTR", 462 0x2b, regvalue, cur_col, wrap)); 463 } 464 465 int 466 ahd_abrtbitptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 467 { 468 return (ahd_print_register(NULL, 0, "ABRTBITPTR", 469 0x2c, regvalue, cur_col, wrap)); 470 } 471 472 int 473 ahd_maxcmdbytes_print(u_int regvalue, u_int *cur_col, u_int wrap) 474 { 475 return (ahd_print_register(NULL, 0, "MAXCMDBYTES", 476 0x2d, regvalue, cur_col, wrap)); 477 } 478 479 int 480 ahd_maxcmd2rcv_print(u_int regvalue, u_int *cur_col, u_int wrap) 481 { 482 return (ahd_print_register(NULL, 0, "MAXCMD2RCV", 483 0x2e, regvalue, cur_col, wrap)); 484 } 485 486 int 487 ahd_shortthresh_print(u_int regvalue, u_int *cur_col, u_int wrap) 488 { 489 return (ahd_print_register(NULL, 0, "SHORTTHRESH", 490 0x2f, regvalue, cur_col, wrap)); 491 } 492 493 static ahd_reg_parse_entry_t LUNLEN_parse_table[] = { 494 { "ILUNLEN", 0x0f, 0x0f }, 495 { "TLUNLEN", 0xf0, 0xf0 } 496 }; 497 498 int 499 ahd_lunlen_print(u_int regvalue, u_int *cur_col, u_int wrap) 500 { 501 return (ahd_print_register(LUNLEN_parse_table, 2, "LUNLEN", 502 0x30, regvalue, cur_col, wrap)); 503 } 504 505 int 506 ahd_cdblimit_print(u_int regvalue, u_int *cur_col, u_int wrap) 507 { 508 return (ahd_print_register(NULL, 0, "CDBLIMIT", 509 0x31, regvalue, cur_col, wrap)); 510 } 511 512 int 513 ahd_maxcmd_print(u_int regvalue, u_int *cur_col, u_int wrap) 514 { 515 return (ahd_print_register(NULL, 0, "MAXCMD", 516 0x32, regvalue, cur_col, wrap)); 517 } 518 519 int 520 ahd_maxcmdcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 521 { 522 return (ahd_print_register(NULL, 0, "MAXCMDCNT", 523 0x33, regvalue, cur_col, wrap)); 524 } 525 526 int 527 ahd_lqrsvd01_print(u_int regvalue, u_int *cur_col, u_int wrap) 528 { 529 return (ahd_print_register(NULL, 0, "LQRSVD01", 530 0x34, regvalue, cur_col, wrap)); 531 } 532 533 int 534 ahd_lqrsvd16_print(u_int regvalue, u_int *cur_col, u_int wrap) 535 { 536 return (ahd_print_register(NULL, 0, "LQRSVD16", 537 0x35, regvalue, cur_col, wrap)); 538 } 539 540 int 541 ahd_lqrsvd17_print(u_int regvalue, u_int *cur_col, u_int wrap) 542 { 543 return (ahd_print_register(NULL, 0, "LQRSVD17", 544 0x36, regvalue, cur_col, wrap)); 545 } 546 547 int 548 ahd_cmdrsvd0_print(u_int regvalue, u_int *cur_col, u_int wrap) 549 { 550 return (ahd_print_register(NULL, 0, "CMDRSVD0", 551 0x37, regvalue, cur_col, wrap)); 552 } 553 554 static ahd_reg_parse_entry_t LQCTL0_parse_table[] = { 555 { "LQ0INITGCLT", 0x03, 0x03 }, 556 { "LQ0TARGCLT", 0x0c, 0x0c }, 557 { "LQIINITGCLT", 0x30, 0x30 }, 558 { "LQITARGCLT", 0xc0, 0xc0 } 559 }; 560 561 int 562 ahd_lqctl0_print(u_int regvalue, u_int *cur_col, u_int wrap) 563 { 564 return (ahd_print_register(LQCTL0_parse_table, 4, "LQCTL0", 565 0x38, regvalue, cur_col, wrap)); 566 } 567 568 static ahd_reg_parse_entry_t LQCTL1_parse_table[] = { 569 { "ABORTPENDING", 0x01, 0x01 }, 570 { "SINGLECMD", 0x02, 0x02 }, 571 { "PCI2PCI", 0x04, 0x04 } 572 }; 573 574 int 575 ahd_lqctl1_print(u_int regvalue, u_int *cur_col, u_int wrap) 576 { 577 return (ahd_print_register(LQCTL1_parse_table, 3, "LQCTL1", 578 0x38, regvalue, cur_col, wrap)); 579 } 580 581 static ahd_reg_parse_entry_t LQCTL2_parse_table[] = { 582 { "LQOPAUSE", 0x01, 0x01 }, 583 { "LQOTOIDLE", 0x02, 0x02 }, 584 { "LQOCONTINUE", 0x04, 0x04 }, 585 { "LQORETRY", 0x08, 0x08 }, 586 { "LQIPAUSE", 0x10, 0x10 }, 587 { "LQITOIDLE", 0x20, 0x20 }, 588 { "LQICONTINUE", 0x40, 0x40 }, 589 { "LQIRETRY", 0x80, 0x80 } 590 }; 591 592 int 593 ahd_lqctl2_print(u_int regvalue, u_int *cur_col, u_int wrap) 594 { 595 return (ahd_print_register(LQCTL2_parse_table, 8, "LQCTL2", 596 0x39, regvalue, cur_col, wrap)); 597 } 598 599 static ahd_reg_parse_entry_t SCSBIST0_parse_table[] = { 600 { "OSBISTRUN", 0x01, 0x01 }, 601 { "OSBISTDONE", 0x02, 0x02 }, 602 { "OSBISTERR", 0x04, 0x04 }, 603 { "GSBISTRUN", 0x10, 0x10 }, 604 { "GSBISTDONE", 0x20, 0x20 }, 605 { "GSBISTERR", 0x40, 0x40 } 606 }; 607 608 int 609 ahd_scsbist0_print(u_int regvalue, u_int *cur_col, u_int wrap) 610 { 611 return (ahd_print_register(SCSBIST0_parse_table, 6, "SCSBIST0", 612 0x39, regvalue, cur_col, wrap)); 613 } 614 615 static ahd_reg_parse_entry_t SCSISEQ0_parse_table[] = { 616 { "SCSIRSTO", 0x01, 0x01 }, 617 { "FORCEBUSFREE", 0x10, 0x10 }, 618 { "ENARBO", 0x20, 0x20 }, 619 { "ENSELO", 0x40, 0x40 }, 620 { "TEMODEO", 0x80, 0x80 } 621 }; 622 623 int 624 ahd_scsiseq0_print(u_int regvalue, u_int *cur_col, u_int wrap) 625 { 626 return (ahd_print_register(SCSISEQ0_parse_table, 5, "SCSISEQ0", 627 0x3a, regvalue, cur_col, wrap)); 628 } 629 630 static ahd_reg_parse_entry_t SCSBIST1_parse_table[] = { 631 { "NTBISTRUN", 0x01, 0x01 }, 632 { "NTBISTDONE", 0x02, 0x02 }, 633 { "NTBISTERR", 0x04, 0x04 } 634 }; 635 636 int 637 ahd_scsbist1_print(u_int regvalue, u_int *cur_col, u_int wrap) 638 { 639 return (ahd_print_register(SCSBIST1_parse_table, 3, "SCSBIST1", 640 0x3a, regvalue, cur_col, wrap)); 641 } 642 643 static ahd_reg_parse_entry_t SCSISEQ1_parse_table[] = { 644 { "ALTSTIM", 0x01, 0x01 }, 645 { "ENAUTOATNP", 0x02, 0x02 }, 646 { "MANUALP", 0x0c, 0x0c }, 647 { "ENRSELI", 0x10, 0x10 }, 648 { "ENSELI", 0x20, 0x20 }, 649 { "MANUALCTL", 0x40, 0x40 } 650 }; 651 652 int 653 ahd_scsiseq1_print(u_int regvalue, u_int *cur_col, u_int wrap) 654 { 655 return (ahd_print_register(SCSISEQ1_parse_table, 6, "SCSISEQ1", 656 0x3b, regvalue, cur_col, wrap)); 657 } 658 659 int 660 ahd_businitid_print(u_int regvalue, u_int *cur_col, u_int wrap) 661 { 662 return (ahd_print_register(NULL, 0, "BUSINITID", 663 0x3c, regvalue, cur_col, wrap)); 664 } 665 666 static ahd_reg_parse_entry_t SXFRCTL0_parse_table[] = { 667 { "SPIOEN", 0x08, 0x08 }, 668 { "BIOSCANCELEN", 0x10, 0x10 }, 669 { "DFPEXP", 0x40, 0x40 }, 670 { "DFON", 0x80, 0x80 } 671 }; 672 673 int 674 ahd_sxfrctl0_print(u_int regvalue, u_int *cur_col, u_int wrap) 675 { 676 return (ahd_print_register(SXFRCTL0_parse_table, 4, "SXFRCTL0", 677 0x3c, regvalue, cur_col, wrap)); 678 } 679 680 int 681 ahd_dlcount_print(u_int regvalue, u_int *cur_col, u_int wrap) 682 { 683 return (ahd_print_register(NULL, 0, "DLCOUNT", 684 0x3c, regvalue, cur_col, wrap)); 685 } 686 687 static ahd_reg_parse_entry_t SXFRCTL1_parse_table[] = { 688 { "STPWEN", 0x01, 0x01 }, 689 { "ACTNEGEN", 0x02, 0x02 }, 690 { "ENSTIMER", 0x04, 0x04 }, 691 { "STIMESEL", 0x18, 0x18 }, 692 { "ENSPCHK", 0x20, 0x20 }, 693 { "ENSACHK", 0x40, 0x40 }, 694 { "BITBUCKET", 0x80, 0x80 } 695 }; 696 697 int 698 ahd_sxfrctl1_print(u_int regvalue, u_int *cur_col, u_int wrap) 699 { 700 return (ahd_print_register(SXFRCTL1_parse_table, 7, "SXFRCTL1", 701 0x3d, regvalue, cur_col, wrap)); 702 } 703 704 int 705 ahd_bustargid_print(u_int regvalue, u_int *cur_col, u_int wrap) 706 { 707 return (ahd_print_register(NULL, 0, "BUSTARGID", 708 0x3e, regvalue, cur_col, wrap)); 709 } 710 711 static ahd_reg_parse_entry_t SXFRCTL2_parse_table[] = { 712 { "ASU", 0x07, 0x07 }, 713 { "CMDDMAEN", 0x08, 0x08 }, 714 { "AUTORSTDIS", 0x10, 0x10 } 715 }; 716 717 int 718 ahd_sxfrctl2_print(u_int regvalue, u_int *cur_col, u_int wrap) 719 { 720 return (ahd_print_register(SXFRCTL2_parse_table, 3, "SXFRCTL2", 721 0x3e, regvalue, cur_col, wrap)); 722 } 723 724 static ahd_reg_parse_entry_t DFFSTAT_parse_table[] = { 725 { "CURRFIFO_0", 0x00, 0x03 }, 726 { "CURRFIFO_1", 0x01, 0x03 }, 727 { "CURRFIFO_NONE", 0x03, 0x03 }, 728 { "FIFO0FREE", 0x10, 0x10 }, 729 { "FIFO1FREE", 0x20, 0x20 }, 730 { "CURRFIFO", 0x03, 0x03 } 731 }; 732 733 int 734 ahd_dffstat_print(u_int regvalue, u_int *cur_col, u_int wrap) 735 { 736 return (ahd_print_register(DFFSTAT_parse_table, 6, "DFFSTAT", 737 0x3f, regvalue, cur_col, wrap)); 738 } 739 740 static ahd_reg_parse_entry_t SCSISIGO_parse_table[] = { 741 { "P_DATAOUT", 0x00, 0xe0 }, 742 { "P_DATAOUT_DT", 0x20, 0xe0 }, 743 { "P_DATAIN", 0x40, 0xe0 }, 744 { "P_DATAIN_DT", 0x60, 0xe0 }, 745 { "P_COMMAND", 0x80, 0xe0 }, 746 { "P_MESGOUT", 0xa0, 0xe0 }, 747 { "P_STATUS", 0xc0, 0xe0 }, 748 { "P_MESGIN", 0xe0, 0xe0 }, 749 { "ACKO", 0x01, 0x01 }, 750 { "REQO", 0x02, 0x02 }, 751 { "BSYO", 0x04, 0x04 }, 752 { "SELO", 0x08, 0x08 }, 753 { "ATNO", 0x10, 0x10 }, 754 { "MSGO", 0x20, 0x20 }, 755 { "IOO", 0x40, 0x40 }, 756 { "CDO", 0x80, 0x80 }, 757 { "PHASE_MASK", 0xe0, 0xe0 } 758 }; 759 760 int 761 ahd_scsisigo_print(u_int regvalue, u_int *cur_col, u_int wrap) 762 { 763 return (ahd_print_register(SCSISIGO_parse_table, 17, "SCSISIGO", 764 0x40, regvalue, cur_col, wrap)); 765 } 766 767 int 768 ahd_multargid_print(u_int regvalue, u_int *cur_col, u_int wrap) 769 { 770 return (ahd_print_register(NULL, 0, "MULTARGID", 771 0x40, regvalue, cur_col, wrap)); 772 } 773 774 static ahd_reg_parse_entry_t SCSISIGI_parse_table[] = { 775 { "P_DATAOUT", 0x00, 0xe0 }, 776 { "P_DATAOUT_DT", 0x20, 0xe0 }, 777 { "P_DATAIN", 0x40, 0xe0 }, 778 { "P_DATAIN_DT", 0x60, 0xe0 }, 779 { "P_COMMAND", 0x80, 0xe0 }, 780 { "P_MESGOUT", 0xa0, 0xe0 }, 781 { "P_STATUS", 0xc0, 0xe0 }, 782 { "P_MESGIN", 0xe0, 0xe0 }, 783 { "ACKI", 0x01, 0x01 }, 784 { "REQI", 0x02, 0x02 }, 785 { "BSYI", 0x04, 0x04 }, 786 { "SELI", 0x08, 0x08 }, 787 { "ATNI", 0x10, 0x10 }, 788 { "MSGI", 0x20, 0x20 }, 789 { "IOI", 0x40, 0x40 }, 790 { "CDI", 0x80, 0x80 }, 791 { "PHASE_MASK", 0xe0, 0xe0 } 792 }; 793 794 int 795 ahd_scsisigi_print(u_int regvalue, u_int *cur_col, u_int wrap) 796 { 797 return (ahd_print_register(SCSISIGI_parse_table, 17, "SCSISIGI", 798 0x41, regvalue, cur_col, wrap)); 799 } 800 801 static ahd_reg_parse_entry_t SCSIPHASE_parse_table[] = { 802 { "DATA_OUT_PHASE", 0x01, 0x03 }, 803 { "DATA_IN_PHASE", 0x02, 0x03 }, 804 { "DATA_PHASE_MASK", 0x03, 0x03 }, 805 { "MSG_OUT_PHASE", 0x04, 0x04 }, 806 { "MSG_IN_PHASE", 0x08, 0x08 }, 807 { "COMMAND_PHASE", 0x10, 0x10 }, 808 { "STATUS_PHASE", 0x20, 0x20 } 809 }; 810 811 int 812 ahd_scsiphase_print(u_int regvalue, u_int *cur_col, u_int wrap) 813 { 814 return (ahd_print_register(SCSIPHASE_parse_table, 7, "SCSIPHASE", 815 0x42, regvalue, cur_col, wrap)); 816 } 817 818 int 819 ahd_scsidat0_img_print(u_int regvalue, u_int *cur_col, u_int wrap) 820 { 821 return (ahd_print_register(NULL, 0, "SCSIDAT0_IMG", 822 0x43, regvalue, cur_col, wrap)); 823 } 824 825 int 826 ahd_scsidat_print(u_int regvalue, u_int *cur_col, u_int wrap) 827 { 828 return (ahd_print_register(NULL, 0, "SCSIDAT", 829 0x44, regvalue, cur_col, wrap)); 830 } 831 832 int 833 ahd_scsibus_print(u_int regvalue, u_int *cur_col, u_int wrap) 834 { 835 return (ahd_print_register(NULL, 0, "SCSIBUS", 836 0x46, regvalue, cur_col, wrap)); 837 } 838 839 static ahd_reg_parse_entry_t TARGIDIN_parse_table[] = { 840 { "TARGID", 0x0f, 0x0f }, 841 { "CLKOUT", 0x80, 0x80 } 842 }; 843 844 int 845 ahd_targidin_print(u_int regvalue, u_int *cur_col, u_int wrap) 846 { 847 return (ahd_print_register(TARGIDIN_parse_table, 2, "TARGIDIN", 848 0x48, regvalue, cur_col, wrap)); 849 } 850 851 static ahd_reg_parse_entry_t SELID_parse_table[] = { 852 { "ONEBIT", 0x08, 0x08 }, 853 { "SELID_MASK", 0xf0, 0xf0 } 854 }; 855 856 int 857 ahd_selid_print(u_int regvalue, u_int *cur_col, u_int wrap) 858 { 859 return (ahd_print_register(SELID_parse_table, 2, "SELID", 860 0x49, regvalue, cur_col, wrap)); 861 } 862 863 static ahd_reg_parse_entry_t OPTIONMODE_parse_table[] = { 864 { "AUTO_MSGOUT_DE", 0x02, 0x02 }, 865 { "ENDGFORMCHK", 0x04, 0x04 }, 866 { "BUSFREEREV", 0x10, 0x10 }, 867 { "BIASCANCTL", 0x20, 0x20 }, 868 { "AUTOACKEN", 0x40, 0x40 }, 869 { "BIOSCANCTL", 0x80, 0x80 }, 870 { "OPTIONMODE_DEFAULTS",0x02, 0x02 } 871 }; 872 873 int 874 ahd_optionmode_print(u_int regvalue, u_int *cur_col, u_int wrap) 875 { 876 return (ahd_print_register(OPTIONMODE_parse_table, 7, "OPTIONMODE", 877 0x4a, regvalue, cur_col, wrap)); 878 } 879 880 static ahd_reg_parse_entry_t SBLKCTL_parse_table[] = { 881 { "SELWIDE", 0x02, 0x02 }, 882 { "ENAB20", 0x04, 0x04 }, 883 { "ENAB40", 0x08, 0x08 }, 884 { "DIAGLEDON", 0x40, 0x40 }, 885 { "DIAGLEDEN", 0x80, 0x80 } 886 }; 887 888 int 889 ahd_sblkctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 890 { 891 return (ahd_print_register(SBLKCTL_parse_table, 5, "SBLKCTL", 892 0x4a, regvalue, cur_col, wrap)); 893 } 894 895 static ahd_reg_parse_entry_t SIMODE0_parse_table[] = { 896 { "ENARBDO", 0x01, 0x01 }, 897 { "ENSPIORDY", 0x02, 0x02 }, 898 { "ENOVERRUN", 0x04, 0x04 }, 899 { "ENIOERR", 0x08, 0x08 }, 900 { "ENSELINGO", 0x10, 0x10 }, 901 { "ENSELDI", 0x20, 0x20 }, 902 { "ENSELDO", 0x40, 0x40 } 903 }; 904 905 int 906 ahd_simode0_print(u_int regvalue, u_int *cur_col, u_int wrap) 907 { 908 return (ahd_print_register(SIMODE0_parse_table, 7, "SIMODE0", 909 0x4b, regvalue, cur_col, wrap)); 910 } 911 912 static ahd_reg_parse_entry_t SSTAT0_parse_table[] = { 913 { "ARBDO", 0x01, 0x01 }, 914 { "SPIORDY", 0x02, 0x02 }, 915 { "OVERRUN", 0x04, 0x04 }, 916 { "IOERR", 0x08, 0x08 }, 917 { "SELINGO", 0x10, 0x10 }, 918 { "SELDI", 0x20, 0x20 }, 919 { "SELDO", 0x40, 0x40 }, 920 { "TARGET", 0x80, 0x80 } 921 }; 922 923 int 924 ahd_sstat0_print(u_int regvalue, u_int *cur_col, u_int wrap) 925 { 926 return (ahd_print_register(SSTAT0_parse_table, 8, "SSTAT0", 927 0x4b, regvalue, cur_col, wrap)); 928 } 929 930 static ahd_reg_parse_entry_t CLRSINT0_parse_table[] = { 931 { "CLRARBDO", 0x01, 0x01 }, 932 { "CLRSPIORDY", 0x02, 0x02 }, 933 { "CLROVERRUN", 0x04, 0x04 }, 934 { "CLRIOERR", 0x08, 0x08 }, 935 { "CLRSELINGO", 0x10, 0x10 }, 936 { "CLRSELDI", 0x20, 0x20 }, 937 { "CLRSELDO", 0x40, 0x40 } 938 }; 939 940 int 941 ahd_clrsint0_print(u_int regvalue, u_int *cur_col, u_int wrap) 942 { 943 return (ahd_print_register(CLRSINT0_parse_table, 7, "CLRSINT0", 944 0x4b, regvalue, cur_col, wrap)); 945 } 946 947 static ahd_reg_parse_entry_t SSTAT1_parse_table[] = { 948 { "REQINIT", 0x01, 0x01 }, 949 { "STRB2FAST", 0x02, 0x02 }, 950 { "SCSIPERR", 0x04, 0x04 }, 951 { "BUSFREE", 0x08, 0x08 }, 952 { "PHASEMIS", 0x10, 0x10 }, 953 { "SCSIRSTI", 0x20, 0x20 }, 954 { "ATNTARG", 0x40, 0x40 }, 955 { "SELTO", 0x80, 0x80 } 956 }; 957 958 int 959 ahd_sstat1_print(u_int regvalue, u_int *cur_col, u_int wrap) 960 { 961 return (ahd_print_register(SSTAT1_parse_table, 8, "SSTAT1", 962 0x4c, regvalue, cur_col, wrap)); 963 } 964 965 static ahd_reg_parse_entry_t CLRSINT1_parse_table[] = { 966 { "CLRREQINIT", 0x01, 0x01 }, 967 { "CLRSTRB2FAST", 0x02, 0x02 }, 968 { "CLRSCSIPERR", 0x04, 0x04 }, 969 { "CLRBUSFREE", 0x08, 0x08 }, 970 { "CLRSCSIRSTI", 0x20, 0x20 }, 971 { "CLRATNO", 0x40, 0x40 }, 972 { "CLRSELTIMEO", 0x80, 0x80 } 973 }; 974 975 int 976 ahd_clrsint1_print(u_int regvalue, u_int *cur_col, u_int wrap) 977 { 978 return (ahd_print_register(CLRSINT1_parse_table, 7, "CLRSINT1", 979 0x4c, regvalue, cur_col, wrap)); 980 } 981 982 static ahd_reg_parse_entry_t SSTAT2_parse_table[] = { 983 { "BUSFREE_LQO", 0x40, 0xc0 }, 984 { "BUSFREE_DFF0", 0x80, 0xc0 }, 985 { "BUSFREE_DFF1", 0xc0, 0xc0 }, 986 { "DMADONE", 0x01, 0x01 }, 987 { "SDONE", 0x02, 0x02 }, 988 { "WIDE_RES", 0x04, 0x04 }, 989 { "BSYX", 0x08, 0x08 }, 990 { "EXP_ACTIVE", 0x10, 0x10 }, 991 { "NONPACKREQ", 0x20, 0x20 }, 992 { "BUSFREETIME", 0xc0, 0xc0 } 993 }; 994 995 int 996 ahd_sstat2_print(u_int regvalue, u_int *cur_col, u_int wrap) 997 { 998 return (ahd_print_register(SSTAT2_parse_table, 10, "SSTAT2", 999 0x4d, regvalue, cur_col, wrap)); 1000 } 1001 1002 static ahd_reg_parse_entry_t CLRSINT2_parse_table[] = { 1003 { "CLRDMADONE", 0x01, 0x01 }, 1004 { "CLRSDONE", 0x02, 0x02 }, 1005 { "CLRWIDE_RES", 0x04, 0x04 }, 1006 { "CLRNONPACKREQ", 0x20, 0x20 } 1007 }; 1008 1009 int 1010 ahd_clrsint2_print(u_int regvalue, u_int *cur_col, u_int wrap) 1011 { 1012 return (ahd_print_register(CLRSINT2_parse_table, 4, "CLRSINT2", 1013 0x4d, regvalue, cur_col, wrap)); 1014 } 1015 1016 static ahd_reg_parse_entry_t SIMODE2_parse_table[] = { 1017 { "ENDMADONE", 0x01, 0x01 }, 1018 { "ENSDONE", 0x02, 0x02 }, 1019 { "ENWIDE_RES", 0x04, 0x04 } 1020 }; 1021 1022 int 1023 ahd_simode2_print(u_int regvalue, u_int *cur_col, u_int wrap) 1024 { 1025 return (ahd_print_register(SIMODE2_parse_table, 3, "SIMODE2", 1026 0x4d, regvalue, cur_col, wrap)); 1027 } 1028 1029 static ahd_reg_parse_entry_t PERRDIAG_parse_table[] = { 1030 { "DTERR", 0x01, 0x01 }, 1031 { "DGFORMERR", 0x02, 0x02 }, 1032 { "CRCERR", 0x04, 0x04 }, 1033 { "AIPERR", 0x08, 0x08 }, 1034 { "PARITYERR", 0x10, 0x10 }, 1035 { "PREVPHASE", 0x20, 0x20 }, 1036 { "HIPERR", 0x40, 0x40 }, 1037 { "HIZERO", 0x80, 0x80 } 1038 }; 1039 1040 int 1041 ahd_perrdiag_print(u_int regvalue, u_int *cur_col, u_int wrap) 1042 { 1043 return (ahd_print_register(PERRDIAG_parse_table, 8, "PERRDIAG", 1044 0x4e, regvalue, cur_col, wrap)); 1045 } 1046 1047 int 1048 ahd_lqistate_print(u_int regvalue, u_int *cur_col, u_int wrap) 1049 { 1050 return (ahd_print_register(NULL, 0, "LQISTATE", 1051 0x4e, regvalue, cur_col, wrap)); 1052 } 1053 1054 int 1055 ahd_soffcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1056 { 1057 return (ahd_print_register(NULL, 0, "SOFFCNT", 1058 0x4f, regvalue, cur_col, wrap)); 1059 } 1060 1061 int 1062 ahd_lqostate_print(u_int regvalue, u_int *cur_col, u_int wrap) 1063 { 1064 return (ahd_print_register(NULL, 0, "LQOSTATE", 1065 0x4f, regvalue, cur_col, wrap)); 1066 } 1067 1068 static ahd_reg_parse_entry_t LQISTAT0_parse_table[] = { 1069 { "LQIATNCMD", 0x01, 0x01 }, 1070 { "LQIATNLQ", 0x02, 0x02 }, 1071 { "LQIBADLQT", 0x04, 0x04 }, 1072 { "LQICRCT2", 0x08, 0x08 }, 1073 { "LQICRCT1", 0x10, 0x10 }, 1074 { "LQIATNQAS", 0x20, 0x20 } 1075 }; 1076 1077 int 1078 ahd_lqistat0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1079 { 1080 return (ahd_print_register(LQISTAT0_parse_table, 6, "LQISTAT0", 1081 0x50, regvalue, cur_col, wrap)); 1082 } 1083 1084 static ahd_reg_parse_entry_t CLRLQIINT0_parse_table[] = { 1085 { "CLRLQIATNCMD", 0x01, 0x01 }, 1086 { "CLRLQIATNLQ", 0x02, 0x02 }, 1087 { "CLRLQIBADLQT", 0x04, 0x04 }, 1088 { "CLRLQICRCT2", 0x08, 0x08 }, 1089 { "CLRLQICRCT1", 0x10, 0x10 }, 1090 { "CLRLQIATNQAS", 0x20, 0x20 } 1091 }; 1092 1093 int 1094 ahd_clrlqiint0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1095 { 1096 return (ahd_print_register(CLRLQIINT0_parse_table, 6, "CLRLQIINT0", 1097 0x50, regvalue, cur_col, wrap)); 1098 } 1099 1100 static ahd_reg_parse_entry_t LQIMODE0_parse_table[] = { 1101 { "ENLQIATNCMD", 0x01, 0x01 }, 1102 { "ENLQIATNLQ", 0x02, 0x02 }, 1103 { "ENLQIBADLQT", 0x04, 0x04 }, 1104 { "ENLQICRCT2", 0x08, 0x08 }, 1105 { "ENLQICRCT1", 0x10, 0x10 }, 1106 { "ENLQIATNQASK", 0x20, 0x20 } 1107 }; 1108 1109 int 1110 ahd_lqimode0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1111 { 1112 return (ahd_print_register(LQIMODE0_parse_table, 6, "LQIMODE0", 1113 0x50, regvalue, cur_col, wrap)); 1114 } 1115 1116 static ahd_reg_parse_entry_t LQISTAT1_parse_table[] = { 1117 { "LQIOVERI_NLQ", 0x01, 0x01 }, 1118 { "LQIOVERI_LQ", 0x02, 0x02 }, 1119 { "LQIBADLQI", 0x04, 0x04 }, 1120 { "LQICRCI_NLQ", 0x08, 0x08 }, 1121 { "LQICRCI_LQ", 0x10, 0x10 }, 1122 { "LQIABORT", 0x20, 0x20 }, 1123 { "LQIPHASE_NLQ", 0x40, 0x40 }, 1124 { "LQIPHASE_LQ", 0x80, 0x80 } 1125 }; 1126 1127 int 1128 ahd_lqistat1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1129 { 1130 return (ahd_print_register(LQISTAT1_parse_table, 8, "LQISTAT1", 1131 0x51, regvalue, cur_col, wrap)); 1132 } 1133 1134 static ahd_reg_parse_entry_t CLRLQIINT1_parse_table[] = { 1135 { "CLRLQIOVERI_NLQ", 0x01, 0x01 }, 1136 { "CLRLQIOVERI_LQ", 0x02, 0x02 }, 1137 { "CLRLQIBADLQI", 0x04, 0x04 }, 1138 { "CLRLQICRCI_NLQ", 0x08, 0x08 }, 1139 { "CLRLQICRCI_LQ", 0x10, 0x10 }, 1140 { "CLRLIQABORT", 0x20, 0x20 }, 1141 { "CLRLQIPHASE_NLQ", 0x40, 0x40 }, 1142 { "CLRLQIPHASE_LQ", 0x80, 0x80 } 1143 }; 1144 1145 int 1146 ahd_clrlqiint1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1147 { 1148 return (ahd_print_register(CLRLQIINT1_parse_table, 8, "CLRLQIINT1", 1149 0x51, regvalue, cur_col, wrap)); 1150 } 1151 1152 static ahd_reg_parse_entry_t LQIMODE1_parse_table[] = { 1153 { "ENLQIOVERI_NLQ", 0x01, 0x01 }, 1154 { "ENLQIOVERI_LQ", 0x02, 0x02 }, 1155 { "ENLQIBADLQI", 0x04, 0x04 }, 1156 { "ENLQICRCI_NLQ", 0x08, 0x08 }, 1157 { "ENLQICRCI_LQ", 0x10, 0x10 }, 1158 { "ENLIQABORT", 0x20, 0x20 }, 1159 { "ENLQIPHASE_NLQ", 0x40, 0x40 }, 1160 { "ENLQIPHASE_LQ", 0x80, 0x80 } 1161 }; 1162 1163 int 1164 ahd_lqimode1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1165 { 1166 return (ahd_print_register(LQIMODE1_parse_table, 8, "LQIMODE1", 1167 0x51, regvalue, cur_col, wrap)); 1168 } 1169 1170 static ahd_reg_parse_entry_t LQISTAT2_parse_table[] = { 1171 { "LQIGSAVAIL", 0x01, 0x01 }, 1172 { "LQISTOPCMD", 0x02, 0x02 }, 1173 { "LQISTOPLQ", 0x04, 0x04 }, 1174 { "LQISTOPPKT", 0x08, 0x08 }, 1175 { "LQIWAITFIFO", 0x10, 0x10 }, 1176 { "LQIWORKONLQ", 0x20, 0x20 }, 1177 { "LQIPHASE_OUTPKT", 0x40, 0x40 }, 1178 { "PACKETIZED", 0x80, 0x80 } 1179 }; 1180 1181 int 1182 ahd_lqistat2_print(u_int regvalue, u_int *cur_col, u_int wrap) 1183 { 1184 return (ahd_print_register(LQISTAT2_parse_table, 8, "LQISTAT2", 1185 0x52, regvalue, cur_col, wrap)); 1186 } 1187 1188 static ahd_reg_parse_entry_t SSTAT3_parse_table[] = { 1189 { "OSRAMPERR", 0x01, 0x01 }, 1190 { "NTRAMPERR", 0x02, 0x02 } 1191 }; 1192 1193 int 1194 ahd_sstat3_print(u_int regvalue, u_int *cur_col, u_int wrap) 1195 { 1196 return (ahd_print_register(SSTAT3_parse_table, 2, "SSTAT3", 1197 0x53, regvalue, cur_col, wrap)); 1198 } 1199 1200 static ahd_reg_parse_entry_t CLRSINT3_parse_table[] = { 1201 { "CLROSRAMPERR", 0x01, 0x01 }, 1202 { "CLRNTRAMPERR", 0x02, 0x02 } 1203 }; 1204 1205 int 1206 ahd_clrsint3_print(u_int regvalue, u_int *cur_col, u_int wrap) 1207 { 1208 return (ahd_print_register(CLRSINT3_parse_table, 2, "CLRSINT3", 1209 0x53, regvalue, cur_col, wrap)); 1210 } 1211 1212 static ahd_reg_parse_entry_t SIMODE3_parse_table[] = { 1213 { "ENOSRAMPERR", 0x01, 0x01 }, 1214 { "ENNTRAMPERR", 0x02, 0x02 } 1215 }; 1216 1217 int 1218 ahd_simode3_print(u_int regvalue, u_int *cur_col, u_int wrap) 1219 { 1220 return (ahd_print_register(SIMODE3_parse_table, 2, "SIMODE3", 1221 0x53, regvalue, cur_col, wrap)); 1222 } 1223 1224 static ahd_reg_parse_entry_t LQOMODE0_parse_table[] = { 1225 { "ENLQOTCRC", 0x01, 0x01 }, 1226 { "ENLQOATNPKT", 0x02, 0x02 }, 1227 { "ENLQOATNLQ", 0x04, 0x04 }, 1228 { "ENLQOSTOPT2", 0x08, 0x08 }, 1229 { "ENLQOTARGSCBPERR", 0x10, 0x10 } 1230 }; 1231 1232 int 1233 ahd_lqomode0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1234 { 1235 return (ahd_print_register(LQOMODE0_parse_table, 5, "LQOMODE0", 1236 0x54, regvalue, cur_col, wrap)); 1237 } 1238 1239 static ahd_reg_parse_entry_t LQOSTAT0_parse_table[] = { 1240 { "LQOTCRC", 0x01, 0x01 }, 1241 { "LQOATNPKT", 0x02, 0x02 }, 1242 { "LQOATNLQ", 0x04, 0x04 }, 1243 { "LQOSTOPT2", 0x08, 0x08 }, 1244 { "LQOTARGSCBPERR", 0x10, 0x10 } 1245 }; 1246 1247 int 1248 ahd_lqostat0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1249 { 1250 return (ahd_print_register(LQOSTAT0_parse_table, 5, "LQOSTAT0", 1251 0x54, regvalue, cur_col, wrap)); 1252 } 1253 1254 static ahd_reg_parse_entry_t CLRLQOINT0_parse_table[] = { 1255 { "CLRLQOTCRC", 0x01, 0x01 }, 1256 { "CLRLQOATNPKT", 0x02, 0x02 }, 1257 { "CLRLQOATNLQ", 0x04, 0x04 }, 1258 { "CLRLQOSTOPT2", 0x08, 0x08 }, 1259 { "CLRLQOTARGSCBPERR", 0x10, 0x10 } 1260 }; 1261 1262 int 1263 ahd_clrlqoint0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1264 { 1265 return (ahd_print_register(CLRLQOINT0_parse_table, 5, "CLRLQOINT0", 1266 0x54, regvalue, cur_col, wrap)); 1267 } 1268 1269 static ahd_reg_parse_entry_t LQOMODE1_parse_table[] = { 1270 { "ENLQOPHACHGINPKT", 0x01, 0x01 }, 1271 { "ENLQOBUSFREE", 0x02, 0x02 }, 1272 { "ENLQOBADQAS", 0x04, 0x04 }, 1273 { "ENLQOSTOPI2", 0x08, 0x08 }, 1274 { "ENLQOINITSCBPERR", 0x10, 0x10 } 1275 }; 1276 1277 int 1278 ahd_lqomode1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1279 { 1280 return (ahd_print_register(LQOMODE1_parse_table, 5, "LQOMODE1", 1281 0x55, regvalue, cur_col, wrap)); 1282 } 1283 1284 static ahd_reg_parse_entry_t LQOSTAT1_parse_table[] = { 1285 { "LQOPHACHGINPKT", 0x01, 0x01 }, 1286 { "LQOBUSFREE", 0x02, 0x02 }, 1287 { "LQOBADQAS", 0x04, 0x04 }, 1288 { "LQOSTOPI2", 0x08, 0x08 }, 1289 { "LQOINITSCBPERR", 0x10, 0x10 } 1290 }; 1291 1292 int 1293 ahd_lqostat1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1294 { 1295 return (ahd_print_register(LQOSTAT1_parse_table, 5, "LQOSTAT1", 1296 0x55, regvalue, cur_col, wrap)); 1297 } 1298 1299 static ahd_reg_parse_entry_t CLRLQOINT1_parse_table[] = { 1300 { "CLRLQOPHACHGINPKT", 0x01, 0x01 }, 1301 { "CLRLQOBUSFREE", 0x02, 0x02 }, 1302 { "CLRLQOBADQAS", 0x04, 0x04 }, 1303 { "CLRLQOSTOPI2", 0x08, 0x08 }, 1304 { "CLRLQOINITSCBPERR", 0x10, 0x10 } 1305 }; 1306 1307 int 1308 ahd_clrlqoint1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1309 { 1310 return (ahd_print_register(CLRLQOINT1_parse_table, 5, "CLRLQOINT1", 1311 0x55, regvalue, cur_col, wrap)); 1312 } 1313 1314 int 1315 ahd_os_space_cnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1316 { 1317 return (ahd_print_register(NULL, 0, "OS_SPACE_CNT", 1318 0x56, regvalue, cur_col, wrap)); 1319 } 1320 1321 static ahd_reg_parse_entry_t LQOSTAT2_parse_table[] = { 1322 { "LQOSTOP0", 0x01, 0x01 }, 1323 { "LQOPHACHGOUTPKT", 0x02, 0x02 }, 1324 { "LQOWAITFIFO", 0x10, 0x10 }, 1325 { "LQOPKT", 0xe0, 0xe0 } 1326 }; 1327 1328 int 1329 ahd_lqostat2_print(u_int regvalue, u_int *cur_col, u_int wrap) 1330 { 1331 return (ahd_print_register(LQOSTAT2_parse_table, 4, "LQOSTAT2", 1332 0x56, regvalue, cur_col, wrap)); 1333 } 1334 1335 static ahd_reg_parse_entry_t SIMODE1_parse_table[] = { 1336 { "ENREQINIT", 0x01, 0x01 }, 1337 { "ENSTRB2FAST", 0x02, 0x02 }, 1338 { "ENSCSIPERR", 0x04, 0x04 }, 1339 { "ENBUSFREE", 0x08, 0x08 }, 1340 { "ENPHASEMIS", 0x10, 0x10 }, 1341 { "ENSCSIRST", 0x20, 0x20 }, 1342 { "ENATNTARG", 0x40, 0x40 }, 1343 { "ENSELTIMO", 0x80, 0x80 } 1344 }; 1345 1346 int 1347 ahd_simode1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1348 { 1349 return (ahd_print_register(SIMODE1_parse_table, 8, "SIMODE1", 1350 0x57, regvalue, cur_col, wrap)); 1351 } 1352 1353 int 1354 ahd_gsfifo_print(u_int regvalue, u_int *cur_col, u_int wrap) 1355 { 1356 return (ahd_print_register(NULL, 0, "GSFIFO", 1357 0x58, regvalue, cur_col, wrap)); 1358 } 1359 1360 static ahd_reg_parse_entry_t DFFSXFRCTL_parse_table[] = { 1361 { "RSTCHN", 0x01, 0x01 }, 1362 { "CLRCHN", 0x02, 0x02 }, 1363 { "CLRSHCNT", 0x04, 0x04 }, 1364 { "DFFBITBUCKET", 0x08, 0x08 } 1365 }; 1366 1367 int 1368 ahd_dffsxfrctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 1369 { 1370 return (ahd_print_register(DFFSXFRCTL_parse_table, 4, "DFFSXFRCTL", 1371 0x5a, regvalue, cur_col, wrap)); 1372 } 1373 1374 int 1375 ahd_nextscb_print(u_int regvalue, u_int *cur_col, u_int wrap) 1376 { 1377 return (ahd_print_register(NULL, 0, "NEXTSCB", 1378 0x5a, regvalue, cur_col, wrap)); 1379 } 1380 1381 static ahd_reg_parse_entry_t LQOSCSCTL_parse_table[] = { 1382 { "LQONOCHKOVER", 0x01, 0x01 }, 1383 { "LQOH2A_VERSION", 0x80, 0x80 } 1384 }; 1385 1386 int 1387 ahd_lqoscsctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 1388 { 1389 return (ahd_print_register(LQOSCSCTL_parse_table, 2, "LQOSCSCTL", 1390 0x5a, regvalue, cur_col, wrap)); 1391 } 1392 1393 static ahd_reg_parse_entry_t SEQINTSRC_parse_table[] = { 1394 { "CFG4TCMD", 0x01, 0x01 }, 1395 { "CFG4ICMD", 0x02, 0x02 }, 1396 { "CFG4TSTAT", 0x04, 0x04 }, 1397 { "CFG4ISTAT", 0x08, 0x08 }, 1398 { "CFG4DATA", 0x10, 0x10 }, 1399 { "SAVEPTRS", 0x20, 0x20 }, 1400 { "CTXTDONE", 0x40, 0x40 } 1401 }; 1402 1403 int 1404 ahd_seqintsrc_print(u_int regvalue, u_int *cur_col, u_int wrap) 1405 { 1406 return (ahd_print_register(SEQINTSRC_parse_table, 7, "SEQINTSRC", 1407 0x5b, regvalue, cur_col, wrap)); 1408 } 1409 1410 static ahd_reg_parse_entry_t CLRSEQINTSRC_parse_table[] = { 1411 { "CLRCFG4TCMD", 0x01, 0x01 }, 1412 { "CLRCFG4ICMD", 0x02, 0x02 }, 1413 { "CLRCFG4TSTAT", 0x04, 0x04 }, 1414 { "CLRCFG4ISTAT", 0x08, 0x08 }, 1415 { "CLRCFG4DATA", 0x10, 0x10 }, 1416 { "CLRSAVEPTRS", 0x20, 0x20 }, 1417 { "CLRCTXTDONE", 0x40, 0x40 } 1418 }; 1419 1420 int 1421 ahd_clrseqintsrc_print(u_int regvalue, u_int *cur_col, u_int wrap) 1422 { 1423 return (ahd_print_register(CLRSEQINTSRC_parse_table, 7, "CLRSEQINTSRC", 1424 0x5b, regvalue, cur_col, wrap)); 1425 } 1426 1427 int 1428 ahd_currscb_print(u_int regvalue, u_int *cur_col, u_int wrap) 1429 { 1430 return (ahd_print_register(NULL, 0, "CURRSCB", 1431 0x5c, regvalue, cur_col, wrap)); 1432 } 1433 1434 static ahd_reg_parse_entry_t SEQIMODE_parse_table[] = { 1435 { "ENCFG4TCMD", 0x01, 0x01 }, 1436 { "ENCFG4ICMD", 0x02, 0x02 }, 1437 { "ENCFG4TSTAT", 0x04, 0x04 }, 1438 { "ENCFG4ISTAT", 0x08, 0x08 }, 1439 { "ENCFG4DATA", 0x10, 0x10 }, 1440 { "ENSAVEPTRS", 0x20, 0x20 }, 1441 { "ENCTXTDONE", 0x40, 0x40 } 1442 }; 1443 1444 int 1445 ahd_seqimode_print(u_int regvalue, u_int *cur_col, u_int wrap) 1446 { 1447 return (ahd_print_register(SEQIMODE_parse_table, 7, "SEQIMODE", 1448 0x5c, regvalue, cur_col, wrap)); 1449 } 1450 1451 static ahd_reg_parse_entry_t MDFFSTAT_parse_table[] = { 1452 { "FIFOFREE", 0x01, 0x01 }, 1453 { "DATAINFIFO", 0x02, 0x02 }, 1454 { "DLZERO", 0x04, 0x04 }, 1455 { "SHVALID", 0x08, 0x08 }, 1456 { "LASTSDONE", 0x10, 0x10 }, 1457 { "SHCNTMINUS1", 0x20, 0x20 }, 1458 { "SHCNTNEGATIVE", 0x40, 0x40 } 1459 }; 1460 1461 int 1462 ahd_mdffstat_print(u_int regvalue, u_int *cur_col, u_int wrap) 1463 { 1464 return (ahd_print_register(MDFFSTAT_parse_table, 7, "MDFFSTAT", 1465 0x5d, regvalue, cur_col, wrap)); 1466 } 1467 1468 static ahd_reg_parse_entry_t CRCCONTROL_parse_table[] = { 1469 { "CRCVALCHKEN", 0x40, 0x40 } 1470 }; 1471 1472 int 1473 ahd_crccontrol_print(u_int regvalue, u_int *cur_col, u_int wrap) 1474 { 1475 return (ahd_print_register(CRCCONTROL_parse_table, 1, "CRCCONTROL", 1476 0x5d, regvalue, cur_col, wrap)); 1477 } 1478 1479 static ahd_reg_parse_entry_t SCSITEST_parse_table[] = { 1480 { "SEL_TXPLL_DEBUG", 0x04, 0x04 }, 1481 { "CNTRTEST", 0x08, 0x08 } 1482 }; 1483 1484 int 1485 ahd_scsitest_print(u_int regvalue, u_int *cur_col, u_int wrap) 1486 { 1487 return (ahd_print_register(SCSITEST_parse_table, 2, "SCSITEST", 1488 0x5e, regvalue, cur_col, wrap)); 1489 } 1490 1491 int 1492 ahd_dfftag_print(u_int regvalue, u_int *cur_col, u_int wrap) 1493 { 1494 return (ahd_print_register(NULL, 0, "DFFTAG", 1495 0x5e, regvalue, cur_col, wrap)); 1496 } 1497 1498 int 1499 ahd_lastscb_print(u_int regvalue, u_int *cur_col, u_int wrap) 1500 { 1501 return (ahd_print_register(NULL, 0, "LASTSCB", 1502 0x5e, regvalue, cur_col, wrap)); 1503 } 1504 1505 static ahd_reg_parse_entry_t IOPDNCTL_parse_table[] = { 1506 { "PDN_DIFFSENSE", 0x01, 0x01 }, 1507 { "PDN_IDIST", 0x04, 0x04 }, 1508 { "DISABLE_OE", 0x80, 0x80 } 1509 }; 1510 1511 int 1512 ahd_iopdnctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 1513 { 1514 return (ahd_print_register(IOPDNCTL_parse_table, 3, "IOPDNCTL", 1515 0x5f, regvalue, cur_col, wrap)); 1516 } 1517 1518 int 1519 ahd_negoaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1520 { 1521 return (ahd_print_register(NULL, 0, "NEGOADDR", 1522 0x60, regvalue, cur_col, wrap)); 1523 } 1524 1525 int 1526 ahd_shaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1527 { 1528 return (ahd_print_register(NULL, 0, "SHADDR", 1529 0x60, regvalue, cur_col, wrap)); 1530 } 1531 1532 int 1533 ahd_dgrpcrci_print(u_int regvalue, u_int *cur_col, u_int wrap) 1534 { 1535 return (ahd_print_register(NULL, 0, "DGRPCRCI", 1536 0x60, regvalue, cur_col, wrap)); 1537 } 1538 1539 int 1540 ahd_negperiod_print(u_int regvalue, u_int *cur_col, u_int wrap) 1541 { 1542 return (ahd_print_register(NULL, 0, "NEGPERIOD", 1543 0x61, regvalue, cur_col, wrap)); 1544 } 1545 1546 int 1547 ahd_packcrci_print(u_int regvalue, u_int *cur_col, u_int wrap) 1548 { 1549 return (ahd_print_register(NULL, 0, "PACKCRCI", 1550 0x62, regvalue, cur_col, wrap)); 1551 } 1552 1553 int 1554 ahd_negoffset_print(u_int regvalue, u_int *cur_col, u_int wrap) 1555 { 1556 return (ahd_print_register(NULL, 0, "NEGOFFSET", 1557 0x62, regvalue, cur_col, wrap)); 1558 } 1559 1560 static ahd_reg_parse_entry_t NEGPPROPTS_parse_table[] = { 1561 { "PPROPT_IUT", 0x01, 0x01 }, 1562 { "PPROPT_DT", 0x02, 0x02 }, 1563 { "PPROPT_QAS", 0x04, 0x04 }, 1564 { "PPROPT_PACE", 0x08, 0x08 } 1565 }; 1566 1567 int 1568 ahd_negppropts_print(u_int regvalue, u_int *cur_col, u_int wrap) 1569 { 1570 return (ahd_print_register(NEGPPROPTS_parse_table, 4, "NEGPPROPTS", 1571 0x63, regvalue, cur_col, wrap)); 1572 } 1573 1574 static ahd_reg_parse_entry_t NEGCONOPTS_parse_table[] = { 1575 { "WIDEXFER", 0x01, 0x01 }, 1576 { "ENAUTOATNO", 0x02, 0x02 }, 1577 { "ENAUTOATNI", 0x04, 0x04 }, 1578 { "ENSLOWCRC", 0x08, 0x08 }, 1579 { "RTI_OVRDTRN", 0x10, 0x10 }, 1580 { "RTI_WRTDIS", 0x20, 0x20 }, 1581 { "ENSNAPSHOT", 0x40, 0x40 } 1582 }; 1583 1584 int 1585 ahd_negconopts_print(u_int regvalue, u_int *cur_col, u_int wrap) 1586 { 1587 return (ahd_print_register(NEGCONOPTS_parse_table, 7, "NEGCONOPTS", 1588 0x64, regvalue, cur_col, wrap)); 1589 } 1590 1591 int 1592 ahd_annexcol_print(u_int regvalue, u_int *cur_col, u_int wrap) 1593 { 1594 return (ahd_print_register(NULL, 0, "ANNEXCOL", 1595 0x65, regvalue, cur_col, wrap)); 1596 } 1597 1598 int 1599 ahd_annexdat_print(u_int regvalue, u_int *cur_col, u_int wrap) 1600 { 1601 return (ahd_print_register(NULL, 0, "ANNEXDAT", 1602 0x66, regvalue, cur_col, wrap)); 1603 } 1604 1605 static ahd_reg_parse_entry_t SCSCHKN_parse_table[] = { 1606 { "LSTSGCLRDIS", 0x01, 0x01 }, 1607 { "SHVALIDSTDIS", 0x02, 0x02 }, 1608 { "DFFACTCLR", 0x04, 0x04 }, 1609 { "SDONEMSKDIS", 0x08, 0x08 }, 1610 { "WIDERESEN", 0x10, 0x10 }, 1611 { "CURRFIFODEF", 0x20, 0x20 }, 1612 { "STSELSKIDDIS", 0x40, 0x40 } 1613 }; 1614 1615 int 1616 ahd_scschkn_print(u_int regvalue, u_int *cur_col, u_int wrap) 1617 { 1618 return (ahd_print_register(SCSCHKN_parse_table, 7, "SCSCHKN", 1619 0x66, regvalue, cur_col, wrap)); 1620 } 1621 1622 int 1623 ahd_iownid_print(u_int regvalue, u_int *cur_col, u_int wrap) 1624 { 1625 return (ahd_print_register(NULL, 0, "IOWNID", 1626 0x67, regvalue, cur_col, wrap)); 1627 } 1628 1629 int 1630 ahd_shcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1631 { 1632 return (ahd_print_register(NULL, 0, "SHCNT", 1633 0x68, regvalue, cur_col, wrap)); 1634 } 1635 1636 static ahd_reg_parse_entry_t PLL960CTL0_parse_table[] = { 1637 { "PLL_ENFBM", 0x01, 0x01 }, 1638 { "PLL_DLPF", 0x02, 0x02 }, 1639 { "PLL_ENLPF", 0x04, 0x04 }, 1640 { "PLL_ENLUD", 0x08, 0x08 }, 1641 { "PLL_NS", 0x30, 0x30 }, 1642 { "PLL_PWDN", 0x40, 0x40 }, 1643 { "PLL_VCOSEL", 0x80, 0x80 } 1644 }; 1645 1646 int 1647 ahd_pll960ctl0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1648 { 1649 return (ahd_print_register(PLL960CTL0_parse_table, 7, "PLL960CTL0", 1650 0x68, regvalue, cur_col, wrap)); 1651 } 1652 1653 static ahd_reg_parse_entry_t PLL960CTL1_parse_table[] = { 1654 { "PLL_RST", 0x01, 0x01 }, 1655 { "PLL_CNTCLR", 0x40, 0x40 }, 1656 { "PLL_CNTEN", 0x80, 0x80 } 1657 }; 1658 1659 int 1660 ahd_pll960ctl1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1661 { 1662 return (ahd_print_register(PLL960CTL1_parse_table, 3, "PLL960CTL1", 1663 0x69, regvalue, cur_col, wrap)); 1664 } 1665 1666 int 1667 ahd_townid_print(u_int regvalue, u_int *cur_col, u_int wrap) 1668 { 1669 return (ahd_print_register(NULL, 0, "TOWNID", 1670 0x69, regvalue, cur_col, wrap)); 1671 } 1672 1673 int 1674 ahd_xsig_print(u_int regvalue, u_int *cur_col, u_int wrap) 1675 { 1676 return (ahd_print_register(NULL, 0, "XSIG", 1677 0x6a, regvalue, cur_col, wrap)); 1678 } 1679 1680 int 1681 ahd_pll960cnt0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1682 { 1683 return (ahd_print_register(NULL, 0, "PLL960CNT0", 1684 0x6a, regvalue, cur_col, wrap)); 1685 } 1686 1687 int 1688 ahd_seloid_print(u_int regvalue, u_int *cur_col, u_int wrap) 1689 { 1690 return (ahd_print_register(NULL, 0, "SELOID", 1691 0x6b, regvalue, cur_col, wrap)); 1692 } 1693 1694 int 1695 ahd_fairness_print(u_int regvalue, u_int *cur_col, u_int wrap) 1696 { 1697 return (ahd_print_register(NULL, 0, "FAIRNESS", 1698 0x6c, regvalue, cur_col, wrap)); 1699 } 1700 1701 static ahd_reg_parse_entry_t PLL400CTL0_parse_table[] = { 1702 { "PLL_ENFBM", 0x01, 0x01 }, 1703 { "PLL_DLPF", 0x02, 0x02 }, 1704 { "PLL_ENLPF", 0x04, 0x04 }, 1705 { "PLL_ENLUD", 0x08, 0x08 }, 1706 { "PLL_NS", 0x30, 0x30 }, 1707 { "PLL_PWDN", 0x40, 0x40 }, 1708 { "PLL_VCOSEL", 0x80, 0x80 } 1709 }; 1710 1711 int 1712 ahd_pll400ctl0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1713 { 1714 return (ahd_print_register(PLL400CTL0_parse_table, 7, "PLL400CTL0", 1715 0x6c, regvalue, cur_col, wrap)); 1716 } 1717 1718 static ahd_reg_parse_entry_t PLL400CTL1_parse_table[] = { 1719 { "PLL_RST", 0x01, 0x01 }, 1720 { "PLL_CNTCLR", 0x40, 0x40 }, 1721 { "PLL_CNTEN", 0x80, 0x80 } 1722 }; 1723 1724 int 1725 ahd_pll400ctl1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1726 { 1727 return (ahd_print_register(PLL400CTL1_parse_table, 3, "PLL400CTL1", 1728 0x6d, regvalue, cur_col, wrap)); 1729 } 1730 1731 int 1732 ahd_pll400cnt0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1733 { 1734 return (ahd_print_register(NULL, 0, "PLL400CNT0", 1735 0x6e, regvalue, cur_col, wrap)); 1736 } 1737 1738 int 1739 ahd_unfairness_print(u_int regvalue, u_int *cur_col, u_int wrap) 1740 { 1741 return (ahd_print_register(NULL, 0, "UNFAIRNESS", 1742 0x6e, regvalue, cur_col, wrap)); 1743 } 1744 1745 int 1746 ahd_hodmaadr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1747 { 1748 return (ahd_print_register(NULL, 0, "HODMAADR", 1749 0x70, regvalue, cur_col, wrap)); 1750 } 1751 1752 int 1753 ahd_haddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1754 { 1755 return (ahd_print_register(NULL, 0, "HADDR", 1756 0x70, regvalue, cur_col, wrap)); 1757 } 1758 1759 static ahd_reg_parse_entry_t PLLDELAY_parse_table[] = { 1760 { "SPLIT_DROP_REQ", 0x80, 0x80 } 1761 }; 1762 1763 int 1764 ahd_plldelay_print(u_int regvalue, u_int *cur_col, u_int wrap) 1765 { 1766 return (ahd_print_register(PLLDELAY_parse_table, 1, "PLLDELAY", 1767 0x70, regvalue, cur_col, wrap)); 1768 } 1769 1770 int 1771 ahd_hcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1772 { 1773 return (ahd_print_register(NULL, 0, "HCNT", 1774 0x78, regvalue, cur_col, wrap)); 1775 } 1776 1777 int 1778 ahd_hodmacnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1779 { 1780 return (ahd_print_register(NULL, 0, "HODMACNT", 1781 0x78, regvalue, cur_col, wrap)); 1782 } 1783 1784 int 1785 ahd_hodmaen_print(u_int regvalue, u_int *cur_col, u_int wrap) 1786 { 1787 return (ahd_print_register(NULL, 0, "HODMAEN", 1788 0x7a, regvalue, cur_col, wrap)); 1789 } 1790 1791 int 1792 ahd_scbhaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1793 { 1794 return (ahd_print_register(NULL, 0, "SCBHADDR", 1795 0x7c, regvalue, cur_col, wrap)); 1796 } 1797 1798 int 1799 ahd_sghaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1800 { 1801 return (ahd_print_register(NULL, 0, "SGHADDR", 1802 0x7c, regvalue, cur_col, wrap)); 1803 } 1804 1805 int 1806 ahd_scbhcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1807 { 1808 return (ahd_print_register(NULL, 0, "SCBHCNT", 1809 0x84, regvalue, cur_col, wrap)); 1810 } 1811 1812 int 1813 ahd_sghcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 1814 { 1815 return (ahd_print_register(NULL, 0, "SGHCNT", 1816 0x84, regvalue, cur_col, wrap)); 1817 } 1818 1819 static ahd_reg_parse_entry_t DFF_THRSH_parse_table[] = { 1820 { "WR_DFTHRSH_MIN", 0x00, 0x70 }, 1821 { "RD_DFTHRSH_MIN", 0x00, 0x07 }, 1822 { "RD_DFTHRSH_25", 0x01, 0x07 }, 1823 { "RD_DFTHRSH_50", 0x02, 0x07 }, 1824 { "RD_DFTHRSH_63", 0x03, 0x07 }, 1825 { "RD_DFTHRSH_75", 0x04, 0x07 }, 1826 { "RD_DFTHRSH_85", 0x05, 0x07 }, 1827 { "RD_DFTHRSH_90", 0x06, 0x07 }, 1828 { "RD_DFTHRSH_MAX", 0x07, 0x07 }, 1829 { "WR_DFTHRSH_25", 0x10, 0x70 }, 1830 { "WR_DFTHRSH_50", 0x20, 0x70 }, 1831 { "WR_DFTHRSH_63", 0x30, 0x70 }, 1832 { "WR_DFTHRSH_75", 0x40, 0x70 }, 1833 { "WR_DFTHRSH_85", 0x50, 0x70 }, 1834 { "WR_DFTHRSH_90", 0x60, 0x70 }, 1835 { "WR_DFTHRSH_MAX", 0x70, 0x70 }, 1836 { "RD_DFTHRSH", 0x07, 0x07 }, 1837 { "WR_DFTHRSH", 0x70, 0x70 } 1838 }; 1839 1840 int 1841 ahd_dff_thrsh_print(u_int regvalue, u_int *cur_col, u_int wrap) 1842 { 1843 return (ahd_print_register(DFF_THRSH_parse_table, 18, "DFF_THRSH", 1844 0x88, regvalue, cur_col, wrap)); 1845 } 1846 1847 int 1848 ahd_romaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 1849 { 1850 return (ahd_print_register(NULL, 0, "ROMADDR", 1851 0x8a, regvalue, cur_col, wrap)); 1852 } 1853 1854 static ahd_reg_parse_entry_t ROMCNTRL_parse_table[] = { 1855 { "RDY", 0x01, 0x01 }, 1856 { "REPEAT", 0x02, 0x02 }, 1857 { "ROMSPD", 0x18, 0x18 }, 1858 { "ROMOP", 0xe0, 0xe0 } 1859 }; 1860 1861 int 1862 ahd_romcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap) 1863 { 1864 return (ahd_print_register(ROMCNTRL_parse_table, 4, "ROMCNTRL", 1865 0x8d, regvalue, cur_col, wrap)); 1866 } 1867 1868 int 1869 ahd_romdata_print(u_int regvalue, u_int *cur_col, u_int wrap) 1870 { 1871 return (ahd_print_register(NULL, 0, "ROMDATA", 1872 0x8e, regvalue, cur_col, wrap)); 1873 } 1874 1875 static ahd_reg_parse_entry_t DCHRXMSG0_parse_table[] = { 1876 { "CFNUM", 0x07, 0x07 }, 1877 { "CDNUM", 0xf8, 0xf8 } 1878 }; 1879 1880 int 1881 ahd_dchrxmsg0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1882 { 1883 return (ahd_print_register(DCHRXMSG0_parse_table, 2, "DCHRXMSG0", 1884 0x90, regvalue, cur_col, wrap)); 1885 } 1886 1887 static ahd_reg_parse_entry_t OVLYRXMSG0_parse_table[] = { 1888 { "CFNUM", 0x07, 0x07 }, 1889 { "CDNUM", 0xf8, 0xf8 } 1890 }; 1891 1892 int 1893 ahd_ovlyrxmsg0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1894 { 1895 return (ahd_print_register(OVLYRXMSG0_parse_table, 2, "OVLYRXMSG0", 1896 0x90, regvalue, cur_col, wrap)); 1897 } 1898 1899 static ahd_reg_parse_entry_t CMCRXMSG0_parse_table[] = { 1900 { "CFNUM", 0x07, 0x07 }, 1901 { "CDNUM", 0xf8, 0xf8 } 1902 }; 1903 1904 int 1905 ahd_cmcrxmsg0_print(u_int regvalue, u_int *cur_col, u_int wrap) 1906 { 1907 return (ahd_print_register(CMCRXMSG0_parse_table, 2, "CMCRXMSG0", 1908 0x90, regvalue, cur_col, wrap)); 1909 } 1910 1911 static ahd_reg_parse_entry_t ROENABLE_parse_table[] = { 1912 { "DCH0ROEN", 0x01, 0x01 }, 1913 { "DCH1ROEN", 0x02, 0x02 }, 1914 { "SGROEN", 0x04, 0x04 }, 1915 { "CMCROEN", 0x08, 0x08 }, 1916 { "OVLYROEN", 0x10, 0x10 }, 1917 { "MSIROEN", 0x20, 0x20 } 1918 }; 1919 1920 int 1921 ahd_roenable_print(u_int regvalue, u_int *cur_col, u_int wrap) 1922 { 1923 return (ahd_print_register(ROENABLE_parse_table, 6, "ROENABLE", 1924 0x90, regvalue, cur_col, wrap)); 1925 } 1926 1927 static ahd_reg_parse_entry_t DCHRXMSG1_parse_table[] = { 1928 { "CBNUM", 0xff, 0xff } 1929 }; 1930 1931 int 1932 ahd_dchrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1933 { 1934 return (ahd_print_register(DCHRXMSG1_parse_table, 1, "DCHRXMSG1", 1935 0x91, regvalue, cur_col, wrap)); 1936 } 1937 1938 static ahd_reg_parse_entry_t OVLYRXMSG1_parse_table[] = { 1939 { "CBNUM", 0xff, 0xff } 1940 }; 1941 1942 int 1943 ahd_ovlyrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1944 { 1945 return (ahd_print_register(OVLYRXMSG1_parse_table, 1, "OVLYRXMSG1", 1946 0x91, regvalue, cur_col, wrap)); 1947 } 1948 1949 static ahd_reg_parse_entry_t CMCRXMSG1_parse_table[] = { 1950 { "CBNUM", 0xff, 0xff } 1951 }; 1952 1953 int 1954 ahd_cmcrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap) 1955 { 1956 return (ahd_print_register(CMCRXMSG1_parse_table, 1, "CMCRXMSG1", 1957 0x91, regvalue, cur_col, wrap)); 1958 } 1959 1960 static ahd_reg_parse_entry_t NSENABLE_parse_table[] = { 1961 { "DCH0NSEN", 0x01, 0x01 }, 1962 { "DCH1NSEN", 0x02, 0x02 }, 1963 { "SGNSEN", 0x04, 0x04 }, 1964 { "CMCNSEN", 0x08, 0x08 }, 1965 { "OVLYNSEN", 0x10, 0x10 }, 1966 { "MSINSEN", 0x20, 0x20 } 1967 }; 1968 1969 int 1970 ahd_nsenable_print(u_int regvalue, u_int *cur_col, u_int wrap) 1971 { 1972 return (ahd_print_register(NSENABLE_parse_table, 6, "NSENABLE", 1973 0x91, regvalue, cur_col, wrap)); 1974 } 1975 1976 static ahd_reg_parse_entry_t DCHRXMSG2_parse_table[] = { 1977 { "MINDEX", 0xff, 0xff } 1978 }; 1979 1980 int 1981 ahd_dchrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap) 1982 { 1983 return (ahd_print_register(DCHRXMSG2_parse_table, 1, "DCHRXMSG2", 1984 0x92, regvalue, cur_col, wrap)); 1985 } 1986 1987 static ahd_reg_parse_entry_t OVLYRXMSG2_parse_table[] = { 1988 { "MINDEX", 0xff, 0xff } 1989 }; 1990 1991 int 1992 ahd_ovlyrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap) 1993 { 1994 return (ahd_print_register(OVLYRXMSG2_parse_table, 1, "OVLYRXMSG2", 1995 0x92, regvalue, cur_col, wrap)); 1996 } 1997 1998 static ahd_reg_parse_entry_t CMCRXMSG2_parse_table[] = { 1999 { "MINDEX", 0xff, 0xff } 2000 }; 2001 2002 int 2003 ahd_cmcrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap) 2004 { 2005 return (ahd_print_register(CMCRXMSG2_parse_table, 1, "CMCRXMSG2", 2006 0x92, regvalue, cur_col, wrap)); 2007 } 2008 2009 int 2010 ahd_ost_print(u_int regvalue, u_int *cur_col, u_int wrap) 2011 { 2012 return (ahd_print_register(NULL, 0, "OST", 2013 0x92, regvalue, cur_col, wrap)); 2014 } 2015 2016 static ahd_reg_parse_entry_t DCHRXMSG3_parse_table[] = { 2017 { "MCLASS", 0x0f, 0x0f } 2018 }; 2019 2020 int 2021 ahd_dchrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap) 2022 { 2023 return (ahd_print_register(DCHRXMSG3_parse_table, 1, "DCHRXMSG3", 2024 0x93, regvalue, cur_col, wrap)); 2025 } 2026 2027 static ahd_reg_parse_entry_t OVLYRXMSG3_parse_table[] = { 2028 { "MCLASS", 0x0f, 0x0f } 2029 }; 2030 2031 int 2032 ahd_ovlyrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap) 2033 { 2034 return (ahd_print_register(OVLYRXMSG3_parse_table, 1, "OVLYRXMSG3", 2035 0x93, regvalue, cur_col, wrap)); 2036 } 2037 2038 static ahd_reg_parse_entry_t CMCRXMSG3_parse_table[] = { 2039 { "MCLASS", 0x0f, 0x0f } 2040 }; 2041 2042 int 2043 ahd_cmcrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap) 2044 { 2045 return (ahd_print_register(CMCRXMSG3_parse_table, 1, "CMCRXMSG3", 2046 0x93, regvalue, cur_col, wrap)); 2047 } 2048 2049 static ahd_reg_parse_entry_t PCIXCTL_parse_table[] = { 2050 { "CMPABCDIS", 0x01, 0x01 }, 2051 { "TSCSERREN", 0x02, 0x02 }, 2052 { "SRSPDPEEN", 0x04, 0x04 }, 2053 { "SPLTSTADIS", 0x08, 0x08 }, 2054 { "SPLTSMADIS", 0x10, 0x10 }, 2055 { "UNEXPSCIEN", 0x20, 0x20 }, 2056 { "SERRPULSE", 0x80, 0x80 } 2057 }; 2058 2059 int 2060 ahd_pcixctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2061 { 2062 return (ahd_print_register(PCIXCTL_parse_table, 7, "PCIXCTL", 2063 0x93, regvalue, cur_col, wrap)); 2064 } 2065 2066 int 2067 ahd_cmcseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 2068 { 2069 return (ahd_print_register(NULL, 0, "CMCSEQBCNT", 2070 0x94, regvalue, cur_col, wrap)); 2071 } 2072 2073 int 2074 ahd_dchseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 2075 { 2076 return (ahd_print_register(NULL, 0, "DCHSEQBCNT", 2077 0x94, regvalue, cur_col, wrap)); 2078 } 2079 2080 int 2081 ahd_ovlyseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 2082 { 2083 return (ahd_print_register(NULL, 0, "OVLYSEQBCNT", 2084 0x94, regvalue, cur_col, wrap)); 2085 } 2086 2087 static ahd_reg_parse_entry_t CMCSPLTSTAT0_parse_table[] = { 2088 { "RXSPLTRSP", 0x01, 0x01 }, 2089 { "RXSCEMSG", 0x02, 0x02 }, 2090 { "RXOVRUN", 0x04, 0x04 }, 2091 { "CNTNOTCMPLT", 0x08, 0x08 }, 2092 { "SCDATBUCKET", 0x10, 0x10 }, 2093 { "SCADERR", 0x20, 0x20 }, 2094 { "SCBCERR", 0x40, 0x40 }, 2095 { "STAETERM", 0x80, 0x80 } 2096 }; 2097 2098 int 2099 ahd_cmcspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap) 2100 { 2101 return (ahd_print_register(CMCSPLTSTAT0_parse_table, 8, "CMCSPLTSTAT0", 2102 0x96, regvalue, cur_col, wrap)); 2103 } 2104 2105 static ahd_reg_parse_entry_t DCHSPLTSTAT0_parse_table[] = { 2106 { "RXSPLTRSP", 0x01, 0x01 }, 2107 { "RXSCEMSG", 0x02, 0x02 }, 2108 { "RXOVRUN", 0x04, 0x04 }, 2109 { "CNTNOTCMPLT", 0x08, 0x08 }, 2110 { "SCDATBUCKET", 0x10, 0x10 }, 2111 { "SCADERR", 0x20, 0x20 }, 2112 { "SCBCERR", 0x40, 0x40 }, 2113 { "STAETERM", 0x80, 0x80 } 2114 }; 2115 2116 int 2117 ahd_dchspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap) 2118 { 2119 return (ahd_print_register(DCHSPLTSTAT0_parse_table, 8, "DCHSPLTSTAT0", 2120 0x96, regvalue, cur_col, wrap)); 2121 } 2122 2123 static ahd_reg_parse_entry_t OVLYSPLTSTAT0_parse_table[] = { 2124 { "RXSPLTRSP", 0x01, 0x01 }, 2125 { "RXSCEMSG", 0x02, 0x02 }, 2126 { "RXOVRUN", 0x04, 0x04 }, 2127 { "CNTNOTCMPLT", 0x08, 0x08 }, 2128 { "SCDATBUCKET", 0x10, 0x10 }, 2129 { "SCADERR", 0x20, 0x20 }, 2130 { "SCBCERR", 0x40, 0x40 }, 2131 { "STAETERM", 0x80, 0x80 } 2132 }; 2133 2134 int 2135 ahd_ovlyspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap) 2136 { 2137 return (ahd_print_register(OVLYSPLTSTAT0_parse_table, 8, "OVLYSPLTSTAT0", 2138 0x96, regvalue, cur_col, wrap)); 2139 } 2140 2141 static ahd_reg_parse_entry_t CMCSPLTSTAT1_parse_table[] = { 2142 { "RXDATABUCKET", 0x01, 0x01 } 2143 }; 2144 2145 int 2146 ahd_cmcspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap) 2147 { 2148 return (ahd_print_register(CMCSPLTSTAT1_parse_table, 1, "CMCSPLTSTAT1", 2149 0x97, regvalue, cur_col, wrap)); 2150 } 2151 2152 static ahd_reg_parse_entry_t DCHSPLTSTAT1_parse_table[] = { 2153 { "RXDATABUCKET", 0x01, 0x01 } 2154 }; 2155 2156 int 2157 ahd_dchspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap) 2158 { 2159 return (ahd_print_register(DCHSPLTSTAT1_parse_table, 1, "DCHSPLTSTAT1", 2160 0x97, regvalue, cur_col, wrap)); 2161 } 2162 2163 static ahd_reg_parse_entry_t OVLYSPLTSTAT1_parse_table[] = { 2164 { "RXDATABUCKET", 0x01, 0x01 } 2165 }; 2166 2167 int 2168 ahd_ovlyspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap) 2169 { 2170 return (ahd_print_register(OVLYSPLTSTAT1_parse_table, 1, "OVLYSPLTSTAT1", 2171 0x97, regvalue, cur_col, wrap)); 2172 } 2173 2174 static ahd_reg_parse_entry_t SGRXMSG0_parse_table[] = { 2175 { "CFNUM", 0x07, 0x07 }, 2176 { "CDNUM", 0xf8, 0xf8 } 2177 }; 2178 2179 int 2180 ahd_sgrxmsg0_print(u_int regvalue, u_int *cur_col, u_int wrap) 2181 { 2182 return (ahd_print_register(SGRXMSG0_parse_table, 2, "SGRXMSG0", 2183 0x98, regvalue, cur_col, wrap)); 2184 } 2185 2186 static ahd_reg_parse_entry_t SLVSPLTOUTADR0_parse_table[] = { 2187 { "LOWER_ADDR", 0x7f, 0x7f } 2188 }; 2189 2190 int 2191 ahd_slvspltoutadr0_print(u_int regvalue, u_int *cur_col, u_int wrap) 2192 { 2193 return (ahd_print_register(SLVSPLTOUTADR0_parse_table, 1, "SLVSPLTOUTADR0", 2194 0x98, regvalue, cur_col, wrap)); 2195 } 2196 2197 static ahd_reg_parse_entry_t SGRXMSG1_parse_table[] = { 2198 { "CBNUM", 0xff, 0xff } 2199 }; 2200 2201 int 2202 ahd_sgrxmsg1_print(u_int regvalue, u_int *cur_col, u_int wrap) 2203 { 2204 return (ahd_print_register(SGRXMSG1_parse_table, 1, "SGRXMSG1", 2205 0x99, regvalue, cur_col, wrap)); 2206 } 2207 2208 static ahd_reg_parse_entry_t SLVSPLTOUTADR1_parse_table[] = { 2209 { "REQ_FNUM", 0x07, 0x07 }, 2210 { "REQ_DNUM", 0xf8, 0xf8 } 2211 }; 2212 2213 int 2214 ahd_slvspltoutadr1_print(u_int regvalue, u_int *cur_col, u_int wrap) 2215 { 2216 return (ahd_print_register(SLVSPLTOUTADR1_parse_table, 2, "SLVSPLTOUTADR1", 2217 0x99, regvalue, cur_col, wrap)); 2218 } 2219 2220 static ahd_reg_parse_entry_t SGRXMSG2_parse_table[] = { 2221 { "MINDEX", 0xff, 0xff } 2222 }; 2223 2224 int 2225 ahd_sgrxmsg2_print(u_int regvalue, u_int *cur_col, u_int wrap) 2226 { 2227 return (ahd_print_register(SGRXMSG2_parse_table, 1, "SGRXMSG2", 2228 0x9a, regvalue, cur_col, wrap)); 2229 } 2230 2231 static ahd_reg_parse_entry_t SLVSPLTOUTADR2_parse_table[] = { 2232 { "REQ_BNUM", 0xff, 0xff } 2233 }; 2234 2235 int 2236 ahd_slvspltoutadr2_print(u_int regvalue, u_int *cur_col, u_int wrap) 2237 { 2238 return (ahd_print_register(SLVSPLTOUTADR2_parse_table, 1, "SLVSPLTOUTADR2", 2239 0x9a, regvalue, cur_col, wrap)); 2240 } 2241 2242 static ahd_reg_parse_entry_t SGRXMSG3_parse_table[] = { 2243 { "MCLASS", 0x0f, 0x0f } 2244 }; 2245 2246 int 2247 ahd_sgrxmsg3_print(u_int regvalue, u_int *cur_col, u_int wrap) 2248 { 2249 return (ahd_print_register(SGRXMSG3_parse_table, 1, "SGRXMSG3", 2250 0x9b, regvalue, cur_col, wrap)); 2251 } 2252 2253 static ahd_reg_parse_entry_t SLVSPLTOUTADR3_parse_table[] = { 2254 { "RLXORD", 0x10, 0x10 }, 2255 { "TAG_NUM", 0x1f, 0x1f } 2256 }; 2257 2258 int 2259 ahd_slvspltoutadr3_print(u_int regvalue, u_int *cur_col, u_int wrap) 2260 { 2261 return (ahd_print_register(SLVSPLTOUTADR3_parse_table, 2, "SLVSPLTOUTADR3", 2262 0x9b, regvalue, cur_col, wrap)); 2263 } 2264 2265 static ahd_reg_parse_entry_t SLVSPLTOUTATTR0_parse_table[] = { 2266 { "LOWER_BCNT", 0xff, 0xff } 2267 }; 2268 2269 int 2270 ahd_slvspltoutattr0_print(u_int regvalue, u_int *cur_col, u_int wrap) 2271 { 2272 return (ahd_print_register(SLVSPLTOUTATTR0_parse_table, 1, "SLVSPLTOUTATTR0", 2273 0x9c, regvalue, cur_col, wrap)); 2274 } 2275 2276 int 2277 ahd_sgseqbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 2278 { 2279 return (ahd_print_register(NULL, 0, "SGSEQBCNT", 2280 0x9c, regvalue, cur_col, wrap)); 2281 } 2282 2283 static ahd_reg_parse_entry_t SLVSPLTOUTATTR1_parse_table[] = { 2284 { "CMPLT_FNUM", 0x07, 0x07 }, 2285 { "CMPLT_DNUM", 0xf8, 0xf8 } 2286 }; 2287 2288 int 2289 ahd_slvspltoutattr1_print(u_int regvalue, u_int *cur_col, u_int wrap) 2290 { 2291 return (ahd_print_register(SLVSPLTOUTATTR1_parse_table, 2, "SLVSPLTOUTATTR1", 2292 0x9d, regvalue, cur_col, wrap)); 2293 } 2294 2295 static ahd_reg_parse_entry_t SLVSPLTOUTATTR2_parse_table[] = { 2296 { "CMPLT_BNUM", 0xff, 0xff } 2297 }; 2298 2299 int 2300 ahd_slvspltoutattr2_print(u_int regvalue, u_int *cur_col, u_int wrap) 2301 { 2302 return (ahd_print_register(SLVSPLTOUTATTR2_parse_table, 1, "SLVSPLTOUTATTR2", 2303 0x9e, regvalue, cur_col, wrap)); 2304 } 2305 2306 static ahd_reg_parse_entry_t SGSPLTSTAT0_parse_table[] = { 2307 { "RXSPLTRSP", 0x01, 0x01 }, 2308 { "RXSCEMSG", 0x02, 0x02 }, 2309 { "RXOVRUN", 0x04, 0x04 }, 2310 { "CNTNOTCMPLT", 0x08, 0x08 }, 2311 { "SCDATBUCKET", 0x10, 0x10 }, 2312 { "SCADERR", 0x20, 0x20 }, 2313 { "SCBCERR", 0x40, 0x40 }, 2314 { "STAETERM", 0x80, 0x80 } 2315 }; 2316 2317 int 2318 ahd_sgspltstat0_print(u_int regvalue, u_int *cur_col, u_int wrap) 2319 { 2320 return (ahd_print_register(SGSPLTSTAT0_parse_table, 8, "SGSPLTSTAT0", 2321 0x9e, regvalue, cur_col, wrap)); 2322 } 2323 2324 static ahd_reg_parse_entry_t SFUNCT_parse_table[] = { 2325 { "TEST_NUM", 0x0f, 0x0f }, 2326 { "TEST_GROUP", 0xf0, 0xf0 } 2327 }; 2328 2329 int 2330 ahd_sfunct_print(u_int regvalue, u_int *cur_col, u_int wrap) 2331 { 2332 return (ahd_print_register(SFUNCT_parse_table, 2, "SFUNCT", 2333 0x9f, regvalue, cur_col, wrap)); 2334 } 2335 2336 static ahd_reg_parse_entry_t SGSPLTSTAT1_parse_table[] = { 2337 { "RXDATABUCKET", 0x01, 0x01 } 2338 }; 2339 2340 int 2341 ahd_sgspltstat1_print(u_int regvalue, u_int *cur_col, u_int wrap) 2342 { 2343 return (ahd_print_register(SGSPLTSTAT1_parse_table, 1, "SGSPLTSTAT1", 2344 0x9f, regvalue, cur_col, wrap)); 2345 } 2346 2347 static ahd_reg_parse_entry_t DF0PCISTAT_parse_table[] = { 2348 { "DPR", 0x01, 0x01 }, 2349 { "TWATERR", 0x02, 0x02 }, 2350 { "RDPERR", 0x04, 0x04 }, 2351 { "SCAAPERR", 0x08, 0x08 }, 2352 { "RTA", 0x10, 0x10 }, 2353 { "RMA", 0x20, 0x20 }, 2354 { "SSE", 0x40, 0x40 }, 2355 { "DPE", 0x80, 0x80 } 2356 }; 2357 2358 int 2359 ahd_df0pcistat_print(u_int regvalue, u_int *cur_col, u_int wrap) 2360 { 2361 return (ahd_print_register(DF0PCISTAT_parse_table, 8, "DF0PCISTAT", 2362 0xa0, regvalue, cur_col, wrap)); 2363 } 2364 2365 int 2366 ahd_reg0_print(u_int regvalue, u_int *cur_col, u_int wrap) 2367 { 2368 return (ahd_print_register(NULL, 0, "REG0", 2369 0xa0, regvalue, cur_col, wrap)); 2370 } 2371 2372 static ahd_reg_parse_entry_t DF1PCISTAT_parse_table[] = { 2373 { "DPR", 0x01, 0x01 }, 2374 { "TWATERR", 0x02, 0x02 }, 2375 { "RDPERR", 0x04, 0x04 }, 2376 { "SCAAPERR", 0x08, 0x08 }, 2377 { "RTA", 0x10, 0x10 }, 2378 { "RMA", 0x20, 0x20 }, 2379 { "SSE", 0x40, 0x40 }, 2380 { "DPE", 0x80, 0x80 } 2381 }; 2382 2383 int 2384 ahd_df1pcistat_print(u_int regvalue, u_int *cur_col, u_int wrap) 2385 { 2386 return (ahd_print_register(DF1PCISTAT_parse_table, 8, "DF1PCISTAT", 2387 0xa1, regvalue, cur_col, wrap)); 2388 } 2389 2390 static ahd_reg_parse_entry_t SGPCISTAT_parse_table[] = { 2391 { "DPR", 0x01, 0x01 }, 2392 { "RDPERR", 0x04, 0x04 }, 2393 { "SCAAPERR", 0x08, 0x08 }, 2394 { "RTA", 0x10, 0x10 }, 2395 { "RMA", 0x20, 0x20 }, 2396 { "SSE", 0x40, 0x40 }, 2397 { "DPE", 0x80, 0x80 } 2398 }; 2399 2400 int 2401 ahd_sgpcistat_print(u_int regvalue, u_int *cur_col, u_int wrap) 2402 { 2403 return (ahd_print_register(SGPCISTAT_parse_table, 7, "SGPCISTAT", 2404 0xa2, regvalue, cur_col, wrap)); 2405 } 2406 2407 int 2408 ahd_reg1_print(u_int regvalue, u_int *cur_col, u_int wrap) 2409 { 2410 return (ahd_print_register(NULL, 0, "REG1", 2411 0xa2, regvalue, cur_col, wrap)); 2412 } 2413 2414 static ahd_reg_parse_entry_t CMCPCISTAT_parse_table[] = { 2415 { "DPR", 0x01, 0x01 }, 2416 { "TWATERR", 0x02, 0x02 }, 2417 { "RDPERR", 0x04, 0x04 }, 2418 { "SCAAPERR", 0x08, 0x08 }, 2419 { "RTA", 0x10, 0x10 }, 2420 { "RMA", 0x20, 0x20 }, 2421 { "SSE", 0x40, 0x40 }, 2422 { "DPE", 0x80, 0x80 } 2423 }; 2424 2425 int 2426 ahd_cmcpcistat_print(u_int regvalue, u_int *cur_col, u_int wrap) 2427 { 2428 return (ahd_print_register(CMCPCISTAT_parse_table, 8, "CMCPCISTAT", 2429 0xa3, regvalue, cur_col, wrap)); 2430 } 2431 2432 static ahd_reg_parse_entry_t OVLYPCISTAT_parse_table[] = { 2433 { "DPR", 0x01, 0x01 }, 2434 { "RDPERR", 0x04, 0x04 }, 2435 { "SCAAPERR", 0x08, 0x08 }, 2436 { "RTA", 0x10, 0x10 }, 2437 { "RMA", 0x20, 0x20 }, 2438 { "SSE", 0x40, 0x40 }, 2439 { "DPE", 0x80, 0x80 } 2440 }; 2441 2442 int 2443 ahd_ovlypcistat_print(u_int regvalue, u_int *cur_col, u_int wrap) 2444 { 2445 return (ahd_print_register(OVLYPCISTAT_parse_table, 7, "OVLYPCISTAT", 2446 0xa4, regvalue, cur_col, wrap)); 2447 } 2448 2449 int 2450 ahd_reg_isr_print(u_int regvalue, u_int *cur_col, u_int wrap) 2451 { 2452 return (ahd_print_register(NULL, 0, "REG_ISR", 2453 0xa4, regvalue, cur_col, wrap)); 2454 } 2455 2456 static ahd_reg_parse_entry_t MSIPCISTAT_parse_table[] = { 2457 { "DPR", 0x01, 0x01 }, 2458 { "TWATERR", 0x02, 0x02 }, 2459 { "CLRPENDMSI", 0x08, 0x08 }, 2460 { "RTA", 0x10, 0x10 }, 2461 { "RMA", 0x20, 0x20 }, 2462 { "SSE", 0x40, 0x40 } 2463 }; 2464 2465 int 2466 ahd_msipcistat_print(u_int regvalue, u_int *cur_col, u_int wrap) 2467 { 2468 return (ahd_print_register(MSIPCISTAT_parse_table, 6, "MSIPCISTAT", 2469 0xa6, regvalue, cur_col, wrap)); 2470 } 2471 2472 static ahd_reg_parse_entry_t SG_STATE_parse_table[] = { 2473 { "SEGS_AVAIL", 0x01, 0x01 }, 2474 { "LOADING_NEEDED", 0x02, 0x02 }, 2475 { "FETCH_INPROG", 0x04, 0x04 } 2476 }; 2477 2478 int 2479 ahd_sg_state_print(u_int regvalue, u_int *cur_col, u_int wrap) 2480 { 2481 return (ahd_print_register(SG_STATE_parse_table, 3, "SG_STATE", 2482 0xa6, regvalue, cur_col, wrap)); 2483 } 2484 2485 static ahd_reg_parse_entry_t TARGPCISTAT_parse_table[] = { 2486 { "TWATERR", 0x02, 0x02 }, 2487 { "STA", 0x08, 0x08 }, 2488 { "SSE", 0x40, 0x40 }, 2489 { "DPE", 0x80, 0x80 } 2490 }; 2491 2492 int 2493 ahd_targpcistat_print(u_int regvalue, u_int *cur_col, u_int wrap) 2494 { 2495 return (ahd_print_register(TARGPCISTAT_parse_table, 4, "TARGPCISTAT", 2496 0xa7, regvalue, cur_col, wrap)); 2497 } 2498 2499 int 2500 ahd_data_count_odd_print(u_int regvalue, u_int *cur_col, u_int wrap) 2501 { 2502 return (ahd_print_register(NULL, 0, "DATA_COUNT_ODD", 2503 0xa7, regvalue, cur_col, wrap)); 2504 } 2505 2506 int 2507 ahd_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 2508 { 2509 return (ahd_print_register(NULL, 0, "SCBPTR", 2510 0xa8, regvalue, cur_col, wrap)); 2511 } 2512 2513 int 2514 ahd_ccscbacnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 2515 { 2516 return (ahd_print_register(NULL, 0, "CCSCBACNT", 2517 0xab, regvalue, cur_col, wrap)); 2518 } 2519 2520 static ahd_reg_parse_entry_t SCBAUTOPTR_parse_table[] = { 2521 { "SCBPTR_OFF", 0x07, 0x07 }, 2522 { "SCBPTR_ADDR", 0x38, 0x38 }, 2523 { "AUSCBPTR_EN", 0x80, 0x80 } 2524 }; 2525 2526 int 2527 ahd_scbautoptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 2528 { 2529 return (ahd_print_register(SCBAUTOPTR_parse_table, 3, "SCBAUTOPTR", 2530 0xab, regvalue, cur_col, wrap)); 2531 } 2532 2533 int 2534 ahd_ccscbadr_bk_print(u_int regvalue, u_int *cur_col, u_int wrap) 2535 { 2536 return (ahd_print_register(NULL, 0, "CCSCBADR_BK", 2537 0xac, regvalue, cur_col, wrap)); 2538 } 2539 2540 int 2541 ahd_ccsgaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 2542 { 2543 return (ahd_print_register(NULL, 0, "CCSGADDR", 2544 0xac, regvalue, cur_col, wrap)); 2545 } 2546 2547 int 2548 ahd_ccscbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 2549 { 2550 return (ahd_print_register(NULL, 0, "CCSCBADDR", 2551 0xac, regvalue, cur_col, wrap)); 2552 } 2553 2554 static ahd_reg_parse_entry_t CCSCBCTL_parse_table[] = { 2555 { "CCSCBRESET", 0x01, 0x01 }, 2556 { "CCSCBDIR", 0x04, 0x04 }, 2557 { "CCSCBEN", 0x08, 0x08 }, 2558 { "CCARREN", 0x10, 0x10 }, 2559 { "ARRDONE", 0x40, 0x40 }, 2560 { "CCSCBDONE", 0x80, 0x80 } 2561 }; 2562 2563 int 2564 ahd_ccscbctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2565 { 2566 return (ahd_print_register(CCSCBCTL_parse_table, 6, "CCSCBCTL", 2567 0xad, regvalue, cur_col, wrap)); 2568 } 2569 2570 static ahd_reg_parse_entry_t CCSGCTL_parse_table[] = { 2571 { "CCSGRESET", 0x01, 0x01 }, 2572 { "SG_FETCH_REQ", 0x02, 0x02 }, 2573 { "CCSGENACK", 0x08, 0x08 }, 2574 { "SG_CACHE_AVAIL", 0x10, 0x10 }, 2575 { "CCSGDONE", 0x80, 0x80 }, 2576 { "CCSGEN", 0x0c, 0x0c } 2577 }; 2578 2579 int 2580 ahd_ccsgctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2581 { 2582 return (ahd_print_register(CCSGCTL_parse_table, 6, "CCSGCTL", 2583 0xad, regvalue, cur_col, wrap)); 2584 } 2585 2586 static ahd_reg_parse_entry_t CMC_RAMBIST_parse_table[] = { 2587 { "CMC_BUFFER_BIST_EN", 0x01, 0x01 }, 2588 { "CMC_BUFFER_BIST_FAIL",0x02, 0x02 }, 2589 { "SG_BIST_EN", 0x10, 0x10 }, 2590 { "SG_BIST_FAIL", 0x20, 0x20 }, 2591 { "SCBRAMBIST_FAIL", 0x40, 0x40 }, 2592 { "SG_ELEMENT_SIZE", 0x80, 0x80 } 2593 }; 2594 2595 int 2596 ahd_cmc_rambist_print(u_int regvalue, u_int *cur_col, u_int wrap) 2597 { 2598 return (ahd_print_register(CMC_RAMBIST_parse_table, 6, "CMC_RAMBIST", 2599 0xad, regvalue, cur_col, wrap)); 2600 } 2601 2602 int 2603 ahd_ccsgram_print(u_int regvalue, u_int *cur_col, u_int wrap) 2604 { 2605 return (ahd_print_register(NULL, 0, "CCSGRAM", 2606 0xb0, regvalue, cur_col, wrap)); 2607 } 2608 2609 int 2610 ahd_ccscbram_print(u_int regvalue, u_int *cur_col, u_int wrap) 2611 { 2612 return (ahd_print_register(NULL, 0, "CCSCBRAM", 2613 0xb0, regvalue, cur_col, wrap)); 2614 } 2615 2616 int 2617 ahd_flexadr_print(u_int regvalue, u_int *cur_col, u_int wrap) 2618 { 2619 return (ahd_print_register(NULL, 0, "FLEXADR", 2620 0xb0, regvalue, cur_col, wrap)); 2621 } 2622 2623 int 2624 ahd_flexcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 2625 { 2626 return (ahd_print_register(NULL, 0, "FLEXCNT", 2627 0xb3, regvalue, cur_col, wrap)); 2628 } 2629 2630 static ahd_reg_parse_entry_t FLEXDMASTAT_parse_table[] = { 2631 { "FLEXDMADONE", 0x01, 0x01 }, 2632 { "FLEXDMAERR", 0x02, 0x02 } 2633 }; 2634 2635 int 2636 ahd_flexdmastat_print(u_int regvalue, u_int *cur_col, u_int wrap) 2637 { 2638 return (ahd_print_register(FLEXDMASTAT_parse_table, 2, "FLEXDMASTAT", 2639 0xb5, regvalue, cur_col, wrap)); 2640 } 2641 2642 int 2643 ahd_flexdata_print(u_int regvalue, u_int *cur_col, u_int wrap) 2644 { 2645 return (ahd_print_register(NULL, 0, "FLEXDATA", 2646 0xb6, regvalue, cur_col, wrap)); 2647 } 2648 2649 int 2650 ahd_brddat_print(u_int regvalue, u_int *cur_col, u_int wrap) 2651 { 2652 return (ahd_print_register(NULL, 0, "BRDDAT", 2653 0xb8, regvalue, cur_col, wrap)); 2654 } 2655 2656 static ahd_reg_parse_entry_t BRDCTL_parse_table[] = { 2657 { "BRDSTB", 0x01, 0x01 }, 2658 { "BRDRW", 0x02, 0x02 }, 2659 { "BRDEN", 0x04, 0x04 }, 2660 { "BRDADDR", 0x38, 0x38 }, 2661 { "FLXARBREQ", 0x40, 0x40 }, 2662 { "FLXARBACK", 0x80, 0x80 } 2663 }; 2664 2665 int 2666 ahd_brdctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2667 { 2668 return (ahd_print_register(BRDCTL_parse_table, 6, "BRDCTL", 2669 0xb9, regvalue, cur_col, wrap)); 2670 } 2671 2672 int 2673 ahd_seeadr_print(u_int regvalue, u_int *cur_col, u_int wrap) 2674 { 2675 return (ahd_print_register(NULL, 0, "SEEADR", 2676 0xba, regvalue, cur_col, wrap)); 2677 } 2678 2679 int 2680 ahd_seedat_print(u_int regvalue, u_int *cur_col, u_int wrap) 2681 { 2682 return (ahd_print_register(NULL, 0, "SEEDAT", 2683 0xbc, regvalue, cur_col, wrap)); 2684 } 2685 2686 static ahd_reg_parse_entry_t SEECTL_parse_table[] = { 2687 { "SEEOP_ERAL", 0x40, 0x70 }, 2688 { "SEEOP_WRITE", 0x50, 0x70 }, 2689 { "SEEOP_READ", 0x60, 0x70 }, 2690 { "SEEOP_ERASE", 0x70, 0x70 }, 2691 { "SEESTART", 0x01, 0x01 }, 2692 { "SEERST", 0x02, 0x02 }, 2693 { "SEEOPCODE", 0x70, 0x70 }, 2694 { "SEEOP_EWEN", 0x40, 0x40 }, 2695 { "SEEOP_WALL", 0x40, 0x40 }, 2696 { "SEEOP_EWDS", 0x40, 0x40 } 2697 }; 2698 2699 int 2700 ahd_seectl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2701 { 2702 return (ahd_print_register(SEECTL_parse_table, 10, "SEECTL", 2703 0xbe, regvalue, cur_col, wrap)); 2704 } 2705 2706 static ahd_reg_parse_entry_t SEESTAT_parse_table[] = { 2707 { "SEESTART", 0x01, 0x01 }, 2708 { "SEEBUSY", 0x02, 0x02 }, 2709 { "SEEARBACK", 0x04, 0x04 }, 2710 { "LDALTID_L", 0x08, 0x08 }, 2711 { "SEEOPCODE", 0x70, 0x70 }, 2712 { "INIT_DONE", 0x80, 0x80 } 2713 }; 2714 2715 int 2716 ahd_seestat_print(u_int regvalue, u_int *cur_col, u_int wrap) 2717 { 2718 return (ahd_print_register(SEESTAT_parse_table, 6, "SEESTAT", 2719 0xbe, regvalue, cur_col, wrap)); 2720 } 2721 2722 int 2723 ahd_scbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 2724 { 2725 return (ahd_print_register(NULL, 0, "SCBCNT", 2726 0xbf, regvalue, cur_col, wrap)); 2727 } 2728 2729 static ahd_reg_parse_entry_t DSPFLTRCTL_parse_table[] = { 2730 { "DSPFCNTSEL", 0x0f, 0x0f }, 2731 { "EDGESENSE", 0x10, 0x10 }, 2732 { "FLTRDISABLE", 0x20, 0x20 } 2733 }; 2734 2735 int 2736 ahd_dspfltrctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2737 { 2738 return (ahd_print_register(DSPFLTRCTL_parse_table, 3, "DSPFLTRCTL", 2739 0xc0, regvalue, cur_col, wrap)); 2740 } 2741 2742 int 2743 ahd_dfwaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 2744 { 2745 return (ahd_print_register(NULL, 0, "DFWADDR", 2746 0xc0, regvalue, cur_col, wrap)); 2747 } 2748 2749 static ahd_reg_parse_entry_t DSPDATACTL_parse_table[] = { 2750 { "XMITOFFSTDIS", 0x02, 0x02 }, 2751 { "RCVROFFSTDIS", 0x04, 0x04 }, 2752 { "DESQDIS", 0x10, 0x10 }, 2753 { "BYPASSENAB", 0x80, 0x80 } 2754 }; 2755 2756 int 2757 ahd_dspdatactl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2758 { 2759 return (ahd_print_register(DSPDATACTL_parse_table, 4, "DSPDATACTL", 2760 0xc1, regvalue, cur_col, wrap)); 2761 } 2762 2763 static ahd_reg_parse_entry_t DSPREQCTL_parse_table[] = { 2764 { "MANREQDLY", 0x3f, 0x3f }, 2765 { "MANREQCTL", 0xc0, 0xc0 } 2766 }; 2767 2768 int 2769 ahd_dspreqctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2770 { 2771 return (ahd_print_register(DSPREQCTL_parse_table, 2, "DSPREQCTL", 2772 0xc2, regvalue, cur_col, wrap)); 2773 } 2774 2775 int 2776 ahd_dfraddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 2777 { 2778 return (ahd_print_register(NULL, 0, "DFRADDR", 2779 0xc2, regvalue, cur_col, wrap)); 2780 } 2781 2782 static ahd_reg_parse_entry_t DSPACKCTL_parse_table[] = { 2783 { "MANACKDLY", 0x3f, 0x3f }, 2784 { "MANACKCTL", 0xc0, 0xc0 } 2785 }; 2786 2787 int 2788 ahd_dspackctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2789 { 2790 return (ahd_print_register(DSPACKCTL_parse_table, 2, "DSPACKCTL", 2791 0xc3, regvalue, cur_col, wrap)); 2792 } 2793 2794 int 2795 ahd_dfdat_print(u_int regvalue, u_int *cur_col, u_int wrap) 2796 { 2797 return (ahd_print_register(NULL, 0, "DFDAT", 2798 0xc4, regvalue, cur_col, wrap)); 2799 } 2800 2801 static ahd_reg_parse_entry_t DSPSELECT_parse_table[] = { 2802 { "DSPSEL", 0x1f, 0x1f }, 2803 { "AUTOINCEN", 0x80, 0x80 } 2804 }; 2805 2806 int 2807 ahd_dspselect_print(u_int regvalue, u_int *cur_col, u_int wrap) 2808 { 2809 return (ahd_print_register(DSPSELECT_parse_table, 2, "DSPSELECT", 2810 0xc4, regvalue, cur_col, wrap)); 2811 } 2812 2813 static ahd_reg_parse_entry_t WRTBIASCTL_parse_table[] = { 2814 { "XMITMANVAL", 0x3f, 0x3f }, 2815 { "AUTOXBCDIS", 0x80, 0x80 } 2816 }; 2817 2818 int 2819 ahd_wrtbiasctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2820 { 2821 return (ahd_print_register(WRTBIASCTL_parse_table, 2, "WRTBIASCTL", 2822 0xc5, regvalue, cur_col, wrap)); 2823 } 2824 2825 static ahd_reg_parse_entry_t RCVRBIOSCTL_parse_table[] = { 2826 { "RCVRMANVAL", 0x3f, 0x3f }, 2827 { "AUTORBCDIS", 0x80, 0x80 } 2828 }; 2829 2830 int 2831 ahd_rcvrbiosctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2832 { 2833 return (ahd_print_register(RCVRBIOSCTL_parse_table, 2, "RCVRBIOSCTL", 2834 0xc6, regvalue, cur_col, wrap)); 2835 } 2836 2837 int 2838 ahd_wrtbiascalc_print(u_int regvalue, u_int *cur_col, u_int wrap) 2839 { 2840 return (ahd_print_register(NULL, 0, "WRTBIASCALC", 2841 0xc7, regvalue, cur_col, wrap)); 2842 } 2843 2844 int 2845 ahd_dfptrs_print(u_int regvalue, u_int *cur_col, u_int wrap) 2846 { 2847 return (ahd_print_register(NULL, 0, "DFPTRS", 2848 0xc8, regvalue, cur_col, wrap)); 2849 } 2850 2851 int 2852 ahd_rcvrbiascalc_print(u_int regvalue, u_int *cur_col, u_int wrap) 2853 { 2854 return (ahd_print_register(NULL, 0, "RCVRBIASCALC", 2855 0xc8, regvalue, cur_col, wrap)); 2856 } 2857 2858 int 2859 ahd_dfbkptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 2860 { 2861 return (ahd_print_register(NULL, 0, "DFBKPTR", 2862 0xc9, regvalue, cur_col, wrap)); 2863 } 2864 2865 int 2866 ahd_skewcalc_print(u_int regvalue, u_int *cur_col, u_int wrap) 2867 { 2868 return (ahd_print_register(NULL, 0, "SKEWCALC", 2869 0xc9, regvalue, cur_col, wrap)); 2870 } 2871 2872 static ahd_reg_parse_entry_t DFDBCTL_parse_table[] = { 2873 { "DFF_RAMBIST_EN", 0x01, 0x01 }, 2874 { "DFF_RAMBIST_DONE", 0x02, 0x02 }, 2875 { "DFF_RAMBIST_FAIL", 0x04, 0x04 }, 2876 { "DFF_DIR_ERR", 0x08, 0x08 }, 2877 { "DFF_CIO_RD_RDY", 0x10, 0x10 }, 2878 { "DFF_CIO_WR_RDY", 0x20, 0x20 } 2879 }; 2880 2881 int 2882 ahd_dfdbctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2883 { 2884 return (ahd_print_register(DFDBCTL_parse_table, 6, "DFDBCTL", 2885 0xcb, regvalue, cur_col, wrap)); 2886 } 2887 2888 int 2889 ahd_dfscnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 2890 { 2891 return (ahd_print_register(NULL, 0, "DFSCNT", 2892 0xcc, regvalue, cur_col, wrap)); 2893 } 2894 2895 int 2896 ahd_dfbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 2897 { 2898 return (ahd_print_register(NULL, 0, "DFBCNT", 2899 0xce, regvalue, cur_col, wrap)); 2900 } 2901 2902 int 2903 ahd_ovlyaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 2904 { 2905 return (ahd_print_register(NULL, 0, "OVLYADDR", 2906 0xd4, regvalue, cur_col, wrap)); 2907 } 2908 2909 static ahd_reg_parse_entry_t SEQCTL0_parse_table[] = { 2910 { "LOADRAM", 0x01, 0x01 }, 2911 { "SEQRESET", 0x02, 0x02 }, 2912 { "STEP", 0x04, 0x04 }, 2913 { "BRKADRINTEN", 0x08, 0x08 }, 2914 { "FASTMODE", 0x10, 0x10 }, 2915 { "FAILDIS", 0x20, 0x20 }, 2916 { "PAUSEDIS", 0x40, 0x40 }, 2917 { "PERRORDIS", 0x80, 0x80 } 2918 }; 2919 2920 int 2921 ahd_seqctl0_print(u_int regvalue, u_int *cur_col, u_int wrap) 2922 { 2923 return (ahd_print_register(SEQCTL0_parse_table, 8, "SEQCTL0", 2924 0xd6, regvalue, cur_col, wrap)); 2925 } 2926 2927 static ahd_reg_parse_entry_t SEQCTL1_parse_table[] = { 2928 { "RAMBIST_EN", 0x01, 0x01 }, 2929 { "RAMBIST_FAIL", 0x02, 0x02 }, 2930 { "RAMBIST_DONE", 0x04, 0x04 }, 2931 { "OVRLAY_DATA_CHK", 0x08, 0x08 } 2932 }; 2933 2934 int 2935 ahd_seqctl1_print(u_int regvalue, u_int *cur_col, u_int wrap) 2936 { 2937 return (ahd_print_register(SEQCTL1_parse_table, 4, "SEQCTL1", 2938 0xd7, regvalue, cur_col, wrap)); 2939 } 2940 2941 static ahd_reg_parse_entry_t FLAGS_parse_table[] = { 2942 { "CARRY", 0x01, 0x01 }, 2943 { "ZERO", 0x02, 0x02 } 2944 }; 2945 2946 int 2947 ahd_flags_print(u_int regvalue, u_int *cur_col, u_int wrap) 2948 { 2949 return (ahd_print_register(FLAGS_parse_table, 2, "FLAGS", 2950 0xd8, regvalue, cur_col, wrap)); 2951 } 2952 2953 static ahd_reg_parse_entry_t SEQINTCTL_parse_table[] = { 2954 { "IRET", 0x01, 0x01 }, 2955 { "INTMASK1", 0x02, 0x02 }, 2956 { "INTMASK2", 0x04, 0x04 }, 2957 { "SCS_SEQ_INT1M0", 0x08, 0x08 }, 2958 { "SCS_SEQ_INT1M1", 0x10, 0x10 }, 2959 { "INT1_CONTEXT", 0x20, 0x20 }, 2960 { "INTVEC1DSL", 0x80, 0x80 } 2961 }; 2962 2963 int 2964 ahd_seqintctl_print(u_int regvalue, u_int *cur_col, u_int wrap) 2965 { 2966 return (ahd_print_register(SEQINTCTL_parse_table, 7, "SEQINTCTL", 2967 0xd9, regvalue, cur_col, wrap)); 2968 } 2969 2970 int 2971 ahd_seqram_print(u_int regvalue, u_int *cur_col, u_int wrap) 2972 { 2973 return (ahd_print_register(NULL, 0, "SEQRAM", 2974 0xda, regvalue, cur_col, wrap)); 2975 } 2976 2977 int 2978 ahd_prgmcnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 2979 { 2980 return (ahd_print_register(NULL, 0, "PRGMCNT", 2981 0xde, regvalue, cur_col, wrap)); 2982 } 2983 2984 int 2985 ahd_accum_print(u_int regvalue, u_int *cur_col, u_int wrap) 2986 { 2987 return (ahd_print_register(NULL, 0, "ACCUM", 2988 0xe0, regvalue, cur_col, wrap)); 2989 } 2990 2991 int 2992 ahd_sindex_print(u_int regvalue, u_int *cur_col, u_int wrap) 2993 { 2994 return (ahd_print_register(NULL, 0, "SINDEX", 2995 0xe2, regvalue, cur_col, wrap)); 2996 } 2997 2998 int 2999 ahd_dindex_print(u_int regvalue, u_int *cur_col, u_int wrap) 3000 { 3001 return (ahd_print_register(NULL, 0, "DINDEX", 3002 0xe4, regvalue, cur_col, wrap)); 3003 } 3004 3005 static ahd_reg_parse_entry_t BRKADDR1_parse_table[] = { 3006 { "BRKDIS", 0x80, 0x80 } 3007 }; 3008 3009 int 3010 ahd_brkaddr1_print(u_int regvalue, u_int *cur_col, u_int wrap) 3011 { 3012 return (ahd_print_register(BRKADDR1_parse_table, 1, "BRKADDR1", 3013 0xe6, regvalue, cur_col, wrap)); 3014 } 3015 3016 int 3017 ahd_brkaddr0_print(u_int regvalue, u_int *cur_col, u_int wrap) 3018 { 3019 return (ahd_print_register(NULL, 0, "BRKADDR0", 3020 0xe6, regvalue, cur_col, wrap)); 3021 } 3022 3023 int 3024 ahd_allones_print(u_int regvalue, u_int *cur_col, u_int wrap) 3025 { 3026 return (ahd_print_register(NULL, 0, "ALLONES", 3027 0xe8, regvalue, cur_col, wrap)); 3028 } 3029 3030 int 3031 ahd_none_print(u_int regvalue, u_int *cur_col, u_int wrap) 3032 { 3033 return (ahd_print_register(NULL, 0, "NONE", 3034 0xea, regvalue, cur_col, wrap)); 3035 } 3036 3037 int 3038 ahd_allzeros_print(u_int regvalue, u_int *cur_col, u_int wrap) 3039 { 3040 return (ahd_print_register(NULL, 0, "ALLZEROS", 3041 0xea, regvalue, cur_col, wrap)); 3042 } 3043 3044 int 3045 ahd_sindir_print(u_int regvalue, u_int *cur_col, u_int wrap) 3046 { 3047 return (ahd_print_register(NULL, 0, "SINDIR", 3048 0xec, regvalue, cur_col, wrap)); 3049 } 3050 3051 int 3052 ahd_dindir_print(u_int regvalue, u_int *cur_col, u_int wrap) 3053 { 3054 return (ahd_print_register(NULL, 0, "DINDIR", 3055 0xed, regvalue, cur_col, wrap)); 3056 } 3057 3058 int 3059 ahd_function1_print(u_int regvalue, u_int *cur_col, u_int wrap) 3060 { 3061 return (ahd_print_register(NULL, 0, "FUNCTION1", 3062 0xf0, regvalue, cur_col, wrap)); 3063 } 3064 3065 int 3066 ahd_stack_print(u_int regvalue, u_int *cur_col, u_int wrap) 3067 { 3068 return (ahd_print_register(NULL, 0, "STACK", 3069 0xf2, regvalue, cur_col, wrap)); 3070 } 3071 3072 int 3073 ahd_intvec1_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3074 { 3075 return (ahd_print_register(NULL, 0, "INTVEC1_ADDR", 3076 0xf4, regvalue, cur_col, wrap)); 3077 } 3078 3079 int 3080 ahd_curaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3081 { 3082 return (ahd_print_register(NULL, 0, "CURADDR", 3083 0xf4, regvalue, cur_col, wrap)); 3084 } 3085 3086 int 3087 ahd_intvec2_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3088 { 3089 return (ahd_print_register(NULL, 0, "INTVEC2_ADDR", 3090 0xf6, regvalue, cur_col, wrap)); 3091 } 3092 3093 int 3094 ahd_lastaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3095 { 3096 return (ahd_print_register(NULL, 0, "LASTADDR", 3097 0xf6, regvalue, cur_col, wrap)); 3098 } 3099 3100 int 3101 ahd_longjmp_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3102 { 3103 return (ahd_print_register(NULL, 0, "LONGJMP_ADDR", 3104 0xf8, regvalue, cur_col, wrap)); 3105 } 3106 3107 int 3108 ahd_accum_save_print(u_int regvalue, u_int *cur_col, u_int wrap) 3109 { 3110 return (ahd_print_register(NULL, 0, "ACCUM_SAVE", 3111 0xfa, regvalue, cur_col, wrap)); 3112 } 3113 3114 int 3115 ahd_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap) 3116 { 3117 return (ahd_print_register(NULL, 0, "SRAM_BASE", 3118 0x100, regvalue, cur_col, wrap)); 3119 } 3120 3121 int 3122 ahd_waiting_scb_tails_print(u_int regvalue, u_int *cur_col, u_int wrap) 3123 { 3124 return (ahd_print_register(NULL, 0, "WAITING_SCB_TAILS", 3125 0x100, regvalue, cur_col, wrap)); 3126 } 3127 3128 int 3129 ahd_ahd_pci_config_base_print(u_int regvalue, u_int *cur_col, u_int wrap) 3130 { 3131 return (ahd_print_register(NULL, 0, "AHD_PCI_CONFIG_BASE", 3132 0x100, regvalue, cur_col, wrap)); 3133 } 3134 3135 int 3136 ahd_waiting_tid_head_print(u_int regvalue, u_int *cur_col, u_int wrap) 3137 { 3138 return (ahd_print_register(NULL, 0, "WAITING_TID_HEAD", 3139 0x120, regvalue, cur_col, wrap)); 3140 } 3141 3142 int 3143 ahd_waiting_tid_tail_print(u_int regvalue, u_int *cur_col, u_int wrap) 3144 { 3145 return (ahd_print_register(NULL, 0, "WAITING_TID_TAIL", 3146 0x122, regvalue, cur_col, wrap)); 3147 } 3148 3149 int 3150 ahd_next_queued_scb_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3151 { 3152 return (ahd_print_register(NULL, 0, "NEXT_QUEUED_SCB_ADDR", 3153 0x124, regvalue, cur_col, wrap)); 3154 } 3155 3156 int 3157 ahd_complete_scb_head_print(u_int regvalue, u_int *cur_col, u_int wrap) 3158 { 3159 return (ahd_print_register(NULL, 0, "COMPLETE_SCB_HEAD", 3160 0x128, regvalue, cur_col, wrap)); 3161 } 3162 3163 int 3164 ahd_complete_scb_dmainprog_head_print(u_int regvalue, u_int *cur_col, u_int wrap) 3165 { 3166 return (ahd_print_register(NULL, 0, "COMPLETE_SCB_DMAINPROG_HEAD", 3167 0x12a, regvalue, cur_col, wrap)); 3168 } 3169 3170 int 3171 ahd_complete_dma_scb_head_print(u_int regvalue, u_int *cur_col, u_int wrap) 3172 { 3173 return (ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_HEAD", 3174 0x12c, regvalue, cur_col, wrap)); 3175 } 3176 3177 int 3178 ahd_complete_dma_scb_tail_print(u_int regvalue, u_int *cur_col, u_int wrap) 3179 { 3180 return (ahd_print_register(NULL, 0, "COMPLETE_DMA_SCB_TAIL", 3181 0x12e, regvalue, cur_col, wrap)); 3182 } 3183 3184 int 3185 ahd_complete_on_qfreeze_head_print(u_int regvalue, u_int *cur_col, u_int wrap) 3186 { 3187 return (ahd_print_register(NULL, 0, "COMPLETE_ON_QFREEZE_HEAD", 3188 0x130, regvalue, cur_col, wrap)); 3189 } 3190 3191 int 3192 ahd_qfreeze_count_print(u_int regvalue, u_int *cur_col, u_int wrap) 3193 { 3194 return (ahd_print_register(NULL, 0, "QFREEZE_COUNT", 3195 0x132, regvalue, cur_col, wrap)); 3196 } 3197 3198 int 3199 ahd_kernel_qfreeze_count_print(u_int regvalue, u_int *cur_col, u_int wrap) 3200 { 3201 return (ahd_print_register(NULL, 0, "KERNEL_QFREEZE_COUNT", 3202 0x134, regvalue, cur_col, wrap)); 3203 } 3204 3205 int 3206 ahd_saved_mode_print(u_int regvalue, u_int *cur_col, u_int wrap) 3207 { 3208 return (ahd_print_register(NULL, 0, "SAVED_MODE", 3209 0x136, regvalue, cur_col, wrap)); 3210 } 3211 3212 int 3213 ahd_msg_out_print(u_int regvalue, u_int *cur_col, u_int wrap) 3214 { 3215 return (ahd_print_register(NULL, 0, "MSG_OUT", 3216 0x137, regvalue, cur_col, wrap)); 3217 } 3218 3219 static ahd_reg_parse_entry_t DMAPARAMS_parse_table[] = { 3220 { "FIFORESET", 0x01, 0x01 }, 3221 { "FIFOFLUSH", 0x02, 0x02 }, 3222 { "DIRECTION", 0x04, 0x04 }, 3223 { "HDMAEN", 0x08, 0x08 }, 3224 { "HDMAENACK", 0x08, 0x08 }, 3225 { "SDMAEN", 0x10, 0x10 }, 3226 { "SDMAENACK", 0x10, 0x10 }, 3227 { "SCSIEN", 0x20, 0x20 }, 3228 { "WIDEODD", 0x40, 0x40 }, 3229 { "PRELOADEN", 0x80, 0x80 } 3230 }; 3231 3232 int 3233 ahd_dmaparams_print(u_int regvalue, u_int *cur_col, u_int wrap) 3234 { 3235 return (ahd_print_register(DMAPARAMS_parse_table, 10, "DMAPARAMS", 3236 0x138, regvalue, cur_col, wrap)); 3237 } 3238 3239 static ahd_reg_parse_entry_t SEQ_FLAGS_parse_table[] = { 3240 { "NO_DISCONNECT", 0x01, 0x01 }, 3241 { "SPHASE_PENDING", 0x02, 0x02 }, 3242 { "DPHASE_PENDING", 0x04, 0x04 }, 3243 { "CMDPHASE_PENDING", 0x08, 0x08 }, 3244 { "TARG_CMD_PENDING", 0x10, 0x10 }, 3245 { "DPHASE", 0x20, 0x20 }, 3246 { "NO_CDB_SENT", 0x40, 0x40 }, 3247 { "TARGET_CMD_IS_TAGGED",0x40, 0x40 }, 3248 { "NOT_IDENTIFIED", 0x80, 0x80 } 3249 }; 3250 3251 int 3252 ahd_seq_flags_print(u_int regvalue, u_int *cur_col, u_int wrap) 3253 { 3254 return (ahd_print_register(SEQ_FLAGS_parse_table, 9, "SEQ_FLAGS", 3255 0x139, regvalue, cur_col, wrap)); 3256 } 3257 3258 int 3259 ahd_saved_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap) 3260 { 3261 return (ahd_print_register(NULL, 0, "SAVED_SCSIID", 3262 0x13a, regvalue, cur_col, wrap)); 3263 } 3264 3265 int 3266 ahd_saved_lun_print(u_int regvalue, u_int *cur_col, u_int wrap) 3267 { 3268 return (ahd_print_register(NULL, 0, "SAVED_LUN", 3269 0x13b, regvalue, cur_col, wrap)); 3270 } 3271 3272 static ahd_reg_parse_entry_t LASTPHASE_parse_table[] = { 3273 { "P_DATAOUT", 0x00, 0xe0 }, 3274 { "P_DATAOUT_DT", 0x20, 0xe0 }, 3275 { "P_DATAIN", 0x40, 0xe0 }, 3276 { "P_DATAIN_DT", 0x60, 0xe0 }, 3277 { "P_COMMAND", 0x80, 0xe0 }, 3278 { "P_MESGOUT", 0xa0, 0xe0 }, 3279 { "P_STATUS", 0xc0, 0xe0 }, 3280 { "P_MESGIN", 0xe0, 0xe0 }, 3281 { "P_BUSFREE", 0x01, 0x01 }, 3282 { "MSGI", 0x20, 0x20 }, 3283 { "IOI", 0x40, 0x40 }, 3284 { "CDI", 0x80, 0x80 }, 3285 { "PHASE_MASK", 0xe0, 0xe0 } 3286 }; 3287 3288 int 3289 ahd_lastphase_print(u_int regvalue, u_int *cur_col, u_int wrap) 3290 { 3291 return (ahd_print_register(LASTPHASE_parse_table, 13, "LASTPHASE", 3292 0x13c, regvalue, cur_col, wrap)); 3293 } 3294 3295 int 3296 ahd_qoutfifo_entry_valid_tag_print(u_int regvalue, u_int *cur_col, u_int wrap) 3297 { 3298 return (ahd_print_register(NULL, 0, "QOUTFIFO_ENTRY_VALID_TAG", 3299 0x13d, regvalue, cur_col, wrap)); 3300 } 3301 3302 int 3303 ahd_kernel_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap) 3304 { 3305 return (ahd_print_register(NULL, 0, "KERNEL_TQINPOS", 3306 0x13e, regvalue, cur_col, wrap)); 3307 } 3308 3309 int 3310 ahd_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap) 3311 { 3312 return (ahd_print_register(NULL, 0, "TQINPOS", 3313 0x13f, regvalue, cur_col, wrap)); 3314 } 3315 3316 int 3317 ahd_shared_data_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3318 { 3319 return (ahd_print_register(NULL, 0, "SHARED_DATA_ADDR", 3320 0x140, regvalue, cur_col, wrap)); 3321 } 3322 3323 int 3324 ahd_qoutfifo_next_addr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3325 { 3326 return (ahd_print_register(NULL, 0, "QOUTFIFO_NEXT_ADDR", 3327 0x144, regvalue, cur_col, wrap)); 3328 } 3329 3330 static ahd_reg_parse_entry_t ARG_1_parse_table[] = { 3331 { "CONT_MSG_LOOP_TARG", 0x02, 0x02 }, 3332 { "CONT_MSG_LOOP_READ", 0x03, 0x03 }, 3333 { "CONT_MSG_LOOP_WRITE",0x04, 0x04 }, 3334 { "EXIT_MSG_LOOP", 0x08, 0x08 }, 3335 { "MSGOUT_PHASEMIS", 0x10, 0x10 }, 3336 { "SEND_REJ", 0x20, 0x20 }, 3337 { "SEND_SENSE", 0x40, 0x40 }, 3338 { "SEND_MSG", 0x80, 0x80 } 3339 }; 3340 3341 int 3342 ahd_arg_1_print(u_int regvalue, u_int *cur_col, u_int wrap) 3343 { 3344 return (ahd_print_register(ARG_1_parse_table, 8, "ARG_1", 3345 0x148, regvalue, cur_col, wrap)); 3346 } 3347 3348 int 3349 ahd_arg_2_print(u_int regvalue, u_int *cur_col, u_int wrap) 3350 { 3351 return (ahd_print_register(NULL, 0, "ARG_2", 3352 0x149, regvalue, cur_col, wrap)); 3353 } 3354 3355 int 3356 ahd_last_msg_print(u_int regvalue, u_int *cur_col, u_int wrap) 3357 { 3358 return (ahd_print_register(NULL, 0, "LAST_MSG", 3359 0x14a, regvalue, cur_col, wrap)); 3360 } 3361 3362 static ahd_reg_parse_entry_t SCSISEQ_TEMPLATE_parse_table[] = { 3363 { "ALTSTIM", 0x01, 0x01 }, 3364 { "ENAUTOATNP", 0x02, 0x02 }, 3365 { "MANUALP", 0x0c, 0x0c }, 3366 { "ENRSELI", 0x10, 0x10 }, 3367 { "ENSELI", 0x20, 0x20 }, 3368 { "MANUALCTL", 0x40, 0x40 } 3369 }; 3370 3371 int 3372 ahd_scsiseq_template_print(u_int regvalue, u_int *cur_col, u_int wrap) 3373 { 3374 return (ahd_print_register(SCSISEQ_TEMPLATE_parse_table, 6, "SCSISEQ_TEMPLATE", 3375 0x14b, regvalue, cur_col, wrap)); 3376 } 3377 3378 int 3379 ahd_initiator_tag_print(u_int regvalue, u_int *cur_col, u_int wrap) 3380 { 3381 return (ahd_print_register(NULL, 0, "INITIATOR_TAG", 3382 0x14c, regvalue, cur_col, wrap)); 3383 } 3384 3385 static ahd_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = { 3386 { "PENDING_MK_MESSAGE", 0x01, 0x01 }, 3387 { "TARGET_MSG_PENDING", 0x02, 0x02 }, 3388 { "SELECTOUT_QFROZEN", 0x04, 0x04 } 3389 }; 3390 3391 int 3392 ahd_seq_flags2_print(u_int regvalue, u_int *cur_col, u_int wrap) 3393 { 3394 return (ahd_print_register(SEQ_FLAGS2_parse_table, 3, "SEQ_FLAGS2", 3395 0x14d, regvalue, cur_col, wrap)); 3396 } 3397 3398 int 3399 ahd_allocfifo_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3400 { 3401 return (ahd_print_register(NULL, 0, "ALLOCFIFO_SCBPTR", 3402 0x14e, regvalue, cur_col, wrap)); 3403 } 3404 3405 int 3406 ahd_int_coalescing_timer_print(u_int regvalue, u_int *cur_col, u_int wrap) 3407 { 3408 return (ahd_print_register(NULL, 0, "INT_COALESCING_TIMER", 3409 0x150, regvalue, cur_col, wrap)); 3410 } 3411 3412 int 3413 ahd_int_coalescing_maxcmds_print(u_int regvalue, u_int *cur_col, u_int wrap) 3414 { 3415 return (ahd_print_register(NULL, 0, "INT_COALESCING_MAXCMDS", 3416 0x152, regvalue, cur_col, wrap)); 3417 } 3418 3419 int 3420 ahd_int_coalescing_mincmds_print(u_int regvalue, u_int *cur_col, u_int wrap) 3421 { 3422 return (ahd_print_register(NULL, 0, "INT_COALESCING_MINCMDS", 3423 0x153, regvalue, cur_col, wrap)); 3424 } 3425 3426 int 3427 ahd_cmds_pending_print(u_int regvalue, u_int *cur_col, u_int wrap) 3428 { 3429 return (ahd_print_register(NULL, 0, "CMDS_PENDING", 3430 0x154, regvalue, cur_col, wrap)); 3431 } 3432 3433 int 3434 ahd_int_coalescing_cmdcount_print(u_int regvalue, u_int *cur_col, u_int wrap) 3435 { 3436 return (ahd_print_register(NULL, 0, "INT_COALESCING_CMDCOUNT", 3437 0x156, regvalue, cur_col, wrap)); 3438 } 3439 3440 int 3441 ahd_local_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap) 3442 { 3443 return (ahd_print_register(NULL, 0, "LOCAL_HS_MAILBOX", 3444 0x157, regvalue, cur_col, wrap)); 3445 } 3446 3447 int 3448 ahd_cmdsize_table_print(u_int regvalue, u_int *cur_col, u_int wrap) 3449 { 3450 return (ahd_print_register(NULL, 0, "CMDSIZE_TABLE", 3451 0x158, regvalue, cur_col, wrap)); 3452 } 3453 3454 int 3455 ahd_mk_message_scb_print(u_int regvalue, u_int *cur_col, u_int wrap) 3456 { 3457 return (ahd_print_register(NULL, 0, "MK_MESSAGE_SCB", 3458 0x160, regvalue, cur_col, wrap)); 3459 } 3460 3461 int 3462 ahd_mk_message_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap) 3463 { 3464 return (ahd_print_register(NULL, 0, "MK_MESSAGE_SCSIID", 3465 0x162, regvalue, cur_col, wrap)); 3466 } 3467 3468 int 3469 ahd_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap) 3470 { 3471 return (ahd_print_register(NULL, 0, "SCB_BASE", 3472 0x180, regvalue, cur_col, wrap)); 3473 } 3474 3475 int 3476 ahd_scb_residual_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 3477 { 3478 return (ahd_print_register(NULL, 0, "SCB_RESIDUAL_DATACNT", 3479 0x180, regvalue, cur_col, wrap)); 3480 } 3481 3482 static ahd_reg_parse_entry_t SCB_RESIDUAL_SGPTR_parse_table[] = { 3483 { "SG_LIST_NULL", 0x01, 0x01 }, 3484 { "SG_OVERRUN_RESID", 0x02, 0x02 }, 3485 { "SG_ADDR_BIT", 0x04, 0x04 }, 3486 { "SG_ADDR_MASK", 0xf8, 0xf8 } 3487 }; 3488 3489 int 3490 ahd_scb_residual_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3491 { 3492 return (ahd_print_register(SCB_RESIDUAL_SGPTR_parse_table, 4, "SCB_RESIDUAL_SGPTR", 3493 0x184, regvalue, cur_col, wrap)); 3494 } 3495 3496 int 3497 ahd_scb_scsi_status_print(u_int regvalue, u_int *cur_col, u_int wrap) 3498 { 3499 return (ahd_print_register(NULL, 0, "SCB_SCSI_STATUS", 3500 0x188, regvalue, cur_col, wrap)); 3501 } 3502 3503 int 3504 ahd_scb_target_phases_print(u_int regvalue, u_int *cur_col, u_int wrap) 3505 { 3506 return (ahd_print_register(NULL, 0, "SCB_TARGET_PHASES", 3507 0x189, regvalue, cur_col, wrap)); 3508 } 3509 3510 int 3511 ahd_scb_target_data_dir_print(u_int regvalue, u_int *cur_col, u_int wrap) 3512 { 3513 return (ahd_print_register(NULL, 0, "SCB_TARGET_DATA_DIR", 3514 0x18a, regvalue, cur_col, wrap)); 3515 } 3516 3517 int 3518 ahd_scb_target_itag_print(u_int regvalue, u_int *cur_col, u_int wrap) 3519 { 3520 return (ahd_print_register(NULL, 0, "SCB_TARGET_ITAG", 3521 0x18b, regvalue, cur_col, wrap)); 3522 } 3523 3524 int 3525 ahd_scb_sense_busaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3526 { 3527 return (ahd_print_register(NULL, 0, "SCB_SENSE_BUSADDR", 3528 0x18c, regvalue, cur_col, wrap)); 3529 } 3530 3531 int 3532 ahd_scb_tag_print(u_int regvalue, u_int *cur_col, u_int wrap) 3533 { 3534 return (ahd_print_register(NULL, 0, "SCB_TAG", 3535 0x190, regvalue, cur_col, wrap)); 3536 } 3537 3538 static ahd_reg_parse_entry_t SCB_CONTROL_parse_table[] = { 3539 { "SCB_TAG_TYPE", 0x03, 0x03 }, 3540 { "DISCONNECTED", 0x04, 0x04 }, 3541 { "STATUS_RCVD", 0x08, 0x08 }, 3542 { "MK_MESSAGE", 0x10, 0x10 }, 3543 { "TAG_ENB", 0x20, 0x20 }, 3544 { "DISCENB", 0x40, 0x40 }, 3545 { "TARGET_SCB", 0x80, 0x80 } 3546 }; 3547 3548 int 3549 ahd_scb_control_print(u_int regvalue, u_int *cur_col, u_int wrap) 3550 { 3551 return (ahd_print_register(SCB_CONTROL_parse_table, 7, "SCB_CONTROL", 3552 0x192, regvalue, cur_col, wrap)); 3553 } 3554 3555 static ahd_reg_parse_entry_t SCB_SCSIID_parse_table[] = { 3556 { "OID", 0x0f, 0x0f }, 3557 { "TID", 0xf0, 0xf0 } 3558 }; 3559 3560 int 3561 ahd_scb_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap) 3562 { 3563 return (ahd_print_register(SCB_SCSIID_parse_table, 2, "SCB_SCSIID", 3564 0x193, regvalue, cur_col, wrap)); 3565 } 3566 3567 static ahd_reg_parse_entry_t SCB_LUN_parse_table[] = { 3568 { "LID", 0xff, 0xff } 3569 }; 3570 3571 int 3572 ahd_scb_lun_print(u_int regvalue, u_int *cur_col, u_int wrap) 3573 { 3574 return (ahd_print_register(SCB_LUN_parse_table, 1, "SCB_LUN", 3575 0x194, regvalue, cur_col, wrap)); 3576 } 3577 3578 static ahd_reg_parse_entry_t SCB_TASK_ATTRIBUTE_parse_table[] = { 3579 { "SCB_XFERLEN_ODD", 0x01, 0x01 } 3580 }; 3581 3582 int 3583 ahd_scb_task_attribute_print(u_int regvalue, u_int *cur_col, u_int wrap) 3584 { 3585 return (ahd_print_register(SCB_TASK_ATTRIBUTE_parse_table, 1, "SCB_TASK_ATTRIBUTE", 3586 0x195, regvalue, cur_col, wrap)); 3587 } 3588 3589 static ahd_reg_parse_entry_t SCB_CDB_LEN_parse_table[] = { 3590 { "SCB_CDB_LEN_PTR", 0x80, 0x80 } 3591 }; 3592 3593 int 3594 ahd_scb_cdb_len_print(u_int regvalue, u_int *cur_col, u_int wrap) 3595 { 3596 return (ahd_print_register(SCB_CDB_LEN_parse_table, 1, "SCB_CDB_LEN", 3597 0x196, regvalue, cur_col, wrap)); 3598 } 3599 3600 int 3601 ahd_scb_task_management_print(u_int regvalue, u_int *cur_col, u_int wrap) 3602 { 3603 return (ahd_print_register(NULL, 0, "SCB_TASK_MANAGEMENT", 3604 0x197, regvalue, cur_col, wrap)); 3605 } 3606 3607 int 3608 ahd_scb_dataptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3609 { 3610 return (ahd_print_register(NULL, 0, "SCB_DATAPTR", 3611 0x198, regvalue, cur_col, wrap)); 3612 } 3613 3614 static ahd_reg_parse_entry_t SCB_DATACNT_parse_table[] = { 3615 { "SG_HIGH_ADDR_BITS", 0x7f, 0x7f }, 3616 { "SG_LAST_SEG", 0x80, 0x80 } 3617 }; 3618 3619 int 3620 ahd_scb_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap) 3621 { 3622 return (ahd_print_register(SCB_DATACNT_parse_table, 2, "SCB_DATACNT", 3623 0x1a0, regvalue, cur_col, wrap)); 3624 } 3625 3626 static ahd_reg_parse_entry_t SCB_SGPTR_parse_table[] = { 3627 { "SG_LIST_NULL", 0x01, 0x01 }, 3628 { "SG_FULL_RESID", 0x02, 0x02 }, 3629 { "SG_STATUS_VALID", 0x04, 0x04 } 3630 }; 3631 3632 int 3633 ahd_scb_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3634 { 3635 return (ahd_print_register(SCB_SGPTR_parse_table, 3, "SCB_SGPTR", 3636 0x1a4, regvalue, cur_col, wrap)); 3637 } 3638 3639 int 3640 ahd_scb_busaddr_print(u_int regvalue, u_int *cur_col, u_int wrap) 3641 { 3642 return (ahd_print_register(NULL, 0, "SCB_BUSADDR", 3643 0x1a8, regvalue, cur_col, wrap)); 3644 } 3645 3646 int 3647 ahd_scb_next_print(u_int regvalue, u_int *cur_col, u_int wrap) 3648 { 3649 return (ahd_print_register(NULL, 0, "SCB_NEXT", 3650 0x1ac, regvalue, cur_col, wrap)); 3651 } 3652 3653 int 3654 ahd_scb_next2_print(u_int regvalue, u_int *cur_col, u_int wrap) 3655 { 3656 return (ahd_print_register(NULL, 0, "SCB_NEXT2", 3657 0x1ae, regvalue, cur_col, wrap)); 3658 } 3659 3660 int 3661 ahd_scb_spare_print(u_int regvalue, u_int *cur_col, u_int wrap) 3662 { 3663 return (ahd_print_register(NULL, 0, "SCB_SPARE", 3664 0x1b0, regvalue, cur_col, wrap)); 3665 } 3666 3667 int 3668 ahd_scb_disconnected_lists_print(u_int regvalue, u_int *cur_col, u_int wrap) 3669 { 3670 return (ahd_print_register(NULL, 0, "SCB_DISCONNECTED_LISTS", 3671 0x1b8, regvalue, cur_col, wrap)); 3672 } 3673