1 /* 2 * Product specific probe and attach routines for: 3 * aic7901 and aic7902 SCSI controllers 4 * 5 * Copyright (c) 1994-2001 Justin T. Gibbs. 6 * Copyright (c) 2000-2001 Adaptec Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 16 * substantially similar to the "NO WARRANTY" disclaimer below 17 * ("Disclaimer") and any redistribution must be conditioned upon 18 * including a substantially similar Disclaimer requirement for further 19 * binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 38 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGES. 40 * 41 * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#33 $ 42 * 43 * $FreeBSD$ 44 */ 45 46 #ifdef __linux__ 47 #include "aic79xx_osm.h" 48 #include "aic79xx_inline.h" 49 #else 50 #include <dev/aic7xxx/aic79xx_osm.h> 51 #include <dev/aic7xxx/aic79xx_inline.h> 52 #endif 53 54 static __inline uint64_t 55 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 56 { 57 uint64_t id; 58 59 id = subvendor 60 | (subdevice << 16) 61 | ((uint64_t)vendor << 32) 62 | ((uint64_t)device << 48); 63 64 return (id); 65 } 66 67 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 68 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 69 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 70 71 #define ID_AIC7901 0x800F9005FFFF9005ull 72 #define ID_AIC7901_IROC 0x80089005FFFF9005ull 73 #define ID_AHA_29320 0x8000900500609005ull 74 #define ID_AHA_29320LP 0x8000900500409005ull 75 76 #define ID_AIC7902 0x801F9005FFFF9005ull 77 #define ID_AIC7902_IROC 0x80189005FFFF9005ull 78 #define ID_AHA_39320 0x8010900500409005ull 79 #define ID_AHA_39320D 0x8011900500419005ull 80 #define ID_AHA_39320D_CPQ 0x8011900500AC0E11ull 81 #define ID_AIC7902_PCI_REV_A3 0x2 82 #define ID_AIC7902_PCI_REV_A4 0x3 83 #define ID_AIC7902_PCI_REV_B0 0xFF /* Rev Id not yet known. */ 84 #define SUBID_CPQ 0x0E11 85 86 #define DEVID_9005_TYPE(id) ((id) & 0xF) 87 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 88 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 89 #define DEVID_9005_TYPE_IROC 0x8 /* Raid(0,1,10) Card */ 90 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 91 92 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 93 94 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 95 96 #define SUBID_9005_TYPE(id) ((id) & 0xF) 97 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 98 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 99 100 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 101 102 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 103 104 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 105 #define SUBID_9005_SEEPTYPE_NONE 0x0 106 #define SUBID_9005_SEEPTYPE_4K 0x1 107 108 static ahd_device_setup_t ahd_aic7901_setup; 109 static ahd_device_setup_t ahd_aic7902_setup; 110 111 struct ahd_pci_identity ahd_pci_ident_table [] = 112 { 113 /* aic7901 based controllers */ 114 { 115 ID_AHA_29320, 116 ID_ALL_MASK, 117 "Adaptec 29320 Ultra320 SCSI adapter", 118 ahd_aic7901_setup 119 }, 120 { 121 ID_AHA_29320LP, 122 ID_ALL_MASK, 123 "Adaptec 29320LP Ultra320 SCSI adapter", 124 ahd_aic7901_setup 125 }, 126 /* aic7902 based controllers */ 127 { 128 ID_AHA_39320, 129 ID_ALL_MASK, 130 "Adaptec 39320 Ultra320 SCSI adapter", 131 ahd_aic7902_setup 132 }, 133 { 134 ID_AHA_39320D, 135 ID_ALL_MASK, 136 "Adaptec 39320D Ultra320 SCSI adapter", 137 ahd_aic7902_setup 138 }, 139 { 140 ID_AHA_39320D_CPQ, 141 ID_ALL_MASK, 142 "Adaptec (Compaq OEM) 39320D Ultra320 SCSI adapter", 143 ahd_aic7902_setup 144 }, 145 /* Generic chip probes for devices we don't know 'exactly' */ 146 { 147 ID_AIC7901 & ID_9005_GENERIC_MASK, 148 ID_9005_GENERIC_MASK, 149 "Adaptec aic7901 Ultra320 SCSI adapter", 150 ahd_aic7901_setup 151 }, 152 { 153 ID_AIC7902 & ID_9005_GENERIC_MASK, 154 ID_9005_GENERIC_MASK, 155 "Adaptec aic7902 Ultra320 SCSI adapter", 156 ahd_aic7902_setup 157 } 158 }; 159 160 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 161 162 #define DEVCONFIG 0x40 163 #define PCIXINITPAT 0x0000E000ul 164 #define PCIXINIT_PCI33_66 0x0000E000ul 165 #define PCIXINIT_PCIX50_66 0x0000C000ul 166 #define PCIXINIT_PCIX66_100 0x0000A000ul 167 #define PCIXINIT_PCIX100_133 0x00008000ul 168 #define PCI_BUS_MODES_INDEX(devconfig) \ 169 (((devconfig) & PCIXINITPAT) >> 13) 170 static const char *pci_bus_modes[] = 171 { 172 "PCI bus mode unknown", 173 "PCI bus mode unknown", 174 "PCI bus mode unknown", 175 "PCI bus mode unknown", 176 "PCI-X 101-133Mhz", 177 "PCI-X 67-100Mhz", 178 "PCI-X 50-66Mhz", 179 "PCI 33 or 66Mhz" 180 }; 181 182 #define TESTMODE 0x00000800ul 183 #define IRDY_RST 0x00000200ul 184 #define FRAME_RST 0x00000100ul 185 #define PCI64BIT 0x00000080ul 186 #define MRDCEN 0x00000040ul 187 #define ENDIANSEL 0x00000020ul 188 #define MIXQWENDIANEN 0x00000008ul 189 #define DACEN 0x00000004ul 190 #define STPWLEVEL 0x00000002ul 191 #define QWENDIANSEL 0x00000001ul 192 193 #define DEVCONFIG1 0x44 194 #define PREQDIS 0x01 195 196 #define CSIZE_LATTIME 0x0c 197 #define CACHESIZE 0x000000fful 198 #define LATTIME 0x0000ff00ul 199 200 static int ahd_check_extport(struct ahd_softc *ahd); 201 static void ahd_configure_termination(struct ahd_softc *ahd, 202 u_int adapter_control); 203 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 204 205 struct ahd_pci_identity * 206 ahd_find_pci_device(ahd_dev_softc_t pci) 207 { 208 uint64_t full_id; 209 uint16_t device; 210 uint16_t vendor; 211 uint16_t subdevice; 212 uint16_t subvendor; 213 struct ahd_pci_identity *entry; 214 u_int i; 215 216 vendor = ahd_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 217 device = ahd_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 218 subvendor = ahd_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 219 subdevice = ahd_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 220 full_id = ahd_compose_id(device, 221 vendor, 222 subdevice, 223 subvendor); 224 225 for (i = 0; i < ahd_num_pci_devs; i++) { 226 entry = &ahd_pci_ident_table[i]; 227 if (entry->full_id == (full_id & entry->id_mask)) { 228 /* Honor exclusion entries. */ 229 if (entry->name == NULL) 230 return (NULL); 231 return (entry); 232 } 233 } 234 return (NULL); 235 } 236 237 int 238 ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry) 239 { 240 struct scb_data *shared_scb_data; 241 u_long l; 242 u_long s; 243 u_int command; 244 uint32_t devconfig; 245 uint16_t subvendor; 246 int error; 247 248 shared_scb_data = NULL; 249 error = entry->setup(ahd); 250 if (error != 0) 251 return (error); 252 253 ahd->description = entry->name; 254 devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 255 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 256 ahd->chip |= AHD_PCI; 257 /* Disable PCIX workarounds when running in PCI mode. */ 258 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 259 } else { 260 ahd->chip |= AHD_PCIX; 261 } 262 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 263 264 /* 265 * Record if this is a Compaq board. 266 */ 267 subvendor = ahd_pci_read_config(ahd->dev_softc, 268 PCIR_SUBVEND_0, /*bytes*/2); 269 if (subvendor == SUBID_CPQ) 270 ahd->flags |= AHD_CPQ_BOARD; 271 272 ahd_power_state_change(ahd, AHD_POWER_STATE_D0); 273 274 error = ahd_pci_map_registers(ahd); 275 if (error != 0) 276 return (error); 277 278 /* 279 * If we need to support high memory, enable dual 280 * address cycles. This bit must be set to enable 281 * high address bit generation even if we are on a 282 * 64bit bus (PCI64BIT set in devconfig). 283 */ 284 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 285 uint32_t devconfig; 286 287 if (bootverbose) 288 printf("%s: Enabling 39Bit Addressing\n", 289 ahd_name(ahd)); 290 devconfig = ahd_pci_read_config(ahd->dev_softc, 291 DEVCONFIG, /*bytes*/4); 292 devconfig |= DACEN; 293 ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, 294 devconfig, /*bytes*/4); 295 } 296 297 /* Ensure busmastering is enabled */ 298 command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/1); 299 command |= PCIM_CMD_BUSMASTEREN; 300 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/1); 301 302 error = ahd_softc_init(ahd); 303 if (error != 0) 304 return (error); 305 306 ahd->bus_intr = ahd_pci_intr; 307 308 error = ahd_reset(ahd); 309 if (error != 0) 310 return (ENXIO); 311 312 ahd->pci_cachesize = 313 ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME, 314 /*bytes*/1) & CACHESIZE; 315 ahd->pci_cachesize *= 4; 316 317 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 318 /* See if we have a SEEPROM and perform auto-term */ 319 error = ahd_check_extport(ahd); 320 if (error != 0) 321 return (error); 322 323 /* Core initialization */ 324 error = ahd_init(ahd); 325 if (error != 0) 326 return (error); 327 328 /* 329 * Allow interrupts now that we are completely setup. 330 */ 331 error = ahd_pci_map_int(ahd); 332 if (error != 0) 333 return (error); 334 335 ahd_list_lock(&l); 336 /* 337 * Link this softc in with all other ahd instances. 338 */ 339 ahd_softc_insert(ahd); 340 341 ahd_lock(ahd, &s); 342 ahd_intr_enable(ahd, TRUE); 343 ahd_unlock(ahd, &s); 344 345 ahd_list_unlock(&l); 346 return (0); 347 } 348 349 /* 350 * Check the external port logic for a serial eeprom 351 * and termination/cable detection contrls. 352 */ 353 static int 354 ahd_check_extport(struct ahd_softc *ahd) 355 { 356 struct seeprom_config *sc; 357 u_int adapter_control; 358 int have_seeprom; 359 int error; 360 361 sc = ahd->seep_config; 362 have_seeprom = ahd_acquire_seeprom(ahd); 363 if (have_seeprom) { 364 u_int start_addr; 365 366 if (bootverbose) 367 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 368 369 /* Address is always in units of 16bit words */ 370 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 371 372 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 373 start_addr, sizeof(*sc)/2); 374 375 if (error != 0) { 376 printf("Unable to read SEEPROM\n"); 377 have_seeprom = 0; 378 } else { 379 have_seeprom = ahd_verify_cksum(sc); 380 381 if (bootverbose) { 382 if (have_seeprom == 0) 383 printf ("checksum error\n"); 384 else 385 printf ("done.\n"); 386 } 387 } 388 ahd_release_seeprom(ahd); 389 } 390 391 if (!have_seeprom) { 392 u_int nvram_scb; 393 394 /* 395 * Pull scratch ram settings and treat them as 396 * if they are the contents of an seeprom if 397 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 398 * in SCB 0xFF. We manually compose the data as 16bit 399 * values to avoid endian issues. 400 */ 401 ahd_set_scbptr(ahd, 0xFF); 402 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 403 printf("nvram_scb == 0x%x\n", nvram_scb); 404 printf("SCBPTR == 0x%x\n", ahd_get_scbptr(ahd)); 405 printf("Signature = %c%c%c%c\n", 406 ahd_inb_scbram(ahd, SCB_BASE + 0), 407 ahd_inb_scbram(ahd, SCB_BASE + 1), 408 ahd_inb_scbram(ahd, SCB_BASE + 2), 409 ahd_inb_scbram(ahd, SCB_BASE + 3)); 410 if (nvram_scb != 0xFF 411 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 412 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 413 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 414 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 415 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 416 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 417 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 418 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 419 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 420 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 421 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 422 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 423 uint16_t *sc_data; 424 int i; 425 426 ahd_set_scbptr(ahd, nvram_scb); 427 sc_data = (uint16_t *)sc; 428 for (i = 0; i < 64; i += 2) 429 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 430 have_seeprom = ahd_verify_cksum(sc); 431 if (have_seeprom) 432 ahd->flags |= AHD_SCB_CONFIG_USED; 433 } 434 } 435 436 #if AHD_DEBUG 437 if (have_seeprom != 0 438 && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 439 uint8_t *sc_data; 440 int i; 441 442 printf("%s: Seeprom Contents:", ahd_name(ahd)); 443 sc_data = (uint8_t *)sc; 444 for (i = 0; i < (sizeof(*sc)); i += 2) 445 printf("\n\t0x%.4x", 446 sc_data[i] | (sc_data[i+1] << 8)); 447 printf("\n"); 448 } 449 #endif 450 451 if (!have_seeprom) { 452 if (bootverbose) 453 printf("%s: No SEEPROM available.\n", ahd_name(ahd)); 454 ahd->flags |= AHD_USEDEFAULTS; 455 error = ahd_default_config(ahd); 456 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 457 free(ahd->seep_config, M_DEVBUF); 458 ahd->seep_config = NULL; 459 } else { 460 error = ahd_parse_cfgdata(ahd, sc); 461 adapter_control = sc->adapter_control; 462 } 463 if (error != 0) 464 return (error); 465 466 ahd_configure_termination(ahd, adapter_control); 467 468 return (0); 469 } 470 471 static void 472 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 473 { 474 int error; 475 u_int sxfrctl1; 476 uint8_t termctl; 477 uint32_t devconfig; 478 479 devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 480 devconfig &= ~STPWLEVEL; 481 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) { 482 devconfig |= STPWLEVEL; 483 } 484 ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 485 486 /* Make sure current sensing is off. */ 487 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 488 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 489 } 490 491 /* 492 * Read to sense. Write to set. 493 */ 494 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 495 if ((adapter_control & CFAUTOTERM) == 0) { 496 if (bootverbose) 497 printf("%s: Manual Primary Termination\n", 498 ahd_name(ahd)); 499 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 500 if ((adapter_control & CFSTERM) != 0) 501 termctl |= FLX_TERMCTL_ENPRILOW; 502 if ((adapter_control & CFWSTERM) != 0) 503 termctl |= FLX_TERMCTL_ENPRIHIGH; 504 } else if (error != 0) { 505 printf("%s: Primary Auto-Term Sensing failed! " 506 "Using Defaults.\n", ahd_name(ahd)); 507 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 508 } 509 510 if ((adapter_control & CFSEAUTOTERM) == 0) { 511 if (bootverbose) 512 printf("%s: Manual Secondary Termination\n", 513 ahd_name(ahd)); 514 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 515 if ((adapter_control & CFSELOWTERM) != 0) 516 termctl |= FLX_TERMCTL_ENSECLOW; 517 if ((adapter_control & CFSEHIGHTERM) != 0) 518 termctl |= FLX_TERMCTL_ENSECHIGH; 519 } else if (error != 0) { 520 printf("%s: Secondary Auto-Term Sensing failed! " 521 "Using Defaults.\n", ahd_name(ahd)); 522 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 523 } 524 525 /* 526 * Now set the termination based on what we found. 527 */ 528 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 529 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 530 ahd->flags |= AHD_TERM_ENB_A; 531 sxfrctl1 |= STPWEN; 532 } 533 /* Must set the latch once in order to be effective. */ 534 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 535 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 536 537 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 538 if (error != 0) { 539 printf("%s: Unable to set termination settings!\n", 540 ahd_name(ahd)); 541 } else if (bootverbose) { 542 printf("%s: Primary High byte termination %sabled\n", 543 ahd_name(ahd), 544 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 545 546 printf("%s: Primary Low byte termination %sabled\n", 547 ahd_name(ahd), 548 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 549 550 printf("%s: Secondary High byte termination %sabled\n", 551 ahd_name(ahd), 552 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 553 554 printf("%s: Secondary Low byte termination %sabled\n", 555 ahd_name(ahd), 556 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 557 } 558 return; 559 } 560 561 #define DPE 0x80 562 #define SSE 0x40 563 #define RMA 0x20 564 #define RTA 0x10 565 #define STA 0x08 566 #define DPR 0x01 567 568 static const char *split_status_source[] = 569 { 570 "DFF0", 571 "DFF1", 572 "OVLY", 573 "CMC", 574 }; 575 576 static const char *pci_status_source[] = 577 { 578 "DFF0", 579 "DFF1", 580 "SG", 581 "CMC", 582 "OVLY", 583 "NONE", 584 "MSI", 585 "TARG" 586 }; 587 588 static const char *split_status_strings[] = 589 { 590 "%s: Received split response in %s.\n" 591 "%s: Received split completion error message in %s\n", 592 "%s: Receive overrun in %s\n", 593 "%s: Count not complete in %s\n", 594 "%s: Split completion data bucket in %s\n", 595 "%s: Split completion address error in %s\n", 596 "%s: Split completion byte count error in %s\n", 597 "%s: Signaled Target-abort to early terminate a split in %s\n", 598 }; 599 600 static const char *pci_status_strings[] = 601 { 602 "%s: Data Parity Error has been reported via PERR# in %s\n", 603 "%s: Target initial wait state error in %s\n", 604 "%s: Split completion read data parity error in %s\n", 605 "%s: Split completion address attribute parity error in %s\n", 606 "%s: Received a Target Abort in %s\n", 607 "%s: Received a Master Abort in %s\n", 608 "%s: Signal System Error Detected in %s\n", 609 "%s: Address or Write Phase Parity Error Detected in %s.\n" 610 }; 611 612 void 613 ahd_pci_intr(struct ahd_softc *ahd) 614 { 615 uint8_t pci_status[8]; 616 ahd_mode_state saved_modes; 617 u_int pci_status1; 618 u_int intstat; 619 u_int i; 620 u_int reg; 621 622 intstat = ahd_inb(ahd, INTSTAT); 623 624 if ((intstat & SPLTINT) != 0) 625 ahd_pci_split_intr(ahd, intstat); 626 627 if ((intstat & PCIINT) == 0) 628 return; 629 630 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 631 saved_modes = ahd_save_modes(ahd); 632 ahd_dump_card_state(ahd); 633 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 634 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 635 636 if (i == 5) 637 continue; 638 pci_status[i] = ahd_inb(ahd, reg); 639 /* Clear latched errors. So our interupt deasserts. */ 640 ahd_outb(ahd, reg, pci_status[i]); 641 } 642 643 for (i = 0; i < 8; i++) { 644 u_int bit; 645 646 if (i == 5) 647 continue; 648 649 for (bit = 0; bit < 8; bit++) { 650 651 if ((pci_status[i] & (0x1 << bit)) != 0) { 652 static const char *s; 653 654 s = pci_status_strings[bit]; 655 if (i == 7/*TARG*/ && bit == 3) 656 s = "%s: Signal Target Abort\n"; 657 printf(s, ahd_name(ahd), pci_status_source[i]); 658 } 659 } 660 } 661 pci_status1 = ahd_pci_read_config(ahd->dev_softc, 662 PCIR_STATUS + 1, /*bytes*/1); 663 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 664 pci_status1, /*bytes*/1); 665 ahd_restore_modes(ahd, saved_modes); 666 ahd_unpause(ahd); 667 } 668 669 static void 670 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 671 { 672 uint8_t split_status[4]; 673 uint8_t split_status1[4]; 674 uint8_t sg_split_status[2]; 675 uint8_t sg_split_status1[2]; 676 ahd_mode_state saved_modes; 677 u_int i; 678 uint16_t pcix_status; 679 680 /* 681 * Check for splits in all modes. Modes 0 and 1 682 * additionally have SG engine splits to look at. 683 */ 684 pcix_status = ahd_pci_read_config(ahd->dev_softc, PCIXR_STATUS, 685 /*bytes*/2); 686 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 687 ahd_name(ahd), pcix_status); 688 saved_modes = ahd_save_modes(ahd); 689 for (i = 0; i < 4; i++) { 690 ahd_set_modes(ahd, i, i); 691 692 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 693 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 694 /* Clear latched errors. So our interupt deasserts. */ 695 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 696 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 697 if (i != 0) 698 continue; 699 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 700 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 701 /* Clear latched errors. So our interupt deasserts. */ 702 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 703 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 704 } 705 706 for (i = 0; i < 4; i++) { 707 u_int bit; 708 709 for (bit = 0; bit < 8; bit++) { 710 711 if ((split_status[i] & (0x1 << bit)) != 0) { 712 static const char *s; 713 714 s = split_status_strings[bit]; 715 printf(s, ahd_name(ahd), 716 split_status_source[i]); 717 } 718 719 if (i != 0) 720 continue; 721 722 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 723 static const char *s; 724 725 s = split_status_strings[bit]; 726 printf(s, ahd_name(ahd), "SG"); 727 } 728 } 729 } 730 /* 731 * Clear PCI-X status bits. 732 */ 733 ahd_pci_write_config(ahd->dev_softc, PCIXR_STATUS, 734 pcix_status, /*bytes*/2); 735 ahd_restore_modes(ahd, saved_modes); 736 } 737 738 static int 739 ahd_aic7901_setup(struct ahd_softc *ahd) 740 { 741 ahd_dev_softc_t pci; 742 743 pci = ahd->dev_softc; 744 ahd->channel = 'A'; 745 ahd->chip = AHD_AIC7901; 746 ahd->features = AHD_AIC7901_FE; 747 return (0); 748 } 749 750 static int 751 ahd_aic7902_setup(struct ahd_softc *ahd) 752 { 753 ahd_dev_softc_t pci; 754 u_int rev; 755 u_int devconfig1; 756 757 pci = ahd->dev_softc; 758 rev = ahd_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 759 if (rev < ID_AIC7902_PCI_REV_A3) { 760 printf("%s: Unable to attach to unsupported chip revision %d\n", 761 ahd_name(ahd), rev); 762 ahd_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/1); 763 return (ENXIO); 764 } 765 if (rev < ID_AIC7902_PCI_REV_B0) { 766 /* 767 * Pending request assertion does not work on the A if we have 768 * DMA requests outstanding on both channels. See H2A3 Razors 769 * #327 and #365. 770 */ 771 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 772 ahd_pci_write_config(pci, DEVCONFIG1, 773 devconfig1|PREQDIS, /*bytes*/1); 774 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 775 /* 776 * Enable A series workarounds. 777 */ 778 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 779 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 780 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 781 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 782 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 783 | AHD_PCIX_CHIPRST_BUG|AHD_PKTIZED_STATUS_BUG; 784 if (rev < ID_AIC7902_PCI_REV_A4) 785 ahd->bugs |= AHD_PCIX_ARBITER_BUG|AHD_PCIX_SPLIT_BUG; 786 } 787 788 ahd->channel = ahd_get_pci_function(pci) + 'A'; 789 ahd->chip = AHD_AIC7902; 790 ahd->features = AHD_AIC7902_FE; 791 return (0); 792 } 793