1 /*- 2 * Product specific probe and attach routines for: 3 * aic7901 and aic7902 SCSI controllers 4 * 5 * Copyright (c) 1994-2001 Justin T. Gibbs. 6 * Copyright (c) 2000-2002 Adaptec Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 16 * substantially similar to the "NO WARRANTY" disclaimer below 17 * ("Disclaimer") and any redistribution must be conditioned upon 18 * including a substantially similar Disclaimer requirement for further 19 * binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 38 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGES. 40 * 41 * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#88 $ 42 */ 43 44 #ifdef __linux__ 45 #include "aic79xx_osm.h" 46 #include "aic79xx_inline.h" 47 #else 48 #include <sys/cdefs.h> 49 __FBSDID("$FreeBSD$"); 50 #include <dev/aic7xxx/aic79xx_osm.h> 51 #include <dev/aic7xxx/aic79xx_inline.h> 52 #endif 53 54 static __inline uint64_t 55 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 56 { 57 uint64_t id; 58 59 id = subvendor 60 | (subdevice << 16) 61 | ((uint64_t)vendor << 32) 62 | ((uint64_t)device << 48); 63 64 return (id); 65 } 66 67 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 68 #define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull 69 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 70 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 71 #define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull 72 73 #define ID_AIC7901 0x800F9005FFFF9005ull 74 #define ID_AHA_29320A 0x8000900500609005ull 75 #define ID_AHA_29320ALP 0x8017900500449005ull 76 77 #define ID_AIC7901A 0x801E9005FFFF9005ull 78 #define ID_AHA_29320LP 0x8014900500449005ull 79 80 #define ID_AIC7902 0x801F9005FFFF9005ull 81 #define ID_AIC7902_B 0x801D9005FFFF9005ull 82 #define ID_AHA_39320 0x8010900500409005ull 83 #define ID_AHA_29320 0x8012900500429005ull 84 #define ID_AHA_29320B 0x8013900500439005ull 85 #define ID_AHA_39320_B 0x8015900500409005ull 86 #define ID_AHA_39320_B_DELL 0x8015900501681028ull 87 #define ID_AHA_39320A 0x8016900500409005ull 88 #define ID_AHA_39320D 0x8011900500419005ull 89 #define ID_AHA_39320D_B 0x801C900500419005ull 90 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull 91 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 92 #define ID_AHA_39320LPE 0x8017900500459005ull 93 #define ID_AIC7902_PCI_REV_A4 0x3 94 #define ID_AIC7902_PCI_REV_B0 0x10 95 #define SUBID_HP 0x0E11 96 97 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 98 99 #define DEVID_9005_TYPE(id) ((id) & 0xF) 100 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 101 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 102 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 103 104 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 105 106 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 107 108 #define SUBID_9005_TYPE(id) ((id) & 0xF) 109 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 110 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 111 112 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 113 114 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 115 116 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 117 #define SUBID_9005_SEEPTYPE_NONE 0x0 118 #define SUBID_9005_SEEPTYPE_4K 0x1 119 120 static ahd_device_setup_t ahd_aic7901_setup; 121 static ahd_device_setup_t ahd_aic7901A_setup; 122 static ahd_device_setup_t ahd_aic7902_setup; 123 static ahd_device_setup_t ahd_aic790X_setup; 124 125 struct ahd_pci_identity ahd_pci_ident_table [] = 126 { 127 /* aic7901 based controllers */ 128 { 129 ID_AHA_29320A, 130 ID_ALL_MASK, 131 "Adaptec 29320A Ultra320 SCSI adapter", 132 ahd_aic7901_setup 133 }, 134 { 135 ID_AHA_29320ALP, 136 ID_ALL_MASK, 137 "Adaptec 29320ALP Ultra320 SCSI adapter", 138 ahd_aic7901_setup 139 }, 140 /* aic7901A based controllers */ 141 { 142 ID_AHA_29320LP, 143 ID_ALL_MASK, 144 "Adaptec 29320LP Ultra320 SCSI adapter", 145 ahd_aic7901A_setup 146 }, 147 /* aic7902 based controllers */ 148 { 149 ID_AHA_29320, 150 ID_ALL_MASK, 151 "Adaptec 29320 Ultra320 SCSI adapter", 152 ahd_aic7902_setup 153 }, 154 { 155 ID_AHA_29320B, 156 ID_ALL_MASK, 157 "Adaptec 29320B Ultra320 SCSI adapter", 158 ahd_aic7902_setup 159 }, 160 { 161 ID_AHA_39320, 162 ID_ALL_MASK, 163 "Adaptec 39320 Ultra320 SCSI adapter", 164 ahd_aic7902_setup 165 }, 166 { 167 ID_AHA_39320_B, 168 ID_ALL_MASK, 169 "Adaptec 39320 Ultra320 SCSI adapter", 170 ahd_aic7902_setup 171 }, 172 { 173 ID_AHA_39320_B_DELL, 174 ID_ALL_MASK, 175 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter", 176 ahd_aic7902_setup 177 }, 178 { 179 ID_AHA_39320A, 180 ID_ALL_MASK, 181 "Adaptec 39320A Ultra320 SCSI adapter", 182 ahd_aic7902_setup 183 }, 184 { 185 ID_AHA_39320D, 186 ID_ALL_MASK, 187 "Adaptec 39320D Ultra320 SCSI adapter", 188 ahd_aic7902_setup 189 }, 190 { 191 ID_AHA_39320D_HP, 192 ID_ALL_MASK, 193 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 194 ahd_aic7902_setup 195 }, 196 { 197 ID_AHA_39320D_B, 198 ID_ALL_MASK, 199 "Adaptec 39320D Ultra320 SCSI adapter", 200 ahd_aic7902_setup 201 }, 202 { 203 ID_AHA_39320D_B_HP, 204 ID_ALL_MASK, 205 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 206 ahd_aic7902_setup 207 }, 208 { 209 ID_AHA_39320LPE, 210 ID_ALL_MASK, 211 "Adaptec 39320LPE Ultra320 SCSI adapter", 212 ahd_aic7902_setup 213 }, 214 /* Generic chip probes for devices we don't know 'exactly' */ 215 { 216 ID_AIC7901 & ID_9005_GENERIC_MASK, 217 ID_9005_GENERIC_MASK, 218 "Adaptec AIC7901 Ultra320 SCSI adapter", 219 ahd_aic7901_setup 220 }, 221 { 222 ID_AIC7901A & ID_DEV_VENDOR_MASK, 223 ID_DEV_VENDOR_MASK, 224 "Adaptec AIC7901A Ultra320 SCSI adapter", 225 ahd_aic7901A_setup 226 }, 227 { 228 ID_AIC7902 & ID_9005_GENERIC_MASK, 229 ID_9005_GENERIC_MASK, 230 "Adaptec AIC7902 Ultra320 SCSI adapter", 231 ahd_aic7902_setup 232 } 233 }; 234 235 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 236 237 #define DEVCONFIG 0x40 238 #define PCIXINITPAT 0x0000E000ul 239 #define PCIXINIT_PCI33_66 0x0000E000ul 240 #define PCIXINIT_PCIX50_66 0x0000C000ul 241 #define PCIXINIT_PCIX66_100 0x0000A000ul 242 #define PCIXINIT_PCIX100_133 0x00008000ul 243 #define PCI_BUS_MODES_INDEX(devconfig) \ 244 (((devconfig) & PCIXINITPAT) >> 13) 245 static const char *pci_bus_modes[] = 246 { 247 "PCI bus mode unknown", 248 "PCI bus mode unknown", 249 "PCI bus mode unknown", 250 "PCI bus mode unknown", 251 "PCI-X 101-133MHz", 252 "PCI-X 67-100MHz", 253 "PCI-X 50-66MHz", 254 "PCI 33 or 66MHz" 255 }; 256 257 #define TESTMODE 0x00000800ul 258 #define IRDY_RST 0x00000200ul 259 #define FRAME_RST 0x00000100ul 260 #define PCI64BIT 0x00000080ul 261 #define MRDCEN 0x00000040ul 262 #define ENDIANSEL 0x00000020ul 263 #define MIXQWENDIANEN 0x00000008ul 264 #define DACEN 0x00000004ul 265 #define STPWLEVEL 0x00000002ul 266 #define QWENDIANSEL 0x00000001ul 267 268 #define DEVCONFIG1 0x44 269 #define PREQDIS 0x01 270 271 #define CSIZE_LATTIME 0x0c 272 #define CACHESIZE 0x000000fful 273 #define LATTIME 0x0000ff00ul 274 275 static int ahd_check_extport(struct ahd_softc *ahd); 276 static void ahd_configure_termination(struct ahd_softc *ahd, 277 u_int adapter_control); 278 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 279 280 struct ahd_pci_identity * 281 ahd_find_pci_device(aic_dev_softc_t pci) 282 { 283 uint64_t full_id; 284 uint16_t device; 285 uint16_t vendor; 286 uint16_t subdevice; 287 uint16_t subvendor; 288 struct ahd_pci_identity *entry; 289 u_int i; 290 291 vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 292 device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 293 subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 294 subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 295 full_id = ahd_compose_id(device, 296 vendor, 297 subdevice, 298 subvendor); 299 300 /* 301 * If we are configured to attach to HostRAID 302 * controllers, mask out the IROC/HostRAID bit 303 * in the 304 */ 305 if (ahd_attach_to_HostRAID_controllers) 306 full_id &= ID_ALL_IROC_MASK; 307 308 for (i = 0; i < ahd_num_pci_devs; i++) { 309 entry = &ahd_pci_ident_table[i]; 310 if (entry->full_id == (full_id & entry->id_mask)) { 311 /* Honor exclusion entries. */ 312 if (entry->name == NULL) 313 return (NULL); 314 return (entry); 315 } 316 } 317 return (NULL); 318 } 319 320 int 321 ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry) 322 { 323 u_int command; 324 uint32_t devconfig; 325 uint16_t device; 326 uint16_t subvendor; 327 int error; 328 329 ahd->description = entry->name; 330 /* 331 * Record if this is a HostRAID board. 332 */ 333 device = aic_pci_read_config(ahd->dev_softc, 334 PCIR_DEVICE, /*bytes*/2); 335 if (DEVID_9005_HOSTRAID(device)) 336 ahd->flags |= AHD_HOSTRAID_BOARD; 337 338 /* 339 * Record if this is an HP board. 340 */ 341 subvendor = aic_pci_read_config(ahd->dev_softc, 342 PCIR_SUBVEND_0, /*bytes*/2); 343 if (subvendor == SUBID_HP) 344 ahd->flags |= AHD_HP_BOARD; 345 346 error = entry->setup(ahd); 347 if (error != 0) 348 return (error); 349 350 /* 351 * Find the PCI-X cap pointer. If we don't find it, 352 * pcix_ptr will be 0. 353 */ 354 pci_find_cap(ahd->dev_softc, PCIY_PCIX, &ahd->pcix_ptr); 355 devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 356 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 357 ahd->chip |= AHD_PCI; 358 /* Disable PCIX workarounds when running in PCI mode. */ 359 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 360 } else { 361 ahd->chip |= AHD_PCIX; 362 if (ahd->pcix_ptr == 0) 363 return (ENXIO); 364 } 365 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 366 367 aic_power_state_change(ahd, AIC_POWER_STATE_D0); 368 369 error = ahd_pci_map_registers(ahd); 370 if (error != 0) 371 return (error); 372 373 /* 374 * If we need to support high memory, enable dual 375 * address cycles. This bit must be set to enable 376 * high address bit generation even if we are on a 377 * 64bit bus (PCI64BIT set in devconfig). 378 */ 379 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 380 uint32_t devconfig; 381 382 if (bootverbose) 383 printf("%s: Enabling 39Bit Addressing\n", 384 ahd_name(ahd)); 385 devconfig = aic_pci_read_config(ahd->dev_softc, 386 DEVCONFIG, /*bytes*/4); 387 devconfig |= DACEN; 388 aic_pci_write_config(ahd->dev_softc, DEVCONFIG, 389 devconfig, /*bytes*/4); 390 } 391 392 /* Ensure busmastering is enabled */ 393 command = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 394 command |= PCIM_CMD_BUSMASTEREN; 395 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2); 396 397 error = ahd_softc_init(ahd); 398 if (error != 0) 399 return (error); 400 401 ahd->bus_intr = ahd_pci_intr; 402 403 error = ahd_reset(ahd, /*reinit*/FALSE); 404 if (error != 0) 405 return (ENXIO); 406 407 ahd->pci_cachesize = 408 aic_pci_read_config(ahd->dev_softc, CSIZE_LATTIME, 409 /*bytes*/1) & CACHESIZE; 410 ahd->pci_cachesize *= 4; 411 412 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 413 /* See if we have a SEEPROM and perform auto-term */ 414 error = ahd_check_extport(ahd); 415 if (error != 0) 416 return (error); 417 418 /* Core initialization */ 419 error = ahd_init(ahd); 420 if (error != 0) 421 return (error); 422 423 /* 424 * Allow interrupts now that we are completely setup. 425 */ 426 error = ahd_pci_map_int(ahd); 427 if (error != 0) 428 return (error); 429 430 ahd_lock(ahd); 431 /* 432 * Link this softc in with all other ahd instances. 433 */ 434 ahd_softc_insert(ahd); 435 ahd_unlock(ahd); 436 return (0); 437 } 438 439 /* 440 * Perform some simple tests that should catch situations where 441 * our registers are invalidly mapped. 442 */ 443 int 444 ahd_pci_test_register_access(struct ahd_softc *ahd) 445 { 446 uint32_t cmd; 447 u_int targpcistat; 448 u_int pci_status1; 449 int error; 450 uint8_t hcntrl; 451 452 error = EIO; 453 454 /* 455 * Enable PCI error interrupt status, but suppress NMIs 456 * generated by SERR raised due to target aborts. 457 */ 458 cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 459 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 460 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2); 461 462 /* 463 * First a simple test to see if any 464 * registers can be read. Reading 465 * HCNTRL has no side effects and has 466 * at least one bit that is guaranteed to 467 * be zero so it is a good register to 468 * use for this test. 469 */ 470 hcntrl = ahd_inb(ahd, HCNTRL); 471 if (hcntrl == 0xFF) 472 goto fail; 473 474 /* 475 * Next create a situation where write combining 476 * or read prefetching could be initiated by the 477 * CPU or host bridge. Our device does not support 478 * either, so look for data corruption and/or flaged 479 * PCI errors. First pause without causing another 480 * chip reset. 481 */ 482 hcntrl &= ~CHIPRST; 483 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 484 while (ahd_is_paused(ahd) == 0) 485 ; 486 487 /* Clear any PCI errors that occurred before our driver attached. */ 488 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 489 targpcistat = ahd_inb(ahd, TARGPCISTAT); 490 ahd_outb(ahd, TARGPCISTAT, targpcistat); 491 pci_status1 = aic_pci_read_config(ahd->dev_softc, 492 PCIR_STATUS + 1, /*bytes*/1); 493 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 494 pci_status1, /*bytes*/1); 495 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 496 ahd_outb(ahd, CLRINT, CLRPCIINT); 497 498 ahd_outb(ahd, SEQCTL0, PERRORDIS); 499 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 500 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 501 goto fail; 502 503 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 504 u_int targpcistat; 505 506 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 507 targpcistat = ahd_inb(ahd, TARGPCISTAT); 508 if ((targpcistat & STA) != 0) 509 goto fail; 510 } 511 512 error = 0; 513 514 fail: 515 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 516 517 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 518 targpcistat = ahd_inb(ahd, TARGPCISTAT); 519 520 /* Silently clear any latched errors. */ 521 ahd_outb(ahd, TARGPCISTAT, targpcistat); 522 pci_status1 = aic_pci_read_config(ahd->dev_softc, 523 PCIR_STATUS + 1, /*bytes*/1); 524 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 525 pci_status1, /*bytes*/1); 526 ahd_outb(ahd, CLRINT, CLRPCIINT); 527 } 528 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 529 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 530 return (error); 531 } 532 533 /* 534 * Check the external port logic for a serial eeprom 535 * and termination/cable detection contrls. 536 */ 537 static int 538 ahd_check_extport(struct ahd_softc *ahd) 539 { 540 struct vpd_config vpd; 541 struct seeprom_config *sc; 542 u_int adapter_control; 543 int have_seeprom; 544 int error; 545 546 sc = ahd->seep_config; 547 have_seeprom = ahd_acquire_seeprom(ahd); 548 if (have_seeprom) { 549 u_int start_addr; 550 551 /* 552 * Fetch VPD for this function and parse it. 553 */ 554 if (bootverbose) 555 printf("%s: Reading VPD from SEEPROM...", 556 ahd_name(ahd)); 557 558 /* Address is always in units of 16bit words */ 559 start_addr = ((2 * sizeof(*sc)) 560 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 561 562 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 563 start_addr, sizeof(vpd)/2, 564 /*bytestream*/TRUE); 565 if (error == 0) 566 error = ahd_parse_vpddata(ahd, &vpd); 567 if (bootverbose) 568 printf("%s: VPD parsing %s\n", 569 ahd_name(ahd), 570 error == 0 ? "successful" : "failed"); 571 572 if (bootverbose) 573 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 574 575 /* Address is always in units of 16bit words */ 576 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 577 578 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 579 start_addr, sizeof(*sc)/2, 580 /*bytestream*/FALSE); 581 582 if (error != 0) { 583 printf("Unable to read SEEPROM\n"); 584 have_seeprom = 0; 585 } else { 586 have_seeprom = ahd_verify_cksum(sc); 587 588 if (bootverbose) { 589 if (have_seeprom == 0) 590 printf ("checksum error\n"); 591 else 592 printf ("done.\n"); 593 } 594 } 595 ahd_release_seeprom(ahd); 596 } 597 598 if (!have_seeprom) { 599 u_int nvram_scb; 600 601 /* 602 * Pull scratch ram settings and treat them as 603 * if they are the contents of an seeprom if 604 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 605 * in SCB 0xFF. We manually compose the data as 16bit 606 * values to avoid endian issues. 607 */ 608 ahd_set_scbptr(ahd, 0xFF); 609 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 610 if (nvram_scb != 0xFF 611 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 612 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 613 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 614 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 615 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 616 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 617 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 618 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 619 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 620 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 621 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 622 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 623 uint16_t *sc_data; 624 int i; 625 626 ahd_set_scbptr(ahd, nvram_scb); 627 sc_data = (uint16_t *)sc; 628 for (i = 0; i < 64; i += 2) 629 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 630 have_seeprom = ahd_verify_cksum(sc); 631 if (have_seeprom) 632 ahd->flags |= AHD_SCB_CONFIG_USED; 633 } 634 } 635 636 #ifdef AHD_DEBUG 637 if (have_seeprom != 0 638 && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 639 uint16_t *sc_data; 640 int i; 641 642 printf("%s: Seeprom Contents:", ahd_name(ahd)); 643 sc_data = (uint16_t *)sc; 644 for (i = 0; i < (sizeof(*sc)); i += 2) 645 printf("\n\t0x%.4x", sc_data[i]); 646 printf("\n"); 647 } 648 #endif 649 650 if (!have_seeprom) { 651 if (bootverbose) 652 printf("%s: No SEEPROM available.\n", ahd_name(ahd)); 653 ahd->flags |= AHD_USEDEFAULTS; 654 error = ahd_default_config(ahd); 655 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 656 free(ahd->seep_config, M_DEVBUF); 657 ahd->seep_config = NULL; 658 } else { 659 error = ahd_parse_cfgdata(ahd, sc); 660 adapter_control = sc->adapter_control; 661 } 662 if (error != 0) 663 return (error); 664 665 ahd_configure_termination(ahd, adapter_control); 666 667 return (0); 668 } 669 670 static void 671 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 672 { 673 int error; 674 u_int sxfrctl1; 675 uint8_t termctl; 676 uint32_t devconfig; 677 678 devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 679 devconfig &= ~STPWLEVEL; 680 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 681 devconfig |= STPWLEVEL; 682 if (bootverbose) 683 printf("%s: STPWLEVEL is %s\n", 684 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 685 aic_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 686 687 /* Make sure current sensing is off. */ 688 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 689 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 690 } 691 692 /* 693 * Read to sense. Write to set. 694 */ 695 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 696 if ((adapter_control & CFAUTOTERM) == 0) { 697 if (bootverbose) 698 printf("%s: Manual Primary Termination\n", 699 ahd_name(ahd)); 700 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 701 if ((adapter_control & CFSTERM) != 0) 702 termctl |= FLX_TERMCTL_ENPRILOW; 703 if ((adapter_control & CFWSTERM) != 0) 704 termctl |= FLX_TERMCTL_ENPRIHIGH; 705 } else if (error != 0) { 706 printf("%s: Primary Auto-Term Sensing failed! " 707 "Using Defaults.\n", ahd_name(ahd)); 708 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 709 } 710 711 if ((adapter_control & CFSEAUTOTERM) == 0) { 712 if (bootverbose) 713 printf("%s: Manual Secondary Termination\n", 714 ahd_name(ahd)); 715 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 716 if ((adapter_control & CFSELOWTERM) != 0) 717 termctl |= FLX_TERMCTL_ENSECLOW; 718 if ((adapter_control & CFSEHIGHTERM) != 0) 719 termctl |= FLX_TERMCTL_ENSECHIGH; 720 } else if (error != 0) { 721 printf("%s: Secondary Auto-Term Sensing failed! " 722 "Using Defaults.\n", ahd_name(ahd)); 723 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 724 } 725 726 /* 727 * Now set the termination based on what we found. 728 */ 729 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 730 ahd->flags &= ~AHD_TERM_ENB_A; 731 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 732 ahd->flags |= AHD_TERM_ENB_A; 733 sxfrctl1 |= STPWEN; 734 } 735 /* Must set the latch once in order to be effective. */ 736 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 737 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 738 739 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 740 if (error != 0) { 741 printf("%s: Unable to set termination settings!\n", 742 ahd_name(ahd)); 743 } else if (bootverbose) { 744 printf("%s: Primary High byte termination %sabled\n", 745 ahd_name(ahd), 746 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 747 748 printf("%s: Primary Low byte termination %sabled\n", 749 ahd_name(ahd), 750 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 751 752 printf("%s: Secondary High byte termination %sabled\n", 753 ahd_name(ahd), 754 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 755 756 printf("%s: Secondary Low byte termination %sabled\n", 757 ahd_name(ahd), 758 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 759 } 760 return; 761 } 762 763 #define DPE 0x80 764 #define SSE 0x40 765 #define RMA 0x20 766 #define RTA 0x10 767 #define STA 0x08 768 #define DPR 0x01 769 770 static const char *split_status_source[] = 771 { 772 "DFF0", 773 "DFF1", 774 "OVLY", 775 "CMC", 776 }; 777 778 static const char *pci_status_source[] = 779 { 780 "DFF0", 781 "DFF1", 782 "SG", 783 "CMC", 784 "OVLY", 785 "NONE", 786 "MSI", 787 "TARG" 788 }; 789 790 static const char *split_status_strings[] = 791 { 792 "%s: Received split response in %s.\n", 793 "%s: Received split completion error message in %s\n", 794 "%s: Receive overrun in %s\n", 795 "%s: Count not complete in %s\n", 796 "%s: Split completion data bucket in %s\n", 797 "%s: Split completion address error in %s\n", 798 "%s: Split completion byte count error in %s\n", 799 "%s: Signaled Target-abort to early terminate a split in %s\n" 800 }; 801 802 static const char *pci_status_strings[] = 803 { 804 "%s: Data Parity Error has been reported via PERR# in %s\n", 805 "%s: Target initial wait state error in %s\n", 806 "%s: Split completion read data parity error in %s\n", 807 "%s: Split completion address attribute parity error in %s\n", 808 "%s: Received a Target Abort in %s\n", 809 "%s: Received a Master Abort in %s\n", 810 "%s: Signal System Error Detected in %s\n", 811 "%s: Address or Write Phase Parity Error Detected in %s.\n" 812 }; 813 814 void 815 ahd_pci_intr(struct ahd_softc *ahd) 816 { 817 uint8_t pci_status[8]; 818 ahd_mode_state saved_modes; 819 u_int pci_status1; 820 u_int intstat; 821 u_int i; 822 u_int reg; 823 824 intstat = ahd_inb(ahd, INTSTAT); 825 826 if ((intstat & SPLTINT) != 0) 827 ahd_pci_split_intr(ahd, intstat); 828 829 if ((intstat & PCIINT) == 0) 830 return; 831 832 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 833 saved_modes = ahd_save_modes(ahd); 834 ahd_dump_card_state(ahd); 835 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 836 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 837 838 if (i == 5) 839 continue; 840 pci_status[i] = ahd_inb(ahd, reg); 841 /* Clear latched errors. So our interrupt deasserts. */ 842 ahd_outb(ahd, reg, pci_status[i]); 843 } 844 845 for (i = 0; i < 8; i++) { 846 u_int bit; 847 848 if (i == 5) 849 continue; 850 851 for (bit = 0; bit < 8; bit++) { 852 853 if ((pci_status[i] & (0x1 << bit)) != 0) { 854 static const char *s; 855 856 s = pci_status_strings[bit]; 857 if (i == 7/*TARG*/ && bit == 3) 858 s = "%s: Signaled Target Abort\n"; 859 printf(s, ahd_name(ahd), pci_status_source[i]); 860 } 861 } 862 } 863 pci_status1 = aic_pci_read_config(ahd->dev_softc, 864 PCIR_STATUS + 1, /*bytes*/1); 865 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 866 pci_status1, /*bytes*/1); 867 ahd_restore_modes(ahd, saved_modes); 868 ahd_outb(ahd, CLRINT, CLRPCIINT); 869 ahd_unpause(ahd); 870 } 871 872 static void 873 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 874 { 875 uint8_t split_status[4]; 876 uint8_t split_status1[4]; 877 uint8_t sg_split_status[2]; 878 uint8_t sg_split_status1[2]; 879 ahd_mode_state saved_modes; 880 u_int i; 881 uint32_t pcix_status; 882 883 /* 884 * Check for splits in all modes. Modes 0 and 1 885 * additionally have SG engine splits to look at. 886 */ 887 pcix_status = aic_pci_read_config(ahd->dev_softc, 888 ahd->pcix_ptr + PCIXR_STATUS, /*bytes*/ 4); 889 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 890 ahd_name(ahd), pcix_status >> 16); 891 saved_modes = ahd_save_modes(ahd); 892 for (i = 0; i < 4; i++) { 893 ahd_set_modes(ahd, i, i); 894 895 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 896 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 897 /* Clear latched errors. So our interrupt deasserts. */ 898 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 899 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 900 if (i > 1) 901 continue; 902 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 903 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 904 /* Clear latched errors. So our interrupt deasserts. */ 905 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 906 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 907 } 908 909 for (i = 0; i < 4; i++) { 910 u_int bit; 911 912 for (bit = 0; bit < 8; bit++) { 913 914 if ((split_status[i] & (0x1 << bit)) != 0) { 915 static const char *s; 916 917 s = split_status_strings[bit]; 918 printf(s, ahd_name(ahd), 919 split_status_source[i]); 920 } 921 922 if (i > 1) 923 continue; 924 925 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 926 static const char *s; 927 928 s = split_status_strings[bit]; 929 printf(s, ahd_name(ahd), "SG"); 930 } 931 } 932 } 933 /* 934 * Clear PCI-X status bits. 935 */ 936 aic_pci_write_config(ahd->dev_softc, ahd->pcix_ptr + PCIXR_STATUS, 937 pcix_status, /*bytes*/4); 938 ahd_outb(ahd, CLRINT, CLRSPLTINT); 939 ahd_restore_modes(ahd, saved_modes); 940 } 941 942 static int 943 ahd_aic7901_setup(struct ahd_softc *ahd) 944 { 945 946 ahd->chip = AHD_AIC7901; 947 ahd->features = AHD_AIC7901_FE; 948 return (ahd_aic790X_setup(ahd)); 949 } 950 951 static int 952 ahd_aic7901A_setup(struct ahd_softc *ahd) 953 { 954 955 ahd->chip = AHD_AIC7901A; 956 ahd->features = AHD_AIC7901A_FE; 957 return (ahd_aic790X_setup(ahd)); 958 } 959 960 static int 961 ahd_aic7902_setup(struct ahd_softc *ahd) 962 { 963 ahd->chip = AHD_AIC7902; 964 ahd->features = AHD_AIC7902_FE; 965 return (ahd_aic790X_setup(ahd)); 966 } 967 968 static int 969 ahd_aic790X_setup(struct ahd_softc *ahd) 970 { 971 aic_dev_softc_t pci; 972 u_int rev; 973 974 pci = ahd->dev_softc; 975 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 976 if (rev < ID_AIC7902_PCI_REV_A4) { 977 printf("%s: Unable to attach to unsupported chip revision %d\n", 978 ahd_name(ahd), rev); 979 aic_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2); 980 return (ENXIO); 981 } 982 ahd->channel = aic_get_pci_function(pci) + 'A'; 983 if (rev < ID_AIC7902_PCI_REV_B0) { 984 /* 985 * Enable A series workarounds. 986 */ 987 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 988 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 989 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 990 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 991 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 992 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 993 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 994 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 995 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 996 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 997 | AHD_FAINT_LED_BUG; 998 999 /* 1000 * IO Cell paramter setup. 1001 */ 1002 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1003 1004 if ((ahd->flags & AHD_HP_BOARD) == 0) 1005 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 1006 } else { 1007 u_int devconfig1; 1008 1009 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1010 | AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY; 1011 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; 1012 1013 /* 1014 * Some issues have been resolved in the 7901B. 1015 */ 1016 if ((ahd->features & AHD_MULTI_FUNC) != 0) 1017 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG 1018 | AHD_BUSFREEREV_BUG; 1019 1020 /* 1021 * IO Cell paramter setup. 1022 */ 1023 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1024 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1025 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1026 1027 /* 1028 * Set the PREQDIS bit for H2B which disables some workaround 1029 * that doesn't work on regular PCI busses. 1030 * XXX - Find out exactly what this does from the hardware 1031 * folks! 1032 */ 1033 devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 1034 aic_pci_write_config(pci, DEVCONFIG1, 1035 devconfig1|PREQDIS, /*bytes*/1); 1036 devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 1037 } 1038 1039 return (0); 1040 } 1041