1 /* 2 * Product specific probe and attach routines for: 3 * aic7901 and aic7902 SCSI controllers 4 * 5 * Copyright (c) 1994-2001 Justin T. Gibbs. 6 * Copyright (c) 2000-2002 Adaptec Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 16 * substantially similar to the "NO WARRANTY" disclaimer below 17 * ("Disclaimer") and any redistribution must be conditioned upon 18 * including a substantially similar Disclaimer requirement for further 19 * binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 38 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGES. 40 * 41 * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#67 $ 42 * 43 * $FreeBSD$ 44 */ 45 46 #ifdef __linux__ 47 #include "aic79xx_osm.h" 48 #include "aic79xx_inline.h" 49 #else 50 #include <dev/aic7xxx/aic79xx_osm.h> 51 #include <dev/aic7xxx/aic79xx_inline.h> 52 #endif 53 54 static __inline uint64_t 55 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 56 { 57 uint64_t id; 58 59 id = subvendor 60 | (subdevice << 16) 61 | ((uint64_t)vendor << 32) 62 | ((uint64_t)device << 48); 63 64 return (id); 65 } 66 67 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 68 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 69 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 70 71 #define ID_AIC7901 0x800F9005FFFF9005ull 72 #define ID_AIC7901A 0x801E9005FFFF9005ull 73 #define ID_AIC7901A_IROC 0x809E9005FFFF9005ull 74 #define ID_AHA_29320A 0x8000900500609005ull 75 #define ID_AHA_29320LP 0x8014900500449005ull 76 #define ID_AHA_29320LP_IROC 0x8094900500449005ull 77 78 #define ID_AIC7902 0x801F9005FFFF9005ull 79 #define ID_AIC7902_IROC 0x809F9005FFFF9005ull 80 #define ID_AIC7902_B 0x801D9005FFFF9005ull 81 #define ID_AIC7902_B_IROC 0x809D9005FFFF9005ull 82 #define ID_AHA_39320 0x8010900500409005ull 83 #define ID_AHA_39320A 0x8016900500409005ull 84 #define ID_AHA_39320D 0x8011900500419005ull 85 #define ID_AHA_39320D_B 0x801C900500419005ull 86 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull 87 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 88 #define ID_AHA_29320 0x8012900500429005ull 89 #define ID_AHA_29320B 0x8013900500439005ull 90 #define ID_AIC7902_PCI_REV_A4 0x3 91 #define ID_AIC7902_PCI_REV_B0 0x10 92 #define SUBID_HP 0x0E11 93 94 #define DEVID_9005_TYPE(id) ((id) & 0xF) 95 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 96 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 97 #define DEVID_9005_TYPE_IROC 0x8 /* Raid(0,1,10) Card */ 98 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 99 100 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 101 102 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 103 104 #define SUBID_9005_TYPE(id) ((id) & 0xF) 105 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 106 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 107 108 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 109 110 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 111 112 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 113 #define SUBID_9005_SEEPTYPE_NONE 0x0 114 #define SUBID_9005_SEEPTYPE_4K 0x1 115 116 static ahd_device_setup_t ahd_aic7901A_setup; 117 static ahd_device_setup_t ahd_aic7902_setup; 118 119 struct ahd_pci_identity ahd_pci_ident_table [] = 120 { 121 /* aic7901A based controllers */ 122 { 123 ID_AHA_29320LP, 124 ID_ALL_MASK, 125 "Adaptec 29320LP Ultra320 SCSI adapter", 126 ahd_aic7901A_setup 127 }, 128 { 129 ID_AHA_29320A, 130 ID_ALL_MASK, 131 "Adaptec 29320A Ultra320 SCSI adapter", 132 ahd_aic7901A_setup 133 }, 134 /* aic7902 based controllers */ 135 { 136 ID_AHA_39320, 137 ID_ALL_MASK, 138 "Adaptec 39320 Ultra320 SCSI adapter", 139 ahd_aic7902_setup 140 }, 141 { 142 ID_AHA_39320A, 143 ID_ALL_MASK, 144 "Adaptec 39320A Ultra320 SCSI adapter", 145 ahd_aic7902_setup 146 }, 147 { 148 ID_AHA_39320D, 149 ID_ALL_MASK, 150 "Adaptec 39320D Ultra320 SCSI adapter", 151 ahd_aic7902_setup 152 }, 153 { 154 ID_AHA_39320D_HP, 155 ID_ALL_MASK, 156 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 157 ahd_aic7902_setup 158 }, 159 { 160 ID_AHA_39320D_B, 161 ID_ALL_MASK, 162 "Adaptec 39320D Ultra320 SCSI adapter", 163 ahd_aic7902_setup 164 }, 165 { 166 ID_AHA_39320D_B_HP, 167 ID_ALL_MASK, 168 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 169 ahd_aic7902_setup 170 }, 171 { 172 ID_AHA_29320, 173 ID_ALL_MASK, 174 "Adaptec 29320 Ultra320 SCSI adapter", 175 ahd_aic7902_setup 176 }, 177 { 178 ID_AHA_29320B, 179 ID_ALL_MASK, 180 "Adaptec 29320B Ultra320 SCSI adapter", 181 ahd_aic7902_setup 182 }, 183 /* Generic chip probes for devices we don't know 'exactly' */ 184 { 185 ID_AIC7901A & ID_DEV_VENDOR_MASK, 186 ID_DEV_VENDOR_MASK, 187 "Adaptec AIC7901A Ultra320 SCSI adapter", 188 ahd_aic7901A_setup 189 }, 190 { 191 ID_AIC7902 & ID_9005_GENERIC_MASK, 192 ID_9005_GENERIC_MASK, 193 "Adaptec AIC7902 Ultra320 SCSI adapter", 194 ahd_aic7902_setup 195 } 196 }; 197 198 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 199 200 #define DEVCONFIG 0x40 201 #define PCIXINITPAT 0x0000E000ul 202 #define PCIXINIT_PCI33_66 0x0000E000ul 203 #define PCIXINIT_PCIX50_66 0x0000C000ul 204 #define PCIXINIT_PCIX66_100 0x0000A000ul 205 #define PCIXINIT_PCIX100_133 0x00008000ul 206 #define PCI_BUS_MODES_INDEX(devconfig) \ 207 (((devconfig) & PCIXINITPAT) >> 13) 208 static const char *pci_bus_modes[] = 209 { 210 "PCI bus mode unknown", 211 "PCI bus mode unknown", 212 "PCI bus mode unknown", 213 "PCI bus mode unknown", 214 "PCI-X 101-133Mhz", 215 "PCI-X 67-100Mhz", 216 "PCI-X 50-66Mhz", 217 "PCI 33 or 66Mhz" 218 }; 219 220 #define TESTMODE 0x00000800ul 221 #define IRDY_RST 0x00000200ul 222 #define FRAME_RST 0x00000100ul 223 #define PCI64BIT 0x00000080ul 224 #define MRDCEN 0x00000040ul 225 #define ENDIANSEL 0x00000020ul 226 #define MIXQWENDIANEN 0x00000008ul 227 #define DACEN 0x00000004ul 228 #define STPWLEVEL 0x00000002ul 229 #define QWENDIANSEL 0x00000001ul 230 231 #define DEVCONFIG1 0x44 232 #define PREQDIS 0x01 233 234 #define CSIZE_LATTIME 0x0c 235 #define CACHESIZE 0x000000fful 236 #define LATTIME 0x0000ff00ul 237 238 static int ahd_check_extport(struct ahd_softc *ahd); 239 static void ahd_configure_termination(struct ahd_softc *ahd, 240 u_int adapter_control); 241 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 242 243 struct ahd_pci_identity * 244 ahd_find_pci_device(ahd_dev_softc_t pci) 245 { 246 uint64_t full_id; 247 uint16_t device; 248 uint16_t vendor; 249 uint16_t subdevice; 250 uint16_t subvendor; 251 struct ahd_pci_identity *entry; 252 u_int i; 253 254 vendor = ahd_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 255 device = ahd_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 256 subvendor = ahd_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 257 subdevice = ahd_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 258 full_id = ahd_compose_id(device, 259 vendor, 260 subdevice, 261 subvendor); 262 263 for (i = 0; i < ahd_num_pci_devs; i++) { 264 entry = &ahd_pci_ident_table[i]; 265 if (entry->full_id == (full_id & entry->id_mask)) { 266 /* Honor exclusion entries. */ 267 if (entry->name == NULL) 268 return (NULL); 269 return (entry); 270 } 271 } 272 return (NULL); 273 } 274 275 int 276 ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry) 277 { 278 struct scb_data *shared_scb_data; 279 u_long l; 280 u_int command; 281 uint32_t devconfig; 282 uint16_t subvendor; 283 int error; 284 285 shared_scb_data = NULL; 286 ahd->description = entry->name; 287 /* 288 * Record if this is an HP board. 289 */ 290 subvendor = ahd_pci_read_config(ahd->dev_softc, 291 PCIR_SUBVEND_0, /*bytes*/2); 292 if (subvendor == SUBID_HP) 293 ahd->flags |= AHD_HP_BOARD; 294 295 error = entry->setup(ahd); 296 if (error != 0) 297 return (error); 298 299 devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 300 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 301 ahd->chip |= AHD_PCI; 302 /* Disable PCIX workarounds when running in PCI mode. */ 303 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 304 } else { 305 ahd->chip |= AHD_PCIX; 306 } 307 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 308 309 ahd_power_state_change(ahd, AHD_POWER_STATE_D0); 310 311 error = ahd_pci_map_registers(ahd); 312 if (error != 0) 313 return (error); 314 315 /* 316 * If we need to support high memory, enable dual 317 * address cycles. This bit must be set to enable 318 * high address bit generation even if we are on a 319 * 64bit bus (PCI64BIT set in devconfig). 320 */ 321 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 322 uint32_t devconfig; 323 324 if (bootverbose) 325 printf("%s: Enabling 39Bit Addressing\n", 326 ahd_name(ahd)); 327 devconfig = ahd_pci_read_config(ahd->dev_softc, 328 DEVCONFIG, /*bytes*/4); 329 devconfig |= DACEN; 330 ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, 331 devconfig, /*bytes*/4); 332 } 333 334 /* Ensure busmastering is enabled */ 335 command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/1); 336 command |= PCIM_CMD_BUSMASTEREN; 337 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/1); 338 339 error = ahd_softc_init(ahd); 340 if (error != 0) 341 return (error); 342 343 ahd->bus_intr = ahd_pci_intr; 344 345 error = ahd_reset(ahd); 346 if (error != 0) 347 return (ENXIO); 348 349 ahd->pci_cachesize = 350 ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME, 351 /*bytes*/1) & CACHESIZE; 352 ahd->pci_cachesize *= 4; 353 354 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 355 /* See if we have a SEEPROM and perform auto-term */ 356 error = ahd_check_extport(ahd); 357 if (error != 0) 358 return (error); 359 360 /* Core initialization */ 361 error = ahd_init(ahd); 362 if (error != 0) 363 return (error); 364 365 /* 366 * Allow interrupts now that we are completely setup. 367 */ 368 error = ahd_pci_map_int(ahd); 369 if (error != 0) 370 return (error); 371 372 ahd_list_lock(&l); 373 /* 374 * Link this softc in with all other ahd instances. 375 */ 376 ahd_softc_insert(ahd); 377 ahd_list_unlock(&l); 378 return (0); 379 } 380 381 /* 382 * Perform some simple tests that should catch situations where 383 * our registers are invalidly mapped. 384 */ 385 int 386 ahd_pci_test_register_access(struct ahd_softc *ahd) 387 { 388 uint32_t cmd; 389 int error; 390 uint8_t hcntrl; 391 392 error = EIO; 393 394 /* 395 * Enable PCI error interrupt status, but suppress NMIs 396 * generated by SERR raised due to target aborts. 397 */ 398 cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 399 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 400 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2); 401 402 /* 403 * First a simple test to see if any 404 * registers can be read. Reading 405 * HCNTRL has no side effects and has 406 * at least one bit that is guaranteed to 407 * be zero so it is a good register to 408 * use for this test. 409 */ 410 hcntrl = ahd_inb(ahd, HCNTRL); 411 if (hcntrl == 0xFF) 412 goto fail; 413 414 /* 415 * Next create a situation where write combining 416 * or read prefetching could be initiated by the 417 * CPU or host bridge. Our device does not support 418 * either, so look for data corruption and/or flaged 419 * PCI errors. 420 */ 421 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 422 while (ahd_is_paused(ahd) == 0) 423 ; 424 ahd_outb(ahd, SEQCTL0, PERRORDIS); 425 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 426 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 427 goto fail; 428 429 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 430 u_int targpcistat; 431 432 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 433 targpcistat = ahd_inb(ahd, TARGPCISTAT); 434 if ((targpcistat & STA) != 0) 435 goto fail; 436 } 437 438 error = 0; 439 440 fail: 441 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 442 u_int targpcistat; 443 u_int pci_status1; 444 445 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 446 targpcistat = ahd_inb(ahd, TARGPCISTAT); 447 448 /* Silently clear any latched errors. */ 449 ahd_outb(ahd, TARGPCISTAT, targpcistat); 450 pci_status1 = ahd_pci_read_config(ahd->dev_softc, 451 PCIR_STATUS + 1, /*bytes*/1); 452 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 453 pci_status1, /*bytes*/1); 454 ahd_outb(ahd, CLRINT, CLRPCIINT); 455 } 456 457 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 458 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 459 return (error); 460 } 461 462 /* 463 * Check the external port logic for a serial eeprom 464 * and termination/cable detection contrls. 465 */ 466 static int 467 ahd_check_extport(struct ahd_softc *ahd) 468 { 469 struct seeprom_config *sc; 470 u_int adapter_control; 471 int have_seeprom; 472 int error; 473 474 sc = ahd->seep_config; 475 have_seeprom = ahd_acquire_seeprom(ahd); 476 if (have_seeprom) { 477 u_int start_addr; 478 479 if (bootverbose) 480 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 481 482 /* Address is always in units of 16bit words */ 483 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 484 485 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 486 start_addr, sizeof(*sc)/2); 487 488 if (error != 0) { 489 printf("Unable to read SEEPROM\n"); 490 have_seeprom = 0; 491 } else { 492 have_seeprom = ahd_verify_cksum(sc); 493 494 if (bootverbose) { 495 if (have_seeprom == 0) 496 printf ("checksum error\n"); 497 else 498 printf ("done.\n"); 499 } 500 } 501 ahd_release_seeprom(ahd); 502 } 503 504 if (!have_seeprom) { 505 u_int nvram_scb; 506 507 /* 508 * Pull scratch ram settings and treat them as 509 * if they are the contents of an seeprom if 510 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 511 * in SCB 0xFF. We manually compose the data as 16bit 512 * values to avoid endian issues. 513 */ 514 ahd_set_scbptr(ahd, 0xFF); 515 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 516 if (nvram_scb != 0xFF 517 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 518 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 519 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 520 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 521 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 522 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 523 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 524 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 525 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 526 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 527 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 528 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 529 uint16_t *sc_data; 530 int i; 531 532 ahd_set_scbptr(ahd, nvram_scb); 533 sc_data = (uint16_t *)sc; 534 for (i = 0; i < 64; i += 2) 535 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 536 have_seeprom = ahd_verify_cksum(sc); 537 if (have_seeprom) 538 ahd->flags |= AHD_SCB_CONFIG_USED; 539 } 540 } 541 542 #if AHD_DEBUG 543 if (have_seeprom != 0 544 && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 545 uint8_t *sc_data; 546 int i; 547 548 printf("%s: Seeprom Contents:", ahd_name(ahd)); 549 sc_data = (uint8_t *)sc; 550 for (i = 0; i < (sizeof(*sc)); i += 2) 551 printf("\n\t0x%.4x", 552 sc_data[i] | (sc_data[i+1] << 8)); 553 printf("\n"); 554 } 555 #endif 556 557 if (!have_seeprom) { 558 if (bootverbose) 559 printf("%s: No SEEPROM available.\n", ahd_name(ahd)); 560 ahd->flags |= AHD_USEDEFAULTS; 561 error = ahd_default_config(ahd); 562 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 563 free(ahd->seep_config, M_DEVBUF); 564 ahd->seep_config = NULL; 565 } else { 566 error = ahd_parse_cfgdata(ahd, sc); 567 adapter_control = sc->adapter_control; 568 } 569 if (error != 0) 570 return (error); 571 572 ahd_configure_termination(ahd, adapter_control); 573 574 return (0); 575 } 576 577 static void 578 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 579 { 580 int error; 581 u_int sxfrctl1; 582 uint8_t termctl; 583 uint32_t devconfig; 584 585 devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 586 devconfig &= ~STPWLEVEL; 587 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 588 devconfig |= STPWLEVEL; 589 if (bootverbose) 590 printf("%s: STPWLEVEL is %s\n", 591 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 592 ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 593 594 /* Make sure current sensing is off. */ 595 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 596 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 597 } 598 599 /* 600 * Read to sense. Write to set. 601 */ 602 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 603 if ((adapter_control & CFAUTOTERM) == 0) { 604 if (bootverbose) 605 printf("%s: Manual Primary Termination\n", 606 ahd_name(ahd)); 607 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 608 if ((adapter_control & CFSTERM) != 0) 609 termctl |= FLX_TERMCTL_ENPRILOW; 610 if ((adapter_control & CFWSTERM) != 0) 611 termctl |= FLX_TERMCTL_ENPRIHIGH; 612 } else if (error != 0) { 613 printf("%s: Primary Auto-Term Sensing failed! " 614 "Using Defaults.\n", ahd_name(ahd)); 615 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 616 } 617 618 if ((adapter_control & CFSEAUTOTERM) == 0) { 619 if (bootverbose) 620 printf("%s: Manual Secondary Termination\n", 621 ahd_name(ahd)); 622 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 623 if ((adapter_control & CFSELOWTERM) != 0) 624 termctl |= FLX_TERMCTL_ENSECLOW; 625 if ((adapter_control & CFSEHIGHTERM) != 0) 626 termctl |= FLX_TERMCTL_ENSECHIGH; 627 } else if (error != 0) { 628 printf("%s: Secondary Auto-Term Sensing failed! " 629 "Using Defaults.\n", ahd_name(ahd)); 630 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 631 } 632 633 /* 634 * Now set the termination based on what we found. 635 */ 636 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 637 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 638 ahd->flags |= AHD_TERM_ENB_A; 639 sxfrctl1 |= STPWEN; 640 } 641 /* Must set the latch once in order to be effective. */ 642 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 643 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 644 645 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 646 if (error != 0) { 647 printf("%s: Unable to set termination settings!\n", 648 ahd_name(ahd)); 649 } else if (bootverbose) { 650 printf("%s: Primary High byte termination %sabled\n", 651 ahd_name(ahd), 652 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 653 654 printf("%s: Primary Low byte termination %sabled\n", 655 ahd_name(ahd), 656 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 657 658 printf("%s: Secondary High byte termination %sabled\n", 659 ahd_name(ahd), 660 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 661 662 printf("%s: Secondary Low byte termination %sabled\n", 663 ahd_name(ahd), 664 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 665 } 666 return; 667 } 668 669 #define DPE 0x80 670 #define SSE 0x40 671 #define RMA 0x20 672 #define RTA 0x10 673 #define STA 0x08 674 #define DPR 0x01 675 676 static const char *split_status_source[] = 677 { 678 "DFF0", 679 "DFF1", 680 "OVLY", 681 "CMC", 682 }; 683 684 static const char *pci_status_source[] = 685 { 686 "DFF0", 687 "DFF1", 688 "SG", 689 "CMC", 690 "OVLY", 691 "NONE", 692 "MSI", 693 "TARG" 694 }; 695 696 static const char *split_status_strings[] = 697 { 698 "%s: Received split response in %s.\n", 699 "%s: Received split completion error message in %s\n", 700 "%s: Receive overrun in %s\n", 701 "%s: Count not complete in %s\n", 702 "%s: Split completion data bucket in %s\n", 703 "%s: Split completion address error in %s\n", 704 "%s: Split completion byte count error in %s\n", 705 "%s: Signaled Target-abort to early terminate a split in %s\n" 706 }; 707 708 static const char *pci_status_strings[] = 709 { 710 "%s: Data Parity Error has been reported via PERR# in %s\n", 711 "%s: Target initial wait state error in %s\n", 712 "%s: Split completion read data parity error in %s\n", 713 "%s: Split completion address attribute parity error in %s\n", 714 "%s: Received a Target Abort in %s\n", 715 "%s: Received a Master Abort in %s\n", 716 "%s: Signal System Error Detected in %s\n", 717 "%s: Address or Write Phase Parity Error Detected in %s.\n" 718 }; 719 720 void 721 ahd_pci_intr(struct ahd_softc *ahd) 722 { 723 uint8_t pci_status[8]; 724 ahd_mode_state saved_modes; 725 u_int pci_status1; 726 u_int intstat; 727 u_int i; 728 u_int reg; 729 730 intstat = ahd_inb(ahd, INTSTAT); 731 732 if ((intstat & SPLTINT) != 0) 733 ahd_pci_split_intr(ahd, intstat); 734 735 if ((intstat & PCIINT) == 0) 736 return; 737 738 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 739 saved_modes = ahd_save_modes(ahd); 740 ahd_dump_card_state(ahd); 741 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 742 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 743 744 if (i == 5) 745 continue; 746 pci_status[i] = ahd_inb(ahd, reg); 747 /* Clear latched errors. So our interrupt deasserts. */ 748 ahd_outb(ahd, reg, pci_status[i]); 749 } 750 751 for (i = 0; i < 8; i++) { 752 u_int bit; 753 754 if (i == 5) 755 continue; 756 757 for (bit = 0; bit < 8; bit++) { 758 759 if ((pci_status[i] & (0x1 << bit)) != 0) { 760 static const char *s; 761 762 s = pci_status_strings[bit]; 763 if (i == 7/*TARG*/ && bit == 3) 764 s = "%s: Signaled Target Abort\n"; 765 printf(s, ahd_name(ahd), pci_status_source[i]); 766 } 767 } 768 } 769 pci_status1 = ahd_pci_read_config(ahd->dev_softc, 770 PCIR_STATUS + 1, /*bytes*/1); 771 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 772 pci_status1, /*bytes*/1); 773 ahd_restore_modes(ahd, saved_modes); 774 ahd_outb(ahd, CLRINT, CLRPCIINT); 775 ahd_unpause(ahd); 776 } 777 778 static void 779 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 780 { 781 uint8_t split_status[4]; 782 uint8_t split_status1[4]; 783 uint8_t sg_split_status[2]; 784 uint8_t sg_split_status1[2]; 785 ahd_mode_state saved_modes; 786 u_int i; 787 uint16_t pcix_status; 788 789 /* 790 * Check for splits in all modes. Modes 0 and 1 791 * additionally have SG engine splits to look at. 792 */ 793 pcix_status = ahd_pci_read_config(ahd->dev_softc, PCIXR_STATUS, 794 /*bytes*/2); 795 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 796 ahd_name(ahd), pcix_status); 797 saved_modes = ahd_save_modes(ahd); 798 for (i = 0; i < 4; i++) { 799 ahd_set_modes(ahd, i, i); 800 801 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 802 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 803 /* Clear latched errors. So our interrupt deasserts. */ 804 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 805 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 806 if (i != 0) 807 continue; 808 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 809 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 810 /* Clear latched errors. So our interrupt deasserts. */ 811 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 812 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 813 } 814 815 for (i = 0; i < 4; i++) { 816 u_int bit; 817 818 for (bit = 0; bit < 8; bit++) { 819 820 if ((split_status[i] & (0x1 << bit)) != 0) { 821 static const char *s; 822 823 s = split_status_strings[bit]; 824 printf(s, ahd_name(ahd), 825 split_status_source[i]); 826 } 827 828 if (i != 0) 829 continue; 830 831 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 832 static const char *s; 833 834 s = split_status_strings[bit]; 835 printf(s, ahd_name(ahd), "SG"); 836 } 837 } 838 } 839 /* 840 * Clear PCI-X status bits. 841 */ 842 ahd_pci_write_config(ahd->dev_softc, PCIXR_STATUS, 843 pcix_status, /*bytes*/2); 844 ahd_outb(ahd, CLRINT, CLRSPLTINT); 845 ahd_restore_modes(ahd, saved_modes); 846 } 847 848 static int 849 ahd_aic7901A_setup(struct ahd_softc *ahd) 850 { 851 int error; 852 853 error = ahd_aic7902_setup(ahd); 854 if (error != 0) 855 return (error); 856 ahd->chip = AHD_AIC7901A; 857 return (0); 858 } 859 860 static int 861 ahd_aic7902_setup(struct ahd_softc *ahd) 862 { 863 ahd_dev_softc_t pci; 864 u_int rev; 865 866 pci = ahd->dev_softc; 867 rev = ahd_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 868 if (rev < ID_AIC7902_PCI_REV_A4) { 869 printf("%s: Unable to attach to unsupported chip revision %d\n", 870 ahd_name(ahd), rev); 871 ahd_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/1); 872 return (ENXIO); 873 } 874 ahd->channel = ahd_get_pci_function(pci) + 'A'; 875 ahd->chip = AHD_AIC7902; 876 ahd->features = AHD_AIC7902_FE; 877 if (rev < ID_AIC7902_PCI_REV_B0) { 878 /* 879 * Enable A series workarounds. 880 */ 881 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 882 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 883 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 884 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 885 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 886 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 887 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 888 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 889 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 890 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG; 891 892 /* 893 * IO Cell paramter setup. 894 */ 895 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 896 897 if ((ahd->flags & AHD_HP_BOARD) == 0) 898 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 899 } else { 900 u_int devconfig1; 901 902 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 903 | AHD_NEW_DFCNTRL_OPTS; 904 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_ABORT_LQI_BUG 905 | AHD_INTCOLLISION_BUG|AHD_EARLY_REQ_BUG; 906 907 /* 908 * IO Cell paramter setup. 909 */ 910 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 911 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 912 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 913 914 /* 915 * Set the PREQDIS bit for H2B which disables some workaround 916 * that doesn't work on regular PCI busses. 917 * XXX - Find out exactly what this does from the hardware 918 * folks! 919 */ 920 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 921 ahd_pci_write_config(pci, DEVCONFIG1, 922 devconfig1|PREQDIS, /*bytes*/1); 923 devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 924 } 925 926 return (0); 927 } 928