1 /*- 2 * Product specific probe and attach routines for: 3 * aic7901 and aic7902 SCSI controllers 4 * 5 * Copyright (c) 1994-2001 Justin T. Gibbs. 6 * Copyright (c) 2000-2002 Adaptec Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 16 * substantially similar to the "NO WARRANTY" disclaimer below 17 * ("Disclaimer") and any redistribution must be conditioned upon 18 * including a substantially similar Disclaimer requirement for further 19 * binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 38 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGES. 40 * 41 * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#88 $ 42 */ 43 44 #ifdef __linux__ 45 #include "aic79xx_osm.h" 46 #include "aic79xx_inline.h" 47 #else 48 #include <sys/cdefs.h> 49 __FBSDID("$FreeBSD$"); 50 #include <dev/aic7xxx/aic79xx_osm.h> 51 #include <dev/aic7xxx/aic79xx_inline.h> 52 #endif 53 54 static __inline uint64_t 55 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 56 { 57 uint64_t id; 58 59 id = subvendor 60 | (subdevice << 16) 61 | ((uint64_t)vendor << 32) 62 | ((uint64_t)device << 48); 63 64 return (id); 65 } 66 67 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 68 #define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull 69 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 70 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 71 #define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull 72 73 #define ID_AIC7901 0x800F9005FFFF9005ull 74 #define ID_AHA_29320A 0x8000900500609005ull 75 #define ID_AHA_29320ALP 0x8017900500449005ull 76 77 #define ID_AIC7901A 0x801E9005FFFF9005ull 78 #define ID_AHA_29320LP 0x8014900500449005ull 79 80 #define ID_AIC7902 0x801F9005FFFF9005ull 81 #define ID_AIC7902_B 0x801D9005FFFF9005ull 82 #define ID_AHA_39320 0x8010900500409005ull 83 #define ID_AHA_29320 0x8012900500429005ull 84 #define ID_AHA_29320B 0x8013900500439005ull 85 #define ID_AHA_39320_B 0x8015900500409005ull 86 #define ID_AHA_39320_B_DELL 0x8015900501681028ull 87 #define ID_AHA_39320A 0x8016900500409005ull 88 #define ID_AHA_39320D 0x8011900500419005ull 89 #define ID_AHA_39320D_B 0x801C900500419005ull 90 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull 91 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 92 #define ID_AIC7902_PCI_REV_A4 0x3 93 #define ID_AIC7902_PCI_REV_B0 0x10 94 #define SUBID_HP 0x0E11 95 96 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 97 98 #define DEVID_9005_TYPE(id) ((id) & 0xF) 99 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 100 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 101 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 102 103 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 104 105 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 106 107 #define SUBID_9005_TYPE(id) ((id) & 0xF) 108 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 109 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 110 111 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 112 113 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 114 115 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 116 #define SUBID_9005_SEEPTYPE_NONE 0x0 117 #define SUBID_9005_SEEPTYPE_4K 0x1 118 119 static ahd_device_setup_t ahd_aic7901_setup; 120 static ahd_device_setup_t ahd_aic7901A_setup; 121 static ahd_device_setup_t ahd_aic7902_setup; 122 static ahd_device_setup_t ahd_aic790X_setup; 123 124 struct ahd_pci_identity ahd_pci_ident_table [] = 125 { 126 /* aic7901 based controllers */ 127 { 128 ID_AHA_29320A, 129 ID_ALL_MASK, 130 "Adaptec 29320A Ultra320 SCSI adapter", 131 ahd_aic7901_setup 132 }, 133 { 134 ID_AHA_29320ALP, 135 ID_ALL_MASK, 136 "Adaptec 29320ALP Ultra320 SCSI adapter", 137 ahd_aic7901_setup 138 }, 139 /* aic7901A based controllers */ 140 { 141 ID_AHA_29320LP, 142 ID_ALL_MASK, 143 "Adaptec 29320LP Ultra320 SCSI adapter", 144 ahd_aic7901A_setup 145 }, 146 /* aic7902 based controllers */ 147 { 148 ID_AHA_29320, 149 ID_ALL_MASK, 150 "Adaptec 29320 Ultra320 SCSI adapter", 151 ahd_aic7902_setup 152 }, 153 { 154 ID_AHA_29320B, 155 ID_ALL_MASK, 156 "Adaptec 29320B Ultra320 SCSI adapter", 157 ahd_aic7902_setup 158 }, 159 { 160 ID_AHA_39320, 161 ID_ALL_MASK, 162 "Adaptec 39320 Ultra320 SCSI adapter", 163 ahd_aic7902_setup 164 }, 165 { 166 ID_AHA_39320_B, 167 ID_ALL_MASK, 168 "Adaptec 39320 Ultra320 SCSI adapter", 169 ahd_aic7902_setup 170 }, 171 { 172 ID_AHA_39320_B_DELL, 173 ID_ALL_MASK, 174 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter", 175 ahd_aic7902_setup 176 }, 177 { 178 ID_AHA_39320A, 179 ID_ALL_MASK, 180 "Adaptec 39320A Ultra320 SCSI adapter", 181 ahd_aic7902_setup 182 }, 183 { 184 ID_AHA_39320D, 185 ID_ALL_MASK, 186 "Adaptec 39320D Ultra320 SCSI adapter", 187 ahd_aic7902_setup 188 }, 189 { 190 ID_AHA_39320D_HP, 191 ID_ALL_MASK, 192 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 193 ahd_aic7902_setup 194 }, 195 { 196 ID_AHA_39320D_B, 197 ID_ALL_MASK, 198 "Adaptec 39320D Ultra320 SCSI adapter", 199 ahd_aic7902_setup 200 }, 201 { 202 ID_AHA_39320D_B_HP, 203 ID_ALL_MASK, 204 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 205 ahd_aic7902_setup 206 }, 207 /* Generic chip probes for devices we don't know 'exactly' */ 208 { 209 ID_AIC7901 & ID_9005_GENERIC_MASK, 210 ID_9005_GENERIC_MASK, 211 "Adaptec AIC7901 Ultra320 SCSI adapter", 212 ahd_aic7901_setup 213 }, 214 { 215 ID_AIC7901A & ID_DEV_VENDOR_MASK, 216 ID_DEV_VENDOR_MASK, 217 "Adaptec AIC7901A Ultra320 SCSI adapter", 218 ahd_aic7901A_setup 219 }, 220 { 221 ID_AIC7902 & ID_9005_GENERIC_MASK, 222 ID_9005_GENERIC_MASK, 223 "Adaptec AIC7902 Ultra320 SCSI adapter", 224 ahd_aic7902_setup 225 } 226 }; 227 228 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 229 230 #define DEVCONFIG 0x40 231 #define PCIXINITPAT 0x0000E000ul 232 #define PCIXINIT_PCI33_66 0x0000E000ul 233 #define PCIXINIT_PCIX50_66 0x0000C000ul 234 #define PCIXINIT_PCIX66_100 0x0000A000ul 235 #define PCIXINIT_PCIX100_133 0x00008000ul 236 #define PCI_BUS_MODES_INDEX(devconfig) \ 237 (((devconfig) & PCIXINITPAT) >> 13) 238 static const char *pci_bus_modes[] = 239 { 240 "PCI bus mode unknown", 241 "PCI bus mode unknown", 242 "PCI bus mode unknown", 243 "PCI bus mode unknown", 244 "PCI-X 101-133Mhz", 245 "PCI-X 67-100Mhz", 246 "PCI-X 50-66Mhz", 247 "PCI 33 or 66Mhz" 248 }; 249 250 #define TESTMODE 0x00000800ul 251 #define IRDY_RST 0x00000200ul 252 #define FRAME_RST 0x00000100ul 253 #define PCI64BIT 0x00000080ul 254 #define MRDCEN 0x00000040ul 255 #define ENDIANSEL 0x00000020ul 256 #define MIXQWENDIANEN 0x00000008ul 257 #define DACEN 0x00000004ul 258 #define STPWLEVEL 0x00000002ul 259 #define QWENDIANSEL 0x00000001ul 260 261 #define DEVCONFIG1 0x44 262 #define PREQDIS 0x01 263 264 #define CSIZE_LATTIME 0x0c 265 #define CACHESIZE 0x000000fful 266 #define LATTIME 0x0000ff00ul 267 268 static int ahd_check_extport(struct ahd_softc *ahd); 269 static void ahd_configure_termination(struct ahd_softc *ahd, 270 u_int adapter_control); 271 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 272 273 struct ahd_pci_identity * 274 ahd_find_pci_device(aic_dev_softc_t pci) 275 { 276 uint64_t full_id; 277 uint16_t device; 278 uint16_t vendor; 279 uint16_t subdevice; 280 uint16_t subvendor; 281 struct ahd_pci_identity *entry; 282 u_int i; 283 284 vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 285 device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 286 subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 287 subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 288 full_id = ahd_compose_id(device, 289 vendor, 290 subdevice, 291 subvendor); 292 293 /* 294 * If we are configured to attach to HostRAID 295 * controllers, mask out the IROC/HostRAID bit 296 * in the 297 */ 298 if (ahd_attach_to_HostRAID_controllers) 299 full_id &= ID_ALL_IROC_MASK; 300 301 for (i = 0; i < ahd_num_pci_devs; i++) { 302 entry = &ahd_pci_ident_table[i]; 303 if (entry->full_id == (full_id & entry->id_mask)) { 304 /* Honor exclusion entries. */ 305 if (entry->name == NULL) 306 return (NULL); 307 return (entry); 308 } 309 } 310 return (NULL); 311 } 312 313 int 314 ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry) 315 { 316 struct scb_data *shared_scb_data; 317 u_long l; 318 u_int command; 319 uint32_t devconfig; 320 uint16_t device; 321 uint16_t subvendor; 322 int error; 323 324 shared_scb_data = NULL; 325 ahd->description = entry->name; 326 /* 327 * Record if this is a HostRAID board. 328 */ 329 device = aic_pci_read_config(ahd->dev_softc, 330 PCIR_DEVICE, /*bytes*/2); 331 if (DEVID_9005_HOSTRAID(device)) 332 ahd->flags |= AHD_HOSTRAID_BOARD; 333 334 /* 335 * Record if this is an HP board. 336 */ 337 subvendor = aic_pci_read_config(ahd->dev_softc, 338 PCIR_SUBVEND_0, /*bytes*/2); 339 if (subvendor == SUBID_HP) 340 ahd->flags |= AHD_HP_BOARD; 341 342 error = entry->setup(ahd); 343 if (error != 0) 344 return (error); 345 346 /* 347 * Find the PCI-X cap pointer. If we don't find it, 348 * pcix_ptr will be 0. 349 */ 350 pci_find_extcap(ahd->dev_softc, PCIY_PCIX, &ahd->pcix_ptr); 351 devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 352 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 353 ahd->chip |= AHD_PCI; 354 /* Disable PCIX workarounds when running in PCI mode. */ 355 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 356 } else { 357 ahd->chip |= AHD_PCIX; 358 if (ahd->pcix_ptr == 0) 359 return (ENXIO); 360 } 361 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 362 363 aic_power_state_change(ahd, AIC_POWER_STATE_D0); 364 365 error = ahd_pci_map_registers(ahd); 366 if (error != 0) 367 return (error); 368 369 /* 370 * If we need to support high memory, enable dual 371 * address cycles. This bit must be set to enable 372 * high address bit generation even if we are on a 373 * 64bit bus (PCI64BIT set in devconfig). 374 */ 375 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 376 uint32_t devconfig; 377 378 if (bootverbose) 379 printf("%s: Enabling 39Bit Addressing\n", 380 ahd_name(ahd)); 381 devconfig = aic_pci_read_config(ahd->dev_softc, 382 DEVCONFIG, /*bytes*/4); 383 devconfig |= DACEN; 384 aic_pci_write_config(ahd->dev_softc, DEVCONFIG, 385 devconfig, /*bytes*/4); 386 } 387 388 /* Ensure busmastering is enabled */ 389 command = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 390 command |= PCIM_CMD_BUSMASTEREN; 391 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2); 392 393 error = ahd_softc_init(ahd); 394 if (error != 0) 395 return (error); 396 397 ahd->bus_intr = ahd_pci_intr; 398 399 error = ahd_reset(ahd, /*reinit*/FALSE); 400 if (error != 0) 401 return (ENXIO); 402 403 ahd->pci_cachesize = 404 aic_pci_read_config(ahd->dev_softc, CSIZE_LATTIME, 405 /*bytes*/1) & CACHESIZE; 406 ahd->pci_cachesize *= 4; 407 408 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 409 /* See if we have a SEEPROM and perform auto-term */ 410 error = ahd_check_extport(ahd); 411 if (error != 0) 412 return (error); 413 414 /* Core initialization */ 415 error = ahd_init(ahd); 416 if (error != 0) 417 return (error); 418 419 /* 420 * Allow interrupts now that we are completely setup. 421 */ 422 error = ahd_pci_map_int(ahd); 423 if (error != 0) 424 return (error); 425 426 ahd_list_lock(&l); 427 /* 428 * Link this softc in with all other ahd instances. 429 */ 430 ahd_softc_insert(ahd); 431 ahd_list_unlock(&l); 432 return (0); 433 } 434 435 /* 436 * Perform some simple tests that should catch situations where 437 * our registers are invalidly mapped. 438 */ 439 int 440 ahd_pci_test_register_access(struct ahd_softc *ahd) 441 { 442 uint32_t cmd; 443 u_int targpcistat; 444 u_int pci_status1; 445 int error; 446 uint8_t hcntrl; 447 448 error = EIO; 449 450 /* 451 * Enable PCI error interrupt status, but suppress NMIs 452 * generated by SERR raised due to target aborts. 453 */ 454 cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 455 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 456 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2); 457 458 /* 459 * First a simple test to see if any 460 * registers can be read. Reading 461 * HCNTRL has no side effects and has 462 * at least one bit that is guaranteed to 463 * be zero so it is a good register to 464 * use for this test. 465 */ 466 hcntrl = ahd_inb(ahd, HCNTRL); 467 if (hcntrl == 0xFF) 468 goto fail; 469 470 /* 471 * Next create a situation where write combining 472 * or read prefetching could be initiated by the 473 * CPU or host bridge. Our device does not support 474 * either, so look for data corruption and/or flaged 475 * PCI errors. First pause without causing another 476 * chip reset. 477 */ 478 hcntrl &= ~CHIPRST; 479 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 480 while (ahd_is_paused(ahd) == 0) 481 ; 482 483 /* Clear any PCI errors that occurred before our driver attached. */ 484 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 485 targpcistat = ahd_inb(ahd, TARGPCISTAT); 486 ahd_outb(ahd, TARGPCISTAT, targpcistat); 487 pci_status1 = aic_pci_read_config(ahd->dev_softc, 488 PCIR_STATUS + 1, /*bytes*/1); 489 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 490 pci_status1, /*bytes*/1); 491 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 492 ahd_outb(ahd, CLRINT, CLRPCIINT); 493 494 ahd_outb(ahd, SEQCTL0, PERRORDIS); 495 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 496 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 497 goto fail; 498 499 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 500 u_int targpcistat; 501 502 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 503 targpcistat = ahd_inb(ahd, TARGPCISTAT); 504 if ((targpcistat & STA) != 0) 505 goto fail; 506 } 507 508 error = 0; 509 510 fail: 511 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 512 513 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 514 targpcistat = ahd_inb(ahd, TARGPCISTAT); 515 516 /* Silently clear any latched errors. */ 517 ahd_outb(ahd, TARGPCISTAT, targpcistat); 518 pci_status1 = aic_pci_read_config(ahd->dev_softc, 519 PCIR_STATUS + 1, /*bytes*/1); 520 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 521 pci_status1, /*bytes*/1); 522 ahd_outb(ahd, CLRINT, CLRPCIINT); 523 } 524 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 525 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 526 return (error); 527 } 528 529 /* 530 * Check the external port logic for a serial eeprom 531 * and termination/cable detection contrls. 532 */ 533 static int 534 ahd_check_extport(struct ahd_softc *ahd) 535 { 536 struct vpd_config vpd; 537 struct seeprom_config *sc; 538 u_int adapter_control; 539 int have_seeprom; 540 int error; 541 542 sc = ahd->seep_config; 543 have_seeprom = ahd_acquire_seeprom(ahd); 544 if (have_seeprom) { 545 u_int start_addr; 546 547 /* 548 * Fetch VPD for this function and parse it. 549 */ 550 if (bootverbose) 551 printf("%s: Reading VPD from SEEPROM...", 552 ahd_name(ahd)); 553 554 /* Address is always in units of 16bit words */ 555 start_addr = ((2 * sizeof(*sc)) 556 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 557 558 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 559 start_addr, sizeof(vpd)/2, 560 /*bytestream*/TRUE); 561 if (error == 0) 562 error = ahd_parse_vpddata(ahd, &vpd); 563 if (bootverbose) 564 printf("%s: VPD parsing %s\n", 565 ahd_name(ahd), 566 error == 0 ? "successful" : "failed"); 567 568 if (bootverbose) 569 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 570 571 /* Address is always in units of 16bit words */ 572 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 573 574 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 575 start_addr, sizeof(*sc)/2, 576 /*bytestream*/FALSE); 577 578 if (error != 0) { 579 printf("Unable to read SEEPROM\n"); 580 have_seeprom = 0; 581 } else { 582 have_seeprom = ahd_verify_cksum(sc); 583 584 if (bootverbose) { 585 if (have_seeprom == 0) 586 printf ("checksum error\n"); 587 else 588 printf ("done.\n"); 589 } 590 } 591 ahd_release_seeprom(ahd); 592 } 593 594 if (!have_seeprom) { 595 u_int nvram_scb; 596 597 /* 598 * Pull scratch ram settings and treat them as 599 * if they are the contents of an seeprom if 600 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 601 * in SCB 0xFF. We manually compose the data as 16bit 602 * values to avoid endian issues. 603 */ 604 ahd_set_scbptr(ahd, 0xFF); 605 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 606 if (nvram_scb != 0xFF 607 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 608 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 609 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 610 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 611 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 612 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 613 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 614 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 615 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 616 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 617 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 618 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 619 uint16_t *sc_data; 620 int i; 621 622 ahd_set_scbptr(ahd, nvram_scb); 623 sc_data = (uint16_t *)sc; 624 for (i = 0; i < 64; i += 2) 625 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 626 have_seeprom = ahd_verify_cksum(sc); 627 if (have_seeprom) 628 ahd->flags |= AHD_SCB_CONFIG_USED; 629 } 630 } 631 632 #ifdef AHD_DEBUG 633 if (have_seeprom != 0 634 && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 635 uint16_t *sc_data; 636 int i; 637 638 printf("%s: Seeprom Contents:", ahd_name(ahd)); 639 sc_data = (uint16_t *)sc; 640 for (i = 0; i < (sizeof(*sc)); i += 2) 641 printf("\n\t0x%.4x", sc_data[i]); 642 printf("\n"); 643 } 644 #endif 645 646 if (!have_seeprom) { 647 if (bootverbose) 648 printf("%s: No SEEPROM available.\n", ahd_name(ahd)); 649 ahd->flags |= AHD_USEDEFAULTS; 650 error = ahd_default_config(ahd); 651 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 652 free(ahd->seep_config, M_DEVBUF); 653 ahd->seep_config = NULL; 654 } else { 655 error = ahd_parse_cfgdata(ahd, sc); 656 adapter_control = sc->adapter_control; 657 } 658 if (error != 0) 659 return (error); 660 661 ahd_configure_termination(ahd, adapter_control); 662 663 return (0); 664 } 665 666 static void 667 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 668 { 669 int error; 670 u_int sxfrctl1; 671 uint8_t termctl; 672 uint32_t devconfig; 673 674 devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 675 devconfig &= ~STPWLEVEL; 676 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 677 devconfig |= STPWLEVEL; 678 if (bootverbose) 679 printf("%s: STPWLEVEL is %s\n", 680 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 681 aic_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 682 683 /* Make sure current sensing is off. */ 684 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 685 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 686 } 687 688 /* 689 * Read to sense. Write to set. 690 */ 691 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 692 if ((adapter_control & CFAUTOTERM) == 0) { 693 if (bootverbose) 694 printf("%s: Manual Primary Termination\n", 695 ahd_name(ahd)); 696 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 697 if ((adapter_control & CFSTERM) != 0) 698 termctl |= FLX_TERMCTL_ENPRILOW; 699 if ((adapter_control & CFWSTERM) != 0) 700 termctl |= FLX_TERMCTL_ENPRIHIGH; 701 } else if (error != 0) { 702 printf("%s: Primary Auto-Term Sensing failed! " 703 "Using Defaults.\n", ahd_name(ahd)); 704 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 705 } 706 707 if ((adapter_control & CFSEAUTOTERM) == 0) { 708 if (bootverbose) 709 printf("%s: Manual Secondary Termination\n", 710 ahd_name(ahd)); 711 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 712 if ((adapter_control & CFSELOWTERM) != 0) 713 termctl |= FLX_TERMCTL_ENSECLOW; 714 if ((adapter_control & CFSEHIGHTERM) != 0) 715 termctl |= FLX_TERMCTL_ENSECHIGH; 716 } else if (error != 0) { 717 printf("%s: Secondary Auto-Term Sensing failed! " 718 "Using Defaults.\n", ahd_name(ahd)); 719 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 720 } 721 722 /* 723 * Now set the termination based on what we found. 724 */ 725 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 726 ahd->flags &= ~AHD_TERM_ENB_A; 727 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 728 ahd->flags |= AHD_TERM_ENB_A; 729 sxfrctl1 |= STPWEN; 730 } 731 /* Must set the latch once in order to be effective. */ 732 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 733 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 734 735 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 736 if (error != 0) { 737 printf("%s: Unable to set termination settings!\n", 738 ahd_name(ahd)); 739 } else if (bootverbose) { 740 printf("%s: Primary High byte termination %sabled\n", 741 ahd_name(ahd), 742 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 743 744 printf("%s: Primary Low byte termination %sabled\n", 745 ahd_name(ahd), 746 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 747 748 printf("%s: Secondary High byte termination %sabled\n", 749 ahd_name(ahd), 750 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 751 752 printf("%s: Secondary Low byte termination %sabled\n", 753 ahd_name(ahd), 754 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 755 } 756 return; 757 } 758 759 #define DPE 0x80 760 #define SSE 0x40 761 #define RMA 0x20 762 #define RTA 0x10 763 #define STA 0x08 764 #define DPR 0x01 765 766 static const char *split_status_source[] = 767 { 768 "DFF0", 769 "DFF1", 770 "OVLY", 771 "CMC", 772 }; 773 774 static const char *pci_status_source[] = 775 { 776 "DFF0", 777 "DFF1", 778 "SG", 779 "CMC", 780 "OVLY", 781 "NONE", 782 "MSI", 783 "TARG" 784 }; 785 786 static const char *split_status_strings[] = 787 { 788 "%s: Received split response in %s.\n", 789 "%s: Received split completion error message in %s\n", 790 "%s: Receive overrun in %s\n", 791 "%s: Count not complete in %s\n", 792 "%s: Split completion data bucket in %s\n", 793 "%s: Split completion address error in %s\n", 794 "%s: Split completion byte count error in %s\n", 795 "%s: Signaled Target-abort to early terminate a split in %s\n" 796 }; 797 798 static const char *pci_status_strings[] = 799 { 800 "%s: Data Parity Error has been reported via PERR# in %s\n", 801 "%s: Target initial wait state error in %s\n", 802 "%s: Split completion read data parity error in %s\n", 803 "%s: Split completion address attribute parity error in %s\n", 804 "%s: Received a Target Abort in %s\n", 805 "%s: Received a Master Abort in %s\n", 806 "%s: Signal System Error Detected in %s\n", 807 "%s: Address or Write Phase Parity Error Detected in %s.\n" 808 }; 809 810 void 811 ahd_pci_intr(struct ahd_softc *ahd) 812 { 813 uint8_t pci_status[8]; 814 ahd_mode_state saved_modes; 815 u_int pci_status1; 816 u_int intstat; 817 u_int i; 818 u_int reg; 819 820 intstat = ahd_inb(ahd, INTSTAT); 821 822 if ((intstat & SPLTINT) != 0) 823 ahd_pci_split_intr(ahd, intstat); 824 825 if ((intstat & PCIINT) == 0) 826 return; 827 828 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 829 saved_modes = ahd_save_modes(ahd); 830 ahd_dump_card_state(ahd); 831 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 832 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 833 834 if (i == 5) 835 continue; 836 pci_status[i] = ahd_inb(ahd, reg); 837 /* Clear latched errors. So our interrupt deasserts. */ 838 ahd_outb(ahd, reg, pci_status[i]); 839 } 840 841 for (i = 0; i < 8; i++) { 842 u_int bit; 843 844 if (i == 5) 845 continue; 846 847 for (bit = 0; bit < 8; bit++) { 848 849 if ((pci_status[i] & (0x1 << bit)) != 0) { 850 static const char *s; 851 852 s = pci_status_strings[bit]; 853 if (i == 7/*TARG*/ && bit == 3) 854 s = "%s: Signaled Target Abort\n"; 855 printf(s, ahd_name(ahd), pci_status_source[i]); 856 } 857 } 858 } 859 pci_status1 = aic_pci_read_config(ahd->dev_softc, 860 PCIR_STATUS + 1, /*bytes*/1); 861 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 862 pci_status1, /*bytes*/1); 863 ahd_restore_modes(ahd, saved_modes); 864 ahd_outb(ahd, CLRINT, CLRPCIINT); 865 ahd_unpause(ahd); 866 } 867 868 static void 869 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 870 { 871 uint8_t split_status[4]; 872 uint8_t split_status1[4]; 873 uint8_t sg_split_status[2]; 874 uint8_t sg_split_status1[2]; 875 ahd_mode_state saved_modes; 876 u_int i; 877 uint32_t pcix_status; 878 879 /* 880 * Check for splits in all modes. Modes 0 and 1 881 * additionally have SG engine splits to look at. 882 */ 883 pcix_status = aic_pci_read_config(ahd->dev_softc, 884 ahd->pcix_ptr + PCIXR_STATUS, /*bytes*/ 4); 885 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 886 ahd_name(ahd), pcix_status >> 16); 887 saved_modes = ahd_save_modes(ahd); 888 for (i = 0; i < 4; i++) { 889 ahd_set_modes(ahd, i, i); 890 891 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 892 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 893 /* Clear latched errors. So our interrupt deasserts. */ 894 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 895 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 896 if (i > 1) 897 continue; 898 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 899 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 900 /* Clear latched errors. So our interrupt deasserts. */ 901 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 902 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 903 } 904 905 for (i = 0; i < 4; i++) { 906 u_int bit; 907 908 for (bit = 0; bit < 8; bit++) { 909 910 if ((split_status[i] & (0x1 << bit)) != 0) { 911 static const char *s; 912 913 s = split_status_strings[bit]; 914 printf(s, ahd_name(ahd), 915 split_status_source[i]); 916 } 917 918 if (i > 1) 919 continue; 920 921 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 922 static const char *s; 923 924 s = split_status_strings[bit]; 925 printf(s, ahd_name(ahd), "SG"); 926 } 927 } 928 } 929 /* 930 * Clear PCI-X status bits. 931 */ 932 aic_pci_write_config(ahd->dev_softc, ahd->pcix_ptr + PCIXR_STATUS, 933 pcix_status, /*bytes*/4); 934 ahd_outb(ahd, CLRINT, CLRSPLTINT); 935 ahd_restore_modes(ahd, saved_modes); 936 } 937 938 static int 939 ahd_aic7901_setup(struct ahd_softc *ahd) 940 { 941 942 ahd->chip = AHD_AIC7901; 943 ahd->features = AHD_AIC7901_FE; 944 return (ahd_aic790X_setup(ahd)); 945 } 946 947 static int 948 ahd_aic7901A_setup(struct ahd_softc *ahd) 949 { 950 951 ahd->chip = AHD_AIC7901A; 952 ahd->features = AHD_AIC7901A_FE; 953 return (ahd_aic790X_setup(ahd)); 954 } 955 956 static int 957 ahd_aic7902_setup(struct ahd_softc *ahd) 958 { 959 ahd->chip = AHD_AIC7902; 960 ahd->features = AHD_AIC7902_FE; 961 return (ahd_aic790X_setup(ahd)); 962 } 963 964 static int 965 ahd_aic790X_setup(struct ahd_softc *ahd) 966 { 967 aic_dev_softc_t pci; 968 u_int rev; 969 970 pci = ahd->dev_softc; 971 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 972 if (rev < ID_AIC7902_PCI_REV_A4) { 973 printf("%s: Unable to attach to unsupported chip revision %d\n", 974 ahd_name(ahd), rev); 975 aic_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2); 976 return (ENXIO); 977 } 978 ahd->channel = aic_get_pci_function(pci) + 'A'; 979 if (rev < ID_AIC7902_PCI_REV_B0) { 980 /* 981 * Enable A series workarounds. 982 */ 983 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 984 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 985 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 986 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 987 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 988 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 989 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 990 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 991 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 992 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 993 | AHD_FAINT_LED_BUG; 994 995 /* 996 * IO Cell paramter setup. 997 */ 998 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 999 1000 if ((ahd->flags & AHD_HP_BOARD) == 0) 1001 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 1002 } else { 1003 u_int devconfig1; 1004 1005 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1006 | AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY; 1007 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; 1008 1009 /* 1010 * Some issues have been resolved in the 7901B. 1011 */ 1012 if ((ahd->features & AHD_MULTI_FUNC) != 0) 1013 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG 1014 | AHD_BUSFREEREV_BUG; 1015 1016 /* 1017 * IO Cell paramter setup. 1018 */ 1019 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1020 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1021 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1022 1023 /* 1024 * Set the PREQDIS bit for H2B which disables some workaround 1025 * that doesn't work on regular PCI busses. 1026 * XXX - Find out exactly what this does from the hardware 1027 * folks! 1028 */ 1029 devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 1030 aic_pci_write_config(pci, DEVCONFIG1, 1031 devconfig1|PREQDIS, /*bytes*/1); 1032 devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 1033 } 1034 1035 return (0); 1036 } 1037