1 /*- 2 * Product specific probe and attach routines for: 3 * aic7901 and aic7902 SCSI controllers 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Copyright (c) 1994-2001 Justin T. Gibbs. 8 * Copyright (c) 2000-2002 Adaptec Inc. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * substantially similar to the "NO WARRANTY" disclaimer below 19 * ("Disclaimer") and any redistribution must be conditioned upon 20 * including a substantially similar Disclaimer requirement for further 21 * binary redistribution. 22 * 3. Neither the names of the above-listed copyright holders nor the names 23 * of any contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * Alternatively, this software may be distributed under the terms of the 27 * GNU General Public License ("GPL") version 2 as published by the Free 28 * Software Foundation. 29 * 30 * NO WARRANTY 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGES. 42 * 43 * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#88 $ 44 */ 45 46 #ifdef __linux__ 47 #include "aic79xx_osm.h" 48 #include "aic79xx_inline.h" 49 #else 50 #include <sys/cdefs.h> 51 #include <dev/aic7xxx/aic79xx_osm.h> 52 #include <dev/aic7xxx/aic79xx_inline.h> 53 #endif 54 55 static __inline uint64_t 56 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 57 { 58 uint64_t id; 59 60 id = subvendor 61 | (subdevice << 16) 62 | ((uint64_t)vendor << 32) 63 | ((uint64_t)device << 48); 64 65 return (id); 66 } 67 68 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 69 #define ID_ALL_IROC_MASK 0xFF7FFFFFFFFFFFFFull 70 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 71 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull 72 #define ID_9005_GENERIC_IROC_MASK 0xFF70FFFF00000000ull 73 74 #define ID_AIC7901 0x800F9005FFFF9005ull 75 #define ID_AHA_29320A 0x8000900500609005ull 76 #define ID_AHA_29320ALP 0x8017900500449005ull 77 #define ID_AHA_29320LPE 0x8017900500459005ull 78 79 #define ID_AIC7901A 0x801E9005FFFF9005ull 80 #define ID_AHA_29320LP 0x8014900500449005ull 81 82 #define ID_AIC7902 0x801F9005FFFF9005ull 83 #define ID_AIC7902_B 0x801D9005FFFF9005ull 84 #define ID_AHA_39320 0x8010900500409005ull 85 #define ID_AHA_29320 0x8012900500429005ull 86 #define ID_AHA_29320B 0x8013900500439005ull 87 #define ID_AHA_39320_B 0x8015900500409005ull 88 #define ID_AHA_39320_B_DELL 0x8015900501681028ull 89 #define ID_AHA_39320A 0x8016900500409005ull 90 #define ID_AHA_39320D 0x8011900500419005ull 91 #define ID_AHA_39320D_B 0x801C900500419005ull 92 #define ID_AHA_39320D_HP 0x8011900500AC0E11ull 93 #define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull 94 #define ID_AIC7902_PCI_REV_A4 0x3 95 #define ID_AIC7902_PCI_REV_B0 0x10 96 #define SUBID_HP 0x0E11 97 #define DEVICE8081 0x8081 98 #define DEVICE8088 0x8088 99 #define DEVICE8089 0x8089 100 #define ADAPTECVENDORID 0x9005 101 #define SUBVENDOR9005 0x9005 102 103 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80) 104 105 #define DEVID_9005_TYPE(id) ((id) & 0xF) 106 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 107 #define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */ 108 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 109 110 #define DEVID_9005_MFUNC(id) ((id) & 0x10) 111 112 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000) 113 114 #define SUBID_9005_TYPE(id) ((id) & 0xF) 115 #define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */ 116 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 117 118 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0) 119 120 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20) 121 122 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6) 123 #define SUBID_9005_SEEPTYPE_NONE 0x0 124 #define SUBID_9005_SEEPTYPE_4K 0x1 125 126 static ahd_device_setup_t ahd_aic7901_setup; 127 static ahd_device_setup_t ahd_aic7901A_setup; 128 static ahd_device_setup_t ahd_aic7902_setup; 129 static ahd_device_setup_t ahd_aic790X_setup; 130 131 struct ahd_pci_identity ahd_pci_ident_table [] = 132 { 133 /* aic7901 based controllers */ 134 { 135 ID_AHA_29320A, 136 ID_ALL_MASK, 137 "Adaptec 29320A Ultra320 SCSI adapter", 138 ahd_aic7901_setup 139 }, 140 { 141 ID_AHA_29320ALP, 142 ID_ALL_MASK, 143 "Adaptec 29320ALP Ultra320 SCSI adapter", 144 ahd_aic7901_setup 145 }, 146 { 147 ID_AHA_29320LPE, 148 ID_ALL_MASK, 149 "Adaptec 29320LPE Ultra320 SCSI adapter", 150 ahd_aic7901_setup 151 }, 152 /* aic7901A based controllers */ 153 { 154 ID_AHA_29320LP, 155 ID_ALL_MASK, 156 "Adaptec 29320LP Ultra320 SCSI adapter", 157 ahd_aic7901A_setup 158 }, 159 /* aic7902 based controllers */ 160 { 161 ID_AHA_29320, 162 ID_ALL_MASK, 163 "Adaptec 29320 Ultra320 SCSI adapter", 164 ahd_aic7902_setup 165 }, 166 { 167 ID_AHA_29320B, 168 ID_ALL_MASK, 169 "Adaptec 29320B Ultra320 SCSI adapter", 170 ahd_aic7902_setup 171 }, 172 { 173 ID_AHA_39320, 174 ID_ALL_MASK, 175 "Adaptec 39320 Ultra320 SCSI adapter", 176 ahd_aic7902_setup 177 }, 178 { 179 ID_AHA_39320_B, 180 ID_ALL_MASK, 181 "Adaptec 39320 Ultra320 SCSI adapter", 182 ahd_aic7902_setup 183 }, 184 { 185 ID_AHA_39320_B_DELL, 186 ID_ALL_MASK, 187 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter", 188 ahd_aic7902_setup 189 }, 190 { 191 ID_AHA_39320A, 192 ID_ALL_MASK, 193 "Adaptec 39320A Ultra320 SCSI adapter", 194 ahd_aic7902_setup 195 }, 196 { 197 ID_AHA_39320D, 198 ID_ALL_MASK, 199 "Adaptec 39320D Ultra320 SCSI adapter", 200 ahd_aic7902_setup 201 }, 202 { 203 ID_AHA_39320D_HP, 204 ID_ALL_MASK, 205 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 206 ahd_aic7902_setup 207 }, 208 { 209 ID_AHA_39320D_B, 210 ID_ALL_MASK, 211 "Adaptec 39320D Ultra320 SCSI adapter", 212 ahd_aic7902_setup 213 }, 214 { 215 ID_AHA_39320D_B_HP, 216 ID_ALL_MASK, 217 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter", 218 ahd_aic7902_setup 219 }, 220 /* Generic chip probes for devices we don't know 'exactly' */ 221 { 222 ID_AIC7901 & ID_9005_GENERIC_MASK, 223 ID_9005_GENERIC_MASK, 224 "Adaptec AIC7901 Ultra320 SCSI adapter", 225 ahd_aic7901_setup 226 }, 227 { 228 ID_AIC7901A & ID_DEV_VENDOR_MASK, 229 ID_DEV_VENDOR_MASK, 230 "Adaptec AIC7901A Ultra320 SCSI adapter", 231 ahd_aic7901A_setup 232 }, 233 { 234 ID_AIC7902 & ID_9005_GENERIC_MASK, 235 ID_9005_GENERIC_MASK, 236 "Adaptec AIC7902 Ultra320 SCSI adapter", 237 ahd_aic7902_setup 238 } 239 }; 240 241 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); 242 243 #define DEVCONFIG 0x40 244 #define PCIXINITPAT 0x0000E000ul 245 #define PCIXINIT_PCI33_66 0x0000E000ul 246 #define PCIXINIT_PCIX50_66 0x0000C000ul 247 #define PCIXINIT_PCIX66_100 0x0000A000ul 248 #define PCIXINIT_PCIX100_133 0x00008000ul 249 #define PCI_BUS_MODES_INDEX(devconfig) \ 250 (((devconfig) & PCIXINITPAT) >> 13) 251 static const char *pci_bus_modes[] = 252 { 253 "PCI bus mode unknown", 254 "PCI bus mode unknown", 255 "PCI bus mode unknown", 256 "PCI bus mode unknown", 257 "PCI-X 101-133MHz", 258 "PCI-X 67-100MHz", 259 "PCI-X 50-66MHz", 260 "PCI 33 or 66MHz" 261 }; 262 263 #define TESTMODE 0x00000800ul 264 #define IRDY_RST 0x00000200ul 265 #define FRAME_RST 0x00000100ul 266 #define PCI64BIT 0x00000080ul 267 #define MRDCEN 0x00000040ul 268 #define ENDIANSEL 0x00000020ul 269 #define MIXQWENDIANEN 0x00000008ul 270 #define DACEN 0x00000004ul 271 #define STPWLEVEL 0x00000002ul 272 #define QWENDIANSEL 0x00000001ul 273 274 #define DEVCONFIG1 0x44 275 #define PREQDIS 0x01 276 277 #define CSIZE_LATTIME 0x0c 278 #define CACHESIZE 0x000000fful 279 #define LATTIME 0x0000ff00ul 280 281 static int ahd_check_extport(struct ahd_softc *ahd); 282 static void ahd_configure_termination(struct ahd_softc *ahd, 283 u_int adapter_control); 284 static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat); 285 286 struct ahd_pci_identity * 287 ahd_find_pci_device(aic_dev_softc_t pci) 288 { 289 uint64_t full_id; 290 uint16_t device; 291 uint16_t vendor; 292 uint16_t subdevice; 293 uint16_t subvendor; 294 struct ahd_pci_identity *entry; 295 u_int i; 296 297 vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 298 device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 299 subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 300 subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 301 302 if ((vendor == ADAPTECVENDORID) && (subvendor == SUBVENDOR9005)) { 303 if ((device == DEVICE8081) || (device == DEVICE8088) || 304 (device == DEVICE8089)) { 305 printf("Controller device ID conflict with PMC Adaptec HBA\n"); 306 return (NULL); 307 } 308 } 309 310 full_id = ahd_compose_id(device, 311 vendor, 312 subdevice, 313 subvendor); 314 315 /* 316 * If we are configured to attach to HostRAID 317 * controllers, mask out the IROC/HostRAID bit 318 * in the 319 */ 320 if (ahd_attach_to_HostRAID_controllers) 321 full_id &= ID_ALL_IROC_MASK; 322 323 for (i = 0; i < ahd_num_pci_devs; i++) { 324 entry = &ahd_pci_ident_table[i]; 325 if (entry->full_id == (full_id & entry->id_mask)) { 326 /* Honor exclusion entries. */ 327 if (entry->name == NULL) 328 return (NULL); 329 return (entry); 330 } 331 } 332 return (NULL); 333 } 334 335 int 336 ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry) 337 { 338 u_int command; 339 uint32_t devconfig; 340 uint16_t device; 341 uint16_t subvendor; 342 int error; 343 344 ahd->description = entry->name; 345 /* 346 * Record if this is a HostRAID board. 347 */ 348 device = aic_pci_read_config(ahd->dev_softc, 349 PCIR_DEVICE, /*bytes*/2); 350 if (DEVID_9005_HOSTRAID(device)) 351 ahd->flags |= AHD_HOSTRAID_BOARD; 352 353 /* 354 * Record if this is an HP board. 355 */ 356 subvendor = aic_pci_read_config(ahd->dev_softc, 357 PCIR_SUBVEND_0, /*bytes*/2); 358 if (subvendor == SUBID_HP) 359 ahd->flags |= AHD_HP_BOARD; 360 361 error = entry->setup(ahd); 362 if (error != 0) 363 return (error); 364 365 /* 366 * Find the PCI-X cap pointer. If we don't find it, 367 * pcix_ptr will be 0. 368 */ 369 pci_find_cap(ahd->dev_softc, PCIY_PCIX, &ahd->pcix_ptr); 370 devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 371 if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { 372 ahd->chip |= AHD_PCI; 373 /* Disable PCIX workarounds when running in PCI mode. */ 374 ahd->bugs &= ~AHD_PCIX_BUG_MASK; 375 } else { 376 ahd->chip |= AHD_PCIX; 377 if (ahd->pcix_ptr == 0) 378 return (ENXIO); 379 } 380 ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; 381 382 aic_power_state_change(ahd, AIC_POWER_STATE_D0); 383 384 error = ahd_pci_map_registers(ahd); 385 if (error != 0) 386 return (error); 387 388 /* 389 * If we need to support high memory, enable dual 390 * address cycles. This bit must be set to enable 391 * high address bit generation even if we are on a 392 * 64bit bus (PCI64BIT set in devconfig). 393 */ 394 if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { 395 uint32_t devconfig; 396 397 if (bootverbose) 398 printf("%s: Enabling 39Bit Addressing\n", 399 ahd_name(ahd)); 400 devconfig = aic_pci_read_config(ahd->dev_softc, 401 DEVCONFIG, /*bytes*/4); 402 devconfig |= DACEN; 403 aic_pci_write_config(ahd->dev_softc, DEVCONFIG, 404 devconfig, /*bytes*/4); 405 } 406 407 /* Ensure busmastering is enabled */ 408 command = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 409 command |= PCIM_CMD_BUSMASTEREN; 410 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2); 411 412 error = ahd_softc_init(ahd); 413 if (error != 0) 414 return (error); 415 416 ahd->bus_intr = ahd_pci_intr; 417 418 error = ahd_reset(ahd, /*reinit*/FALSE); 419 if (error != 0) 420 return (ENXIO); 421 422 ahd->pci_cachesize = 423 aic_pci_read_config(ahd->dev_softc, CSIZE_LATTIME, 424 /*bytes*/1) & CACHESIZE; 425 ahd->pci_cachesize *= 4; 426 427 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 428 /* See if we have a SEEPROM and perform auto-term */ 429 error = ahd_check_extport(ahd); 430 if (error != 0) 431 return (error); 432 433 /* Core initialization */ 434 error = ahd_init(ahd); 435 if (error != 0) 436 return (error); 437 438 /* 439 * Allow interrupts now that we are completely setup. 440 */ 441 error = ahd_pci_map_int(ahd); 442 if (error != 0) 443 return (error); 444 445 ahd_lock(ahd); 446 /* 447 * Link this softc in with all other ahd instances. 448 */ 449 ahd_softc_insert(ahd); 450 ahd_unlock(ahd); 451 return (0); 452 } 453 454 /* 455 * Perform some simple tests that should catch situations where 456 * our registers are invalidly mapped. 457 */ 458 int 459 ahd_pci_test_register_access(struct ahd_softc *ahd) 460 { 461 uint32_t cmd; 462 u_int targpcistat; 463 u_int pci_status1; 464 int error; 465 uint8_t hcntrl; 466 467 error = EIO; 468 469 /* 470 * Enable PCI error interrupt status, but suppress NMIs 471 * generated by SERR raised due to target aborts. 472 */ 473 cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 474 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 475 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2); 476 477 /* 478 * First a simple test to see if any 479 * registers can be read. Reading 480 * HCNTRL has no side effects and has 481 * at least one bit that is guaranteed to 482 * be zero so it is a good register to 483 * use for this test. 484 */ 485 hcntrl = ahd_inb(ahd, HCNTRL); 486 if (hcntrl == 0xFF) 487 goto fail; 488 489 /* 490 * Next create a situation where write combining 491 * or read prefetching could be initiated by the 492 * CPU or host bridge. Our device does not support 493 * either, so look for data corruption and/or flagged 494 * PCI errors. First pause without causing another 495 * chip reset. 496 */ 497 hcntrl &= ~CHIPRST; 498 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); 499 while (ahd_is_paused(ahd) == 0) 500 ; 501 502 /* Clear any PCI errors that occurred before our driver attached. */ 503 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 504 targpcistat = ahd_inb(ahd, TARGPCISTAT); 505 ahd_outb(ahd, TARGPCISTAT, targpcistat); 506 pci_status1 = aic_pci_read_config(ahd->dev_softc, 507 PCIR_STATUS + 1, /*bytes*/1); 508 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 509 pci_status1, /*bytes*/1); 510 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 511 ahd_outb(ahd, CLRINT, CLRPCIINT); 512 513 ahd_outb(ahd, SEQCTL0, PERRORDIS); 514 ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); 515 if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) 516 goto fail; 517 518 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 519 u_int targpcistat; 520 521 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 522 targpcistat = ahd_inb(ahd, TARGPCISTAT); 523 if ((targpcistat & STA) != 0) 524 goto fail; 525 } 526 527 error = 0; 528 529 fail: 530 if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { 531 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 532 targpcistat = ahd_inb(ahd, TARGPCISTAT); 533 534 /* Silently clear any latched errors. */ 535 ahd_outb(ahd, TARGPCISTAT, targpcistat); 536 pci_status1 = aic_pci_read_config(ahd->dev_softc, 537 PCIR_STATUS + 1, /*bytes*/1); 538 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 539 pci_status1, /*bytes*/1); 540 ahd_outb(ahd, CLRINT, CLRPCIINT); 541 } 542 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); 543 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 544 return (error); 545 } 546 547 /* 548 * Check the external port logic for a serial eeprom 549 * and termination/cable detection contrls. 550 */ 551 static int 552 ahd_check_extport(struct ahd_softc *ahd) 553 { 554 struct vpd_config vpd; 555 struct seeprom_config *sc; 556 u_int adapter_control; 557 int have_seeprom; 558 int error; 559 560 sc = ahd->seep_config; 561 have_seeprom = ahd_acquire_seeprom(ahd); 562 if (have_seeprom) { 563 u_int start_addr; 564 565 /* 566 * Fetch VPD for this function and parse it. 567 */ 568 if (bootverbose) 569 printf("%s: Reading VPD from SEEPROM...", 570 ahd_name(ahd)); 571 572 /* Address is always in units of 16bit words */ 573 start_addr = ((2 * sizeof(*sc)) 574 + (sizeof(vpd) * (ahd->channel - 'A'))) / 2; 575 576 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd, 577 start_addr, sizeof(vpd)/2, 578 /*bytestream*/TRUE); 579 if (error == 0) 580 error = ahd_parse_vpddata(ahd, &vpd); 581 if (bootverbose) 582 printf("%s: VPD parsing %s\n", 583 ahd_name(ahd), 584 error == 0 ? "successful" : "failed"); 585 586 if (bootverbose) 587 printf("%s: Reading SEEPROM...", ahd_name(ahd)); 588 589 /* Address is always in units of 16bit words */ 590 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A'); 591 592 error = ahd_read_seeprom(ahd, (uint16_t *)sc, 593 start_addr, sizeof(*sc)/2, 594 /*bytestream*/FALSE); 595 596 if (error != 0) { 597 printf("Unable to read SEEPROM\n"); 598 have_seeprom = 0; 599 } else { 600 have_seeprom = ahd_verify_cksum(sc); 601 602 if (bootverbose) { 603 if (have_seeprom == 0) 604 printf ("checksum error\n"); 605 else 606 printf ("done.\n"); 607 } 608 } 609 ahd_release_seeprom(ahd); 610 } 611 612 if (!have_seeprom) { 613 u_int nvram_scb; 614 615 /* 616 * Pull scratch ram settings and treat them as 617 * if they are the contents of an seeprom if 618 * the 'ADPT', 'BIOS', or 'ASPI' signature is found 619 * in SCB 0xFF. We manually compose the data as 16bit 620 * values to avoid endian issues. 621 */ 622 ahd_set_scbptr(ahd, 0xFF); 623 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET); 624 if (nvram_scb != 0xFF 625 && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 626 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D' 627 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 628 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T') 629 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B' 630 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I' 631 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O' 632 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S') 633 || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A' 634 && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S' 635 && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P' 636 && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) { 637 uint16_t *sc_data; 638 int i; 639 640 ahd_set_scbptr(ahd, nvram_scb); 641 sc_data = (uint16_t *)sc; 642 for (i = 0; i < 64; i += 2) 643 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i); 644 have_seeprom = ahd_verify_cksum(sc); 645 if (have_seeprom) 646 ahd->flags |= AHD_SCB_CONFIG_USED; 647 } 648 } 649 650 #ifdef AHD_DEBUG 651 if (have_seeprom != 0 652 && (ahd_debug & AHD_DUMP_SEEPROM) != 0) { 653 uint16_t *sc_data; 654 int i; 655 656 printf("%s: Seeprom Contents:", ahd_name(ahd)); 657 sc_data = (uint16_t *)sc; 658 for (i = 0; i < (sizeof(*sc)); i += 2) 659 printf("\n\t0x%.4x", sc_data[i]); 660 printf("\n"); 661 } 662 #endif 663 664 if (!have_seeprom) { 665 if (bootverbose) 666 printf("%s: No SEEPROM available.\n", ahd_name(ahd)); 667 ahd->flags |= AHD_USEDEFAULTS; 668 error = ahd_default_config(ahd); 669 adapter_control = CFAUTOTERM|CFSEAUTOTERM; 670 free(ahd->seep_config, M_DEVBUF); 671 ahd->seep_config = NULL; 672 } else { 673 error = ahd_parse_cfgdata(ahd, sc); 674 adapter_control = sc->adapter_control; 675 } 676 if (error != 0) 677 return (error); 678 679 ahd_configure_termination(ahd, adapter_control); 680 681 return (0); 682 } 683 684 static void 685 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) 686 { 687 int error; 688 u_int sxfrctl1; 689 uint8_t termctl; 690 uint32_t devconfig; 691 692 devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); 693 devconfig &= ~STPWLEVEL; 694 if ((ahd->flags & AHD_STPWLEVEL_A) != 0) 695 devconfig |= STPWLEVEL; 696 if (bootverbose) 697 printf("%s: STPWLEVEL is %s\n", 698 ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); 699 aic_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 700 701 /* Make sure current sensing is off. */ 702 if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { 703 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 704 } 705 706 /* 707 * Read to sense. Write to set. 708 */ 709 error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); 710 if ((adapter_control & CFAUTOTERM) == 0) { 711 if (bootverbose) 712 printf("%s: Manual Primary Termination\n", 713 ahd_name(ahd)); 714 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); 715 if ((adapter_control & CFSTERM) != 0) 716 termctl |= FLX_TERMCTL_ENPRILOW; 717 if ((adapter_control & CFWSTERM) != 0) 718 termctl |= FLX_TERMCTL_ENPRIHIGH; 719 } else if (error != 0) { 720 printf("%s: Primary Auto-Term Sensing failed! " 721 "Using Defaults.\n", ahd_name(ahd)); 722 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; 723 } 724 725 if ((adapter_control & CFSEAUTOTERM) == 0) { 726 if (bootverbose) 727 printf("%s: Manual Secondary Termination\n", 728 ahd_name(ahd)); 729 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); 730 if ((adapter_control & CFSELOWTERM) != 0) 731 termctl |= FLX_TERMCTL_ENSECLOW; 732 if ((adapter_control & CFSEHIGHTERM) != 0) 733 termctl |= FLX_TERMCTL_ENSECHIGH; 734 } else if (error != 0) { 735 printf("%s: Secondary Auto-Term Sensing failed! " 736 "Using Defaults.\n", ahd_name(ahd)); 737 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; 738 } 739 740 /* 741 * Now set the termination based on what we found. 742 */ 743 sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; 744 ahd->flags &= ~AHD_TERM_ENB_A; 745 if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { 746 ahd->flags |= AHD_TERM_ENB_A; 747 sxfrctl1 |= STPWEN; 748 } 749 /* Must set the latch once in order to be effective. */ 750 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 751 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 752 753 error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); 754 if (error != 0) { 755 printf("%s: Unable to set termination settings!\n", 756 ahd_name(ahd)); 757 } else if (bootverbose) { 758 printf("%s: Primary High byte termination %sabled\n", 759 ahd_name(ahd), 760 (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); 761 762 printf("%s: Primary Low byte termination %sabled\n", 763 ahd_name(ahd), 764 (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); 765 766 printf("%s: Secondary High byte termination %sabled\n", 767 ahd_name(ahd), 768 (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); 769 770 printf("%s: Secondary Low byte termination %sabled\n", 771 ahd_name(ahd), 772 (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); 773 } 774 return; 775 } 776 777 #define DPE 0x80 778 #define SSE 0x40 779 #define RMA 0x20 780 #define RTA 0x10 781 #define STA 0x08 782 #define DPR 0x01 783 784 static const char *split_status_source[] = 785 { 786 "DFF0", 787 "DFF1", 788 "OVLY", 789 "CMC", 790 }; 791 792 static const char *pci_status_source[] = 793 { 794 "DFF0", 795 "DFF1", 796 "SG", 797 "CMC", 798 "OVLY", 799 "NONE", 800 "MSI", 801 "TARG" 802 }; 803 804 static const char *split_status_strings[] = 805 { 806 "%s: Received split response in %s.\n", 807 "%s: Received split completion error message in %s\n", 808 "%s: Receive overrun in %s\n", 809 "%s: Count not complete in %s\n", 810 "%s: Split completion data bucket in %s\n", 811 "%s: Split completion address error in %s\n", 812 "%s: Split completion byte count error in %s\n", 813 "%s: Signaled Target-abort to early terminate a split in %s\n" 814 }; 815 816 static const char *pci_status_strings[] = 817 { 818 "%s: Data Parity Error has been reported via PERR# in %s\n", 819 "%s: Target initial wait state error in %s\n", 820 "%s: Split completion read data parity error in %s\n", 821 "%s: Split completion address attribute parity error in %s\n", 822 "%s: Received a Target Abort in %s\n", 823 "%s: Received a Master Abort in %s\n", 824 "%s: Signal System Error Detected in %s\n", 825 "%s: Address or Write Phase Parity Error Detected in %s.\n" 826 }; 827 828 void 829 ahd_pci_intr(struct ahd_softc *ahd) 830 { 831 uint8_t pci_status[8]; 832 ahd_mode_state saved_modes; 833 u_int pci_status1; 834 u_int intstat; 835 u_int i; 836 u_int reg; 837 838 intstat = ahd_inb(ahd, INTSTAT); 839 840 if ((intstat & SPLTINT) != 0) 841 ahd_pci_split_intr(ahd, intstat); 842 843 if ((intstat & PCIINT) == 0) 844 return; 845 846 printf("%s: PCI error Interrupt\n", ahd_name(ahd)); 847 saved_modes = ahd_save_modes(ahd); 848 ahd_dump_card_state(ahd); 849 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 850 for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) { 851 if (i == 5) 852 continue; 853 pci_status[i] = ahd_inb(ahd, reg); 854 /* Clear latched errors. So our interrupt deasserts. */ 855 ahd_outb(ahd, reg, pci_status[i]); 856 } 857 858 for (i = 0; i < 8; i++) { 859 u_int bit; 860 861 if (i == 5) 862 continue; 863 864 for (bit = 0; bit < 8; bit++) { 865 if ((pci_status[i] & (0x1 << bit)) != 0) { 866 static const char *s; 867 868 s = pci_status_strings[bit]; 869 if (i == 7/*TARG*/ && bit == 3) 870 s = "%s: Signaled Target Abort\n"; 871 printf(s, ahd_name(ahd), pci_status_source[i]); 872 } 873 } 874 } 875 pci_status1 = aic_pci_read_config(ahd->dev_softc, 876 PCIR_STATUS + 1, /*bytes*/1); 877 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 878 pci_status1, /*bytes*/1); 879 ahd_restore_modes(ahd, saved_modes); 880 ahd_outb(ahd, CLRINT, CLRPCIINT); 881 ahd_unpause(ahd); 882 } 883 884 static void 885 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) 886 { 887 uint8_t split_status[4]; 888 uint8_t split_status1[4]; 889 uint8_t sg_split_status[2]; 890 uint8_t sg_split_status1[2]; 891 ahd_mode_state saved_modes; 892 u_int i; 893 uint32_t pcix_status; 894 895 /* 896 * Check for splits in all modes. Modes 0 and 1 897 * additionally have SG engine splits to look at. 898 */ 899 pcix_status = aic_pci_read_config(ahd->dev_softc, 900 ahd->pcix_ptr + PCIXR_STATUS, /*bytes*/ 4); 901 printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", 902 ahd_name(ahd), pcix_status >> 16); 903 saved_modes = ahd_save_modes(ahd); 904 for (i = 0; i < 4; i++) { 905 ahd_set_modes(ahd, i, i); 906 907 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); 908 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); 909 /* Clear latched errors. So our interrupt deasserts. */ 910 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); 911 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); 912 if (i > 1) 913 continue; 914 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); 915 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); 916 /* Clear latched errors. So our interrupt deasserts. */ 917 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); 918 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); 919 } 920 921 for (i = 0; i < 4; i++) { 922 u_int bit; 923 924 for (bit = 0; bit < 8; bit++) { 925 if ((split_status[i] & (0x1 << bit)) != 0) { 926 static const char *s; 927 928 s = split_status_strings[bit]; 929 printf(s, ahd_name(ahd), 930 split_status_source[i]); 931 } 932 933 if (i > 1) 934 continue; 935 936 if ((sg_split_status[i] & (0x1 << bit)) != 0) { 937 static const char *s; 938 939 s = split_status_strings[bit]; 940 printf(s, ahd_name(ahd), "SG"); 941 } 942 } 943 } 944 /* 945 * Clear PCI-X status bits. 946 */ 947 aic_pci_write_config(ahd->dev_softc, ahd->pcix_ptr + PCIXR_STATUS, 948 pcix_status, /*bytes*/4); 949 ahd_outb(ahd, CLRINT, CLRSPLTINT); 950 ahd_restore_modes(ahd, saved_modes); 951 } 952 953 static int 954 ahd_aic7901_setup(struct ahd_softc *ahd) 955 { 956 957 ahd->chip = AHD_AIC7901; 958 ahd->features = AHD_AIC7901_FE; 959 return (ahd_aic790X_setup(ahd)); 960 } 961 962 static int 963 ahd_aic7901A_setup(struct ahd_softc *ahd) 964 { 965 966 ahd->chip = AHD_AIC7901A; 967 ahd->features = AHD_AIC7901A_FE; 968 return (ahd_aic790X_setup(ahd)); 969 } 970 971 static int 972 ahd_aic7902_setup(struct ahd_softc *ahd) 973 { 974 ahd->chip = AHD_AIC7902; 975 ahd->features = AHD_AIC7902_FE; 976 return (ahd_aic790X_setup(ahd)); 977 } 978 979 static int 980 ahd_aic790X_setup(struct ahd_softc *ahd) 981 { 982 aic_dev_softc_t pci; 983 u_int rev; 984 985 pci = ahd->dev_softc; 986 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 987 if (rev < ID_AIC7902_PCI_REV_A4) { 988 printf("%s: Unable to attach to unsupported chip revision %d\n", 989 ahd_name(ahd), rev); 990 aic_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2); 991 return (ENXIO); 992 } 993 ahd->channel = aic_get_pci_function(pci) + 'A'; 994 if (rev < ID_AIC7902_PCI_REV_B0) { 995 /* 996 * Enable A series workarounds. 997 */ 998 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG 999 | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG 1000 | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG 1001 | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG 1002 | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG 1003 | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG 1004 | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG 1005 | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG 1006 | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG 1007 | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG 1008 | AHD_FAINT_LED_BUG; 1009 1010 /* 1011 * IO Cell parameter setup. 1012 */ 1013 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1014 1015 if ((ahd->flags & AHD_HP_BOARD) == 0) 1016 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); 1017 } else { 1018 u_int devconfig1; 1019 1020 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS 1021 | AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY; 1022 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; 1023 1024 /* 1025 * Some issues have been resolved in the 7901B. 1026 */ 1027 if ((ahd->features & AHD_MULTI_FUNC) != 0) 1028 ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG 1029 | AHD_BUSFREEREV_BUG; 1030 1031 /* 1032 * IO Cell parameter setup. 1033 */ 1034 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); 1035 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); 1036 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); 1037 1038 /* 1039 * Set the PREQDIS bit for H2B which disables some workaround 1040 * that doesn't work on regular PCI busses. 1041 * XXX - Find out exactly what this does from the hardware 1042 * folks! 1043 */ 1044 devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 1045 aic_pci_write_config(pci, DEVCONFIG1, 1046 devconfig1|PREQDIS, /*bytes*/1); 1047 devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); 1048 } 1049 1050 return (0); 1051 } 1052