1/*- 2 * Aic79xx register and scratch ram definitions. 3 * 4 * Copyright (c) 1994-2001, 2004 Justin T. Gibbs. 5 * Copyright (c) 2000-2002 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 */ 40VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#76 $" 41 42/* 43 * This file is processed by the aic7xxx_asm utility for use in assembling 44 * firmware for the aic79xx family of SCSI host adapters as well as to generate 45 * a C header file for use in the kernel portion of the Aic79xx driver. 46 */ 47 48/* Register window Modes */ 49#define M_DFF0 0 50#define M_DFF1 1 51#define M_CCHAN 2 52#define M_SCSI 3 53#define M_CFG 4 54#define M_DST_SHIFT 4 55 56#define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT)) 57#define SET_MODE(src, dst) \ 58 SET_SRC_MODE src; \ 59 SET_DST_MODE dst; \ 60 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 61 mvi MK_MODE(src, dst) call set_mode_work_around; \ 62 } else { \ 63 mvi MODE_PTR, MK_MODE(src, dst); \ 64 } 65 66#define RESTORE_MODE(mode) \ 67 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ 68 mov mode call set_mode_work_around; \ 69 } else { \ 70 mov MODE_PTR, mode; \ 71 } 72 73#define SET_SEQINTCODE(code) \ 74 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { \ 75 mvi code call set_seqint_work_around; \ 76 } else { \ 77 mvi SEQINTCODE, code; \ 78 } 79 80/* 81 * Mode Pointer 82 * Controls which of the 5, 512byte, address spaces should be used 83 * as the source and destination of any register accesses in our 84 * register window. 85 */ 86register MODE_PTR { 87 address 0x000 88 access_mode RW 89 field DST_MODE 0x70 90 field SRC_MODE 0x07 91 mode_pointer 92} 93 94const SRC_MODE_SHIFT 0 95const DST_MODE_SHIFT 4 96 97/* 98 * Host Interrupt Status 99 */ 100register INTSTAT { 101 address 0x001 102 access_mode RW 103 field HWERRINT 0x80 104 field BRKADRINT 0x40 105 field SWTMINT 0x20 106 field PCIINT 0x10 107 field SCSIINT 0x08 108 field SEQINT 0x04 109 field CMDCMPLT 0x02 110 field SPLTINT 0x01 111 mask INT_PEND 0xFF 112} 113 114/* 115 * Sequencer Interrupt Code 116 */ 117register SEQINTCODE { 118 address 0x002 119 access_mode RW 120 field { 121 NO_SEQINT, /* No seqint pending. */ 122 BAD_PHASE, /* unknown scsi bus phase */ 123 SEND_REJECT, /* sending a message reject */ 124 PROTO_VIOLATION, /* Protocol Violation */ 125 NO_MATCH, /* no cmd match for reconnect */ 126 IGN_WIDE_RES, /* Complex IGN Wide Res Msg */ 127 PDATA_REINIT, /* 128 * Returned to data phase 129 * that requires data 130 * transfer pointers to be 131 * recalculated from the 132 * transfer residual. 133 */ 134 HOST_MSG_LOOP, /* 135 * The bus is ready for the 136 * host to perform another 137 * message transaction. This 138 * mechanism is used for things 139 * like sync/wide negotiation 140 * that require a kernel based 141 * message state engine. 142 */ 143 BAD_STATUS, /* Bad status from target */ 144 DATA_OVERRUN, /* 145 * Target attempted to write 146 * beyond the bounds of its 147 * command. 148 */ 149 MKMSG_FAILED, /* 150 * Target completed command 151 * without honoring our ATN 152 * request to issue a message. 153 */ 154 MISSED_BUSFREE, /* 155 * The sequencer never saw 156 * the bus go free after 157 * either a command complete 158 * or disconnect message. 159 */ 160 DUMP_CARD_STATE, 161 ILLEGAL_PHASE, 162 INVALID_SEQINT, 163 CFG4ISTAT_INTR, 164 STATUS_OVERRUN, 165 CFG4OVERRUN, 166 ENTERING_NONPACK, 167 TASKMGMT_FUNC_COMPLETE, /* 168 * Task management function 169 * request completed with 170 * an expected busfree. 171 */ 172 TASKMGMT_CMD_CMPLT_OKAY, /* 173 * A command with a non-zero 174 * task management function 175 * has completed via the normal 176 * command completion method 177 * for commands with a zero 178 * task management function. 179 * This happens when an attempt 180 * to abort a command loses 181 * the race for the command to 182 * complete normally. 183 */ 184 TRACEPOINT0, 185 TRACEPOINT1, 186 TRACEPOINT2, 187 TRACEPOINT3, 188 SAW_HWERR, 189 BAD_SCB_STATUS 190 } 191} 192 193/* 194 * Clear Host Interrupt 195 */ 196register CLRINT { 197 address 0x003 198 access_mode WO 199 field CLRHWERRINT 0x80 /* Rev B or greater */ 200 field CLRBRKADRINT 0x40 201 field CLRSWTMINT 0x20 202 field CLRPCIINT 0x10 203 field CLRSCSIINT 0x08 204 field CLRSEQINT 0x04 205 field CLRCMDINT 0x02 206 field CLRSPLTINT 0x01 207} 208 209/* 210 * Error Register 211 */ 212register ERROR { 213 address 0x004 214 access_mode RO 215 field CIOPARERR 0x80 216 field CIOACCESFAIL 0x40 /* Rev B or greater */ 217 field MPARERR 0x20 218 field DPARERR 0x10 219 field SQPARERR 0x08 220 field ILLOPCODE 0x04 221 field DSCTMOUT 0x02 222} 223 224/* 225 * Clear Error 226 */ 227register CLRERR { 228 address 0x004 229 access_mode WO 230 field CLRCIOPARERR 0x80 231 field CLRCIOACCESFAIL 0x40 /* Rev B or greater */ 232 field CLRMPARERR 0x20 233 field CLRDPARERR 0x10 234 field CLRSQPARERR 0x08 235 field CLRILLOPCODE 0x04 236 field CLRDSCTMOUT 0x02 237} 238 239/* 240 * Host Control Register 241 * Overall host control of the device. 242 */ 243register HCNTRL { 244 address 0x005 245 access_mode RW 246 field SEQ_RESET 0x80 /* Rev B or greater */ 247 field POWRDN 0x40 248 field SWINT 0x10 249 field SWTIMER_START_B 0x08 /* Rev B or greater */ 250 field PAUSE 0x04 251 field INTEN 0x02 252 field CHIPRST 0x01 253 field CHIPRSTACK 0x01 254} 255 256/* 257 * Host New SCB Queue Offset 258 */ 259register HNSCB_QOFF { 260 address 0x006 261 access_mode RW 262 size 2 263} 264 265/* 266 * Host Empty SCB Queue Offset 267 */ 268register HESCB_QOFF { 269 address 0x008 270 access_mode RW 271} 272 273/* 274 * Host Mailbox 275 */ 276register HS_MAILBOX { 277 address 0x00B 278 access_mode RW 279 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ 280 mask ENINT_COALESCE 0x40 /* Perform interrupt coalescing */ 281} 282 283/* 284 * Sequencer Interrupt Status 285 */ 286register SEQINTSTAT { 287 address 0x00C 288 access_mode RO 289 field SEQ_SWTMRTO 0x10 290 field SEQ_SEQINT 0x08 291 field SEQ_SCSIINT 0x04 292 field SEQ_PCIINT 0x02 293 field SEQ_SPLTINT 0x01 294} 295 296/* 297 * Clear SEQ Interrupt 298 */ 299register CLRSEQINTSTAT { 300 address 0x00C 301 access_mode WO 302 field CLRSEQ_SWTMRTO 0x10 303 field CLRSEQ_SEQINT 0x08 304 field CLRSEQ_SCSIINT 0x04 305 field CLRSEQ_PCIINT 0x02 306 field CLRSEQ_SPLTINT 0x01 307} 308 309/* 310 * Software Timer 311 */ 312register SWTIMER { 313 address 0x00E 314 access_mode RW 315 size 2 316} 317 318/* 319 * SEQ New SCB Queue Offset 320 */ 321register SNSCB_QOFF { 322 address 0x010 323 access_mode RW 324 size 2 325 modes M_CCHAN 326} 327 328/* 329 * SEQ Empty SCB Queue Offset 330 */ 331register SESCB_QOFF { 332 address 0x012 333 access_mode RW 334 modes M_CCHAN 335} 336 337/* 338 * SEQ Done SCB Queue Offset 339 */ 340register SDSCB_QOFF { 341 address 0x014 342 access_mode RW 343 modes M_CCHAN 344 size 2 345} 346 347/* 348 * Queue Offset Control & Status 349 */ 350register QOFF_CTLSTA { 351 address 0x016 352 access_mode RW 353 modes M_CCHAN 354 field EMPTY_SCB_AVAIL 0x80 355 field NEW_SCB_AVAIL 0x40 356 field SDSCB_ROLLOVR 0x20 357 field HS_MAILBOX_ACT 0x10 358 field SCB_QSIZE 0x0F { 359 SCB_QSIZE_4, 360 SCB_QSIZE_8, 361 SCB_QSIZE_16, 362 SCB_QSIZE_32, 363 SCB_QSIZE_64, 364 SCB_QSIZE_128, 365 SCB_QSIZE_256, 366 SCB_QSIZE_512, 367 SCB_QSIZE_1024, 368 SCB_QSIZE_2048, 369 SCB_QSIZE_4096, 370 SCB_QSIZE_8192, 371 SCB_QSIZE_16384 372 } 373} 374 375/* 376 * Interrupt Control 377 */ 378register INTCTL { 379 address 0x018 380 access_mode RW 381 field SWTMINTMASK 0x80 382 field SWTMINTEN 0x40 383 field SWTIMER_START 0x20 384 field AUTOCLRCMDINT 0x10 385 field PCIINTEN 0x08 386 field SCSIINTEN 0x04 387 field SEQINTEN 0x02 388 field SPLTINTEN 0x01 389} 390 391/* 392 * Data FIFO Control 393 */ 394register DFCNTRL { 395 address 0x019 396 access_mode RW 397 modes M_DFF0, M_DFF1 398 field PRELOADEN 0x80 399 field SCSIENWRDIS 0x40 /* Rev B only. */ 400 field SCSIEN 0x20 401 field SCSIENACK 0x20 402 field HDMAEN 0x08 403 field HDMAENACK 0x08 404 field DIRECTION 0x04 405 field DIRECTIONACK 0x04 406 field FIFOFLUSH 0x02 407 field FIFOFLUSHACK 0x02 408 field DIRECTIONEN 0x01 409} 410 411/* 412 * Device Space Command 0 413 */ 414register DSCOMMAND0 { 415 address 0x019 416 access_mode RW 417 modes M_CFG 418 field CACHETHEN 0x80 /* Cache Threshold enable */ 419 field DPARCKEN 0x40 /* Data Parity Check Enable */ 420 field MPARCKEN 0x20 /* Memory Parity Check Enable */ 421 field EXTREQLCK 0x10 /* External Request Lock */ 422 field DISABLE_TWATE 0x02 /* Rev B or greater */ 423 field CIOPARCKEN 0x01 /* Internal bus parity error enable */ 424} 425 426/* 427 * Data FIFO Status 428 */ 429register DFSTATUS { 430 address 0x01A 431 access_mode RO 432 modes M_DFF0, M_DFF1 433 field PRELOAD_AVAIL 0x80 434 field PKT_PRELOAD_AVAIL 0x40 435 field MREQPEND 0x10 436 field HDONE 0x08 437 field DFTHRESH 0x04 438 field FIFOFULL 0x02 439 field FIFOEMP 0x01 440} 441 442/* 443 * S/G Cache Pointer 444 */ 445register SG_CACHE_PRE { 446 address 0x01B 447 access_mode WO 448 modes M_DFF0, M_DFF1 449 field SG_ADDR_MASK 0xf8 450 field ODD_SEG 0x04 451 field LAST_SEG 0x02 452} 453 454register SG_CACHE_SHADOW { 455 address 0x01B 456 access_mode RO 457 modes M_DFF0, M_DFF1 458 field SG_ADDR_MASK 0xf8 459 field ODD_SEG 0x04 460 field LAST_SEG 0x02 461 field LAST_SEG_DONE 0x01 462} 463 464/* 465 * Arbiter Control 466 */ 467register ARBCTL { 468 address 0x01B 469 access_mode RW 470 modes M_CFG 471 field RESET_HARB 0x80 472 field RETRY_SWEN 0x08 473 field USE_TIME 0x07 474} 475 476/* 477 * Data Channel Host Address 478 */ 479register HADDR { 480 address 0x070 481 access_mode RW 482 size 8 483 modes M_DFF0, M_DFF1 484} 485 486/* 487 * Host Overlay DMA Address 488 */ 489register HODMAADR { 490 address 0x070 491 access_mode RW 492 size 8 493 modes M_SCSI 494} 495 496/* 497 * PCI PLL Delay. 498 */ 499register PLLDELAY { 500 address 0x070 501 access_mode RW 502 size 1 503 modes M_CFG 504 field SPLIT_DROP_REQ 0x80 505} 506 507/* 508 * Data Channel Host Count 509 */ 510register HCNT { 511 address 0x078 512 access_mode RW 513 size 3 514 modes M_DFF0, M_DFF1 515} 516 517/* 518 * Host Overlay DMA Count 519 */ 520register HODMACNT { 521 address 0x078 522 access_mode RW 523 size 2 524 modes M_SCSI 525} 526 527/* 528 * Host Overlay DMA Enable 529 */ 530register HODMAEN { 531 address 0x07A 532 access_mode RW 533 modes M_SCSI 534} 535 536/* 537 * Scatter/Gather Host Address 538 */ 539register SGHADDR { 540 address 0x07C 541 access_mode RW 542 size 8 543 modes M_DFF0, M_DFF1 544} 545 546/* 547 * SCB Host Address 548 */ 549register SCBHADDR { 550 address 0x07C 551 access_mode RW 552 size 8 553 modes M_CCHAN 554} 555 556/* 557 * Scatter/Gather Host Count 558 */ 559register SGHCNT { 560 address 0x084 561 access_mode RW 562 modes M_DFF0, M_DFF1 563} 564 565/* 566 * SCB Host Count 567 */ 568register SCBHCNT { 569 address 0x084 570 access_mode RW 571 modes M_CCHAN 572} 573 574/* 575 * Data FIFO Threshold 576 */ 577register DFF_THRSH { 578 address 0x088 579 access_mode RW 580 modes M_CFG 581 field WR_DFTHRSH 0x70 { 582 WR_DFTHRSH_MIN, 583 WR_DFTHRSH_25, 584 WR_DFTHRSH_50, 585 WR_DFTHRSH_63, 586 WR_DFTHRSH_75, 587 WR_DFTHRSH_85, 588 WR_DFTHRSH_90, 589 WR_DFTHRSH_MAX 590 } 591 field RD_DFTHRSH 0x07 { 592 RD_DFTHRSH_MIN, 593 RD_DFTHRSH_25, 594 RD_DFTHRSH_50, 595 RD_DFTHRSH_63, 596 RD_DFTHRSH_75, 597 RD_DFTHRSH_85, 598 RD_DFTHRSH_90, 599 RD_DFTHRSH_MAX 600 } 601} 602 603/* 604 * ROM Address 605 */ 606register ROMADDR { 607 address 0x08A 608 access_mode RW 609 size 3 610} 611 612/* 613 * ROM Control 614 */ 615register ROMCNTRL { 616 address 0x08D 617 access_mode RW 618 field ROMOP 0xE0 619 field ROMSPD 0x18 620 field REPEAT 0x02 621 field RDY 0x01 622} 623 624/* 625 * ROM Data 626 */ 627register ROMDATA { 628 address 0x08E 629 access_mode RW 630} 631 632/* 633 * Data Channel Receive Message 0 634 */ 635register DCHRXMSG0 { 636 address 0x090 637 access_mode RO 638 modes M_DFF0, M_DFF1 639 field CDNUM 0xF8 640 field CFNUM 0x07 641} 642 643/* 644 * CMC Receive Message 0 645 */ 646register CMCRXMSG0 { 647 address 0x090 648 access_mode RO 649 modes M_CCHAN 650 field CDNUM 0xF8 651 field CFNUM 0x07 652} 653 654/* 655 * Overlay Receive Message 0 656 */ 657register OVLYRXMSG0 { 658 address 0x090 659 access_mode RO 660 modes M_SCSI 661 field CDNUM 0xF8 662 field CFNUM 0x07 663} 664 665/* 666 * Relaxed Order Enable 667 */ 668register ROENABLE { 669 address 0x090 670 access_mode RW 671 modes M_CFG 672 field MSIROEN 0x20 673 field OVLYROEN 0x10 674 field CMCROEN 0x08 675 field SGROEN 0x04 676 field DCH1ROEN 0x02 677 field DCH0ROEN 0x01 678} 679 680/* 681 * Data Channel Receive Message 1 682 */ 683register DCHRXMSG1 { 684 address 0x091 685 access_mode RO 686 modes M_DFF0, M_DFF1 687 field CBNUM 0xFF 688} 689 690/* 691 * CMC Receive Message 1 692 */ 693register CMCRXMSG1 { 694 address 0x091 695 access_mode RO 696 modes M_CCHAN 697 field CBNUM 0xFF 698} 699 700/* 701 * Overlay Receive Message 1 702 */ 703register OVLYRXMSG1 { 704 address 0x091 705 access_mode RO 706 modes M_SCSI 707 field CBNUM 0xFF 708} 709 710/* 711 * No Snoop Enable 712 */ 713register NSENABLE { 714 address 0x091 715 access_mode RW 716 modes M_CFG 717 field MSINSEN 0x20 718 field OVLYNSEN 0x10 719 field CMCNSEN 0x08 720 field SGNSEN 0x04 721 field DCH1NSEN 0x02 722 field DCH0NSEN 0x01 723} 724 725/* 726 * Data Channel Receive Message 2 727 */ 728register DCHRXMSG2 { 729 address 0x092 730 access_mode RO 731 modes M_DFF0, M_DFF1 732 field MINDEX 0xFF 733} 734 735/* 736 * CMC Receive Message 2 737 */ 738register CMCRXMSG2 { 739 address 0x092 740 access_mode RO 741 modes M_CCHAN 742 field MINDEX 0xFF 743} 744 745/* 746 * Overlay Receive Message 2 747 */ 748register OVLYRXMSG2 { 749 address 0x092 750 access_mode RO 751 modes M_SCSI 752 field MINDEX 0xFF 753} 754 755/* 756 * Outstanding Split Transactions 757 */ 758register OST { 759 address 0x092 760 access_mode RW 761 modes M_CFG 762} 763 764/* 765 * Data Channel Receive Message 3 766 */ 767register DCHRXMSG3 { 768 address 0x093 769 access_mode RO 770 modes M_DFF0, M_DFF1 771 field MCLASS 0x0F 772} 773 774/* 775 * CMC Receive Message 3 776 */ 777register CMCRXMSG3 { 778 address 0x093 779 access_mode RO 780 modes M_CCHAN 781 field MCLASS 0x0F 782} 783 784/* 785 * Overlay Receive Message 3 786 */ 787register OVLYRXMSG3 { 788 address 0x093 789 access_mode RO 790 modes M_SCSI 791 field MCLASS 0x0F 792} 793 794/* 795 * PCI-X Control 796 */ 797register PCIXCTL { 798 address 0x093 799 access_mode RW 800 modes M_CFG 801 field SERRPULSE 0x80 802 field UNEXPSCIEN 0x20 803 field SPLTSMADIS 0x10 804 field SPLTSTADIS 0x08 805 field SRSPDPEEN 0x04 806 field TSCSERREN 0x02 807 field CMPABCDIS 0x01 808} 809 810/* 811 * CMC Sequencer Byte Count 812 */ 813register CMCSEQBCNT { 814 address 0x094 815 access_mode RO 816 modes M_CCHAN 817} 818 819/* 820 * Overlay Sequencer Byte Count 821 */ 822register OVLYSEQBCNT { 823 address 0x094 824 access_mode RO 825 modes M_SCSI 826} 827 828/* 829 * Data Channel Sequencer Byte Count 830 */ 831register DCHSEQBCNT { 832 address 0x094 833 access_mode RO 834 size 2 835 modes M_DFF0, M_DFF1 836} 837 838/* 839 * Data Channel Split Status 0 840 */ 841register DCHSPLTSTAT0 { 842 address 0x096 843 access_mode RW 844 modes M_DFF0, M_DFF1 845 field STAETERM 0x80 846 field SCBCERR 0x40 847 field SCADERR 0x20 848 field SCDATBUCKET 0x10 849 field CNTNOTCMPLT 0x08 850 field RXOVRUN 0x04 851 field RXSCEMSG 0x02 852 field RXSPLTRSP 0x01 853} 854 855/* 856 * CMC Split Status 0 857 */ 858register CMCSPLTSTAT0 { 859 address 0x096 860 access_mode RW 861 modes M_CCHAN 862 field STAETERM 0x80 863 field SCBCERR 0x40 864 field SCADERR 0x20 865 field SCDATBUCKET 0x10 866 field CNTNOTCMPLT 0x08 867 field RXOVRUN 0x04 868 field RXSCEMSG 0x02 869 field RXSPLTRSP 0x01 870} 871 872/* 873 * Overlay Split Status 0 874 */ 875register OVLYSPLTSTAT0 { 876 address 0x096 877 access_mode RW 878 modes M_SCSI 879 field STAETERM 0x80 880 field SCBCERR 0x40 881 field SCADERR 0x20 882 field SCDATBUCKET 0x10 883 field CNTNOTCMPLT 0x08 884 field RXOVRUN 0x04 885 field RXSCEMSG 0x02 886 field RXSPLTRSP 0x01 887} 888 889/* 890 * Data Channel Split Status 1 891 */ 892register DCHSPLTSTAT1 { 893 address 0x097 894 access_mode RW 895 modes M_DFF0, M_DFF1 896 field RXDATABUCKET 0x01 897} 898 899/* 900 * CMC Split Status 1 901 */ 902register CMCSPLTSTAT1 { 903 address 0x097 904 access_mode RW 905 modes M_CCHAN 906 field RXDATABUCKET 0x01 907} 908 909/* 910 * Overlay Split Status 1 911 */ 912register OVLYSPLTSTAT1 { 913 address 0x097 914 access_mode RW 915 modes M_SCSI 916 field RXDATABUCKET 0x01 917} 918 919/* 920 * S/G Receive Message 0 921 */ 922register SGRXMSG0 { 923 address 0x098 924 access_mode RO 925 modes M_DFF0, M_DFF1 926 field CDNUM 0xF8 927 field CFNUM 0x07 928} 929 930/* 931 * S/G Receive Message 1 932 */ 933register SGRXMSG1 { 934 address 0x099 935 access_mode RO 936 modes M_DFF0, M_DFF1 937 field CBNUM 0xFF 938} 939 940/* 941 * S/G Receive Message 2 942 */ 943register SGRXMSG2 { 944 address 0x09A 945 access_mode RO 946 modes M_DFF0, M_DFF1 947 field MINDEX 0xFF 948} 949 950/* 951 * S/G Receive Message 3 952 */ 953register SGRXMSG3 { 954 address 0x09B 955 access_mode RO 956 modes M_DFF0, M_DFF1 957 field MCLASS 0x0F 958} 959 960/* 961 * Slave Split Out Address 0 962 */ 963register SLVSPLTOUTADR0 { 964 address 0x098 965 access_mode RO 966 modes M_SCSI 967 field LOWER_ADDR 0x7F 968} 969 970/* 971 * Slave Split Out Address 1 972 */ 973register SLVSPLTOUTADR1 { 974 address 0x099 975 access_mode RO 976 modes M_SCSI 977 field REQ_DNUM 0xF8 978 field REQ_FNUM 0x07 979} 980 981/* 982 * Slave Split Out Address 2 983 */ 984register SLVSPLTOUTADR2 { 985 address 0x09A 986 access_mode RO 987 modes M_SCSI 988 field REQ_BNUM 0xFF 989} 990 991/* 992 * Slave Split Out Address 3 993 */ 994register SLVSPLTOUTADR3 { 995 address 0x09B 996 access_mode RO 997 modes M_SCSI 998 field RLXORD 020 999 field TAG_NUM 0x1F 1000} 1001 1002/* 1003 * SG Sequencer Byte Count 1004 */ 1005register SGSEQBCNT { 1006 address 0x09C 1007 access_mode RO 1008 modes M_DFF0, M_DFF1 1009} 1010 1011/* 1012 * Slave Split Out Attribute 0 1013 */ 1014register SLVSPLTOUTATTR0 { 1015 address 0x09C 1016 access_mode RO 1017 modes M_SCSI 1018 field LOWER_BCNT 0xFF 1019} 1020 1021/* 1022 * Slave Split Out Attribute 1 1023 */ 1024register SLVSPLTOUTATTR1 { 1025 address 0x09D 1026 access_mode RO 1027 modes M_SCSI 1028 field CMPLT_DNUM 0xF8 1029 field CMPLT_FNUM 0x07 1030} 1031 1032/* 1033 * Slave Split Out Attribute 2 1034 */ 1035register SLVSPLTOUTATTR2 { 1036 address 0x09E 1037 access_mode RO 1038 size 2 1039 modes M_SCSI 1040 field CMPLT_BNUM 0xFF 1041} 1042/* 1043 * S/G Split Status 0 1044 */ 1045register SGSPLTSTAT0 { 1046 address 0x09E 1047 access_mode RW 1048 modes M_DFF0, M_DFF1 1049 field STAETERM 0x80 1050 field SCBCERR 0x40 1051 field SCADERR 0x20 1052 field SCDATBUCKET 0x10 1053 field CNTNOTCMPLT 0x08 1054 field RXOVRUN 0x04 1055 field RXSCEMSG 0x02 1056 field RXSPLTRSP 0x01 1057} 1058 1059/* 1060 * S/G Split Status 1 1061 */ 1062register SGSPLTSTAT1 { 1063 address 0x09F 1064 access_mode RW 1065 modes M_DFF0, M_DFF1 1066 field RXDATABUCKET 0x01 1067} 1068 1069/* 1070 * Special Function 1071 */ 1072register SFUNCT { 1073 address 0x09f 1074 access_mode RW 1075 modes M_CFG 1076 field TEST_GROUP 0xF0 1077 field TEST_NUM 0x0F 1078} 1079 1080/* 1081 * Data FIFO 0 PCI Status 1082 */ 1083register DF0PCISTAT { 1084 address 0x0A0 1085 access_mode RW 1086 modes M_CFG 1087 field DPE 0x80 1088 field SSE 0x40 1089 field RMA 0x20 1090 field RTA 0x10 1091 field SCAAPERR 0x08 1092 field RDPERR 0x04 1093 field TWATERR 0x02 1094 field DPR 0x01 1095} 1096 1097/* 1098 * Data FIFO 1 PCI Status 1099 */ 1100register DF1PCISTAT { 1101 address 0x0A1 1102 access_mode RW 1103 modes M_CFG 1104 field DPE 0x80 1105 field SSE 0x40 1106 field RMA 0x20 1107 field RTA 0x10 1108 field SCAAPERR 0x08 1109 field RDPERR 0x04 1110 field TWATERR 0x02 1111 field DPR 0x01 1112} 1113 1114/* 1115 * S/G PCI Status 1116 */ 1117register SGPCISTAT { 1118 address 0x0A2 1119 access_mode RW 1120 modes M_CFG 1121 field DPE 0x80 1122 field SSE 0x40 1123 field RMA 0x20 1124 field RTA 0x10 1125 field SCAAPERR 0x08 1126 field RDPERR 0x04 1127 field DPR 0x01 1128} 1129 1130/* 1131 * CMC PCI Status 1132 */ 1133register CMCPCISTAT { 1134 address 0x0A3 1135 access_mode RW 1136 modes M_CFG 1137 field DPE 0x80 1138 field SSE 0x40 1139 field RMA 0x20 1140 field RTA 0x10 1141 field SCAAPERR 0x08 1142 field RDPERR 0x04 1143 field TWATERR 0x02 1144 field DPR 0x01 1145} 1146 1147/* 1148 * Overlay PCI Status 1149 */ 1150register OVLYPCISTAT { 1151 address 0x0A4 1152 access_mode RW 1153 modes M_CFG 1154 field DPE 0x80 1155 field SSE 0x40 1156 field RMA 0x20 1157 field RTA 0x10 1158 field SCAAPERR 0x08 1159 field RDPERR 0x04 1160 field DPR 0x01 1161} 1162 1163/* 1164 * PCI Status for MSI Master DMA Transfer 1165 */ 1166register MSIPCISTAT { 1167 address 0x0A6 1168 access_mode RW 1169 modes M_CFG 1170 field SSE 0x40 1171 field RMA 0x20 1172 field RTA 0x10 1173 field CLRPENDMSI 0x08 1174 field TWATERR 0x02 1175 field DPR 0x01 1176} 1177 1178/* 1179 * PCI Status for Target 1180 */ 1181register TARGPCISTAT { 1182 address 0x0A7 1183 access_mode RW 1184 modes M_CFG 1185 field DPE 0x80 1186 field SSE 0x40 1187 field STA 0x08 1188 field TWATERR 0x02 1189} 1190 1191/* 1192 * LQ Packet In 1193 * The last LQ Packet received 1194 */ 1195register LQIN { 1196 address 0x020 1197 access_mode RW 1198 size 20 1199 modes M_DFF0, M_DFF1, M_SCSI 1200} 1201 1202/* 1203 * SCB Type Pointer 1204 * SCB offset for Target Mode SCB type information 1205 */ 1206register TYPEPTR { 1207 address 0x020 1208 access_mode RW 1209 modes M_CFG 1210} 1211 1212/* 1213 * Queue Tag Pointer 1214 * SCB offset to the Two Byte tag identifier used for target mode. 1215 */ 1216register TAGPTR { 1217 address 0x021 1218 access_mode RW 1219 modes M_CFG 1220} 1221 1222/* 1223 * Logical Unit Number Pointer 1224 * SCB offset to the LSB (little endian) of the lun field. 1225 */ 1226register LUNPTR { 1227 address 0x022 1228 access_mode RW 1229 modes M_CFG 1230} 1231 1232/* 1233 * Data Length Pointer 1234 * SCB offset for the 4 byte data length field in target mode. 1235 */ 1236register DATALENPTR { 1237 address 0x023 1238 access_mode RW 1239 modes M_CFG 1240} 1241 1242/* 1243 * Status Length Pointer 1244 * SCB offset to the two byte status field in target SCBs. 1245 */ 1246register STATLENPTR { 1247 address 0x024 1248 access_mode RW 1249 modes M_CFG 1250} 1251 1252/* 1253 * Command Length Pointer 1254 * Scb offset for the CDB length field in initiator SCBs. 1255 */ 1256register CMDLENPTR { 1257 address 0x025 1258 access_mode RW 1259 modes M_CFG 1260} 1261 1262/* 1263 * Task Attribute Pointer 1264 * Scb offset for the byte field specifying the attribute byte 1265 * to be used in command packets. 1266 */ 1267register ATTRPTR { 1268 address 0x026 1269 access_mode RW 1270 modes M_CFG 1271} 1272 1273/* 1274 * Task Management Flags Pointer 1275 * Scb offset for the byte field specifying the attribute flags 1276 * byte to be used in command packets. 1277 */ 1278register FLAGPTR { 1279 address 0x027 1280 access_mode RW 1281 modes M_CFG 1282} 1283 1284/* 1285 * Command Pointer 1286 * Scb offset for the first byte in the CDB for initiator SCBs. 1287 */ 1288register CMDPTR { 1289 address 0x028 1290 access_mode RW 1291 modes M_CFG 1292} 1293 1294/* 1295 * Queue Next Pointer 1296 * Scb offset for the 2 byte "next scb link". 1297 */ 1298register QNEXTPTR { 1299 address 0x029 1300 access_mode RW 1301 modes M_CFG 1302} 1303 1304/* 1305 * SCSI ID Pointer 1306 * Scb offset to the value to place in the SCSIID register 1307 * during target mode connections. 1308 */ 1309register IDPTR { 1310 address 0x02A 1311 access_mode RW 1312 modes M_CFG 1313} 1314 1315/* 1316 * Command Aborted Byte Pointer 1317 * Offset to the SCB flags field that includes the 1318 * "SCB aborted" status bit. 1319 */ 1320register ABRTBYTEPTR { 1321 address 0x02B 1322 access_mode RW 1323 modes M_CFG 1324} 1325 1326/* 1327 * Command Aborted Bit Pointer 1328 * Bit offset in the SCB flags field for "SCB aborted" status. 1329 */ 1330register ABRTBITPTR { 1331 address 0x02C 1332 access_mode RW 1333 modes M_CFG 1334} 1335 1336/* 1337 * Rev B or greater. 1338 */ 1339register MAXCMDBYTES { 1340 address 0x02D 1341 access_mode RW 1342 modes M_CFG 1343} 1344 1345/* 1346 * Rev B or greater. 1347 */ 1348register MAXCMD2RCV { 1349 address 0x02E 1350 access_mode RW 1351 modes M_CFG 1352} 1353 1354/* 1355 * Rev B or greater. 1356 */ 1357register SHORTTHRESH { 1358 address 0x02F 1359 access_mode RW 1360 modes M_CFG 1361} 1362 1363/* 1364 * Logical Unit Number Length 1365 * The length, in bytes, of the SCB lun field. 1366 */ 1367register LUNLEN { 1368 address 0x030 1369 access_mode RW 1370 modes M_CFG 1371 mask ILUNLEN 0x0F 1372 mask TLUNLEN 0xF0 1373} 1374const LUNLEN_SINGLE_LEVEL_LUN 0xF 1375 1376/* 1377 * CDB Limit 1378 * The size, in bytes, of the embedded CDB field in initator SCBs. 1379 */ 1380register CDBLIMIT { 1381 address 0x031 1382 access_mode RW 1383 modes M_CFG 1384} 1385 1386/* 1387 * Maximum Commands 1388 * The maximum number of commands to issue during a 1389 * single packetized connection. 1390 */ 1391register MAXCMD { 1392 address 0x032 1393 access_mode RW 1394 modes M_CFG 1395} 1396 1397/* 1398 * Maximum Command Counter 1399 * The number of commands already sent during this connection 1400 */ 1401register MAXCMDCNT { 1402 address 0x033 1403 access_mode RW 1404 modes M_CFG 1405} 1406 1407/* 1408 * LQ Packet Reserved Bytes 1409 * The bytes to be sent in the currently reserved fileds 1410 * of all LQ packets. 1411 */ 1412register LQRSVD01 { 1413 address 0x034 1414 access_mode RW 1415 modes M_SCSI 1416} 1417register LQRSVD16 { 1418 address 0x035 1419 access_mode RW 1420 modes M_SCSI 1421} 1422register LQRSVD17 { 1423 address 0x036 1424 access_mode RW 1425 modes M_SCSI 1426} 1427 1428/* 1429 * Command Reserved 0 1430 * The byte to be sent for the reserved byte 0 of 1431 * outgoing command packets. 1432 */ 1433register CMDRSVD0 { 1434 address 0x037 1435 access_mode RW 1436 modes M_CFG 1437} 1438 1439/* 1440 * LQ Manager Control 0 1441 */ 1442register LQCTL0 { 1443 address 0x038 1444 access_mode RW 1445 modes M_CFG 1446 field LQITARGCLT 0xC0 1447 field LQIINITGCLT 0x30 1448 field LQ0TARGCLT 0x0C 1449 field LQ0INITGCLT 0x03 1450} 1451 1452/* 1453 * LQ Manager Control 1 1454 */ 1455register LQCTL1 { 1456 address 0x038 1457 access_mode RW 1458 modes M_DFF0, M_DFF1, M_SCSI 1459 field PCI2PCI 0x04 1460 field SINGLECMD 0x02 1461 field ABORTPENDING 0x01 1462} 1463 1464/* 1465 * LQ Manager Control 2 1466 */ 1467register LQCTL2 { 1468 address 0x039 1469 access_mode RW 1470 modes M_DFF0, M_DFF1, M_SCSI 1471 field LQIRETRY 0x80 1472 field LQICONTINUE 0x40 1473 field LQITOIDLE 0x20 1474 field LQIPAUSE 0x10 1475 field LQORETRY 0x08 1476 field LQOCONTINUE 0x04 1477 field LQOTOIDLE 0x02 1478 field LQOPAUSE 0x01 1479} 1480 1481/* 1482 * SCSI RAM BIST0 1483 */ 1484register SCSBIST0 { 1485 address 0x039 1486 access_mode RW 1487 modes M_CFG 1488 field GSBISTERR 0x40 1489 field GSBISTDONE 0x20 1490 field GSBISTRUN 0x10 1491 field OSBISTERR 0x04 1492 field OSBISTDONE 0x02 1493 field OSBISTRUN 0x01 1494} 1495 1496/* 1497 * SCSI Sequence Control0 1498 */ 1499register SCSISEQ0 { 1500 address 0x03A 1501 access_mode RW 1502 modes M_DFF0, M_DFF1, M_SCSI 1503 field TEMODEO 0x80 1504 field ENSELO 0x40 1505 field ENARBO 0x20 1506 field FORCEBUSFREE 0x10 1507 field SCSIRSTO 0x01 1508} 1509 1510/* 1511 * SCSI RAM BIST 1 1512 */ 1513register SCSBIST1 { 1514 address 0x03A 1515 access_mode RW 1516 modes M_CFG 1517 field NTBISTERR 0x04 1518 field NTBISTDONE 0x02 1519 field NTBISTRUN 0x01 1520} 1521 1522/* 1523 * SCSI Sequence Control 1 1524 */ 1525register SCSISEQ1 { 1526 address 0x03B 1527 access_mode RW 1528 modes M_DFF0, M_DFF1, M_SCSI 1529 field MANUALCTL 0x40 1530 field ENSELI 0x20 1531 field ENRSELI 0x10 1532 field MANUALP 0x0C 1533 field ENAUTOATNP 0x02 1534 field ALTSTIM 0x01 1535} 1536 1537/* 1538 * SCSI Transfer Control 0 1539 */ 1540register SXFRCTL0 { 1541 address 0x03C 1542 access_mode RW 1543 modes M_SCSI 1544 field DFON 0x80 1545 field DFPEXP 0x40 1546 field BIOSCANCELEN 0x10 1547 field SPIOEN 0x08 1548} 1549 1550/* 1551 * SCSI Transfer Control 1 1552 */ 1553register SXFRCTL1 { 1554 address 0x03D 1555 access_mode RW 1556 modes M_SCSI 1557 field BITBUCKET 0x80 1558 field ENSACHK 0x40 1559 field ENSPCHK 0x20 1560 field STIMESEL 0x18 1561 field ENSTIMER 0x04 1562 field ACTNEGEN 0x02 1563 field STPWEN 0x01 1564} 1565 1566/* 1567 * SCSI Transfer Control 2 1568 */ 1569register SXFRCTL2 { 1570 address 0x03E 1571 access_mode RW 1572 modes M_SCSI 1573 field AUTORSTDIS 0x10 1574 field CMDDMAEN 0x08 1575 field ASU 0x07 1576} 1577 1578/* 1579 * SCSI Bus Initiator IDs 1580 * Bitmask of observed initiators on the bus. 1581 */ 1582register BUSINITID { 1583 address 0x03C 1584 access_mode RW 1585 modes M_CFG 1586 size 2 1587} 1588 1589/* 1590 * Data Length Counters 1591 * Packet byte counter. 1592 */ 1593register DLCOUNT { 1594 address 0x03C 1595 access_mode RW 1596 modes M_DFF0, M_DFF1 1597 size 3 1598} 1599 1600/* 1601 * Data FIFO Status 1602 */ 1603register DFFSTAT { 1604 address 0x03F 1605 access_mode RW 1606 modes M_SCSI 1607 field FIFO1FREE 0x20 1608 field FIFO0FREE 0x10 1609 /* 1610 * On the B, this enum only works 1611 * in the read direction. For writes, 1612 * you must use the B version of the 1613 * CURRFIFO_0 definition which is defined 1614 * as a constant outside of this register 1615 * definition to avoid confusing the 1616 * register pretty printing code. 1617 */ 1618 enum CURRFIFO 0x03 { 1619 CURRFIFO_0, 1620 CURRFIFO_1, 1621 CURRFIFO_NONE 0x3 1622 } 1623} 1624 1625const B_CURRFIFO_0 0x2 1626 1627/* 1628 * SCSI Bus Target IDs 1629 * Bitmask of observed targets on the bus. 1630 */ 1631register BUSTARGID { 1632 address 0x03E 1633 access_mode RW 1634 modes M_CFG 1635 size 2 1636} 1637 1638/* 1639 * SCSI Control Signal Out 1640 */ 1641register SCSISIGO { 1642 address 0x040 1643 access_mode RW 1644 modes M_DFF0, M_DFF1, M_SCSI 1645 field CDO 0x80 1646 field IOO 0x40 1647 field MSGO 0x20 1648 field ATNO 0x10 1649 field SELO 0x08 1650 field BSYO 0x04 1651 field REQO 0x02 1652 field ACKO 0x01 1653/* 1654 * Possible phases to write into SCSISIG0 1655 */ 1656 enum PHASE_MASK CDO|IOO|MSGO { 1657 P_DATAOUT 0x0, 1658 P_DATAIN IOO, 1659 P_DATAOUT_DT P_DATAOUT|MSGO, 1660 P_DATAIN_DT P_DATAIN|MSGO, 1661 P_COMMAND CDO, 1662 P_MESGOUT CDO|MSGO, 1663 P_STATUS CDO|IOO, 1664 P_MESGIN CDO|IOO|MSGO 1665 } 1666} 1667 1668register SCSISIGI { 1669 address 0x041 1670 access_mode RO 1671 modes M_DFF0, M_DFF1, M_SCSI 1672 field CDI 0x80 1673 field IOI 0x40 1674 field MSGI 0x20 1675 field ATNI 0x10 1676 field SELI 0x08 1677 field BSYI 0x04 1678 field REQI 0x02 1679 field ACKI 0x01 1680/* 1681 * Possible phases in SCSISIGI 1682 */ 1683 enum PHASE_MASK CDO|IOO|MSGO { 1684 P_DATAOUT 0x0, 1685 P_DATAIN IOO, 1686 P_DATAOUT_DT P_DATAOUT|MSGO, 1687 P_DATAIN_DT P_DATAIN|MSGO, 1688 P_COMMAND CDO, 1689 P_MESGOUT CDO|MSGO, 1690 P_STATUS CDO|IOO, 1691 P_MESGIN CDO|IOO|MSGO 1692 } 1693} 1694 1695/* 1696 * Multiple Target IDs 1697 * Bitmask of ids to respond as a target. 1698 */ 1699register MULTARGID { 1700 address 0x040 1701 access_mode RW 1702 modes M_CFG 1703 size 2 1704} 1705 1706/* 1707 * SCSI Phase 1708 */ 1709register SCSIPHASE { 1710 address 0x042 1711 access_mode RO 1712 modes M_DFF0, M_DFF1, M_SCSI 1713 field STATUS_PHASE 0x20 1714 field COMMAND_PHASE 0x10 1715 field MSG_IN_PHASE 0x08 1716 field MSG_OUT_PHASE 0x04 1717 field DATA_PHASE_MASK 0x03 { 1718 DATA_OUT_PHASE 0x01, 1719 DATA_IN_PHASE 0x02 1720 } 1721} 1722 1723/* 1724 * SCSI Data 0 Image 1725 */ 1726register SCSIDAT0_IMG { 1727 address 0x043 1728 access_mode RW 1729 modes M_DFF0, M_DFF1, M_SCSI 1730} 1731 1732/* 1733 * SCSI Latched Data 1734 */ 1735register SCSIDAT { 1736 address 0x044 1737 access_mode RW 1738 modes M_DFF0, M_DFF1, M_SCSI 1739 size 2 1740} 1741 1742/* 1743 * SCSI Data Bus 1744 */ 1745register SCSIBUS { 1746 address 0x046 1747 access_mode RW 1748 modes M_DFF0, M_DFF1, M_SCSI 1749 size 2 1750} 1751 1752/* 1753 * Target ID In 1754 */ 1755register TARGIDIN { 1756 address 0x048 1757 access_mode RO 1758 modes M_DFF0, M_DFF1, M_SCSI 1759 field CLKOUT 0x80 1760 field TARGID 0x0F 1761} 1762 1763/* 1764 * Selection/Reselection ID 1765 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 1766 * device did not set its own ID. 1767 */ 1768register SELID { 1769 address 0x049 1770 access_mode RW 1771 modes M_DFF0, M_DFF1, M_SCSI 1772 field SELID_MASK 0xf0 1773 field ONEBIT 0x08 1774} 1775 1776/* 1777 * SCSI Block Control 1778 * Controls Bus type and channel selection. SELWIDE allows for the 1779 * coexistence of 8bit and 16bit devices on a wide bus. 1780 */ 1781register SBLKCTL { 1782 address 0x04A 1783 access_mode RW 1784 modes M_DFF0, M_DFF1, M_SCSI 1785 field DIAGLEDEN 0x80 1786 field DIAGLEDON 0x40 1787 field ENAB40 0x08 /* LVD transceiver active */ 1788 field ENAB20 0x04 /* SE/HVD transceiver active */ 1789 field SELWIDE 0x02 1790} 1791 1792/* 1793 * Option Mode 1794 */ 1795register OPTIONMODE { 1796 address 0x04A 1797 access_mode RW 1798 modes M_CFG 1799 field BIOSCANCTL 0x80 1800 field AUTOACKEN 0x40 1801 field BIASCANCTL 0x20 1802 field BUSFREEREV 0x10 1803 field ENDGFORMCHK 0x04 1804 field AUTO_MSGOUT_DE 0x02 1805 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE 1806} 1807 1808/* 1809 * SCSI Status 0 1810 */ 1811register SSTAT0 { 1812 address 0x04B 1813 access_mode RO 1814 modes M_DFF0, M_DFF1, M_SCSI 1815 field TARGET 0x80 /* Board acting as target */ 1816 field SELDO 0x40 /* Selection Done */ 1817 field SELDI 0x20 /* Board has been selected */ 1818 field SELINGO 0x10 /* Selection In Progress */ 1819 field IOERR 0x08 /* LVD Tranceiver mode changed */ 1820 field OVERRUN 0x04 /* SCSI Offset overrun detected */ 1821 field SPIORDY 0x02 /* SCSI PIO Ready */ 1822 field ARBDO 0x01 /* Arbitration Done Out */ 1823} 1824 1825/* 1826 * Clear SCSI Interrupt 0 1827 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. 1828 */ 1829register CLRSINT0 { 1830 address 0x04B 1831 access_mode WO 1832 modes M_DFF0, M_DFF1, M_SCSI 1833 field CLRSELDO 0x40 1834 field CLRSELDI 0x20 1835 field CLRSELINGO 0x10 1836 field CLRIOERR 0x08 1837 field CLROVERRUN 0x04 1838 field CLRSPIORDY 0x02 1839 field CLRARBDO 0x01 1840} 1841 1842/* 1843 * SCSI Interrupt Mode 0 1844 * Setting any bit will enable the corresponding function 1845 * in SIMODE0 to interrupt via the IRQ pin. 1846 */ 1847register SIMODE0 { 1848 address 0x04B 1849 access_mode RW 1850 modes M_CFG 1851 field ENSELDO 0x40 1852 field ENSELDI 0x20 1853 field ENSELINGO 0x10 1854 field ENIOERR 0x08 1855 field ENOVERRUN 0x04 1856 field ENSPIORDY 0x02 1857 field ENARBDO 0x01 1858} 1859 1860/* 1861 * SCSI Status 1 1862 */ 1863register SSTAT1 { 1864 address 0x04C 1865 access_mode RO 1866 modes M_DFF0, M_DFF1, M_SCSI 1867 field SELTO 0x80 1868 field ATNTARG 0x40 1869 field SCSIRSTI 0x20 1870 field PHASEMIS 0x10 1871 field BUSFREE 0x08 1872 field SCSIPERR 0x04 1873 field STRB2FAST 0x02 1874 field REQINIT 0x01 1875} 1876 1877/* 1878 * Clear SCSI Interrupt 1 1879 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 1880 */ 1881register CLRSINT1 { 1882 address 0x04C 1883 access_mode WO 1884 modes M_DFF0, M_DFF1, M_SCSI 1885 field CLRSELTIMEO 0x80 1886 field CLRATNO 0x40 1887 field CLRSCSIRSTI 0x20 1888 field CLRBUSFREE 0x08 1889 field CLRSCSIPERR 0x04 1890 field CLRSTRB2FAST 0x02 1891 field CLRREQINIT 0x01 1892} 1893 1894/* 1895 * SCSI Status 2 1896 */ 1897register SSTAT2 { 1898 address 0x04d 1899 access_mode RO 1900 modes M_DFF0, M_DFF1, M_SCSI 1901 field BUSFREETIME 0xc0 { 1902 BUSFREE_LQO 0x40, 1903 BUSFREE_DFF0 0x80, 1904 BUSFREE_DFF1 0xC0 1905 } 1906 field NONPACKREQ 0x20 1907 field EXP_ACTIVE 0x10 /* SCSI Expander Active */ 1908 field BSYX 0x08 /* Busy Expander */ 1909 field WIDE_RES 0x04 /* Modes 0 and 1 only */ 1910 field SDONE 0x02 /* Modes 0 and 1 only */ 1911 field DMADONE 0x01 /* Modes 0 and 1 only */ 1912} 1913 1914/* 1915 * Clear SCSI Interrupt 2 1916 */ 1917register CLRSINT2 { 1918 address 0x04D 1919 access_mode WO 1920 modes M_DFF0, M_DFF1, M_SCSI 1921 field CLRNONPACKREQ 0x20 1922 field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */ 1923 field CLRSDONE 0x02 /* Modes 0 and 1 only */ 1924 field CLRDMADONE 0x01 /* Modes 0 and 1 only */ 1925} 1926 1927/* 1928 * SCSI Interrupt Mode 2 1929 */ 1930register SIMODE2 { 1931 address 0x04D 1932 access_mode RW 1933 modes M_CFG 1934 field ENWIDE_RES 0x04 1935 field ENSDONE 0x02 1936 field ENDMADONE 0x01 1937} 1938 1939/* 1940 * Physical Error Diagnosis 1941 */ 1942register PERRDIAG { 1943 address 0x04E 1944 access_mode RO 1945 modes M_DFF0, M_DFF1, M_SCSI 1946 field HIZERO 0x80 1947 field HIPERR 0x40 1948 field PREVPHASE 0x20 1949 field PARITYERR 0x10 1950 field AIPERR 0x08 1951 field CRCERR 0x04 1952 field DGFORMERR 0x02 1953 field DTERR 0x01 1954} 1955 1956/* 1957 * LQI Manager Current State 1958 */ 1959register LQISTATE { 1960 address 0x04E 1961 access_mode RO 1962 modes M_CFG 1963} 1964 1965/* 1966 * SCSI Offset Count 1967 */ 1968register SOFFCNT { 1969 address 0x04F 1970 access_mode RO 1971 modes M_DFF0, M_DFF1, M_SCSI 1972} 1973 1974/* 1975 * LQO Manager Current State 1976 */ 1977register LQOSTATE { 1978 address 0x04F 1979 access_mode RO 1980 modes M_CFG 1981} 1982 1983/* 1984 * LQI Manager Status 1985 */ 1986register LQISTAT0 { 1987 address 0x050 1988 access_mode RO 1989 modes M_DFF0, M_DFF1, M_SCSI 1990 field LQIATNQAS 0x20 1991 field LQICRCT1 0x10 1992 field LQICRCT2 0x08 1993 field LQIBADLQT 0x04 1994 field LQIATNLQ 0x02 1995 field LQIATNCMD 0x01 1996} 1997 1998/* 1999 * Clear LQI Interrupts 0 2000 */ 2001register CLRLQIINT0 { 2002 address 0x050 2003 access_mode WO 2004 modes M_DFF0, M_DFF1, M_SCSI 2005 field CLRLQIATNQAS 0x20 2006 field CLRLQICRCT1 0x10 2007 field CLRLQICRCT2 0x08 2008 field CLRLQIBADLQT 0x04 2009 field CLRLQIATNLQ 0x02 2010 field CLRLQIATNCMD 0x01 2011} 2012 2013/* 2014 * LQI Manager Interrupt Mode 0 2015 */ 2016register LQIMODE0 { 2017 address 0x050 2018 access_mode RW 2019 modes M_CFG 2020 field ENLQIATNQASK 0x20 2021 field ENLQICRCT1 0x10 2022 field ENLQICRCT2 0x08 2023 field ENLQIBADLQT 0x04 2024 field ENLQIATNLQ 0x02 2025 field ENLQIATNCMD 0x01 2026} 2027 2028/* 2029 * LQI Manager Status 1 2030 */ 2031register LQISTAT1 { 2032 address 0x051 2033 access_mode RO 2034 modes M_DFF0, M_DFF1, M_SCSI 2035 field LQIPHASE_LQ 0x80 2036 field LQIPHASE_NLQ 0x40 2037 field LQIABORT 0x20 2038 field LQICRCI_LQ 0x10 2039 field LQICRCI_NLQ 0x08 2040 field LQIBADLQI 0x04 2041 field LQIOVERI_LQ 0x02 2042 field LQIOVERI_NLQ 0x01 2043} 2044 2045/* 2046 * Clear LQI Manager Interrupts1 2047 */ 2048register CLRLQIINT1 { 2049 address 0x051 2050 access_mode WO 2051 modes M_DFF0, M_DFF1, M_SCSI 2052 field CLRLQIPHASE_LQ 0x80 2053 field CLRLQIPHASE_NLQ 0x40 2054 field CLRLIQABORT 0x20 2055 field CLRLQICRCI_LQ 0x10 2056 field CLRLQICRCI_NLQ 0x08 2057 field CLRLQIBADLQI 0x04 2058 field CLRLQIOVERI_LQ 0x02 2059 field CLRLQIOVERI_NLQ 0x01 2060} 2061 2062/* 2063 * LQI Manager Interrupt Mode 1 2064 */ 2065register LQIMODE1 { 2066 address 0x051 2067 access_mode RW 2068 modes M_CFG 2069 field ENLQIPHASE_LQ 0x80 /* LQIPHASE1 */ 2070 field ENLQIPHASE_NLQ 0x40 /* LQIPHASE2 */ 2071 field ENLIQABORT 0x20 2072 field ENLQICRCI_LQ 0x10 /* LQICRCI1 */ 2073 field ENLQICRCI_NLQ 0x08 /* LQICRCI2 */ 2074 field ENLQIBADLQI 0x04 2075 field ENLQIOVERI_LQ 0x02 /* LQIOVERI1 */ 2076 field ENLQIOVERI_NLQ 0x01 /* LQIOVERI2 */ 2077} 2078 2079/* 2080 * LQI Manager Status 2 2081 */ 2082register LQISTAT2 { 2083 address 0x052 2084 access_mode RO 2085 modes M_DFF0, M_DFF1, M_SCSI 2086 field PACKETIZED 0x80 2087 field LQIPHASE_OUTPKT 0x40 2088 field LQIWORKONLQ 0x20 2089 field LQIWAITFIFO 0x10 2090 field LQISTOPPKT 0x08 2091 field LQISTOPLQ 0x04 2092 field LQISTOPCMD 0x02 2093 field LQIGSAVAIL 0x01 2094} 2095 2096/* 2097 * SCSI Status 3 2098 */ 2099register SSTAT3 { 2100 address 0x053 2101 access_mode RO 2102 modes M_DFF0, M_DFF1, M_SCSI 2103 field NTRAMPERR 0x02 2104 field OSRAMPERR 0x01 2105} 2106 2107/* 2108 * Clear SCSI Status 3 2109 */ 2110register CLRSINT3 { 2111 address 0x053 2112 access_mode WO 2113 modes M_DFF0, M_DFF1, M_SCSI 2114 field CLRNTRAMPERR 0x02 2115 field CLROSRAMPERR 0x01 2116} 2117 2118/* 2119 * SCSI Interrupt Mode 3 2120 */ 2121register SIMODE3 { 2122 address 0x053 2123 access_mode RW 2124 modes M_CFG 2125 field ENNTRAMPERR 0x02 2126 field ENOSRAMPERR 0x01 2127} 2128 2129/* 2130 * LQO Manager Status 0 2131 */ 2132register LQOSTAT0 { 2133 address 0x054 2134 access_mode RO 2135 modes M_DFF0, M_DFF1, M_SCSI 2136 field LQOTARGSCBPERR 0x10 2137 field LQOSTOPT2 0x08 2138 field LQOATNLQ 0x04 2139 field LQOATNPKT 0x02 2140 field LQOTCRC 0x01 2141} 2142 2143/* 2144 * Clear LQO Manager interrupt 0 2145 */ 2146register CLRLQOINT0 { 2147 address 0x054 2148 access_mode WO 2149 modes M_DFF0, M_DFF1, M_SCSI 2150 field CLRLQOTARGSCBPERR 0x10 2151 field CLRLQOSTOPT2 0x08 2152 field CLRLQOATNLQ 0x04 2153 field CLRLQOATNPKT 0x02 2154 field CLRLQOTCRC 0x01 2155} 2156 2157/* 2158 * LQO Manager Interrupt Mode 0 2159 */ 2160register LQOMODE0 { 2161 address 0x054 2162 access_mode RW 2163 modes M_CFG 2164 field ENLQOTARGSCBPERR 0x10 2165 field ENLQOSTOPT2 0x08 2166 field ENLQOATNLQ 0x04 2167 field ENLQOATNPKT 0x02 2168 field ENLQOTCRC 0x01 2169} 2170 2171/* 2172 * LQO Manager Status 1 2173 */ 2174register LQOSTAT1 { 2175 address 0x055 2176 access_mode RO 2177 modes M_DFF0, M_DFF1, M_SCSI 2178 field LQOINITSCBPERR 0x10 2179 field LQOSTOPI2 0x08 2180 field LQOBADQAS 0x04 2181 field LQOBUSFREE 0x02 2182 field LQOPHACHGINPKT 0x01 2183} 2184 2185/* 2186 * Clear LOQ Interrupt 1 2187 */ 2188register CLRLQOINT1 { 2189 address 0x055 2190 access_mode WO 2191 modes M_DFF0, M_DFF1, M_SCSI 2192 field CLRLQOINITSCBPERR 0x10 2193 field CLRLQOSTOPI2 0x08 2194 field CLRLQOBADQAS 0x04 2195 field CLRLQOBUSFREE 0x02 2196 field CLRLQOPHACHGINPKT 0x01 2197} 2198 2199/* 2200 * LQO Manager Interrupt Mode 1 2201 */ 2202register LQOMODE1 { 2203 address 0x055 2204 access_mode RW 2205 modes M_CFG 2206 field ENLQOINITSCBPERR 0x10 2207 field ENLQOSTOPI2 0x08 2208 field ENLQOBADQAS 0x04 2209 field ENLQOBUSFREE 0x02 2210 field ENLQOPHACHGINPKT 0x01 2211} 2212 2213/* 2214 * LQO Manager Status 2 2215 */ 2216register LQOSTAT2 { 2217 address 0x056 2218 access_mode RO 2219 modes M_DFF0, M_DFF1, M_SCSI 2220 field LQOPKT 0xE0 2221 field LQOWAITFIFO 0x10 2222 field LQOPHACHGOUTPKT 0x02 /* outside of packet boundaries. */ 2223 field LQOSTOP0 0x01 /* Stopped after sending all packets */ 2224} 2225 2226/* 2227 * Output Synchronizer Space Count 2228 */ 2229register OS_SPACE_CNT { 2230 address 0x056 2231 access_mode RO 2232 modes M_CFG 2233} 2234 2235/* 2236 * SCSI Interrupt Mode 1 2237 * Setting any bit will enable the corresponding function 2238 * in SIMODE1 to interrupt via the IRQ pin. 2239 */ 2240register SIMODE1 { 2241 address 0x057 2242 access_mode RW 2243 modes M_DFF0, M_DFF1, M_SCSI 2244 field ENSELTIMO 0x80 2245 field ENATNTARG 0x40 2246 field ENSCSIRST 0x20 2247 field ENPHASEMIS 0x10 2248 field ENBUSFREE 0x08 2249 field ENSCSIPERR 0x04 2250 field ENSTRB2FAST 0x02 2251 field ENREQINIT 0x01 2252} 2253 2254/* 2255 * Good Status FIFO 2256 */ 2257register GSFIFO { 2258 address 0x058 2259 access_mode RO 2260 size 2 2261 modes M_DFF0, M_DFF1, M_SCSI 2262} 2263 2264/* 2265 * Data FIFO SCSI Transfer Control 2266 */ 2267register DFFSXFRCTL { 2268 address 0x05A 2269 access_mode RW 2270 modes M_DFF0, M_DFF1 2271 field DFFBITBUCKET 0x08 2272 field CLRSHCNT 0x04 2273 field CLRCHN 0x02 2274 field RSTCHN 0x01 2275} 2276 2277/* 2278 * Next SCSI Control Block 2279 */ 2280register NEXTSCB { 2281 address 0x05A 2282 access_mode RW 2283 size 2 2284 modes M_SCSI 2285} 2286 2287/* Rev B only. */ 2288register LQOSCSCTL { 2289 address 0x05A 2290 access_mode RW 2291 size 1 2292 modes M_CFG 2293 field LQOH2A_VERSION 0x80 2294 field LQONOCHKOVER 0x01 2295} 2296 2297/* 2298 * SEQ Interrupts 2299 */ 2300register SEQINTSRC { 2301 address 0x05B 2302 access_mode RO 2303 modes M_DFF0, M_DFF1 2304 field CTXTDONE 0x40 2305 field SAVEPTRS 0x20 2306 field CFG4DATA 0x10 2307 field CFG4ISTAT 0x08 2308 field CFG4TSTAT 0x04 2309 field CFG4ICMD 0x02 2310 field CFG4TCMD 0x01 2311} 2312 2313/* 2314 * Clear Arp Interrupts 2315 */ 2316register CLRSEQINTSRC { 2317 address 0x05B 2318 access_mode WO 2319 modes M_DFF0, M_DFF1 2320 field CLRCTXTDONE 0x40 2321 field CLRSAVEPTRS 0x20 2322 field CLRCFG4DATA 0x10 2323 field CLRCFG4ISTAT 0x08 2324 field CLRCFG4TSTAT 0x04 2325 field CLRCFG4ICMD 0x02 2326 field CLRCFG4TCMD 0x01 2327} 2328 2329/* 2330 * SEQ Interrupt Enabled (Shared) 2331 */ 2332register SEQIMODE { 2333 address 0x05C 2334 access_mode RW 2335 modes M_DFF0, M_DFF1 2336 field ENCTXTDONE 0x40 2337 field ENSAVEPTRS 0x20 2338 field ENCFG4DATA 0x10 2339 field ENCFG4ISTAT 0x08 2340 field ENCFG4TSTAT 0x04 2341 field ENCFG4ICMD 0x02 2342 field ENCFG4TCMD 0x01 2343} 2344 2345/* 2346 * Current SCSI Control Block 2347 */ 2348register CURRSCB { 2349 address 0x05C 2350 access_mode RW 2351 size 2 2352 modes M_SCSI 2353} 2354 2355/* 2356 * Data FIFO Status 2357 */ 2358register MDFFSTAT { 2359 address 0x05D 2360 access_mode RO 2361 modes M_DFF0, M_DFF1 2362 field SHCNTNEGATIVE 0x40 /* Rev B or higher */ 2363 field SHCNTMINUS1 0x20 /* Rev B or higher */ 2364 field LASTSDONE 0x10 2365 field SHVALID 0x08 2366 field DLZERO 0x04 /* FIFO data ends on packet boundary. */ 2367 field DATAINFIFO 0x02 2368 field FIFOFREE 0x01 2369} 2370 2371/* 2372 * CRC Control 2373 */ 2374register CRCCONTROL { 2375 address 0x05d 2376 access_mode RW 2377 modes M_CFG 2378 field CRCVALCHKEN 0x40 2379} 2380 2381/* 2382 * SCSI Test Control 2383 */ 2384register SCSITEST { 2385 address 0x05E 2386 access_mode RW 2387 modes M_CFG 2388 field CNTRTEST 0x08 2389 field SEL_TXPLL_DEBUG 0x04 2390} 2391 2392/* 2393 * Data FIFO Queue Tag 2394 */ 2395register DFFTAG { 2396 address 0x05E 2397 access_mode RW 2398 size 2 2399 modes M_DFF0, M_DFF1 2400} 2401 2402/* 2403 * Last SCSI Control Block 2404 */ 2405register LASTSCB { 2406 address 0x05E 2407 access_mode RW 2408 size 2 2409 modes M_SCSI 2410} 2411 2412/* 2413 * SCSI I/O Cell Power-down Control 2414 */ 2415register IOPDNCTL { 2416 address 0x05F 2417 access_mode RW 2418 modes M_CFG 2419 field DISABLE_OE 0x80 2420 field PDN_IDIST 0x04 2421 field PDN_DIFFSENSE 0x01 2422} 2423 2424/* 2425 * Shadow Host Address. 2426 */ 2427register SHADDR { 2428 address 0x060 2429 access_mode RO 2430 size 8 2431 modes M_DFF0, M_DFF1 2432} 2433 2434/* 2435 * Data Group CRC Interval. 2436 */ 2437register DGRPCRCI { 2438 address 0x060 2439 access_mode RW 2440 size 2 2441 modes M_CFG 2442} 2443 2444/* 2445 * Data Transfer Negotiation Address 2446 */ 2447register NEGOADDR { 2448 address 0x060 2449 access_mode RW 2450 modes M_SCSI 2451} 2452 2453/* 2454 * Data Transfer Negotiation Data - Period Byte 2455 */ 2456register NEGPERIOD { 2457 address 0x061 2458 access_mode RW 2459 modes M_SCSI 2460} 2461 2462/* 2463 * Packetized CRC Interval 2464 */ 2465register PACKCRCI { 2466 address 0x062 2467 access_mode RW 2468 size 2 2469 modes M_CFG 2470} 2471 2472/* 2473 * Data Transfer Negotiation Data - Offset Byte 2474 */ 2475register NEGOFFSET { 2476 address 0x062 2477 access_mode RW 2478 modes M_SCSI 2479} 2480 2481/* 2482 * Data Transfer Negotiation Data - PPR Options 2483 */ 2484register NEGPPROPTS { 2485 address 0x063 2486 access_mode RW 2487 modes M_SCSI 2488 field PPROPT_PACE 0x08 2489 field PPROPT_QAS 0x04 2490 field PPROPT_DT 0x02 2491 field PPROPT_IUT 0x01 2492} 2493 2494/* 2495 * Data Transfer Negotiation Data - Connection Options 2496 */ 2497register NEGCONOPTS { 2498 address 0x064 2499 access_mode RW 2500 modes M_SCSI 2501 field ENSNAPSHOT 0x40 2502 field RTI_WRTDIS 0x20 2503 field RTI_OVRDTRN 0x10 2504 field ENSLOWCRC 0x08 2505 field ENAUTOATNI 0x04 2506 field ENAUTOATNO 0x02 2507 field WIDEXFER 0x01 2508} 2509 2510/* 2511 * Negotiation Table Annex Column Index. 2512 */ 2513register ANNEXCOL { 2514 address 0x065 2515 access_mode RW 2516 modes M_SCSI 2517} 2518 2519register SCSCHKN { 2520 address 0x066 2521 access_mode RW 2522 modes M_CFG 2523 field STSELSKIDDIS 0x40 2524 field CURRFIFODEF 0x20 2525 field WIDERESEN 0x10 2526 field SDONEMSKDIS 0x08 2527 field DFFACTCLR 0x04 2528 field SHVALIDSTDIS 0x02 2529 field LSTSGCLRDIS 0x01 2530} 2531 2532const AHD_ANNEXCOL_PER_DEV0 4 2533const AHD_NUM_PER_DEV_ANNEXCOLS 4 2534const AHD_ANNEXCOL_PRECOMP_SLEW 4 2535const AHD_PRECOMP_MASK 0x07 2536const AHD_PRECOMP_SHIFT 0 2537const AHD_PRECOMP_CUTBACK_17 0x04 2538const AHD_PRECOMP_CUTBACK_29 0x06 2539const AHD_PRECOMP_CUTBACK_37 0x07 2540const AHD_SLEWRATE_MASK 0x78 2541const AHD_SLEWRATE_SHIFT 3 2542/* 2543 * Rev A has only a single bit (high bit of field) of slew adjustment. 2544 * Rev B has 4 bits. The current default happens to be the same for both. 2545 */ 2546const AHD_SLEWRATE_DEF_REVA 0x08 2547const AHD_SLEWRATE_DEF_REVB 0x08 2548 2549/* Rev A does not have any amplitude setting. */ 2550const AHD_ANNEXCOL_AMPLITUDE 6 2551const AHD_AMPLITUDE_MASK 0x7 2552const AHD_AMPLITUDE_SHIFT 0 2553const AHD_AMPLITUDE_DEF 0x7 2554 2555/* 2556 * Negotiation Table Annex Data Port. 2557 */ 2558register ANNEXDAT { 2559 address 0x066 2560 access_mode RW 2561 modes M_SCSI 2562} 2563 2564/* 2565 * Initiator's Own Id. 2566 * The SCSI ID to use for Selection Out and seen during a reselection.. 2567 */ 2568register IOWNID { 2569 address 0x067 2570 access_mode RW 2571 modes M_SCSI 2572} 2573 2574/* 2575 * 960MHz Phase-Locked Loop Control 0 2576 */ 2577register PLL960CTL0 { 2578 address 0x068 2579 access_mode RW 2580 modes M_CFG 2581 field PLL_VCOSEL 0x80 2582 field PLL_PWDN 0x40 2583 field PLL_NS 0x30 2584 field PLL_ENLUD 0x08 2585 field PLL_ENLPF 0x04 2586 field PLL_DLPF 0x02 2587 field PLL_ENFBM 0x01 2588} 2589 2590/* 2591 * Target Own Id 2592 */ 2593register TOWNID { 2594 address 0x069 2595 access_mode RW 2596 modes M_SCSI 2597} 2598 2599/* 2600 * 960MHz Phase-Locked Loop Control 1 2601 */ 2602register PLL960CTL1 { 2603 address 0x069 2604 access_mode RW 2605 modes M_CFG 2606 field PLL_CNTEN 0x80 2607 field PLL_CNTCLR 0x40 2608 field PLL_RST 0x01 2609} 2610 2611/* 2612 * Expander Signature 2613 */ 2614register XSIG { 2615 address 0x06A 2616 access_mode RW 2617 modes M_SCSI 2618} 2619 2620/* 2621 * Shadow Byte Count 2622 */ 2623register SHCNT { 2624 address 0x068 2625 access_mode RW 2626 size 3 2627 modes M_DFF0, M_DFF1 2628} 2629 2630/* 2631 * Selection Out ID 2632 */ 2633register SELOID { 2634 address 0x06B 2635 access_mode RW 2636 modes M_SCSI 2637} 2638 2639/* 2640 * 960-MHz Phase-Locked Loop Test Count 2641 */ 2642register PLL960CNT0 { 2643 address 0x06A 2644 access_mode RO 2645 size 2 2646 modes M_CFG 2647} 2648 2649/* 2650 * 400-MHz Phase-Locked Loop Control 0 2651 */ 2652register PLL400CTL0 { 2653 address 0x06C 2654 access_mode RW 2655 modes M_CFG 2656 field PLL_VCOSEL 0x80 2657 field PLL_PWDN 0x40 2658 field PLL_NS 0x30 2659 field PLL_ENLUD 0x08 2660 field PLL_ENLPF 0x04 2661 field PLL_DLPF 0x02 2662 field PLL_ENFBM 0x01 2663} 2664 2665/* 2666 * Arbitration Fairness 2667 */ 2668register FAIRNESS { 2669 address 0x06C 2670 access_mode RW 2671 size 2 2672 modes M_SCSI 2673} 2674 2675/* 2676 * 400-MHz Phase-Locked Loop Control 1 2677 */ 2678register PLL400CTL1 { 2679 address 0x06D 2680 access_mode RW 2681 modes M_CFG 2682 field PLL_CNTEN 0x80 2683 field PLL_CNTCLR 0x40 2684 field PLL_RST 0x01 2685} 2686 2687/* 2688 * Arbitration Unfairness 2689 */ 2690register UNFAIRNESS { 2691 address 0x06E 2692 access_mode RW 2693 size 2 2694 modes M_SCSI 2695} 2696 2697/* 2698 * 400-MHz Phase-Locked Loop Test Count 2699 */ 2700register PLL400CNT0 { 2701 address 0x06E 2702 access_mode RO 2703 size 2 2704 modes M_CFG 2705} 2706 2707/* 2708 * SCB Page Pointer 2709 */ 2710register SCBPTR { 2711 address 0x0A8 2712 access_mode RW 2713 size 2 2714 modes M_DFF0, M_DFF1, M_CCHAN, M_SCSI 2715} 2716 2717/* 2718 * CMC SCB Array Count 2719 * Number of bytes to transfer between CMC SCB memory and SCBRAM. 2720 * Transfers must be 8byte aligned and sized. 2721 */ 2722register CCSCBACNT { 2723 address 0x0AB 2724 access_mode RW 2725 modes M_CCHAN 2726} 2727 2728/* 2729 * SCB Autopointer 2730 * SCB-Next Address Snooping logic. When an SCB is transferred to 2731 * the card, the next SCB address to be used by the CMC array can 2732 * be autoloaded from that transfer. 2733 */ 2734register SCBAUTOPTR { 2735 address 0x0AB 2736 access_mode RW 2737 modes M_CFG 2738 field AUSCBPTR_EN 0x80 2739 field SCBPTR_ADDR 0x38 2740 field SCBPTR_OFF 0x07 2741} 2742 2743/* 2744 * CMC SG Ram Address Pointer 2745 */ 2746register CCSGADDR { 2747 address 0x0AC 2748 access_mode RW 2749 modes M_DFF0, M_DFF1 2750} 2751 2752/* 2753 * CMC SCB RAM Address Pointer 2754 */ 2755register CCSCBADDR { 2756 address 0x0AC 2757 access_mode RW 2758 modes M_CCHAN 2759} 2760 2761/* 2762 * CMC SCB Ram Back-up Address Pointer 2763 * Indicates the true stop location of transfers halted prior 2764 * to SCBHCNT going to 0. 2765 */ 2766register CCSCBADR_BK { 2767 address 0x0AC 2768 access_mode RO 2769 modes M_CFG 2770} 2771 2772/* 2773 * CMC SG Control 2774 */ 2775register CCSGCTL { 2776 address 0x0AD 2777 access_mode RW 2778 modes M_DFF0, M_DFF1 2779 field CCSGDONE 0x80 2780 field SG_CACHE_AVAIL 0x10 2781 field CCSGENACK 0x08 2782 mask CCSGEN 0x0C 2783 field SG_FETCH_REQ 0x02 2784 field CCSGRESET 0x01 2785} 2786 2787/* 2788 * CMD SCB Control 2789 */ 2790register CCSCBCTL { 2791 address 0x0AD 2792 access_mode RW 2793 modes M_CCHAN 2794 field CCSCBDONE 0x80 2795 field ARRDONE 0x40 2796 field CCARREN 0x10 2797 field CCSCBEN 0x08 2798 field CCSCBDIR 0x04 2799 field CCSCBRESET 0x01 2800} 2801 2802/* 2803 * CMC Ram BIST 2804 */ 2805register CMC_RAMBIST { 2806 address 0x0AD 2807 access_mode RW 2808 modes M_CFG 2809 field SG_ELEMENT_SIZE 0x80 2810 field SCBRAMBIST_FAIL 0x40 2811 field SG_BIST_FAIL 0x20 2812 field SG_BIST_EN 0x10 2813 field CMC_BUFFER_BIST_FAIL 0x02 2814 field CMC_BUFFER_BIST_EN 0x01 2815} 2816 2817/* 2818 * CMC SG RAM Data Port 2819 */ 2820register CCSGRAM { 2821 address 0x0B0 2822 access_mode RW 2823 modes M_DFF0, M_DFF1 2824} 2825 2826/* 2827 * CMC SCB RAM Data Port 2828 */ 2829register CCSCBRAM { 2830 address 0x0B0 2831 access_mode RW 2832 modes M_CCHAN 2833} 2834 2835/* 2836 * Flex DMA Address. 2837 */ 2838register FLEXADR { 2839 address 0x0B0 2840 access_mode RW 2841 size 3 2842 modes M_SCSI 2843} 2844 2845/* 2846 * Flex DMA Byte Count 2847 */ 2848register FLEXCNT { 2849 address 0x0B3 2850 access_mode RW 2851 size 2 2852 modes M_SCSI 2853} 2854 2855/* 2856 * Flex DMA Status 2857 */ 2858register FLEXDMASTAT { 2859 address 0x0B5 2860 access_mode RW 2861 modes M_SCSI 2862 field FLEXDMAERR 0x02 2863 field FLEXDMADONE 0x01 2864} 2865 2866/* 2867 * Flex DMA Data Port 2868 */ 2869register FLEXDATA { 2870 address 0x0B6 2871 access_mode RW 2872 modes M_SCSI 2873} 2874 2875/* 2876 * Board Data 2877 */ 2878register BRDDAT { 2879 address 0x0B8 2880 access_mode RW 2881 modes M_SCSI 2882} 2883 2884/* 2885 * Board Control 2886 */ 2887register BRDCTL { 2888 address 0x0B9 2889 access_mode RW 2890 modes M_SCSI 2891 field FLXARBACK 0x80 2892 field FLXARBREQ 0x40 2893 field BRDADDR 0x38 2894 field BRDEN 0x04 2895 field BRDRW 0x02 2896 field BRDSTB 0x01 2897} 2898 2899/* 2900 * Serial EEPROM Address 2901 */ 2902register SEEADR { 2903 address 0x0BA 2904 access_mode RW 2905 modes M_SCSI 2906} 2907 2908/* 2909 * Serial EEPROM Data 2910 */ 2911register SEEDAT { 2912 address 0x0BC 2913 access_mode RW 2914 size 2 2915 modes M_SCSI 2916} 2917 2918/* 2919 * Serial EEPROM Status 2920 */ 2921register SEESTAT { 2922 address 0x0BE 2923 access_mode RO 2924 modes M_SCSI 2925 field INIT_DONE 0x80 2926 field SEEOPCODE 0x70 2927 field LDALTID_L 0x08 2928 field SEEARBACK 0x04 2929 field SEEBUSY 0x02 2930 field SEESTART 0x01 2931} 2932 2933/* 2934 * Serial EEPROM Control 2935 */ 2936register SEECTL { 2937 address 0x0BE 2938 access_mode RW 2939 modes M_SCSI 2940 field SEEOPCODE 0x70 { 2941 SEEOP_ERASE 0x70, 2942 SEEOP_READ 0x60, 2943 SEEOP_WRITE 0x50, 2944 /* 2945 * The following four commands use special 2946 * addresses for differentiation. 2947 */ 2948 SEEOP_ERAL 0x40 2949 } 2950 mask SEEOP_EWEN 0x40 2951 mask SEEOP_WALL 0x40 2952 mask SEEOP_EWDS 0x40 2953 field SEERST 0x02 2954 field SEESTART 0x01 2955} 2956 2957const SEEOP_ERAL_ADDR 0x80 2958const SEEOP_EWEN_ADDR 0xC0 2959const SEEOP_WRAL_ADDR 0x40 2960const SEEOP_EWDS_ADDR 0x00 2961 2962/* 2963 * SCB Counter 2964 */ 2965register SCBCNT { 2966 address 0x0BF 2967 access_mode RW 2968 modes M_SCSI 2969} 2970 2971/* 2972 * Data FIFO Write Address 2973 * Pointer to the next QWD location to be written to the data FIFO. 2974 */ 2975register DFWADDR { 2976 address 0x0C0 2977 access_mode RW 2978 size 2 2979 modes M_DFF0, M_DFF1 2980} 2981 2982/* 2983 * DSP Filter Control 2984 */ 2985register DSPFLTRCTL { 2986 address 0x0C0 2987 access_mode RW 2988 modes M_CFG 2989 field FLTRDISABLE 0x20 2990 field EDGESENSE 0x10 2991 field DSPFCNTSEL 0x0F 2992} 2993 2994/* 2995 * DSP Data Channel Control 2996 */ 2997register DSPDATACTL { 2998 address 0x0C1 2999 access_mode RW 3000 modes M_CFG 3001 field BYPASSENAB 0x80 3002 field DESQDIS 0x10 3003 field RCVROFFSTDIS 0x04 3004 field XMITOFFSTDIS 0x02 3005} 3006 3007/* 3008 * Data FIFO Read Address 3009 * Pointer to the next QWD location to be read from the data FIFO. 3010 */ 3011register DFRADDR { 3012 address 0x0C2 3013 access_mode RW 3014 size 2 3015 modes M_DFF0, M_DFF1 3016} 3017 3018/* 3019 * DSP REQ Control 3020 */ 3021register DSPREQCTL { 3022 address 0x0C2 3023 access_mode RW 3024 modes M_CFG 3025 field MANREQCTL 0xC0 3026 field MANREQDLY 0x3F 3027} 3028 3029/* 3030 * DSP ACK Control 3031 */ 3032register DSPACKCTL { 3033 address 0x0C3 3034 access_mode RW 3035 modes M_CFG 3036 field MANACKCTL 0xC0 3037 field MANACKDLY 0x3F 3038} 3039 3040/* 3041 * Data FIFO Data 3042 * Read/Write byte port into the data FIFO. The read and write 3043 * FIFO pointers increment with each read and write respectively 3044 * to this port. 3045 */ 3046register DFDAT { 3047 address 0x0C4 3048 access_mode RW 3049 modes M_DFF0, M_DFF1 3050} 3051 3052/* 3053 * DSP Channel Select 3054 */ 3055register DSPSELECT { 3056 address 0x0C4 3057 access_mode RW 3058 modes M_CFG 3059 field AUTOINCEN 0x80 3060 field DSPSEL 0x1F 3061} 3062 3063const NUMDSPS 0x14 3064 3065/* 3066 * Write Bias Control 3067 */ 3068register WRTBIASCTL { 3069 address 0x0C5 3070 access_mode WO 3071 modes M_CFG 3072 field AUTOXBCDIS 0x80 3073 field XMITMANVAL 0x3F 3074} 3075 3076/* 3077 * Currently the WRTBIASCTL is the same as the default. 3078 */ 3079const WRTBIASCTL_HP_DEFAULT 0x0 3080 3081/* 3082 * Receiver Bias Control 3083 */ 3084register RCVRBIOSCTL { 3085 address 0x0C6 3086 access_mode WO 3087 modes M_CFG 3088 field AUTORBCDIS 0x80 3089 field RCVRMANVAL 0x3F 3090} 3091 3092/* 3093 * Write Bias Calculator 3094 */ 3095register WRTBIASCALC { 3096 address 0x0C7 3097 access_mode RO 3098 modes M_CFG 3099} 3100 3101/* 3102 * Data FIFO Pointers 3103 * Contains the byte offset from DFWADDR and DWRADDR to the current 3104 * FIFO write/read locations. 3105 */ 3106register DFPTRS { 3107 address 0x0C8 3108 access_mode RW 3109 modes M_DFF0, M_DFF1 3110} 3111 3112/* 3113 * Receiver Bias Calculator 3114 */ 3115register RCVRBIASCALC { 3116 address 0x0C8 3117 access_mode RO 3118 modes M_CFG 3119} 3120 3121/* 3122 * Data FIFO Backup Read Pointer 3123 * Contains the data FIFO address to be restored if the last 3124 * data accessed from the data FIFO was not transferred successfully. 3125 */ 3126register DFBKPTR { 3127 address 0x0C9 3128 access_mode RW 3129 size 2 3130 modes M_DFF0, M_DFF1 3131} 3132 3133/* 3134 * Skew Calculator 3135 */ 3136register SKEWCALC { 3137 address 0x0C9 3138 access_mode RO 3139 modes M_CFG 3140} 3141 3142/* 3143 * Data FIFO Debug Control 3144 */ 3145register DFDBCTL { 3146 address 0x0CB 3147 access_mode RW 3148 modes M_DFF0, M_DFF1 3149 field DFF_CIO_WR_RDY 0x20 3150 field DFF_CIO_RD_RDY 0x10 3151 field DFF_DIR_ERR 0x08 3152 field DFF_RAMBIST_FAIL 0x04 3153 field DFF_RAMBIST_DONE 0x02 3154 field DFF_RAMBIST_EN 0x01 3155} 3156 3157/* 3158 * Data FIFO Space Count 3159 * Number of FIFO locations that are free. 3160 */ 3161register DFSCNT { 3162 address 0x0CC 3163 access_mode RO 3164 size 2 3165 modes M_DFF0, M_DFF1 3166} 3167 3168/* 3169 * Data FIFO Byte Count 3170 * Number of filled FIFO locations. 3171 */ 3172register DFBCNT { 3173 address 0x0CE 3174 access_mode RO 3175 size 2 3176 modes M_DFF0, M_DFF1 3177} 3178 3179/* 3180 * Sequencer Program Overlay Address. 3181 * Low address must be written prior to high address. 3182 */ 3183register OVLYADDR { 3184 address 0x0D4 3185 modes M_SCSI 3186 size 2 3187 access_mode RW 3188} 3189 3190/* 3191 * Sequencer Control 0 3192 * Error detection mode, speed configuration, 3193 * single step, breakpoints and program load. 3194 */ 3195register SEQCTL0 { 3196 address 0x0D6 3197 access_mode RW 3198 field PERRORDIS 0x80 3199 field PAUSEDIS 0x40 3200 field FAILDIS 0x20 3201 field FASTMODE 0x10 3202 field BRKADRINTEN 0x08 3203 field STEP 0x04 3204 field SEQRESET 0x02 3205 field LOADRAM 0x01 3206} 3207 3208/* 3209 * Sequencer Control 1 3210 * Instruction RAM Diagnostics 3211 */ 3212register SEQCTL1 { 3213 address 0x0D7 3214 access_mode RW 3215 field OVRLAY_DATA_CHK 0x08 3216 field RAMBIST_DONE 0x04 3217 field RAMBIST_FAIL 0x02 3218 field RAMBIST_EN 0x01 3219} 3220 3221/* 3222 * Sequencer Flags 3223 * Zero and Carry state of the ALU. 3224 */ 3225register FLAGS { 3226 address 0x0D8 3227 access_mode RO 3228 field ZERO 0x02 3229 field CARRY 0x01 3230} 3231 3232/* 3233 * Sequencer Interrupt Control 3234 */ 3235register SEQINTCTL { 3236 address 0x0D9 3237 access_mode RW 3238 field INTVEC1DSL 0x80 3239 field INT1_CONTEXT 0x20 3240 field SCS_SEQ_INT1M1 0x10 3241 field SCS_SEQ_INT1M0 0x08 3242 field INTMASK2 0x04 3243 field INTMASK1 0x02 3244 field IRET 0x01 3245} 3246 3247/* 3248 * Sequencer RAM Data Port 3249 * Single byte window into the Sequencer Instruction Ram area starting 3250 * at the address specified by OVLYADDR. To write a full instruction word, 3251 * simply write four bytes in succession. OVLYADDR will increment after the 3252 * most significant instrution byte (the byte with the parity bit) is written. 3253 */ 3254register SEQRAM { 3255 address 0x0DA 3256 access_mode RW 3257} 3258 3259/* 3260 * Sequencer Program Counter 3261 * Low byte must be written prior to high byte. 3262 */ 3263register PRGMCNT { 3264 address 0x0DE 3265 access_mode RW 3266 size 2 3267} 3268 3269/* 3270 * Accumulator 3271 */ 3272register ACCUM { 3273 address 0x0E0 3274 access_mode RW 3275 accumulator 3276} 3277 3278/* 3279 * Source Index Register 3280 * Incrementing index for reads of SINDIR and the destination (low byte only) 3281 * for any immediate operands passed in jmp, jc, jnc, call instructions. 3282 * Example: 3283 * mvi 0xFF call some_routine; 3284 * 3285 * Will set SINDEX[0] to 0xFF and call the routine "some_routine. 3286 */ 3287register SINDEX { 3288 address 0x0E2 3289 access_mode RW 3290 size 2 3291 sindex 3292} 3293 3294/* 3295 * Destination Index Register 3296 * Incrementing index for writes to DINDIR. Can be used as a scratch register. 3297 */ 3298register DINDEX { 3299 address 0x0E4 3300 access_mode RW 3301 size 2 3302} 3303 3304/* 3305 * Break Address 3306 * Sequencer instruction breakpoint address address. 3307 */ 3308register BRKADDR0 { 3309 address 0x0E6 3310 access_mode RW 3311} 3312 3313register BRKADDR1 { 3314 address 0x0E6 3315 access_mode RW 3316 field BRKDIS 0x80 /* Disable Breakpoint */ 3317} 3318 3319/* 3320 * All Ones 3321 * All reads to this register return the value 0xFF. 3322 */ 3323register ALLONES { 3324 address 0x0E8 3325 access_mode RO 3326 allones 3327} 3328 3329/* 3330 * All Zeros 3331 * All reads to this register return the value 0. 3332 */ 3333register ALLZEROS { 3334 address 0x0EA 3335 access_mode RO 3336 allzeros 3337} 3338 3339/* 3340 * No Destination 3341 * Writes to this register have no effect. 3342 */ 3343register NONE { 3344 address 0x0EA 3345 access_mode WO 3346 none 3347} 3348 3349/* 3350 * Source Index Indirect 3351 * Reading this register is equivalent to reading (register_base + SINDEX) and 3352 * incrementing SINDEX by 1. 3353 */ 3354register SINDIR { 3355 address 0x0EC 3356 access_mode RO 3357} 3358 3359/* 3360 * Destination Index Indirect 3361 * Writing this register is equivalent to writing to (register_base + DINDEX) 3362 * and incrementing DINDEX by 1. 3363 */ 3364register DINDIR { 3365 address 0x0ED 3366 access_mode WO 3367} 3368 3369/* 3370 * Function One 3371 * 2's complement to bit value conversion. Write the 2's complement value 3372 * (0-7 only) to the top nibble and retrieve the bit indexed by that value 3373 * on the next read of this register. 3374 * Example: 3375 * Write 0x60 3376 * Read 0x40 3377 */ 3378register FUNCTION1 { 3379 address 0x0F0 3380 access_mode RW 3381} 3382 3383/* 3384 * Stack 3385 * Window into the stack. Each stack location is 10 bits wide reported 3386 * low byte followed by high byte. There are 8 stack locations. 3387 */ 3388register STACK { 3389 address 0x0F2 3390 access_mode RW 3391} 3392 3393/* 3394 * Interrupt Vector 1 Address 3395 * Interrupt branch address for SCS SEQ_INT1 mode 0 and 1 interrupts. 3396 */ 3397register INTVEC1_ADDR { 3398 address 0x0F4 3399 access_mode RW 3400 size 2 3401 modes M_CFG 3402} 3403 3404/* 3405 * Current Address 3406 * Address of the SEQRAM instruction currently executing instruction. 3407 */ 3408register CURADDR { 3409 address 0x0F4 3410 access_mode RW 3411 size 2 3412 modes M_SCSI 3413} 3414 3415/* 3416 * Interrupt Vector 2 Address 3417 * Interrupt branch address for HST_SEQ_INT2 interrupts. 3418 */ 3419register INTVEC2_ADDR { 3420 address 0x0F6 3421 access_mode RW 3422 size 2 3423 modes M_CFG 3424} 3425 3426/* 3427 * Last Address 3428 * Address of the SEQRAM instruction executed prior to the current instruction. 3429 */ 3430register LASTADDR { 3431 address 0x0F6 3432 access_mode RW 3433 size 2 3434 modes M_SCSI 3435} 3436 3437register AHD_PCI_CONFIG_BASE { 3438 address 0x100 3439 access_mode RW 3440 size 256 3441 modes M_CFG 3442} 3443 3444/* ---------------------- Scratch RAM Offsets ------------------------- */ 3445scratch_ram { 3446 /* Mode Specific */ 3447 address 0x0A0 3448 size 8 3449 modes 0, 1, 2, 3 3450 REG0 { 3451 size 2 3452 } 3453 REG1 { 3454 size 2 3455 } 3456 REG_ISR { 3457 size 2 3458 } 3459 SG_STATE { 3460 size 1 3461 field SEGS_AVAIL 0x01 3462 field LOADING_NEEDED 0x02 3463 field FETCH_INPROG 0x04 3464 } 3465 /* 3466 * Track whether the transfer byte count for 3467 * the current data phase is odd. 3468 */ 3469 DATA_COUNT_ODD { 3470 size 1 3471 } 3472} 3473 3474scratch_ram { 3475 /* Mode Specific */ 3476 address 0x0F8 3477 size 8 3478 modes 0, 1, 2, 3 3479 LONGJMP_ADDR { 3480 size 2 3481 } 3482 ACCUM_SAVE { 3483 size 1 3484 } 3485} 3486 3487 3488scratch_ram { 3489 address 0x100 3490 size 128 3491 modes 0, 1, 2, 3 3492 /* 3493 * Per "other-id" execution queues. We use an array of 3494 * tail pointers into lists of SCBs sorted by "other-id". 3495 * The execution head pointer threads the head SCBs for 3496 * each list. 3497 */ 3498 WAITING_SCB_TAILS { 3499 size 32 3500 } 3501 WAITING_TID_HEAD { 3502 size 2 3503 } 3504 WAITING_TID_TAIL { 3505 size 2 3506 } 3507 /* 3508 * SCBID of the next SCB in the new SCB queue. 3509 */ 3510 NEXT_QUEUED_SCB_ADDR { 3511 size 4 3512 } 3513 /* 3514 * head of list of SCBs that have 3515 * completed but have not been 3516 * put into the qoutfifo. 3517 */ 3518 COMPLETE_SCB_HEAD { 3519 size 2 3520 } 3521 /* 3522 * The list of completed SCBs in 3523 * the active DMA. 3524 */ 3525 COMPLETE_SCB_DMAINPROG_HEAD { 3526 size 2 3527 } 3528 /* 3529 * head of list of SCBs that have 3530 * completed but need to be uploaded 3531 * to the host prior to being completed. 3532 */ 3533 COMPLETE_DMA_SCB_HEAD { 3534 size 2 3535 } 3536 /* 3537 * tail of list of SCBs that have 3538 * completed but need to be uploaded 3539 * to the host prior to being completed. 3540 */ 3541 COMPLETE_DMA_SCB_TAIL { 3542 size 2 3543 } 3544 /* 3545 * head of list of SCBs that have 3546 * been uploaded to the host, but cannot 3547 * be completed until the QFREEZE is in 3548 * full effect (i.e. no selections pending). 3549 */ 3550 COMPLETE_ON_QFREEZE_HEAD { 3551 size 2 3552 } 3553 /* 3554 * Counting semaphore to prevent new select-outs 3555 * The queue is frozen so long as the sequencer 3556 * and kernel freeze counts differ. 3557 */ 3558 QFREEZE_COUNT { 3559 size 2 3560 } 3561 KERNEL_QFREEZE_COUNT { 3562 size 2 3563 } 3564 /* 3565 * Mode to restore on legacy idle loop exit. 3566 */ 3567 SAVED_MODE { 3568 size 1 3569 } 3570 /* 3571 * Single byte buffer used to designate the type or message 3572 * to send to a target. 3573 */ 3574 MSG_OUT { 3575 size 1 3576 } 3577 /* Parameters for DMA Logic */ 3578 DMAPARAMS { 3579 size 1 3580 field PRELOADEN 0x80 3581 field WIDEODD 0x40 3582 field SCSIEN 0x20 3583 field SDMAEN 0x10 3584 field SDMAENACK 0x10 3585 field HDMAEN 0x08 3586 field HDMAENACK 0x08 3587 field DIRECTION 0x04 /* Set indicates PCI->SCSI */ 3588 field FIFOFLUSH 0x02 3589 field FIFORESET 0x01 3590 } 3591 SEQ_FLAGS { 3592 size 1 3593 field NOT_IDENTIFIED 0x80 3594 field NO_CDB_SENT 0x40 3595 field TARGET_CMD_IS_TAGGED 0x40 3596 field DPHASE 0x20 3597 /* Target flags */ 3598 field TARG_CMD_PENDING 0x10 3599 field CMDPHASE_PENDING 0x08 3600 field DPHASE_PENDING 0x04 3601 field SPHASE_PENDING 0x02 3602 field NO_DISCONNECT 0x01 3603 } 3604 /* 3605 * Temporary storage for the 3606 * target/channel/lun of a 3607 * reconnecting target 3608 */ 3609 SAVED_SCSIID { 3610 size 1 3611 } 3612 SAVED_LUN { 3613 size 1 3614 } 3615 /* 3616 * The last bus phase as seen by the sequencer. 3617 */ 3618 LASTPHASE { 3619 size 1 3620 field CDI 0x80 3621 field IOI 0x40 3622 field MSGI 0x20 3623 field P_BUSFREE 0x01 3624 enum PHASE_MASK CDO|IOO|MSGO { 3625 P_DATAOUT 0x0, 3626 P_DATAIN IOO, 3627 P_DATAOUT_DT P_DATAOUT|MSGO, 3628 P_DATAIN_DT P_DATAIN|MSGO, 3629 P_COMMAND CDO, 3630 P_MESGOUT CDO|MSGO, 3631 P_STATUS CDO|IOO, 3632 P_MESGIN CDO|IOO|MSGO 3633 } 3634 } 3635 /* 3636 * Value to "or" into the SCBPTR[1] value to 3637 * indicate that an entry in the QINFIFO is valid. 3638 */ 3639 QOUTFIFO_ENTRY_VALID_TAG { 3640 size 1 3641 } 3642 /* 3643 * Kernel and sequencer offsets into the queue of 3644 * incoming target mode command descriptors. The 3645 * queue is full when the KERNEL_TQINPOS == TQINPOS. 3646 */ 3647 KERNEL_TQINPOS { 3648 size 1 3649 } 3650 TQINPOS { 3651 size 1 3652 } 3653 /* 3654 * Base address of our shared data with the kernel driver in host 3655 * memory. This includes the qoutfifo and target mode 3656 * incoming command queue. 3657 */ 3658 SHARED_DATA_ADDR { 3659 size 4 3660 } 3661 /* 3662 * Pointer to location in host memory for next 3663 * position in the qoutfifo. 3664 */ 3665 QOUTFIFO_NEXT_ADDR { 3666 size 4 3667 } 3668 ARG_1 { 3669 size 1 3670 mask SEND_MSG 0x80 3671 mask SEND_SENSE 0x40 3672 mask SEND_REJ 0x20 3673 mask MSGOUT_PHASEMIS 0x10 3674 mask EXIT_MSG_LOOP 0x08 3675 mask CONT_MSG_LOOP_WRITE 0x04 3676 mask CONT_MSG_LOOP_READ 0x03 3677 mask CONT_MSG_LOOP_TARG 0x02 3678 alias RETURN_1 3679 } 3680 ARG_2 { 3681 size 1 3682 alias RETURN_2 3683 } 3684 3685 /* 3686 * Snapshot of MSG_OUT taken after each message is sent. 3687 */ 3688 LAST_MSG { 3689 size 1 3690 } 3691 3692 /* 3693 * Sequences the kernel driver has okayed for us. This allows 3694 * the driver to do things like prevent initiator or target 3695 * operations. 3696 */ 3697 SCSISEQ_TEMPLATE { 3698 size 1 3699 field MANUALCTL 0x40 3700 field ENSELI 0x20 3701 field ENRSELI 0x10 3702 field MANUALP 0x0C 3703 field ENAUTOATNP 0x02 3704 field ALTSTIM 0x01 3705 } 3706 3707 /* 3708 * The initiator specified tag for this target mode transaction. 3709 */ 3710 INITIATOR_TAG { 3711 size 1 3712 } 3713 3714 SEQ_FLAGS2 { 3715 size 1 3716 field PENDING_MK_MESSAGE 0x01 3717 field TARGET_MSG_PENDING 0x02 3718 field SELECTOUT_QFROZEN 0x04 3719 } 3720 3721 ALLOCFIFO_SCBPTR { 3722 size 2 3723 } 3724 3725 /* 3726 * The maximum amount of time to wait, when interrupt coalescing 3727 * is enabled, before issuing a CMDCMPLT interrupt for a completed 3728 * command. 3729 */ 3730 INT_COALESCING_TIMER { 3731 size 2 3732 } 3733 3734 /* 3735 * The maximum number of commands to coalesce into a single interrupt. 3736 * Actually the 2's complement of that value to simplify sequencer 3737 * code. 3738 */ 3739 INT_COALESCING_MAXCMDS { 3740 size 1 3741 } 3742 3743 /* 3744 * The minimum number of commands still outstanding required 3745 * to continue coalescing (2's complement of value). 3746 */ 3747 INT_COALESCING_MINCMDS { 3748 size 1 3749 } 3750 3751 /* 3752 * Number of commands "in-flight". 3753 */ 3754 CMDS_PENDING { 3755 size 2 3756 } 3757 3758 /* 3759 * The count of commands that have been coalesced. 3760 */ 3761 INT_COALESCING_CMDCOUNT { 3762 size 1 3763 } 3764 3765 /* 3766 * Since the HS_MAIBOX is self clearing, copy its contents to 3767 * this position in scratch ram every time it changes. 3768 */ 3769 LOCAL_HS_MAILBOX { 3770 size 1 3771 } 3772 /* 3773 * Target-mode CDB type to CDB length table used 3774 * in non-packetized operation. 3775 */ 3776 CMDSIZE_TABLE { 3777 size 8 3778 } 3779 /* 3780 * When an SCB with the MK_MESSAGE flag is 3781 * queued to the controller, it cannot enter 3782 * the waiting for selection list until the 3783 * selections for any previously queued 3784 * commands to that target complete. During 3785 * the wait, the MK_MESSAGE SCB is queued 3786 * here. 3787 */ 3788 MK_MESSAGE_SCB { 3789 size 2 3790 } 3791 /* 3792 * Saved SCSIID of MK_MESSAGE_SCB to avoid 3793 * an extra SCBPTR operation when deciding 3794 * if the MK_MESSAGE_SCB can be run. 3795 */ 3796 MK_MESSAGE_SCSIID { 3797 size 1 3798 } 3799} 3800 3801/************************* Hardware SCB Definition ****************************/ 3802scb { 3803 address 0x180 3804 size 64 3805 modes 0, 1, 2, 3 3806 SCB_RESIDUAL_DATACNT { 3807 size 4 3808 alias SCB_CDB_STORE 3809 alias SCB_HOST_CDB_PTR 3810 } 3811 SCB_RESIDUAL_SGPTR { 3812 size 4 3813 field SG_ADDR_MASK 0xf8 /* In the last byte */ 3814 field SG_ADDR_BIT 0x04 3815 field SG_OVERRUN_RESID 0x02 /* In the first byte */ 3816 field SG_LIST_NULL 0x01 /* In the first byte */ 3817 } 3818 SCB_SCSI_STATUS { 3819 size 1 3820 alias SCB_HOST_CDB_LEN 3821 } 3822 SCB_TARGET_PHASES { 3823 size 1 3824 } 3825 SCB_TARGET_DATA_DIR { 3826 size 1 3827 } 3828 SCB_TARGET_ITAG { 3829 size 1 3830 } 3831 SCB_SENSE_BUSADDR { 3832 /* 3833 * Only valid if CDB length is less than 13 bytes or 3834 * we are using a CDB pointer. Otherwise contains 3835 * the last 4 bytes of embedded cdb information. 3836 */ 3837 size 4 3838 alias SCB_NEXT_COMPLETE 3839 } 3840 SCB_TAG { 3841 alias SCB_FIFO_USE_COUNT 3842 size 2 3843 } 3844 SCB_CONTROL { 3845 size 1 3846 field TARGET_SCB 0x80 3847 field DISCENB 0x40 3848 field TAG_ENB 0x20 3849 field MK_MESSAGE 0x10 3850 field STATUS_RCVD 0x08 3851 field DISCONNECTED 0x04 3852 field SCB_TAG_TYPE 0x03 3853 } 3854 SCB_SCSIID { 3855 size 1 3856 field TID 0xF0 3857 field OID 0x0F 3858 } 3859 SCB_LUN { 3860 size 1 3861 field LID 0xff 3862 } 3863 SCB_TASK_ATTRIBUTE { 3864 size 1 3865 /* 3866 * Overloaded field for non-packetized 3867 * ignore wide residue message handling. 3868 */ 3869 field SCB_XFERLEN_ODD 0x01 3870 } 3871 SCB_CDB_LEN { 3872 size 1 3873 field SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */ 3874 } 3875 SCB_TASK_MANAGEMENT { 3876 size 1 3877 } 3878 SCB_DATAPTR { 3879 size 8 3880 } 3881 SCB_DATACNT { 3882 /* 3883 * The last byte is really the high address bits for 3884 * the data address. 3885 */ 3886 size 4 3887 field SG_LAST_SEG 0x80 /* In the fourth byte */ 3888 field SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ 3889 } 3890 SCB_SGPTR { 3891 size 4 3892 field SG_STATUS_VALID 0x04 /* In the first byte */ 3893 field SG_FULL_RESID 0x02 /* In the first byte */ 3894 field SG_LIST_NULL 0x01 /* In the first byte */ 3895 } 3896 SCB_BUSADDR { 3897 size 4 3898 } 3899 SCB_NEXT { 3900 alias SCB_NEXT_SCB_BUSADDR 3901 size 2 3902 } 3903 SCB_NEXT2 { 3904 size 2 3905 } 3906 SCB_SPARE { 3907 size 8 3908 alias SCB_PKT_LUN 3909 } 3910 SCB_DISCONNECTED_LISTS { 3911 size 8 3912 } 3913} 3914 3915/*********************************** Constants ********************************/ 3916const MK_MESSAGE_BIT_OFFSET 4 3917const TID_SHIFT 4 3918const TARGET_CMD_CMPLT 0xfe 3919const INVALID_ADDR 0x80 3920#define SCB_LIST_NULL 0xff 3921#define QOUTFIFO_ENTRY_VALID_TOGGLE 0x80 3922 3923const CCSGADDR_MAX 0x80 3924const CCSCBADDR_MAX 0x80 3925const CCSGRAM_MAXSEGS 16 3926 3927/* Selection Timeout Timer Constants */ 3928const STIMESEL_SHIFT 3 3929const STIMESEL_MIN 0x18 3930const STIMESEL_BUG_ADJ 0x8 3931 3932/* WDTR Message values */ 3933const BUS_8_BIT 0x00 3934const BUS_16_BIT 0x01 3935const BUS_32_BIT 0x02 3936 3937/* Offset maximums */ 3938const MAX_OFFSET 0xfe 3939const MAX_OFFSET_PACED 0xfe 3940const MAX_OFFSET_PACED_BUG 0x7f 3941/* 3942 * Some 160 devices incorrectly accept 0xfe as a 3943 * sync offset, but will overrun this value. Limit 3944 * to 0x7f for speed lower than U320 which will 3945 * avoid the persistent sync offset overruns. 3946 */ 3947const MAX_OFFSET_NON_PACED 0x7f 3948const HOST_MSG 0xff 3949 3950/* 3951 * The size of our sense buffers. 3952 * Sense buffer mapping can be handled in either of two ways. 3953 * The first is to allocate a dmamap for each transaction. 3954 * Depending on the architecture, dmamaps can be costly. The 3955 * alternative is to statically map the buffers in much the same 3956 * way we handle our scatter gather lists. The driver implements 3957 * the later. 3958 */ 3959const AHD_SENSE_BUFSIZE 256 3960 3961/* Target mode command processing constants */ 3962const CMD_GROUP_CODE_SHIFT 0x05 3963 3964const STATUS_BUSY 0x08 3965const STATUS_QUEUE_FULL 0x28 3966const STATUS_PKT_SENSE 0xFF 3967const TARGET_DATA_IN 1 3968 3969const SCB_TRANSFER_SIZE_FULL_LUN 56 3970const SCB_TRANSFER_SIZE_1BYTE_LUN 48 3971/* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */ 3972const PKT_OVERRUN_BUFSIZE 512 3973 3974/* 3975 * Timer parameters. 3976 */ 3977const AHD_TIMER_US_PER_TICK 25 3978const AHD_TIMER_MAX_TICKS 0xFFFF 3979const AHD_TIMER_MAX_US (AHD_TIMER_MAX_TICKS * AHD_TIMER_US_PER_TICK) 3980 3981/* 3982 * Downloaded (kernel inserted) constants 3983 */ 3984const SG_PREFETCH_CNT download 3985const SG_PREFETCH_CNT_LIMIT download 3986const SG_PREFETCH_ALIGN_MASK download 3987const SG_PREFETCH_ADDR_MASK download 3988const SG_SIZEOF download 3989const PKT_OVERRUN_BUFOFFSET download 3990const SCB_TRANSFER_SIZE download 3991const CACHELINE_MASK download 3992 3993/* 3994 * BIOS SCB offsets 3995 */ 3996const NVRAM_SCB_OFFSET 0x2C 3997