1 /* 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2002 Justin T. Gibbs. 5 * Copyright (c) 2000-2002 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#84 $ 41 * 42 * $FreeBSD$ 43 */ 44 45 #ifndef _AIC79XX_H_ 46 #define _AIC79XX_H_ 47 48 /* Register Definitions */ 49 #include "aic79xx_reg.h" 50 51 /************************* Forward Declarations *******************************/ 52 struct ahd_platform_data; 53 struct scb_platform_data; 54 55 /****************************** Useful Macros *********************************/ 56 #ifndef MAX 57 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 58 #endif 59 60 #ifndef MIN 61 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 62 #endif 63 64 #ifndef TRUE 65 #define TRUE 1 66 #endif 67 #ifndef FALSE 68 #define FALSE 0 69 #endif 70 71 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 72 73 #define ALL_CHANNELS '\0' 74 #define ALL_TARGETS_MASK 0xFFFF 75 #define INITIATOR_WILDCARD (~0) 76 #define SCB_LIST_NULL 0xFF00 77 #define SCB_LIST_NULL_LE (ahd_htole16(SCB_LIST_NULL)) 78 #define QOUTFIFO_ENTRY_VALID 0x8000 79 #define QOUTFIFO_ENTRY_VALID_LE (ahd_htole16(0x8000)) 80 #define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL) 81 82 #define SCSIID_TARGET(ahd, scsiid) \ 83 (((scsiid) & TID) >> TID_SHIFT) 84 #define SCSIID_OUR_ID(scsiid) \ 85 ((scsiid) & OID) 86 #define SCSIID_CHANNEL(ahd, scsiid) ('A') 87 #define SCB_IS_SCSIBUS_B(ahd, scb) (0) 88 #define SCB_GET_OUR_ID(scb) \ 89 SCSIID_OUR_ID((scb)->hscb->scsiid) 90 #define SCB_GET_TARGET(ahd, scb) \ 91 SCSIID_TARGET((ahd), (scb)->hscb->scsiid) 92 #define SCB_GET_CHANNEL(ahd, scb) \ 93 SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid) 94 #define SCB_GET_LUN(scb) \ 95 ((scb)->hscb->lun) 96 #define SCB_GET_TARGET_OFFSET(ahd, scb) \ 97 SCB_GET_TARGET(ahd, scb) 98 #define SCB_GET_TARGET_MASK(ahd, scb) \ 99 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb))) 100 #ifdef AHD_DEBUG 101 #define SCB_IS_SILENT(scb) \ 102 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \ 103 && (((scb)->flags & SCB_SILENT) != 0)) 104 #else 105 #define SCB_IS_SILENT(scb) \ 106 (((scb)->flags & SCB_SILENT) != 0) 107 #endif 108 /* 109 * TCLs have the following format: TTTTLLLLLLLL 110 */ 111 #define TCL_TARGET_OFFSET(tcl) \ 112 ((((tcl) >> 4) & TID) >> 4) 113 #define TCL_LUN(tcl) \ 114 (tcl & (AHD_NUM_LUNS - 1)) 115 #define BUILD_TCL(scsiid, lun) \ 116 ((lun) | (((scsiid) & TID) << 4)) 117 #define BUILD_TCL_RAW(target, channel, lun) \ 118 ((lun) | ((target) << 8)) 119 120 #define SCB_GET_TAG(scb) \ 121 ahd_le16toh(scb->hscb->tag) 122 123 #ifndef AHD_TARGET_MODE 124 #undef AHD_TMODE_ENABLE 125 #define AHD_TMODE_ENABLE 0 126 #endif 127 128 #define AHD_BUILD_COL_IDX(target, lun) \ 129 (((lun) << 4) | target) 130 131 #define AHD_GET_SCB_COL_IDX(ahd, scb) \ 132 ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb)) 133 134 #define AHD_SET_SCB_COL_IDX(scb, col_idx) \ 135 do { \ 136 (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \ 137 (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \ 138 } while (0) 139 140 #define AHD_COPY_SCB_COL_IDX(dst, src) \ 141 do { \ 142 dst->hscb->scsiid = src->hscb->scsiid; \ 143 dst->hscb->lun = src->hscb->lun; \ 144 } while (0) 145 146 #define AHD_NEVER_COL_IDX 0xFFFF 147 148 /**************************** Driver Constants ********************************/ 149 /* 150 * The maximum number of supported targets. 151 */ 152 #define AHD_NUM_TARGETS 16 153 154 /* 155 * The maximum number of supported luns. 156 * The identify message only supports 64 luns in non-packetized transfers. 157 * You can have 2^64 luns when information unit transfers are enabled, 158 * but until we see a need to support that many, we support 256. 159 */ 160 #define AHD_NUM_LUNS_NONPKT 64 161 #define AHD_NUM_LUNS 256 162 163 /* 164 * The maximum transfer per S/G segment. 165 */ 166 #define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 167 168 /* 169 * The maximum amount of SCB storage in hardware on a controller. 170 * This value represents an upper bound. Due to software design, 171 * we may not be able to use this number. 172 */ 173 #define AHD_SCB_MAX 512 174 175 /* 176 * The maximum number of concurrent transactions supported per driver instance. 177 * Sequencer Control Blocks (SCBs) store per-transaction information. 178 */ 179 #define AHD_MAX_QUEUE AHD_SCB_MAX 180 181 /* 182 * Define the size of our QIN and QOUT FIFOs. They must be a power of 2 183 * in size and accomodate as many transactions as can be queued concurrently. 184 */ 185 #define AHD_QIN_SIZE AHD_MAX_QUEUE 186 #define AHD_QOUT_SIZE AHD_MAX_QUEUE 187 188 #define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1)) 189 /* 190 * The maximum amount of SCB storage we allocate in host memory. 191 */ 192 #define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE 193 194 /* 195 * Ring Buffer of incoming target commands. 196 * We allocate 256 to simplify the logic in the sequencer 197 * by using the natural wrap point of an 8bit counter. 198 */ 199 #define AHD_TMODE_CMDS 256 200 201 /* Reset line assertion time in us */ 202 #define AHD_BUSRESET_DELAY 25 203 204 /******************* Chip Characteristics/Operating Settings *****************/ 205 /* 206 * Chip Type 207 * The chip order is from least sophisticated to most sophisticated. 208 */ 209 typedef enum { 210 AHD_NONE = 0x0000, 211 AHD_CHIPID_MASK = 0x00FF, 212 AHD_AIC7901 = 0x0001, 213 AHD_AIC7902 = 0x0002, 214 AHD_AIC7901A = 0x0003, 215 AHD_PCI = 0x0100, /* Bus type PCI */ 216 AHD_PCIX = 0x0200, /* Bus type PCIX */ 217 AHD_BUS_MASK = 0x0F00 218 } ahd_chip; 219 220 /* 221 * Features available in each chip type. 222 */ 223 typedef enum { 224 AHD_FENONE = 0x00000, 225 AHD_WIDE = 0x00001,/* Wide Channel */ 226 AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */ 227 AHD_TARGETMODE = 0x01000,/* Has tested target mode support */ 228 AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */ 229 AHD_RTI = 0x04000,/* Retained Training Support */ 230 AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */ 231 AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */ 232 AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/ 233 AHD_AIC7901_FE = AHD_FENONE, 234 AHD_AIC7902_FE = AHD_MULTI_FUNC 235 } ahd_feature; 236 237 /* 238 * Bugs in the silicon that we work around in software. 239 */ 240 typedef enum { 241 AHD_BUGNONE = 0x0000, 242 /* 243 * Rev A hardware fails to update LAST/CURR/NEXTSCB 244 * correctly in certain packetized selection cases. 245 */ 246 AHD_SENT_SCB_UPDATE_BUG = 0x0001, 247 /* The wrong SCB is accessed to check the abort pending bit. */ 248 AHD_ABORT_LQI_BUG = 0x0002, 249 /* Packetized bitbucket crosses packet boundaries. */ 250 AHD_PKT_BITBUCKET_BUG = 0x0004, 251 /* The selection timer runs twice as long as its setting. */ 252 AHD_LONG_SETIMO_BUG = 0x0008, 253 /* The Non-LQ CRC error status is delayed until phase change. */ 254 AHD_NLQICRC_DELAYED_BUG = 0x0010, 255 /* The chip must be reset for all outgoing bus resets. */ 256 AHD_SCSIRST_BUG = 0x0020, 257 /* Some PCIX fields must be saved and restored across chip reset. */ 258 AHD_PCIX_CHIPRST_BUG = 0x0040, 259 /* MMAPIO is not functional in PCI-X mode. */ 260 AHD_PCIX_MMAPIO_BUG = 0x0080, 261 /* Bug workarounds that can be disabled on non-PCIX busses. */ 262 AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG 263 | AHD_PCIX_MMAPIO_BUG, 264 /* 265 * LQOSTOP0 status set even for forced selections with ATN 266 * to perform non-packetized message delivery. 267 */ 268 AHD_LQO_ATNO_BUG = 0x0100, 269 /* FIFO auto-flush does not always trigger. */ 270 AHD_AUTOFLUSH_BUG = 0x0200, 271 /* The CLRLQO registers are not self-clearing. */ 272 AHD_CLRLQO_AUTOCLR_BUG = 0x0400, 273 /* The PACKETIZED status bit refers to the previous connection. */ 274 AHD_PKTIZED_STATUS_BUG = 0x0800, 275 /* "Short Luns" are not placed into outgoing LQ packets correctly. */ 276 AHD_PKT_LUN_BUG = 0x1000, 277 /* 278 * Only the FIFO allocated to the non-packetized connection may 279 * be in use during a non-packetzied connection. 280 */ 281 AHD_NONPACKFIFO_BUG = 0x2000, 282 /* 283 * Writing to a DFF SCBPTR register may fail if concurent with 284 * a hardware write to the other DFF SCBPTR register. This is 285 * not currently a concern in our sequencer since all chips with 286 * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern 287 * occur in non-packetized connections. 288 */ 289 AHD_MDFF_WSCBPTR_BUG = 0x4000, 290 /* SGHADDR updates are slow. */ 291 AHD_REG_SLOW_SETTLE_BUG = 0x8000, 292 /* 293 * Changing the MODE_PTR coincident with an interrupt that 294 * switches to a different mode will cause the interrupt to 295 * be in the mode written outside of interrupt context. 296 */ 297 AHD_SET_MODE_BUG = 0x10000, 298 /* Non-packetized busfree revision does not work. */ 299 AHD_BUSFREEREV_BUG = 0x20000, 300 /* 301 * Paced transfers are indicated with a non-standard PPR 302 * option bit in the neg table, 160MHz is indicated by 303 * sync factor 0x7, and the offset if off by a factor of 2. 304 */ 305 AHD_PACED_NEGTABLE_BUG = 0x40000, 306 /* LQOOVERRUN false positives. */ 307 AHD_LQOOVERRUN_BUG = 0x80000, 308 /* 309 * Controller write to INTSTAT will lose to a host 310 * write to CLRINT. 311 */ 312 AHD_INTCOLLISION_BUG = 0x100000, 313 /* 314 * The GEM318 violates the SCSI spec by not waiting 315 * the mandated bus settle delay between phase changes 316 * in some situations. Some aic79xx chip revs. are more 317 * strict in this regard and will treat REQ assertions 318 * that fall within the bus settle delay window as 319 * glitches. This flag tells the firmware to tolerate 320 * early REQ assertions. 321 */ 322 AHD_EARLY_REQ_BUG = 0x200000 323 } ahd_bug; 324 325 /* 326 * Configuration specific settings. 327 * The driver determines these settings by probing the 328 * chip/controller's configuration. 329 */ 330 typedef enum { 331 AHD_FNONE = 0x00000, 332 AHD_PRIMARY_CHANNEL = 0x00003,/* 333 * The channel that should 334 * be probed first. 335 */ 336 AHD_USEDEFAULTS = 0x00004,/* 337 * For cards without an seeprom 338 * or a BIOS to initialize the chip's 339 * SRAM, we use the default target 340 * settings. 341 */ 342 AHD_SEQUENCER_DEBUG = 0x00008, 343 AHD_RESET_BUS_A = 0x00010, 344 AHD_EXTENDED_TRANS_A = 0x00020, 345 AHD_TERM_ENB_A = 0x00040, 346 AHD_SPCHK_ENB_A = 0x00080, 347 AHD_STPWLEVEL_A = 0x00100, 348 AHD_INITIATORROLE = 0x00200,/* 349 * Allow initiator operations on 350 * this controller. 351 */ 352 AHD_TARGETROLE = 0x00400,/* 353 * Allow target operations on this 354 * controller. 355 */ 356 AHD_RESOURCE_SHORTAGE = 0x00800, 357 AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */ 358 AHD_INT50_SPEEDFLEX = 0x02000,/* 359 * Internal 50pin connector 360 * sits behind an aic3860 361 */ 362 AHD_BIOS_ENABLED = 0x04000, 363 AHD_ALL_INTERRUPTS = 0x08000, 364 AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */ 365 AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */ 366 AHD_CURRENT_SENSING = 0x40000, 367 AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */ 368 AHD_HP_BOARD = 0x100000, 369 AHD_RESET_POLL_ACTIVE = 0x200000, 370 AHD_UPDATE_PEND_CMDS = 0x400000, 371 AHD_RUNNING_QOUTFIFO = 0x800000 372 } ahd_flag; 373 374 /************************* Hardware SCB Definition ***************************/ 375 376 /* 377 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 378 * consists of a "hardware SCB" mirroring the fields availible on the card 379 * and additional information the kernel stores for each transaction. 380 * 381 * To minimize space utilization, a portion of the hardware scb stores 382 * different data during different portions of a SCSI transaction. 383 * As initialized by the host driver for the initiator role, this area 384 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 385 * the cdb has been presented to the target, this area serves to store 386 * residual transfer information and the SCSI status byte. 387 * For the target role, the contents of this area do not change, but 388 * still serve a different purpose than for the initiator role. See 389 * struct target_data for details. 390 */ 391 392 /* 393 * Status information embedded in the shared poriton of 394 * an SCB after passing the cdb to the target. The kernel 395 * driver will only read this data for transactions that 396 * complete abnormally. 397 */ 398 struct initiator_status { 399 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 400 uint32_t residual_sgptr; /* The next S/G for this transfer */ 401 uint8_t scsi_status; /* Standard SCSI status byte */ 402 }; 403 404 struct target_status { 405 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 406 uint32_t residual_sgptr; /* The next S/G for this transfer */ 407 uint8_t scsi_status; /* SCSI status to give to initiator */ 408 uint8_t target_phases; /* Bitmap of phases to execute */ 409 uint8_t data_phase; /* Data-In or Data-Out */ 410 uint8_t initiator_tag; /* Initiator's transaction tag */ 411 }; 412 413 /* 414 * Initiator mode SCB shared data area. 415 * If the embedded CDB is 12 bytes or less, we embed 416 * the sense buffer address in the SCB. This allows 417 * us to retrieve sense information without interrupting 418 * the host in packetized mode. 419 */ 420 typedef uint32_t sense_addr_t; 421 #define MAX_CDB_LEN 16 422 #define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t)) 423 union initiator_data { 424 struct { 425 uint64_t cdbptr; 426 uint8_t cdblen; 427 } cdb_from_host; 428 uint8_t cdb[MAX_CDB_LEN]; 429 struct { 430 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR]; 431 sense_addr_t sense_addr; 432 } cdb_plus_saddr; 433 }; 434 435 /* 436 * Target mode version of the shared data SCB segment. 437 */ 438 struct target_data { 439 uint32_t spare[2]; 440 uint8_t scsi_status; /* SCSI status to give to initiator */ 441 uint8_t target_phases; /* Bitmap of phases to execute */ 442 uint8_t data_phase; /* Data-In or Data-Out */ 443 uint8_t initiator_tag; /* Initiator's transaction tag */ 444 }; 445 446 struct hardware_scb { 447 /*0*/ union { 448 union initiator_data idata; 449 struct target_data tdata; 450 struct initiator_status istatus; 451 struct target_status tstatus; 452 } shared_data; 453 /* 454 * A word about residuals. 455 * The scb is presented to the sequencer with the dataptr and datacnt 456 * fields initialized to the contents of the first S/G element to 457 * transfer. The sgptr field is initialized to the bus address for 458 * the S/G element that follows the first in the in core S/G array 459 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 460 * S/G entry for this transfer (single S/G element transfer with the 461 * first elements address and length preloaded in the dataptr/datacnt 462 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 463 * The SG_FULL_RESID flag ensures that the residual will be correctly 464 * noted even if no data transfers occur. Once the data phase is entered, 465 * the residual sgptr and datacnt are loaded from the sgptr and the 466 * datacnt fields. After each S/G element's dataptr and length are 467 * loaded into the hardware, the residual sgptr is advanced. After 468 * each S/G element is expired, its datacnt field is checked to see 469 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 470 * residual sg ptr and the transfer is considered complete. If the 471 * sequencer determines that there is a residual in the tranfer, or 472 * there is non-zero status, it will set the SG_STATUS_VALID flag in 473 * sgptr and dma the scb back into host memory. To sumarize: 474 * 475 * Sequencer: 476 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 477 * or residual_sgptr does not have SG_LIST_NULL set. 478 * 479 * o We are transfering the last segment if residual_datacnt has 480 * the SG_LAST_SEG flag set. 481 * 482 * Host: 483 * o A residual can only have occurred if a completed scb has the 484 * SG_STATUS_VALID flag set. Inspection of the SCSI status field, 485 * the residual_datacnt, and the residual_sgptr field will tell 486 * for sure. 487 * 488 * o residual_sgptr and sgptr refer to the "next" sg entry 489 * and so may point beyond the last valid sg entry for the 490 * transfer. 491 */ 492 #define SG_PTR_MASK 0xFFFFFFF8 493 /*16*/ uint16_t tag; 494 /*18*/ uint8_t cdb_len; 495 /*19*/ uint8_t task_management; 496 /*20*/ uint32_t next_hscb_busaddr; 497 /*24*/ uint64_t dataptr; 498 /*32*/ uint32_t datacnt; /* Byte 3 is spare. */ 499 /*36*/ uint32_t sgptr; 500 /*40*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */ 501 /*41*/ uint8_t scsiid; /* 502 * Selection out Id 503 * Our Id (bits 0-3) Their ID (bits 4-7) 504 */ 505 /*42*/ uint8_t lun; 506 /*43*/ uint8_t task_attribute; 507 /*44*/ uint32_t hscb_busaddr; 508 /******* Long lun field only downloaded for full 8 byte lun support *******/ 509 /*48*/ uint8_t pkt_long_lun[8]; 510 /******* Fields below are not Downloaded (Sequencer may use for scratch) ******/ 511 /*56*/ uint8_t spare[8]; 512 }; 513 514 /************************ Kernel SCB Definitions ******************************/ 515 /* 516 * Some fields of the SCB are OS dependent. Here we collect the 517 * definitions for elements that all OS platforms need to include 518 * in there SCB definition. 519 */ 520 521 /* 522 * Definition of a scatter/gather element as transfered to the controller. 523 * The aic7xxx chips only support a 24bit length. We use the top byte of 524 * the length to store additional address bits and a flag to indicate 525 * that a given segment terminates the transfer. This gives us an 526 * addressable range of 512GB on machines with 64bit PCI or with chips 527 * that can support dual address cycles on 32bit PCI busses. 528 */ 529 struct ahd_dma_seg { 530 uint32_t addr; 531 uint32_t len; 532 #define AHD_DMA_LAST_SEG 0x80000000 533 #define AHD_SG_HIGH_ADDR_MASK 0x7F000000 534 #define AHD_SG_LEN_MASK 0x00FFFFFF 535 }; 536 537 struct ahd_dma64_seg { 538 uint64_t addr; 539 uint32_t len; 540 uint32_t pad; 541 }; 542 543 struct map_node { 544 bus_dmamap_t dmamap; 545 bus_addr_t physaddr; 546 uint8_t *vaddr; 547 SLIST_ENTRY(map_node) links; 548 }; 549 550 /* 551 * The current state of this SCB. 552 */ 553 typedef enum { 554 SCB_FLAG_NONE = 0x00000, 555 SCB_TRANSMISSION_ERROR = 0x00001,/* 556 * We detected a parity or CRC 557 * error that has effected the 558 * payload of the command. This 559 * flag is checked when normal 560 * status is returned to catch 561 * the case of a target not 562 * responding to our attempt 563 * to report the error. 564 */ 565 SCB_OTHERTCL_TIMEOUT = 0x00002,/* 566 * Another device was active 567 * during the first timeout for 568 * this SCB so we gave ourselves 569 * an additional timeout period 570 * in case it was hogging the 571 * bus. 572 */ 573 SCB_DEVICE_RESET = 0x00004, 574 SCB_SENSE = 0x00008, 575 SCB_CDB32_PTR = 0x00010, 576 SCB_RECOVERY_SCB = 0x00020, 577 SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */ 578 SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */ 579 SCB_ABORT = 0x00100, 580 SCB_ACTIVE = 0x00200, 581 SCB_TARGET_IMMEDIATE = 0x00400, 582 SCB_PACKETIZED = 0x00800, 583 SCB_EXPECT_PPR_BUSFREE = 0x01000, 584 SCB_PKT_SENSE = 0x02000, 585 SCB_CMDPHASE_ABORT = 0x04000, 586 SCB_ON_COL_LIST = 0x08000, 587 SCB_SILENT = 0x10000 /* 588 * Be quiet about transmission type 589 * errors. They are expected and we 590 * don't want to upset the user. This 591 * flag is typically used during DV. 592 */ 593 } scb_flag; 594 595 struct scb { 596 struct hardware_scb *hscb; 597 union { 598 SLIST_ENTRY(scb) sle; 599 LIST_ENTRY(scb) le; 600 TAILQ_ENTRY(scb) tqe; 601 } links; 602 union { 603 SLIST_ENTRY(scb) sle; 604 LIST_ENTRY(scb) le; 605 TAILQ_ENTRY(scb) tqe; 606 } links2; 607 #define pending_links links2.le 608 #define collision_links links2.le 609 struct scb *col_scb; 610 ahd_io_ctx_t io_ctx; 611 struct ahd_softc *ahd_softc; 612 scb_flag flags; 613 #ifndef __linux__ 614 bus_dmamap_t dmamap; 615 #endif 616 struct scb_platform_data *platform_data; 617 struct map_node *hscb_map; 618 struct map_node *sg_map; 619 struct map_node *sense_map; 620 void *sg_list; 621 uint8_t *sense_data; 622 bus_addr_t sg_list_busaddr; 623 bus_addr_t sense_busaddr; 624 u_int sg_count;/* How full ahd_dma_seg is */ 625 #define AHD_MAX_LQ_CRC_ERRORS 5 626 u_int crc_retry_count; 627 }; 628 629 TAILQ_HEAD(scb_tailq, scb); 630 LIST_HEAD(scb_list, scb); 631 632 struct scb_data { 633 /* 634 * TAILQ of lists of free SCBs grouped by device 635 * collision domains. 636 */ 637 struct scb_tailq free_scbs; 638 639 /* 640 * Per-device lists of SCBs whose tag ID would collide 641 * with an already active tag on the device. 642 */ 643 struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT]; 644 645 /* 646 * SCBs that will not collide with any active device. 647 */ 648 struct scb_list any_dev_free_scb_list; 649 650 /* 651 * Mapping from tag to SCB. 652 */ 653 struct scb *scbindex[AHD_SCB_MAX]; 654 655 /* 656 * "Bus" addresses of our data structures. 657 */ 658 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 659 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 660 bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */ 661 SLIST_HEAD(, map_node) hscb_maps; 662 SLIST_HEAD(, map_node) sg_maps; 663 SLIST_HEAD(, map_node) sense_maps; 664 int scbs_left; /* unallocated scbs in head map_node */ 665 int sgs_left; /* unallocated sgs in head map_node */ 666 int sense_left; /* unallocated sense in head map_node */ 667 uint16_t numscbs; 668 uint16_t maxhscbs; /* Number of SCBs on the card */ 669 uint8_t init_level; /* 670 * How far we've initialized 671 * this structure. 672 */ 673 }; 674 675 /************************ Target Mode Definitions *****************************/ 676 677 /* 678 * Connection desciptor for select-in requests in target mode. 679 */ 680 struct target_cmd { 681 uint8_t scsiid; /* Our ID and the initiator's ID */ 682 uint8_t identify; /* Identify message */ 683 uint8_t bytes[22]; /* 684 * Bytes contains any additional message 685 * bytes terminated by 0xFF. The remainder 686 * is the cdb to execute. 687 */ 688 uint8_t cmd_valid; /* 689 * When a command is complete, the firmware 690 * will set cmd_valid to all bits set. 691 * After the host has seen the command, 692 * the bits are cleared. This allows us 693 * to just peek at host memory to determine 694 * if more work is complete. cmd_valid is on 695 * an 8 byte boundary to simplify setting 696 * it on aic7880 hardware which only has 697 * limited direct access to the DMA FIFO. 698 */ 699 uint8_t pad[7]; 700 }; 701 702 /* 703 * Number of events we can buffer up if we run out 704 * of immediate notify ccbs. 705 */ 706 #define AHD_TMODE_EVENT_BUFFER_SIZE 8 707 struct ahd_tmode_event { 708 uint8_t initiator_id; 709 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 710 #define EVENT_TYPE_BUS_RESET 0xFF 711 uint8_t event_arg; 712 }; 713 714 /* 715 * Per enabled lun target mode state. 716 * As this state is directly influenced by the host OS'es target mode 717 * environment, we let the OS module define it. Forward declare the 718 * structure here so we can store arrays of them, etc. in OS neutral 719 * data structures. 720 */ 721 #ifdef AHD_TARGET_MODE 722 struct ahd_tmode_lstate { 723 struct cam_path *path; 724 struct ccb_hdr_slist accept_tios; 725 struct ccb_hdr_slist immed_notifies; 726 struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE]; 727 uint8_t event_r_idx; 728 uint8_t event_w_idx; 729 }; 730 #else 731 struct ahd_tmode_lstate; 732 #endif 733 734 /******************** Transfer Negotiation Datastructures *********************/ 735 #define AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */ 736 #define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 737 #define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */ 738 #define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */ 739 #define AHD_PERIOD_10MHz 0x19 740 741 #define AHD_WIDTH_UNKNOWN 0xFF 742 #define AHD_PERIOD_UNKNOWN 0xFF 743 #define AHD_OFFSET_UNKNOWN 0xFF 744 #define AHD_PPR_OPTS_UNKNOWN 0xFF 745 746 /* 747 * Transfer Negotiation Information. 748 */ 749 struct ahd_transinfo { 750 uint8_t protocol_version; /* SCSI Revision level */ 751 uint8_t transport_version; /* SPI Revision level */ 752 uint8_t width; /* Bus width */ 753 uint8_t period; /* Sync rate factor */ 754 uint8_t offset; /* Sync offset */ 755 uint8_t ppr_options; /* Parallel Protocol Request options */ 756 }; 757 758 /* 759 * Per-initiator current, goal and user transfer negotiation information. */ 760 struct ahd_initiator_tinfo { 761 struct ahd_transinfo curr; 762 struct ahd_transinfo goal; 763 struct ahd_transinfo user; 764 }; 765 766 /* 767 * Per enabled target ID state. 768 * Pointers to lun target state as well as sync/wide negotiation information 769 * for each initiator<->target mapping. For the initiator role we pretend 770 * that we are the target and the targets are the initiators since the 771 * negotiation is the same regardless of role. 772 */ 773 struct ahd_tmode_tstate { 774 struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS]; 775 struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS]; 776 777 /* 778 * Per initiator state bitmasks. 779 */ 780 uint16_t auto_negotiate;/* Auto Negotiation Required */ 781 uint16_t discenable; /* Disconnection allowed */ 782 uint16_t tagenable; /* Tagged Queuing allowed */ 783 }; 784 785 /* 786 * Points of interest along the negotiated transfer scale. 787 */ 788 #define AHD_SYNCRATE_160 0x8 789 #define AHD_SYNCRATE_PACED 0x8 790 #define AHD_SYNCRATE_DT 0x9 791 #define AHD_SYNCRATE_ULTRA2 0xa 792 #define AHD_SYNCRATE_ULTRA 0xc 793 #define AHD_SYNCRATE_FAST 0x19 794 #define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST 795 #define AHD_SYNCRATE_SYNC 0x32 796 #define AHD_SYNCRATE_MIN 0x60 797 #define AHD_SYNCRATE_ASYNC 0xFF 798 #define AHD_SYNCRATE_MAX AHD_SYNCRATE_160 799 800 /* Safe and valid period for async negotiations. */ 801 #define AHD_ASYNC_XFER_PERIOD 0x44 802 803 /* 804 * In RevA, the synctable uses a 120MHz rate for the period 805 * factor 8 and 160MHz for the period factor 7. The 120MHz 806 * rate never made it into the official SCSI spec, so we must 807 * compensate when setting the negotiation table for Rev A 808 * parts. 809 */ 810 #define AHD_SYNCRATE_REVA_120 0x8 811 #define AHD_SYNCRATE_REVA_160 0x7 812 813 /***************************** Lookup Tables **********************************/ 814 /* 815 * Phase -> name and message out response 816 * to parity errors in each phase table. 817 */ 818 struct ahd_phase_table_entry { 819 uint8_t phase; 820 uint8_t mesg_out; /* Message response to parity errors */ 821 char *phasemsg; 822 }; 823 824 /************************** Serial EEPROM Format ******************************/ 825 826 struct seeprom_config { 827 /* 828 * Per SCSI ID Configuration Flags 829 */ 830 uint16_t device_flags[16]; /* words 0-15 */ 831 #define CFXFER 0x003F /* synchronous transfer rate */ 832 #define CFXFER_ASYNC 0x3F 833 #define CFQAS 0x0040 /* Negotiate QAS */ 834 #define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */ 835 #define CFSTART 0x0100 /* send start unit SCSI command */ 836 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 837 #define CFDISC 0x0400 /* enable disconnection */ 838 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 839 #define CFWIDEB 0x1000 /* wide bus device */ 840 #define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */ 841 842 /* 843 * BIOS Control Bits 844 */ 845 uint16_t bios_control; /* word 16 */ 846 #define CFSUPREM 0x0001 /* support all removeable drives */ 847 #define CFSUPREMB 0x0002 /* support removeable boot drives */ 848 #define CFBIOSSTATE 0x000C /* BIOS Action State */ 849 #define CFBS_DISABLED 0x00 850 #define CFBS_ENABLED 0x04 851 #define CFBS_DISABLED_SCAN 0x08 852 #define CFENABLEDV 0x0010 /* Perform Domain Validation */ 853 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 854 #define CFSPARITY 0x0040 /* SCSI parity */ 855 #define CFEXTEND 0x0080 /* extended translation enabled */ 856 #define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */ 857 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 858 #define CFMSG_VERBOSE 0x0000 859 #define CFMSG_SILENT 0x0200 860 #define CFMSG_DIAG 0x0400 861 #define CFRESETB 0x0800 /* reset SCSI bus at boot */ 862 /* UNUSED 0xf000 */ 863 864 /* 865 * Host Adapter Control Bits 866 */ 867 uint16_t adapter_control; /* word 17 */ 868 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 869 #define CFSTERM 0x0002 /* SCSI low byte termination */ 870 #define CFWSTERM 0x0004 /* SCSI high byte termination */ 871 #define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/ 872 #define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */ 873 #define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */ 874 #define CFSTPWLEVEL 0x0040 /* Termination level control */ 875 #define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */ 876 #define CFTERM_MENU 0x0100 /* BIOS displays termination menu */ 877 #define CFCLUSTERENB 0x8000 /* Cluster Enable */ 878 879 /* 880 * Bus Release Time, Host Adapter ID 881 */ 882 uint16_t brtime_id; /* word 18 */ 883 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 884 /* UNUSED 0x00f0 */ 885 #define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */ 886 887 /* 888 * Maximum targets 889 */ 890 uint16_t max_targets; /* word 19 */ 891 #define CFMAXTARG 0x00ff /* maximum targets */ 892 #define CFBOOTLUN 0x0f00 /* Lun to boot from */ 893 #define CFBOOTID 0xf000 /* Target to boot from */ 894 uint16_t res_1[10]; /* words 20-29 */ 895 uint16_t signature; /* BIOS Signature */ 896 #define CFSIGNATURE 0x400 897 uint16_t checksum; /* word 31 */ 898 }; 899 900 /****************************** Flexport Logic ********************************/ 901 #define FLXADDR_TERMCTL 0x0 902 #define FLX_TERMCTL_ENSECHIGH 0x8 903 #define FLX_TERMCTL_ENSECLOW 0x4 904 #define FLX_TERMCTL_ENPRIHIGH 0x2 905 #define FLX_TERMCTL_ENPRILOW 0x1 906 #define FLXADDR_ROMSTAT_CURSENSECTL 0x1 907 #define FLX_ROMSTAT_SEECFG 0xF0 908 #define FLX_ROMSTAT_EECFG 0x0F 909 #define FLX_ROMSTAT_SEE_93C66 0x00 910 #define FLX_ROMSTAT_SEE_NONE 0xF0 911 #define FLX_ROMSTAT_EE_512x8 0x0 912 #define FLX_ROMSTAT_EE_1MBx8 0x1 913 #define FLX_ROMSTAT_EE_2MBx8 0x2 914 #define FLX_ROMSTAT_EE_4MBx8 0x3 915 #define FLX_ROMSTAT_EE_16MBx8 0x4 916 #define CURSENSE_ENB 0x1 917 #define FLXADDR_FLEXSTAT 0x2 918 #define FLX_FSTAT_BUSY 0x1 919 #define FLXADDR_CURRENT_STAT 0x4 920 #define FLX_CSTAT_SEC_HIGH 0xC0 921 #define FLX_CSTAT_SEC_LOW 0x30 922 #define FLX_CSTAT_PRI_HIGH 0x0C 923 #define FLX_CSTAT_PRI_LOW 0x03 924 #define FLX_CSTAT_MASK 0x03 925 #define FLX_CSTAT_SHIFT 2 926 #define FLX_CSTAT_OKAY 0x0 927 #define FLX_CSTAT_OVER 0x1 928 #define FLX_CSTAT_UNDER 0x2 929 #define FLX_CSTAT_INVALID 0x3 930 931 int ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 932 u_int start_addr, u_int count); 933 934 int ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 935 u_int start_addr, u_int count); 936 int ahd_wait_seeprom(struct ahd_softc *ahd); 937 int ahd_verify_cksum(struct seeprom_config *sc); 938 int ahd_acquire_seeprom(struct ahd_softc *ahd); 939 void ahd_release_seeprom(struct ahd_softc *ahd); 940 941 /**************************** Message Buffer *********************************/ 942 typedef enum { 943 MSG_FLAG_NONE = 0x00, 944 MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01, 945 MSG_FLAG_IU_REQ_CHANGED = 0x02, 946 MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04, 947 MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08, 948 MSG_FLAG_PACKETIZED = 0x10 949 } ahd_msg_flags; 950 951 typedef enum { 952 MSG_TYPE_NONE = 0x00, 953 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 954 MSG_TYPE_INITIATOR_MSGIN = 0x02, 955 MSG_TYPE_TARGET_MSGOUT = 0x03, 956 MSG_TYPE_TARGET_MSGIN = 0x04 957 } ahd_msg_type; 958 959 typedef enum { 960 MSGLOOP_IN_PROG, 961 MSGLOOP_MSGCOMPLETE, 962 MSGLOOP_TERMINATED 963 } msg_loop_stat; 964 965 /*********************** Software Configuration Structure *********************/ 966 struct ahd_suspend_channel_state { 967 uint8_t scsiseq; 968 uint8_t sxfrctl0; 969 uint8_t sxfrctl1; 970 uint8_t simode0; 971 uint8_t simode1; 972 uint8_t seltimer; 973 uint8_t seqctl; 974 }; 975 976 struct ahd_suspend_state { 977 struct ahd_suspend_channel_state channel[2]; 978 uint8_t optionmode; 979 uint8_t dscommand0; 980 uint8_t dspcistatus; 981 /* hsmailbox */ 982 uint8_t crccontrol1; 983 uint8_t scbbaddr; 984 /* Host and sequencer SCB counts */ 985 uint8_t dff_thrsh; 986 uint8_t *scratch_ram; 987 uint8_t *btt; 988 }; 989 990 typedef void (*ahd_bus_intr_t)(struct ahd_softc *); 991 992 typedef enum { 993 AHD_MODE_DFF0, 994 AHD_MODE_DFF1, 995 AHD_MODE_CCHAN, 996 AHD_MODE_SCSI, 997 AHD_MODE_CFG, 998 AHD_MODE_UNKNOWN 999 } ahd_mode; 1000 1001 #define AHD_MK_MSK(x) (0x01 << (x)) 1002 #define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0) 1003 #define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1) 1004 #define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN) 1005 #define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI) 1006 #define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG) 1007 #define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN) 1008 #define AHD_MODE_ANY_MSK (~0) 1009 1010 typedef uint8_t ahd_mode_state; 1011 1012 typedef void ahd_callback_t (void *); 1013 1014 struct ahd_softc { 1015 bus_space_tag_t tags[2]; 1016 bus_space_handle_t bshs[2]; 1017 #ifndef __linux__ 1018 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 1019 #endif 1020 struct scb_data scb_data; 1021 1022 struct hardware_scb *next_queued_hscb; 1023 1024 /* 1025 * SCBs that have been sent to the controller 1026 */ 1027 LIST_HEAD(, scb) pending_scbs; 1028 1029 /* 1030 * Current register window mode information. 1031 */ 1032 ahd_mode dst_mode; 1033 ahd_mode src_mode; 1034 1035 /* 1036 * Saved register window mode information 1037 * used for restore on next unpause. 1038 */ 1039 ahd_mode saved_dst_mode; 1040 ahd_mode saved_src_mode; 1041 1042 /* 1043 * Platform specific data. 1044 */ 1045 struct ahd_platform_data *platform_data; 1046 1047 /* 1048 * Platform specific device information. 1049 */ 1050 ahd_dev_softc_t dev_softc; 1051 1052 /* 1053 * Bus specific device information. 1054 */ 1055 ahd_bus_intr_t bus_intr; 1056 1057 /* 1058 * Target mode related state kept on a per enabled lun basis. 1059 * Targets that are not enabled will have null entries. 1060 * As an initiator, we keep one target entry for our initiator 1061 * ID to store our sync/wide transfer settings. 1062 */ 1063 struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS]; 1064 1065 /* 1066 * The black hole device responsible for handling requests for 1067 * disabled luns on enabled targets. 1068 */ 1069 struct ahd_tmode_lstate *black_hole; 1070 1071 /* 1072 * Device instance currently on the bus awaiting a continue TIO 1073 * for a command that was not given the disconnect priveledge. 1074 */ 1075 struct ahd_tmode_lstate *pending_device; 1076 1077 /* 1078 * Timer handles for timer driven callbacks. 1079 */ 1080 ahd_timer_t reset_timer; 1081 ahd_timer_t stat_timer; 1082 1083 /* 1084 * Statistics. 1085 */ 1086 #define AHD_STAT_UPDATE_US 250000 /* 250ms */ 1087 #define AHD_STAT_BUCKETS 4 1088 u_int cmdcmplt_bucket; 1089 uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS]; 1090 uint32_t cmdcmplt_total; 1091 1092 /* 1093 * Card characteristics 1094 */ 1095 ahd_chip chip; 1096 ahd_feature features; 1097 ahd_bug bugs; 1098 ahd_flag flags; 1099 struct seeprom_config *seep_config; 1100 1101 /* Values to store in the SEQCTL register for pause and unpause */ 1102 uint8_t unpause; 1103 uint8_t pause; 1104 1105 /* Command Queues */ 1106 uint16_t qoutfifonext; 1107 uint16_t qoutfifonext_valid_tag; 1108 uint16_t qinfifonext; 1109 uint16_t qinfifo[AHD_SCB_MAX]; 1110 uint16_t *qoutfifo; 1111 1112 /* Critical Section Data */ 1113 struct cs *critical_sections; 1114 u_int num_critical_sections; 1115 1116 /* Buffer for handling packetized bitbucket. */ 1117 uint8_t *overrun_buf; 1118 1119 /* Links for chaining softcs */ 1120 TAILQ_ENTRY(ahd_softc) links; 1121 1122 /* Channel Names ('A', 'B', etc.) */ 1123 char channel; 1124 1125 /* Initiator Bus ID */ 1126 uint8_t our_id; 1127 1128 /* 1129 * Target incoming command FIFO. 1130 */ 1131 struct target_cmd *targetcmds; 1132 uint8_t tqinfifonext; 1133 1134 /* 1135 * Cached verson of the hs_mailbox so we can avoid 1136 * pausing the sequencer during mailbox updates. 1137 */ 1138 uint8_t hs_mailbox; 1139 1140 /* 1141 * Incoming and outgoing message handling. 1142 */ 1143 uint8_t send_msg_perror; 1144 ahd_msg_flags msg_flags; 1145 ahd_msg_type msg_type; 1146 uint8_t msgout_buf[12];/* Message we are sending */ 1147 uint8_t msgin_buf[12];/* Message we are receiving */ 1148 u_int msgout_len; /* Length of message to send */ 1149 u_int msgout_index; /* Current index in msgout */ 1150 u_int msgin_index; /* Current index in msgin */ 1151 1152 /* 1153 * Mapping information for data structures shared 1154 * between the sequencer and kernel. 1155 */ 1156 bus_dma_tag_t parent_dmat; 1157 bus_dma_tag_t shared_data_dmat; 1158 bus_dmamap_t shared_data_dmamap; 1159 bus_addr_t shared_data_busaddr; 1160 1161 /* Information saved through suspend/resume cycles */ 1162 struct ahd_suspend_state suspend_state; 1163 1164 /* Number of enabled target mode device on this card */ 1165 u_int enabled_luns; 1166 1167 /* Initialization level of this data structure */ 1168 u_int init_level; 1169 1170 /* PCI cacheline size. */ 1171 u_int pci_cachesize; 1172 1173 /* IO Cell Parameters */ 1174 uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS]; 1175 1176 u_int stack_size; 1177 uint16_t *saved_stack; 1178 1179 /* Per-Unit descriptive information */ 1180 const char *description; 1181 const char *bus_description; 1182 char *name; 1183 int unit; 1184 1185 /* Selection Timer settings */ 1186 int seltime; 1187 1188 /* 1189 * Interrupt coalessing settings. 1190 */ 1191 #define AHD_INT_COALESSING_TIMER_DEFAULT 250 /*us*/ 1192 #define AHD_INT_COALESSING_MAXCMDS_DEFAULT 10 1193 #define AHD_INT_COALESSING_MAXCMDS_MAX 127 1194 #define AHD_INT_COALESSING_MINCMDS_DEFAULT 5 1195 #define AHD_INT_COALESSING_MINCMDS_MAX 127 1196 #define AHD_INT_COALESSING_THRESHOLD_DEFAULT 2000 1197 #define AHD_INT_COALESSING_STOP_THRESHOLD_DEFAULT 1000 1198 u_int int_coalessing_timer; 1199 u_int int_coalessing_maxcmds; 1200 u_int int_coalessing_mincmds; 1201 u_int int_coalessing_threshold; 1202 u_int int_coalessing_stop_threshold; 1203 1204 uint16_t user_discenable;/* Disconnection allowed */ 1205 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1206 }; 1207 1208 TAILQ_HEAD(ahd_softc_tailq, ahd_softc); 1209 extern struct ahd_softc_tailq ahd_tailq; 1210 1211 /*************************** IO Cell Configuration ****************************/ 1212 #define AHD_PRECOMP_SLEW_INDEX \ 1213 (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0) 1214 1215 #define AHD_AMPLITUDE_INDEX \ 1216 (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0) 1217 1218 #define AHD_SET_SLEWRATE(ahd, new_slew) \ 1219 do { \ 1220 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK; \ 1221 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1222 (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK); \ 1223 } while (0) 1224 1225 #define AHD_SET_PRECOMP(ahd, new_pcomp) \ 1226 do { \ 1227 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; \ 1228 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1229 (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK); \ 1230 } while (0) 1231 1232 #define AHD_SET_AMPLITUDE(ahd, new_amp) \ 1233 do { \ 1234 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \ 1235 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |= \ 1236 (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK); \ 1237 } while (0) 1238 1239 /************************ Active Device Information ***************************/ 1240 typedef enum { 1241 ROLE_UNKNOWN, 1242 ROLE_INITIATOR, 1243 ROLE_TARGET 1244 } role_t; 1245 1246 struct ahd_devinfo { 1247 int our_scsiid; 1248 int target_offset; 1249 uint16_t target_mask; 1250 u_int target; 1251 u_int lun; 1252 char channel; 1253 role_t role; /* 1254 * Only guaranteed to be correct if not 1255 * in the busfree state. 1256 */ 1257 }; 1258 1259 /****************************** PCI Structures ********************************/ 1260 #define AHD_PCI_IOADDR0 PCIR_MAPS /* I/O BAR*/ 1261 #define AHD_PCI_MEMADDR (PCIR_MAPS + 4) /* Memory BAR */ 1262 #define AHD_PCI_IOADDR1 (PCIR_MAPS + 12)/* Second I/O BAR */ 1263 1264 typedef int (ahd_device_setup_t)(struct ahd_softc *); 1265 1266 struct ahd_pci_identity { 1267 uint64_t full_id; 1268 uint64_t id_mask; 1269 char *name; 1270 ahd_device_setup_t *setup; 1271 }; 1272 extern struct ahd_pci_identity ahd_pci_ident_table []; 1273 extern const u_int ahd_num_pci_devs; 1274 1275 /***************************** VL/EISA Declarations ***************************/ 1276 struct aic7770_identity { 1277 uint32_t full_id; 1278 uint32_t id_mask; 1279 char *name; 1280 ahd_device_setup_t *setup; 1281 }; 1282 extern struct aic7770_identity aic7770_ident_table []; 1283 extern const int ahd_num_aic7770_devs; 1284 1285 #define AHD_EISA_SLOT_OFFSET 0xc00 1286 #define AHD_EISA_IOSIZE 0x100 1287 1288 /*************************** Function Declarations ****************************/ 1289 /******************************************************************************/ 1290 void ahd_reset_cmds_pending(struct ahd_softc *ahd); 1291 u_int ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl); 1292 void ahd_busy_tcl(struct ahd_softc *ahd, 1293 u_int tcl, u_int busyid); 1294 static __inline void ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl); 1295 static __inline void 1296 ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl) 1297 { 1298 ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL); 1299 } 1300 1301 /***************************** PCI Front End *********************************/ 1302 struct ahd_pci_identity *ahd_find_pci_device(ahd_dev_softc_t); 1303 int ahd_pci_config(struct ahd_softc *, 1304 struct ahd_pci_identity *); 1305 int ahd_pci_test_register_access(struct ahd_softc *); 1306 1307 /************************** SCB and SCB queue management **********************/ 1308 int ahd_probe_scbs(struct ahd_softc *); 1309 void ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, 1310 struct scb *scb); 1311 int ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, 1312 int target, char channel, int lun, 1313 u_int tag, role_t role); 1314 1315 /****************************** Initialization ********************************/ 1316 struct ahd_softc *ahd_alloc(void *platform_arg, char *name); 1317 int ahd_softc_init(struct ahd_softc *); 1318 void ahd_controller_info(struct ahd_softc *ahd, char *buf); 1319 int ahd_init(struct ahd_softc *ahd); 1320 int ahd_default_config(struct ahd_softc *ahd); 1321 int ahd_parse_cfgdata(struct ahd_softc *ahd, 1322 struct seeprom_config *sc); 1323 void ahd_intr_enable(struct ahd_softc *ahd, int enable); 1324 void ahd_update_coalessing_values(struct ahd_softc *ahd, 1325 u_int timer, 1326 u_int maxcmds, 1327 u_int mincmds); 1328 void ahd_enable_coalessing(struct ahd_softc *ahd, 1329 int enable); 1330 void ahd_pause_and_flushwork(struct ahd_softc *ahd); 1331 int ahd_suspend(struct ahd_softc *ahd); 1332 int ahd_resume(struct ahd_softc *ahd); 1333 void ahd_softc_insert(struct ahd_softc *); 1334 struct ahd_softc *ahd_find_softc(struct ahd_softc *ahd); 1335 void ahd_set_unit(struct ahd_softc *, int); 1336 void ahd_set_name(struct ahd_softc *, char *); 1337 struct scb *ahd_get_scb(struct ahd_softc *ahd, u_int col_idx); 1338 void ahd_free_scb(struct ahd_softc *ahd, struct scb *scb); 1339 void ahd_alloc_scbs(struct ahd_softc *ahd); 1340 void ahd_free(struct ahd_softc *ahd); 1341 int ahd_reset(struct ahd_softc *ahd); 1342 void ahd_shutdown(void *arg); 1343 int ahd_write_flexport(struct ahd_softc *ahd, 1344 u_int addr, u_int value); 1345 int ahd_read_flexport(struct ahd_softc *ahd, u_int addr, 1346 uint8_t *value); 1347 int ahd_wait_flexport(struct ahd_softc *ahd); 1348 1349 /*************************** Interrupt Services *******************************/ 1350 void ahd_pci_intr(struct ahd_softc *ahd); 1351 void ahd_clear_intstat(struct ahd_softc *ahd); 1352 void ahd_flush_qoutfifo(struct ahd_softc *ahd); 1353 void ahd_run_qoutfifo(struct ahd_softc *ahd); 1354 #ifdef AHD_TARGET_MODE 1355 void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused); 1356 #endif 1357 void ahd_handle_hwerrint(struct ahd_softc *ahd); 1358 void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat); 1359 void ahd_handle_scsiint(struct ahd_softc *ahd, 1360 u_int intstat); 1361 void ahd_clear_critical_section(struct ahd_softc *ahd); 1362 1363 /***************************** Error Recovery *********************************/ 1364 typedef enum { 1365 SEARCH_COMPLETE, 1366 SEARCH_COUNT, 1367 SEARCH_REMOVE, 1368 SEARCH_PRINT 1369 } ahd_search_action; 1370 int ahd_search_qinfifo(struct ahd_softc *ahd, int target, 1371 char channel, int lun, u_int tag, 1372 role_t role, uint32_t status, 1373 ahd_search_action action); 1374 int ahd_search_disc_list(struct ahd_softc *ahd, int target, 1375 char channel, int lun, u_int tag, 1376 int stop_on_first, int remove, 1377 int save_state); 1378 void ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb); 1379 int ahd_reset_channel(struct ahd_softc *ahd, char channel, 1380 int initiate_reset); 1381 int ahd_abort_scbs(struct ahd_softc *ahd, int target, 1382 char channel, int lun, u_int tag, 1383 role_t role, uint32_t status); 1384 void ahd_restart(struct ahd_softc *ahd); 1385 void ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo); 1386 void ahd_handle_scb_status(struct ahd_softc *ahd, 1387 struct scb *scb); 1388 void ahd_handle_scsi_status(struct ahd_softc *ahd, 1389 struct scb *scb); 1390 void ahd_calc_residual(struct ahd_softc *ahd, 1391 struct scb *scb); 1392 /*************************** Utility Functions ********************************/ 1393 struct ahd_phase_table_entry* 1394 ahd_lookup_phase_entry(int phase); 1395 void ahd_compile_devinfo(struct ahd_devinfo *devinfo, 1396 u_int our_id, u_int target, 1397 u_int lun, char channel, 1398 role_t role); 1399 /************************** Transfer Negotiation ******************************/ 1400 void ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 1401 u_int *ppr_options, u_int maxsync); 1402 void ahd_validate_offset(struct ahd_softc *ahd, 1403 struct ahd_initiator_tinfo *tinfo, 1404 u_int period, u_int *offset, 1405 int wide, role_t role); 1406 void ahd_validate_width(struct ahd_softc *ahd, 1407 struct ahd_initiator_tinfo *tinfo, 1408 u_int *bus_width, 1409 role_t role); 1410 /* 1411 * Negotiation types. These are used to qualify if we should renegotiate 1412 * even if our goal and current transport parameters are identical. 1413 */ 1414 typedef enum { 1415 AHD_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1416 AHD_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1417 AHD_NEG_ALWAYS /* Renegotiat even if goal is async. */ 1418 } ahd_neg_type; 1419 int ahd_update_neg_request(struct ahd_softc*, 1420 struct ahd_devinfo*, 1421 struct ahd_tmode_tstate*, 1422 struct ahd_initiator_tinfo*, 1423 ahd_neg_type); 1424 void ahd_set_width(struct ahd_softc *ahd, 1425 struct ahd_devinfo *devinfo, 1426 u_int width, u_int type, int paused); 1427 void ahd_set_syncrate(struct ahd_softc *ahd, 1428 struct ahd_devinfo *devinfo, 1429 u_int period, u_int offset, 1430 u_int ppr_options, 1431 u_int type, int paused); 1432 typedef enum { 1433 AHD_QUEUE_NONE, 1434 AHD_QUEUE_BASIC, 1435 AHD_QUEUE_TAGGED 1436 } ahd_queue_alg; 1437 1438 void ahd_set_tags(struct ahd_softc *ahd, 1439 struct ahd_devinfo *devinfo, 1440 ahd_queue_alg alg); 1441 1442 /**************************** Target Mode *************************************/ 1443 #ifdef AHD_TARGET_MODE 1444 void ahd_send_lstate_events(struct ahd_softc *, 1445 struct ahd_tmode_lstate *); 1446 void ahd_handle_en_lun(struct ahd_softc *ahd, 1447 struct cam_sim *sim, union ccb *ccb); 1448 cam_status ahd_find_tmode_devs(struct ahd_softc *ahd, 1449 struct cam_sim *sim, union ccb *ccb, 1450 struct ahd_tmode_tstate **tstate, 1451 struct ahd_tmode_lstate **lstate, 1452 int notfound_failure); 1453 #ifndef AHD_TMODE_ENABLE 1454 #define AHD_TMODE_ENABLE 0 1455 #endif 1456 #endif 1457 /******************************* Debug ***************************************/ 1458 #ifdef AHD_DEBUG 1459 extern uint32_t ahd_debug; 1460 #define AHD_SHOW_MISC 0x00001 1461 #define AHD_SHOW_SENSE 0x00002 1462 #define AHD_SHOW_RECOVERY 0x00004 1463 #define AHD_DUMP_SEEPROM 0x00008 1464 #define AHD_SHOW_TERMCTL 0x00010 1465 #define AHD_SHOW_MEMORY 0x00020 1466 #define AHD_SHOW_MESSAGES 0x00040 1467 #define AHD_SHOW_MODEPTR 0x00080 1468 #define AHD_SHOW_SELTO 0x00100 1469 #define AHD_SHOW_FIFOS 0x00200 1470 #define AHD_SHOW_QFULL 0x00400 1471 #define AHD_SHOW_DV 0x00800 1472 #define AHD_SHOW_MASKED_ERRORS 0x01000 1473 #define AHD_SHOW_QUEUE 0x02000 1474 #define AHD_SHOW_TQIN 0x04000 1475 #define AHD_SHOW_SG 0x08000 1476 #define AHD_SHOW_INT_COALESSING 0x10000 1477 #define AHD_DEBUG_SEQUENCER 0x20000 1478 #endif 1479 void ahd_print_scb(struct scb *scb); 1480 void ahd_print_devinfo(struct ahd_softc *ahd, 1481 struct ahd_devinfo *devinfo); 1482 void ahd_dump_sglist(struct scb *scb); 1483 void ahd_dump_all_cards_state(void); 1484 void ahd_dump_card_state(struct ahd_softc *ahd); 1485 int ahd_print_register(ahd_reg_parse_entry_t *table, 1486 u_int num_entries, 1487 const char *name, 1488 u_int address, 1489 u_int value, 1490 u_int *cur_column, 1491 u_int wrap_point); 1492 void ahd_dump_scbs(struct ahd_softc *ahd); 1493 #endif /* _AIC79XX_H_ */ 1494