1 /* 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2001 Justin T. Gibbs. 5 * Copyright (c) 2000-2001 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#47 $ 41 * 42 * $FreeBSD$ 43 */ 44 45 #ifndef _AIC79XX_H_ 46 #define _AIC79XX_H_ 47 48 /* Register Definitions */ 49 #include "aic79xx_reg.h" 50 51 /************************* Forward Declarations *******************************/ 52 struct ahd_platform_data; 53 struct scb_platform_data; 54 55 /****************************** Useful Macros *********************************/ 56 #ifndef MAX 57 #define MAX(a,b) (((a) > (b)) ? (a) : (b)) 58 #endif 59 60 #ifndef MIN 61 #define MIN(a,b) (((a) < (b)) ? (a) : (b)) 62 #endif 63 64 #ifndef TRUE 65 #define TRUE 1 66 #endif 67 #ifndef FALSE 68 #define FALSE 0 69 #endif 70 71 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 72 73 #define ALL_CHANNELS '\0' 74 #define ALL_TARGETS_MASK 0xFFFF 75 #define INITIATOR_WILDCARD (~0) 76 #define SCB_LIST_NULL 0xFF00 77 #define SCB_LIST_NULL_LE (ahd_htole16(SCB_LIST_NULL)) 78 #define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL) 79 80 #define SCSIID_TARGET(ahd, scsiid) \ 81 (((scsiid) & TID) >> TID_SHIFT) 82 #define SCSIID_OUR_ID(scsiid) \ 83 ((scsiid) & OID) 84 #define SCSIID_CHANNEL(ahd, scsiid) ('A') 85 #define SCB_IS_SCSIBUS_B(ahd, scb) (0) 86 #define SCB_GET_OUR_ID(scb) \ 87 SCSIID_OUR_ID((scb)->hscb->scsiid) 88 #define SCB_GET_TARGET(ahd, scb) \ 89 SCSIID_TARGET((ahd), (scb)->hscb->scsiid) 90 #define SCB_GET_CHANNEL(ahd, scb) \ 91 SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid) 92 #define SCB_GET_LUN(scb) \ 93 ((scb)->hscb->lun) 94 #define SCB_GET_TARGET_OFFSET(ahd, scb) \ 95 SCB_GET_TARGET(ahd, scb) 96 #define SCB_GET_TARGET_MASK(ahd, scb) \ 97 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb))) 98 /* 99 * TCLs have the following format: TTTTLLLLLLLL 100 */ 101 #define TCL_TARGET_OFFSET(tcl) \ 102 ((((tcl) >> 4) & TID) >> 4) 103 #define TCL_LUN(tcl) \ 104 (tcl & (AHD_NUM_LUNS_NONPKT - 1)) 105 #define BUILD_TCL(scsiid, lun) \ 106 ((lun) | (((scsiid) & TID) << 4)) 107 #define BUILD_TCL_RAW(target, channel, lun) \ 108 ((lun) | ((target) << 8)) 109 110 #define SCB_GET_TAG(scb) \ 111 ahd_le16toh(scb->hscb->tag) 112 113 #ifndef AHD_TARGET_MODE 114 #undef AHD_TMODE_ENABLE 115 #define AHD_TMODE_ENABLE 0 116 #endif 117 118 /**************************** Driver Constants ********************************/ 119 /* 120 * The maximum number of supported targets. 121 */ 122 #define AHD_NUM_TARGETS 16 123 124 /* 125 * The maximum number of supported luns. 126 * The identify message only supports 64 luns in non-packetized transfers. 127 * You can have 2^64 luns when information unit transfers are enabled, 128 * but until we see a need to support that many, we support 256. 129 */ 130 #define AHD_NUM_LUNS_NONPKT 64 131 #define AHD_NUM_LUNS 256 132 133 /* 134 * The maximum transfer per S/G segment. 135 */ 136 #define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 137 138 /* 139 * The maximum amount of SCB storage in hardware on a controller. 140 * This value represents an upper bound. Due to software design, 141 * we may not be able to use this number. 142 */ 143 #define AHD_SCB_MAX 512 144 145 /* 146 * The maximum number of concurrent transactions supported per driver instance. 147 * Sequencer Control Blocks (SCBs) store per-transaction information. 148 * We are limited to 510 because: 149 * 1) SCB storage space holds us to at most 512. 150 * 2) Our input queue scheme requires one SCB to always be reserved 151 * in advance of queuing any SCBs. This takes us down to 511. 152 * 3) To handle our output queue correctly on machines that only 153 * support 32bit stores, we must clear the array 4 bytes at a 154 * time. To avoid colliding with a DMA write from the sequencer, 155 * we must be sure that 2, 16bit slots are empty when we write to 156 * clear the queue. This restricts us to only 511 SCBs: 1 that 157 * just completed and the known additional empty slot in the queue 158 * that precedes it. 159 #define AHD_MAX_QUEUE 510 160 */ 161 #define AHD_MAX_QUEUE 255 162 163 /* 164 * Define the size of our QIN and QOUT FIFOs. They must be a power of 2 165 * in size and accomodate as many transactions as can be queued concurrently. 166 */ 167 #define AHD_QIN_SIZE 512 168 #define AHD_QOUT_SIZE 512 169 170 #define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1)) 171 #define AHD_QOUT_WRAP(x) ((x) & (AHD_QOUT_SIZE-1)) 172 173 /* 174 * The maximum amount of SCB storage we allocate in host memory. This 175 * number should reflect the 1 additional SCB we require to handle our 176 * qinfifo mechanism. 177 */ 178 #define AHD_SCB_MAX_ALLOC (AHD_MAX_QUEUE+1) 179 180 /* 181 * Ring Buffer of incoming target commands. 182 * We allocate 256 to simplify the logic in the sequencer 183 * by using the natural wrap point of an 8bit counter. 184 */ 185 #define AHD_TMODE_CMDS 256 186 187 /* Reset line assertion time in us */ 188 #define AHD_BUSRESET_DELAY 250 189 190 /******************* Chip Characteristics/Operating Settings *****************/ 191 /* 192 * Chip Type 193 * The chip order is from least sophisticated to most sophisticated. 194 */ 195 typedef enum { 196 AHD_NONE = 0x0000, 197 AHD_CHIPID_MASK = 0x00FF, 198 AHD_AIC7901 = 0x0001, 199 AHD_AIC7902 = 0x0002, 200 AHD_PCI = 0x0100, /* Bus type PCI */ 201 AHD_PCIX = 0x0200, /* Bus type PCIX */ 202 AHD_BUS_MASK = 0x0F00 203 } ahd_chip; 204 205 /* 206 * Features available in each chip type. 207 */ 208 typedef enum { 209 AHD_FENONE = 0x00000, 210 AHD_WIDE = 0x00001, /* Wide Channel */ 211 AHD_MULTI_FUNC = 0x00100, /* Multi-Function Twin Channel Device */ 212 AHD_TARGETMODE = 0x01000, /* Has tested target mode support */ 213 AHD_MULTIROLE = 0x02000, /* Space for two roles at a time */ 214 AHD_REMOVABLE = 0x00000, /* Hot-Swap supported - None so far*/ 215 AHD_AIC7901_FE = AHD_FENONE, 216 AHD_AIC7902_FE = AHD_MULTI_FUNC 217 } ahd_feature; 218 219 /* 220 * Bugs in the silicon that we work around in software. 221 */ 222 typedef enum { 223 AHD_BUGNONE = 0x0000, 224 AHD_SENT_SCB_UPDATE_BUG = 0x0001, 225 AHD_ABORT_LQI_BUG = 0x0002, 226 AHD_PKT_BITBUCKET_BUG = 0x0004, 227 AHD_LONG_SETIMO_BUG = 0x0008, 228 AHD_NLQICRC_DELAYED_BUG = 0x0010, 229 AHD_SCSIRST_BUG = 0x0020, 230 AHD_PCIX_ARBITER_BUG = 0x0040, 231 AHD_PCIX_SPLIT_BUG = 0x0080, 232 AHD_PCIX_CHIPRST_BUG = 0x0100, 233 AHD_PCIX_MMAPIO_BUG = 0x0200, 234 /* Bug workarounds that can be disabled on non-PCIX busses. */ 235 AHD_PCIX_BUG_MASK = AHD_PCIX_ARBITER_BUG 236 | AHD_PCIX_SPLIT_BUG 237 | AHD_PCIX_CHIPRST_BUG 238 | AHD_PCIX_MMAPIO_BUG, 239 AHD_LQO_ATNO_BUG = 0x0400, 240 AHD_AUTOFLUSH_BUG = 0x0800, 241 AHD_CLRLQO_AUTOCLR_BUG = 0x1000, 242 AHD_PKTIZED_STATUS_BUG = 0x2000 243 } ahd_bug; 244 245 /* 246 * Configuration specific settings. 247 * The driver determines these settings by probing the 248 * chip/controller's configuration. 249 */ 250 typedef enum { 251 AHD_FNONE = 0x00000, 252 AHD_PRIMARY_CHANNEL = 0x00003,/* 253 * The channel that should 254 * be probed first. 255 */ 256 AHD_USEDEFAULTS = 0x00004,/* 257 * For cards without an seeprom 258 * or a BIOS to initialize the chip's 259 * SRAM, we use the default target 260 * settings. 261 */ 262 AHD_SEQUENCER_DEBUG = 0x00008, 263 AHD_RESET_BUS_A = 0x00010, 264 AHD_EXTENDED_TRANS_A = 0x00020, 265 AHD_TERM_ENB_A = 0x00040, 266 AHD_SPCHK_ENB_A = 0x00080, 267 AHD_STPWLEVEL_A = 0x00100, 268 AHD_INITIATORROLE = 0x00200,/* 269 * Allow initiator operations on 270 * this controller. 271 */ 272 AHD_TARGETROLE = 0x00400,/* 273 * Allow target operations on this 274 * controller. 275 */ 276 AHD_RESOURCE_SHORTAGE = 0x00800, 277 AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */ 278 AHD_INT50_SPEEDFLEX = 0x02000,/* 279 * Internal 50pin connector 280 * sits behind an aic3860 281 */ 282 AHD_BIOS_ENABLED = 0x04000, 283 AHD_ALL_INTERRUPTS = 0x08000, 284 AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */ 285 AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */ 286 AHD_CURRENT_SENSING = 0x40000, 287 AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */ 288 AHD_CPQ_BOARD = 0x100000 289 } ahd_flag; 290 291 /************************* Hardware SCB Definition ***************************/ 292 293 /* 294 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 295 * consists of a "hardware SCB" mirroring the fields availible on the card 296 * and additional information the kernel stores for each transaction. 297 * 298 * To minimize space utilization, a portion of the hardware scb stores 299 * different data during different portions of a SCSI transaction. 300 * As initialized by the host driver for the initiator role, this area 301 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 302 * the cdb has been presented to the target, this area serves to store 303 * residual transfer information and the SCSI status byte. 304 * For the target role, the contents of this area do not change, but 305 * still serve a different purpose than for the initiator role. See 306 * struct target_data for details. 307 */ 308 309 /* 310 * Status information embedded in the shared poriton of 311 * an SCB after passing the cdb to the target. The kernel 312 * driver will only read this data for transactions that 313 * complete abnormally. 314 */ 315 struct initiator_status { 316 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 317 uint32_t residual_sgptr; /* The next S/G for this transfer */ 318 uint8_t scsi_status; /* Standard SCSI status byte */ 319 }; 320 321 struct target_status { 322 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 323 uint32_t residual_sgptr; /* The next S/G for this transfer */ 324 uint8_t scsi_status; /* SCSI status to give to initiator */ 325 uint8_t target_phases; /* Bitmap of phases to execute */ 326 uint8_t data_phase; /* Data-In or Data-Out */ 327 uint8_t initiator_tag; /* Initiator's transaction tag */ 328 }; 329 330 /* 331 * Initiator mode SCB shared data area. 332 * If the embedded CDB is 12 bytes or less, we embed 333 * the sense buffer address in the SCB. This allows 334 * us to retrieve sense information without interupting 335 * the host in packetized mode. 336 */ 337 typedef uint32_t sense_addr_t; 338 #define MAX_CDB_LEN 16 339 #define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t)) 340 union initiator_data { 341 uint64_t cdbptr; 342 uint8_t cdb[MAX_CDB_LEN]; 343 struct { 344 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR]; 345 sense_addr_t sense_addr; 346 } cdb_plus_saddr; 347 }; 348 349 /* 350 * Target mode version of the shared data SCB segment. 351 */ 352 struct target_data { 353 uint32_t spare[2]; 354 uint8_t scsi_status; /* SCSI status to give to initiator */ 355 uint8_t target_phases; /* Bitmap of phases to execute */ 356 uint8_t data_phase; /* Data-In or Data-Out */ 357 uint8_t initiator_tag; /* Initiator's transaction tag */ 358 }; 359 360 struct hardware_scb { 361 /*0*/ union { 362 union initiator_data idata; 363 struct target_data tdata; 364 struct initiator_status istatus; 365 struct target_status tstatus; 366 } shared_data; 367 /* 368 * A word about residuals. 369 * The scb is presented to the sequencer with the dataptr and datacnt 370 * fields initialized to the contents of the first S/G element to 371 * transfer. The sgptr field is initialized to the bus address for 372 * the S/G element that follows the first in the in core S/G array 373 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 374 * S/G entry for this transfer (single S/G element transfer with the 375 * first elements address and length preloaded in the dataptr/datacnt 376 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 377 * The SG_FULL_RESID flag ensures that the residual will be correctly 378 * noted even if no data transfers occur. Once the data phase is entered, 379 * the residual sgptr and datacnt are loaded from the sgptr and the 380 * datacnt fields. After each S/G element's dataptr and length are 381 * loaded into the hardware, the residual sgptr is advanced. After 382 * each S/G element is expired, its datacnt field is checked to see 383 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 384 * residual sg ptr and the transfer is considered complete. If the 385 * sequencer determines that there is a residual in the tranfer, or 386 * there is non-zero status, it will set the SG_STATUS_VALID flag in 387 * sgptr and dma the scb back into host memory. To sumarize: 388 * 389 * Sequencer: 390 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 391 * or residual_sgptr does not have SG_LIST_NULL set. 392 * 393 * o We are transfering the last segment if residual_datacnt has 394 * the SG_LAST_SEG flag set. 395 * 396 * Host: 397 * o A residual can only have occurred if a completed scb has the 398 * SG_STATUS_VALID flag set. Inspection of the SCSI status field, 399 * the residual_datacnt, and the residual_sgptr field will tell 400 * for sure. 401 * 402 * o residual_sgptr and sgptr refer to the "next" sg entry 403 * and so may point beyond the last valid sg entry for the 404 * transfer. 405 */ 406 #define SG_PTR_MASK 0xFFFFFFF8 407 /*16*/ uint8_t cdb_len; 408 /*17*/ uint8_t task_management; 409 /*18*/ uint16_t tag; 410 /*20*/ uint32_t next_hscb_busaddr; 411 /*24*/ uint64_t dataptr; 412 /*32*/ uint32_t datacnt; /* Byte 3 is spare. */ 413 /*36*/ uint32_t sgptr; 414 /*40*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */ 415 /*41*/ uint8_t scsiid; /* 416 * Selection out Id 417 * Our Id (bits 0-3) Their ID (bits 4-7) 418 */ 419 /*42*/ uint8_t lun; 420 /*43*/ uint8_t task_attribute_nonpkt_tag; 421 /*44*/ uint32_t hscb_busaddr; 422 /******* Fields below are not Downloaded (Sequencer may use for scratch) ******/ 423 /*48*/ uint8_t spare[16]; 424 }; 425 426 /************************ Kernel SCB Definitions ******************************/ 427 /* 428 * Some fields of the SCB are OS dependent. Here we collect the 429 * definitions for elements that all OS platforms need to include 430 * in there SCB definition. 431 */ 432 433 /* 434 * Definition of a scatter/gather element as transfered to the controller. 435 * The aic7xxx chips only support a 24bit length. We use the top byte of 436 * the length to store additional address bits and a flag to indicate 437 * that a given segment terminates the transfer. This gives us an 438 * addressable range of 512GB on machines with 64bit PCI or with chips 439 * that can support dual address cycles on 32bit PCI busses. 440 */ 441 struct ahd_dma_seg { 442 uint32_t addr; 443 uint32_t len; 444 #define AHD_DMA_LAST_SEG 0x80000000 445 #define AHD_SG_HIGH_ADDR_MASK 0x7F000000 446 #define AHD_SG_LEN_MASK 0x00FFFFFF 447 }; 448 449 struct ahd_dma64_seg { 450 uint64_t addr; 451 uint32_t len; 452 uint32_t pad; 453 }; 454 455 struct map_node { 456 bus_dmamap_t dmamap; 457 bus_addr_t physaddr; 458 uint8_t *vaddr; 459 SLIST_ENTRY(map_node) links; 460 }; 461 462 /* 463 * The current state of this SCB. 464 */ 465 typedef enum { 466 SCB_FREE = 0x0000, 467 SCB_TRANSMISSION_ERROR = 0x0001,/* 468 * We detected a parity or CRC 469 * error that has effected the 470 * payload of the command. This 471 * flag is checked when normal 472 * status is returned to catch 473 * the case of a target not 474 * responding to our attempt 475 * to report the error. 476 */ 477 SCB_OTHERTCL_TIMEOUT = 0x0002,/* 478 * Another device was active 479 * during the first timeout for 480 * this SCB so we gave ourselves 481 * an additional timeout period 482 * in case it was hogging the 483 * bus. 484 */ 485 SCB_DEVICE_RESET = 0x0004, 486 SCB_SENSE = 0x0008, 487 SCB_CDB32_PTR = 0x0010, 488 SCB_RECOVERY_SCB = 0x0020, 489 SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */ 490 SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */ 491 SCB_ABORT = 0x0100, 492 SCB_UNTAGGEDQ = 0x0200, 493 SCB_ACTIVE = 0x0400, 494 SCB_TARGET_IMMEDIATE = 0x0800, 495 SCB_PACKETIZED = 0x1000, 496 SCB_EXPECT_PPR_BUSFREE = 0x2000, 497 SCB_PKT_SENSE = 0x4000, 498 SCB_CMDPHASE_ABORT = 0x8000 499 } scb_flag; 500 501 struct scb { 502 struct hardware_scb *hscb; 503 union { 504 SLIST_ENTRY(scb) sle; 505 TAILQ_ENTRY(scb) tqe; 506 } links; 507 LIST_ENTRY(scb) pending_links; 508 ahd_io_ctx_t io_ctx; 509 struct ahd_softc *ahd_softc; 510 scb_flag flags; 511 #ifndef __linux__ 512 bus_dmamap_t dmamap; 513 #endif 514 struct scb_platform_data *platform_data; 515 struct map_node *hscb_map; 516 struct map_node *sg_map; 517 struct map_node *sense_map; 518 void *sg_list; 519 uint8_t *sense_data; 520 bus_addr_t sg_list_busaddr; 521 bus_addr_t sense_busaddr; 522 u_int sg_count;/* How full ahd_dma_seg is */ 523 }; 524 525 struct scb_data { 526 SLIST_HEAD(, scb) free_scbs; /* 527 * Pool of SCBs ready to be assigned 528 * commands to execute. 529 */ 530 struct scb *scbindex[AHD_SCB_MAX]; 531 /* 532 * Mapping from tag to SCB. 533 */ 534 /* 535 * "Bus" addresses of our data structures. 536 */ 537 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 538 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 539 bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */ 540 SLIST_HEAD(, map_node) hscb_maps; 541 SLIST_HEAD(, map_node) sg_maps; 542 SLIST_HEAD(, map_node) sense_maps; 543 int scbs_left; /* unallocated scbs in head map_node */ 544 int sgs_left; /* unallocated sgs in head map_node */ 545 int sense_left; /* unallocated sense in head map_node */ 546 uint16_t numscbs; 547 uint16_t maxhscbs; /* Number of SCBs on the card */ 548 uint8_t init_level; /* 549 * How far we've initialized 550 * this structure. 551 */ 552 }; 553 554 /************************ Target Mode Definitions *****************************/ 555 556 /* 557 * Connection desciptor for select-in requests in target mode. 558 */ 559 struct target_cmd { 560 uint8_t scsiid; /* Our ID and the initiator's ID */ 561 uint8_t identify; /* Identify message */ 562 uint8_t bytes[22]; /* 563 * Bytes contains any additional message 564 * bytes terminated by 0xFF. The remainder 565 * is the cdb to execute. 566 */ 567 uint8_t cmd_valid; /* 568 * When a command is complete, the firmware 569 * will set cmd_valid to all bits set. 570 * After the host has seen the command, 571 * the bits are cleared. This allows us 572 * to just peek at host memory to determine 573 * if more work is complete. cmd_valid is on 574 * an 8 byte boundary to simplify setting 575 * it on aic7880 hardware which only has 576 * limited direct access to the DMA FIFO. 577 */ 578 uint8_t pad[7]; 579 }; 580 581 /* 582 * Number of events we can buffer up if we run out 583 * of immediate notify ccbs. 584 */ 585 #define AHD_TMODE_EVENT_BUFFER_SIZE 8 586 struct ahd_tmode_event { 587 uint8_t initiator_id; 588 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 589 #define EVENT_TYPE_BUS_RESET 0xFF 590 uint8_t event_arg; 591 }; 592 593 /* 594 * Per enabled lun target mode state. 595 * As this state is directly influenced by the host OS'es target mode 596 * environment, we let the OS module define it. Forward declare the 597 * structure here so we can store arrays of them, etc. in OS neutral 598 * data structures. 599 */ 600 #ifdef AHD_TARGET_MODE 601 struct ahd_tmode_lstate { 602 struct cam_path *path; 603 struct ccb_hdr_slist accept_tios; 604 struct ccb_hdr_slist immed_notifies; 605 struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE]; 606 uint8_t event_r_idx; 607 uint8_t event_w_idx; 608 }; 609 #else 610 struct ahd_tmode_lstate; 611 #endif 612 613 /******************** Transfer Negotiation Datastructures *********************/ 614 #define AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */ 615 #define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 616 #define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */ 617 #define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */ 618 #define AHD_PERIOD_ASYNC 0xFF 619 #define AHD_PERIOD_10MHz 0x19 620 621 /* 622 * Transfer Negotiation Information. 623 */ 624 struct ahd_transinfo { 625 uint8_t protocol_version; /* SCSI Revision level */ 626 uint8_t transport_version; /* SPI Revision level */ 627 uint8_t width; /* Bus width */ 628 uint8_t period; /* Sync rate factor */ 629 uint8_t offset; /* Sync offset */ 630 uint8_t ppr_options; /* Parallel Protocol Request options */ 631 }; 632 633 /* 634 * Per-initiator current, goal and user transfer negotiation information. */ 635 struct ahd_initiator_tinfo { 636 struct ahd_transinfo curr; 637 struct ahd_transinfo goal; 638 struct ahd_transinfo user; 639 }; 640 641 /* 642 * Per enabled target ID state. 643 * Pointers to lun target state as well as sync/wide negotiation information 644 * for each initiator<->target mapping. For the initiator role we pretend 645 * that we are the target and the targets are the initiators since the 646 * negotiation is the same regardless of role. 647 */ 648 struct ahd_tmode_tstate { 649 struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS]; 650 struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS]; 651 652 /* 653 * Per initiator state bitmasks. 654 */ 655 uint16_t auto_negotiate;/* Auto Negotiation Required */ 656 uint16_t discenable; /* Disconnection allowed */ 657 uint16_t tagenable; /* Tagged Queuing allowed */ 658 }; 659 660 /* 661 * Points of interest along the negotiated transfer scale. 662 */ 663 #define AHD_SYNCRATE_MAX 0x8 664 #define AHD_SYNCRATE_160 0x8 665 #define AHD_SYNCRATE_PACED 0x8 666 #define AHD_SYNCRATE_DT 0x9 667 #define AHD_SYNCRATE_ULTRA2 0xa 668 #define AHD_SYNCRATE_ULTRA 0xc 669 #define AHD_SYNCRATE_FAST 0x19 670 #define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST 671 #define AHD_SYNCRATE_SYNC 0x32 672 #define AHD_SYNCRATE_MIN 0x60 673 #define AHD_SYNCRATE_ASYNC 0xFF 674 675 /* 676 * In RevA, the synctable uses a 120MHz rate for the period 677 * factor 8 and 160MHz for the period factor 7. The 120MHz 678 * rate never made it into the official SCSI spec, so we must 679 * compensate when setting the negotiation table for Rev A 680 * parts. 681 */ 682 #define AHD_SYNCRATE_REVA_120 0x8 683 #define AHD_SYNCRATE_REVA_160 0x7 684 685 /***************************** Lookup Tables **********************************/ 686 /* 687 * Phase -> name and message out response 688 * to parity errors in each phase table. 689 */ 690 struct ahd_phase_table_entry { 691 uint8_t phase; 692 uint8_t mesg_out; /* Message response to parity errors */ 693 char *phasemsg; 694 }; 695 696 /************************** Serial EEPROM Format ******************************/ 697 698 struct seeprom_config { 699 /* 700 * Per SCSI ID Configuration Flags 701 */ 702 uint16_t device_flags[16]; /* words 0-15 */ 703 #define CFXFER 0x003F /* synchronous transfer rate */ 704 #define CFXFER_ASYNC 0x3F 705 #define CFQAS 0x0040 /* Negotiate QAS */ 706 #define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */ 707 #define CFSTART 0x0100 /* send start unit SCSI command */ 708 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 709 #define CFDISC 0x0400 /* enable disconnection */ 710 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 711 #define CFWIDEB 0x1000 /* wide bus device */ 712 #define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */ 713 714 /* 715 * BIOS Control Bits 716 */ 717 uint16_t bios_control; /* word 16 */ 718 #define CFSUPREM 0x0001 /* support all removeable drives */ 719 #define CFSUPREMB 0x0002 /* support removeable boot drives */ 720 #define CFBIOSSTATE 0x000C /* BIOS Action State */ 721 #define CFBS_DISABLED 0x00 722 #define CFBS_ENABLED 0x04 723 #define CFBS_DISABLED_SCAN 0x08 724 #define CFENABLEDV 0x0010 /* Perform Domain Validation */ 725 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 726 #define CFSPARITY 0x0040 /* SCSI parity */ 727 #define CFEXTEND 0x0080 /* extended translation enabled */ 728 #define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */ 729 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 730 #define CFMSG_VERBOSE 0x0000 731 #define CFMSG_SILENT 0x0200 732 #define CFMSG_DIAG 0x0400 733 #define CFRESETB 0x0800 /* reset SCSI bus at boot */ 734 /* UNUSED 0xf000 */ 735 736 /* 737 * Host Adapter Control Bits 738 */ 739 uint16_t adapter_control; /* word 17 */ 740 #define CFAUTOTERM 0x0001 /* Perform Auto termination */ 741 #define CFSTERM 0x0002 /* SCSI low byte termination */ 742 #define CFWSTERM 0x0004 /* SCSI high byte termination */ 743 #define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/ 744 #define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */ 745 #define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */ 746 #define CFSTPWLEVEL 0x0040 /* Termination level control */ 747 #define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */ 748 #define CFTERM_MENU 0x0100 /* BIOS displays termination menu */ 749 #define CFCLUSTERENB 0x8000 /* Cluster Enable */ 750 751 /* 752 * Bus Release Time, Host Adapter ID 753 */ 754 uint16_t brtime_id; /* word 18 */ 755 #define CFSCSIID 0x000f /* host adapter SCSI ID */ 756 /* UNUSED 0x00f0 */ 757 #define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */ 758 759 /* 760 * Maximum targets 761 */ 762 uint16_t max_targets; /* word 19 */ 763 #define CFMAXTARG 0x00ff /* maximum targets */ 764 #define CFBOOTLUN 0x0f00 /* Lun to boot from */ 765 #define CFBOOTID 0xf000 /* Target to boot from */ 766 uint16_t res_1[10]; /* words 20-29 */ 767 uint16_t signature; /* BIOS Signature */ 768 #define CFSIGNATURE 0x400 769 uint16_t checksum; /* word 31 */ 770 }; 771 772 /****************************** Flexport Logic ********************************/ 773 #define FLXADDR_TERMCTL 0x0 774 #define FLX_TERMCTL_ENSECHIGH 0x8 775 #define FLX_TERMCTL_ENSECLOW 0x4 776 #define FLX_TERMCTL_ENPRIHIGH 0x2 777 #define FLX_TERMCTL_ENPRILOW 0x1 778 #define FLXADDR_ROMSTAT_CURSENSECTL 0x1 779 #define FLX_ROMSTAT_SEECFG 0xF0 780 #define FLX_ROMSTAT_EECFG 0x0F 781 #define FLX_ROMSTAT_SEE_93C66 0x00 782 #define FLX_ROMSTAT_SEE_NONE 0xF0 783 #define FLX_ROMSTAT_EE_512x8 0x0 784 #define FLX_ROMSTAT_EE_1MBx8 0x1 785 #define FLX_ROMSTAT_EE_2MBx8 0x2 786 #define FLX_ROMSTAT_EE_4MBx8 0x3 787 #define FLX_ROMSTAT_EE_16MBx8 0x4 788 #define CURSENSE_ENB 0x1 789 #define FLXADDR_FLEXSTAT 0x2 790 #define FLX_FSTAT_BUSY 0x1 791 #define FLXADDR_CURRENT_STAT 0x4 792 #define FLX_CSTAT_SEC_HIGH 0xC0 793 #define FLX_CSTAT_SEC_LOW 0x30 794 #define FLX_CSTAT_PRI_HIGH 0x0C 795 #define FLX_CSTAT_PRI_LOW 0x03 796 #define FLX_CSTAT_MASK 0x03 797 #define FLX_CSTAT_SHIFT 2 798 #define FLX_CSTAT_OKAY 0x0 799 #define FLX_CSTAT_OVER 0x1 800 #define FLX_CSTAT_UNDER 0x2 801 #define FLX_CSTAT_INVALID 0x3 802 803 int ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 804 u_int start_addr, u_int count); 805 806 int ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 807 u_int start_addr, u_int count); 808 int ahd_wait_seeprom(struct ahd_softc *ahd); 809 int ahd_verify_cksum(struct seeprom_config *sc); 810 int ahd_acquire_seeprom(struct ahd_softc *ahd); 811 void ahd_release_seeprom(struct ahd_softc *ahd); 812 813 /**************************** Message Buffer *********************************/ 814 typedef enum { 815 MSG_FLAG_NONE = 0x00, 816 MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01, 817 MSG_FLAG_IU_REQ_CHANGED = 0x02, 818 MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04, 819 MSG_FLAG_PACKETIZED = 0x08 820 } ahd_msg_flags; 821 822 typedef enum { 823 MSG_TYPE_NONE = 0x00, 824 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 825 MSG_TYPE_INITIATOR_MSGIN = 0x02, 826 MSG_TYPE_TARGET_MSGOUT = 0x03, 827 MSG_TYPE_TARGET_MSGIN = 0x04 828 } ahd_msg_type; 829 830 typedef enum { 831 MSGLOOP_IN_PROG, 832 MSGLOOP_MSGCOMPLETE, 833 MSGLOOP_TERMINATED 834 } msg_loop_stat; 835 836 /*********************** Software Configuration Structure *********************/ 837 TAILQ_HEAD(scb_tailq, scb); 838 839 struct ahd_suspend_channel_state { 840 uint8_t scsiseq; 841 uint8_t sxfrctl0; 842 uint8_t sxfrctl1; 843 uint8_t simode0; 844 uint8_t simode1; 845 uint8_t seltimer; 846 uint8_t seqctl; 847 }; 848 849 struct ahd_suspend_state { 850 struct ahd_suspend_channel_state channel[2]; 851 uint8_t optionmode; 852 uint8_t dscommand0; 853 uint8_t dspcistatus; 854 /* hsmailbox */ 855 uint8_t crccontrol1; 856 uint8_t scbbaddr; 857 /* Host and sequencer SCB counts */ 858 uint8_t dff_thrsh; 859 uint8_t *scratch_ram; 860 uint8_t *btt; 861 }; 862 863 typedef void (*ahd_bus_intr_t)(struct ahd_softc *); 864 865 typedef enum { 866 AHD_MODE_DFF0, 867 AHD_MODE_DFF1, 868 AHD_MODE_CCHAN, 869 AHD_MODE_SCSI, 870 AHD_MODE_CFG, 871 AHD_MODE_UNKNOWN 872 } ahd_mode; 873 874 #define AHD_MK_MSK(x) (0x01 << (x)) 875 #define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0) 876 #define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1) 877 #define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN) 878 #define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI) 879 #define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG) 880 #define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN) 881 #define AHD_MODE_ANY_MSK (~0) 882 883 typedef uint8_t ahd_mode_state; 884 885 typedef void ahd_callback_t (void *); 886 887 struct ahd_softc { 888 bus_space_tag_t tags[2]; 889 bus_space_handle_t bshs[2]; 890 #ifndef __linux__ 891 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 892 #endif 893 struct scb_data scb_data; 894 895 struct scb *next_queued_scb; 896 897 /* 898 * SCBs that have been sent to the controller 899 */ 900 LIST_HEAD(, scb) pending_scbs; 901 902 /* 903 * Current register window mode information. 904 */ 905 ahd_mode dst_mode; 906 ahd_mode src_mode; 907 908 /* 909 * Saved register window mode information 910 * used for restore on next unpause. 911 */ 912 ahd_mode saved_dst_mode; 913 ahd_mode saved_src_mode; 914 915 /* 916 * Counting lock for deferring the release of additional 917 * untagged transactions from the untagged_queues. When 918 * the lock is decremented to 0, all queues in the 919 * untagged_queues array are run. 920 */ 921 u_int untagged_queue_lock; 922 923 /* 924 * Per-target queue of untagged-transactions. The 925 * transaction at the head of the queue is the 926 * currently pending untagged transaction for the 927 * target. The driver only allows a single untagged 928 * transaction per target. 929 */ 930 struct scb_tailq untagged_queues[AHD_NUM_TARGETS]; 931 932 /* 933 * Platform specific data. 934 */ 935 struct ahd_platform_data *platform_data; 936 937 /* 938 * Platform specific device information. 939 */ 940 ahd_dev_softc_t dev_softc; 941 942 /* 943 * Bus specific device information. 944 */ 945 ahd_bus_intr_t bus_intr; 946 947 /* 948 * Target mode related state kept on a per enabled lun basis. 949 * Targets that are not enabled will have null entries. 950 * As an initiator, we keep one target entry for our initiator 951 * ID to store our sync/wide transfer settings. 952 */ 953 struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS]; 954 955 /* 956 * The black hole device responsible for handling requests for 957 * disabled luns on enabled targets. 958 */ 959 struct ahd_tmode_lstate *black_hole; 960 961 /* 962 * Device instance currently on the bus awaiting a continue TIO 963 * for a command that was not given the disconnect priveledge. 964 */ 965 struct ahd_tmode_lstate *pending_device; 966 967 /* 968 * Timer handles for timer driven callbacks. 969 */ 970 ahd_timer_t reset_timer; 971 972 /* 973 * Card characteristics 974 */ 975 ahd_chip chip; 976 ahd_feature features; 977 ahd_bug bugs; 978 ahd_flag flags; 979 struct seeprom_config *seep_config; 980 981 /* Values to store in the SEQCTL register for pause and unpause */ 982 uint8_t unpause; 983 uint8_t pause; 984 985 /* Command Queues */ 986 uint16_t qoutfifonext; 987 uint16_t qinfifonext; 988 uint16_t qinfifo[AHD_SCB_MAX]; 989 uint16_t *qoutfifo; 990 991 /* Critical Section Data */ 992 struct cs *critical_sections; 993 u_int num_critical_sections; 994 995 /* Buffer for handling packetized bitbucket. */ 996 uint8_t *overrun_buf; 997 998 /* Links for chaining softcs */ 999 TAILQ_ENTRY(ahd_softc) links; 1000 1001 /* Channel Names ('A', 'B', etc.) */ 1002 char channel; 1003 1004 /* Initiator Bus ID */ 1005 uint8_t our_id; 1006 1007 /* 1008 * PCI error detection. 1009 */ 1010 int unsolicited_ints; 1011 1012 /* 1013 * Target incoming command FIFO. 1014 */ 1015 struct target_cmd *targetcmds; 1016 uint8_t tqinfifonext; 1017 1018 /* 1019 * Incoming and outgoing message handling. 1020 */ 1021 uint8_t send_msg_perror; 1022 ahd_msg_flags msg_flags; 1023 ahd_msg_type msg_type; 1024 uint8_t msgout_buf[12];/* Message we are sending */ 1025 uint8_t msgin_buf[12];/* Message we are receiving */ 1026 u_int msgout_len; /* Length of message to send */ 1027 u_int msgout_index; /* Current index in msgout */ 1028 u_int msgin_index; /* Current index in msgin */ 1029 1030 /* 1031 * Mapping information for data structures shared 1032 * between the sequencer and kernel. 1033 */ 1034 bus_dma_tag_t parent_dmat; 1035 bus_dma_tag_t shared_data_dmat; 1036 bus_dmamap_t shared_data_dmamap; 1037 bus_addr_t shared_data_busaddr; 1038 1039 /* Information saved through suspend/resume cycles */ 1040 struct ahd_suspend_state suspend_state; 1041 1042 /* Number of enabled target mode device on this card */ 1043 u_int enabled_luns; 1044 1045 /* Initialization level of this data structure */ 1046 u_int init_level; 1047 1048 /* PCI cacheline size. */ 1049 u_int pci_cachesize; 1050 1051 /* Per-Unit descriptive information */ 1052 const char *description; 1053 const char *bus_description; 1054 char *name; 1055 int unit; 1056 1057 /* Selection Timer settings */ 1058 int seltime; 1059 1060 uint16_t user_discenable;/* Disconnection allowed */ 1061 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1062 }; 1063 1064 TAILQ_HEAD(ahd_softc_tailq, ahd_softc); 1065 extern struct ahd_softc_tailq ahd_tailq; 1066 1067 /************************ Active Device Information ***************************/ 1068 typedef enum { 1069 ROLE_UNKNOWN, 1070 ROLE_INITIATOR, 1071 ROLE_TARGET 1072 } role_t; 1073 1074 struct ahd_devinfo { 1075 int our_scsiid; 1076 int target_offset; 1077 uint16_t target_mask; 1078 u_int target; 1079 u_int lun; 1080 char channel; 1081 role_t role; /* 1082 * Only guaranteed to be correct if not 1083 * in the busfree state. 1084 */ 1085 }; 1086 1087 /****************************** PCI Structures ********************************/ 1088 #define AHD_PCI_IOADDR0 PCIR_MAPS /* I/O BAR*/ 1089 #define AHD_PCI_MEMADDR (PCIR_MAPS + 4) /* Memory BAR */ 1090 #define AHD_PCI_IOADDR1 (PCIR_MAPS + 12)/* Second I/O BAR */ 1091 1092 typedef int (ahd_device_setup_t)(struct ahd_softc *); 1093 1094 struct ahd_pci_identity { 1095 uint64_t full_id; 1096 uint64_t id_mask; 1097 char *name; 1098 ahd_device_setup_t *setup; 1099 }; 1100 extern struct ahd_pci_identity ahd_pci_ident_table []; 1101 extern const u_int ahd_num_pci_devs; 1102 1103 /***************************** VL/EISA Declarations ***************************/ 1104 struct aic7770_identity { 1105 uint32_t full_id; 1106 uint32_t id_mask; 1107 char *name; 1108 ahd_device_setup_t *setup; 1109 }; 1110 extern struct aic7770_identity aic7770_ident_table []; 1111 extern const int ahd_num_aic7770_devs; 1112 1113 #define AHD_EISA_SLOT_OFFSET 0xc00 1114 #define AHD_EISA_IOSIZE 0x100 1115 1116 /*************************** Function Declarations ****************************/ 1117 /******************************************************************************/ 1118 u_int ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl); 1119 void ahd_set_disconnected_list(struct ahd_softc *ahd, 1120 u_int target, u_int lun, 1121 u_int scbid); 1122 void ahd_busy_tcl(struct ahd_softc *ahd, 1123 u_int tcl, u_int busyid); 1124 static __inline void ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl); 1125 static __inline void 1126 ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl) 1127 { 1128 ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL); 1129 } 1130 1131 /***************************** PCI Front End *********************************/ 1132 struct ahd_pci_identity *ahd_find_pci_device(ahd_dev_softc_t); 1133 int ahd_pci_config(struct ahd_softc *, 1134 struct ahd_pci_identity *); 1135 1136 /*************************** EISA/VL Front End ********************************/ 1137 struct aic7770_identity *aic7770_find_device(uint32_t); 1138 int aic7770_config(struct ahd_softc *ahd, 1139 struct aic7770_identity *); 1140 1141 /************************** SCB and SCB queue management **********************/ 1142 int ahd_probe_scbs(struct ahd_softc *); 1143 void ahd_run_untagged_queues(struct ahd_softc *ahd); 1144 void ahd_run_untagged_queue(struct ahd_softc *ahd, 1145 struct scb_tailq *queue); 1146 void ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, 1147 struct scb *scb); 1148 int ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, 1149 int target, char channel, int lun, 1150 u_int tag, role_t role); 1151 1152 /****************************** Initialization ********************************/ 1153 struct ahd_softc *ahd_alloc(void *platform_arg, char *name); 1154 int ahd_softc_init(struct ahd_softc *); 1155 void ahd_controller_info(struct ahd_softc *ahd, char *buf); 1156 int ahd_init(struct ahd_softc *ahd); 1157 int ahd_default_config(struct ahd_softc *ahd); 1158 int ahd_parse_cfgdata(struct ahd_softc *ahd, 1159 struct seeprom_config *sc); 1160 void ahd_intr_enable(struct ahd_softc *ahd, int enable); 1161 void ahd_pause_and_flushwork(struct ahd_softc *ahd); 1162 int ahd_suspend(struct ahd_softc *ahd); 1163 int ahd_resume(struct ahd_softc *ahd); 1164 void ahd_softc_insert(struct ahd_softc *); 1165 struct ahd_softc *ahd_find_softc(struct ahd_softc *ahd); 1166 void ahd_set_unit(struct ahd_softc *, int); 1167 void ahd_set_name(struct ahd_softc *, char *); 1168 void ahd_alloc_scbs(struct ahd_softc *ahd); 1169 void ahd_free(struct ahd_softc *ahd); 1170 int ahd_reset(struct ahd_softc *ahd); 1171 void ahd_shutdown(void *arg); 1172 int ahd_write_flexport(struct ahd_softc *ahd, 1173 u_int addr, u_int value); 1174 int ahd_read_flexport(struct ahd_softc *ahd, u_int addr, 1175 uint8_t *value); 1176 int ahd_wait_flexport(struct ahd_softc *ahd); 1177 1178 /*************************** Interrupt Services *******************************/ 1179 void ahd_pci_intr(struct ahd_softc *ahd); 1180 void ahd_clear_intstat(struct ahd_softc *ahd); 1181 void ahd_run_qoutfifo(struct ahd_softc *ahd); 1182 #ifdef AHD_TARGET_MODE 1183 void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused); 1184 #endif 1185 void ahd_handle_hwerrint(struct ahd_softc *ahd); 1186 void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat); 1187 void ahd_handle_scsiint(struct ahd_softc *ahd, 1188 u_int intstat); 1189 void ahd_clear_critical_section(struct ahd_softc *ahd); 1190 1191 /***************************** Error Recovery *********************************/ 1192 typedef enum { 1193 SEARCH_COMPLETE, 1194 SEARCH_COUNT, 1195 SEARCH_REMOVE, 1196 SEARCH_PRINT 1197 } ahd_search_action; 1198 int ahd_search_qinfifo(struct ahd_softc *ahd, int target, 1199 char channel, int lun, u_int tag, 1200 role_t role, uint32_t status, 1201 ahd_search_action action); 1202 int ahd_search_disc_list(struct ahd_softc *ahd, int target, 1203 char channel, int lun, u_int tag, 1204 int stop_on_first, int remove, 1205 int save_state); 1206 void ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb); 1207 int ahd_reset_channel(struct ahd_softc *ahd, char channel, 1208 int initiate_reset); 1209 int ahd_abort_scbs(struct ahd_softc *ahd, int target, 1210 char channel, int lun, u_int tag, 1211 role_t role, uint32_t status); 1212 void ahd_restart(struct ahd_softc *ahd); 1213 void ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo); 1214 void ahd_handle_scb_status(struct ahd_softc *ahd, 1215 struct scb *scb); 1216 void ahd_handle_scsi_status(struct ahd_softc *ahd, 1217 struct scb *scb); 1218 void ahd_calc_residual(struct ahd_softc *ahd, 1219 struct scb *scb); 1220 /*************************** Utility Functions ********************************/ 1221 struct ahd_phase_table_entry* 1222 ahd_lookup_phase_entry(int phase); 1223 void ahd_compile_devinfo(struct ahd_devinfo *devinfo, 1224 u_int our_id, u_int target, 1225 u_int lun, char channel, 1226 role_t role); 1227 /************************** Transfer Negotiation ******************************/ 1228 void ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 1229 u_int *ppr_options, u_int maxsync); 1230 void ahd_validate_offset(struct ahd_softc *ahd, 1231 struct ahd_initiator_tinfo *tinfo, 1232 u_int period, u_int *offset, 1233 int wide, role_t role); 1234 void ahd_validate_width(struct ahd_softc *ahd, 1235 struct ahd_initiator_tinfo *tinfo, 1236 u_int *bus_width, 1237 role_t role); 1238 int ahd_update_neg_request(struct ahd_softc*, 1239 struct ahd_devinfo*, 1240 struct ahd_tmode_tstate*, 1241 struct ahd_initiator_tinfo*, 1242 int /*force*/); 1243 void ahd_set_width(struct ahd_softc *ahd, 1244 struct ahd_devinfo *devinfo, 1245 u_int width, u_int type, int paused); 1246 void ahd_set_syncrate(struct ahd_softc *ahd, 1247 struct ahd_devinfo *devinfo, 1248 u_int period, u_int offset, 1249 u_int ppr_options, 1250 u_int type, int paused); 1251 typedef enum { 1252 AHD_QUEUE_NONE, 1253 AHD_QUEUE_BASIC, 1254 AHD_QUEUE_TAGGED 1255 } ahd_queue_alg; 1256 1257 void ahd_set_tags(struct ahd_softc *ahd, 1258 struct ahd_devinfo *devinfo, 1259 ahd_queue_alg alg); 1260 1261 /**************************** Target Mode *************************************/ 1262 #ifdef AHD_TARGET_MODE 1263 void ahd_send_lstate_events(struct ahd_softc *, 1264 struct ahd_tmode_lstate *); 1265 void ahd_handle_en_lun(struct ahd_softc *ahd, 1266 struct cam_sim *sim, union ccb *ccb); 1267 cam_status ahd_find_tmode_devs(struct ahd_softc *ahd, 1268 struct cam_sim *sim, union ccb *ccb, 1269 struct ahd_tmode_tstate **tstate, 1270 struct ahd_tmode_lstate **lstate, 1271 int notfound_failure); 1272 #ifndef AHD_TMODE_ENABLE 1273 #define AHD_TMODE_ENABLE 0 1274 #endif 1275 #endif 1276 /******************************* Debug ***************************************/ 1277 #ifdef AHD_DEBUG 1278 extern uint32_t ahd_debug; 1279 #define AHD_SHOW_MISC 0x0001 1280 #define AHD_SHOW_SENSE 0x0002 1281 #define AHD_DUMP_SEEPROM 0x0004 1282 #define AHD_SHOW_TERMCTL 0x0008 1283 #define AHD_SHOW_MEMORY 0x0010 1284 #define AHD_SHOW_MESSAGES 0x0020 1285 #define AHD_SHOW_MODEPTR 0x0040 1286 #define AHD_SHOW_SELTO 0x0080 1287 #define AHD_SHOW_FIFOS 0x0100 1288 #define AHD_SHOW_QFULL 0x0200 1289 #define AHD_SHOW_QUEUE 0x0400 1290 #define AHD_SHOW_TQIN 0x0800 1291 #define AHD_DEBUG_SEQUENCER 0x1000 1292 #endif 1293 void ahd_print_scb(struct scb *scb); 1294 void ahd_dump_sglist(struct scb *scb); 1295 void ahd_dump_all_cards_state(void); 1296 void ahd_dump_card_state(struct ahd_softc *ahd); 1297 void ahd_dump_scbs(struct ahd_softc *ahd); 1298 #endif /* _AIC79XX_H_ */ 1299