1 /* 2 * Core routines and tables shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2002 Justin T. Gibbs. 5 * Copyright (c) 2000-2003 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.c#165 $ 41 * 42 * $FreeBSD$ 43 */ 44 45 #ifdef __linux__ 46 #include "aic79xx_osm.h" 47 #include "aic79xx_inline.h" 48 #include "aicasm/aicasm_insformat.h" 49 #else 50 #include <dev/aic7xxx/aic79xx_osm.h> 51 #include <dev/aic7xxx/aic79xx_inline.h> 52 #include <dev/aic7xxx/aicasm/aicasm_insformat.h> 53 #endif 54 55 /******************************** Globals *************************************/ 56 struct ahd_softc_tailq ahd_tailq = TAILQ_HEAD_INITIALIZER(ahd_tailq); 57 58 /***************************** Lookup Tables **********************************/ 59 char *ahd_chip_names[] = 60 { 61 "NONE", 62 "aic7901", 63 "aic7902", 64 "aic7901A" 65 }; 66 static const u_int num_chip_names = NUM_ELEMENTS(ahd_chip_names); 67 68 /* 69 * Hardware error codes. 70 */ 71 struct ahd_hard_error_entry { 72 uint8_t errno; 73 char *errmesg; 74 }; 75 76 static struct ahd_hard_error_entry ahd_hard_errors[] = { 77 { DSCTMOUT, "Discard Timer has timed out" }, 78 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 79 { SQPARERR, "Sequencer Parity Error" }, 80 { DPARERR, "Data-path Parity Error" }, 81 { MPARERR, "Scratch or SCB Memory Parity Error" }, 82 { CIOPARERR, "CIOBUS Parity Error" }, 83 }; 84 static const u_int num_errors = NUM_ELEMENTS(ahd_hard_errors); 85 86 static struct ahd_phase_table_entry ahd_phase_table[] = 87 { 88 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 89 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 90 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 91 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 92 { P_COMMAND, MSG_NOOP, "in Command phase" }, 93 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 94 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 95 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 96 { P_BUSFREE, MSG_NOOP, "while idle" }, 97 { 0, MSG_NOOP, "in unknown phase" } 98 }; 99 100 /* 101 * In most cases we only wish to itterate over real phases, so 102 * exclude the last element from the count. 103 */ 104 static const u_int num_phases = NUM_ELEMENTS(ahd_phase_table) - 1; 105 106 /* Our Sequencer Program */ 107 #include "aic79xx_seq.h" 108 109 /**************************** Function Declarations ***************************/ 110 static void ahd_handle_transmission_error(struct ahd_softc *ahd); 111 static void ahd_handle_lqiphase_error(struct ahd_softc *ahd, 112 u_int lqistat1); 113 static int ahd_handle_pkt_busfree(struct ahd_softc *ahd, 114 u_int busfreetime); 115 static int ahd_handle_nonpkt_busfree(struct ahd_softc *ahd); 116 static void ahd_handle_proto_violation(struct ahd_softc *ahd); 117 static void ahd_force_renegotiation(struct ahd_softc *ahd, 118 struct ahd_devinfo *devinfo); 119 120 static struct ahd_tmode_tstate* 121 ahd_alloc_tstate(struct ahd_softc *ahd, 122 u_int scsi_id, char channel); 123 #ifdef AHD_TARGET_MODE 124 static void ahd_free_tstate(struct ahd_softc *ahd, 125 u_int scsi_id, char channel, int force); 126 #endif 127 static void ahd_devlimited_syncrate(struct ahd_softc *ahd, 128 struct ahd_initiator_tinfo *, 129 u_int *period, 130 u_int *ppr_options, 131 role_t role); 132 static void ahd_update_neg_table(struct ahd_softc *ahd, 133 struct ahd_devinfo *devinfo, 134 struct ahd_transinfo *tinfo); 135 static void ahd_update_pending_scbs(struct ahd_softc *ahd); 136 static void ahd_fetch_devinfo(struct ahd_softc *ahd, 137 struct ahd_devinfo *devinfo); 138 static void ahd_scb_devinfo(struct ahd_softc *ahd, 139 struct ahd_devinfo *devinfo, 140 struct scb *scb); 141 static void ahd_setup_initiator_msgout(struct ahd_softc *ahd, 142 struct ahd_devinfo *devinfo, 143 struct scb *scb); 144 static void ahd_build_transfer_msg(struct ahd_softc *ahd, 145 struct ahd_devinfo *devinfo); 146 static void ahd_construct_sdtr(struct ahd_softc *ahd, 147 struct ahd_devinfo *devinfo, 148 u_int period, u_int offset); 149 static void ahd_construct_wdtr(struct ahd_softc *ahd, 150 struct ahd_devinfo *devinfo, 151 u_int bus_width); 152 static void ahd_construct_ppr(struct ahd_softc *ahd, 153 struct ahd_devinfo *devinfo, 154 u_int period, u_int offset, 155 u_int bus_width, u_int ppr_options); 156 static void ahd_clear_msg_state(struct ahd_softc *ahd); 157 static void ahd_handle_message_phase(struct ahd_softc *ahd); 158 typedef enum { 159 AHDMSG_1B, 160 AHDMSG_2B, 161 AHDMSG_EXT 162 } ahd_msgtype; 163 static int ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, 164 u_int msgval, int full); 165 static int ahd_parse_msg(struct ahd_softc *ahd, 166 struct ahd_devinfo *devinfo); 167 static int ahd_handle_msg_reject(struct ahd_softc *ahd, 168 struct ahd_devinfo *devinfo); 169 static void ahd_handle_ign_wide_residue(struct ahd_softc *ahd, 170 struct ahd_devinfo *devinfo); 171 static void ahd_reinitialize_dataptrs(struct ahd_softc *ahd); 172 static void ahd_handle_devreset(struct ahd_softc *ahd, 173 struct ahd_devinfo *devinfo, 174 u_int lun, cam_status status, 175 char *message, int verbose_level); 176 #if AHD_TARGET_MODE 177 static void ahd_setup_target_msgin(struct ahd_softc *ahd, 178 struct ahd_devinfo *devinfo, 179 struct scb *scb); 180 #endif 181 182 static u_int ahd_sglist_size(struct ahd_softc *ahd); 183 static u_int ahd_sglist_allocsize(struct ahd_softc *ahd); 184 static bus_dmamap_callback_t 185 ahd_dmamap_cb; 186 static void ahd_initialize_hscbs(struct ahd_softc *ahd); 187 static int ahd_init_scbdata(struct ahd_softc *ahd); 188 static void ahd_fini_scbdata(struct ahd_softc *ahd); 189 static void ahd_setup_iocell_workaround(struct ahd_softc *ahd); 190 static void ahd_iocell_first_selection(struct ahd_softc *ahd); 191 static void ahd_add_col_list(struct ahd_softc *ahd, 192 struct scb *scb, u_int col_idx); 193 static void ahd_rem_col_list(struct ahd_softc *ahd, 194 struct scb *scb); 195 static void ahd_chip_init(struct ahd_softc *ahd); 196 static void ahd_qinfifo_requeue(struct ahd_softc *ahd, 197 struct scb *prev_scb, 198 struct scb *scb); 199 static int ahd_qinfifo_count(struct ahd_softc *ahd); 200 static int ahd_search_scb_list(struct ahd_softc *ahd, int target, 201 char channel, int lun, u_int tag, 202 role_t role, uint32_t status, 203 ahd_search_action action, 204 u_int *list_head, u_int tid); 205 static void ahd_stitch_tid_list(struct ahd_softc *ahd, 206 u_int tid_prev, u_int tid_cur, 207 u_int tid_next); 208 static void ahd_add_scb_to_free_list(struct ahd_softc *ahd, 209 u_int scbid); 210 static u_int ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, 211 u_int prev, u_int next, u_int tid); 212 static void ahd_reset_current_bus(struct ahd_softc *ahd); 213 static ahd_callback_t ahd_reset_poll; 214 static ahd_callback_t ahd_stat_timer; 215 #ifdef AHD_DUMP_SEQ 216 static void ahd_dumpseq(struct ahd_softc *ahd); 217 #endif 218 static void ahd_loadseq(struct ahd_softc *ahd); 219 static int ahd_check_patch(struct ahd_softc *ahd, 220 struct patch **start_patch, 221 u_int start_instr, u_int *skip_addr); 222 static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd, 223 u_int address); 224 static void ahd_download_instr(struct ahd_softc *ahd, 225 u_int instrptr, uint8_t *dconsts); 226 static int ahd_probe_stack_size(struct ahd_softc *ahd); 227 #ifdef AHD_TARGET_MODE 228 static void ahd_queue_lstate_event(struct ahd_softc *ahd, 229 struct ahd_tmode_lstate *lstate, 230 u_int initiator_id, 231 u_int event_type, 232 u_int event_arg); 233 static void ahd_update_scsiid(struct ahd_softc *ahd, 234 u_int targid_mask); 235 static int ahd_handle_target_cmd(struct ahd_softc *ahd, 236 struct target_cmd *cmd); 237 #endif 238 239 /******************************** Private Inlines *****************************/ 240 static __inline void ahd_assert_atn(struct ahd_softc *ahd); 241 static __inline int ahd_currently_packetized(struct ahd_softc *ahd); 242 static __inline int ahd_set_active_fifo(struct ahd_softc *ahd); 243 244 static __inline void 245 ahd_assert_atn(struct ahd_softc *ahd) 246 { 247 ahd_outb(ahd, SCSISIGO, ATNO); 248 } 249 250 /* 251 * Determine if the current connection has a packetized 252 * agreement. This does not necessarily mean that we 253 * are currently in a packetized transfer. We could 254 * just as easily be sending or receiving a message. 255 */ 256 static __inline int 257 ahd_currently_packetized(struct ahd_softc *ahd) 258 { 259 ahd_mode_state saved_modes; 260 int packetized; 261 262 saved_modes = ahd_save_modes(ahd); 263 if ((ahd->bugs & AHD_PKTIZED_STATUS_BUG) != 0) { 264 /* 265 * The packetized bit refers to the last 266 * connection, not the current one. Check 267 * for non-zero LQISTATE instead. 268 */ 269 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 270 packetized = ahd_inb(ahd, LQISTATE) != 0; 271 } else { 272 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 273 packetized = ahd_inb(ahd, LQISTAT2) & PACKETIZED; 274 } 275 ahd_restore_modes(ahd, saved_modes); 276 return (packetized); 277 } 278 279 static __inline int 280 ahd_set_active_fifo(struct ahd_softc *ahd) 281 { 282 u_int active_fifo; 283 284 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 285 active_fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; 286 switch (active_fifo) { 287 case 0: 288 case 1: 289 ahd_set_modes(ahd, active_fifo, active_fifo); 290 return (1); 291 default: 292 return (0); 293 } 294 } 295 296 /************************* Sequencer Execution Control ************************/ 297 /* 298 * Restart the sequencer program from address zero 299 */ 300 void 301 ahd_restart(struct ahd_softc *ahd) 302 { 303 304 ahd_pause(ahd); 305 306 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 307 308 /* No more pending messages */ 309 ahd_clear_msg_state(ahd); 310 ahd_outb(ahd, SCSISIGO, 0); /* De-assert BSY */ 311 ahd_outb(ahd, MSG_OUT, MSG_NOOP); /* No message to send */ 312 ahd_outb(ahd, SXFRCTL1, ahd_inb(ahd, SXFRCTL1) & ~BITBUCKET); 313 ahd_outb(ahd, SEQINTCTL, 0); 314 ahd_outb(ahd, LASTPHASE, P_BUSFREE); 315 ahd_outb(ahd, SEQ_FLAGS, 0); 316 ahd_outb(ahd, SAVED_SCSIID, 0xFF); 317 ahd_outb(ahd, SAVED_LUN, 0xFF); 318 319 /* 320 * Ensure that the sequencer's idea of TQINPOS 321 * matches our own. The sequencer increments TQINPOS 322 * only after it sees a DMA complete and a reset could 323 * occur before the increment leaving the kernel to believe 324 * the command arrived but the sequencer to not. 325 */ 326 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); 327 328 /* Always allow reselection */ 329 ahd_outb(ahd, SCSISEQ1, 330 ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 331 /* Ensure that no DMA operations are in progress */ 332 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 333 ahd_outb(ahd, SCBHCNT, 0); 334 ahd_outb(ahd, CCSCBCTL, CCSCBRESET); 335 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); 336 ahd_unpause(ahd); 337 } 338 339 void 340 ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo) 341 { 342 ahd_mode_state saved_modes; 343 344 #ifdef AHD_DEBUG 345 if ((ahd_debug & AHD_SHOW_FIFOS) != 0) 346 printf("%s: Clearing FIFO %d\n", ahd_name(ahd), fifo); 347 #endif 348 saved_modes = ahd_save_modes(ahd); 349 ahd_set_modes(ahd, fifo, fifo); 350 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); 351 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) 352 ahd_outb(ahd, CCSGCTL, CCSGRESET); 353 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 354 ahd_outb(ahd, SG_STATE, 0); 355 ahd_restore_modes(ahd, saved_modes); 356 } 357 358 /************************* Input/Output Queues ********************************/ 359 /* 360 * Flush and completed commands that are sitting in the command 361 * complete queues down on the chip but have yet to be dma'ed back up. 362 */ 363 void 364 ahd_flush_qoutfifo(struct ahd_softc *ahd) 365 { 366 struct scb *scb; 367 ahd_mode_state saved_modes; 368 u_int saved_scbptr; 369 u_int ccscbctl; 370 u_int scbid; 371 u_int next_scbid; 372 373 saved_modes = ahd_save_modes(ahd); 374 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 375 saved_scbptr = ahd_get_scbptr(ahd); 376 377 /* 378 * Wait for any inprogress DMA to complete and clear DMA state 379 * if this if for an SCB in the qinfifo. 380 */ 381 while ((ccscbctl = ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0) { 382 383 if ((ccscbctl & (CCSCBDIR|CCARREN)) == (CCSCBDIR|CCARREN)) { 384 if ((ccscbctl & ARRDONE) != 0) 385 break; 386 } else if ((ccscbctl & CCSCBDONE) != 0) 387 break; 388 ahd_delay(200); 389 } 390 if ((ccscbctl & CCSCBDIR) != 0) 391 ahd_outb(ahd, CCSCBCTL, ccscbctl & ~(CCARREN|CCSCBEN)); 392 393 /* 394 * Complete any SCBs that just finished being 395 * DMA'ed into the qoutfifo. 396 */ 397 ahd_run_qoutfifo(ahd); 398 399 /* 400 * Manually update/complete any completed SCBs that are waiting to be 401 * DMA'ed back up to the host. 402 */ 403 scbid = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 404 while (!SCBID_IS_NULL(scbid)) { 405 uint8_t *hscb_ptr; 406 u_int i; 407 408 ahd_set_scbptr(ahd, scbid); 409 next_scbid = ahd_inw(ahd, SCB_NEXT_COMPLETE); 410 scb = ahd_lookup_scb(ahd, scbid); 411 if (scb == NULL) { 412 printf("%s: Warning - DMA-up and complete " 413 "SCB %d invalid\n", ahd_name(ahd), scbid); 414 continue; 415 } 416 hscb_ptr = (uint8_t *)scb->hscb; 417 for (i = 0; i < sizeof(struct hardware_scb); i++) 418 *hscb_ptr++ = ahd_inb(ahd, SCB_BASE + i); 419 420 ahd_complete_scb(ahd, scb); 421 scbid = next_scbid; 422 } 423 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); 424 425 scbid = ahd_inw(ahd, COMPLETE_SCB_HEAD); 426 while (!SCBID_IS_NULL(scbid)) { 427 428 ahd_set_scbptr(ahd, scbid); 429 next_scbid = ahd_inw(ahd, SCB_NEXT_COMPLETE); 430 scb = ahd_lookup_scb(ahd, scbid); 431 if (scb == NULL) { 432 printf("%s: Warning - Complete SCB %d invalid\n", 433 ahd_name(ahd), scbid); 434 continue; 435 } 436 437 ahd_complete_scb(ahd, scb); 438 scbid = next_scbid; 439 } 440 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); 441 ahd_set_scbptr(ahd, saved_scbptr); 442 443 /* 444 * Flush the good status FIFO for compelted packetized commands. 445 */ 446 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 447 while ((ahd_inb(ahd, LQISTAT2) & LQIGSAVAIL) != 0) { 448 scbid = (ahd_inb(ahd, GSFIFO+1) << 8) 449 | ahd_inb(ahd, GSFIFO); 450 scb = ahd_lookup_scb(ahd, scbid); 451 if (scb == NULL) { 452 printf("%s: Warning - GSFIFO SCB %d invalid\n", 453 ahd_name(ahd), scbid); 454 continue; 455 } 456 ahd_complete_scb(ahd, scb); 457 } 458 459 /* 460 * Restore state. 461 */ 462 ahd_restore_modes(ahd, saved_modes); 463 ahd->flags |= AHD_UPDATE_PEND_CMDS; 464 } 465 466 void 467 ahd_run_qoutfifo(struct ahd_softc *ahd) 468 { 469 struct scb *scb; 470 u_int scb_index; 471 472 if ((ahd->flags & AHD_RUNNING_QOUTFIFO) != 0) 473 panic("ahd_run_qoutfifo recursion"); 474 ahd->flags |= AHD_RUNNING_QOUTFIFO; 475 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD); 476 while ((ahd->qoutfifo[ahd->qoutfifonext] 477 & QOUTFIFO_ENTRY_VALID_LE) == ahd->qoutfifonext_valid_tag) { 478 479 scb_index = ahd_le16toh(ahd->qoutfifo[ahd->qoutfifonext] 480 & ~QOUTFIFO_ENTRY_VALID_LE); 481 scb = ahd_lookup_scb(ahd, scb_index); 482 if (scb == NULL) { 483 printf("%s: WARNING no command for scb %d " 484 "(cmdcmplt)\nQOUTPOS = %d\n", 485 ahd_name(ahd), scb_index, 486 ahd->qoutfifonext); 487 ahd_dump_card_state(ahd); 488 } else 489 ahd_complete_scb(ahd, scb); 490 491 ahd->qoutfifonext = (ahd->qoutfifonext+1) & (AHD_QOUT_SIZE-1); 492 if (ahd->qoutfifonext == 0) 493 ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID_LE; 494 } 495 ahd->flags &= ~AHD_RUNNING_QOUTFIFO; 496 } 497 498 /************************* Interrupt Handling *********************************/ 499 void 500 ahd_handle_hwerrint(struct ahd_softc *ahd) 501 { 502 /* 503 * Some catastrophic hardware error has occurred. 504 * Print it for the user and disable the controller. 505 */ 506 int i; 507 int error; 508 509 error = ahd_inb(ahd, ERROR); 510 for (i = 0; i < num_errors; i++) { 511 if ((error & ahd_hard_errors[i].errno) != 0) 512 printf("%s: hwerrint, %s\n", 513 ahd_name(ahd), ahd_hard_errors[i].errmesg); 514 } 515 516 ahd_dump_card_state(ahd); 517 panic("BRKADRINT"); 518 519 /* Tell everyone that this HBA is no longer availible */ 520 ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, 521 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 522 CAM_NO_HBA); 523 524 /* Tell the system that this controller has gone away. */ 525 ahd_free(ahd); 526 } 527 528 void 529 ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat) 530 { 531 u_int seqintcode; 532 533 /* 534 * Save the sequencer interrupt code and clear the SEQINT 535 * bit. We will unpause the sequencer, if appropriate, 536 * after servicing the request. 537 */ 538 seqintcode = ahd_inb(ahd, SEQINTCODE); 539 ahd_outb(ahd, CLRINT, CLRSEQINT); 540 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { 541 /* 542 * Unpause the sequencer and let it clear 543 * SEQINT by writing NO_SEQINT to it. This 544 * will cause the sequencer to be paused again, 545 * which is the expected state of this routine. 546 */ 547 ahd_unpause(ahd); 548 while (!ahd_is_paused(ahd)) 549 ; 550 ahd_outb(ahd, CLRINT, CLRSEQINT); 551 } 552 ahd_update_modes(ahd); 553 #ifdef AHD_DEBUG 554 if ((ahd_debug & AHD_SHOW_MISC) != 0) 555 printf("%s: Handle Seqint Called for code %d\n", 556 ahd_name(ahd), seqintcode); 557 #endif 558 switch (seqintcode) { 559 case ENTERING_NONPACK: 560 { 561 struct scb *scb; 562 u_int scbid; 563 564 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 565 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 566 scbid = ahd_get_scbptr(ahd); 567 scb = ahd_lookup_scb(ahd, scbid); 568 if (scb == NULL) { 569 /* 570 * Somehow need to know if this 571 * is from a selection or reselection. 572 * From that, we can termine target 573 * ID so we at least have an I_T nexus. 574 */ 575 } else { 576 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); 577 ahd_outb(ahd, SAVED_LUN, scb->hscb->lun); 578 ahd_outb(ahd, SEQ_FLAGS, 0x0); 579 } 580 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0 581 && (ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { 582 /* 583 * Phase change after read stream with 584 * CRC error with P0 asserted on last 585 * packet. 586 */ 587 #ifdef AHD_DEBUG 588 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 589 printf("%s: Assuming LQIPHASE_NLQ with " 590 "P0 assertion\n", ahd_name(ahd)); 591 #endif 592 } 593 #ifdef AHD_DEBUG 594 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 595 printf("%s: Entering NONPACK\n", ahd_name(ahd)); 596 #endif 597 break; 598 } 599 case INVALID_SEQINT: 600 printf("%s: Invalid Sequencer interrupt occurred.\n", 601 ahd_name(ahd)); 602 ahd_dump_card_state(ahd); 603 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 604 break; 605 case STATUS_OVERRUN: 606 { 607 printf("%s: Status Overrun", ahd_name(ahd)); 608 ahd_dump_card_state(ahd); 609 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 610 break; 611 } 612 case CFG4ISTAT_INTR: 613 { 614 struct scb *scb; 615 u_int scbid; 616 617 scbid = ahd_get_scbptr(ahd); 618 scb = ahd_lookup_scb(ahd, scbid); 619 if (scb == NULL) { 620 ahd_dump_card_state(ahd); 621 printf("CFG4ISTAT: Free SCB %d referenced", scbid); 622 panic("For safety"); 623 } 624 ahd_outq(ahd, HADDR, scb->sense_busaddr); 625 ahd_outw(ahd, HCNT, AHD_SENSE_BUFSIZE); 626 ahd_outb(ahd, HCNT + 2, 0); 627 ahd_outb(ahd, SG_CACHE_PRE, SG_LAST_SEG); 628 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN); 629 break; 630 } 631 case ILLEGAL_PHASE: 632 { 633 u_int bus_phase; 634 635 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 636 printf("%s: ILLEGAL_PHASE 0x%x\n", 637 ahd_name(ahd), bus_phase); 638 639 switch (bus_phase) { 640 case P_DATAOUT: 641 case P_DATAIN: 642 case P_DATAOUT_DT: 643 case P_DATAIN_DT: 644 case P_MESGOUT: 645 case P_STATUS: 646 case P_MESGIN: 647 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 648 printf("%s: Issued Bus Reset.\n", ahd_name(ahd)); 649 break; 650 case P_COMMAND: 651 { 652 struct ahd_devinfo devinfo; 653 struct scb *scb; 654 struct ahd_initiator_tinfo *targ_info; 655 struct ahd_tmode_tstate *tstate; 656 struct ahd_transinfo *tinfo; 657 u_int scbid; 658 659 /* 660 * If a target takes us into the command phase 661 * assume that it has been externally reset and 662 * has thus lost our previous packetized negotiation 663 * agreement. Since we have not sent an identify 664 * message and may not have fully qualified the 665 * connection, we change our command to TUR, assert 666 * ATN and ABORT the task when we go to message in 667 * phase. The OSM will see the REQUEUE_REQUEST 668 * status and retry the command. 669 */ 670 scbid = ahd_get_scbptr(ahd); 671 scb = ahd_lookup_scb(ahd, scbid); 672 if (scb == NULL) { 673 printf("Invalid phase with no valid SCB. " 674 "Resetting bus.\n"); 675 ahd_reset_channel(ahd, 'A', 676 /*Initiate Reset*/TRUE); 677 break; 678 } 679 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), 680 SCB_GET_TARGET(ahd, scb), 681 SCB_GET_LUN(scb), 682 SCB_GET_CHANNEL(ahd, scb), 683 ROLE_INITIATOR); 684 targ_info = ahd_fetch_transinfo(ahd, 685 devinfo.channel, 686 devinfo.our_scsiid, 687 devinfo.target, 688 &tstate); 689 tinfo = &targ_info->curr; 690 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 691 AHD_TRANS_ACTIVE, /*paused*/TRUE); 692 ahd_set_syncrate(ahd, &devinfo, /*period*/0, 693 /*offset*/0, /*ppr_options*/0, 694 AHD_TRANS_ACTIVE, /*paused*/TRUE); 695 ahd_outb(ahd, SCB_CDB_STORE, 0); 696 ahd_outb(ahd, SCB_CDB_STORE+1, 0); 697 ahd_outb(ahd, SCB_CDB_STORE+2, 0); 698 ahd_outb(ahd, SCB_CDB_STORE+3, 0); 699 ahd_outb(ahd, SCB_CDB_STORE+4, 0); 700 ahd_outb(ahd, SCB_CDB_STORE+5, 0); 701 ahd_outb(ahd, SCB_CDB_LEN, 6); 702 scb->hscb->control &= ~(TAG_ENB|SCB_TAG_TYPE); 703 scb->hscb->control |= MK_MESSAGE; 704 ahd_outb(ahd, SCB_CONTROL, scb->hscb->control); 705 ahd_outb(ahd, MSG_OUT, HOST_MSG); 706 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); 707 /* 708 * The lun is 0, regardless of the SCB's lun 709 * as we have not sent an identify message. 710 */ 711 ahd_outb(ahd, SAVED_LUN, 0); 712 ahd_outb(ahd, SEQ_FLAGS, 0); 713 ahd_assert_atn(ahd); 714 scb->flags &= ~(SCB_PACKETIZED); 715 scb->flags |= SCB_ABORT|SCB_CMDPHASE_ABORT; 716 ahd_freeze_devq(ahd, scb); 717 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ); 718 ahd_freeze_scb(scb); 719 720 /* 721 * Allow the sequencer to continue with 722 * non-pack processing. 723 */ 724 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 725 ahd_outb(ahd, CLRLQOINT1, CLRLQOPHACHGINPKT); 726 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 727 ahd_outb(ahd, CLRLQOINT1, 0); 728 } 729 #ifdef AHD_DEBUG 730 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 731 ahd_print_path(ahd, scb); 732 printf("Unexpected command phase from " 733 "packetized target\n"); 734 } 735 #endif 736 break; 737 } 738 } 739 break; 740 } 741 case CFG4OVERRUN: 742 { 743 struct scb *scb; 744 u_int scb_index; 745 746 #ifdef AHD_DEBUG 747 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 748 printf("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd), 749 ahd_inb(ahd, MODE_PTR)); 750 } 751 #endif 752 scb_index = ahd_get_scbptr(ahd); 753 scb = ahd_lookup_scb(ahd, scb_index); 754 if (scb == NULL) { 755 /* 756 * Attempt to transfer to an SCB that is 757 * not outstanding. 758 */ 759 ahd_assert_atn(ahd); 760 ahd_outb(ahd, MSG_OUT, HOST_MSG); 761 ahd->msgout_buf[0] = MSG_ABORT_TASK; 762 ahd->msgout_len = 1; 763 ahd->msgout_index = 0; 764 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 765 /* 766 * Clear status received flag to prevent any 767 * attempt to complete this bogus SCB. 768 */ 769 ahd_outb(ahd, SCB_CONTROL, 770 ahd_inb(ahd, SCB_CONTROL) & ~STATUS_RCVD); 771 } 772 break; 773 } 774 case DUMP_CARD_STATE: 775 { 776 ahd_dump_card_state(ahd); 777 break; 778 } 779 case PDATA_REINIT: 780 { 781 #ifdef AHD_DEBUG 782 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 783 printf("%s: PDATA_REINIT - DFCNTRL = 0x%x " 784 "SG_CACHE_SHADOW = 0x%x\n", 785 ahd_name(ahd), ahd_inb(ahd, DFCNTRL), 786 ahd_inb(ahd, SG_CACHE_SHADOW)); 787 } 788 #endif 789 ahd_reinitialize_dataptrs(ahd); 790 break; 791 } 792 case HOST_MSG_LOOP: 793 { 794 struct ahd_devinfo devinfo; 795 796 /* 797 * The sequencer has encountered a message phase 798 * that requires host assistance for completion. 799 * While handling the message phase(s), we will be 800 * notified by the sequencer after each byte is 801 * transfered so we can track bus phase changes. 802 * 803 * If this is the first time we've seen a HOST_MSG_LOOP 804 * interrupt, initialize the state of the host message 805 * loop. 806 */ 807 ahd_fetch_devinfo(ahd, &devinfo); 808 if (ahd->msg_type == MSG_TYPE_NONE) { 809 struct scb *scb; 810 u_int scb_index; 811 u_int bus_phase; 812 813 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 814 if (bus_phase != P_MESGIN 815 && bus_phase != P_MESGOUT) { 816 printf("ahd_intr: HOST_MSG_LOOP bad " 817 "phase 0x%x\n", bus_phase); 818 /* 819 * Probably transitioned to bus free before 820 * we got here. Just punt the message. 821 */ 822 ahd_dump_card_state(ahd); 823 ahd_clear_intstat(ahd); 824 ahd_restart(ahd); 825 return; 826 } 827 828 scb_index = ahd_get_scbptr(ahd); 829 scb = ahd_lookup_scb(ahd, scb_index); 830 if (devinfo.role == ROLE_INITIATOR) { 831 if (bus_phase == P_MESGOUT) 832 ahd_setup_initiator_msgout(ahd, 833 &devinfo, 834 scb); 835 else { 836 ahd->msg_type = 837 MSG_TYPE_INITIATOR_MSGIN; 838 ahd->msgin_index = 0; 839 } 840 } 841 #if AHD_TARGET_MODE 842 else { 843 if (bus_phase == P_MESGOUT) { 844 ahd->msg_type = 845 MSG_TYPE_TARGET_MSGOUT; 846 ahd->msgin_index = 0; 847 } 848 else 849 ahd_setup_target_msgin(ahd, 850 &devinfo, 851 scb); 852 } 853 #endif 854 } 855 856 ahd_handle_message_phase(ahd); 857 break; 858 } 859 case NO_MATCH: 860 { 861 /* Ensure we don't leave the selection hardware on */ 862 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 863 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 864 865 printf("%s:%c:%d: no active SCB for reconnecting " 866 "target - issuing BUS DEVICE RESET\n", 867 ahd_name(ahd), 'A', ahd_inb(ahd, SELID) >> 4); 868 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 869 "REG0 == 0x%x ACCUM = 0x%x\n", 870 ahd_inb(ahd, SAVED_SCSIID), ahd_inb(ahd, SAVED_LUN), 871 ahd_inw(ahd, REG0), ahd_inb(ahd, ACCUM)); 872 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 873 "SINDEX == 0x%x\n", 874 ahd_inb(ahd, SEQ_FLAGS), ahd_get_scbptr(ahd), 875 ahd_find_busy_tcl(ahd, 876 BUILD_TCL(ahd_inb(ahd, SAVED_SCSIID), 877 ahd_inb(ahd, SAVED_LUN))), 878 ahd_inw(ahd, SINDEX)); 879 printf("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 880 "SCB_CONTROL == 0x%x\n", 881 ahd_inb(ahd, SELID), ahd_inb_scbram(ahd, SCB_SCSIID), 882 ahd_inb_scbram(ahd, SCB_LUN), 883 ahd_inb_scbram(ahd, SCB_CONTROL)); 884 printf("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n", 885 ahd_inb(ahd, SCSIBUS), ahd_inb(ahd, SCSISIGI)); 886 printf("SXFRCTL0 == 0x%x\n", ahd_inb(ahd, SXFRCTL0)); 887 printf("SEQCTL0 == 0x%x\n", ahd_inb(ahd, SEQCTL0)); 888 ahd_dump_card_state(ahd); 889 ahd->msgout_buf[0] = MSG_BUS_DEV_RESET; 890 ahd->msgout_len = 1; 891 ahd->msgout_index = 0; 892 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 893 ahd_outb(ahd, MSG_OUT, HOST_MSG); 894 ahd_assert_atn(ahd); 895 break; 896 } 897 case PROTO_VIOLATION: 898 { 899 ahd_handle_proto_violation(ahd); 900 break; 901 } 902 case IGN_WIDE_RES: 903 { 904 struct ahd_devinfo devinfo; 905 906 ahd_fetch_devinfo(ahd, &devinfo); 907 ahd_handle_ign_wide_residue(ahd, &devinfo); 908 break; 909 } 910 case BAD_PHASE: 911 { 912 u_int lastphase; 913 914 lastphase = ahd_inb(ahd, LASTPHASE); 915 printf("%s:%c:%d: unknown scsi bus phase %x, " 916 "lastphase = 0x%x. Attempting to continue\n", 917 ahd_name(ahd), 'A', 918 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), 919 lastphase, ahd_inb(ahd, SCSISIGI)); 920 break; 921 } 922 case MISSED_BUSFREE: 923 { 924 u_int lastphase; 925 926 lastphase = ahd_inb(ahd, LASTPHASE); 927 printf("%s:%c:%d: Missed busfree. " 928 "Lastphase = 0x%x, Curphase = 0x%x\n", 929 ahd_name(ahd), 'A', 930 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), 931 lastphase, ahd_inb(ahd, SCSISIGI)); 932 ahd_restart(ahd); 933 return; 934 } 935 case DATA_OVERRUN: 936 { 937 /* 938 * When the sequencer detects an overrun, it 939 * places the controller in "BITBUCKET" mode 940 * and allows the target to complete its transfer. 941 * Unfortunately, none of the counters get updated 942 * when the controller is in this mode, so we have 943 * no way of knowing how large the overrun was. 944 */ 945 struct scb *scb; 946 u_int scbindex; 947 #ifdef AHD_DEBUG 948 u_int lastphase; 949 #endif 950 951 scbindex = ahd_get_scbptr(ahd); 952 scb = ahd_lookup_scb(ahd, scbindex); 953 #ifdef AHD_DEBUG 954 lastphase = ahd_inb(ahd, LASTPHASE); 955 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 956 ahd_print_path(ahd, scb); 957 printf("data overrun detected %s. Tag == 0x%x.\n", 958 ahd_lookup_phase_entry(lastphase)->phasemsg, 959 SCB_GET_TAG(scb)); 960 ahd_print_path(ahd, scb); 961 printf("%s seen Data Phase. Length = %ld. " 962 "NumSGs = %d.\n", 963 ahd_inb(ahd, SEQ_FLAGS) & DPHASE 964 ? "Have" : "Haven't", 965 ahd_get_transfer_length(scb), scb->sg_count); 966 ahd_dump_sglist(scb); 967 } 968 #endif 969 970 /* 971 * Set this and it will take effect when the 972 * target does a command complete. 973 */ 974 ahd_freeze_devq(ahd, scb); 975 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR); 976 ahd_freeze_scb(scb); 977 break; 978 } 979 case MKMSG_FAILED: 980 { 981 struct ahd_devinfo devinfo; 982 struct scb *scb; 983 u_int scbid; 984 985 ahd_fetch_devinfo(ahd, &devinfo); 986 printf("%s:%c:%d:%d: Attempt to issue message failed\n", 987 ahd_name(ahd), devinfo.channel, devinfo.target, 988 devinfo.lun); 989 scbid = ahd_get_scbptr(ahd); 990 scb = ahd_lookup_scb(ahd, scbid); 991 if (scb != NULL 992 && (scb->flags & SCB_RECOVERY_SCB) != 0) 993 /* 994 * Ensure that we didn't put a second instance of this 995 * SCB into the QINFIFO. 996 */ 997 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 998 SCB_GET_CHANNEL(ahd, scb), 999 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1000 ROLE_INITIATOR, /*status*/0, 1001 SEARCH_REMOVE); 1002 ahd_outb(ahd, SCB_CONTROL, 1003 ahd_inb(ahd, SCB_CONTROL) & ~MK_MESSAGE); 1004 break; 1005 } 1006 case TASKMGMT_FUNC_COMPLETE: 1007 { 1008 u_int scbid; 1009 struct scb *scb; 1010 1011 scbid = ahd_get_scbptr(ahd); 1012 scb = ahd_lookup_scb(ahd, scbid); 1013 if (scb != NULL) { 1014 u_int lun; 1015 u_int tag; 1016 cam_status error; 1017 1018 ahd_print_path(ahd, scb); 1019 printf("Task Management Func 0x%x Complete\n", 1020 scb->hscb->task_management); 1021 lun = CAM_LUN_WILDCARD; 1022 tag = SCB_LIST_NULL; 1023 1024 switch (scb->hscb->task_management) { 1025 case SIU_TASKMGMT_ABORT_TASK: 1026 tag = scb->hscb->tag; 1027 case SIU_TASKMGMT_ABORT_TASK_SET: 1028 case SIU_TASKMGMT_CLEAR_TASK_SET: 1029 lun = scb->hscb->lun; 1030 error = CAM_REQ_ABORTED; 1031 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 1032 'A', lun, tag, ROLE_INITIATOR, 1033 error); 1034 break; 1035 case SIU_TASKMGMT_LUN_RESET: 1036 lun = scb->hscb->lun; 1037 case SIU_TASKMGMT_TARGET_RESET: 1038 { 1039 struct ahd_devinfo devinfo; 1040 1041 ahd_scb_devinfo(ahd, &devinfo, scb); 1042 error = CAM_BDR_SENT; 1043 ahd_handle_devreset(ahd, &devinfo, lun, 1044 CAM_BDR_SENT, 1045 lun != CAM_LUN_WILDCARD 1046 ? "Lun Reset" 1047 : "Target Reset", 1048 /*verbose_level*/0); 1049 break; 1050 } 1051 default: 1052 panic("Unexpected TaskMgmt Func\n"); 1053 break; 1054 } 1055 } 1056 break; 1057 } 1058 case TASKMGMT_CMD_CMPLT_OKAY: 1059 { 1060 u_int scbid; 1061 struct scb *scb; 1062 1063 /* 1064 * An ABORT TASK TMF failed to be delivered before 1065 * the targeted command completed normally. 1066 */ 1067 scbid = ahd_get_scbptr(ahd); 1068 scb = ahd_lookup_scb(ahd, scbid); 1069 if (scb != NULL) { 1070 /* 1071 * Remove the second instance of this SCB from 1072 * the QINFIFO if it is still there. 1073 */ 1074 ahd_print_path(ahd, scb); 1075 printf("SCB completes before TMF\n"); 1076 /* 1077 * Handle losing the race. Wait until any 1078 * current selection completes. We will then 1079 * set the TMF back to zero in this SCB so that 1080 * the sequencer doesn't bother to issue another 1081 * sequencer interrupt for its completion. 1082 */ 1083 while ((ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0 1084 && (ahd_inb(ahd, SSTAT0) & SELDO) == 0 1085 && (ahd_inb(ahd, SSTAT1) & SELTO) == 0) 1086 ; 1087 ahd_outb(ahd, SCB_TASK_MANAGEMENT, 0); 1088 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 1089 SCB_GET_CHANNEL(ahd, scb), 1090 SCB_GET_LUN(scb), scb->hscb->tag, 1091 ROLE_INITIATOR, /*status*/0, 1092 SEARCH_REMOVE); 1093 } 1094 break; 1095 } 1096 case TRACEPOINT0: 1097 case TRACEPOINT1: 1098 case TRACEPOINT2: 1099 case TRACEPOINT3: 1100 printf("%s: Tracepoint %d\n", ahd_name(ahd), 1101 seqintcode - TRACEPOINT0); 1102 break; 1103 case NO_SEQINT: 1104 break; 1105 case SAW_HWERR: 1106 ahd_handle_hwerrint(ahd); 1107 break; 1108 default: 1109 printf("%s: Unexpected SEQINTCODE %d\n", ahd_name(ahd), 1110 seqintcode); 1111 break; 1112 } 1113 /* 1114 * The sequencer is paused immediately on 1115 * a SEQINT, so we should restart it when 1116 * we're done. 1117 */ 1118 ahd_unpause(ahd); 1119 } 1120 1121 void 1122 ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat) 1123 { 1124 struct scb *scb; 1125 u_int status0; 1126 u_int status3; 1127 u_int status; 1128 u_int lqistat1; 1129 u_int lqostat0; 1130 u_int scbid; 1131 u_int busfreetime; 1132 1133 ahd_update_modes(ahd); 1134 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1135 1136 status3 = ahd_inb(ahd, SSTAT3) & (NTRAMPERR|OSRAMPERR); 1137 status0 = ahd_inb(ahd, SSTAT0) & (IOERR|OVERRUN|SELDI|SELDO); 1138 status = ahd_inb(ahd, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 1139 lqistat1 = ahd_inb(ahd, LQISTAT1); 1140 lqostat0 = ahd_inb(ahd, LQOSTAT0); 1141 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; 1142 if ((status0 & (SELDI|SELDO)) != 0) { 1143 u_int simode0; 1144 1145 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 1146 simode0 = ahd_inb(ahd, SIMODE0); 1147 status0 &= simode0 & (IOERR|OVERRUN|SELDI|SELDO); 1148 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1149 } 1150 scbid = ahd_get_scbptr(ahd); 1151 scb = ahd_lookup_scb(ahd, scbid); 1152 if (scb != NULL 1153 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1154 scb = NULL; 1155 1156 /* Make sure the sequencer is in a safe location. */ 1157 ahd_clear_critical_section(ahd); 1158 1159 if ((status0 & IOERR) != 0) { 1160 u_int now_lvd; 1161 1162 now_lvd = ahd_inb(ahd, SBLKCTL) & ENAB40; 1163 printf("%s: Transceiver State Has Changed to %s mode\n", 1164 ahd_name(ahd), now_lvd ? "LVD" : "SE"); 1165 ahd_outb(ahd, CLRSINT0, CLRIOERR); 1166 /* 1167 * A change in I/O mode is equivalent to a bus reset. 1168 */ 1169 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE); 1170 ahd_pause(ahd); 1171 ahd_setup_iocell_workaround(ahd); 1172 ahd_unpause(ahd); 1173 } else if ((status0 & OVERRUN) != 0) { 1174 printf("%s: SCSI offset overrun detected. Resetting bus.\n", 1175 ahd_name(ahd)); 1176 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1177 } else if ((status & SCSIRSTI) != 0) { 1178 printf("%s: Someone reset channel A\n", ahd_name(ahd)); 1179 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE); 1180 } else if ((status & SCSIPERR) != 0) { 1181 ahd_handle_transmission_error(ahd); 1182 } else if (lqostat0 != 0) { 1183 printf("%s: lqostat0 == 0x%x!\n", ahd_name(ahd), lqostat0); 1184 ahd_outb(ahd, CLRLQOINT0, lqostat0); 1185 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 1186 ahd_outb(ahd, CLRLQOINT1, 0); 1187 } 1188 } else if ((status & SELTO) != 0) { 1189 u_int scbid; 1190 1191 /* Stop the selection */ 1192 ahd_outb(ahd, SCSISEQ0, 0); 1193 1194 /* No more pending messages */ 1195 ahd_clear_msg_state(ahd); 1196 1197 /* Clear interrupt state */ 1198 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1199 1200 /* 1201 * Although the driver does not care about the 1202 * 'Selection in Progress' status bit, the busy 1203 * LED does. SELINGO is only cleared by a sucessfull 1204 * selection, so we must manually clear it to insure 1205 * the LED turns off just incase no future successful 1206 * selections occur (e.g. no devices on the bus). 1207 */ 1208 ahd_outb(ahd, CLRSINT0, CLRSELINGO); 1209 1210 scbid = ahd_inw(ahd, WAITING_TID_HEAD); 1211 scb = ahd_lookup_scb(ahd, scbid); 1212 if (scb == NULL) { 1213 printf("%s: ahd_intr - referenced scb not " 1214 "valid during SELTO scb(0x%x)\n", 1215 ahd_name(ahd), scbid); 1216 ahd_dump_card_state(ahd); 1217 } else { 1218 struct ahd_devinfo devinfo; 1219 #ifdef AHD_DEBUG 1220 if ((ahd_debug & AHD_SHOW_SELTO) != 0) { 1221 ahd_print_path(ahd, scb); 1222 printf("Saw Selection Timeout for SCB 0x%x\n", 1223 scbid); 1224 } 1225 #endif 1226 /* 1227 * Force a renegotiation with this target just in 1228 * case the cable was pulled and will later be 1229 * re-attached. The target may forget its negotiation 1230 * settings with us should it attempt to reselect 1231 * during the interruption. The target will not issue 1232 * a unit attention in this case, so we must always 1233 * renegotiate. 1234 */ 1235 ahd_scb_devinfo(ahd, &devinfo, scb); 1236 ahd_force_renegotiation(ahd, &devinfo); 1237 ahd_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1238 ahd_freeze_devq(ahd, scb); 1239 } 1240 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1241 ahd_iocell_first_selection(ahd); 1242 ahd_unpause(ahd); 1243 } else if ((status0 & (SELDI|SELDO)) != 0) { 1244 ahd_iocell_first_selection(ahd); 1245 ahd_unpause(ahd); 1246 } else if (status3 != 0) { 1247 printf("%s: SCSI Cell parity error SSTAT3 == 0x%x\n", 1248 ahd_name(ahd), status3); 1249 ahd_outb(ahd, CLRSINT3, status3); 1250 } else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) { 1251 ahd_handle_lqiphase_error(ahd, lqistat1); 1252 } else if ((lqistat1 & LQICRCI_NLQ) != 0) { 1253 /* 1254 * This status can be delayed during some 1255 * streaming operations. The SCSIPHASE 1256 * handler has already dealt with this case 1257 * so just clear the error. 1258 */ 1259 ahd_outb(ahd, CLRLQIINT1, CLRLQICRCI_NLQ); 1260 } else if ((status & BUSFREE) != 0) { 1261 u_int lqostat1; 1262 int restart; 1263 int clear_fifo; 1264 int packetized; 1265 u_int mode; 1266 1267 /* 1268 * Clear our selection hardware as soon as possible. 1269 * We may have an entry in the waiting Q for this target, 1270 * that is affected by this busfree and we don't want to 1271 * go about selecting the target while we handle the event. 1272 */ 1273 ahd_outb(ahd, SCSISEQ0, 0); 1274 1275 /* 1276 * Determine what we were up to at the time of 1277 * the busfree. 1278 */ 1279 mode = AHD_MODE_SCSI; 1280 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; 1281 lqostat1 = ahd_inb(ahd, LQOSTAT1); 1282 switch (busfreetime) { 1283 case BUSFREE_DFF0: 1284 case BUSFREE_DFF1: 1285 { 1286 u_int scbid; 1287 struct scb *scb; 1288 1289 mode = busfreetime == BUSFREE_DFF0 1290 ? AHD_MODE_DFF0 : AHD_MODE_DFF1; 1291 ahd_set_modes(ahd, mode, mode); 1292 scbid = ahd_get_scbptr(ahd); 1293 scb = ahd_lookup_scb(ahd, scbid); 1294 if (scb == NULL) { 1295 printf("%s: Invalid SCB in DFF%d " 1296 "during unexpected busfree\n", 1297 ahd_name(ahd), mode); 1298 packetized = 0; 1299 } else 1300 packetized = (scb->flags & SCB_PACKETIZED) != 0; 1301 clear_fifo = 1; 1302 break; 1303 } 1304 case BUSFREE_LQO: 1305 clear_fifo = 0; 1306 packetized = 1; 1307 break; 1308 default: 1309 clear_fifo = 0; 1310 packetized = (lqostat1 & LQOBUSFREE) != 0; 1311 if (!packetized 1312 && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) 1313 packetized = 1; 1314 break; 1315 } 1316 1317 #ifdef AHD_DEBUG 1318 if ((ahd_debug & AHD_SHOW_MISC) != 0) 1319 printf("Saw Busfree. Busfreetime = 0x%x.\n", 1320 busfreetime); 1321 #endif 1322 /* 1323 * Busfrees that occur in non-packetized phases are 1324 * handled by the nonpkt_busfree handler. 1325 */ 1326 if (packetized && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) { 1327 restart = ahd_handle_pkt_busfree(ahd, busfreetime); 1328 } else { 1329 packetized = 0; 1330 restart = ahd_handle_nonpkt_busfree(ahd); 1331 } 1332 /* 1333 * Clear the busfree interrupt status. The setting of 1334 * the interrupt is a pulse, so in a perfect world, we 1335 * would not need to muck with the ENBUSFREE logic. This 1336 * would ensure that if the bus moves on to another 1337 * connection, busfree protection is still in force. If 1338 * BUSFREEREV is broken, however, we must manually clear 1339 * the ENBUSFREE if the busfree occurred during a non-pack 1340 * connection so that we don't get false positives during 1341 * future, packetized, connections. 1342 */ 1343 ahd_outb(ahd, CLRSINT1, CLRBUSFREE); 1344 if (packetized == 0 1345 && (ahd->bugs & AHD_BUSFREEREV_BUG) != 0) 1346 ahd_outb(ahd, SIMODE1, 1347 ahd_inb(ahd, SIMODE1) & ~ENBUSFREE); 1348 1349 if (clear_fifo) 1350 ahd_clear_fifo(ahd, mode); 1351 1352 ahd_clear_msg_state(ahd); 1353 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1354 if (restart) { 1355 ahd_restart(ahd); 1356 } else { 1357 ahd_unpause(ahd); 1358 } 1359 } else { 1360 printf("%s: Missing case in ahd_handle_scsiint. status = %x\n", 1361 ahd_name(ahd), status); 1362 ahd_dump_card_state(ahd); 1363 ahd_clear_intstat(ahd); 1364 ahd_unpause(ahd); 1365 } 1366 } 1367 1368 static void 1369 ahd_handle_transmission_error(struct ahd_softc *ahd) 1370 { 1371 struct scb *scb; 1372 u_int scbid; 1373 u_int lqistat1; 1374 u_int lqistat2; 1375 u_int msg_out; 1376 u_int curphase; 1377 u_int lastphase; 1378 u_int perrdiag; 1379 u_int cur_col; 1380 int silent; 1381 1382 scb = NULL; 1383 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1384 lqistat1 = ahd_inb(ahd, LQISTAT1) & ~(LQIPHASE_LQ|LQIPHASE_NLQ); 1385 lqistat2 = ahd_inb(ahd, LQISTAT2); 1386 if ((lqistat1 & (LQICRCI_NLQ|LQICRCI_LQ)) == 0 1387 && (ahd->bugs & AHD_NLQICRC_DELAYED_BUG) != 0) { 1388 u_int lqistate; 1389 1390 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 1391 lqistate = ahd_inb(ahd, LQISTATE); 1392 if ((lqistate >= 0x1E && lqistate <= 0x24) 1393 || (lqistate == 0x29)) { 1394 #ifdef AHD_DEBUG 1395 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1396 printf("%s: NLQCRC found via LQISTATE\n", 1397 ahd_name(ahd)); 1398 } 1399 #endif 1400 lqistat1 |= LQICRCI_NLQ; 1401 } 1402 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1403 } 1404 1405 ahd_outb(ahd, CLRLQIINT1, lqistat1); 1406 lastphase = ahd_inb(ahd, LASTPHASE); 1407 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1408 perrdiag = ahd_inb(ahd, PERRDIAG); 1409 msg_out = MSG_INITIATOR_DET_ERR; 1410 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR); 1411 1412 /* 1413 * Try to find the SCB associated with this error. 1414 */ 1415 silent = FALSE; 1416 if (lqistat1 == 0 1417 || (lqistat1 & LQICRCI_NLQ) != 0) { 1418 if ((lqistat1 & (LQICRCI_NLQ|LQIOVERI_NLQ)) != 0) 1419 ahd_set_active_fifo(ahd); 1420 scbid = ahd_get_scbptr(ahd); 1421 scb = ahd_lookup_scb(ahd, scbid); 1422 if (scb != NULL && SCB_IS_SILENT(scb)) 1423 silent = TRUE; 1424 } 1425 1426 cur_col = 0; 1427 if (silent == FALSE) { 1428 printf("%s: Transmission error detected\n", ahd_name(ahd)); 1429 ahd_lqistat1_print(lqistat1, &cur_col, 50); 1430 ahd_lastphase_print(lastphase, &cur_col, 50); 1431 ahd_scsisigi_print(curphase, &cur_col, 50); 1432 ahd_perrdiag_print(perrdiag, &cur_col, 50); 1433 printf("\n"); 1434 ahd_dump_card_state(ahd); 1435 } 1436 1437 if ((lqistat1 & (LQIOVERI_LQ|LQIOVERI_NLQ)) != 0) { 1438 if (silent == FALSE) { 1439 printf("%s: Gross protocol error during incoming " 1440 "packet. lqistat1 == 0x%x. Resetting bus.\n", 1441 ahd_name(ahd), lqistat1); 1442 } 1443 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1444 return; 1445 } else if ((lqistat1 & LQICRCI_LQ) != 0) { 1446 /* 1447 * A CRC error has been detected on an incoming LQ. 1448 * The bus is currently hung on the last ACK. 1449 * Hit LQIRETRY to release the last ack, and 1450 * wait for the sequencer to determine that ATNO 1451 * is asserted while in message out to take us 1452 * to our host message loop. No NONPACKREQ or 1453 * LQIPHASE type errors will occur in this 1454 * scenario. After this first LQIRETRY, the LQI 1455 * manager will be in ISELO where it will 1456 * happily sit until another packet phase begins. 1457 * Unexpected bus free detection is enabled 1458 * through any phases that occur after we release 1459 * this last ack until the LQI manager sees a 1460 * packet phase. This implies we may have to 1461 * ignore a perfectly valid "unexected busfree" 1462 * after our "initiator detected error" message is 1463 * sent. A busfree is the expected response after 1464 * we tell the target that it's L_Q was corrupted. 1465 * (SPI4R09 10.7.3.3.3) 1466 */ 1467 ahd_outb(ahd, LQCTL2, LQIRETRY); 1468 printf("LQIRetry for LQICRCI_LQ to release ACK\n"); 1469 } else if ((lqistat1 & LQICRCI_NLQ) != 0) { 1470 /* 1471 * We detected a CRC error in a NON-LQ packet. 1472 * The hardware has varying behavior in this situation 1473 * depending on whether this packet was part of a 1474 * stream or not. 1475 * 1476 * PKT by PKT mode: 1477 * The hardware has already acked the complete packet. 1478 * If the target honors our outstanding ATN condition, 1479 * we should be (or soon will be) in MSGOUT phase. 1480 * This will trigger the LQIPHASE_LQ status bit as the 1481 * hardware was expecting another LQ. Unexpected 1482 * busfree detection is enabled. Once LQIPHASE_LQ is 1483 * true (first entry into host message loop is much 1484 * the same), we must clear LQIPHASE_LQ and hit 1485 * LQIRETRY so the hardware is ready to handle 1486 * a future LQ. NONPACKREQ will not be asserted again 1487 * once we hit LQIRETRY until another packet is 1488 * processed. The target may either go busfree 1489 * or start another packet in response to our message. 1490 * 1491 * Read Streaming P0 asserted: 1492 * If we raise ATN and the target completes the entire 1493 * stream (P0 asserted during the last packet), the 1494 * hardware will ack all data and return to the ISTART 1495 * state. When the target reponds to our ATN condition, 1496 * LQIPHASE_LQ will be asserted. We should respond to 1497 * this with an LQIRETRY to prepare for any future 1498 * packets. NONPACKREQ will not be asserted again 1499 * once we hit LQIRETRY until another packet is 1500 * processed. The target may either go busfree or 1501 * start another packet in response to our message. 1502 * Busfree detection is enabled. 1503 * 1504 * Read Streaming P0 not asserted: 1505 * If we raise ATN and the target transitions to 1506 * MSGOUT in or after a packet where P0 is not 1507 * asserted, the hardware will assert LQIPHASE_NLQ. 1508 * We should respond to the LQIPHASE_NLQ with an 1509 * LQIRETRY. Should the target stay in a non-pkt 1510 * phase after we send our message, the hardware 1511 * will assert LQIPHASE_LQ. Recovery is then just as 1512 * listed above for the read streaming with P0 asserted. 1513 * Busfree detection is enabled. 1514 */ 1515 if (silent == FALSE) 1516 printf("LQICRC_NLQ\n"); 1517 if (scb == NULL) { 1518 printf("%s: No SCB valid for LQICRC_NLQ. " 1519 "Resetting bus\n", ahd_name(ahd)); 1520 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1521 return; 1522 } 1523 } else if ((lqistat1 & LQIBADLQI) != 0) { 1524 printf("Need to handle BADLQI!\n"); 1525 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1526 return; 1527 } else if ((perrdiag & (PARITYERR|PREVPHASE)) == PARITYERR) { 1528 if ((curphase & ~P_DATAIN_DT) != 0) { 1529 /* Ack the byte. So we can continue. */ 1530 if (silent == FALSE) 1531 printf("Acking %s to clear perror\n", 1532 ahd_lookup_phase_entry(curphase)->phasemsg); 1533 ahd_inb(ahd, SCSIDAT); 1534 } 1535 1536 if (curphase == P_MESGIN) 1537 msg_out = MSG_PARITY_ERROR; 1538 } 1539 1540 /* 1541 * We've set the hardware to assert ATN if we 1542 * get a parity error on "in" phases, so all we 1543 * need to do is stuff the message buffer with 1544 * the appropriate message. "In" phases have set 1545 * mesg_out to something other than MSG_NOP. 1546 */ 1547 ahd->send_msg_perror = msg_out; 1548 if (scb != NULL && msg_out == MSG_INITIATOR_DET_ERR) 1549 scb->flags |= SCB_TRANSMISSION_ERROR; 1550 ahd_outb(ahd, MSG_OUT, HOST_MSG); 1551 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1552 ahd_unpause(ahd); 1553 } 1554 1555 static void 1556 ahd_handle_lqiphase_error(struct ahd_softc *ahd, u_int lqistat1) 1557 { 1558 /* 1559 * Clear the sources of the interrupts. 1560 */ 1561 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1562 ahd_outb(ahd, CLRLQIINT1, lqistat1); 1563 1564 /* 1565 * If the "illegal" phase changes were in response 1566 * to our ATN to flag a CRC error, AND we ended up 1567 * on packet boundaries, clear the error, restart the 1568 * LQI manager as appropriate, and go on our merry 1569 * way toward sending the message. Otherwise, reset 1570 * the bus to clear the error. 1571 */ 1572 ahd_set_active_fifo(ahd); 1573 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0 1574 && (ahd_inb(ahd, MDFFSTAT) & DLZERO) != 0) { 1575 if ((lqistat1 & LQIPHASE_LQ) != 0) { 1576 printf("LQIRETRY for LQIPHASE_LQ\n"); 1577 ahd_outb(ahd, LQCTL2, LQIRETRY); 1578 } else if ((lqistat1 & LQIPHASE_NLQ) != 0) { 1579 printf("LQIRETRY for LQIPHASE_NLQ\n"); 1580 ahd_outb(ahd, LQCTL2, LQIRETRY); 1581 } else 1582 panic("ahd_handle_lqiphase_error: No phase errors\n"); 1583 ahd_dump_card_state(ahd); 1584 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1585 ahd_unpause(ahd); 1586 } else { 1587 printf("Reseting Channel for LQI Phase error\n"); 1588 ahd_dump_card_state(ahd); 1589 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1590 } 1591 } 1592 1593 /* 1594 * Packetized unexpected or expected busfree. 1595 * Entered in mode based on busfreetime. 1596 */ 1597 static int 1598 ahd_handle_pkt_busfree(struct ahd_softc *ahd, u_int busfreetime) 1599 { 1600 u_int lqostat1; 1601 1602 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 1603 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 1604 lqostat1 = ahd_inb(ahd, LQOSTAT1); 1605 if ((lqostat1 & LQOBUSFREE) != 0) { 1606 struct scb *scb; 1607 u_int scbid; 1608 u_int saved_scbptr; 1609 u_int waiting_h; 1610 u_int waiting_t; 1611 u_int next; 1612 1613 if ((busfreetime & BUSFREE_LQO) == 0) 1614 printf("%s: Warning, BUSFREE time is 0x%x. " 1615 "Expected BUSFREE_LQO.\n", 1616 ahd_name(ahd), busfreetime); 1617 /* 1618 * The LQO manager detected an unexpected busfree 1619 * either: 1620 * 1621 * 1) During an outgoing LQ. 1622 * 2) After an outgoing LQ but before the first 1623 * REQ of the command packet. 1624 * 3) During an outgoing command packet. 1625 * 1626 * In all cases, CURRSCB is pointing to the 1627 * SCB that encountered the failure. Clean 1628 * up the queue, clear SELDO and LQOBUSFREE, 1629 * and allow the sequencer to restart the select 1630 * out at its lesure. 1631 */ 1632 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1633 scbid = ahd_inw(ahd, CURRSCB); 1634 scb = ahd_lookup_scb(ahd, scbid); 1635 if (scb == NULL) 1636 panic("SCB not valid during LQOBUSFREE"); 1637 /* 1638 * Clear the status. 1639 */ 1640 ahd_outb(ahd, CLRLQOINT1, CLRLQOBUSFREE); 1641 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) 1642 ahd_outb(ahd, CLRLQOINT1, 0); 1643 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 1644 ahd_flush_device_writes(ahd); 1645 ahd_outb(ahd, CLRSINT0, CLRSELDO); 1646 1647 /* 1648 * Return the LQO manager to its idle loop. It will 1649 * not do this automatically if the busfree occurs 1650 * after the first REQ of either the LQ or command 1651 * packet or between the LQ and command packet. 1652 */ 1653 ahd_outb(ahd, LQCTL2, ahd_inb(ahd, LQCTL2) | LQOTOIDLE); 1654 1655 /* 1656 * Update the waiting for selection queue so 1657 * we restart on the correct SCB. 1658 */ 1659 waiting_h = ahd_inw(ahd, WAITING_TID_HEAD); 1660 saved_scbptr = ahd_get_scbptr(ahd); 1661 if (waiting_h != scbid) { 1662 1663 ahd_outw(ahd, WAITING_TID_HEAD, scbid); 1664 waiting_t = ahd_inw(ahd, WAITING_TID_TAIL); 1665 if (waiting_t == waiting_h) { 1666 ahd_outw(ahd, WAITING_TID_TAIL, scbid); 1667 next = SCB_LIST_NULL; 1668 } else { 1669 ahd_set_scbptr(ahd, waiting_h); 1670 next = ahd_inw(ahd, SCB_NEXT2); 1671 } 1672 ahd_set_scbptr(ahd, scbid); 1673 ahd_outw(ahd, SCB_NEXT2, next); 1674 } 1675 ahd_set_scbptr(ahd, saved_scbptr); 1676 if (scb->crc_retry_count < AHD_MAX_LQ_CRC_ERRORS) { 1677 if (SCB_IS_SILENT(scb) == FALSE) { 1678 ahd_print_path(ahd, scb); 1679 printf("Probable outgoing LQ CRC error. " 1680 "Retrying command\n"); 1681 } 1682 scb->crc_retry_count++; 1683 } else { 1684 ahd_set_transaction_status(scb, CAM_UNCOR_PARITY); 1685 ahd_freeze_scb(scb); 1686 ahd_freeze_devq(ahd, scb); 1687 } 1688 /* Return unpausing the sequencer. */ 1689 return (0); 1690 } else if ((ahd_inb(ahd, PERRDIAG) & PARITYERR) != 0) { 1691 /* 1692 * Ignore what are really parity errors that 1693 * occur on the last REQ of a free running 1694 * clock prior to going busfree. Some drives 1695 * do not properly active negate just before 1696 * going busfree resulting in a parity glitch. 1697 */ 1698 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR|CLRBUSFREE); 1699 #ifdef AHD_DEBUG 1700 if ((ahd_debug & AHD_SHOW_MASKED_ERRORS) != 0) 1701 printf("%s: Parity on last REQ detected " 1702 "during busfree phase.\n", 1703 ahd_name(ahd)); 1704 #endif 1705 /* Return unpausing the sequencer. */ 1706 return (0); 1707 } 1708 if (ahd->src_mode != AHD_MODE_SCSI) { 1709 u_int scbid; 1710 struct scb *scb; 1711 1712 scbid = ahd_get_scbptr(ahd); 1713 scb = ahd_lookup_scb(ahd, scbid); 1714 ahd_print_path(ahd, scb); 1715 printf("Unexpected PKT busfree condition\n"); 1716 ahd_dump_card_state(ahd); 1717 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 'A', 1718 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1719 ROLE_INITIATOR, CAM_UNEXP_BUSFREE); 1720 1721 /* Return restarting the sequencer. */ 1722 return (1); 1723 } 1724 printf("%s: Unexpected PKT busfree condition\n", ahd_name(ahd)); 1725 ahd_dump_card_state(ahd); 1726 /* Restart the sequencer. */ 1727 return (1); 1728 } 1729 1730 /* 1731 * Non-packetized unexpected or expected busfree. 1732 */ 1733 static int 1734 ahd_handle_nonpkt_busfree(struct ahd_softc *ahd) 1735 { 1736 struct ahd_devinfo devinfo; 1737 struct scb *scb; 1738 u_int lastphase; 1739 u_int saved_scsiid; 1740 u_int saved_lun; 1741 u_int target; 1742 u_int initiator_role_id; 1743 u_int scbid; 1744 u_int ppr_busfree; 1745 int printerror; 1746 1747 /* 1748 * Look at what phase we were last in. If its message out, 1749 * chances are pretty good that the busfree was in response 1750 * to one of our abort requests. 1751 */ 1752 lastphase = ahd_inb(ahd, LASTPHASE); 1753 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); 1754 saved_lun = ahd_inb(ahd, SAVED_LUN); 1755 target = SCSIID_TARGET(ahd, saved_scsiid); 1756 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 1757 ahd_compile_devinfo(&devinfo, initiator_role_id, 1758 target, saved_lun, 'A', ROLE_INITIATOR); 1759 printerror = 1; 1760 1761 scbid = ahd_get_scbptr(ahd); 1762 scb = ahd_lookup_scb(ahd, scbid); 1763 if (scb != NULL 1764 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1765 scb = NULL; 1766 1767 ppr_busfree = (ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0; 1768 if (lastphase == P_MESGOUT) { 1769 u_int tag; 1770 1771 tag = SCB_LIST_NULL; 1772 if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT_TAG, TRUE) 1773 || ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT, TRUE)) { 1774 int found; 1775 int sent_msg; 1776 1777 if (scb == NULL) { 1778 ahd_print_devinfo(ahd, &devinfo); 1779 printf("Abort for unidentified " 1780 "connection completed.\n"); 1781 /* restart the sequencer. */ 1782 return (1); 1783 } 1784 sent_msg = ahd->msgout_buf[ahd->msgout_index - 1]; 1785 ahd_print_path(ahd, scb); 1786 printf("SCB %d - Abort%s Completed.\n", 1787 SCB_GET_TAG(scb), 1788 sent_msg == MSG_ABORT_TAG ? "" : " Tag"); 1789 1790 if (sent_msg == MSG_ABORT_TAG) 1791 tag = SCB_GET_TAG(scb); 1792 1793 if ((scb->flags & SCB_CMDPHASE_ABORT) != 0) { 1794 /* 1795 * This abort is in response to an 1796 * unexpected switch to command phase 1797 * for a packetized connection. Since 1798 * the identify message was never sent, 1799 * "saved lun" is 0. We really want to 1800 * abort only the SCB that encountered 1801 * this error, which could have a different 1802 * lun. The SCB will be retried so the OS 1803 * will see the UA after renegotiating to 1804 * packetized. 1805 */ 1806 tag = SCB_GET_TAG(scb); 1807 saved_lun = scb->hscb->lun; 1808 } 1809 found = ahd_abort_scbs(ahd, target, 'A', saved_lun, 1810 tag, ROLE_INITIATOR, 1811 CAM_REQ_ABORTED); 1812 printf("found == 0x%x\n", found); 1813 printerror = 0; 1814 } else if (ahd_sent_msg(ahd, AHDMSG_1B, 1815 MSG_BUS_DEV_RESET, TRUE)) { 1816 #ifdef __FreeBSD__ 1817 /* 1818 * Don't mark the user's request for this BDR 1819 * as completing with CAM_BDR_SENT. CAM3 1820 * specifies CAM_REQ_CMP. 1821 */ 1822 if (scb != NULL 1823 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 1824 && ahd_match_scb(ahd, scb, target, 'A', 1825 CAM_LUN_WILDCARD, SCB_LIST_NULL, 1826 ROLE_INITIATOR)) 1827 ahd_set_transaction_status(scb, CAM_REQ_CMP); 1828 #endif 1829 ahd_handle_devreset(ahd, &devinfo, CAM_LUN_WILDCARD, 1830 CAM_BDR_SENT, "Bus Device Reset", 1831 /*verbose_level*/0); 1832 printerror = 0; 1833 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, FALSE) 1834 && ppr_busfree == 0) { 1835 struct ahd_initiator_tinfo *tinfo; 1836 struct ahd_tmode_tstate *tstate; 1837 1838 /* 1839 * PPR Rejected. Try non-ppr negotiation 1840 * and retry command. 1841 */ 1842 #ifdef AHD_DEBUG 1843 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1844 printf("PPR negotiation rejected busfree.\n"); 1845 #endif 1846 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel, 1847 devinfo.our_scsiid, 1848 devinfo.target, &tstate); 1849 tinfo->curr.transport_version = 2; 1850 tinfo->goal.transport_version = 2; 1851 tinfo->goal.ppr_options = 0; 1852 ahd_qinfifo_requeue_tail(ahd, scb); 1853 printerror = 0; 1854 } else if ((ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, FALSE) 1855 || ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, FALSE)) 1856 && ppr_busfree == 0) { 1857 /* 1858 * Negotiation Rejected. Go-async and 1859 * retry command. 1860 */ 1861 #ifdef AHD_DEBUG 1862 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1863 printf("Negotiation rejected busfree.\n"); 1864 #endif 1865 ahd_set_width(ahd, &devinfo, 1866 MSG_EXT_WDTR_BUS_8_BIT, 1867 AHD_TRANS_CUR|AHD_TRANS_GOAL, 1868 /*paused*/TRUE); 1869 ahd_set_syncrate(ahd, &devinfo, 1870 /*period*/0, /*offset*/0, 1871 /*ppr_options*/0, 1872 AHD_TRANS_CUR|AHD_TRANS_GOAL, 1873 /*paused*/TRUE); 1874 ahd_qinfifo_requeue_tail(ahd, scb); 1875 printerror = 0; 1876 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_IDE_BUSFREE) != 0 1877 && ahd_sent_msg(ahd, AHDMSG_1B, 1878 MSG_INITIATOR_DET_ERR, TRUE)) { 1879 1880 #ifdef AHD_DEBUG 1881 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1882 printf("Expected IDE Busfree\n"); 1883 #endif 1884 printerror = 0; 1885 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_QASREJ_BUSFREE) 1886 && ahd_sent_msg(ahd, AHDMSG_1B, 1887 MSG_MESSAGE_REJECT, TRUE)) { 1888 1889 #ifdef AHD_DEBUG 1890 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1891 printf("Expected QAS Reject Busfree\n"); 1892 #endif 1893 printerror = 0; 1894 } 1895 } 1896 1897 /* 1898 * The busfree required flag is honored at the end of 1899 * the message phases. We check it last in case we 1900 * had to send some other message that caused a busfree. 1901 */ 1902 if (printerror != 0 1903 && (lastphase == P_MESGIN || lastphase == P_MESGOUT) 1904 && ((ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0)) { 1905 1906 ahd_freeze_devq(ahd, scb); 1907 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ); 1908 ahd_freeze_scb(scb); 1909 if ((ahd->msg_flags & MSG_FLAG_IU_REQ_CHANGED) != 0) { 1910 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 1911 SCB_GET_CHANNEL(ahd, scb), 1912 SCB_GET_LUN(scb), SCB_LIST_NULL, 1913 ROLE_INITIATOR, CAM_REQ_ABORTED); 1914 } else { 1915 #ifdef AHD_DEBUG 1916 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1917 printf("PPR Negotiation Busfree.\n"); 1918 #endif 1919 ahd_done(ahd, scb); 1920 } 1921 printerror = 0; 1922 } 1923 if (printerror != 0) { 1924 int aborted; 1925 1926 aborted = 0; 1927 if (scb != NULL) { 1928 u_int tag; 1929 1930 if ((scb->hscb->control & TAG_ENB) != 0) 1931 tag = SCB_GET_TAG(scb); 1932 else 1933 tag = SCB_LIST_NULL; 1934 ahd_print_path(ahd, scb); 1935 aborted = ahd_abort_scbs(ahd, target, 'A', 1936 SCB_GET_LUN(scb), tag, 1937 ROLE_INITIATOR, 1938 CAM_UNEXP_BUSFREE); 1939 } else { 1940 /* 1941 * We had not fully identified this connection, 1942 * so we cannot abort anything. 1943 */ 1944 printf("%s: ", ahd_name(ahd)); 1945 } 1946 if (lastphase != P_BUSFREE) 1947 ahd_force_renegotiation(ahd, &devinfo); 1948 printf("Unexpected busfree %s, %d SCBs aborted, " 1949 "PRGMCNT == 0x%x\n", 1950 ahd_lookup_phase_entry(lastphase)->phasemsg, 1951 aborted, 1952 ahd_inb(ahd, PRGMCNT) 1953 | (ahd_inb(ahd, PRGMCNT+1) << 8)); 1954 ahd_dump_card_state(ahd); 1955 } 1956 /* Always restart the sequencer. */ 1957 return (1); 1958 } 1959 1960 static void 1961 ahd_handle_proto_violation(struct ahd_softc *ahd) 1962 { 1963 struct ahd_devinfo devinfo; 1964 struct scb *scb; 1965 u_int scbid; 1966 u_int seq_flags; 1967 u_int curphase; 1968 u_int lastphase; 1969 int found; 1970 1971 ahd_fetch_devinfo(ahd, &devinfo); 1972 scbid = ahd_get_scbptr(ahd); 1973 scb = ahd_lookup_scb(ahd, scbid); 1974 seq_flags = ahd_inb(ahd, SEQ_FLAGS); 1975 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1976 lastphase = ahd_inb(ahd, LASTPHASE); 1977 if ((seq_flags & NOT_IDENTIFIED) != 0) { 1978 1979 /* 1980 * The reconnecting target either did not send an 1981 * identify message, or did, but we didn't find an SCB 1982 * to match. 1983 */ 1984 ahd_print_devinfo(ahd, &devinfo); 1985 printf("Target did not send an IDENTIFY message. " 1986 "LASTPHASE = 0x%x.\n", lastphase); 1987 scb = NULL; 1988 } else if (scb == NULL) { 1989 /* 1990 * We don't seem to have an SCB active for this 1991 * transaction. Print an error and reset the bus. 1992 */ 1993 ahd_print_devinfo(ahd, &devinfo); 1994 printf("No SCB found during protocol violation\n"); 1995 goto proto_violation_reset; 1996 } else { 1997 ahd_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 1998 if ((seq_flags & NO_CDB_SENT) != 0) { 1999 ahd_print_path(ahd, scb); 2000 printf("No or incomplete CDB sent to device.\n"); 2001 } else if ((ahd_inb(ahd, SCB_CONTROL) & STATUS_RCVD) == 0) { 2002 /* 2003 * The target never bothered to provide status to 2004 * us prior to completing the command. Since we don't 2005 * know the disposition of this command, we must attempt 2006 * to abort it. Assert ATN and prepare to send an abort 2007 * message. 2008 */ 2009 ahd_print_path(ahd, scb); 2010 printf("Completed command without status.\n"); 2011 } else { 2012 ahd_print_path(ahd, scb); 2013 printf("Unknown protocol violation.\n"); 2014 ahd_dump_card_state(ahd); 2015 } 2016 } 2017 if ((lastphase & ~P_DATAIN_DT) == 0 2018 || lastphase == P_COMMAND) { 2019 proto_violation_reset: 2020 /* 2021 * Target either went directly to data 2022 * phase or didn't respond to our ATN. 2023 * The only safe thing to do is to blow 2024 * it away with a bus reset. 2025 */ 2026 found = ahd_reset_channel(ahd, 'A', TRUE); 2027 printf("%s: Issued Channel %c Bus Reset. " 2028 "%d SCBs aborted\n", ahd_name(ahd), 'A', found); 2029 } else { 2030 /* 2031 * Leave the selection hardware off in case 2032 * this abort attempt will affect yet to 2033 * be sent commands. 2034 */ 2035 ahd_outb(ahd, SCSISEQ0, 2036 ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 2037 ahd_assert_atn(ahd); 2038 ahd_outb(ahd, MSG_OUT, HOST_MSG); 2039 if (scb == NULL) { 2040 ahd_print_devinfo(ahd, &devinfo); 2041 ahd->msgout_buf[0] = MSG_ABORT_TASK; 2042 ahd->msgout_len = 1; 2043 ahd->msgout_index = 0; 2044 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2045 } else { 2046 ahd_print_path(ahd, scb); 2047 scb->flags |= SCB_ABORT; 2048 } 2049 printf("Protocol violation %s. Attempting to abort.\n", 2050 ahd_lookup_phase_entry(curphase)->phasemsg); 2051 } 2052 } 2053 2054 /* 2055 * Force renegotiation to occur the next time we initiate 2056 * a command to the current device. 2057 */ 2058 static void 2059 ahd_force_renegotiation(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 2060 { 2061 struct ahd_initiator_tinfo *targ_info; 2062 struct ahd_tmode_tstate *tstate; 2063 2064 #ifdef AHD_DEBUG 2065 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 2066 ahd_print_devinfo(ahd, devinfo); 2067 printf("Forcing renegotiation\n"); 2068 } 2069 #endif 2070 targ_info = ahd_fetch_transinfo(ahd, 2071 devinfo->channel, 2072 devinfo->our_scsiid, 2073 devinfo->target, 2074 &tstate); 2075 ahd_update_neg_request(ahd, devinfo, tstate, 2076 targ_info, AHD_NEG_IF_NON_ASYNC); 2077 } 2078 2079 #define AHD_MAX_STEPS 2000 2080 void 2081 ahd_clear_critical_section(struct ahd_softc *ahd) 2082 { 2083 ahd_mode_state saved_modes; 2084 int stepping; 2085 int steps; 2086 int first_instr; 2087 u_int simode0; 2088 u_int simode1; 2089 u_int simode3; 2090 u_int lqimode0; 2091 u_int lqimode1; 2092 u_int lqomode0; 2093 u_int lqomode1; 2094 2095 if (ahd->num_critical_sections == 0) 2096 return; 2097 2098 stepping = FALSE; 2099 steps = 0; 2100 first_instr = 0; 2101 simode0 = 0; 2102 simode1 = 0; 2103 simode3 = 0; 2104 lqimode0 = 0; 2105 lqimode1 = 0; 2106 lqomode0 = 0; 2107 lqomode1 = 0; 2108 saved_modes = ahd_save_modes(ahd); 2109 for (;;) { 2110 struct cs *cs; 2111 u_int seqaddr; 2112 u_int i; 2113 2114 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2115 seqaddr = ahd_inb(ahd, CURADDR) 2116 | (ahd_inb(ahd, CURADDR+1) << 8); 2117 2118 cs = ahd->critical_sections; 2119 for (i = 0; i < ahd->num_critical_sections; i++, cs++) { 2120 2121 if (cs->begin < seqaddr && cs->end >= seqaddr) 2122 break; 2123 } 2124 2125 if (i == ahd->num_critical_sections) 2126 break; 2127 2128 if (steps > AHD_MAX_STEPS) { 2129 printf("%s: Infinite loop in critical section\n" 2130 "%s: First Instruction 0x%x now 0x%x\n", 2131 ahd_name(ahd), ahd_name(ahd), first_instr, 2132 seqaddr); 2133 ahd_dump_card_state(ahd); 2134 panic("critical section loop"); 2135 } 2136 2137 steps++; 2138 #ifdef AHD_DEBUG 2139 if ((ahd_debug & AHD_SHOW_MISC) != 0) 2140 printf("%s: Single stepping at 0x%x\n", ahd_name(ahd), 2141 seqaddr); 2142 #endif 2143 if (stepping == FALSE) { 2144 2145 first_instr = seqaddr; 2146 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 2147 simode0 = ahd_inb(ahd, SIMODE0); 2148 simode3 = ahd_inb(ahd, SIMODE3); 2149 lqimode0 = ahd_inb(ahd, LQIMODE0); 2150 lqimode1 = ahd_inb(ahd, LQIMODE1); 2151 lqomode0 = ahd_inb(ahd, LQOMODE0); 2152 lqomode1 = ahd_inb(ahd, LQOMODE1); 2153 ahd_outb(ahd, SIMODE0, 0); 2154 ahd_outb(ahd, SIMODE3, 0); 2155 ahd_outb(ahd, LQIMODE0, 0); 2156 ahd_outb(ahd, LQIMODE1, 0); 2157 ahd_outb(ahd, LQOMODE0, 0); 2158 ahd_outb(ahd, LQOMODE1, 0); 2159 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2160 simode1 = ahd_inb(ahd, SIMODE1); 2161 ahd_outb(ahd, SIMODE1, ENBUSFREE); 2162 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) | STEP); 2163 stepping = TRUE; 2164 } 2165 ahd_outb(ahd, CLRSINT1, CLRBUSFREE); 2166 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2167 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 2168 ahd_outb(ahd, HCNTRL, ahd->unpause); 2169 do { 2170 ahd_delay(200); 2171 } while (!ahd_is_paused(ahd)); 2172 ahd_update_modes(ahd); 2173 } 2174 if (stepping) { 2175 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 2176 ahd_outb(ahd, SIMODE0, simode0); 2177 ahd_outb(ahd, SIMODE3, simode3); 2178 ahd_outb(ahd, LQIMODE0, lqimode0); 2179 ahd_outb(ahd, LQIMODE1, lqimode1); 2180 ahd_outb(ahd, LQOMODE0, lqomode0); 2181 ahd_outb(ahd, LQOMODE1, lqomode1); 2182 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2183 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP); 2184 ahd_outb(ahd, SIMODE1, simode1); 2185 } 2186 ahd_restore_modes(ahd, saved_modes); 2187 } 2188 2189 /* 2190 * Clear any pending interrupt status. 2191 */ 2192 void 2193 ahd_clear_intstat(struct ahd_softc *ahd) 2194 { 2195 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 2196 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 2197 /* Clear any interrupt conditions this may have caused */ 2198 ahd_outb(ahd, CLRLQIINT0, CLRLQIATNQAS|CLRLQICRCT1|CLRLQICRCT2 2199 |CLRLQIBADLQT|CLRLQIATNLQ|CLRLQIATNCMD); 2200 ahd_outb(ahd, CLRLQIINT1, CLRLQIPHASE_LQ|CLRLQIPHASE_NLQ|CLRLIQABORT 2201 |CLRLQICRCI_LQ|CLRLQICRCI_NLQ|CLRLQIBADLQI 2202 |CLRLQIOVERI_LQ|CLRLQIOVERI_NLQ|CLRNONPACKREQ); 2203 ahd_outb(ahd, CLRLQOINT0, CLRLQOTARGSCBPERR|CLRLQOSTOPT2|CLRLQOATNLQ 2204 |CLRLQOATNPKT|CLRLQOTCRC); 2205 ahd_outb(ahd, CLRLQOINT1, CLRLQOINITSCBPERR|CLRLQOSTOPI2|CLRLQOBADQAS 2206 |CLRLQOBUSFREE|CLRLQOPHACHGINPKT); 2207 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 2208 ahd_outb(ahd, CLRLQOINT0, 0); 2209 ahd_outb(ahd, CLRLQOINT1, 0); 2210 } 2211 ahd_outb(ahd, CLRSINT3, CLRNTRAMPERR|CLROSRAMPERR); 2212 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 2213 |CLRBUSFREE|CLRSCSIPERR|CLRREQINIT); 2214 ahd_outb(ahd, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO 2215 |CLRIOERR|CLROVERRUN); 2216 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2217 } 2218 2219 /**************************** Debugging Routines ******************************/ 2220 #ifdef AHD_DEBUG 2221 uint32_t ahd_debug = AHD_DEBUG_OPTS; 2222 #endif 2223 void 2224 ahd_print_scb(struct scb *scb) 2225 { 2226 struct hardware_scb *hscb; 2227 int i; 2228 2229 hscb = scb->hscb; 2230 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 2231 (void *)scb, 2232 hscb->control, 2233 hscb->scsiid, 2234 hscb->lun, 2235 hscb->cdb_len); 2236 printf("Shared Data: "); 2237 for (i = 0; i < sizeof(hscb->shared_data.idata.cdb); i++) 2238 printf("%#02x", hscb->shared_data.idata.cdb[i]); 2239 printf(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n", 2240 (uint32_t)((ahd_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF), 2241 (uint32_t)(ahd_le64toh(hscb->dataptr) & 0xFFFFFFFF), 2242 ahd_le32toh(hscb->datacnt), 2243 ahd_le32toh(hscb->sgptr), 2244 SCB_GET_TAG(scb)); 2245 ahd_dump_sglist(scb); 2246 } 2247 2248 void 2249 ahd_dump_sglist(struct scb *scb) 2250 { 2251 int i; 2252 2253 if (scb->sg_count > 0) { 2254 if ((scb->ahd_softc->flags & AHD_64BIT_ADDRESSING) != 0) { 2255 struct ahd_dma64_seg *sg_list; 2256 2257 sg_list = (struct ahd_dma64_seg*)scb->sg_list; 2258 for (i = 0; i < scb->sg_count; i++) { 2259 uint64_t addr; 2260 uint32_t len; 2261 2262 addr = ahd_le64toh(sg_list[i].addr); 2263 len = ahd_le32toh(sg_list[i].len); 2264 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n", 2265 i, 2266 (uint32_t)((addr >> 32) & 0xFFFFFFFF), 2267 (uint32_t)(addr & 0xFFFFFFFF), 2268 sg_list[i].len & AHD_SG_LEN_MASK, 2269 (sg_list[i].len & AHD_DMA_LAST_SEG) 2270 ? " Last" : ""); 2271 } 2272 } else { 2273 struct ahd_dma_seg *sg_list; 2274 2275 sg_list = (struct ahd_dma_seg*)scb->sg_list; 2276 for (i = 0; i < scb->sg_count; i++) { 2277 uint32_t len; 2278 2279 len = ahd_le32toh(sg_list[i].len); 2280 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n", 2281 i, 2282 (len >> 24) & SG_HIGH_ADDR_BITS, 2283 ahd_le32toh(sg_list[i].addr), 2284 len & AHD_SG_LEN_MASK, 2285 len & AHD_DMA_LAST_SEG ? " Last" : ""); 2286 } 2287 } 2288 } 2289 } 2290 2291 /************************* Transfer Negotiation *******************************/ 2292 /* 2293 * Allocate per target mode instance (ID we respond to as a target) 2294 * transfer negotiation data structures. 2295 */ 2296 static struct ahd_tmode_tstate * 2297 ahd_alloc_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel) 2298 { 2299 struct ahd_tmode_tstate *master_tstate; 2300 struct ahd_tmode_tstate *tstate; 2301 int i; 2302 2303 master_tstate = ahd->enabled_targets[ahd->our_id]; 2304 if (ahd->enabled_targets[scsi_id] != NULL 2305 && ahd->enabled_targets[scsi_id] != master_tstate) 2306 panic("%s: ahd_alloc_tstate - Target already allocated", 2307 ahd_name(ahd)); 2308 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); 2309 if (tstate == NULL) 2310 return (NULL); 2311 2312 /* 2313 * If we have allocated a master tstate, copy user settings from 2314 * the master tstate (taken from SRAM or the EEPROM) for this 2315 * channel, but reset our current and goal settings to async/narrow 2316 * until an initiator talks to us. 2317 */ 2318 if (master_tstate != NULL) { 2319 memcpy(tstate, master_tstate, sizeof(*tstate)); 2320 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 2321 for (i = 0; i < 16; i++) { 2322 memset(&tstate->transinfo[i].curr, 0, 2323 sizeof(tstate->transinfo[i].curr)); 2324 memset(&tstate->transinfo[i].goal, 0, 2325 sizeof(tstate->transinfo[i].goal)); 2326 } 2327 } else 2328 memset(tstate, 0, sizeof(*tstate)); 2329 ahd->enabled_targets[scsi_id] = tstate; 2330 return (tstate); 2331 } 2332 2333 #ifdef AHD_TARGET_MODE 2334 /* 2335 * Free per target mode instance (ID we respond to as a target) 2336 * transfer negotiation data structures. 2337 */ 2338 static void 2339 ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force) 2340 { 2341 struct ahd_tmode_tstate *tstate; 2342 2343 /* 2344 * Don't clean up our "master" tstate. 2345 * It has our default user settings. 2346 */ 2347 if (scsi_id == ahd->our_id 2348 && force == FALSE) 2349 return; 2350 2351 tstate = ahd->enabled_targets[scsi_id]; 2352 if (tstate != NULL) 2353 free(tstate, M_DEVBUF); 2354 ahd->enabled_targets[scsi_id] = NULL; 2355 } 2356 #endif 2357 2358 /* 2359 * Called when we have an active connection to a target on the bus, 2360 * this function finds the nearest period to the input period limited 2361 * by the capabilities of the bus connectivity of and sync settings for 2362 * the target. 2363 */ 2364 void 2365 ahd_devlimited_syncrate(struct ahd_softc *ahd, 2366 struct ahd_initiator_tinfo *tinfo, 2367 u_int *period, u_int *ppr_options, role_t role) 2368 { 2369 struct ahd_transinfo *transinfo; 2370 u_int maxsync; 2371 2372 if ((ahd_inb(ahd, SBLKCTL) & ENAB40) != 0 2373 && (ahd_inb(ahd, SSTAT2) & EXP_ACTIVE) == 0) { 2374 maxsync = AHD_SYNCRATE_PACED; 2375 } else { 2376 maxsync = AHD_SYNCRATE_ULTRA; 2377 /* Can't do DT related options on an SE bus */ 2378 *ppr_options &= MSG_EXT_PPR_QAS_REQ; 2379 } 2380 /* 2381 * Never allow a value higher than our current goal 2382 * period otherwise we may allow a target initiated 2383 * negotiation to go above the limit as set by the 2384 * user. In the case of an initiator initiated 2385 * sync negotiation, we limit based on the user 2386 * setting. This allows the system to still accept 2387 * incoming negotiations even if target initiated 2388 * negotiation is not performed. 2389 */ 2390 if (role == ROLE_TARGET) 2391 transinfo = &tinfo->user; 2392 else 2393 transinfo = &tinfo->goal; 2394 *ppr_options &= (transinfo->ppr_options|MSG_EXT_PPR_PCOMP_EN); 2395 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 2396 maxsync = MAX(maxsync, AHD_SYNCRATE_ULTRA2); 2397 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2398 } 2399 if (transinfo->period == 0) { 2400 *period = 0; 2401 *ppr_options = 0; 2402 } else { 2403 *period = MAX(*period, transinfo->period); 2404 ahd_find_syncrate(ahd, period, ppr_options, maxsync); 2405 } 2406 } 2407 2408 /* 2409 * Look up the valid period to SCSIRATE conversion in our table. 2410 * Return the period and offset that should be sent to the target 2411 * if this was the beginning of an SDTR. 2412 */ 2413 void 2414 ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 2415 u_int *ppr_options, u_int maxsync) 2416 { 2417 if (*period < maxsync) 2418 *period = maxsync; 2419 2420 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) != 0 2421 && *period > AHD_SYNCRATE_MIN_DT) 2422 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2423 2424 if (*period > AHD_SYNCRATE_MIN) 2425 *period = 0; 2426 2427 /* Honor PPR option conformance rules. */ 2428 if (*period > AHD_SYNCRATE_PACED) 2429 *ppr_options &= ~MSG_EXT_PPR_RTI; 2430 2431 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0) 2432 *ppr_options &= (MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_QAS_REQ); 2433 2434 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0) 2435 *ppr_options &= MSG_EXT_PPR_QAS_REQ; 2436 2437 /* Skip all PACED only entries if IU is not available */ 2438 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0 2439 && *period < AHD_SYNCRATE_DT) 2440 *period = AHD_SYNCRATE_DT; 2441 2442 /* Skip all DT only entries if DT is not available */ 2443 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 2444 && *period < AHD_SYNCRATE_ULTRA2) 2445 *period = AHD_SYNCRATE_ULTRA2; 2446 } 2447 2448 /* 2449 * Truncate the given synchronous offset to a value the 2450 * current adapter type and syncrate are capable of. 2451 */ 2452 void 2453 ahd_validate_offset(struct ahd_softc *ahd, 2454 struct ahd_initiator_tinfo *tinfo, 2455 u_int period, u_int *offset, int wide, 2456 role_t role) 2457 { 2458 u_int maxoffset; 2459 2460 /* Limit offset to what we can do */ 2461 if (period == 0) 2462 maxoffset = 0; 2463 else if (period <= AHD_SYNCRATE_PACED) { 2464 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) 2465 maxoffset = MAX_OFFSET_PACED_BUG; 2466 else 2467 maxoffset = MAX_OFFSET_PACED; 2468 } else 2469 maxoffset = MAX_OFFSET_NON_PACED; 2470 *offset = MIN(*offset, maxoffset); 2471 if (tinfo != NULL) { 2472 if (role == ROLE_TARGET) 2473 *offset = MIN(*offset, tinfo->user.offset); 2474 else 2475 *offset = MIN(*offset, tinfo->goal.offset); 2476 } 2477 } 2478 2479 /* 2480 * Truncate the given transfer width parameter to a value the 2481 * current adapter type is capable of. 2482 */ 2483 void 2484 ahd_validate_width(struct ahd_softc *ahd, struct ahd_initiator_tinfo *tinfo, 2485 u_int *bus_width, role_t role) 2486 { 2487 switch (*bus_width) { 2488 default: 2489 if (ahd->features & AHD_WIDE) { 2490 /* Respond Wide */ 2491 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 2492 break; 2493 } 2494 /* FALLTHROUGH */ 2495 case MSG_EXT_WDTR_BUS_8_BIT: 2496 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 2497 break; 2498 } 2499 if (tinfo != NULL) { 2500 if (role == ROLE_TARGET) 2501 *bus_width = MIN(tinfo->user.width, *bus_width); 2502 else 2503 *bus_width = MIN(tinfo->goal.width, *bus_width); 2504 } 2505 } 2506 2507 /* 2508 * Update the bitmask of targets for which the controller should 2509 * negotiate with at the next convenient oportunity. This currently 2510 * means the next time we send the initial identify messages for 2511 * a new transaction. 2512 */ 2513 int 2514 ahd_update_neg_request(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2515 struct ahd_tmode_tstate *tstate, 2516 struct ahd_initiator_tinfo *tinfo, ahd_neg_type neg_type) 2517 { 2518 u_int auto_negotiate_orig; 2519 2520 auto_negotiate_orig = tstate->auto_negotiate; 2521 if (neg_type == AHD_NEG_ALWAYS) { 2522 /* 2523 * Force our "current" settings to be 2524 * unknown so that unless a bus reset 2525 * occurs the need to renegotiate is 2526 * recorded persistently. 2527 */ 2528 if ((ahd->features & AHD_WIDE) != 0) 2529 tinfo->curr.width = AHD_WIDTH_UNKNOWN; 2530 tinfo->curr.period = AHD_PERIOD_UNKNOWN; 2531 tinfo->curr.offset = AHD_OFFSET_UNKNOWN; 2532 } 2533 if (tinfo->curr.period != tinfo->goal.period 2534 || tinfo->curr.width != tinfo->goal.width 2535 || tinfo->curr.offset != tinfo->goal.offset 2536 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 2537 || (neg_type == AHD_NEG_IF_NON_ASYNC 2538 && (tinfo->goal.offset != 0 2539 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 2540 || tinfo->goal.ppr_options != 0))) 2541 tstate->auto_negotiate |= devinfo->target_mask; 2542 else 2543 tstate->auto_negotiate &= ~devinfo->target_mask; 2544 2545 return (auto_negotiate_orig != tstate->auto_negotiate); 2546 } 2547 2548 /* 2549 * Update the user/goal/curr tables of synchronous negotiation 2550 * parameters as well as, in the case of a current or active update, 2551 * any data structures on the host controller. In the case of an 2552 * active update, the specified target is currently talking to us on 2553 * the bus, so the transfer parameter update must take effect 2554 * immediately. 2555 */ 2556 void 2557 ahd_set_syncrate(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2558 u_int period, u_int offset, u_int ppr_options, 2559 u_int type, int paused) 2560 { 2561 struct ahd_initiator_tinfo *tinfo; 2562 struct ahd_tmode_tstate *tstate; 2563 u_int old_period; 2564 u_int old_offset; 2565 u_int old_ppr; 2566 int active; 2567 int update_needed; 2568 2569 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; 2570 update_needed = 0; 2571 2572 if (period == 0 || offset == 0) { 2573 period = 0; 2574 offset = 0; 2575 } 2576 2577 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 2578 devinfo->target, &tstate); 2579 2580 if ((type & AHD_TRANS_USER) != 0) { 2581 tinfo->user.period = period; 2582 tinfo->user.offset = offset; 2583 tinfo->user.ppr_options = ppr_options; 2584 } 2585 2586 if ((type & AHD_TRANS_GOAL) != 0) { 2587 tinfo->goal.period = period; 2588 tinfo->goal.offset = offset; 2589 tinfo->goal.ppr_options = ppr_options; 2590 } 2591 2592 old_period = tinfo->curr.period; 2593 old_offset = tinfo->curr.offset; 2594 old_ppr = tinfo->curr.ppr_options; 2595 2596 if ((type & AHD_TRANS_CUR) != 0 2597 && (old_period != period 2598 || old_offset != offset 2599 || old_ppr != ppr_options)) { 2600 2601 update_needed++; 2602 2603 tinfo->curr.period = period; 2604 tinfo->curr.offset = offset; 2605 tinfo->curr.ppr_options = ppr_options; 2606 2607 ahd_send_async(ahd, devinfo->channel, devinfo->target, 2608 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2609 if (bootverbose) { 2610 if (offset != 0) { 2611 int options; 2612 2613 printf("%s: target %d synchronous with " 2614 "period = 0x%x, offset = 0x%x", 2615 ahd_name(ahd), devinfo->target, 2616 period, offset); 2617 options = 0; 2618 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) { 2619 printf("(DT"); 2620 options++; 2621 } 2622 if ((ppr_options & MSG_EXT_PPR_IU_REQ) != 0) { 2623 printf("%s", options ? "|IU" : "(IU"); 2624 options++; 2625 } 2626 if ((ppr_options & MSG_EXT_PPR_RTI) != 0) { 2627 printf("%s", options ? "|RTI" : "(RTI"); 2628 options++; 2629 } 2630 if ((ppr_options & MSG_EXT_PPR_QAS_REQ) != 0) { 2631 printf("%s", options ? "|QAS" : "(QAS"); 2632 options++; 2633 } 2634 if (options != 0) 2635 printf(")\n"); 2636 else 2637 printf("\n"); 2638 } else { 2639 printf("%s: target %d using " 2640 "asynchronous transfers%s\n", 2641 ahd_name(ahd), devinfo->target, 2642 (ppr_options & MSG_EXT_PPR_QAS_REQ) != 0 2643 ? "(QAS)" : ""); 2644 } 2645 } 2646 } 2647 /* 2648 * Always refresh the neg-table to handle the case of the 2649 * sequencer setting the ENATNO bit for a MK_MESSAGE request. 2650 * We will always renegotiate in that case if this is a 2651 * packetized request. Also manage the busfree expected flag 2652 * from this common routine so that we catch changes due to 2653 * WDTR or SDTR messages. 2654 */ 2655 if ((type & AHD_TRANS_CUR) != 0) { 2656 if (!paused) 2657 ahd_pause(ahd); 2658 ahd_update_neg_table(ahd, devinfo, &tinfo->curr); 2659 if (!paused) 2660 ahd_unpause(ahd); 2661 if (ahd->msg_type != MSG_TYPE_NONE) { 2662 if ((old_ppr & MSG_EXT_PPR_IU_REQ) 2663 != (ppr_options & MSG_EXT_PPR_IU_REQ)) { 2664 #ifdef AHD_DEBUG 2665 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 2666 ahd_print_devinfo(ahd, devinfo); 2667 printf("Expecting IU Change busfree\n"); 2668 } 2669 #endif 2670 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE 2671 | MSG_FLAG_IU_REQ_CHANGED; 2672 } 2673 if ((old_ppr & MSG_EXT_PPR_IU_REQ) != 0) { 2674 #ifdef AHD_DEBUG 2675 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2676 printf("PPR with IU_REQ outstanding\n"); 2677 #endif 2678 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE; 2679 } 2680 } 2681 } 2682 2683 update_needed += ahd_update_neg_request(ahd, devinfo, tstate, 2684 tinfo, AHD_NEG_TO_GOAL); 2685 2686 if (update_needed && active) 2687 ahd_update_pending_scbs(ahd); 2688 } 2689 2690 /* 2691 * Update the user/goal/curr tables of wide negotiation 2692 * parameters as well as, in the case of a current or active update, 2693 * any data structures on the host controller. In the case of an 2694 * active update, the specified target is currently talking to us on 2695 * the bus, so the transfer parameter update must take effect 2696 * immediately. 2697 */ 2698 void 2699 ahd_set_width(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2700 u_int width, u_int type, int paused) 2701 { 2702 struct ahd_initiator_tinfo *tinfo; 2703 struct ahd_tmode_tstate *tstate; 2704 u_int oldwidth; 2705 int active; 2706 int update_needed; 2707 2708 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; 2709 update_needed = 0; 2710 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 2711 devinfo->target, &tstate); 2712 2713 if ((type & AHD_TRANS_USER) != 0) 2714 tinfo->user.width = width; 2715 2716 if ((type & AHD_TRANS_GOAL) != 0) 2717 tinfo->goal.width = width; 2718 2719 oldwidth = tinfo->curr.width; 2720 if ((type & AHD_TRANS_CUR) != 0 && oldwidth != width) { 2721 2722 update_needed++; 2723 2724 tinfo->curr.width = width; 2725 ahd_send_async(ahd, devinfo->channel, devinfo->target, 2726 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2727 if (bootverbose) { 2728 printf("%s: target %d using %dbit transfers\n", 2729 ahd_name(ahd), devinfo->target, 2730 8 * (0x01 << width)); 2731 } 2732 } 2733 2734 if ((type & AHD_TRANS_CUR) != 0) { 2735 if (!paused) 2736 ahd_pause(ahd); 2737 ahd_update_neg_table(ahd, devinfo, &tinfo->curr); 2738 if (!paused) 2739 ahd_unpause(ahd); 2740 } 2741 2742 update_needed += ahd_update_neg_request(ahd, devinfo, tstate, 2743 tinfo, AHD_NEG_TO_GOAL); 2744 if (update_needed && active) 2745 ahd_update_pending_scbs(ahd); 2746 2747 } 2748 2749 /* 2750 * Update the current state of tagged queuing for a given target. 2751 */ 2752 void 2753 ahd_set_tags(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2754 ahd_queue_alg alg) 2755 { 2756 ahd_platform_set_tags(ahd, devinfo, alg); 2757 ahd_send_async(ahd, devinfo->channel, devinfo->target, 2758 devinfo->lun, AC_TRANSFER_NEG, &alg); 2759 } 2760 2761 static void 2762 ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2763 struct ahd_transinfo *tinfo) 2764 { 2765 ahd_mode_state saved_modes; 2766 u_int period; 2767 u_int ppr_opts; 2768 u_int con_opts; 2769 u_int offset; 2770 u_int saved_negoaddr; 2771 uint8_t iocell_opts[sizeof(ahd->iocell_opts)]; 2772 2773 saved_modes = ahd_save_modes(ahd); 2774 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2775 2776 saved_negoaddr = ahd_inb(ahd, NEGOADDR); 2777 ahd_outb(ahd, NEGOADDR, devinfo->target); 2778 period = tinfo->period; 2779 offset = tinfo->offset; 2780 memcpy(iocell_opts, ahd->iocell_opts, sizeof(ahd->iocell_opts)); 2781 ppr_opts = tinfo->ppr_options & (MSG_EXT_PPR_QAS_REQ|MSG_EXT_PPR_DT_REQ 2782 |MSG_EXT_PPR_IU_REQ|MSG_EXT_PPR_RTI); 2783 con_opts = 0; 2784 if (period == 0) 2785 period = AHD_SYNCRATE_ASYNC; 2786 if (period == AHD_SYNCRATE_160) { 2787 2788 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) { 2789 /* 2790 * When the SPI4 spec was finalized, PACE transfers 2791 * was not made a configurable option in the PPR 2792 * message. Instead it is assumed to be enabled for 2793 * any syncrate faster than 80MHz. Nevertheless, 2794 * Harpoon2A4 allows this to be configurable. 2795 * 2796 * Harpoon2A4 also assumes at most 2 data bytes per 2797 * negotiated REQ/ACK offset. Paced transfers take 2798 * 4, so we must adjust our offset. 2799 */ 2800 ppr_opts |= PPROPT_PACE; 2801 offset *= 2; 2802 2803 /* 2804 * Harpoon2A assumed that there would be a 2805 * fallback rate between 160MHz and 80Mhz, 2806 * so 7 is used as the period factor rather 2807 * than 8 for 160MHz. 2808 */ 2809 period = AHD_SYNCRATE_REVA_160; 2810 } 2811 if ((tinfo->ppr_options & MSG_EXT_PPR_PCOMP_EN) == 0) 2812 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= 2813 ~AHD_PRECOMP_MASK; 2814 } else { 2815 /* 2816 * Precomp should be disabled for non-paced transfers. 2817 */ 2818 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; 2819 2820 if ((ahd->features & AHD_NEW_IOCELL_OPTS) != 0 2821 && (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0) { 2822 /* 2823 * Slow down our CRC interval to be 2824 * compatible with devices that can't 2825 * handle a CRC at full speed. 2826 */ 2827 con_opts |= ENSLOWCRC; 2828 } 2829 } 2830 2831 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP_SLEW); 2832 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_PRECOMP_SLEW_INDEX]); 2833 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_AMPLITUDE); 2834 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_AMPLITUDE_INDEX]); 2835 2836 ahd_outb(ahd, NEGPERIOD, period); 2837 ahd_outb(ahd, NEGPPROPTS, ppr_opts); 2838 ahd_outb(ahd, NEGOFFSET, offset); 2839 2840 if (tinfo->width == MSG_EXT_WDTR_BUS_16_BIT) 2841 con_opts |= WIDEXFER; 2842 2843 /* 2844 * During packetized transfers, the target will 2845 * give us the oportunity to send command packets 2846 * without us asserting attention. 2847 */ 2848 if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0) 2849 con_opts |= ENAUTOATNO; 2850 ahd_outb(ahd, NEGCONOPTS, con_opts); 2851 ahd_outb(ahd, NEGOADDR, saved_negoaddr); 2852 ahd_restore_modes(ahd, saved_modes); 2853 } 2854 2855 /* 2856 * When the transfer settings for a connection change, setup for 2857 * negotiation in pending SCBs to effect the change as quickly as 2858 * possible. We also cancel any negotiations that are scheduled 2859 * for inflight SCBs that have not been started yet. 2860 */ 2861 static void 2862 ahd_update_pending_scbs(struct ahd_softc *ahd) 2863 { 2864 struct scb *pending_scb; 2865 int pending_scb_count; 2866 int i; 2867 int paused; 2868 u_int saved_scbptr; 2869 ahd_mode_state saved_modes; 2870 2871 /* 2872 * Traverse the pending SCB list and ensure that all of the 2873 * SCBs there have the proper settings. We can only safely 2874 * clear the negotiation required flag (setting requires the 2875 * execution queue to be modified) and this is only possible 2876 * if we are not already attempting to select out for this 2877 * SCB. For this reason, all callers only call this routine 2878 * if we are changing the negotiation settings for the currently 2879 * active transaction on the bus. 2880 */ 2881 pending_scb_count = 0; 2882 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) { 2883 struct ahd_devinfo devinfo; 2884 struct hardware_scb *pending_hscb; 2885 struct ahd_initiator_tinfo *tinfo; 2886 struct ahd_tmode_tstate *tstate; 2887 2888 ahd_scb_devinfo(ahd, &devinfo, pending_scb); 2889 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel, 2890 devinfo.our_scsiid, 2891 devinfo.target, &tstate); 2892 pending_hscb = pending_scb->hscb; 2893 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 2894 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 2895 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 2896 pending_hscb->control &= ~MK_MESSAGE; 2897 } 2898 ahd_sync_scb(ahd, pending_scb, 2899 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2900 pending_scb_count++; 2901 } 2902 2903 if (pending_scb_count == 0) 2904 return; 2905 2906 if (ahd_is_paused(ahd)) { 2907 paused = 1; 2908 } else { 2909 paused = 0; 2910 ahd_pause(ahd); 2911 } 2912 2913 /* 2914 * Force the sequencer to reinitialize the selection for 2915 * the command at the head of the execution queue if it 2916 * has already been setup. The negotiation changes may 2917 * effect whether we select-out with ATN. 2918 */ 2919 saved_modes = ahd_save_modes(ahd); 2920 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2921 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 2922 saved_scbptr = ahd_get_scbptr(ahd); 2923 /* Ensure that the hscbs down on the card match the new information */ 2924 for (i = 0; i < ahd->scb_data.maxhscbs; i++) { 2925 struct hardware_scb *pending_hscb; 2926 u_int control; 2927 u_int scb_tag; 2928 2929 ahd_set_scbptr(ahd, i); 2930 scb_tag = i; 2931 pending_scb = ahd_lookup_scb(ahd, scb_tag); 2932 if (pending_scb == NULL) 2933 continue; 2934 2935 pending_hscb = pending_scb->hscb; 2936 control = ahd_inb_scbram(ahd, SCB_CONTROL); 2937 control &= ~MK_MESSAGE; 2938 control |= pending_hscb->control & MK_MESSAGE; 2939 ahd_outb(ahd, SCB_CONTROL, control); 2940 } 2941 ahd_set_scbptr(ahd, saved_scbptr); 2942 ahd_restore_modes(ahd, saved_modes); 2943 2944 if (paused == 0) 2945 ahd_unpause(ahd); 2946 } 2947 2948 /**************************** Pathing Information *****************************/ 2949 static void 2950 ahd_fetch_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 2951 { 2952 ahd_mode_state saved_modes; 2953 u_int saved_scsiid; 2954 role_t role; 2955 int our_id; 2956 2957 saved_modes = ahd_save_modes(ahd); 2958 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2959 2960 if (ahd_inb(ahd, SSTAT0) & TARGET) 2961 role = ROLE_TARGET; 2962 else 2963 role = ROLE_INITIATOR; 2964 2965 if (role == ROLE_TARGET 2966 && (ahd_inb(ahd, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 2967 /* We were selected, so pull our id from TARGIDIN */ 2968 our_id = ahd_inb(ahd, TARGIDIN) & OID; 2969 } else if (role == ROLE_TARGET) 2970 our_id = ahd_inb(ahd, TOWNID); 2971 else 2972 our_id = ahd_inb(ahd, IOWNID); 2973 2974 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); 2975 ahd_compile_devinfo(devinfo, 2976 our_id, 2977 SCSIID_TARGET(ahd, saved_scsiid), 2978 ahd_inb(ahd, SAVED_LUN), 2979 SCSIID_CHANNEL(ahd, saved_scsiid), 2980 role); 2981 ahd_restore_modes(ahd, saved_modes); 2982 } 2983 2984 void 2985 ahd_print_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 2986 { 2987 printf("%s:%c:%d:%d: ", ahd_name(ahd), 'A', 2988 devinfo->target, devinfo->lun); 2989 } 2990 2991 struct ahd_phase_table_entry* 2992 ahd_lookup_phase_entry(int phase) 2993 { 2994 struct ahd_phase_table_entry *entry; 2995 struct ahd_phase_table_entry *last_entry; 2996 2997 /* 2998 * num_phases doesn't include the default entry which 2999 * will be returned if the phase doesn't match. 3000 */ 3001 last_entry = &ahd_phase_table[num_phases]; 3002 for (entry = ahd_phase_table; entry < last_entry; entry++) { 3003 if (phase == entry->phase) 3004 break; 3005 } 3006 return (entry); 3007 } 3008 3009 void 3010 ahd_compile_devinfo(struct ahd_devinfo *devinfo, u_int our_id, u_int target, 3011 u_int lun, char channel, role_t role) 3012 { 3013 devinfo->our_scsiid = our_id; 3014 devinfo->target = target; 3015 devinfo->lun = lun; 3016 devinfo->target_offset = target; 3017 devinfo->channel = channel; 3018 devinfo->role = role; 3019 if (channel == 'B') 3020 devinfo->target_offset += 8; 3021 devinfo->target_mask = (0x01 << devinfo->target_offset); 3022 } 3023 3024 static void 3025 ahd_scb_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3026 struct scb *scb) 3027 { 3028 role_t role; 3029 int our_id; 3030 3031 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 3032 role = ROLE_INITIATOR; 3033 if ((scb->hscb->control & TARGET_SCB) != 0) 3034 role = ROLE_TARGET; 3035 ahd_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahd, scb), 3036 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahd, scb), role); 3037 } 3038 3039 3040 /************************ Message Phase Processing ****************************/ 3041 /* 3042 * When an initiator transaction with the MK_MESSAGE flag either reconnects 3043 * or enters the initial message out phase, we are interrupted. Fill our 3044 * outgoing message buffer with the appropriate message and beging handing 3045 * the message phase(s) manually. 3046 */ 3047 static void 3048 ahd_setup_initiator_msgout(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3049 struct scb *scb) 3050 { 3051 /* 3052 * To facilitate adding multiple messages together, 3053 * each routine should increment the index and len 3054 * variables instead of setting them explicitly. 3055 */ 3056 ahd->msgout_index = 0; 3057 ahd->msgout_len = 0; 3058 3059 if (ahd_currently_packetized(ahd)) 3060 ahd->msg_flags |= MSG_FLAG_PACKETIZED; 3061 3062 if (ahd->send_msg_perror 3063 && ahd_inb(ahd, MSG_OUT) == HOST_MSG) { 3064 ahd->msgout_buf[ahd->msgout_index++] = ahd->send_msg_perror; 3065 ahd->msgout_len++; 3066 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3067 #ifdef AHD_DEBUG 3068 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3069 printf("Setting up for Parity Error delivery\n"); 3070 #endif 3071 return; 3072 } else if (scb == NULL) { 3073 printf("%s: WARNING. No pending message for " 3074 "I_T msgin. Issuing NO-OP\n", ahd_name(ahd)); 3075 ahd->msgout_buf[ahd->msgout_index++] = MSG_NOOP; 3076 ahd->msgout_len++; 3077 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3078 return; 3079 } 3080 3081 if ((scb->flags & SCB_DEVICE_RESET) == 0 3082 && (scb->flags & SCB_PACKETIZED) == 0 3083 && ahd_inb(ahd, MSG_OUT) == MSG_IDENTIFYFLAG) { 3084 u_int identify_msg; 3085 3086 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 3087 if ((scb->hscb->control & DISCENB) != 0) 3088 identify_msg |= MSG_IDENTIFY_DISCFLAG; 3089 ahd->msgout_buf[ahd->msgout_index++] = identify_msg; 3090 ahd->msgout_len++; 3091 3092 if ((scb->hscb->control & TAG_ENB) != 0) { 3093 ahd->msgout_buf[ahd->msgout_index++] = 3094 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 3095 ahd->msgout_buf[ahd->msgout_index++] = SCB_GET_TAG(scb); 3096 ahd->msgout_len += 2; 3097 } 3098 } 3099 3100 if (scb->flags & SCB_DEVICE_RESET) { 3101 ahd->msgout_buf[ahd->msgout_index++] = MSG_BUS_DEV_RESET; 3102 ahd->msgout_len++; 3103 ahd_print_path(ahd, scb); 3104 printf("Bus Device Reset Message Sent\n"); 3105 /* 3106 * Clear our selection hardware in advance of 3107 * the busfree. We may have an entry in the waiting 3108 * Q for this target, and we don't want to go about 3109 * selecting while we handle the busfree and blow it 3110 * away. 3111 */ 3112 ahd_outb(ahd, SCSISEQ0, 0); 3113 } else if ((scb->flags & SCB_ABORT) != 0) { 3114 3115 if ((scb->hscb->control & TAG_ENB) != 0) { 3116 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT_TAG; 3117 } else { 3118 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT; 3119 } 3120 ahd->msgout_len++; 3121 ahd_print_path(ahd, scb); 3122 printf("Abort%s Message Sent\n", 3123 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 3124 /* 3125 * Clear our selection hardware in advance of 3126 * the busfree. We may have an entry in the waiting 3127 * Q for this target, and we don't want to go about 3128 * selecting while we handle the busfree and blow it 3129 * away. 3130 */ 3131 ahd_outb(ahd, SCSISEQ0, 0); 3132 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 3133 ahd_build_transfer_msg(ahd, devinfo); 3134 /* 3135 * Clear our selection hardware in advance of potential 3136 * PPR IU status change busfree. We may have an entry in 3137 * the waiting Q for this target, and we don't want to go 3138 * about selecting while we handle the busfree and blow 3139 * it away. 3140 */ 3141 ahd_outb(ahd, SCSISEQ0, 0); 3142 } else { 3143 printf("ahd_intr: AWAITING_MSG for an SCB that " 3144 "does not have a waiting message\n"); 3145 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 3146 devinfo->target_mask); 3147 panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x " 3148 "SCB flags = %x", SCB_GET_TAG(scb), scb->hscb->control, 3149 ahd_inb(ahd, SCB_CONTROL), ahd_inb(ahd, MSG_OUT), 3150 scb->flags); 3151 } 3152 3153 /* 3154 * Clear the MK_MESSAGE flag from the SCB so we aren't 3155 * asked to send this message again. 3156 */ 3157 ahd_outb(ahd, SCB_CONTROL, 3158 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE); 3159 scb->hscb->control &= ~MK_MESSAGE; 3160 ahd->msgout_index = 0; 3161 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3162 } 3163 3164 /* 3165 * Build an appropriate transfer negotiation message for the 3166 * currently active target. 3167 */ 3168 static void 3169 ahd_build_transfer_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3170 { 3171 /* 3172 * We need to initiate transfer negotiations. 3173 * If our current and goal settings are identical, 3174 * we want to renegotiate due to a check condition. 3175 */ 3176 struct ahd_initiator_tinfo *tinfo; 3177 struct ahd_tmode_tstate *tstate; 3178 int dowide; 3179 int dosync; 3180 int doppr; 3181 u_int period; 3182 u_int ppr_options; 3183 u_int offset; 3184 3185 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3186 devinfo->target, &tstate); 3187 /* 3188 * Filter our period based on the current connection. 3189 * If we can't perform DT transfers on this segment (not in LVD 3190 * mode for instance), then our decision to issue a PPR message 3191 * may change. 3192 */ 3193 period = tinfo->goal.period; 3194 ppr_options = tinfo->goal.ppr_options; 3195 /* Target initiated PPR is not allowed in the SCSI spec */ 3196 if (devinfo->role == ROLE_TARGET) 3197 ppr_options = 0; 3198 ahd_devlimited_syncrate(ahd, tinfo, &period, 3199 &ppr_options, devinfo->role); 3200 dowide = tinfo->curr.width != tinfo->goal.width; 3201 dosync = tinfo->curr.period != period; 3202 /* 3203 * Only use PPR if we have options that need it, even if the device 3204 * claims to support it. There might be an expander in the way 3205 * that doesn't. 3206 */ 3207 doppr = ppr_options != 0; 3208 3209 if (!dowide && !dosync && !doppr) { 3210 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 3211 dosync = tinfo->goal.period != 0; 3212 } 3213 3214 if (!dowide && !dosync && !doppr) { 3215 /* 3216 * Force async with a WDTR message if we have a wide bus, 3217 * or just issue an SDTR with a 0 offset. 3218 */ 3219 if ((ahd->features & AHD_WIDE) != 0) 3220 dowide = 1; 3221 else 3222 dosync = 1; 3223 3224 if (bootverbose) { 3225 ahd_print_devinfo(ahd, devinfo); 3226 printf("Ensuring async\n"); 3227 } 3228 } 3229 /* Target initiated PPR is not allowed in the SCSI spec */ 3230 if (devinfo->role == ROLE_TARGET) 3231 doppr = 0; 3232 3233 /* 3234 * Both the PPR message and SDTR message require the 3235 * goal syncrate to be limited to what the target device 3236 * is capable of handling (based on whether an LVD->SE 3237 * expander is on the bus), so combine these two cases. 3238 * Regardless, guarantee that if we are using WDTR and SDTR 3239 * messages that WDTR comes first. 3240 */ 3241 if (doppr || (dosync && !dowide)) { 3242 3243 offset = tinfo->goal.offset; 3244 ahd_validate_offset(ahd, tinfo, period, &offset, 3245 doppr ? tinfo->goal.width 3246 : tinfo->curr.width, 3247 devinfo->role); 3248 if (doppr) { 3249 ahd_construct_ppr(ahd, devinfo, period, offset, 3250 tinfo->goal.width, ppr_options); 3251 } else { 3252 ahd_construct_sdtr(ahd, devinfo, period, offset); 3253 } 3254 } else { 3255 ahd_construct_wdtr(ahd, devinfo, tinfo->goal.width); 3256 } 3257 } 3258 3259 /* 3260 * Build a synchronous negotiation message in our message 3261 * buffer based on the input parameters. 3262 */ 3263 static void 3264 ahd_construct_sdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3265 u_int period, u_int offset) 3266 { 3267 if (offset == 0) 3268 period = AHD_ASYNC_XFER_PERIOD; 3269 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3270 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR_LEN; 3271 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR; 3272 ahd->msgout_buf[ahd->msgout_index++] = period; 3273 ahd->msgout_buf[ahd->msgout_index++] = offset; 3274 ahd->msgout_len += 5; 3275 if (bootverbose) { 3276 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 3277 ahd_name(ahd), devinfo->channel, devinfo->target, 3278 devinfo->lun, period, offset); 3279 } 3280 } 3281 3282 /* 3283 * Build a wide negotiateion message in our message 3284 * buffer based on the input parameters. 3285 */ 3286 static void 3287 ahd_construct_wdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3288 u_int bus_width) 3289 { 3290 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3291 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR_LEN; 3292 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR; 3293 ahd->msgout_buf[ahd->msgout_index++] = bus_width; 3294 ahd->msgout_len += 4; 3295 if (bootverbose) { 3296 printf("(%s:%c:%d:%d): Sending WDTR %x\n", 3297 ahd_name(ahd), devinfo->channel, devinfo->target, 3298 devinfo->lun, bus_width); 3299 } 3300 } 3301 3302 /* 3303 * Build a parallel protocol request message in our message 3304 * buffer based on the input parameters. 3305 */ 3306 static void 3307 ahd_construct_ppr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3308 u_int period, u_int offset, u_int bus_width, 3309 u_int ppr_options) 3310 { 3311 /* 3312 * Always request precompensation from 3313 * the other target if we are running 3314 * at paced syncrates. 3315 */ 3316 if (period <= AHD_SYNCRATE_PACED) 3317 ppr_options |= MSG_EXT_PPR_PCOMP_EN; 3318 if (offset == 0) 3319 period = AHD_ASYNC_XFER_PERIOD; 3320 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3321 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR_LEN; 3322 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR; 3323 ahd->msgout_buf[ahd->msgout_index++] = period; 3324 ahd->msgout_buf[ahd->msgout_index++] = 0; 3325 ahd->msgout_buf[ahd->msgout_index++] = offset; 3326 ahd->msgout_buf[ahd->msgout_index++] = bus_width; 3327 ahd->msgout_buf[ahd->msgout_index++] = ppr_options; 3328 ahd->msgout_len += 8; 3329 if (bootverbose) { 3330 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, " 3331 "offset %x, ppr_options %x\n", ahd_name(ahd), 3332 devinfo->channel, devinfo->target, devinfo->lun, 3333 bus_width, period, offset, ppr_options); 3334 } 3335 } 3336 3337 /* 3338 * Clear any active message state. 3339 */ 3340 static void 3341 ahd_clear_msg_state(struct ahd_softc *ahd) 3342 { 3343 ahd_mode_state saved_modes; 3344 3345 saved_modes = ahd_save_modes(ahd); 3346 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3347 ahd->send_msg_perror = 0; 3348 ahd->msg_flags = MSG_FLAG_NONE; 3349 ahd->msgout_len = 0; 3350 ahd->msgin_index = 0; 3351 ahd->msg_type = MSG_TYPE_NONE; 3352 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { 3353 /* 3354 * The target didn't care to respond to our 3355 * message request, so clear ATN. 3356 */ 3357 ahd_outb(ahd, CLRSINT1, CLRATNO); 3358 } 3359 ahd_outb(ahd, MSG_OUT, MSG_NOOP); 3360 ahd_outb(ahd, SEQ_FLAGS2, 3361 ahd_inb(ahd, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 3362 ahd_restore_modes(ahd, saved_modes); 3363 } 3364 3365 /* 3366 * Manual message loop handler. 3367 */ 3368 static void 3369 ahd_handle_message_phase(struct ahd_softc *ahd) 3370 { 3371 struct ahd_devinfo devinfo; 3372 u_int bus_phase; 3373 int end_session; 3374 3375 ahd_fetch_devinfo(ahd, &devinfo); 3376 end_session = FALSE; 3377 bus_phase = ahd_inb(ahd, LASTPHASE); 3378 3379 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0) { 3380 printf("LQIRETRY for LQIPHASE_OUTPKT\n"); 3381 ahd_outb(ahd, LQCTL2, LQIRETRY); 3382 } 3383 reswitch: 3384 switch (ahd->msg_type) { 3385 case MSG_TYPE_INITIATOR_MSGOUT: 3386 { 3387 int lastbyte; 3388 int phasemis; 3389 int msgdone; 3390 3391 if (ahd->msgout_len == 0 && ahd->send_msg_perror == 0) 3392 panic("HOST_MSG_LOOP interrupt with no active message"); 3393 3394 #ifdef AHD_DEBUG 3395 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3396 ahd_print_devinfo(ahd, &devinfo); 3397 printf("INITIATOR_MSG_OUT"); 3398 } 3399 #endif 3400 phasemis = bus_phase != P_MESGOUT; 3401 if (phasemis) { 3402 #ifdef AHD_DEBUG 3403 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3404 printf(" PHASEMIS %s\n", 3405 ahd_lookup_phase_entry(bus_phase) 3406 ->phasemsg); 3407 } 3408 #endif 3409 if (bus_phase == P_MESGIN) { 3410 /* 3411 * Change gears and see if 3412 * this messages is of interest to 3413 * us or should be passed back to 3414 * the sequencer. 3415 */ 3416 ahd_outb(ahd, CLRSINT1, CLRATNO); 3417 ahd->send_msg_perror = 0; 3418 ahd->msg_type = MSG_TYPE_INITIATOR_MSGIN; 3419 ahd->msgin_index = 0; 3420 goto reswitch; 3421 } 3422 end_session = TRUE; 3423 break; 3424 } 3425 3426 if (ahd->send_msg_perror) { 3427 ahd_outb(ahd, CLRSINT1, CLRATNO); 3428 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3429 #ifdef AHD_DEBUG 3430 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3431 printf(" byte 0x%x\n", ahd->send_msg_perror); 3432 #endif 3433 /* 3434 * If we are notifying the target of a CRC error 3435 * during packetized operations, the target is 3436 * within its rights to acknowledge our message 3437 * with a busfree. 3438 */ 3439 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0 3440 && ahd->send_msg_perror == MSG_INITIATOR_DET_ERR) 3441 ahd->msg_flags |= MSG_FLAG_EXPECT_IDE_BUSFREE; 3442 3443 ahd_outb(ahd, RETURN_2, ahd->send_msg_perror); 3444 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); 3445 break; 3446 } 3447 3448 msgdone = ahd->msgout_index == ahd->msgout_len; 3449 if (msgdone) { 3450 /* 3451 * The target has requested a retry. 3452 * Re-assert ATN, reset our message index to 3453 * 0, and try again. 3454 */ 3455 ahd->msgout_index = 0; 3456 ahd_assert_atn(ahd); 3457 } 3458 3459 lastbyte = ahd->msgout_index == (ahd->msgout_len - 1); 3460 if (lastbyte) { 3461 /* Last byte is signified by dropping ATN */ 3462 ahd_outb(ahd, CLRSINT1, CLRATNO); 3463 } 3464 3465 /* 3466 * Clear our interrupt status and present 3467 * the next byte on the bus. 3468 */ 3469 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3470 #ifdef AHD_DEBUG 3471 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3472 printf(" byte 0x%x\n", 3473 ahd->msgout_buf[ahd->msgout_index]); 3474 #endif 3475 ahd_outb(ahd, RETURN_2, ahd->msgout_buf[ahd->msgout_index++]); 3476 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); 3477 break; 3478 } 3479 case MSG_TYPE_INITIATOR_MSGIN: 3480 { 3481 int phasemis; 3482 int message_done; 3483 3484 #ifdef AHD_DEBUG 3485 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3486 ahd_print_devinfo(ahd, &devinfo); 3487 printf("INITIATOR_MSG_IN"); 3488 } 3489 #endif 3490 phasemis = bus_phase != P_MESGIN; 3491 if (phasemis) { 3492 #ifdef AHD_DEBUG 3493 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3494 printf(" PHASEMIS %s\n", 3495 ahd_lookup_phase_entry(bus_phase) 3496 ->phasemsg); 3497 } 3498 #endif 3499 ahd->msgin_index = 0; 3500 if (bus_phase == P_MESGOUT 3501 && (ahd->send_msg_perror != 0 3502 || (ahd->msgout_len != 0 3503 && ahd->msgout_index == 0))) { 3504 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3505 goto reswitch; 3506 } 3507 end_session = TRUE; 3508 break; 3509 } 3510 3511 /* Pull the byte in without acking it */ 3512 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIBUS); 3513 #ifdef AHD_DEBUG 3514 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3515 printf(" byte 0x%x\n", 3516 ahd->msgin_buf[ahd->msgin_index]); 3517 #endif 3518 3519 message_done = ahd_parse_msg(ahd, &devinfo); 3520 3521 if (message_done) { 3522 /* 3523 * Clear our incoming message buffer in case there 3524 * is another message following this one. 3525 */ 3526 ahd->msgin_index = 0; 3527 3528 /* 3529 * If this message illicited a response, 3530 * assert ATN so the target takes us to the 3531 * message out phase. 3532 */ 3533 if (ahd->msgout_len != 0) { 3534 #ifdef AHD_DEBUG 3535 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3536 ahd_print_devinfo(ahd, &devinfo); 3537 printf("Asserting ATN for response\n"); 3538 } 3539 #endif 3540 ahd_assert_atn(ahd); 3541 } 3542 } else 3543 ahd->msgin_index++; 3544 3545 if (message_done == MSGLOOP_TERMINATED) { 3546 end_session = TRUE; 3547 } else { 3548 /* Ack the byte */ 3549 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3550 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_READ); 3551 } 3552 break; 3553 } 3554 case MSG_TYPE_TARGET_MSGIN: 3555 { 3556 int msgdone; 3557 int msgout_request; 3558 3559 /* 3560 * By default, the message loop will continue. 3561 */ 3562 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); 3563 3564 if (ahd->msgout_len == 0) 3565 panic("Target MSGIN with no active message"); 3566 3567 /* 3568 * If we interrupted a mesgout session, the initiator 3569 * will not know this until our first REQ. So, we 3570 * only honor mesgout requests after we've sent our 3571 * first byte. 3572 */ 3573 if ((ahd_inb(ahd, SCSISIGI) & ATNI) != 0 3574 && ahd->msgout_index > 0) 3575 msgout_request = TRUE; 3576 else 3577 msgout_request = FALSE; 3578 3579 if (msgout_request) { 3580 3581 /* 3582 * Change gears and see if 3583 * this messages is of interest to 3584 * us or should be passed back to 3585 * the sequencer. 3586 */ 3587 ahd->msg_type = MSG_TYPE_TARGET_MSGOUT; 3588 ahd_outb(ahd, SCSISIGO, P_MESGOUT | BSYO); 3589 ahd->msgin_index = 0; 3590 /* Dummy read to REQ for first byte */ 3591 ahd_inb(ahd, SCSIDAT); 3592 ahd_outb(ahd, SXFRCTL0, 3593 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3594 break; 3595 } 3596 3597 msgdone = ahd->msgout_index == ahd->msgout_len; 3598 if (msgdone) { 3599 ahd_outb(ahd, SXFRCTL0, 3600 ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); 3601 end_session = TRUE; 3602 break; 3603 } 3604 3605 /* 3606 * Present the next byte on the bus. 3607 */ 3608 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3609 ahd_outb(ahd, SCSIDAT, ahd->msgout_buf[ahd->msgout_index++]); 3610 break; 3611 } 3612 case MSG_TYPE_TARGET_MSGOUT: 3613 { 3614 int lastbyte; 3615 int msgdone; 3616 3617 /* 3618 * By default, the message loop will continue. 3619 */ 3620 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); 3621 3622 /* 3623 * The initiator signals that this is 3624 * the last byte by dropping ATN. 3625 */ 3626 lastbyte = (ahd_inb(ahd, SCSISIGI) & ATNI) == 0; 3627 3628 /* 3629 * Read the latched byte, but turn off SPIOEN first 3630 * so that we don't inadvertently cause a REQ for the 3631 * next byte. 3632 */ 3633 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); 3634 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIDAT); 3635 msgdone = ahd_parse_msg(ahd, &devinfo); 3636 if (msgdone == MSGLOOP_TERMINATED) { 3637 /* 3638 * The message is *really* done in that it caused 3639 * us to go to bus free. The sequencer has already 3640 * been reset at this point, so pull the ejection 3641 * handle. 3642 */ 3643 return; 3644 } 3645 3646 ahd->msgin_index++; 3647 3648 /* 3649 * XXX Read spec about initiator dropping ATN too soon 3650 * and use msgdone to detect it. 3651 */ 3652 if (msgdone == MSGLOOP_MSGCOMPLETE) { 3653 ahd->msgin_index = 0; 3654 3655 /* 3656 * If this message illicited a response, transition 3657 * to the Message in phase and send it. 3658 */ 3659 if (ahd->msgout_len != 0) { 3660 ahd_outb(ahd, SCSISIGO, P_MESGIN | BSYO); 3661 ahd_outb(ahd, SXFRCTL0, 3662 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3663 ahd->msg_type = MSG_TYPE_TARGET_MSGIN; 3664 ahd->msgin_index = 0; 3665 break; 3666 } 3667 } 3668 3669 if (lastbyte) 3670 end_session = TRUE; 3671 else { 3672 /* Ask for the next byte. */ 3673 ahd_outb(ahd, SXFRCTL0, 3674 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3675 } 3676 3677 break; 3678 } 3679 default: 3680 panic("Unknown REQINIT message type"); 3681 } 3682 3683 if (end_session) { 3684 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0) { 3685 printf("%s: Returning to Idle Loop\n", 3686 ahd_name(ahd)); 3687 ahd_outb(ahd, LASTPHASE, P_BUSFREE); 3688 ahd_clear_msg_state(ahd); 3689 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); 3690 } else { 3691 ahd_clear_msg_state(ahd); 3692 ahd_outb(ahd, RETURN_1, EXIT_MSG_LOOP); 3693 } 3694 } 3695 } 3696 3697 /* 3698 * See if we sent a particular extended message to the target. 3699 * If "full" is true, return true only if the target saw the full 3700 * message. If "full" is false, return true if the target saw at 3701 * least the first byte of the message. 3702 */ 3703 static int 3704 ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, u_int msgval, int full) 3705 { 3706 int found; 3707 u_int index; 3708 3709 found = FALSE; 3710 index = 0; 3711 3712 while (index < ahd->msgout_len) { 3713 if (ahd->msgout_buf[index] == MSG_EXTENDED) { 3714 u_int end_index; 3715 3716 end_index = index + 1 + ahd->msgout_buf[index + 1]; 3717 if (ahd->msgout_buf[index+2] == msgval 3718 && type == AHDMSG_EXT) { 3719 3720 if (full) { 3721 if (ahd->msgout_index > end_index) 3722 found = TRUE; 3723 } else if (ahd->msgout_index > index) 3724 found = TRUE; 3725 } 3726 index = end_index; 3727 } else if (ahd->msgout_buf[index] >= MSG_SIMPLE_TASK 3728 && ahd->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 3729 3730 /* Skip tag type and tag id or residue param*/ 3731 index += 2; 3732 } else { 3733 /* Single byte message */ 3734 if (type == AHDMSG_1B 3735 && ahd->msgout_index > index 3736 && (ahd->msgout_buf[index] == msgval 3737 || ((ahd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0 3738 && msgval == MSG_IDENTIFYFLAG))) 3739 found = TRUE; 3740 index++; 3741 } 3742 3743 if (found) 3744 break; 3745 } 3746 return (found); 3747 } 3748 3749 /* 3750 * Wait for a complete incoming message, parse it, and respond accordingly. 3751 */ 3752 static int 3753 ahd_parse_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3754 { 3755 struct ahd_initiator_tinfo *tinfo; 3756 struct ahd_tmode_tstate *tstate; 3757 int reject; 3758 int done; 3759 int response; 3760 3761 done = MSGLOOP_IN_PROG; 3762 response = FALSE; 3763 reject = FALSE; 3764 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3765 devinfo->target, &tstate); 3766 3767 /* 3768 * Parse as much of the message as is availible, 3769 * rejecting it if we don't support it. When 3770 * the entire message is availible and has been 3771 * handled, return MSGLOOP_MSGCOMPLETE, indicating 3772 * that we have parsed an entire message. 3773 * 3774 * In the case of extended messages, we accept the length 3775 * byte outright and perform more checking once we know the 3776 * extended message type. 3777 */ 3778 switch (ahd->msgin_buf[0]) { 3779 case MSG_DISCONNECT: 3780 case MSG_SAVEDATAPOINTER: 3781 case MSG_CMDCOMPLETE: 3782 case MSG_RESTOREPOINTERS: 3783 case MSG_IGN_WIDE_RESIDUE: 3784 /* 3785 * End our message loop as these are messages 3786 * the sequencer handles on its own. 3787 */ 3788 done = MSGLOOP_TERMINATED; 3789 break; 3790 case MSG_MESSAGE_REJECT: 3791 response = ahd_handle_msg_reject(ahd, devinfo); 3792 /* FALLTHROUGH */ 3793 case MSG_NOOP: 3794 done = MSGLOOP_MSGCOMPLETE; 3795 break; 3796 case MSG_EXTENDED: 3797 { 3798 /* Wait for enough of the message to begin validation */ 3799 if (ahd->msgin_index < 2) 3800 break; 3801 switch (ahd->msgin_buf[2]) { 3802 case MSG_EXT_SDTR: 3803 { 3804 u_int period; 3805 u_int ppr_options; 3806 u_int offset; 3807 u_int saved_offset; 3808 3809 if (ahd->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 3810 reject = TRUE; 3811 break; 3812 } 3813 3814 /* 3815 * Wait until we have both args before validating 3816 * and acting on this message. 3817 * 3818 * Add one to MSG_EXT_SDTR_LEN to account for 3819 * the extended message preamble. 3820 */ 3821 if (ahd->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 3822 break; 3823 3824 period = ahd->msgin_buf[3]; 3825 ppr_options = 0; 3826 saved_offset = offset = ahd->msgin_buf[4]; 3827 ahd_devlimited_syncrate(ahd, tinfo, &period, 3828 &ppr_options, devinfo->role); 3829 ahd_validate_offset(ahd, tinfo, period, &offset, 3830 tinfo->curr.width, devinfo->role); 3831 if (bootverbose) { 3832 printf("(%s:%c:%d:%d): Received " 3833 "SDTR period %x, offset %x\n\t" 3834 "Filtered to period %x, offset %x\n", 3835 ahd_name(ahd), devinfo->channel, 3836 devinfo->target, devinfo->lun, 3837 ahd->msgin_buf[3], saved_offset, 3838 period, offset); 3839 } 3840 ahd_set_syncrate(ahd, devinfo, period, 3841 offset, ppr_options, 3842 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 3843 /*paused*/TRUE); 3844 3845 /* 3846 * See if we initiated Sync Negotiation 3847 * and didn't have to fall down to async 3848 * transfers. 3849 */ 3850 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, TRUE)) { 3851 /* We started it */ 3852 if (saved_offset != offset) { 3853 /* Went too low - force async */ 3854 reject = TRUE; 3855 } 3856 } else { 3857 /* 3858 * Send our own SDTR in reply 3859 */ 3860 if (bootverbose 3861 && devinfo->role == ROLE_INITIATOR) { 3862 printf("(%s:%c:%d:%d): Target " 3863 "Initiated SDTR\n", 3864 ahd_name(ahd), devinfo->channel, 3865 devinfo->target, devinfo->lun); 3866 } 3867 ahd->msgout_index = 0; 3868 ahd->msgout_len = 0; 3869 ahd_construct_sdtr(ahd, devinfo, 3870 period, offset); 3871 ahd->msgout_index = 0; 3872 response = TRUE; 3873 } 3874 done = MSGLOOP_MSGCOMPLETE; 3875 break; 3876 } 3877 case MSG_EXT_WDTR: 3878 { 3879 u_int bus_width; 3880 u_int saved_width; 3881 u_int sending_reply; 3882 3883 sending_reply = FALSE; 3884 if (ahd->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3885 reject = TRUE; 3886 break; 3887 } 3888 3889 /* 3890 * Wait until we have our arg before validating 3891 * and acting on this message. 3892 * 3893 * Add one to MSG_EXT_WDTR_LEN to account for 3894 * the extended message preamble. 3895 */ 3896 if (ahd->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3897 break; 3898 3899 bus_width = ahd->msgin_buf[3]; 3900 saved_width = bus_width; 3901 ahd_validate_width(ahd, tinfo, &bus_width, 3902 devinfo->role); 3903 if (bootverbose) { 3904 printf("(%s:%c:%d:%d): Received WDTR " 3905 "%x filtered to %x\n", 3906 ahd_name(ahd), devinfo->channel, 3907 devinfo->target, devinfo->lun, 3908 saved_width, bus_width); 3909 } 3910 3911 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, TRUE)) { 3912 /* 3913 * Don't send a WDTR back to the 3914 * target, since we asked first. 3915 * If the width went higher than our 3916 * request, reject it. 3917 */ 3918 if (saved_width > bus_width) { 3919 reject = TRUE; 3920 printf("(%s:%c:%d:%d): requested %dBit " 3921 "transfers. Rejecting...\n", 3922 ahd_name(ahd), devinfo->channel, 3923 devinfo->target, devinfo->lun, 3924 8 * (0x01 << bus_width)); 3925 bus_width = 0; 3926 } 3927 } else { 3928 /* 3929 * Send our own WDTR in reply 3930 */ 3931 if (bootverbose 3932 && devinfo->role == ROLE_INITIATOR) { 3933 printf("(%s:%c:%d:%d): Target " 3934 "Initiated WDTR\n", 3935 ahd_name(ahd), devinfo->channel, 3936 devinfo->target, devinfo->lun); 3937 } 3938 ahd->msgout_index = 0; 3939 ahd->msgout_len = 0; 3940 ahd_construct_wdtr(ahd, devinfo, bus_width); 3941 ahd->msgout_index = 0; 3942 response = TRUE; 3943 sending_reply = TRUE; 3944 } 3945 ahd_set_width(ahd, devinfo, bus_width, 3946 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 3947 /*paused*/TRUE); 3948 /* After a wide message, we are async */ 3949 ahd_set_syncrate(ahd, devinfo, /*period*/0, 3950 /*offset*/0, /*ppr_options*/0, 3951 AHD_TRANS_ACTIVE, /*paused*/TRUE); 3952 if (sending_reply == FALSE && reject == FALSE) { 3953 3954 if (tinfo->goal.offset) { 3955 ahd->msgout_index = 0; 3956 ahd->msgout_len = 0; 3957 ahd_build_transfer_msg(ahd, devinfo); 3958 ahd->msgout_index = 0; 3959 response = TRUE; 3960 } 3961 } 3962 done = MSGLOOP_MSGCOMPLETE; 3963 break; 3964 } 3965 case MSG_EXT_PPR: 3966 { 3967 u_int period; 3968 u_int offset; 3969 u_int bus_width; 3970 u_int ppr_options; 3971 u_int saved_width; 3972 u_int saved_offset; 3973 u_int saved_ppr_options; 3974 3975 if (ahd->msgin_buf[1] != MSG_EXT_PPR_LEN) { 3976 reject = TRUE; 3977 break; 3978 } 3979 3980 /* 3981 * Wait until we have all args before validating 3982 * and acting on this message. 3983 * 3984 * Add one to MSG_EXT_PPR_LEN to account for 3985 * the extended message preamble. 3986 */ 3987 if (ahd->msgin_index < (MSG_EXT_PPR_LEN + 1)) 3988 break; 3989 3990 period = ahd->msgin_buf[3]; 3991 offset = ahd->msgin_buf[5]; 3992 bus_width = ahd->msgin_buf[6]; 3993 saved_width = bus_width; 3994 ppr_options = ahd->msgin_buf[7]; 3995 /* 3996 * According to the spec, a DT only 3997 * period factor with no DT option 3998 * set implies async. 3999 */ 4000 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 4001 && period <= 9) 4002 offset = 0; 4003 saved_ppr_options = ppr_options; 4004 saved_offset = offset; 4005 4006 /* 4007 * Transfer options are only available if we 4008 * are negotiating wide. 4009 */ 4010 if (bus_width == 0) 4011 ppr_options &= MSG_EXT_PPR_QAS_REQ; 4012 4013 ahd_validate_width(ahd, tinfo, &bus_width, 4014 devinfo->role); 4015 ahd_devlimited_syncrate(ahd, tinfo, &period, 4016 &ppr_options, devinfo->role); 4017 ahd_validate_offset(ahd, tinfo, period, &offset, 4018 bus_width, devinfo->role); 4019 4020 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, TRUE)) { 4021 /* 4022 * If we are unable to do any of the 4023 * requested options (we went too low), 4024 * then we'll have to reject the message. 4025 */ 4026 if (saved_width > bus_width 4027 || saved_offset != offset 4028 || saved_ppr_options != ppr_options) { 4029 reject = TRUE; 4030 period = 0; 4031 offset = 0; 4032 bus_width = 0; 4033 ppr_options = 0; 4034 } 4035 } else { 4036 if (devinfo->role != ROLE_TARGET) 4037 printf("(%s:%c:%d:%d): Target " 4038 "Initiated PPR\n", 4039 ahd_name(ahd), devinfo->channel, 4040 devinfo->target, devinfo->lun); 4041 else 4042 printf("(%s:%c:%d:%d): Initiator " 4043 "Initiated PPR\n", 4044 ahd_name(ahd), devinfo->channel, 4045 devinfo->target, devinfo->lun); 4046 ahd->msgout_index = 0; 4047 ahd->msgout_len = 0; 4048 ahd_construct_ppr(ahd, devinfo, period, offset, 4049 bus_width, ppr_options); 4050 ahd->msgout_index = 0; 4051 response = TRUE; 4052 } 4053 if (bootverbose) { 4054 printf("(%s:%c:%d:%d): Received PPR width %x, " 4055 "period %x, offset %x,options %x\n" 4056 "\tFiltered to width %x, period %x, " 4057 "offset %x, options %x\n", 4058 ahd_name(ahd), devinfo->channel, 4059 devinfo->target, devinfo->lun, 4060 saved_width, ahd->msgin_buf[3], 4061 saved_offset, saved_ppr_options, 4062 bus_width, period, offset, ppr_options); 4063 } 4064 ahd_set_width(ahd, devinfo, bus_width, 4065 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4066 /*paused*/TRUE); 4067 ahd_set_syncrate(ahd, devinfo, period, 4068 offset, ppr_options, 4069 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4070 /*paused*/TRUE); 4071 4072 done = MSGLOOP_MSGCOMPLETE; 4073 break; 4074 } 4075 default: 4076 /* Unknown extended message. Reject it. */ 4077 reject = TRUE; 4078 break; 4079 } 4080 break; 4081 } 4082 #ifdef AHD_TARGET_MODE 4083 case MSG_BUS_DEV_RESET: 4084 ahd_handle_devreset(ahd, devinfo, CAM_LUN_WILDCARD, 4085 CAM_BDR_SENT, 4086 "Bus Device Reset Received", 4087 /*verbose_level*/0); 4088 ahd_restart(ahd); 4089 done = MSGLOOP_TERMINATED; 4090 break; 4091 case MSG_ABORT_TAG: 4092 case MSG_ABORT: 4093 case MSG_CLEAR_QUEUE: 4094 { 4095 int tag; 4096 4097 /* Target mode messages */ 4098 if (devinfo->role != ROLE_TARGET) { 4099 reject = TRUE; 4100 break; 4101 } 4102 tag = SCB_LIST_NULL; 4103 if (ahd->msgin_buf[0] == MSG_ABORT_TAG) 4104 tag = ahd_inb(ahd, INITIATOR_TAG); 4105 ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, 4106 devinfo->lun, tag, ROLE_TARGET, 4107 CAM_REQ_ABORTED); 4108 4109 tstate = ahd->enabled_targets[devinfo->our_scsiid]; 4110 if (tstate != NULL) { 4111 struct ahd_tmode_lstate* lstate; 4112 4113 lstate = tstate->enabled_luns[devinfo->lun]; 4114 if (lstate != NULL) { 4115 ahd_queue_lstate_event(ahd, lstate, 4116 devinfo->our_scsiid, 4117 ahd->msgin_buf[0], 4118 /*arg*/tag); 4119 ahd_send_lstate_events(ahd, lstate); 4120 } 4121 } 4122 ahd_restart(ahd); 4123 done = MSGLOOP_TERMINATED; 4124 break; 4125 } 4126 #endif 4127 case MSG_QAS_REQUEST: 4128 #ifdef AHD_DEBUG 4129 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 4130 printf("%s: QAS request. SCSISIGI == 0x%x\n", 4131 ahd_name(ahd), ahd_inb(ahd, SCSISIGI)); 4132 #endif 4133 ahd->msg_flags |= MSG_FLAG_EXPECT_QASREJ_BUSFREE; 4134 /* FALLTHROUGH */ 4135 case MSG_TERM_IO_PROC: 4136 default: 4137 reject = TRUE; 4138 break; 4139 } 4140 4141 if (reject) { 4142 /* 4143 * Setup to reject the message. 4144 */ 4145 ahd->msgout_index = 0; 4146 ahd->msgout_len = 1; 4147 ahd->msgout_buf[0] = MSG_MESSAGE_REJECT; 4148 done = MSGLOOP_MSGCOMPLETE; 4149 response = TRUE; 4150 } 4151 4152 if (done != MSGLOOP_IN_PROG && !response) 4153 /* Clear the outgoing message buffer */ 4154 ahd->msgout_len = 0; 4155 4156 return (done); 4157 } 4158 4159 /* 4160 * Process a message reject message. 4161 */ 4162 static int 4163 ahd_handle_msg_reject(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4164 { 4165 /* 4166 * What we care about here is if we had an 4167 * outstanding SDTR or WDTR message for this 4168 * target. If we did, this is a signal that 4169 * the target is refusing negotiation. 4170 */ 4171 struct scb *scb; 4172 struct ahd_initiator_tinfo *tinfo; 4173 struct ahd_tmode_tstate *tstate; 4174 u_int scb_index; 4175 u_int last_msg; 4176 int response = 0; 4177 4178 scb_index = ahd_get_scbptr(ahd); 4179 scb = ahd_lookup_scb(ahd, scb_index); 4180 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, 4181 devinfo->our_scsiid, 4182 devinfo->target, &tstate); 4183 /* Might be necessary */ 4184 last_msg = ahd_inb(ahd, LAST_MSG); 4185 4186 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 4187 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/TRUE) 4188 && tinfo->goal.period <= AHD_SYNCRATE_PACED) { 4189 /* 4190 * Target may not like our SPI-4 PPR Options. 4191 * Attempt to negotiate 80MHz which will turn 4192 * off these options. 4193 */ 4194 if (bootverbose) { 4195 printf("(%s:%c:%d:%d): PPR Rejected. " 4196 "Trying simple U160 PPR\n", 4197 ahd_name(ahd), devinfo->channel, 4198 devinfo->target, devinfo->lun); 4199 } 4200 tinfo->goal.period = AHD_SYNCRATE_DT; 4201 tinfo->goal.ppr_options &= MSG_EXT_PPR_IU_REQ 4202 | MSG_EXT_PPR_QAS_REQ 4203 | MSG_EXT_PPR_DT_REQ; 4204 } else { 4205 /* 4206 * Target does not support the PPR message. 4207 * Attempt to negotiate SPI-2 style. 4208 */ 4209 if (bootverbose) { 4210 printf("(%s:%c:%d:%d): PPR Rejected. " 4211 "Trying WDTR/SDTR\n", 4212 ahd_name(ahd), devinfo->channel, 4213 devinfo->target, devinfo->lun); 4214 } 4215 tinfo->goal.ppr_options = 0; 4216 tinfo->curr.transport_version = 2; 4217 tinfo->goal.transport_version = 2; 4218 } 4219 ahd->msgout_index = 0; 4220 ahd->msgout_len = 0; 4221 ahd_build_transfer_msg(ahd, devinfo); 4222 ahd->msgout_index = 0; 4223 response = 1; 4224 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 4225 4226 /* note 8bit xfers */ 4227 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 4228 "8bit transfers\n", ahd_name(ahd), 4229 devinfo->channel, devinfo->target, devinfo->lun); 4230 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 4231 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4232 /*paused*/TRUE); 4233 /* 4234 * No need to clear the sync rate. If the target 4235 * did not accept the command, our syncrate is 4236 * unaffected. If the target started the negotiation, 4237 * but rejected our response, we already cleared the 4238 * sync rate before sending our WDTR. 4239 */ 4240 if (tinfo->goal.offset != tinfo->curr.offset) { 4241 4242 /* Start the sync negotiation */ 4243 ahd->msgout_index = 0; 4244 ahd->msgout_len = 0; 4245 ahd_build_transfer_msg(ahd, devinfo); 4246 ahd->msgout_index = 0; 4247 response = 1; 4248 } 4249 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 4250 /* note asynch xfers and clear flag */ 4251 ahd_set_syncrate(ahd, devinfo, /*period*/0, 4252 /*offset*/0, /*ppr_options*/0, 4253 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4254 /*paused*/TRUE); 4255 printf("(%s:%c:%d:%d): refuses synchronous negotiation. " 4256 "Using asynchronous transfers\n", 4257 ahd_name(ahd), devinfo->channel, 4258 devinfo->target, devinfo->lun); 4259 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 4260 int tag_type; 4261 int mask; 4262 4263 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 4264 4265 if (tag_type == MSG_SIMPLE_TASK) { 4266 printf("(%s:%c:%d:%d): refuses tagged commands. " 4267 "Performing non-tagged I/O\n", ahd_name(ahd), 4268 devinfo->channel, devinfo->target, devinfo->lun); 4269 ahd_set_tags(ahd, devinfo, AHD_QUEUE_NONE); 4270 mask = ~0x23; 4271 } else { 4272 printf("(%s:%c:%d:%d): refuses %s tagged commands. " 4273 "Performing simple queue tagged I/O only\n", 4274 ahd_name(ahd), devinfo->channel, devinfo->target, 4275 devinfo->lun, tag_type == MSG_ORDERED_TASK 4276 ? "ordered" : "head of queue"); 4277 ahd_set_tags(ahd, devinfo, AHD_QUEUE_BASIC); 4278 mask = ~0x03; 4279 } 4280 4281 /* 4282 * Resend the identify for this CCB as the target 4283 * may believe that the selection is invalid otherwise. 4284 */ 4285 ahd_outb(ahd, SCB_CONTROL, 4286 ahd_inb_scbram(ahd, SCB_CONTROL) & mask); 4287 scb->hscb->control &= mask; 4288 ahd_set_transaction_tag(scb, /*enabled*/FALSE, 4289 /*type*/MSG_SIMPLE_TASK); 4290 ahd_outb(ahd, MSG_OUT, MSG_IDENTIFYFLAG); 4291 ahd_assert_atn(ahd); 4292 ahd_busy_tcl(ahd, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 4293 SCB_GET_TAG(scb)); 4294 4295 /* 4296 * Requeue all tagged commands for this target 4297 * currently in our posession so they can be 4298 * converted to untagged commands. 4299 */ 4300 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 4301 SCB_GET_CHANNEL(ahd, scb), 4302 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 4303 ROLE_INITIATOR, CAM_REQUEUE_REQ, 4304 SEARCH_COMPLETE); 4305 } else if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_IDENTIFYFLAG, TRUE)) { 4306 /* 4307 * Most likely the device believes that we had 4308 * previously negotiated packetized. 4309 */ 4310 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE 4311 | MSG_FLAG_IU_REQ_CHANGED; 4312 4313 ahd_force_renegotiation(ahd, devinfo); 4314 ahd->msgout_index = 0; 4315 ahd->msgout_len = 0; 4316 ahd_build_transfer_msg(ahd, devinfo); 4317 ahd->msgout_index = 0; 4318 response = 1; 4319 } else { 4320 /* 4321 * Otherwise, we ignore it. 4322 */ 4323 printf("%s:%c:%d: Message reject for %x -- ignored\n", 4324 ahd_name(ahd), devinfo->channel, devinfo->target, 4325 last_msg); 4326 } 4327 return (response); 4328 } 4329 4330 /* 4331 * Process an ingnore wide residue message. 4332 */ 4333 static void 4334 ahd_handle_ign_wide_residue(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4335 { 4336 u_int scb_index; 4337 struct scb *scb; 4338 4339 scb_index = ahd_get_scbptr(ahd); 4340 scb = ahd_lookup_scb(ahd, scb_index); 4341 /* 4342 * XXX Actually check data direction in the sequencer? 4343 * Perhaps add datadir to some spare bits in the hscb? 4344 */ 4345 if ((ahd_inb(ahd, SEQ_FLAGS) & DPHASE) == 0 4346 || ahd_get_transfer_dir(scb) != CAM_DIR_IN) { 4347 /* 4348 * Ignore the message if we haven't 4349 * seen an appropriate data phase yet. 4350 */ 4351 } else { 4352 /* 4353 * If the residual occurred on the last 4354 * transfer and the transfer request was 4355 * expected to end on an odd count, do 4356 * nothing. Otherwise, subtract a byte 4357 * and update the residual count accordingly. 4358 */ 4359 uint32_t sgptr; 4360 4361 sgptr = ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR); 4362 if ((sgptr & SG_LIST_NULL) != 0 4363 && ahd_inb(ahd, DATA_COUNT_ODD) == 1) { 4364 /* 4365 * If the residual occurred on the last 4366 * transfer and the transfer request was 4367 * expected to end on an odd count, do 4368 * nothing. 4369 */ 4370 } else { 4371 uint32_t data_cnt; 4372 uint64_t data_addr; 4373 uint32_t sglen; 4374 4375 /* Pull in the rest of the sgptr */ 4376 sgptr |= 4377 (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 3) << 24) 4378 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 2) << 16) 4379 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 1) << 8); 4380 sgptr &= SG_PTR_MASK; 4381 data_cnt = 4382 (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+3) << 24) 4383 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+2) << 16) 4384 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+1) << 8) 4385 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT)); 4386 4387 data_addr = (((uint64_t)ahd_inb(ahd, SHADDR + 7)) << 56) 4388 | (((uint64_t)ahd_inb(ahd, SHADDR + 6)) << 48) 4389 | (((uint64_t)ahd_inb(ahd, SHADDR + 5)) << 40) 4390 | (((uint64_t)ahd_inb(ahd, SHADDR + 4)) << 32) 4391 | (ahd_inb(ahd, SHADDR + 3) << 24) 4392 | (ahd_inb(ahd, SHADDR + 2) << 16) 4393 | (ahd_inb(ahd, SHADDR + 1) << 8) 4394 | (ahd_inb(ahd, SHADDR)); 4395 4396 data_cnt += 1; 4397 data_addr -= 1; 4398 4399 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 4400 struct ahd_dma64_seg *sg; 4401 4402 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4403 4404 /* 4405 * The residual sg ptr points to the next S/G 4406 * to load so we must go back one. 4407 */ 4408 sg--; 4409 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 4410 if (sg != scb->sg_list 4411 && sglen < (data_cnt & AHD_SG_LEN_MASK)) { 4412 4413 sg--; 4414 sglen = ahd_le32toh(sg->len); 4415 /* 4416 * Preserve High Address and SG_LIST 4417 * bits while setting the count to 1. 4418 */ 4419 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); 4420 data_addr = ahd_le64toh(sg->addr) 4421 + (sglen & AHD_SG_LEN_MASK) 4422 - 1; 4423 4424 /* 4425 * Increment sg so it points to the 4426 * "next" sg. 4427 */ 4428 sg++; 4429 sgptr = ahd_sg_virt_to_bus(ahd, scb, 4430 sg); 4431 } 4432 } else { 4433 struct ahd_dma_seg *sg; 4434 4435 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4436 4437 /* 4438 * The residual sg ptr points to the next S/G 4439 * to load so we must go back one. 4440 */ 4441 sg--; 4442 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 4443 if (sg != scb->sg_list 4444 && sglen < (data_cnt & AHD_SG_LEN_MASK)) { 4445 4446 sg--; 4447 sglen = ahd_le32toh(sg->len); 4448 /* 4449 * Preserve High Address and SG_LIST 4450 * bits while setting the count to 1. 4451 */ 4452 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); 4453 data_addr = ahd_le32toh(sg->addr) 4454 + (sglen & AHD_SG_LEN_MASK) 4455 - 1; 4456 4457 /* 4458 * Increment sg so it points to the 4459 * "next" sg. 4460 */ 4461 sg++; 4462 sgptr = ahd_sg_virt_to_bus(ahd, scb, 4463 sg); 4464 } 4465 } 4466 ahd_outb(ahd, SCB_RESIDUAL_SGPTR + 3, sgptr >> 24); 4467 ahd_outb(ahd, SCB_RESIDUAL_SGPTR + 2, sgptr >> 16); 4468 ahd_outb(ahd, SCB_RESIDUAL_SGPTR + 1, sgptr >> 8); 4469 ahd_outb(ahd, SCB_RESIDUAL_SGPTR, sgptr); 4470 4471 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 3, data_cnt >> 24); 4472 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 2, data_cnt >> 16); 4473 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 1, data_cnt >> 8); 4474 ahd_outb(ahd, SCB_RESIDUAL_DATACNT, data_cnt); 4475 4476 /* 4477 * The FIFO's pointers will be updated if/when the 4478 * sequencer re-enters a data phase. 4479 */ 4480 } 4481 } 4482 } 4483 4484 4485 /* 4486 * Reinitialize the data pointers for the active transfer 4487 * based on its current residual. 4488 */ 4489 static void 4490 ahd_reinitialize_dataptrs(struct ahd_softc *ahd) 4491 { 4492 struct scb *scb; 4493 ahd_mode_state saved_modes; 4494 u_int scb_index; 4495 u_int wait; 4496 uint32_t sgptr; 4497 uint32_t resid; 4498 uint64_t dataptr; 4499 4500 AHD_ASSERT_MODES(ahd, AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK, 4501 AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK); 4502 4503 scb_index = ahd_get_scbptr(ahd); 4504 scb = ahd_lookup_scb(ahd, scb_index); 4505 4506 /* 4507 * Release and reacquire the FIFO so we 4508 * have a clean slate. 4509 */ 4510 ahd_outb(ahd, DFFSXFRCTL, CLRCHN); 4511 wait = 1000; 4512 do { 4513 ahd_delay(100); 4514 } while (--wait && !(ahd_inb(ahd, MDFFSTAT) & FIFOFREE)); 4515 if (wait == 0) { 4516 ahd_print_path(ahd, scb); 4517 printf("ahd_reinitialize_dataptrs: Forcing FIFO free.\n"); 4518 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); 4519 } 4520 saved_modes = ahd_save_modes(ahd); 4521 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 4522 ahd_outb(ahd, DFFSTAT, 4523 ahd_inb(ahd, DFFSTAT) 4524 | (saved_modes == 0x11 ? CURRFIFO_1 : CURRFIFO_0)); 4525 4526 /* 4527 * Determine initial values for data_addr and data_cnt 4528 * for resuming the data phase. 4529 */ 4530 sgptr = (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 3) << 24) 4531 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 2) << 16) 4532 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 1) << 8) 4533 | ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR); 4534 sgptr &= SG_PTR_MASK; 4535 4536 resid = (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 2) << 16) 4537 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 1) << 8) 4538 | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT); 4539 4540 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 4541 struct ahd_dma64_seg *sg; 4542 4543 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4544 4545 /* The residual sg_ptr always points to the next sg */ 4546 sg--; 4547 4548 dataptr = ahd_le64toh(sg->addr) 4549 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK) 4550 - resid; 4551 ahd_outb(ahd, HADDR + 7, dataptr >> 56); 4552 ahd_outb(ahd, HADDR + 6, dataptr >> 48); 4553 ahd_outb(ahd, HADDR + 5, dataptr >> 40); 4554 ahd_outb(ahd, HADDR + 4, dataptr >> 32); 4555 } else { 4556 struct ahd_dma_seg *sg; 4557 4558 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4559 4560 /* The residual sg_ptr always points to the next sg */ 4561 sg--; 4562 4563 dataptr = ahd_le32toh(sg->addr) 4564 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK) 4565 - resid; 4566 ahd_outb(ahd, HADDR + 4, 4567 (ahd_le32toh(sg->len) & ~AHD_SG_LEN_MASK) >> 24); 4568 } 4569 ahd_outb(ahd, HADDR + 3, dataptr >> 24); 4570 ahd_outb(ahd, HADDR + 2, dataptr >> 16); 4571 ahd_outb(ahd, HADDR + 1, dataptr >> 8); 4572 ahd_outb(ahd, HADDR, dataptr); 4573 ahd_outb(ahd, HCNT + 2, resid >> 16); 4574 ahd_outb(ahd, HCNT + 1, resid >> 8); 4575 ahd_outb(ahd, HCNT, resid); 4576 } 4577 4578 /* 4579 * Handle the effects of issuing a bus device reset message. 4580 */ 4581 static void 4582 ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 4583 u_int lun, cam_status status, char *message, 4584 int verbose_level) 4585 { 4586 #ifdef AHD_TARGET_MODE 4587 struct ahd_tmode_tstate* tstate; 4588 #endif 4589 int found; 4590 4591 found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, 4592 lun, SCB_LIST_NULL, devinfo->role, 4593 status); 4594 4595 #ifdef AHD_TARGET_MODE 4596 /* 4597 * Send an immediate notify ccb to all target mord peripheral 4598 * drivers affected by this action. 4599 */ 4600 tstate = ahd->enabled_targets[devinfo->our_scsiid]; 4601 if (tstate != NULL) { 4602 u_int cur_lun; 4603 u_int max_lun; 4604 4605 if (lun != CAM_LUN_WILDCARD) { 4606 cur_lun = 0; 4607 max_lun = AHD_NUM_LUNS - 1; 4608 } else { 4609 cur_lun = lun; 4610 max_lun = lun; 4611 } 4612 for (cur_lun <= max_lun; cur_lun++) { 4613 struct ahd_tmode_lstate* lstate; 4614 4615 lstate = tstate->enabled_luns[cur_lun]; 4616 if (lstate == NULL) 4617 continue; 4618 4619 ahd_queue_lstate_event(ahd, lstate, devinfo->our_scsiid, 4620 MSG_BUS_DEV_RESET, /*arg*/0); 4621 ahd_send_lstate_events(ahd, lstate); 4622 } 4623 } 4624 #endif 4625 4626 /* 4627 * Go back to async/narrow transfers and renegotiate. 4628 */ 4629 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 4630 AHD_TRANS_CUR, /*paused*/TRUE); 4631 ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0, 4632 /*ppr_options*/0, AHD_TRANS_CUR, /*paused*/TRUE); 4633 4634 ahd_send_async(ahd, devinfo->channel, devinfo->target, 4635 lun, AC_SENT_BDR, NULL); 4636 4637 if (message != NULL 4638 && (verbose_level <= bootverbose)) 4639 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd), 4640 message, devinfo->channel, devinfo->target, found); 4641 } 4642 4643 #ifdef AHD_TARGET_MODE 4644 static void 4645 ahd_setup_target_msgin(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 4646 struct scb *scb) 4647 { 4648 4649 /* 4650 * To facilitate adding multiple messages together, 4651 * each routine should increment the index and len 4652 * variables instead of setting them explicitly. 4653 */ 4654 ahd->msgout_index = 0; 4655 ahd->msgout_len = 0; 4656 4657 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 4658 ahd_build_transfer_msg(ahd, devinfo); 4659 else 4660 panic("ahd_intr: AWAITING target message with no message"); 4661 4662 ahd->msgout_index = 0; 4663 ahd->msg_type = MSG_TYPE_TARGET_MSGIN; 4664 } 4665 #endif 4666 /**************************** Initialization **********************************/ 4667 static u_int 4668 ahd_sglist_size(struct ahd_softc *ahd) 4669 { 4670 bus_size_t list_size; 4671 4672 list_size = sizeof(struct ahd_dma_seg) * AHD_NSEG; 4673 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 4674 list_size = sizeof(struct ahd_dma64_seg) * AHD_NSEG; 4675 return (list_size); 4676 } 4677 4678 /* 4679 * Calculate the optimum S/G List allocation size. S/G elements used 4680 * for a given transaction must be physically contiguous. Assume the 4681 * OS will allocate full pages to us, so it doesn't make sense to request 4682 * less than a page. 4683 */ 4684 static u_int 4685 ahd_sglist_allocsize(struct ahd_softc *ahd) 4686 { 4687 bus_size_t sg_list_increment; 4688 bus_size_t sg_list_size; 4689 bus_size_t max_list_size; 4690 bus_size_t best_list_size; 4691 4692 /* Start out with the minimum required for AHD_NSEG. */ 4693 sg_list_increment = ahd_sglist_size(ahd); 4694 sg_list_size = sg_list_increment; 4695 4696 /* Get us as close as possible to a page in size. */ 4697 while ((sg_list_size + sg_list_increment) <= PAGE_SIZE) 4698 sg_list_size += sg_list_increment; 4699 4700 /* 4701 * Try to reduce the amount of wastage by allocating 4702 * multiple pages. 4703 */ 4704 best_list_size = sg_list_size; 4705 max_list_size = roundup(sg_list_increment, PAGE_SIZE); 4706 if (max_list_size < 4 * PAGE_SIZE) 4707 max_list_size = 4 * PAGE_SIZE; 4708 if (max_list_size > (AHD_SCB_MAX_ALLOC * sg_list_increment)) 4709 max_list_size = (AHD_SCB_MAX_ALLOC * sg_list_increment); 4710 while ((sg_list_size + sg_list_increment) <= max_list_size 4711 && (sg_list_size % PAGE_SIZE) != 0) { 4712 bus_size_t new_mod; 4713 bus_size_t best_mod; 4714 4715 sg_list_size += sg_list_increment; 4716 new_mod = sg_list_size % PAGE_SIZE; 4717 best_mod = best_list_size % PAGE_SIZE; 4718 if (new_mod > best_mod || new_mod == 0) { 4719 best_list_size = sg_list_size; 4720 } 4721 } 4722 return (best_list_size); 4723 } 4724 4725 /* 4726 * Allocate a controller structure for a new device 4727 * and perform initial initializion. 4728 */ 4729 struct ahd_softc * 4730 ahd_alloc(void *platform_arg, char *name) 4731 { 4732 struct ahd_softc *ahd; 4733 4734 #ifndef __FreeBSD__ 4735 ahd = malloc(sizeof(*ahd), M_DEVBUF, M_NOWAIT); 4736 if (!ahd) { 4737 printf("aic7xxx: cannot malloc softc!\n"); 4738 free(name, M_DEVBUF); 4739 return NULL; 4740 } 4741 #else 4742 ahd = device_get_softc((device_t)platform_arg); 4743 #endif 4744 memset(ahd, 0, sizeof(*ahd)); 4745 ahd->seep_config = malloc(sizeof(*ahd->seep_config), 4746 M_DEVBUF, M_NOWAIT); 4747 if (ahd->seep_config == NULL) { 4748 #ifndef __FreeBSD__ 4749 free(ahd, M_DEVBUF); 4750 #endif 4751 free(name, M_DEVBUF); 4752 return (NULL); 4753 } 4754 LIST_INIT(&ahd->pending_scbs); 4755 /* We don't know our unit number until the OSM sets it */ 4756 ahd->name = name; 4757 ahd->unit = -1; 4758 ahd->description = NULL; 4759 ahd->bus_description = NULL; 4760 ahd->channel = 'A'; 4761 ahd->chip = AHD_NONE; 4762 ahd->features = AHD_FENONE; 4763 ahd->bugs = AHD_BUGNONE; 4764 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A 4765 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A; 4766 ahd_timer_init(&ahd->reset_timer); 4767 ahd_timer_init(&ahd->stat_timer); 4768 ahd->int_coalessing_timer = AHD_INT_COALESSING_TIMER_DEFAULT; 4769 ahd->int_coalessing_maxcmds = AHD_INT_COALESSING_MAXCMDS_DEFAULT; 4770 ahd->int_coalessing_mincmds = AHD_INT_COALESSING_MINCMDS_DEFAULT; 4771 ahd->int_coalessing_threshold = AHD_INT_COALESSING_THRESHOLD_DEFAULT; 4772 ahd->int_coalessing_stop_threshold = 4773 AHD_INT_COALESSING_STOP_THRESHOLD_DEFAULT; 4774 4775 if (ahd_platform_alloc(ahd, platform_arg) != 0) { 4776 ahd_free(ahd); 4777 ahd = NULL; 4778 } 4779 #ifdef AHD_DEBUG 4780 if ((ahd_debug & AHD_SHOW_MEMORY) != 0) { 4781 printf("%s: scb size = 0x%x, hscb size = 0x%x\n", 4782 ahd_name(ahd), (u_int)sizeof(struct scb), 4783 (u_int)sizeof(struct hardware_scb)); 4784 } 4785 #endif 4786 return (ahd); 4787 } 4788 4789 int 4790 ahd_softc_init(struct ahd_softc *ahd) 4791 { 4792 4793 ahd->unpause = 0; 4794 ahd->pause = PAUSE; 4795 return (0); 4796 } 4797 4798 void 4799 ahd_softc_insert(struct ahd_softc *ahd) 4800 { 4801 struct ahd_softc *list_ahd; 4802 4803 #if AHD_PCI_CONFIG > 0 4804 /* 4805 * Second Function PCI devices need to inherit some 4806 * settings from function 0. 4807 */ 4808 if ((ahd->features & AHD_MULTI_FUNC) != 0) { 4809 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) { 4810 ahd_dev_softc_t list_pci; 4811 ahd_dev_softc_t pci; 4812 4813 list_pci = list_ahd->dev_softc; 4814 pci = ahd->dev_softc; 4815 if (ahd_get_pci_slot(list_pci) == ahd_get_pci_slot(pci) 4816 && ahd_get_pci_bus(list_pci) == ahd_get_pci_bus(pci)) { 4817 struct ahd_softc *master; 4818 struct ahd_softc *slave; 4819 4820 if (ahd_get_pci_function(list_pci) == 0) { 4821 master = list_ahd; 4822 slave = ahd; 4823 } else { 4824 master = ahd; 4825 slave = list_ahd; 4826 } 4827 slave->flags &= ~AHD_BIOS_ENABLED; 4828 slave->flags |= 4829 master->flags & AHD_BIOS_ENABLED; 4830 slave->flags &= ~AHD_PRIMARY_CHANNEL; 4831 slave->flags |= 4832 master->flags & AHD_PRIMARY_CHANNEL; 4833 break; 4834 } 4835 } 4836 } 4837 #endif 4838 4839 /* 4840 * Insertion sort into our list of softcs. 4841 */ 4842 list_ahd = TAILQ_FIRST(&ahd_tailq); 4843 while (list_ahd != NULL 4844 && ahd_softc_comp(list_ahd, ahd) <= 0) 4845 list_ahd = TAILQ_NEXT(list_ahd, links); 4846 if (list_ahd != NULL) 4847 TAILQ_INSERT_BEFORE(list_ahd, ahd, links); 4848 else 4849 TAILQ_INSERT_TAIL(&ahd_tailq, ahd, links); 4850 ahd->init_level++; 4851 } 4852 4853 /* 4854 * Verify that the passed in softc pointer is for a 4855 * controller that is still configured. 4856 */ 4857 struct ahd_softc * 4858 ahd_find_softc(struct ahd_softc *ahd) 4859 { 4860 struct ahd_softc *list_ahd; 4861 4862 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) { 4863 if (list_ahd == ahd) 4864 return (ahd); 4865 } 4866 return (NULL); 4867 } 4868 4869 void 4870 ahd_set_unit(struct ahd_softc *ahd, int unit) 4871 { 4872 ahd->unit = unit; 4873 } 4874 4875 void 4876 ahd_set_name(struct ahd_softc *ahd, char *name) 4877 { 4878 if (ahd->name != NULL) 4879 free(ahd->name, M_DEVBUF); 4880 ahd->name = name; 4881 } 4882 4883 void 4884 ahd_free(struct ahd_softc *ahd) 4885 { 4886 int i; 4887 4888 ahd_fini_scbdata(ahd); 4889 switch (ahd->init_level) { 4890 default: 4891 case 5: 4892 ahd_shutdown(ahd); 4893 TAILQ_REMOVE(&ahd_tailq, ahd, links); 4894 /* FALLTHROUGH */ 4895 case 4: 4896 ahd_dmamap_unload(ahd, ahd->shared_data_dmat, 4897 ahd->shared_data_dmamap); 4898 /* FALLTHROUGH */ 4899 case 3: 4900 ahd_dmamem_free(ahd, ahd->shared_data_dmat, ahd->qoutfifo, 4901 ahd->shared_data_dmamap); 4902 ahd_dmamap_destroy(ahd, ahd->shared_data_dmat, 4903 ahd->shared_data_dmamap); 4904 /* FALLTHROUGH */ 4905 case 2: 4906 ahd_dma_tag_destroy(ahd, ahd->shared_data_dmat); 4907 case 1: 4908 #ifndef __linux__ 4909 ahd_dma_tag_destroy(ahd, ahd->buffer_dmat); 4910 #endif 4911 break; 4912 case 0: 4913 break; 4914 } 4915 4916 #ifndef __linux__ 4917 ahd_dma_tag_destroy(ahd, ahd->parent_dmat); 4918 #endif 4919 ahd_platform_free(ahd); 4920 for (i = 0; i < AHD_NUM_TARGETS; i++) { 4921 struct ahd_tmode_tstate *tstate; 4922 4923 tstate = ahd->enabled_targets[i]; 4924 if (tstate != NULL) { 4925 #if AHD_TARGET_MODE 4926 int j; 4927 4928 for (j = 0; j < AHD_NUM_LUNS; j++) { 4929 struct ahd_tmode_lstate *lstate; 4930 4931 lstate = tstate->enabled_luns[j]; 4932 if (lstate != NULL) { 4933 xpt_free_path(lstate->path); 4934 free(lstate, M_DEVBUF); 4935 } 4936 } 4937 #endif 4938 free(tstate, M_DEVBUF); 4939 } 4940 } 4941 #if AHD_TARGET_MODE 4942 if (ahd->black_hole != NULL) { 4943 xpt_free_path(ahd->black_hole->path); 4944 free(ahd->black_hole, M_DEVBUF); 4945 } 4946 #endif 4947 if (ahd->name != NULL) 4948 free(ahd->name, M_DEVBUF); 4949 if (ahd->seep_config != NULL) 4950 free(ahd->seep_config, M_DEVBUF); 4951 if (ahd->saved_stack != NULL) 4952 free(ahd->saved_stack, M_DEVBUF); 4953 #ifndef __FreeBSD__ 4954 free(ahd, M_DEVBUF); 4955 #endif 4956 return; 4957 } 4958 4959 void 4960 ahd_shutdown(void *arg) 4961 { 4962 struct ahd_softc *ahd; 4963 4964 ahd = (struct ahd_softc *)arg; 4965 4966 /* 4967 * Stop periodic timer callbacks. 4968 */ 4969 ahd_timer_stop(&ahd->reset_timer); 4970 ahd_timer_stop(&ahd->stat_timer); 4971 4972 /* This will reset most registers to 0, but not all */ 4973 ahd_reset(ahd); 4974 } 4975 4976 /* 4977 * Reset the controller and record some information about it 4978 * that is only available just after a reset. 4979 */ 4980 int 4981 ahd_reset(struct ahd_softc *ahd) 4982 { 4983 u_int sxfrctl1; 4984 int wait; 4985 uint32_t cmd; 4986 4987 /* 4988 * Preserve the value of the SXFRCTL1 register for all channels. 4989 * It contains settings that affect termination and we don't want 4990 * to disturb the integrity of the bus. 4991 */ 4992 ahd_pause(ahd); 4993 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 4994 sxfrctl1 = ahd_inb(ahd, SXFRCTL1); 4995 4996 cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 4997 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { 4998 uint32_t mod_cmd; 4999 5000 /* 5001 * A4 Razor #632 5002 * During the assertion of CHIPRST, the chip 5003 * does not disable its parity logic prior to 5004 * the start of the reset. This may cause a 5005 * parity error to be detected and thus a 5006 * spurious SERR or PERR assertion. Disble 5007 * PERR and SERR responses during the CHIPRST. 5008 */ 5009 mod_cmd = cmd & ~(PCIM_CMD_PERRESPEN|PCIM_CMD_SERRESPEN); 5010 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 5011 mod_cmd, /*bytes*/2); 5012 } 5013 ahd_outb(ahd, HCNTRL, CHIPRST | ahd->pause); 5014 5015 /* 5016 * Ensure that the reset has finished. We delay 1000us 5017 * prior to reading the register to make sure the chip 5018 * has sufficiently completed its reset to handle register 5019 * accesses. 5020 */ 5021 wait = 1000; 5022 do { 5023 ahd_delay(1000); 5024 } while (--wait && !(ahd_inb(ahd, HCNTRL) & CHIPRSTACK)); 5025 5026 if (wait == 0) { 5027 printf("%s: WARNING - Failed chip reset! " 5028 "Trying to initialize anyway.\n", ahd_name(ahd)); 5029 } 5030 ahd_outb(ahd, HCNTRL, ahd->pause); 5031 5032 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { 5033 /* 5034 * Clear any latched PCI error status and restore 5035 * previous SERR and PERR response enables. 5036 */ 5037 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 5038 0xFF, /*bytes*/1); 5039 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 5040 cmd, /*bytes*/2); 5041 } 5042 5043 /* 5044 * Mode should be SCSI after a chip reset, but lets 5045 * set it just to be safe. 5046 */ 5047 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5048 ahd_known_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5049 5050 /* 5051 * Restore SXFRCTL1. 5052 * 5053 * We must always initialize STPWEN to 1 before we 5054 * restore the saved values. STPWEN is initialized 5055 * to a tri-state condition which can only be cleared 5056 * by turning it on. 5057 */ 5058 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 5059 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 5060 5061 /* Determine chip configuration */ 5062 ahd->features &= ~AHD_WIDE; 5063 if ((ahd_inb(ahd, SBLKCTL) & SELWIDE) != 0) 5064 ahd->features |= AHD_WIDE; 5065 5066 /* 5067 * If a recovery action has forced a chip reset, 5068 * re-initialize the chip to our liking. 5069 */ 5070 if (ahd->init_level > 0) 5071 ahd_chip_init(ahd); 5072 5073 return (0); 5074 } 5075 5076 /* 5077 * Determine the number of SCBs available on the controller 5078 */ 5079 int 5080 ahd_probe_scbs(struct ahd_softc *ahd) { 5081 int i; 5082 5083 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 5084 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 5085 for (i = 0; i < AHD_SCB_MAX; i++) { 5086 int j; 5087 5088 ahd_set_scbptr(ahd, i); 5089 ahd_outw(ahd, SCB_BASE, i); 5090 for (j = 2; j < 64; j++) 5091 ahd_outb(ahd, SCB_BASE+j, 0); 5092 /* Start out life as unallocated (needing an abort) */ 5093 ahd_outb(ahd, SCB_CONTROL, MK_MESSAGE); 5094 if (ahd_inw_scbram(ahd, SCB_BASE) != i) 5095 break; 5096 ahd_set_scbptr(ahd, 0); 5097 if (ahd_inw_scbram(ahd, SCB_BASE) != 0) 5098 break; 5099 } 5100 return (i); 5101 } 5102 5103 static void 5104 ahd_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 5105 { 5106 bus_addr_t *baddr; 5107 5108 baddr = (bus_addr_t *)arg; 5109 *baddr = segs->ds_addr; 5110 } 5111 5112 static void 5113 ahd_initialize_hscbs(struct ahd_softc *ahd) 5114 { 5115 int i; 5116 5117 for (i = 0; i < ahd->scb_data.maxhscbs; i++) { 5118 ahd_set_scbptr(ahd, i); 5119 5120 /* Clear the control byte. */ 5121 ahd_outb(ahd, SCB_CONTROL, 0); 5122 5123 /* Set the next pointer */ 5124 ahd_outw(ahd, SCB_NEXT, SCB_LIST_NULL); 5125 } 5126 } 5127 5128 static int 5129 ahd_init_scbdata(struct ahd_softc *ahd) 5130 { 5131 struct scb_data *scb_data; 5132 int i; 5133 5134 scb_data = &ahd->scb_data; 5135 TAILQ_INIT(&scb_data->free_scbs); 5136 for (i = 0; i < AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT; i++) 5137 LIST_INIT(&scb_data->free_scb_lists[i]); 5138 LIST_INIT(&scb_data->any_dev_free_scb_list); 5139 SLIST_INIT(&scb_data->hscb_maps); 5140 SLIST_INIT(&scb_data->sg_maps); 5141 SLIST_INIT(&scb_data->sense_maps); 5142 5143 /* Determine the number of hardware SCBs and initialize them */ 5144 scb_data->maxhscbs = ahd_probe_scbs(ahd); 5145 if (scb_data->maxhscbs == 0) { 5146 printf("%s: No SCB space found\n", ahd_name(ahd)); 5147 return (ENXIO); 5148 } 5149 5150 ahd_initialize_hscbs(ahd); 5151 5152 /* 5153 * Create our DMA tags. These tags define the kinds of device 5154 * accessible memory allocations and memory mappings we will 5155 * need to perform during normal operation. 5156 * 5157 * Unless we need to further restrict the allocation, we rely 5158 * on the restrictions of the parent dmat, hence the common 5159 * use of MAXADDR and MAXSIZE. 5160 */ 5161 5162 /* DMA tag for our hardware scb structures */ 5163 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1, 5164 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 5165 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 5166 /*highaddr*/BUS_SPACE_MAXADDR, 5167 /*filter*/NULL, /*filterarg*/NULL, 5168 PAGE_SIZE, /*nsegments*/1, 5169 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 5170 /*flags*/0, &scb_data->hscb_dmat) != 0) { 5171 goto error_exit; 5172 } 5173 5174 scb_data->init_level++; 5175 5176 /* DMA tag for our S/G structures. */ 5177 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/8, 5178 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 5179 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 5180 /*highaddr*/BUS_SPACE_MAXADDR, 5181 /*filter*/NULL, /*filterarg*/NULL, 5182 ahd_sglist_allocsize(ahd), /*nsegments*/1, 5183 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 5184 /*flags*/0, &scb_data->sg_dmat) != 0) { 5185 goto error_exit; 5186 } 5187 #ifdef AHD_DEBUG 5188 if ((ahd_debug & AHD_SHOW_MEMORY) != 0) 5189 printf("%s: ahd_sglist_allocsize = 0x%x\n", ahd_name(ahd), 5190 ahd_sglist_allocsize(ahd)); 5191 #endif 5192 5193 scb_data->init_level++; 5194 5195 /* DMA tag for our sense buffers. We allocate in page sized chunks */ 5196 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1, 5197 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 5198 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 5199 /*highaddr*/BUS_SPACE_MAXADDR, 5200 /*filter*/NULL, /*filterarg*/NULL, 5201 PAGE_SIZE, /*nsegments*/1, 5202 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 5203 /*flags*/0, &scb_data->sense_dmat) != 0) { 5204 goto error_exit; 5205 } 5206 5207 scb_data->init_level++; 5208 5209 /* Perform initial CCB allocation */ 5210 ahd_alloc_scbs(ahd); 5211 5212 if (scb_data->numscbs == 0) { 5213 printf("%s: ahd_init_scbdata - " 5214 "Unable to allocate initial scbs\n", 5215 ahd_name(ahd)); 5216 goto error_exit; 5217 } 5218 5219 /* 5220 * Note that we were successfull 5221 */ 5222 return (0); 5223 5224 error_exit: 5225 5226 return (ENOMEM); 5227 } 5228 5229 static struct scb * 5230 ahd_find_scb_by_tag(struct ahd_softc *ahd, u_int tag) 5231 { 5232 struct scb *scb; 5233 5234 /* 5235 * Look on the pending list. 5236 */ 5237 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 5238 if (SCB_GET_TAG(scb) == tag) 5239 return (scb); 5240 } 5241 5242 /* 5243 * Then on all of the collision free lists. 5244 */ 5245 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 5246 struct scb *list_scb; 5247 5248 list_scb = scb; 5249 do { 5250 if (SCB_GET_TAG(list_scb) == tag) 5251 return (list_scb); 5252 list_scb = LIST_NEXT(list_scb, collision_links); 5253 } while (list_scb); 5254 } 5255 5256 /* 5257 * And finally on the generic free list. 5258 */ 5259 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { 5260 if (SCB_GET_TAG(scb) == tag) 5261 return (scb); 5262 } 5263 5264 return (NULL); 5265 } 5266 5267 static void 5268 ahd_fini_scbdata(struct ahd_softc *ahd) 5269 { 5270 struct scb_data *scb_data; 5271 5272 scb_data = &ahd->scb_data; 5273 if (scb_data == NULL) 5274 return; 5275 5276 switch (scb_data->init_level) { 5277 default: 5278 case 7: 5279 { 5280 struct map_node *sns_map; 5281 5282 while ((sns_map = SLIST_FIRST(&scb_data->sense_maps)) != NULL) { 5283 SLIST_REMOVE_HEAD(&scb_data->sense_maps, links); 5284 ahd_dmamap_unload(ahd, scb_data->sense_dmat, 5285 sns_map->dmamap); 5286 ahd_dmamem_free(ahd, scb_data->sense_dmat, 5287 sns_map->vaddr, sns_map->dmamap); 5288 free(sns_map, M_DEVBUF); 5289 } 5290 ahd_dma_tag_destroy(ahd, scb_data->sense_dmat); 5291 /* FALLTHROUGH */ 5292 } 5293 case 6: 5294 { 5295 struct map_node *sg_map; 5296 5297 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)) != NULL) { 5298 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 5299 ahd_dmamap_unload(ahd, scb_data->sg_dmat, 5300 sg_map->dmamap); 5301 ahd_dmamem_free(ahd, scb_data->sg_dmat, 5302 sg_map->vaddr, sg_map->dmamap); 5303 free(sg_map, M_DEVBUF); 5304 } 5305 ahd_dma_tag_destroy(ahd, scb_data->sg_dmat); 5306 /* FALLTHROUGH */ 5307 } 5308 case 5: 5309 { 5310 struct map_node *hscb_map; 5311 5312 while ((hscb_map = SLIST_FIRST(&scb_data->hscb_maps)) != NULL) { 5313 SLIST_REMOVE_HEAD(&scb_data->hscb_maps, links); 5314 ahd_dmamap_unload(ahd, scb_data->hscb_dmat, 5315 hscb_map->dmamap); 5316 ahd_dmamem_free(ahd, scb_data->hscb_dmat, 5317 hscb_map->vaddr, hscb_map->dmamap); 5318 free(hscb_map, M_DEVBUF); 5319 } 5320 ahd_dma_tag_destroy(ahd, scb_data->hscb_dmat); 5321 /* FALLTHROUGH */ 5322 } 5323 case 4: 5324 case 3: 5325 case 2: 5326 case 1: 5327 case 0: 5328 break; 5329 } 5330 } 5331 5332 /* 5333 * DSP filter Bypass must be enabled until the first selection 5334 * after a change in bus mode (Razor #491 and #493). 5335 */ 5336 static void 5337 ahd_setup_iocell_workaround(struct ahd_softc *ahd) 5338 { 5339 ahd_mode_state saved_modes; 5340 5341 saved_modes = ahd_save_modes(ahd); 5342 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5343 ahd_outb(ahd, DSPDATACTL, ahd_inb(ahd, DSPDATACTL) 5344 | BYPASSENAB | RCVROFFSTDIS | XMITOFFSTDIS); 5345 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) | (ENSELDO|ENSELDI)); 5346 #ifdef AHD_DEBUG 5347 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5348 printf("%s: Setting up iocell workaround\n", ahd_name(ahd)); 5349 #endif 5350 ahd_restore_modes(ahd, saved_modes); 5351 } 5352 5353 static void 5354 ahd_iocell_first_selection(struct ahd_softc *ahd) 5355 { 5356 ahd_mode_state saved_modes; 5357 u_int sblkctl; 5358 5359 saved_modes = ahd_save_modes(ahd); 5360 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5361 sblkctl = ahd_inb(ahd, SBLKCTL); 5362 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5363 #ifdef AHD_DEBUG 5364 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5365 printf("%s: iocell first selection\n", ahd_name(ahd)); 5366 #endif 5367 if ((sblkctl & ENAB40) != 0) { 5368 ahd_outb(ahd, DSPDATACTL, 5369 ahd_inb(ahd, DSPDATACTL) & ~BYPASSENAB); 5370 #ifdef AHD_DEBUG 5371 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5372 printf("%s: BYPASS now disabled\n", ahd_name(ahd)); 5373 #endif 5374 } 5375 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) & ~(ENSELDO|ENSELDI)); 5376 ahd_outb(ahd, CLRINT, CLRSCSIINT); 5377 ahd_restore_modes(ahd, saved_modes); 5378 } 5379 5380 /*************************** SCB Management ***********************************/ 5381 static void 5382 ahd_add_col_list(struct ahd_softc *ahd, struct scb *scb, u_int col_idx) 5383 { 5384 struct scb_list *free_list; 5385 struct scb_tailq *free_tailq; 5386 struct scb *first_scb; 5387 5388 scb->flags |= SCB_ON_COL_LIST; 5389 AHD_SET_SCB_COL_IDX(scb, col_idx); 5390 free_list = &ahd->scb_data.free_scb_lists[col_idx]; 5391 free_tailq = &ahd->scb_data.free_scbs; 5392 first_scb = LIST_FIRST(free_list); 5393 if (first_scb != NULL) { 5394 LIST_INSERT_AFTER(first_scb, scb, collision_links); 5395 } else { 5396 LIST_INSERT_HEAD(free_list, scb, collision_links); 5397 TAILQ_INSERT_TAIL(free_tailq, scb, links.tqe); 5398 } 5399 } 5400 5401 static void 5402 ahd_rem_col_list(struct ahd_softc *ahd, struct scb *scb) 5403 { 5404 struct scb_list *free_list; 5405 struct scb_tailq *free_tailq; 5406 struct scb *first_scb; 5407 u_int col_idx; 5408 5409 scb->flags &= ~SCB_ON_COL_LIST; 5410 col_idx = AHD_GET_SCB_COL_IDX(ahd, scb); 5411 free_list = &ahd->scb_data.free_scb_lists[col_idx]; 5412 free_tailq = &ahd->scb_data.free_scbs; 5413 first_scb = LIST_FIRST(free_list); 5414 if (first_scb == scb) { 5415 struct scb *next_scb; 5416 5417 /* 5418 * Maintain order in the collision free 5419 * lists for fairness if this device has 5420 * other colliding tags active. 5421 */ 5422 next_scb = LIST_NEXT(scb, collision_links); 5423 if (next_scb != NULL) { 5424 TAILQ_INSERT_AFTER(free_tailq, scb, 5425 next_scb, links.tqe); 5426 } 5427 TAILQ_REMOVE(free_tailq, scb, links.tqe); 5428 } 5429 LIST_REMOVE(scb, collision_links); 5430 } 5431 5432 /* 5433 * Get a free scb. If there are none, see if we can allocate a new SCB. 5434 */ 5435 struct scb * 5436 ahd_get_scb(struct ahd_softc *ahd, u_int col_idx) 5437 { 5438 struct scb *scb; 5439 int tries; 5440 5441 tries = 0; 5442 look_again: 5443 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 5444 if (AHD_GET_SCB_COL_IDX(ahd, scb) != col_idx) { 5445 ahd_rem_col_list(ahd, scb); 5446 goto found; 5447 } 5448 } 5449 if ((scb = LIST_FIRST(&ahd->scb_data.any_dev_free_scb_list)) == NULL) { 5450 5451 if (tries++ != 0) 5452 return (NULL); 5453 ahd_alloc_scbs(ahd); 5454 goto look_again; 5455 } 5456 LIST_REMOVE(scb, links.le); 5457 if (col_idx != AHD_NEVER_COL_IDX 5458 && (scb->col_scb != NULL) 5459 && (scb->col_scb->flags & SCB_ACTIVE) == 0) { 5460 LIST_REMOVE(scb->col_scb, links.le); 5461 ahd_add_col_list(ahd, scb->col_scb, col_idx); 5462 } 5463 found: 5464 scb->flags |= SCB_ACTIVE; 5465 return (scb); 5466 } 5467 5468 /* 5469 * Return an SCB resource to the free list. 5470 */ 5471 void 5472 ahd_free_scb(struct ahd_softc *ahd, struct scb *scb) 5473 { 5474 5475 /* Clean up for the next user */ 5476 scb->flags = SCB_FLAG_NONE; 5477 scb->hscb->control = 0; 5478 ahd->scb_data.scbindex[scb->hscb->tag] = NULL; 5479 5480 if (scb->col_scb == NULL) { 5481 5482 /* 5483 * No collision possible. Just free normally. 5484 */ 5485 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5486 scb, links.le); 5487 } else if ((scb->col_scb->flags & SCB_ON_COL_LIST) != 0) { 5488 5489 /* 5490 * The SCB we might have collided with is on 5491 * a free collision list. Put both SCBs on 5492 * the generic list. 5493 */ 5494 ahd_rem_col_list(ahd, scb->col_scb); 5495 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5496 scb, links.le); 5497 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5498 scb->col_scb, links.le); 5499 } else if ((scb->col_scb->flags 5500 & (SCB_PACKETIZED|SCB_ACTIVE)) == SCB_ACTIVE 5501 && (scb->col_scb->hscb->control & TAG_ENB) != 0) { 5502 5503 /* 5504 * The SCB we might collide with on the next allocation 5505 * is still active in a non-packetized, tagged, context. 5506 * Put us on the SCB collision list. 5507 */ 5508 ahd_add_col_list(ahd, scb, 5509 AHD_GET_SCB_COL_IDX(ahd, scb->col_scb)); 5510 } else { 5511 /* 5512 * The SCB we might collide with on the next allocation 5513 * is either active in a packetized context, or free. 5514 * Since we can't collide, put this SCB on the generic 5515 * free list. 5516 */ 5517 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5518 scb, links.le); 5519 } 5520 5521 ahd_platform_scb_free(ahd, scb); 5522 } 5523 5524 void 5525 ahd_alloc_scbs(struct ahd_softc *ahd) 5526 { 5527 struct scb_data *scb_data; 5528 struct scb *next_scb; 5529 struct hardware_scb *hscb; 5530 struct map_node *hscb_map; 5531 struct map_node *sg_map; 5532 struct map_node *sense_map; 5533 uint8_t *segs; 5534 uint8_t *sense_data; 5535 bus_addr_t hscb_busaddr; 5536 bus_addr_t sg_busaddr; 5537 bus_addr_t sense_busaddr; 5538 int newcount; 5539 int i; 5540 5541 scb_data = &ahd->scb_data; 5542 if (scb_data->numscbs >= AHD_SCB_MAX_ALLOC) 5543 /* Can't allocate any more */ 5544 return; 5545 5546 if (scb_data->scbs_left != 0) { 5547 int offset; 5548 5549 offset = (PAGE_SIZE / sizeof(*hscb)) - scb_data->scbs_left; 5550 hscb_map = SLIST_FIRST(&scb_data->hscb_maps); 5551 hscb = &((struct hardware_scb *)hscb_map->vaddr)[offset]; 5552 hscb_busaddr = hscb_map->physaddr + (offset * sizeof(*hscb)); 5553 } else { 5554 hscb_map = malloc(sizeof(*hscb_map), M_DEVBUF, M_NOWAIT); 5555 5556 if (hscb_map == NULL) 5557 return; 5558 5559 /* Allocate the next batch of hardware SCBs */ 5560 if (ahd_dmamem_alloc(ahd, scb_data->hscb_dmat, 5561 (void **)&hscb_map->vaddr, 5562 BUS_DMA_NOWAIT, &hscb_map->dmamap) != 0) { 5563 free(hscb_map, M_DEVBUF); 5564 return; 5565 } 5566 5567 SLIST_INSERT_HEAD(&scb_data->hscb_maps, hscb_map, links); 5568 5569 ahd_dmamap_load(ahd, scb_data->hscb_dmat, hscb_map->dmamap, 5570 hscb_map->vaddr, PAGE_SIZE, ahd_dmamap_cb, 5571 &hscb_map->physaddr, /*flags*/0); 5572 5573 hscb = (struct hardware_scb *)hscb_map->vaddr; 5574 hscb_busaddr = hscb_map->physaddr; 5575 scb_data->scbs_left = PAGE_SIZE / sizeof(*hscb); 5576 } 5577 5578 if (scb_data->sgs_left != 0) { 5579 int offset; 5580 5581 offset = ahd_sglist_allocsize(ahd) 5582 - (scb_data->sgs_left * ahd_sglist_size(ahd)); 5583 sg_map = SLIST_FIRST(&scb_data->sg_maps); 5584 segs = sg_map->vaddr + offset; 5585 sg_busaddr = sg_map->physaddr + offset; 5586 } else { 5587 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 5588 5589 if (sg_map == NULL) 5590 return; 5591 5592 /* Allocate the next batch of S/G lists */ 5593 if (ahd_dmamem_alloc(ahd, scb_data->sg_dmat, 5594 (void **)&sg_map->vaddr, 5595 BUS_DMA_NOWAIT, &sg_map->dmamap) != 0) { 5596 free(sg_map, M_DEVBUF); 5597 return; 5598 } 5599 5600 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 5601 5602 ahd_dmamap_load(ahd, scb_data->sg_dmat, sg_map->dmamap, 5603 sg_map->vaddr, ahd_sglist_allocsize(ahd), 5604 ahd_dmamap_cb, &sg_map->physaddr, /*flags*/0); 5605 5606 segs = sg_map->vaddr; 5607 sg_busaddr = sg_map->physaddr; 5608 scb_data->sgs_left = 5609 ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd); 5610 #ifdef AHD_DEBUG 5611 if (ahd_debug & AHD_SHOW_MEMORY) 5612 printf("Mapped SG data\n"); 5613 #endif 5614 } 5615 5616 if (scb_data->sense_left != 0) { 5617 int offset; 5618 5619 offset = PAGE_SIZE - (AHD_SENSE_BUFSIZE * scb_data->sense_left); 5620 sense_map = SLIST_FIRST(&scb_data->sense_maps); 5621 sense_data = sense_map->vaddr + offset; 5622 sense_busaddr = sense_map->physaddr + offset; 5623 } else { 5624 sense_map = malloc(sizeof(*sense_map), M_DEVBUF, M_NOWAIT); 5625 5626 if (sense_map == NULL) 5627 return; 5628 5629 /* Allocate the next batch of sense buffers */ 5630 if (ahd_dmamem_alloc(ahd, scb_data->sense_dmat, 5631 (void **)&sense_map->vaddr, 5632 BUS_DMA_NOWAIT, &sense_map->dmamap) != 0) { 5633 free(sense_map, M_DEVBUF); 5634 return; 5635 } 5636 5637 SLIST_INSERT_HEAD(&scb_data->sense_maps, sense_map, links); 5638 5639 ahd_dmamap_load(ahd, scb_data->sense_dmat, sense_map->dmamap, 5640 sense_map->vaddr, PAGE_SIZE, ahd_dmamap_cb, 5641 &sense_map->physaddr, /*flags*/0); 5642 5643 sense_data = sense_map->vaddr; 5644 sense_busaddr = sense_map->physaddr; 5645 scb_data->sense_left = PAGE_SIZE / AHD_SENSE_BUFSIZE; 5646 #ifdef AHD_DEBUG 5647 if (ahd_debug & AHD_SHOW_MEMORY) 5648 printf("Mapped sense data\n"); 5649 #endif 5650 } 5651 5652 newcount = MIN(scb_data->sense_left, scb_data->scbs_left); 5653 newcount = MIN(newcount, scb_data->sgs_left); 5654 newcount = MIN(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs)); 5655 scb_data->sense_left -= newcount; 5656 scb_data->scbs_left -= newcount; 5657 scb_data->sgs_left -= newcount; 5658 for (i = 0; i < newcount; i++) { 5659 u_int col_tag; 5660 5661 struct scb_platform_data *pdata; 5662 #ifndef __linux__ 5663 int error; 5664 #endif 5665 next_scb = (struct scb *)malloc(sizeof(*next_scb), 5666 M_DEVBUF, M_NOWAIT); 5667 if (next_scb == NULL) 5668 break; 5669 5670 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), 5671 M_DEVBUF, M_NOWAIT); 5672 if (pdata == NULL) { 5673 free(next_scb, M_DEVBUF); 5674 break; 5675 } 5676 next_scb->platform_data = pdata; 5677 next_scb->hscb_map = hscb_map; 5678 next_scb->sg_map = sg_map; 5679 next_scb->sense_map = sense_map; 5680 next_scb->sg_list = segs; 5681 next_scb->sense_data = sense_data; 5682 next_scb->sense_busaddr = sense_busaddr; 5683 next_scb->hscb = hscb; 5684 hscb->hscb_busaddr = ahd_htole32(hscb_busaddr); 5685 5686 /* 5687 * The sequencer always starts with the second entry. 5688 * The first entry is embedded in the scb. 5689 */ 5690 next_scb->sg_list_busaddr = sg_busaddr; 5691 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 5692 next_scb->sg_list_busaddr 5693 += sizeof(struct ahd_dma64_seg); 5694 else 5695 next_scb->sg_list_busaddr += sizeof(struct ahd_dma_seg); 5696 next_scb->ahd_softc = ahd; 5697 next_scb->flags = SCB_FLAG_NONE; 5698 #ifndef __linux__ 5699 error = ahd_dmamap_create(ahd, ahd->buffer_dmat, /*flags*/0, 5700 &next_scb->dmamap); 5701 if (error != 0) { 5702 free(next_scb, M_DEVBUF); 5703 free(pdata, M_DEVBUF); 5704 break; 5705 } 5706 #endif 5707 next_scb->hscb->tag = ahd_htole16(scb_data->numscbs); 5708 col_tag = scb_data->numscbs ^ 0x100; 5709 next_scb->col_scb = ahd_find_scb_by_tag(ahd, col_tag); 5710 if (next_scb->col_scb != NULL) 5711 next_scb->col_scb->col_scb = next_scb; 5712 ahd_free_scb(ahd, next_scb); 5713 hscb++; 5714 hscb_busaddr += sizeof(*hscb); 5715 segs += ahd_sglist_size(ahd); 5716 sg_busaddr += ahd_sglist_size(ahd); 5717 sense_data += AHD_SENSE_BUFSIZE; 5718 sense_busaddr += AHD_SENSE_BUFSIZE; 5719 scb_data->numscbs++; 5720 } 5721 } 5722 5723 void 5724 ahd_controller_info(struct ahd_softc *ahd, char *buf) 5725 { 5726 const char *speed; 5727 const char *type; 5728 int len; 5729 5730 len = sprintf(buf, "%s: ", ahd_chip_names[ahd->chip & AHD_CHIPID_MASK]); 5731 buf += len; 5732 5733 speed = "Ultra320 "; 5734 if ((ahd->features & AHD_WIDE) != 0) { 5735 type = "Wide "; 5736 } else { 5737 type = "Single "; 5738 } 5739 len = sprintf(buf, "%s%sChannel %c, SCSI Id=%d, ", 5740 speed, type, ahd->channel, ahd->our_id); 5741 buf += len; 5742 5743 sprintf(buf, "%s, %d SCBs", ahd->bus_description, 5744 ahd->scb_data.maxhscbs); 5745 } 5746 5747 static const char *channel_strings[] = { 5748 "Primary Low", 5749 "Primary High", 5750 "Secondary Low", 5751 "Secondary High" 5752 }; 5753 5754 static const char *termstat_strings[] = { 5755 "Terminated Correctly", 5756 "Over Terminated", 5757 "Under Terminated", 5758 "Not Configured" 5759 }; 5760 5761 /* 5762 * Start the board, ready for normal operation 5763 */ 5764 int 5765 ahd_init(struct ahd_softc *ahd) 5766 { 5767 uint8_t *base_vaddr; 5768 uint8_t *next_vaddr; 5769 bus_addr_t next_baddr; 5770 size_t driver_data_size; 5771 int i; 5772 int error; 5773 u_int warn_user; 5774 uint8_t current_sensing; 5775 uint8_t fstat; 5776 5777 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 5778 5779 ahd->stack_size = ahd_probe_stack_size(ahd); 5780 ahd->saved_stack = malloc(ahd->stack_size * sizeof(uint16_t), 5781 M_DEVBUF, M_NOWAIT); 5782 if (ahd->saved_stack == NULL) 5783 return (ENOMEM); 5784 5785 /* 5786 * Verify that the compiler hasn't over-agressively 5787 * padded important structures. 5788 */ 5789 if (sizeof(struct hardware_scb) != 64) 5790 panic("Hardware SCB size is incorrect"); 5791 5792 #ifdef AHD_DEBUG 5793 if ((ahd_debug & AHD_DEBUG_SEQUENCER) != 0) 5794 ahd->flags |= AHD_SEQUENCER_DEBUG; 5795 #endif 5796 5797 /* 5798 * Default to allowing initiator operations. 5799 */ 5800 ahd->flags |= AHD_INITIATORROLE; 5801 5802 /* 5803 * Only allow target mode features if this unit has them enabled. 5804 */ 5805 if ((AHD_TMODE_ENABLE & (0x1 << ahd->unit)) == 0) 5806 ahd->features &= ~AHD_TARGETMODE; 5807 5808 #ifndef __linux__ 5809 /* DMA tag for mapping buffers into device visible space. */ 5810 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1, 5811 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 5812 /*lowaddr*/BUS_SPACE_MAXADDR, 5813 /*highaddr*/BUS_SPACE_MAXADDR, 5814 /*filter*/NULL, /*filterarg*/NULL, 5815 /*maxsize*/(AHD_NSEG - 1) * PAGE_SIZE, 5816 /*nsegments*/AHD_NSEG, 5817 /*maxsegsz*/AHD_MAXTRANSFER_SIZE, 5818 /*flags*/BUS_DMA_ALLOCNOW, 5819 &ahd->buffer_dmat) != 0) { 5820 return (ENOMEM); 5821 } 5822 #endif 5823 5824 ahd->init_level++; 5825 5826 /* 5827 * DMA tag for our command fifos and other data in system memory 5828 * the card's sequencer must be able to access. For initiator 5829 * roles, we need to allocate space for the qoutfifo. When providing 5830 * for the target mode role, we must additionally provide space for 5831 * the incoming target command fifo. 5832 */ 5833 driver_data_size = AHD_SCB_MAX * sizeof(uint16_t) 5834 + sizeof(struct hardware_scb); 5835 if ((ahd->features & AHD_TARGETMODE) != 0) 5836 driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd); 5837 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) 5838 driver_data_size += PKT_OVERRUN_BUFSIZE; 5839 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1, 5840 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 5841 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 5842 /*highaddr*/BUS_SPACE_MAXADDR, 5843 /*filter*/NULL, /*filterarg*/NULL, 5844 driver_data_size, 5845 /*nsegments*/1, 5846 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 5847 /*flags*/0, &ahd->shared_data_dmat) != 0) { 5848 return (ENOMEM); 5849 } 5850 5851 ahd->init_level++; 5852 5853 /* Allocation of driver data */ 5854 if (ahd_dmamem_alloc(ahd, ahd->shared_data_dmat, 5855 (void **)&base_vaddr, 5856 BUS_DMA_NOWAIT, &ahd->shared_data_dmamap) != 0) { 5857 return (ENOMEM); 5858 } 5859 5860 ahd->init_level++; 5861 5862 /* And permanently map it in */ 5863 ahd_dmamap_load(ahd, ahd->shared_data_dmat, ahd->shared_data_dmamap, 5864 base_vaddr, driver_data_size, ahd_dmamap_cb, 5865 &ahd->shared_data_busaddr, /*flags*/0); 5866 ahd->qoutfifo = (uint16_t *)base_vaddr; 5867 next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE]; 5868 next_baddr = ahd->shared_data_busaddr + AHD_QOUT_SIZE*sizeof(uint16_t); 5869 if ((ahd->features & AHD_TARGETMODE) != 0) { 5870 ahd->targetcmds = (struct target_cmd *)next_vaddr; 5871 next_vaddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); 5872 next_baddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); 5873 } 5874 5875 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) { 5876 ahd->overrun_buf = next_vaddr; 5877 next_vaddr += PKT_OVERRUN_BUFSIZE; 5878 next_baddr += PKT_OVERRUN_BUFSIZE; 5879 } 5880 5881 /* 5882 * We need one SCB to serve as the "next SCB". Since the 5883 * tag identifier in this SCB will never be used, there is 5884 * no point in using a valid HSCB tag from an SCB pulled from 5885 * the standard free pool. So, we allocate this "sentinel" 5886 * specially from the DMA safe memory chunk used for the QOUTFIFO. 5887 */ 5888 ahd->next_queued_hscb = (struct hardware_scb *)next_vaddr; 5889 ahd->next_queued_hscb->hscb_busaddr = next_baddr; 5890 5891 ahd->init_level++; 5892 5893 /* Allocate SCB data now that buffer_dmat is initialized */ 5894 if (ahd_init_scbdata(ahd) != 0) 5895 return (ENOMEM); 5896 5897 if ((ahd->flags & AHD_INITIATORROLE) == 0) 5898 ahd->flags &= ~AHD_RESET_BUS_A; 5899 5900 /* 5901 * Before committing these settings to the chip, give 5902 * the OSM one last chance to modify our configuration. 5903 */ 5904 ahd_platform_init(ahd); 5905 5906 /* Bring up the chip. */ 5907 ahd_chip_init(ahd); 5908 5909 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 5910 5911 if ((ahd->flags & AHD_CURRENT_SENSING) == 0) 5912 goto init_done; 5913 5914 /* 5915 * Verify termination based on current draw and 5916 * warn user if the bus is over/under terminated. 5917 */ 5918 error = ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 5919 CURSENSE_ENB); 5920 if (error != 0) { 5921 printf("%s: current sensing timeout 1\n", ahd_name(ahd)); 5922 goto init_done; 5923 } 5924 for (i = 20, fstat = FLX_FSTAT_BUSY; 5925 (fstat & FLX_FSTAT_BUSY) != 0 && i; i--) { 5926 error = ahd_read_flexport(ahd, FLXADDR_FLEXSTAT, &fstat); 5927 if (error != 0) { 5928 printf("%s: current sensing timeout 2\n", 5929 ahd_name(ahd)); 5930 goto init_done; 5931 } 5932 } 5933 if (i == 0) { 5934 printf("%s: Timedout during current-sensing test\n", 5935 ahd_name(ahd)); 5936 goto init_done; 5937 } 5938 5939 /* Latch Current Sensing status. */ 5940 error = ahd_read_flexport(ahd, FLXADDR_CURRENT_STAT, ¤t_sensing); 5941 if (error != 0) { 5942 printf("%s: current sensing timeout 3\n", ahd_name(ahd)); 5943 goto init_done; 5944 } 5945 5946 /* Diable current sensing. */ 5947 ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 5948 5949 #ifdef AHD_DEBUG 5950 if ((ahd_debug & AHD_SHOW_TERMCTL) != 0) { 5951 printf("%s: current_sensing == 0x%x\n", 5952 ahd_name(ahd), current_sensing); 5953 } 5954 #endif 5955 warn_user = 0; 5956 for (i = 0; i < 4; i++, current_sensing >>= FLX_CSTAT_SHIFT) { 5957 u_int term_stat; 5958 5959 term_stat = (current_sensing & FLX_CSTAT_MASK); 5960 switch (term_stat) { 5961 case FLX_CSTAT_OVER: 5962 case FLX_CSTAT_UNDER: 5963 warn_user++; 5964 case FLX_CSTAT_INVALID: 5965 case FLX_CSTAT_OKAY: 5966 if (warn_user == 0 && bootverbose == 0) 5967 break; 5968 printf("%s: %s Channel %s\n", ahd_name(ahd), 5969 channel_strings[i], termstat_strings[term_stat]); 5970 break; 5971 } 5972 } 5973 if (warn_user) { 5974 printf("%s: WARNING. Termination is not configured correctly.\n" 5975 "%s: WARNING. SCSI bus operations may FAIL.\n", 5976 ahd_name(ahd), ahd_name(ahd)); 5977 } 5978 init_done: 5979 ahd_restart(ahd); 5980 ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US, 5981 ahd_stat_timer, ahd); 5982 return (0); 5983 } 5984 5985 /* 5986 * (Re)initialize chip state after a chip reset. 5987 */ 5988 static void 5989 ahd_chip_init(struct ahd_softc *ahd) 5990 { 5991 uint32_t busaddr; 5992 u_int sxfrctl1; 5993 u_int scsiseq_template; 5994 u_int wait; 5995 u_int i; 5996 u_int target; 5997 5998 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5999 /* 6000 * Take the LED out of diagnostic mode 6001 */ 6002 ahd_outb(ahd, SBLKCTL, ahd_inb(ahd, SBLKCTL) & ~(DIAGLEDEN|DIAGLEDON)); 6003 6004 /* 6005 * Return HS_MAILBOX to its default value. 6006 */ 6007 ahd->hs_mailbox = 0; 6008 ahd_outb(ahd, HS_MAILBOX, 0); 6009 6010 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */ 6011 ahd_outb(ahd, IOWNID, ahd->our_id); 6012 ahd_outb(ahd, TOWNID, ahd->our_id); 6013 sxfrctl1 = (ahd->flags & AHD_TERM_ENB_A) != 0 ? STPWEN : 0; 6014 sxfrctl1 |= (ahd->flags & AHD_SPCHK_ENB_A) != 0 ? ENSPCHK : 0; 6015 if ((ahd->bugs & AHD_LONG_SETIMO_BUG) 6016 && (ahd->seltime != STIMESEL_MIN)) { 6017 /* 6018 * The selection timer duration is twice as long 6019 * as it should be. Halve it by adding "1" to 6020 * the user specified setting. 6021 */ 6022 sxfrctl1 |= ahd->seltime + STIMESEL_BUG_ADJ; 6023 } else { 6024 sxfrctl1 |= ahd->seltime; 6025 } 6026 6027 ahd_outb(ahd, SXFRCTL0, DFON); 6028 ahd_outb(ahd, SXFRCTL1, sxfrctl1|ahd->seltime|ENSTIMER|ACTNEGEN); 6029 ahd_outb(ahd, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 6030 6031 /* 6032 * Now that termination is set, wait for up 6033 * to 500ms for our transceivers to settle. If 6034 * the adapter does not have a cable attached, 6035 * the tranceivers may never settle, so don't 6036 * complain if we fail here. 6037 */ 6038 for (wait = 10000; 6039 (ahd_inb(ahd, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 6040 wait--) 6041 ahd_delay(100); 6042 6043 /* Clear any false bus resets due to the transceivers settling */ 6044 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); 6045 ahd_outb(ahd, CLRINT, CLRSCSIINT); 6046 6047 /* Initialize mode specific S/G state. */ 6048 for (i = 0; i < 2; i++) { 6049 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); 6050 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 6051 ahd_outw(ahd, LONGJMP_SCB, SCB_LIST_NULL); 6052 ahd_outb(ahd, SG_STATE, 0); 6053 ahd_outb(ahd, CLRSEQINTSRC, 0xFF); 6054 ahd_outb(ahd, SEQIMODE, 6055 ENSAVEPTRS|ENCFG4DATA|ENCFG4ISTAT 6056 |ENCFG4TSTAT|ENCFG4ICMD|ENCFG4TCMD); 6057 } 6058 6059 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 6060 ahd_outb(ahd, DSCOMMAND0, ahd_inb(ahd, DSCOMMAND0)|MPARCKEN|CACHETHEN); 6061 ahd_outb(ahd, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 6062 ahd_outb(ahd, SIMODE0, ENIOERR|ENOVERRUN); 6063 ahd_outb(ahd, SIMODE3, ENNTRAMPERR|ENOSRAMPERR); 6064 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) { 6065 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|AUTO_MSGOUT_DE); 6066 } else { 6067 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|BUSFREEREV|AUTO_MSGOUT_DE); 6068 } 6069 ahd_outb(ahd, SCSCHKN, CURRFIFODEF|WIDERESEN|SHVALIDSTDIS); 6070 if ((ahd->chip & AHD_BUS_MASK) == AHD_PCIX) 6071 /* 6072 * Do not issue a target abort when a split completion 6073 * error occurs. Let our PCIX interrupt handler deal 6074 * with it instead. H2A4 Razor #625 6075 */ 6076 ahd_outb(ahd, PCIXCTL, ahd_inb(ahd, PCIXCTL) | SPLTSTADIS); 6077 6078 if ((ahd->bugs & AHD_LQOOVERRUN_BUG) != 0) 6079 ahd_outb(ahd, LQOSCSCTL, LQONOCHKOVER); 6080 6081 /* 6082 * Tweak IOCELL settings. 6083 */ 6084 if ((ahd->flags & AHD_HP_BOARD) != 0) { 6085 for (i = 0; i < NUMDSPS; i++) { 6086 ahd_outb(ahd, DSPSELECT, i); 6087 ahd_outb(ahd, WRTBIASCTL, WRTBIASCTL_HP_DEFAULT); 6088 } 6089 #ifdef AHD_DEBUG 6090 if ((ahd_debug & AHD_SHOW_MISC) != 0) 6091 printf("%s: WRTBIASCTL now 0x%x\n", ahd_name(ahd), 6092 WRTBIASCTL_HP_DEFAULT); 6093 #endif 6094 } 6095 ahd_setup_iocell_workaround(ahd); 6096 6097 /* 6098 * Enable LQI Manager interrupts. 6099 */ 6100 ahd_outb(ahd, LQIMODE1, ENLQIPHASE_LQ|ENLQIPHASE_NLQ|ENLIQABORT 6101 | ENLQICRCI_LQ|ENLQICRCI_NLQ|ENLQIBADLQI 6102 | ENLQIOVERI_LQ|ENLQIOVERI_NLQ); 6103 ahd_outb(ahd, LQOMODE0, ENLQOATNLQ|ENLQOATNPKT|ENLQOTCRC); 6104 /* 6105 * An interrupt from LQOBUSFREE is made redundant by the 6106 * BUSFREE interrupt. We choose to have the sequencer catch 6107 * LQOPHCHGINPKT errors manually for the command phase at the 6108 * start of a packetized selection case. 6109 ahd_outb(ahd, LQOMODE1, ENLQOBUSFREE|ENLQOPHACHGINPKT); 6110 */ 6111 ahd_outb(ahd, LQOMODE1, 0); 6112 6113 /* 6114 * Setup sequencer interrupt handlers. 6115 */ 6116 ahd_outw(ahd, INTVEC1_ADDR, ahd_resolve_seqaddr(ahd, LABEL_seq_isr)); 6117 ahd_outw(ahd, INTVEC2_ADDR, ahd_resolve_seqaddr(ahd, LABEL_timer_isr)); 6118 6119 /* 6120 * Setup SCB Offset registers. 6121 */ 6122 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { 6123 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, 6124 pkt_long_lun)); 6125 } else { 6126 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, lun)); 6127 } 6128 ahd_outb(ahd, CMDLENPTR, offsetof(struct hardware_scb, cdb_len)); 6129 ahd_outb(ahd, ATTRPTR, offsetof(struct hardware_scb, task_attribute)); 6130 ahd_outb(ahd, FLAGPTR, offsetof(struct hardware_scb, task_management)); 6131 ahd_outb(ahd, CMDPTR, offsetof(struct hardware_scb, 6132 shared_data.idata.cdb)); 6133 ahd_outb(ahd, QNEXTPTR, 6134 offsetof(struct hardware_scb, next_hscb_busaddr)); 6135 ahd_outb(ahd, ABRTBITPTR, MK_MESSAGE_BIT_OFFSET); 6136 ahd_outb(ahd, ABRTBYTEPTR, offsetof(struct hardware_scb, control)); 6137 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { 6138 ahd_outb(ahd, LUNLEN, 6139 sizeof(ahd->next_queued_hscb->pkt_long_lun) - 1); 6140 } else { 6141 ahd_outb(ahd, LUNLEN, sizeof(ahd->next_queued_hscb->lun) - 1); 6142 } 6143 ahd_outb(ahd, CDBLIMIT, SCB_CDB_LEN_PTR - 1); 6144 ahd_outb(ahd, MAXCMD, 0xFF); 6145 ahd_outb(ahd, SCBAUTOPTR, 6146 AUSCBPTR_EN | offsetof(struct hardware_scb, tag)); 6147 6148 /* We haven't been enabled for target mode yet. */ 6149 ahd_outb(ahd, MULTARGID, 0); 6150 ahd_outb(ahd, MULTARGID + 1, 0); 6151 6152 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6153 /* Initialize the negotiation table. */ 6154 if ((ahd->features & AHD_NEW_IOCELL_OPTS) == 0) { 6155 /* 6156 * Clear the spare bytes in the neg table to avoid 6157 * spurious parity errors. 6158 */ 6159 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6160 ahd_outb(ahd, NEGOADDR, target); 6161 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PER_DEV0); 6162 for (i = 0; i < AHD_NUM_PER_DEV_ANNEXCOLS; i++) 6163 ahd_outb(ahd, ANNEXDAT, 0); 6164 } 6165 } 6166 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6167 struct ahd_devinfo devinfo; 6168 struct ahd_initiator_tinfo *tinfo; 6169 struct ahd_tmode_tstate *tstate; 6170 6171 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6172 target, &tstate); 6173 ahd_compile_devinfo(&devinfo, ahd->our_id, 6174 target, CAM_LUN_WILDCARD, 6175 'A', ROLE_INITIATOR); 6176 ahd_update_neg_table(ahd, &devinfo, &tinfo->curr); 6177 } 6178 6179 ahd_outb(ahd, CLRSINT3, NTRAMPERR|OSRAMPERR); 6180 ahd_outb(ahd, CLRINT, CLRSCSIINT); 6181 6182 /* 6183 * Always enable abort on incoming L_Qs if this feature is 6184 * supported. We use this to catch invalid SCB references. 6185 */ 6186 if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0) 6187 ahd_outb(ahd, LQCTL1, ABORTPENDING); 6188 else 6189 ahd_outb(ahd, LQCTL1, 0); 6190 6191 /* All of our queues are empty */ 6192 ahd->qoutfifonext = 0; 6193 ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID_LE; 6194 ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID >> 8); 6195 for (i = 0; i < AHD_QOUT_SIZE; i++) 6196 ahd->qoutfifo[i] = 0; 6197 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD); 6198 6199 ahd->qinfifonext = 0; 6200 for (i = 0; i < AHD_QIN_SIZE; i++) 6201 ahd->qinfifo[i] = SCB_LIST_NULL; 6202 6203 if ((ahd->features & AHD_TARGETMODE) != 0) { 6204 /* All target command blocks start out invalid. */ 6205 for (i = 0; i < AHD_TMODE_CMDS; i++) 6206 ahd->targetcmds[i].cmd_valid = 0; 6207 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_PREREAD); 6208 ahd->tqinfifonext = 1; 6209 ahd_outb(ahd, KERNEL_TQINPOS, ahd->tqinfifonext - 1); 6210 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); 6211 } 6212 6213 /* Initialize Scratch Ram. */ 6214 ahd_outb(ahd, SEQ_FLAGS, 0); 6215 ahd_outb(ahd, SEQ_FLAGS2, 0); 6216 6217 /* We don't have any waiting selections */ 6218 ahd_outw(ahd, WAITING_TID_HEAD, SCB_LIST_NULL); 6219 ahd_outw(ahd, WAITING_TID_TAIL, SCB_LIST_NULL); 6220 for (i = 0; i < AHD_NUM_TARGETS; i++) 6221 ahd_outw(ahd, WAITING_SCB_TAILS + (2 * i), SCB_LIST_NULL); 6222 6223 /* 6224 * Nobody is waiting to be DMAed into the QOUTFIFO. 6225 */ 6226 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); 6227 ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL); 6228 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); 6229 6230 /* 6231 * The Freeze Count is 0. 6232 */ 6233 ahd_outw(ahd, QFREEZE_COUNT, 0); 6234 6235 /* 6236 * Tell the sequencer where it can find our arrays in memory. 6237 */ 6238 busaddr = ahd->shared_data_busaddr; 6239 ahd_outb(ahd, SHARED_DATA_ADDR, busaddr & 0xFF); 6240 ahd_outb(ahd, SHARED_DATA_ADDR + 1, (busaddr >> 8) & 0xFF); 6241 ahd_outb(ahd, SHARED_DATA_ADDR + 2, (busaddr >> 16) & 0xFF); 6242 ahd_outb(ahd, SHARED_DATA_ADDR + 3, (busaddr >> 24) & 0xFF); 6243 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR, busaddr & 0xFF); 6244 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 1, (busaddr >> 8) & 0xFF); 6245 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 2, (busaddr >> 16) & 0xFF); 6246 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 3, (busaddr >> 24) & 0xFF); 6247 6248 /* 6249 * Setup the allowed SCSI Sequences based on operational mode. 6250 * If we are a target, we'll enable select in operations once 6251 * we've had a lun enabled. 6252 */ 6253 scsiseq_template = ENAUTOATNP; 6254 if ((ahd->flags & AHD_INITIATORROLE) != 0) 6255 scsiseq_template |= ENRSELI; 6256 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq_template); 6257 6258 /* There are no busy SCBs yet. */ 6259 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6260 int lun; 6261 6262 for (lun = 0; lun < AHD_NUM_LUNS_NONPKT; lun++) 6263 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(target, 'A', lun)); 6264 } 6265 6266 /* 6267 * Initialize the group code to command length table. 6268 * Vendor Unique codes are set to 0 so we only capture 6269 * the first byte of the cdb. These can be overridden 6270 * when target mode is enabled. 6271 */ 6272 ahd_outb(ahd, CMDSIZE_TABLE, 5); 6273 ahd_outb(ahd, CMDSIZE_TABLE + 1, 9); 6274 ahd_outb(ahd, CMDSIZE_TABLE + 2, 9); 6275 ahd_outb(ahd, CMDSIZE_TABLE + 3, 0); 6276 ahd_outb(ahd, CMDSIZE_TABLE + 4, 15); 6277 ahd_outb(ahd, CMDSIZE_TABLE + 5, 11); 6278 ahd_outb(ahd, CMDSIZE_TABLE + 6, 0); 6279 ahd_outb(ahd, CMDSIZE_TABLE + 7, 0); 6280 6281 /* Tell the sequencer of our initial queue positions */ 6282 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6283 ahd_outb(ahd, QOFF_CTLSTA, SCB_QSIZE_512); 6284 ahd->qinfifonext = 0; 6285 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 6286 ahd_set_hescb_qoff(ahd, 0); 6287 ahd_set_snscb_qoff(ahd, 0); 6288 ahd_set_sescb_qoff(ahd, 0); 6289 ahd_set_sdscb_qoff(ahd, 0); 6290 6291 /* 6292 * Tell the sequencer which SCB will be the next one it receives. 6293 */ 6294 busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr); 6295 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); 6296 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); 6297 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); 6298 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); 6299 6300 /* 6301 * Default to coalessing disabled. 6302 */ 6303 ahd_outw(ahd, INT_COALESSING_CMDCOUNT, 0); 6304 ahd_outw(ahd, CMDS_PENDING, 0); 6305 ahd_update_coalessing_values(ahd, ahd->int_coalessing_timer, 6306 ahd->int_coalessing_maxcmds, 6307 ahd->int_coalessing_mincmds); 6308 ahd_enable_coalessing(ahd, FALSE); 6309 6310 ahd_loadseq(ahd); 6311 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6312 } 6313 6314 /* 6315 * Setup default device and controller settings. 6316 * This should only be called if our probe has 6317 * determined that no configuration data is available. 6318 */ 6319 int 6320 ahd_default_config(struct ahd_softc *ahd) 6321 { 6322 int targ; 6323 6324 ahd->our_id = 7; 6325 6326 /* 6327 * Allocate a tstate to house information for our 6328 * initiator presence on the bus as well as the user 6329 * data for any target mode initiator. 6330 */ 6331 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { 6332 printf("%s: unable to allocate ahd_tmode_tstate. " 6333 "Failing attach\n", ahd_name(ahd)); 6334 return (ENOMEM); 6335 } 6336 6337 for (targ = 0; targ < AHD_NUM_TARGETS; targ++) { 6338 struct ahd_devinfo devinfo; 6339 struct ahd_initiator_tinfo *tinfo; 6340 struct ahd_tmode_tstate *tstate; 6341 uint16_t target_mask; 6342 6343 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6344 targ, &tstate); 6345 /* 6346 * We support SPC2 and SPI4. 6347 */ 6348 tinfo->user.protocol_version = 4; 6349 tinfo->user.transport_version = 4; 6350 6351 target_mask = 0x01 << targ; 6352 ahd->user_discenable |= target_mask; 6353 tstate->discenable |= target_mask; 6354 ahd->user_tagenable |= target_mask; 6355 #ifdef AHD_FORCE_160 6356 tinfo->user.period = AHD_SYNCRATE_DT; 6357 #else 6358 tinfo->user.period = AHD_SYNCRATE_160; 6359 #endif 6360 tinfo->user.offset = MAX_OFFSET; 6361 tinfo->user.ppr_options = MSG_EXT_PPR_RD_STRM 6362 | MSG_EXT_PPR_WR_FLOW 6363 | MSG_EXT_PPR_HOLD_MCS 6364 | MSG_EXT_PPR_IU_REQ 6365 | MSG_EXT_PPR_QAS_REQ 6366 | MSG_EXT_PPR_DT_REQ; 6367 if ((ahd->features & AHD_RTI) != 0) 6368 tinfo->user.ppr_options |= MSG_EXT_PPR_RTI; 6369 6370 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 6371 6372 /* 6373 * Start out Async/Narrow/Untagged and with 6374 * conservative protocol support. 6375 */ 6376 tinfo->goal.protocol_version = 2; 6377 tinfo->goal.transport_version = 2; 6378 tinfo->curr.protocol_version = 2; 6379 tinfo->curr.transport_version = 2; 6380 ahd_compile_devinfo(&devinfo, ahd->our_id, 6381 targ, CAM_LUN_WILDCARD, 6382 'A', ROLE_INITIATOR); 6383 tstate->tagenable &= ~target_mask; 6384 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6385 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); 6386 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, 6387 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, 6388 /*paused*/TRUE); 6389 } 6390 return (0); 6391 } 6392 6393 /* 6394 * Parse device configuration information. 6395 */ 6396 int 6397 ahd_parse_cfgdata(struct ahd_softc *ahd, struct seeprom_config *sc) 6398 { 6399 int targ; 6400 int max_targ; 6401 6402 max_targ = sc->max_targets & CFMAXTARG; 6403 ahd->our_id = sc->brtime_id & CFSCSIID; 6404 6405 /* 6406 * Allocate a tstate to house information for our 6407 * initiator presence on the bus as well as the user 6408 * data for any target mode initiator. 6409 */ 6410 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { 6411 printf("%s: unable to allocate ahd_tmode_tstate. " 6412 "Failing attach\n", ahd_name(ahd)); 6413 return (ENOMEM); 6414 } 6415 6416 for (targ = 0; targ < max_targ; targ++) { 6417 struct ahd_devinfo devinfo; 6418 struct ahd_initiator_tinfo *tinfo; 6419 struct ahd_transinfo *user_tinfo; 6420 struct ahd_tmode_tstate *tstate; 6421 uint16_t target_mask; 6422 6423 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6424 targ, &tstate); 6425 user_tinfo = &tinfo->user; 6426 6427 /* 6428 * We support SPC2 and SPI4. 6429 */ 6430 tinfo->user.protocol_version = 4; 6431 tinfo->user.transport_version = 4; 6432 6433 target_mask = 0x01 << targ; 6434 ahd->user_discenable &= ~target_mask; 6435 tstate->discenable &= ~target_mask; 6436 ahd->user_tagenable &= ~target_mask; 6437 if (sc->device_flags[targ] & CFDISC) { 6438 tstate->discenable |= target_mask; 6439 ahd->user_discenable |= target_mask; 6440 ahd->user_tagenable |= target_mask; 6441 } else { 6442 /* 6443 * Cannot be packetized without disconnection. 6444 */ 6445 sc->device_flags[targ] &= ~CFPACKETIZED; 6446 } 6447 6448 user_tinfo->ppr_options = 0; 6449 user_tinfo->period = (sc->device_flags[targ] & CFXFER); 6450 if (user_tinfo->period < CFXFER_ASYNC) { 6451 if (user_tinfo->period <= AHD_PERIOD_10MHz) 6452 user_tinfo->ppr_options |= MSG_EXT_PPR_DT_REQ; 6453 user_tinfo->offset = MAX_OFFSET; 6454 } else { 6455 user_tinfo->offset = 0; 6456 user_tinfo->period = AHD_ASYNC_XFER_PERIOD; 6457 } 6458 #ifdef AHD_FORCE_160 6459 if (user_tinfo->period <= AHD_SYNCRATE_160) 6460 user_tinfo->period = AHD_SYNCRATE_DT; 6461 #endif 6462 6463 if ((sc->device_flags[targ] & CFPACKETIZED) != 0) { 6464 user_tinfo->ppr_options |= MSG_EXT_PPR_RD_STRM 6465 | MSG_EXT_PPR_WR_FLOW 6466 | MSG_EXT_PPR_HOLD_MCS 6467 | MSG_EXT_PPR_IU_REQ; 6468 if ((ahd->features & AHD_RTI) != 0) 6469 user_tinfo->ppr_options |= MSG_EXT_PPR_RTI; 6470 } 6471 6472 if ((sc->device_flags[targ] & CFQAS) != 0) 6473 user_tinfo->ppr_options |= MSG_EXT_PPR_QAS_REQ; 6474 6475 if ((sc->device_flags[targ] & CFWIDEB) != 0) 6476 user_tinfo->width = MSG_EXT_WDTR_BUS_16_BIT; 6477 else 6478 user_tinfo->width = MSG_EXT_WDTR_BUS_8_BIT; 6479 #ifdef AHD_DEBUG 6480 if ((ahd_debug & AHD_SHOW_MISC) != 0) 6481 printf("(%d): %x:%x:%x:%x\n", targ, user_tinfo->width, 6482 user_tinfo->period, user_tinfo->offset, 6483 user_tinfo->ppr_options); 6484 #endif 6485 /* 6486 * Start out Async/Narrow/Untagged and with 6487 * conservative protocol support. 6488 */ 6489 tstate->tagenable &= ~target_mask; 6490 tinfo->goal.protocol_version = 2; 6491 tinfo->goal.transport_version = 2; 6492 tinfo->curr.protocol_version = 2; 6493 tinfo->curr.transport_version = 2; 6494 ahd_compile_devinfo(&devinfo, ahd->our_id, 6495 targ, CAM_LUN_WILDCARD, 6496 'A', ROLE_INITIATOR); 6497 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6498 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); 6499 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, 6500 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, 6501 /*paused*/TRUE); 6502 } 6503 6504 ahd->flags &= ~AHD_SPCHK_ENB_A; 6505 if (sc->bios_control & CFSPARITY) 6506 ahd->flags |= AHD_SPCHK_ENB_A; 6507 6508 ahd->flags &= ~AHD_RESET_BUS_A; 6509 if (sc->bios_control & CFRESETB) 6510 ahd->flags |= AHD_RESET_BUS_A; 6511 6512 ahd->flags &= ~AHD_EXTENDED_TRANS_A; 6513 if (sc->bios_control & CFEXTEND) 6514 ahd->flags |= AHD_EXTENDED_TRANS_A; 6515 6516 ahd->flags &= ~AHD_BIOS_ENABLED; 6517 if ((sc->bios_control & CFBIOSSTATE) == CFBS_ENABLED) 6518 ahd->flags |= AHD_BIOS_ENABLED; 6519 6520 ahd->flags &= ~AHD_STPWLEVEL_A; 6521 if ((sc->adapter_control & CFSTPWLEVEL) != 0) 6522 ahd->flags |= AHD_STPWLEVEL_A; 6523 6524 return (0); 6525 } 6526 6527 void 6528 ahd_intr_enable(struct ahd_softc *ahd, int enable) 6529 { 6530 u_int hcntrl; 6531 6532 hcntrl = ahd_inb(ahd, HCNTRL); 6533 hcntrl &= ~INTEN; 6534 ahd->pause &= ~INTEN; 6535 ahd->unpause &= ~INTEN; 6536 if (enable) { 6537 hcntrl |= INTEN; 6538 ahd->pause |= INTEN; 6539 ahd->unpause |= INTEN; 6540 } 6541 ahd_outb(ahd, HCNTRL, hcntrl); 6542 } 6543 6544 void 6545 ahd_update_coalessing_values(struct ahd_softc *ahd, u_int timer, u_int maxcmds, 6546 u_int mincmds) 6547 { 6548 if (timer > AHD_TIMER_MAX_US) 6549 timer = AHD_TIMER_MAX_US; 6550 ahd->int_coalessing_timer = timer; 6551 6552 if (maxcmds > AHD_INT_COALESSING_MAXCMDS_MAX) 6553 maxcmds = AHD_INT_COALESSING_MAXCMDS_MAX; 6554 if (mincmds > AHD_INT_COALESSING_MINCMDS_MAX) 6555 mincmds = AHD_INT_COALESSING_MINCMDS_MAX; 6556 ahd->int_coalessing_maxcmds = maxcmds; 6557 ahd_outw(ahd, INT_COALESSING_TIMER, timer / AHD_TIMER_US_PER_TICK); 6558 ahd_outb(ahd, INT_COALESSING_MAXCMDS, -maxcmds); 6559 ahd_outb(ahd, INT_COALESSING_MINCMDS, -mincmds); 6560 } 6561 6562 void 6563 ahd_enable_coalessing(struct ahd_softc *ahd, int enable) 6564 { 6565 6566 ahd->hs_mailbox &= ~ENINT_COALESS; 6567 if (enable) 6568 ahd->hs_mailbox |= ENINT_COALESS; 6569 ahd_outb(ahd, HS_MAILBOX, ahd->hs_mailbox); 6570 ahd_flush_device_writes(ahd); 6571 ahd_run_qoutfifo(ahd); 6572 } 6573 6574 /* 6575 * Ensure that the card is paused in a location 6576 * outside of all critical sections and that all 6577 * pending work is completed prior to returning. 6578 * This routine should only be called from outside 6579 * an interrupt context. 6580 */ 6581 void 6582 ahd_pause_and_flushwork(struct ahd_softc *ahd) 6583 { 6584 ahd_mode_state saved_modes; 6585 u_int intstat; 6586 u_int maxloops; 6587 int paused; 6588 6589 maxloops = 1000; 6590 ahd->flags |= AHD_ALL_INTERRUPTS; 6591 paused = FALSE; 6592 do { 6593 struct scb *waiting_scb; 6594 6595 if (paused) 6596 ahd_unpause(ahd); 6597 ahd_intr(ahd); 6598 ahd_pause(ahd); 6599 paused = TRUE; 6600 ahd_clear_critical_section(ahd); 6601 saved_modes = ahd_save_modes(ahd); 6602 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6603 if ((ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0) 6604 ahd_outb(ahd, SCSISEQ0, 6605 ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 6606 /* 6607 * In the non-packetized case, the sequencer (for Rev A), 6608 * relies on ENSELO remaining set after SELDO. The hardware 6609 * auto-clears ENSELO in the packetized case. 6610 */ 6611 waiting_scb = ahd_lookup_scb(ahd, 6612 ahd_inw(ahd, WAITING_TID_HEAD)); 6613 if (waiting_scb != NULL 6614 && (waiting_scb->flags & SCB_PACKETIZED) == 0 6615 && (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0) 6616 ahd_outb(ahd, SCSISEQ0, 6617 ahd_inb(ahd, SCSISEQ0) | ENSELO); 6618 6619 intstat = ahd_inb(ahd, INTSTAT); 6620 } while (--maxloops 6621 && (intstat != 0xFF || (ahd->features & AHD_REMOVABLE) == 0) 6622 && ((intstat & INT_PEND) != 0 6623 || (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)))); 6624 if (maxloops == 0) { 6625 printf("Infinite interrupt loop, INTSTAT = %x", 6626 ahd_inb(ahd, INTSTAT)); 6627 } 6628 6629 ahd_flush_qoutfifo(ahd); 6630 6631 ahd_platform_flushwork(ahd); 6632 ahd->flags &= ~AHD_ALL_INTERRUPTS; 6633 ahd_restore_modes(ahd, saved_modes); 6634 } 6635 6636 int 6637 ahd_suspend(struct ahd_softc *ahd) 6638 { 6639 #if 0 6640 uint8_t *ptr; 6641 int i; 6642 6643 ahd_pause_and_flushwork(ahd); 6644 6645 if (LIST_FIRST(&ahd->pending_scbs) != NULL) 6646 return (EBUSY); 6647 6648 #if AHD_TARGET_MODE 6649 /* 6650 * XXX What about ATIOs that have not yet been serviced? 6651 * Perhaps we should just refuse to be suspended if we 6652 * are acting in a target role. 6653 */ 6654 if (ahd->pending_device != NULL) 6655 return (EBUSY); 6656 #endif 6657 6658 /* Save volatile registers */ 6659 ahd->suspend_state.channel[0].scsiseq = ahd_inb(ahd, SCSISEQ0); 6660 ahd->suspend_state.channel[0].sxfrctl0 = ahd_inb(ahd, SXFRCTL0); 6661 ahd->suspend_state.channel[0].sxfrctl1 = ahd_inb(ahd, SXFRCTL1); 6662 ahd->suspend_state.channel[0].simode0 = ahd_inb(ahd, SIMODE0); 6663 ahd->suspend_state.channel[0].simode1 = ahd_inb(ahd, SIMODE1); 6664 ahd->suspend_state.channel[0].seltimer = ahd_inb(ahd, SELTIMER); 6665 ahd->suspend_state.channel[0].seqctl = ahd_inb(ahd, SEQCTL0); 6666 ahd->suspend_state.dscommand0 = ahd_inb(ahd, DSCOMMAND0); 6667 ahd->suspend_state.dspcistatus = ahd_inb(ahd, DSPCISTATUS); 6668 6669 if ((ahd->features & AHD_DT) != 0) { 6670 u_int sfunct; 6671 6672 sfunct = ahd_inb(ahd, SFUNCT) & ~ALT_MODE; 6673 ahd_outb(ahd, SFUNCT, sfunct | ALT_MODE); 6674 ahd->suspend_state.optionmode = ahd_inb(ahd, OPTIONMODE); 6675 ahd_outb(ahd, SFUNCT, sfunct); 6676 ahd->suspend_state.crccontrol1 = ahd_inb(ahd, CRCCONTROL1); 6677 } 6678 6679 if ((ahd->features & AHD_MULTI_FUNC) != 0) 6680 ahd->suspend_state.scbbaddr = ahd_inb(ahd, SCBBADDR); 6681 6682 if ((ahd->features & AHD_ULTRA2) != 0) 6683 ahd->suspend_state.dff_thrsh = ahd_inb(ahd, DFF_THRSH); 6684 6685 ptr = ahd->suspend_state.scratch_ram; 6686 for (i = 0; i < 64; i++) 6687 *ptr++ = ahd_inb(ahd, SRAM_BASE + i); 6688 6689 if ((ahd->features & AHD_MORE_SRAM) != 0) { 6690 for (i = 0; i < 16; i++) 6691 *ptr++ = ahd_inb(ahd, TARG_OFFSET + i); 6692 } 6693 6694 ptr = ahd->suspend_state.btt; 6695 for (i = 0;i < AHD_NUM_TARGETS; i++) { 6696 int j; 6697 6698 for (j = 0;j < AHD_NUM_LUNS_NONPKT; j++) { 6699 u_int tcl; 6700 6701 tcl = BUILD_TCL_RAW(i, 'A', j); 6702 *ptr = ahd_find_busy_tcl(ahd, tcl); 6703 } 6704 } 6705 ahd_shutdown(ahd); 6706 #endif 6707 return (0); 6708 } 6709 6710 int 6711 ahd_resume(struct ahd_softc *ahd) 6712 { 6713 #if 0 6714 uint8_t *ptr; 6715 int i; 6716 6717 ahd_reset(ahd); 6718 6719 ahd_build_free_scb_list(ahd); 6720 6721 /* Restore volatile registers */ 6722 ahd_outb(ahd, SCSISEQ0, ahd->suspend_state.channel[0].scsiseq); 6723 ahd_outb(ahd, SXFRCTL0, ahd->suspend_state.channel[0].sxfrctl0); 6724 ahd_outb(ahd, SXFRCTL1, ahd->suspend_state.channel[0].sxfrctl1); 6725 ahd_outb(ahd, SIMODE0, ahd->suspend_state.channel[0].simode0); 6726 ahd_outb(ahd, SIMODE1, ahd->suspend_state.channel[0].simode1); 6727 ahd_outb(ahd, SELTIMER, ahd->suspend_state.channel[0].seltimer); 6728 ahd_outb(ahd, SEQCTL0, ahd->suspend_state.channel[0].seqctl); 6729 if ((ahd->features & AHD_ULTRA2) != 0) 6730 ahd_outb(ahd, SCSIID_ULTRA2, ahd->our_id); 6731 else 6732 ahd_outb(ahd, SCSIID, ahd->our_id); 6733 6734 ahd_outb(ahd, DSCOMMAND0, ahd->suspend_state.dscommand0); 6735 ahd_outb(ahd, DSPCISTATUS, ahd->suspend_state.dspcistatus); 6736 6737 if ((ahd->features & AHD_DT) != 0) { 6738 u_int sfunct; 6739 6740 sfunct = ahd_inb(ahd, SFUNCT) & ~ALT_MODE; 6741 ahd_outb(ahd, SFUNCT, sfunct | ALT_MODE); 6742 ahd_outb(ahd, OPTIONMODE, ahd->suspend_state.optionmode); 6743 ahd_outb(ahd, SFUNCT, sfunct); 6744 ahd_outb(ahd, CRCCONTROL1, ahd->suspend_state.crccontrol1); 6745 } 6746 6747 if ((ahd->features & AHD_MULTI_FUNC) != 0) 6748 ahd_outb(ahd, SCBBADDR, ahd->suspend_state.scbbaddr); 6749 6750 if ((ahd->features & AHD_ULTRA2) != 0) 6751 ahd_outb(ahd, DFF_THRSH, ahd->suspend_state.dff_thrsh); 6752 6753 ptr = ahd->suspend_state.scratch_ram; 6754 for (i = 0; i < 64; i++) 6755 ahd_outb(ahd, SRAM_BASE + i, *ptr++); 6756 6757 if ((ahd->features & AHD_MORE_SRAM) != 0) { 6758 for (i = 0; i < 16; i++) 6759 ahd_outb(ahd, TARG_OFFSET + i, *ptr++); 6760 } 6761 6762 ptr = ahd->suspend_state.btt; 6763 for (i = 0;i < AHD_NUM_TARGETS; i++) { 6764 int j; 6765 6766 for (j = 0;j < AHD_NUM_LUNS; j++) { 6767 u_int tcl; 6768 6769 tcl = BUILD_TCL(i << 4, j); 6770 ahd_busy_tcl(ahd, tcl, *ptr); 6771 } 6772 } 6773 #endif 6774 return (0); 6775 } 6776 6777 /************************** Busy Target Table *********************************/ 6778 /* 6779 * Set SCBPTR to the SCB that contains the busy 6780 * table entry for TCL. Return the offset into 6781 * the SCB that contains the entry for TCL. 6782 * saved_scbid is dereferenced and set to the 6783 * scbid that should be restored once manipualtion 6784 * of the TCL entry is complete. 6785 */ 6786 static __inline u_int 6787 ahd_index_busy_tcl(struct ahd_softc *ahd, u_int *saved_scbid, u_int tcl) 6788 { 6789 /* 6790 * Index to the SCB that contains the busy entry. 6791 */ 6792 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 6793 *saved_scbid = ahd_get_scbptr(ahd); 6794 ahd_set_scbptr(ahd, TCL_LUN(tcl) 6795 | ((TCL_TARGET_OFFSET(tcl) & 0xC) << 4)); 6796 6797 /* 6798 * And now calculate the SCB offset to the entry. 6799 * Each entry is 2 bytes wide, hence the 6800 * multiplication by 2. 6801 */ 6802 return (((TCL_TARGET_OFFSET(tcl) & 0x3) << 1) + SCB_DISCONNECTED_LISTS); 6803 } 6804 6805 /* 6806 * Return the untagged transaction id for a given target/channel lun. 6807 * Optionally, clear the entry. 6808 */ 6809 u_int 6810 ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl) 6811 { 6812 u_int scbid; 6813 u_int scb_offset; 6814 u_int saved_scbptr; 6815 6816 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); 6817 scbid = ahd_inw_scbram(ahd, scb_offset); 6818 ahd_set_scbptr(ahd, saved_scbptr); 6819 return (scbid); 6820 } 6821 6822 void 6823 ahd_busy_tcl(struct ahd_softc *ahd, u_int tcl, u_int scbid) 6824 { 6825 u_int scb_offset; 6826 u_int saved_scbptr; 6827 6828 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); 6829 ahd_outw(ahd, scb_offset, scbid); 6830 ahd_set_scbptr(ahd, saved_scbptr); 6831 } 6832 6833 /************************** SCB and SCB queue management **********************/ 6834 int 6835 ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, int target, 6836 char channel, int lun, u_int tag, role_t role) 6837 { 6838 int targ = SCB_GET_TARGET(ahd, scb); 6839 char chan = SCB_GET_CHANNEL(ahd, scb); 6840 int slun = SCB_GET_LUN(scb); 6841 int match; 6842 6843 match = ((chan == channel) || (channel == ALL_CHANNELS)); 6844 if (match != 0) 6845 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 6846 if (match != 0) 6847 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 6848 if (match != 0) { 6849 #if AHD_TARGET_MODE 6850 int group; 6851 6852 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 6853 if (role == ROLE_INITIATOR) { 6854 match = (group != XPT_FC_GROUP_TMODE) 6855 && ((tag == SCB_GET_TAG(scb)) 6856 || (tag == SCB_LIST_NULL)); 6857 } else if (role == ROLE_TARGET) { 6858 match = (group == XPT_FC_GROUP_TMODE) 6859 && ((tag == scb->io_ctx->csio.tag_id) 6860 || (tag == SCB_LIST_NULL)); 6861 } 6862 #else /* !AHD_TARGET_MODE */ 6863 match = ((tag == SCB_GET_TAG(scb)) || (tag == SCB_LIST_NULL)); 6864 #endif /* AHD_TARGET_MODE */ 6865 } 6866 6867 return match; 6868 } 6869 6870 void 6871 ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb) 6872 { 6873 int target; 6874 char channel; 6875 int lun; 6876 6877 target = SCB_GET_TARGET(ahd, scb); 6878 lun = SCB_GET_LUN(scb); 6879 channel = SCB_GET_CHANNEL(ahd, scb); 6880 6881 ahd_search_qinfifo(ahd, target, channel, lun, 6882 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 6883 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 6884 6885 ahd_platform_freeze_devq(ahd, scb); 6886 } 6887 6888 void 6889 ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, struct scb *scb) 6890 { 6891 struct scb *prev_scb; 6892 ahd_mode_state saved_modes; 6893 6894 saved_modes = ahd_save_modes(ahd); 6895 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6896 prev_scb = NULL; 6897 if (ahd_qinfifo_count(ahd) != 0) { 6898 u_int prev_tag; 6899 u_int prev_pos; 6900 6901 prev_pos = AHD_QIN_WRAP(ahd->qinfifonext - 1); 6902 prev_tag = ahd->qinfifo[prev_pos]; 6903 prev_scb = ahd_lookup_scb(ahd, prev_tag); 6904 } 6905 ahd_qinfifo_requeue(ahd, prev_scb, scb); 6906 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 6907 ahd_restore_modes(ahd, saved_modes); 6908 } 6909 6910 static void 6911 ahd_qinfifo_requeue(struct ahd_softc *ahd, struct scb *prev_scb, 6912 struct scb *scb) 6913 { 6914 if (prev_scb == NULL) { 6915 uint32_t busaddr; 6916 6917 busaddr = ahd_le32toh(scb->hscb->hscb_busaddr); 6918 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); 6919 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); 6920 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); 6921 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); 6922 } else { 6923 prev_scb->hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr; 6924 ahd_sync_scb(ahd, prev_scb, 6925 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 6926 } 6927 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb); 6928 ahd->qinfifonext++; 6929 scb->hscb->next_hscb_busaddr = ahd->next_queued_hscb->hscb_busaddr; 6930 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 6931 } 6932 6933 static int 6934 ahd_qinfifo_count(struct ahd_softc *ahd) 6935 { 6936 u_int qinpos; 6937 u_int wrap_qinpos; 6938 u_int wrap_qinfifonext; 6939 6940 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 6941 qinpos = ahd_get_snscb_qoff(ahd); 6942 wrap_qinpos = AHD_QIN_WRAP(qinpos); 6943 wrap_qinfifonext = AHD_QIN_WRAP(ahd->qinfifonext); 6944 if (wrap_qinfifonext >= wrap_qinpos) 6945 return (wrap_qinfifonext - wrap_qinpos); 6946 else 6947 return (wrap_qinfifonext 6948 + NUM_ELEMENTS(ahd->qinfifo) - wrap_qinpos); 6949 } 6950 6951 void 6952 ahd_reset_cmds_pending(struct ahd_softc *ahd) 6953 { 6954 struct scb *scb; 6955 ahd_mode_state saved_modes; 6956 u_int pending_cmds; 6957 6958 saved_modes = ahd_save_modes(ahd); 6959 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6960 6961 /* 6962 * Don't count any commands as outstanding that the 6963 * sequencer has already marked for completion. 6964 */ 6965 ahd_flush_qoutfifo(ahd); 6966 6967 pending_cmds = 0; 6968 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 6969 pending_cmds++; 6970 } 6971 ahd_outw(ahd, CMDS_PENDING, pending_cmds - ahd_qinfifo_count(ahd)); 6972 ahd_restore_modes(ahd, saved_modes); 6973 ahd->flags &= ~AHD_UPDATE_PEND_CMDS; 6974 } 6975 6976 int 6977 ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel, 6978 int lun, u_int tag, role_t role, uint32_t status, 6979 ahd_search_action action) 6980 { 6981 struct scb *scb; 6982 struct scb *prev_scb; 6983 ahd_mode_state saved_modes; 6984 u_int qinstart; 6985 u_int qinpos; 6986 u_int qintail; 6987 u_int tid_next; 6988 u_int tid_prev; 6989 u_int scbid; 6990 u_int savedscbptr; 6991 uint32_t busaddr; 6992 int found; 6993 int targets; 6994 6995 /* Must be in CCHAN mode */ 6996 saved_modes = ahd_save_modes(ahd); 6997 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6998 6999 /* 7000 * Halt any pending SCB DMA. The sequencer will reinitiate 7001 * this dma if the qinfifo is not empty once we unpause. 7002 */ 7003 if ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN|CCSCBDIR)) 7004 == (CCARREN|CCSCBEN|CCSCBDIR)) { 7005 ahd_outb(ahd, CCSCBCTL, 7006 ahd_inb(ahd, CCSCBCTL) & ~(CCARREN|CCSCBEN)); 7007 while ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0) 7008 ; 7009 } 7010 /* Determine sequencer's position in the qinfifo. */ 7011 qintail = AHD_QIN_WRAP(ahd->qinfifonext); 7012 qinstart = ahd_get_snscb_qoff(ahd); 7013 qinpos = AHD_QIN_WRAP(qinstart); 7014 found = 0; 7015 prev_scb = NULL; 7016 7017 if (action == SEARCH_PRINT) { 7018 printf("qinstart = %d qinfifonext = %d\nQINFIFO:", 7019 qinstart, ahd->qinfifonext); 7020 } 7021 7022 /* 7023 * Start with an empty queue. Entries that are not chosen 7024 * for removal will be re-added to the queue as we go. 7025 */ 7026 ahd->qinfifonext = qinstart; 7027 busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr); 7028 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); 7029 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); 7030 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); 7031 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); 7032 7033 while (qinpos != qintail) { 7034 scb = ahd_lookup_scb(ahd, ahd->qinfifo[qinpos]); 7035 if (scb == NULL) { 7036 printf("qinpos = %d, SCB index = %d\n", 7037 qinpos, ahd->qinfifo[qinpos]); 7038 panic("Loop 1\n"); 7039 } 7040 7041 if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) { 7042 /* 7043 * We found an scb that needs to be acted on. 7044 */ 7045 found++; 7046 switch (action) { 7047 case SEARCH_COMPLETE: 7048 { 7049 cam_status ostat; 7050 cam_status cstat; 7051 7052 ostat = ahd_get_transaction_status(scb); 7053 if (ostat == CAM_REQ_INPROG) 7054 ahd_set_transaction_status(scb, 7055 status); 7056 cstat = ahd_get_transaction_status(scb); 7057 if (cstat != CAM_REQ_CMP) 7058 ahd_freeze_scb(scb); 7059 if ((scb->flags & SCB_ACTIVE) == 0) 7060 printf("Inactive SCB in qinfifo\n"); 7061 ahd_done(ahd, scb); 7062 7063 /* FALLTHROUGH */ 7064 } 7065 case SEARCH_REMOVE: 7066 break; 7067 case SEARCH_PRINT: 7068 printf(" 0x%x", ahd->qinfifo[qinpos]); 7069 /* FALLTHROUGH */ 7070 case SEARCH_COUNT: 7071 ahd_qinfifo_requeue(ahd, prev_scb, scb); 7072 prev_scb = scb; 7073 break; 7074 } 7075 } else { 7076 ahd_qinfifo_requeue(ahd, prev_scb, scb); 7077 prev_scb = scb; 7078 } 7079 qinpos = AHD_QIN_WRAP(qinpos+1); 7080 } 7081 7082 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 7083 7084 if (action == SEARCH_PRINT) 7085 printf("\nWAITING_TID_QUEUES:\n"); 7086 7087 /* 7088 * Search waiting for selection lists. We traverse the 7089 * list of "their ids" waiting for selection and, if 7090 * appropriate, traverse the SCBs of each "their id" 7091 * looking for matches. 7092 */ 7093 savedscbptr = ahd_get_scbptr(ahd); 7094 tid_next = ahd_inw(ahd, WAITING_TID_HEAD); 7095 tid_prev = SCB_LIST_NULL; 7096 targets = 0; 7097 for (scbid = tid_next; !SCBID_IS_NULL(scbid); scbid = tid_next) { 7098 u_int tid_head; 7099 7100 /* 7101 * We limit based on the number of SCBs since 7102 * MK_MESSAGE SCBs are not in the per-tid lists. 7103 */ 7104 targets++; 7105 if (targets > AHD_SCB_MAX) { 7106 panic("TID LIST LOOP"); 7107 } 7108 if (scbid >= ahd->scb_data.numscbs) { 7109 printf("%s: Waiting TID List inconsistency. " 7110 "SCB index == 0x%x, yet numscbs == 0x%x.", 7111 ahd_name(ahd), scbid, ahd->scb_data.numscbs); 7112 ahd_dump_card_state(ahd); 7113 panic("for safety"); 7114 } 7115 scb = ahd_lookup_scb(ahd, scbid); 7116 if (scb == NULL) { 7117 printf("%s: SCB = 0x%x Not Active!\n", 7118 ahd_name(ahd), scbid); 7119 panic("Waiting TID List traversal\n"); 7120 } 7121 ahd_set_scbptr(ahd, scbid); 7122 tid_next = ahd_inw_scbram(ahd, SCB_NEXT2); 7123 if (ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD, 7124 SCB_LIST_NULL, ROLE_UNKNOWN) == 0) { 7125 tid_prev = scbid; 7126 continue; 7127 } 7128 7129 /* 7130 * We found a list of scbs that needs to be searched. 7131 */ 7132 if (action == SEARCH_PRINT) 7133 printf(" %d ( ", SCB_GET_TARGET(ahd, scb)); 7134 tid_head = scbid; 7135 found += ahd_search_scb_list(ahd, target, channel, 7136 lun, tag, role, status, 7137 action, &tid_head, 7138 SCB_GET_TARGET(ahd, scb)); 7139 if (tid_head != scbid) 7140 ahd_stitch_tid_list(ahd, tid_prev, tid_head, tid_next); 7141 if (!SCBID_IS_NULL(tid_head)) 7142 tid_prev = tid_head; 7143 if (action == SEARCH_PRINT) 7144 printf(")\n"); 7145 } 7146 ahd_set_scbptr(ahd, savedscbptr); 7147 ahd_restore_modes(ahd, saved_modes); 7148 return (found); 7149 } 7150 7151 static int 7152 ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel, 7153 int lun, u_int tag, role_t role, uint32_t status, 7154 ahd_search_action action, u_int *list_head, u_int tid) 7155 { 7156 struct scb *scb; 7157 u_int scbid; 7158 u_int next; 7159 u_int prev; 7160 int found; 7161 7162 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7163 found = 0; 7164 prev = SCB_LIST_NULL; 7165 next = *list_head; 7166 for (scbid = next; !SCBID_IS_NULL(scbid); scbid = next) { 7167 if (scbid >= ahd->scb_data.numscbs) { 7168 printf("%s:SCB List inconsistency. " 7169 "SCB == 0x%x, yet numscbs == 0x%x.", 7170 ahd_name(ahd), scbid, ahd->scb_data.numscbs); 7171 ahd_dump_card_state(ahd); 7172 panic("for safety"); 7173 } 7174 scb = ahd_lookup_scb(ahd, scbid); 7175 if (scb == NULL) { 7176 printf("%s: SCB = %d Not Active!\n", 7177 ahd_name(ahd), scbid); 7178 panic("Waiting List traversal\n"); 7179 } 7180 ahd_set_scbptr(ahd, scbid); 7181 next = ahd_inw_scbram(ahd, SCB_NEXT); 7182 if (ahd_match_scb(ahd, scb, target, channel, 7183 lun, SCB_LIST_NULL, role) == 0) { 7184 prev = scbid; 7185 continue; 7186 } 7187 found++; 7188 switch (action) { 7189 case SEARCH_COMPLETE: 7190 { 7191 cam_status ostat; 7192 cam_status cstat; 7193 7194 ostat = ahd_get_transaction_status(scb); 7195 if (ostat == CAM_REQ_INPROG) 7196 ahd_set_transaction_status(scb, status); 7197 cstat = ahd_get_transaction_status(scb); 7198 if (cstat != CAM_REQ_CMP) 7199 ahd_freeze_scb(scb); 7200 if ((scb->flags & SCB_ACTIVE) == 0) 7201 printf("Inactive SCB in Waiting List\n"); 7202 ahd_done(ahd, scb); 7203 /* FALLTHROUGH */ 7204 } 7205 case SEARCH_REMOVE: 7206 ahd_rem_wscb(ahd, scbid, prev, next, tid); 7207 if (prev == SCB_LIST_NULL) 7208 *list_head = next; 7209 break; 7210 case SEARCH_PRINT: 7211 printf("0x%x ", scbid); 7212 case SEARCH_COUNT: 7213 prev = scbid; 7214 break; 7215 } 7216 if (found > AHD_SCB_MAX) 7217 panic("SCB LIST LOOP"); 7218 } 7219 if (action == SEARCH_COMPLETE 7220 || action == SEARCH_REMOVE) 7221 ahd_outw(ahd, CMDS_PENDING, ahd_inw(ahd, CMDS_PENDING) - found); 7222 return (found); 7223 } 7224 7225 static void 7226 ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev, 7227 u_int tid_cur, u_int tid_next) 7228 { 7229 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7230 7231 if (SCBID_IS_NULL(tid_cur)) { 7232 7233 /* Bypass current TID list */ 7234 if (SCBID_IS_NULL(tid_prev)) { 7235 ahd_outw(ahd, WAITING_TID_HEAD, tid_next); 7236 } else { 7237 ahd_set_scbptr(ahd, tid_prev); 7238 ahd_outw(ahd, SCB_NEXT2, tid_next); 7239 } 7240 if (SCBID_IS_NULL(tid_next)) 7241 ahd_outw(ahd, WAITING_TID_TAIL, tid_prev); 7242 } else { 7243 7244 /* Stitch through tid_cur */ 7245 if (SCBID_IS_NULL(tid_prev)) { 7246 ahd_outw(ahd, WAITING_TID_HEAD, tid_cur); 7247 } else { 7248 ahd_set_scbptr(ahd, tid_prev); 7249 ahd_outw(ahd, SCB_NEXT2, tid_cur); 7250 } 7251 ahd_set_scbptr(ahd, tid_cur); 7252 ahd_outw(ahd, SCB_NEXT2, tid_next); 7253 7254 if (SCBID_IS_NULL(tid_next)) 7255 ahd_outw(ahd, WAITING_TID_TAIL, tid_cur); 7256 } 7257 } 7258 7259 /* 7260 * Manipulate the waiting for selection list and return the 7261 * scb that follows the one that we remove. 7262 */ 7263 static u_int 7264 ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, 7265 u_int prev, u_int next, u_int tid) 7266 { 7267 u_int tail_offset; 7268 7269 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7270 if (!SCBID_IS_NULL(prev)) { 7271 ahd_set_scbptr(ahd, prev); 7272 ahd_outw(ahd, SCB_NEXT, next); 7273 } 7274 7275 /* 7276 * SCBs that had MK_MESSAGE set in them will not 7277 * be queued to the per-target lists, so don't 7278 * blindly clear the tail pointer. 7279 */ 7280 tail_offset = WAITING_SCB_TAILS + (2 * tid); 7281 if (SCBID_IS_NULL(next) 7282 && ahd_inw(ahd, tail_offset) == scbid) 7283 ahd_outw(ahd, tail_offset, prev); 7284 ahd_add_scb_to_free_list(ahd, scbid); 7285 return (next); 7286 } 7287 7288 /* 7289 * Add the SCB as selected by SCBPTR onto the on chip list of 7290 * free hardware SCBs. This list is empty/unused if we are not 7291 * performing SCB paging. 7292 */ 7293 static void 7294 ahd_add_scb_to_free_list(struct ahd_softc *ahd, u_int scbid) 7295 { 7296 /* XXX Need some other mechanism to designate "free". */ 7297 /* 7298 * Invalidate the tag so that our abort 7299 * routines don't think it's active. 7300 ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL); 7301 */ 7302 } 7303 7304 /******************************** Error Handling ******************************/ 7305 /* 7306 * Abort all SCBs that match the given description (target/channel/lun/tag), 7307 * setting their status to the passed in status if the status has not already 7308 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 7309 * is paused before it is called. 7310 */ 7311 int 7312 ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel, 7313 int lun, u_int tag, role_t role, uint32_t status) 7314 { 7315 struct scb *scbp; 7316 struct scb *scbp_next; 7317 u_int active_scb; 7318 u_int i, j; 7319 u_int maxtarget; 7320 u_int minlun; 7321 u_int maxlun; 7322 int found; 7323 ahd_mode_state saved_modes; 7324 7325 /* restore these when we're done */ 7326 active_scb = ahd_get_scbptr(ahd); 7327 saved_modes = ahd_save_modes(ahd); 7328 7329 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7330 found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL, 7331 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 7332 7333 /* 7334 * Clean out the busy target table for any untagged commands. 7335 */ 7336 i = 0; 7337 maxtarget = 16; 7338 if (target != CAM_TARGET_WILDCARD) { 7339 i = target; 7340 if (channel == 'B') 7341 i += 8; 7342 maxtarget = i + 1; 7343 } 7344 7345 if (lun == CAM_LUN_WILDCARD) { 7346 minlun = 0; 7347 maxlun = AHD_NUM_LUNS_NONPKT; 7348 } else if (lun >= AHD_NUM_LUNS_NONPKT) { 7349 minlun = maxlun = 0; 7350 } else { 7351 minlun = lun; 7352 maxlun = lun + 1; 7353 } 7354 7355 if (role != ROLE_TARGET) { 7356 for (;i < maxtarget; i++) { 7357 for (j = minlun;j < maxlun; j++) { 7358 u_int scbid; 7359 u_int tcl; 7360 7361 tcl = BUILD_TCL_RAW(i, 'A', j); 7362 scbid = ahd_find_busy_tcl(ahd, tcl); 7363 scbp = ahd_lookup_scb(ahd, scbid); 7364 if (scbp == NULL 7365 || ahd_match_scb(ahd, scbp, target, channel, 7366 lun, tag, role) == 0) 7367 continue; 7368 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(i, 'A', j)); 7369 } 7370 } 7371 } 7372 7373 /* 7374 * Don't abort commands that have already completed, 7375 * but haven't quite made it up to the host yet. 7376 */ 7377 ahd_flush_qoutfifo(ahd); 7378 7379 /* 7380 * Go through the pending CCB list and look for 7381 * commands for this target that are still active. 7382 * These are other tagged commands that were 7383 * disconnected when the reset occurred. 7384 */ 7385 scbp_next = LIST_FIRST(&ahd->pending_scbs); 7386 while (scbp_next != NULL) { 7387 scbp = scbp_next; 7388 scbp_next = LIST_NEXT(scbp, pending_links); 7389 if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) { 7390 cam_status ostat; 7391 7392 ostat = ahd_get_transaction_status(scbp); 7393 if (ostat == CAM_REQ_INPROG) 7394 ahd_set_transaction_status(scbp, status); 7395 if (ahd_get_transaction_status(scbp) != CAM_REQ_CMP) 7396 ahd_freeze_scb(scbp); 7397 if ((scbp->flags & SCB_ACTIVE) == 0) 7398 printf("Inactive SCB on pending list\n"); 7399 ahd_done(ahd, scbp); 7400 found++; 7401 } 7402 } 7403 ahd_set_scbptr(ahd, active_scb); 7404 ahd_restore_modes(ahd, saved_modes); 7405 ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status); 7406 ahd->flags |= AHD_UPDATE_PEND_CMDS; 7407 return found; 7408 } 7409 7410 static void 7411 ahd_reset_current_bus(struct ahd_softc *ahd) 7412 { 7413 uint8_t scsiseq; 7414 7415 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7416 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENSCSIRST); 7417 scsiseq = ahd_inb(ahd, SCSISEQ0) & ~(ENSELO|ENARBO|SCSIRSTO); 7418 ahd_outb(ahd, SCSISEQ0, scsiseq | SCSIRSTO); 7419 ahd_delay(AHD_BUSRESET_DELAY); 7420 /* Turn off the bus reset */ 7421 ahd_outb(ahd, SCSISEQ0, scsiseq); 7422 if ((ahd->bugs & AHD_SCSIRST_BUG) != 0) { 7423 /* 7424 * 2A Razor #474 7425 * Certain chip state is not cleared for 7426 * SCSI bus resets that we initiate, so 7427 * we must reset the chip. 7428 */ 7429 ahd_delay(AHD_BUSRESET_DELAY); 7430 ahd_reset(ahd); 7431 ahd_intr_enable(ahd, /*enable*/TRUE); 7432 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7433 } 7434 7435 ahd_clear_intstat(ahd); 7436 } 7437 7438 int 7439 ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset) 7440 { 7441 struct ahd_devinfo devinfo; 7442 u_int initiator; 7443 u_int target; 7444 u_int max_scsiid; 7445 int found; 7446 u_int fifo; 7447 u_int next_fifo; 7448 7449 ahd->pending_device = NULL; 7450 7451 ahd_compile_devinfo(&devinfo, 7452 CAM_TARGET_WILDCARD, 7453 CAM_TARGET_WILDCARD, 7454 CAM_LUN_WILDCARD, 7455 channel, ROLE_UNKNOWN); 7456 ahd_pause(ahd); 7457 7458 /* Make sure the sequencer is in a safe location. */ 7459 ahd_clear_critical_section(ahd); 7460 7461 #if AHD_TARGET_MODE 7462 if ((ahd->flags & AHD_TARGETROLE) != 0) { 7463 ahd_run_tqinfifo(ahd, /*paused*/TRUE); 7464 } 7465 #endif 7466 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7467 7468 /* 7469 * Disable selections so no automatic hardware 7470 * functions will modify chip state. 7471 */ 7472 ahd_outb(ahd, SCSISEQ0, 0); 7473 ahd_outb(ahd, SCSISEQ1, 0); 7474 7475 /* 7476 * Safely shut down our DMA engines. Always start with 7477 * the FIFO that is not currently active (if any are 7478 * actively connected). 7479 */ 7480 next_fifo = fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; 7481 if (next_fifo > CURRFIFO_1) 7482 /* If disconneced, arbitrarily start with FIFO1. */ 7483 next_fifo = fifo = 0; 7484 do { 7485 next_fifo ^= CURRFIFO_1; 7486 ahd_set_modes(ahd, next_fifo, next_fifo); 7487 ahd_outb(ahd, DFCNTRL, 7488 ahd_inb(ahd, DFCNTRL) & ~(SCSIEN|HDMAEN)); 7489 while ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) 7490 ahd_delay(10); 7491 /* 7492 * Set CURRFIFO to the now inactive channel. 7493 */ 7494 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7495 ahd_outb(ahd, DFFSTAT, next_fifo); 7496 } while (next_fifo != fifo); 7497 /* 7498 * Reset the bus if we are initiating this reset 7499 */ 7500 ahd_clear_msg_state(ahd); 7501 ahd_outb(ahd, SIMODE1, 7502 ahd_inb(ahd, SIMODE1) & ~(ENBUSFREE|ENSCSIRST|ENBUSFREE)); 7503 if (initiate_reset) 7504 ahd_reset_current_bus(ahd); 7505 ahd_clear_intstat(ahd); 7506 7507 /* 7508 * Clean up all the state information for the 7509 * pending transactions on this bus. 7510 */ 7511 found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel, 7512 CAM_LUN_WILDCARD, SCB_LIST_NULL, 7513 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 7514 7515 /* 7516 * Cleanup anything left in the FIFOs. 7517 */ 7518 ahd_clear_fifo(ahd, 0); 7519 ahd_clear_fifo(ahd, 1); 7520 7521 /* 7522 * Revert to async/narrow transfers until we renegotiate. 7523 */ 7524 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7; 7525 for (target = 0; target <= max_scsiid; target++) { 7526 7527 if (ahd->enabled_targets[target] == NULL) 7528 continue; 7529 for (initiator = 0; initiator <= max_scsiid; initiator++) { 7530 struct ahd_devinfo devinfo; 7531 7532 ahd_compile_devinfo(&devinfo, target, initiator, 7533 CAM_LUN_WILDCARD, 7534 'A', ROLE_UNKNOWN); 7535 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 7536 AHD_TRANS_CUR, /*paused*/TRUE); 7537 ahd_set_syncrate(ahd, &devinfo, /*period*/0, 7538 /*offset*/0, /*ppr_options*/0, 7539 AHD_TRANS_CUR, /*paused*/TRUE); 7540 } 7541 } 7542 7543 #ifdef AHD_TARGET_MODE 7544 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7; 7545 7546 /* 7547 * Send an immediate notify ccb to all target more peripheral 7548 * drivers affected by this action. 7549 */ 7550 for (target = 0; target <= max_scsiid; target++) { 7551 struct ahd_tmode_tstate* tstate; 7552 u_int lun; 7553 7554 tstate = ahd->enabled_targets[target]; 7555 if (tstate == NULL) 7556 continue; 7557 for (lun = 0; lun < AHD_NUM_LUNS; lun++) { 7558 struct ahd_tmode_lstate* lstate; 7559 7560 lstate = tstate->enabled_luns[lun]; 7561 if (lstate == NULL) 7562 continue; 7563 7564 ahd_queue_lstate_event(ahd, lstate, CAM_TARGET_WILDCARD, 7565 EVENT_TYPE_BUS_RESET, /*arg*/0); 7566 ahd_send_lstate_events(ahd, lstate); 7567 } 7568 } 7569 #endif 7570 /* Notify the XPT that a bus reset occurred */ 7571 ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD, 7572 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL); 7573 ahd_restart(ahd); 7574 /* 7575 * Freeze the SIMQ until our poller can determine that 7576 * the bus reset has really gone away. We set the initial 7577 * timer to 0 to have the check performed as soon as possible 7578 * from the timer context. 7579 */ 7580 if ((ahd->flags & AHD_RESET_POLL_ACTIVE) == 0) { 7581 ahd->flags |= AHD_RESET_POLL_ACTIVE; 7582 ahd_freeze_simq(ahd); 7583 ahd_timer_reset(&ahd->reset_timer, 0, ahd_reset_poll, ahd); 7584 } 7585 return (found); 7586 } 7587 7588 7589 #define AHD_RESET_POLL_US 1000 7590 static void 7591 ahd_reset_poll(void *arg) 7592 { 7593 struct ahd_softc *ahd; 7594 u_int scsiseq1; 7595 u_long l; 7596 u_long s; 7597 7598 ahd_list_lock(&l); 7599 ahd = ahd_find_softc((struct ahd_softc *)arg); 7600 if (ahd == NULL) { 7601 printf("ahd_reset_poll: Instance %p no longer exists\n", arg); 7602 ahd_list_unlock(&l); 7603 return; 7604 } 7605 ahd_lock(ahd, &s); 7606 ahd_pause(ahd); 7607 ahd_update_modes(ahd); 7608 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7609 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); 7610 if ((ahd_inb(ahd, SSTAT1) & SCSIRSTI) != 0) { 7611 ahd_timer_reset(&ahd->reset_timer, AHD_RESET_POLL_US, 7612 ahd_reset_poll, ahd); 7613 ahd_unpause(ahd); 7614 ahd_unlock(ahd, &s); 7615 ahd_list_unlock(&l); 7616 return; 7617 } 7618 7619 /* Reset is now low. Complete chip reinitialization. */ 7620 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST); 7621 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 7622 ahd_outb(ahd, SCSISEQ1, scsiseq1 & (ENSELI|ENRSELI|ENAUTOATNP)); 7623 ahd_unpause(ahd); 7624 ahd->flags &= ~AHD_RESET_POLL_ACTIVE; 7625 ahd_unlock(ahd, &s); 7626 ahd_release_simq(ahd); 7627 ahd_list_unlock(&l); 7628 } 7629 7630 /**************************** Statistics Processing ***************************/ 7631 static void 7632 ahd_stat_timer(void *arg) 7633 { 7634 struct ahd_softc *ahd; 7635 u_long l; 7636 u_long s; 7637 int enint_coal; 7638 7639 ahd_list_lock(&l); 7640 ahd = ahd_find_softc((struct ahd_softc *)arg); 7641 if (ahd == NULL) { 7642 printf("ahd_stat_timer: Instance %p no longer exists\n", arg); 7643 ahd_list_unlock(&l); 7644 return; 7645 } 7646 ahd_lock(ahd, &s); 7647 7648 enint_coal = ahd->hs_mailbox & ENINT_COALESS; 7649 if (ahd->cmdcmplt_total > ahd->int_coalessing_threshold) 7650 enint_coal |= ENINT_COALESS; 7651 else if (ahd->cmdcmplt_total < ahd->int_coalessing_stop_threshold) 7652 enint_coal &= ~ENINT_COALESS; 7653 7654 if (enint_coal != (ahd->hs_mailbox & ENINT_COALESS)) { 7655 ahd_enable_coalessing(ahd, enint_coal); 7656 #ifdef AHD_DEBUG 7657 if ((ahd_debug & AHD_SHOW_INT_COALESSING) != 0) 7658 printf("%s: Interrupt coalessing " 7659 "now %sabled. Cmds %d\n", 7660 ahd_name(ahd), 7661 (enint_coal & ENINT_COALESS) ? "en" : "dis", 7662 ahd->cmdcmplt_total); 7663 #endif 7664 } 7665 7666 ahd->cmdcmplt_bucket = (ahd->cmdcmplt_bucket+1) & (AHD_STAT_BUCKETS-1); 7667 ahd->cmdcmplt_total -= ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket]; 7668 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket] = 0; 7669 ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US, 7670 ahd_stat_timer, ahd); 7671 ahd_unlock(ahd, &s); 7672 ahd_list_unlock(&l); 7673 } 7674 7675 /****************************** Status Processing *****************************/ 7676 void 7677 ahd_handle_scb_status(struct ahd_softc *ahd, struct scb *scb) 7678 { 7679 if (scb->hscb->shared_data.istatus.scsi_status != 0) { 7680 ahd_handle_scsi_status(ahd, scb); 7681 } else { 7682 ahd_calc_residual(ahd, scb); 7683 ahd_done(ahd, scb); 7684 } 7685 } 7686 7687 void 7688 ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb) 7689 { 7690 struct hardware_scb *hscb; 7691 u_int qfreeze_cnt; 7692 ahd_mode_state saved_modes; 7693 7694 /* 7695 * The sequencer freezes its select-out queue 7696 * anytime a SCSI status error occurs. We must 7697 * handle the error and decrement the QFREEZE count 7698 * to allow the sequencer to continue. 7699 */ 7700 hscb = scb->hscb; 7701 7702 /* Freeze the queue until the client sees the error. */ 7703 ahd_pause(ahd); 7704 saved_modes = ahd_save_modes(ahd); 7705 ahd_clear_critical_section(ahd); 7706 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7707 ahd_freeze_devq(ahd, scb); 7708 ahd_freeze_scb(scb); 7709 qfreeze_cnt = ahd_inw(ahd, QFREEZE_COUNT); 7710 if (qfreeze_cnt == 0) { 7711 printf("%s: Bad status with 0 qfreeze count!\n", ahd_name(ahd)); 7712 } else { 7713 qfreeze_cnt--; 7714 ahd_outw(ahd, QFREEZE_COUNT, qfreeze_cnt); 7715 } 7716 if (qfreeze_cnt == 0) 7717 ahd_outb(ahd, SEQ_FLAGS2, 7718 ahd_inb(ahd, SEQ_FLAGS2) & ~SELECTOUT_QFROZEN); 7719 ahd_unpause(ahd); 7720 /* Don't want to clobber the original sense code */ 7721 if ((scb->flags & SCB_SENSE) != 0) { 7722 /* 7723 * Clear the SCB_SENSE Flag and perform 7724 * a normal command completion. 7725 */ 7726 scb->flags &= ~SCB_SENSE; 7727 ahd_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 7728 ahd_done(ahd, scb); 7729 return; 7730 } 7731 ahd_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR); 7732 ahd_set_scsi_status(scb, hscb->shared_data.istatus.scsi_status); 7733 switch (hscb->shared_data.istatus.scsi_status) { 7734 case STATUS_PKT_SENSE: 7735 { 7736 struct scsi_status_iu_header *siu; 7737 7738 ahd_sync_sense(ahd, scb, BUS_DMASYNC_POSTREAD); 7739 siu = (struct scsi_status_iu_header *)scb->sense_data; 7740 ahd_set_scsi_status(scb, siu->status); 7741 #ifdef AHD_DEBUG 7742 if ((ahd_debug & AHD_SHOW_SENSE) != 0) { 7743 ahd_print_path(ahd, scb); 7744 printf("SCB 0x%x Received PKT Status of 0x%x\n", 7745 SCB_GET_TAG(scb), siu->status); 7746 printf("\tflags = 0x%x, sense len = 0x%x, " 7747 "pktfail = 0x%x\n", 7748 siu->flags, scsi_4btoul(siu->sense_length), 7749 scsi_4btoul(siu->pkt_failures_length)); 7750 } 7751 #endif 7752 if ((siu->flags & SIU_RSPVALID) != 0) { 7753 ahd_print_path(ahd, scb); 7754 if (scsi_4btoul(siu->pkt_failures_length) < 4) { 7755 printf("Unable to parse pkt_failures\n"); 7756 } else { 7757 7758 switch (SIU_PKTFAIL_CODE(siu)) { 7759 case SIU_PFC_NONE: 7760 printf("No packet failure found\n"); 7761 break; 7762 case SIU_PFC_CIU_FIELDS_INVALID: 7763 printf("Invalid Command IU Field\n"); 7764 break; 7765 case SIU_PFC_TMF_NOT_SUPPORTED: 7766 printf("TMF not supportd\n"); 7767 break; 7768 case SIU_PFC_TMF_FAILED: 7769 printf("TMF failed\n"); 7770 break; 7771 case SIU_PFC_INVALID_TYPE_CODE: 7772 printf("Invalid L_Q Type code\n"); 7773 break; 7774 case SIU_PFC_ILLEGAL_REQUEST: 7775 printf("Illegal request\n"); 7776 default: 7777 break; 7778 } 7779 } 7780 if (siu->status == SCSI_STATUS_OK) 7781 ahd_set_transaction_status(scb, 7782 CAM_REQ_CMP_ERR); 7783 } 7784 if ((siu->flags & SIU_SNSVALID) != 0) { 7785 scb->flags |= SCB_PKT_SENSE; 7786 #ifdef AHD_DEBUG 7787 if ((ahd_debug & AHD_SHOW_SENSE) != 0) 7788 printf("Sense data available\n"); 7789 #endif 7790 } 7791 ahd_done(ahd, scb); 7792 break; 7793 } 7794 case SCSI_STATUS_CMD_TERMINATED: 7795 case SCSI_STATUS_CHECK_COND: 7796 { 7797 struct ahd_devinfo devinfo; 7798 struct ahd_dma_seg *sg; 7799 struct scsi_sense *sc; 7800 struct ahd_initiator_tinfo *targ_info; 7801 struct ahd_tmode_tstate *tstate; 7802 struct ahd_transinfo *tinfo; 7803 #ifdef AHD_DEBUG 7804 if (ahd_debug & AHD_SHOW_SENSE) { 7805 ahd_print_path(ahd, scb); 7806 printf("SCB %d: requests Check Status\n", 7807 SCB_GET_TAG(scb)); 7808 } 7809 #endif 7810 7811 if (ahd_perform_autosense(scb) == 0) 7812 break; 7813 7814 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), 7815 SCB_GET_TARGET(ahd, scb), 7816 SCB_GET_LUN(scb), 7817 SCB_GET_CHANNEL(ahd, scb), 7818 ROLE_INITIATOR); 7819 targ_info = ahd_fetch_transinfo(ahd, 7820 devinfo.channel, 7821 devinfo.our_scsiid, 7822 devinfo.target, 7823 &tstate); 7824 tinfo = &targ_info->curr; 7825 sg = scb->sg_list; 7826 sc = (struct scsi_sense *)hscb->shared_data.idata.cdb; 7827 /* 7828 * Save off the residual if there is one. 7829 */ 7830 ahd_update_residual(ahd, scb); 7831 #ifdef AHD_DEBUG 7832 if (ahd_debug & AHD_SHOW_SENSE) { 7833 ahd_print_path(ahd, scb); 7834 printf("Sending Sense\n"); 7835 } 7836 #endif 7837 scb->sg_count = 0; 7838 sg = ahd_sg_setup(ahd, scb, sg, ahd_get_sense_bufaddr(ahd, scb), 7839 ahd_get_sense_bufsize(ahd, scb), 7840 /*last*/TRUE); 7841 sc->opcode = REQUEST_SENSE; 7842 sc->byte2 = 0; 7843 if (tinfo->protocol_version <= SCSI_REV_2 7844 && SCB_GET_LUN(scb) < 8) 7845 sc->byte2 = SCB_GET_LUN(scb) << 5; 7846 sc->unused[0] = 0; 7847 sc->unused[1] = 0; 7848 sc->length = ahd_get_sense_bufsize(ahd, scb); 7849 sc->control = 0; 7850 7851 /* 7852 * We can't allow the target to disconnect. 7853 * This will be an untagged transaction and 7854 * having the target disconnect will make this 7855 * transaction indestinguishable from outstanding 7856 * tagged transactions. 7857 */ 7858 hscb->control = 0; 7859 7860 /* 7861 * This request sense could be because the 7862 * the device lost power or in some other 7863 * way has lost our transfer negotiations. 7864 * Renegotiate if appropriate. Unit attention 7865 * errors will be reported before any data 7866 * phases occur. 7867 */ 7868 if (ahd_get_residual(scb) == ahd_get_transfer_length(scb)) { 7869 ahd_update_neg_request(ahd, &devinfo, 7870 tstate, targ_info, 7871 AHD_NEG_IF_NON_ASYNC); 7872 } 7873 if (tstate->auto_negotiate & devinfo.target_mask) { 7874 hscb->control |= MK_MESSAGE; 7875 scb->flags &= 7876 ~(SCB_NEGOTIATE|SCB_ABORT|SCB_DEVICE_RESET); 7877 scb->flags |= SCB_AUTO_NEGOTIATE; 7878 } 7879 hscb->cdb_len = sizeof(*sc); 7880 ahd_setup_data_scb(ahd, scb); 7881 scb->flags |= SCB_SENSE; 7882 ahd_queue_scb(ahd, scb); 7883 /* 7884 * Ensure we have enough time to actually 7885 * retrieve the sense. 7886 */ 7887 ahd_scb_timer_reset(scb, 5 * 1000000); 7888 break; 7889 } 7890 case SCSI_STATUS_OK: 7891 printf("%s: Interrupted for staus of 0???\n", 7892 ahd_name(ahd)); 7893 /* FALLTHROUGH */ 7894 default: 7895 ahd_done(ahd, scb); 7896 break; 7897 } 7898 } 7899 7900 /* 7901 * Calculate the residual for a just completed SCB. 7902 */ 7903 void 7904 ahd_calc_residual(struct ahd_softc *ahd, struct scb *scb) 7905 { 7906 struct hardware_scb *hscb; 7907 struct initiator_status *spkt; 7908 uint32_t sgptr; 7909 uint32_t resid_sgptr; 7910 uint32_t resid; 7911 7912 /* 7913 * 5 cases. 7914 * 1) No residual. 7915 * SG_STATUS_VALID clear in sgptr. 7916 * 2) Transferless command 7917 * 3) Never performed any transfers. 7918 * sgptr has SG_FULL_RESID set. 7919 * 4) No residual but target did not 7920 * save data pointers after the 7921 * last transfer, so sgptr was 7922 * never updated. 7923 * 5) We have a partial residual. 7924 * Use residual_sgptr to determine 7925 * where we are. 7926 */ 7927 7928 hscb = scb->hscb; 7929 sgptr = ahd_le32toh(hscb->sgptr); 7930 if ((sgptr & SG_STATUS_VALID) == 0) 7931 /* Case 1 */ 7932 return; 7933 sgptr &= ~SG_STATUS_VALID; 7934 7935 if ((sgptr & SG_LIST_NULL) != 0) 7936 /* Case 2 */ 7937 return; 7938 7939 /* 7940 * Residual fields are the same in both 7941 * target and initiator status packets, 7942 * so we can always use the initiator fields 7943 * regardless of the role for this SCB. 7944 */ 7945 spkt = &hscb->shared_data.istatus; 7946 resid_sgptr = ahd_le32toh(spkt->residual_sgptr); 7947 if ((sgptr & SG_FULL_RESID) != 0) { 7948 /* Case 3 */ 7949 resid = ahd_get_transfer_length(scb); 7950 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 7951 /* Case 4 */ 7952 return; 7953 } else if ((resid_sgptr & SG_OVERRUN_RESID) != 0) { 7954 ahd_print_path(ahd, scb); 7955 printf("data overrun detected Tag == 0x%x.\n", 7956 SCB_GET_TAG(scb)); 7957 ahd_freeze_devq(ahd, scb); 7958 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR); 7959 ahd_freeze_scb(scb); 7960 return; 7961 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 7962 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 7963 /* NOTREACHED */ 7964 } else { 7965 struct ahd_dma_seg *sg; 7966 7967 /* 7968 * Remainder of the SG where the transfer 7969 * stopped. 7970 */ 7971 resid = ahd_le32toh(spkt->residual_datacnt) & AHD_SG_LEN_MASK; 7972 sg = ahd_sg_bus_to_virt(ahd, scb, resid_sgptr & SG_PTR_MASK); 7973 7974 /* The residual sg_ptr always points to the next sg */ 7975 sg--; 7976 7977 /* 7978 * Add up the contents of all residual 7979 * SG segments that are after the SG where 7980 * the transfer stopped. 7981 */ 7982 while ((ahd_le32toh(sg->len) & AHD_DMA_LAST_SEG) == 0) { 7983 sg++; 7984 resid += ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 7985 } 7986 } 7987 if ((scb->flags & SCB_SENSE) == 0) 7988 ahd_set_residual(scb, resid); 7989 else 7990 ahd_set_sense_residual(scb, resid); 7991 7992 #ifdef AHD_DEBUG 7993 if ((ahd_debug & AHD_SHOW_MISC) != 0) { 7994 ahd_print_path(ahd, scb); 7995 printf("Handled %sResidual of %d bytes\n", 7996 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 7997 } 7998 #endif 7999 } 8000 8001 /******************************* Target Mode **********************************/ 8002 #ifdef AHD_TARGET_MODE 8003 /* 8004 * Add a target mode event to this lun's queue 8005 */ 8006 static void 8007 ahd_queue_lstate_event(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate, 8008 u_int initiator_id, u_int event_type, u_int event_arg) 8009 { 8010 struct ahd_tmode_event *event; 8011 int pending; 8012 8013 xpt_freeze_devq(lstate->path, /*count*/1); 8014 if (lstate->event_w_idx >= lstate->event_r_idx) 8015 pending = lstate->event_w_idx - lstate->event_r_idx; 8016 else 8017 pending = AHD_TMODE_EVENT_BUFFER_SIZE + 1 8018 - (lstate->event_r_idx - lstate->event_w_idx); 8019 8020 if (event_type == EVENT_TYPE_BUS_RESET 8021 || event_type == MSG_BUS_DEV_RESET) { 8022 /* 8023 * Any earlier events are irrelevant, so reset our buffer. 8024 * This has the effect of allowing us to deal with reset 8025 * floods (an external device holding down the reset line) 8026 * without losing the event that is really interesting. 8027 */ 8028 lstate->event_r_idx = 0; 8029 lstate->event_w_idx = 0; 8030 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 8031 } 8032 8033 if (pending == AHD_TMODE_EVENT_BUFFER_SIZE) { 8034 xpt_print_path(lstate->path); 8035 printf("immediate event %x:%x lost\n", 8036 lstate->event_buffer[lstate->event_r_idx].event_type, 8037 lstate->event_buffer[lstate->event_r_idx].event_arg); 8038 lstate->event_r_idx++; 8039 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 8040 lstate->event_r_idx = 0; 8041 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 8042 } 8043 8044 event = &lstate->event_buffer[lstate->event_w_idx]; 8045 event->initiator_id = initiator_id; 8046 event->event_type = event_type; 8047 event->event_arg = event_arg; 8048 lstate->event_w_idx++; 8049 if (lstate->event_w_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 8050 lstate->event_w_idx = 0; 8051 } 8052 8053 /* 8054 * Send any target mode events queued up waiting 8055 * for immediate notify resources. 8056 */ 8057 void 8058 ahd_send_lstate_events(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate) 8059 { 8060 struct ccb_hdr *ccbh; 8061 struct ccb_immed_notify *inot; 8062 8063 while (lstate->event_r_idx != lstate->event_w_idx 8064 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 8065 struct ahd_tmode_event *event; 8066 8067 event = &lstate->event_buffer[lstate->event_r_idx]; 8068 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 8069 inot = (struct ccb_immed_notify *)ccbh; 8070 switch (event->event_type) { 8071 case EVENT_TYPE_BUS_RESET: 8072 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 8073 break; 8074 default: 8075 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 8076 inot->message_args[0] = event->event_type; 8077 inot->message_args[1] = event->event_arg; 8078 break; 8079 } 8080 inot->initiator_id = event->initiator_id; 8081 inot->sense_len = 0; 8082 xpt_done((union ccb *)inot); 8083 lstate->event_r_idx++; 8084 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 8085 lstate->event_r_idx = 0; 8086 } 8087 } 8088 #endif 8089 8090 /******************** Sequencer Program Patching/Download *********************/ 8091 8092 #ifdef AHD_DUMP_SEQ 8093 void 8094 ahd_dumpseq(struct ahd_softc* ahd) 8095 { 8096 int i; 8097 int max_prog; 8098 8099 max_prog = 2048; 8100 8101 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 8102 ahd_outb(ahd, PRGMCNT, 0); 8103 ahd_outb(ahd, PRGMCNT+1, 0); 8104 for (i = 0; i < max_prog; i++) { 8105 uint8_t ins_bytes[4]; 8106 8107 ahd_insb(ahd, SEQRAM, ins_bytes, 4); 8108 printf("0x%08x\n", ins_bytes[0] << 24 8109 | ins_bytes[1] << 16 8110 | ins_bytes[2] << 8 8111 | ins_bytes[3]); 8112 } 8113 } 8114 #endif 8115 8116 static void 8117 ahd_loadseq(struct ahd_softc *ahd) 8118 { 8119 struct cs cs_table[num_critical_sections]; 8120 u_int begin_set[num_critical_sections]; 8121 u_int end_set[num_critical_sections]; 8122 struct patch *cur_patch; 8123 u_int cs_count; 8124 u_int cur_cs; 8125 u_int i; 8126 int downloaded; 8127 u_int skip_addr; 8128 u_int sg_prefetch_cnt; 8129 u_int sg_prefetch_cnt_limit; 8130 u_int sg_prefetch_align; 8131 u_int sg_size; 8132 uint8_t download_consts[DOWNLOAD_CONST_COUNT]; 8133 8134 if (bootverbose) 8135 printf("%s: Downloading Sequencer Program...", 8136 ahd_name(ahd)); 8137 8138 #if DOWNLOAD_CONST_COUNT != 7 8139 #error "Download Const Mismatch" 8140 #endif 8141 /* 8142 * Start out with 0 critical sections 8143 * that apply to this firmware load. 8144 */ 8145 cs_count = 0; 8146 cur_cs = 0; 8147 memset(begin_set, 0, sizeof(begin_set)); 8148 memset(end_set, 0, sizeof(end_set)); 8149 8150 /* 8151 * Setup downloadable constant table. 8152 * 8153 * The computation for the S/G prefetch variables is 8154 * a bit complicated. We would like to always fetch 8155 * in terms of cachelined sized increments. However, 8156 * if the cacheline is not an even multiple of the 8157 * SG element size or is larger than our SG RAM, using 8158 * just the cache size might leave us with only a portion 8159 * of an SG element at the tail of a prefetch. If the 8160 * cacheline is larger than our S/G prefetch buffer less 8161 * the size of an SG element, we may round down to a cacheline 8162 * that doesn't contain any or all of the S/G of interest 8163 * within the bounds of our S/G ram. Provide variables to 8164 * the sequencer that will allow it to handle these edge 8165 * cases. 8166 */ 8167 /* Start by aligning to the nearest cacheline. */ 8168 sg_prefetch_align = ahd->pci_cachesize; 8169 if (sg_prefetch_align == 0) 8170 sg_prefetch_align = 8; 8171 /* Round down to the nearest power of 2. */ 8172 while (powerof2(sg_prefetch_align) == 0) 8173 sg_prefetch_align--; 8174 /* 8175 * If the cacheline boundary is greater than half our prefetch RAM 8176 * we risk not being able to fetch even a single complete S/G 8177 * segment if we align to that boundary. 8178 */ 8179 if (sg_prefetch_align > CCSGADDR_MAX/2) 8180 sg_prefetch_align = CCSGADDR_MAX/2; 8181 /* Start by fetching a single cacheline. */ 8182 sg_prefetch_cnt = sg_prefetch_align; 8183 /* 8184 * Increment the prefetch count by cachelines until 8185 * at least one S/G element will fit. 8186 */ 8187 sg_size = sizeof(struct ahd_dma_seg); 8188 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 8189 sg_size = sizeof(struct ahd_dma64_seg); 8190 while (sg_prefetch_cnt < sg_size) 8191 sg_prefetch_cnt += sg_prefetch_align; 8192 /* 8193 * If the cacheline is not an even multiple of 8194 * the S/G size, we may only get a partial S/G when 8195 * we align. Add a cacheline if this is the case. 8196 */ 8197 if ((sg_prefetch_align % sg_size) != 0 8198 && (sg_prefetch_cnt < CCSGADDR_MAX)) 8199 sg_prefetch_cnt += sg_prefetch_align; 8200 /* 8201 * Lastly, compute a value that the sequencer can use 8202 * to determine if the remainder of the CCSGRAM buffer 8203 * has a full S/G element in it. 8204 */ 8205 sg_prefetch_cnt_limit = -(sg_prefetch_cnt - sg_size + 1); 8206 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 8207 download_consts[SG_PREFETCH_CNT_LIMIT] = sg_prefetch_cnt_limit; 8208 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_align - 1); 8209 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_align - 1); 8210 download_consts[SG_SIZEOF] = sg_size; 8211 download_consts[PKT_OVERRUN_BUFOFFSET] = 8212 (ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256; 8213 download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_1BYTE_LUN; 8214 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) 8215 download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_FULL_LUN; 8216 cur_patch = patches; 8217 downloaded = 0; 8218 skip_addr = 0; 8219 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 8220 ahd_outb(ahd, PRGMCNT, 0); 8221 ahd_outb(ahd, PRGMCNT+1, 0); 8222 8223 for (i = 0; i < sizeof(seqprog)/4; i++) { 8224 if (ahd_check_patch(ahd, &cur_patch, i, &skip_addr) == 0) { 8225 /* 8226 * Don't download this instruction as it 8227 * is in a patch that was removed. 8228 */ 8229 continue; 8230 } 8231 /* 8232 * Move through the CS table until we find a CS 8233 * that might apply to this instruction. 8234 */ 8235 for (; cur_cs < num_critical_sections; cur_cs++) { 8236 if (critical_sections[cur_cs].end <= i) { 8237 if (begin_set[cs_count] == TRUE 8238 && end_set[cs_count] == FALSE) { 8239 cs_table[cs_count].end = downloaded; 8240 end_set[cs_count] = TRUE; 8241 cs_count++; 8242 } 8243 continue; 8244 } 8245 if (critical_sections[cur_cs].begin <= i 8246 && begin_set[cs_count] == FALSE) { 8247 cs_table[cs_count].begin = downloaded; 8248 begin_set[cs_count] = TRUE; 8249 } 8250 break; 8251 } 8252 ahd_download_instr(ahd, i, download_consts); 8253 downloaded++; 8254 } 8255 8256 ahd->num_critical_sections = cs_count; 8257 if (cs_count != 0) { 8258 8259 cs_count *= sizeof(struct cs); 8260 ahd->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 8261 if (ahd->critical_sections == NULL) 8262 panic("ahd_loadseq: Could not malloc"); 8263 memcpy(ahd->critical_sections, cs_table, cs_count); 8264 } 8265 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE); 8266 8267 if (bootverbose) { 8268 printf(" %d instructions downloaded\n", downloaded); 8269 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 8270 ahd_name(ahd), ahd->features, ahd->bugs, ahd->flags); 8271 } 8272 } 8273 8274 static int 8275 ahd_check_patch(struct ahd_softc *ahd, struct patch **start_patch, 8276 u_int start_instr, u_int *skip_addr) 8277 { 8278 struct patch *cur_patch; 8279 struct patch *last_patch; 8280 u_int num_patches; 8281 8282 num_patches = sizeof(patches)/sizeof(struct patch); 8283 last_patch = &patches[num_patches]; 8284 cur_patch = *start_patch; 8285 8286 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 8287 8288 if (cur_patch->patch_func(ahd) == 0) { 8289 8290 /* Start rejecting code */ 8291 *skip_addr = start_instr + cur_patch->skip_instr; 8292 cur_patch += cur_patch->skip_patch; 8293 } else { 8294 /* Accepted this patch. Advance to the next 8295 * one and wait for our intruction pointer to 8296 * hit this point. 8297 */ 8298 cur_patch++; 8299 } 8300 } 8301 8302 *start_patch = cur_patch; 8303 if (start_instr < *skip_addr) 8304 /* Still skipping */ 8305 return (0); 8306 8307 return (1); 8308 } 8309 8310 static u_int 8311 ahd_resolve_seqaddr(struct ahd_softc *ahd, u_int address) 8312 { 8313 struct patch *cur_patch; 8314 int address_offset; 8315 u_int skip_addr; 8316 u_int i; 8317 8318 address_offset = 0; 8319 cur_patch = patches; 8320 skip_addr = 0; 8321 8322 for (i = 0; i < address;) { 8323 8324 ahd_check_patch(ahd, &cur_patch, i, &skip_addr); 8325 8326 if (skip_addr > i) { 8327 int end_addr; 8328 8329 end_addr = MIN(address, skip_addr); 8330 address_offset += end_addr - i; 8331 i = skip_addr; 8332 } else { 8333 i++; 8334 } 8335 } 8336 return (address - address_offset); 8337 } 8338 8339 static void 8340 ahd_download_instr(struct ahd_softc *ahd, u_int instrptr, uint8_t *dconsts) 8341 { 8342 union ins_formats instr; 8343 struct ins_format1 *fmt1_ins; 8344 struct ins_format3 *fmt3_ins; 8345 u_int opcode; 8346 8347 /* 8348 * The firmware is always compiled into a little endian format. 8349 */ 8350 instr.integer = ahd_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 8351 8352 fmt1_ins = &instr.format1; 8353 fmt3_ins = NULL; 8354 8355 /* Pull the opcode */ 8356 opcode = instr.format1.opcode; 8357 switch (opcode) { 8358 case AIC_OP_JMP: 8359 case AIC_OP_JC: 8360 case AIC_OP_JNC: 8361 case AIC_OP_CALL: 8362 case AIC_OP_JNE: 8363 case AIC_OP_JNZ: 8364 case AIC_OP_JE: 8365 case AIC_OP_JZ: 8366 { 8367 fmt3_ins = &instr.format3; 8368 fmt3_ins->address = ahd_resolve_seqaddr(ahd, fmt3_ins->address); 8369 /* FALLTHROUGH */ 8370 } 8371 case AIC_OP_OR: 8372 case AIC_OP_AND: 8373 case AIC_OP_XOR: 8374 case AIC_OP_ADD: 8375 case AIC_OP_ADC: 8376 case AIC_OP_BMOV: 8377 if (fmt1_ins->parity != 0) { 8378 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 8379 } 8380 fmt1_ins->parity = 0; 8381 /* FALLTHROUGH */ 8382 case AIC_OP_ROL: 8383 { 8384 int i, count; 8385 8386 /* Calculate odd parity for the instruction */ 8387 for (i = 0, count = 0; i < 31; i++) { 8388 uint32_t mask; 8389 8390 mask = 0x01 << i; 8391 if ((instr.integer & mask) != 0) 8392 count++; 8393 } 8394 if ((count & 0x01) == 0) 8395 instr.format1.parity = 1; 8396 8397 /* The sequencer is a little endian cpu */ 8398 instr.integer = ahd_htole32(instr.integer); 8399 ahd_outsb(ahd, SEQRAM, instr.bytes, 4); 8400 break; 8401 } 8402 default: 8403 panic("Unknown opcode encountered in seq program"); 8404 break; 8405 } 8406 } 8407 8408 static int 8409 ahd_probe_stack_size(struct ahd_softc *ahd) 8410 { 8411 int last_probe; 8412 8413 last_probe = 0; 8414 while (1) { 8415 int i; 8416 8417 /* 8418 * We avoid using 0 as a pattern to avoid 8419 * confusion if the stack implementation 8420 * "back-fills" with zeros when "poping' 8421 * entries. 8422 */ 8423 for (i = 1; i <= last_probe+1; i++) { 8424 ahd_outb(ahd, STACK, i & 0xFF); 8425 ahd_outb(ahd, STACK, (i >> 8) & 0xFF); 8426 } 8427 8428 /* Verify */ 8429 for (i = last_probe+1; i > 0; i--) { 8430 u_int stack_entry; 8431 8432 stack_entry = ahd_inb(ahd, STACK) 8433 |(ahd_inb(ahd, STACK) << 8); 8434 if (stack_entry != i) 8435 goto sized; 8436 } 8437 last_probe++; 8438 } 8439 sized: 8440 return (last_probe); 8441 } 8442 8443 void 8444 ahd_dump_all_cards_state() 8445 { 8446 struct ahd_softc *list_ahd; 8447 8448 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) { 8449 ahd_dump_card_state(list_ahd); 8450 } 8451 } 8452 8453 int 8454 ahd_print_register(ahd_reg_parse_entry_t *table, u_int num_entries, 8455 const char *name, u_int address, u_int value, 8456 u_int *cur_column, u_int wrap_point) 8457 { 8458 int printed; 8459 u_int printed_mask; 8460 8461 if (cur_column != NULL && *cur_column >= wrap_point) { 8462 printf("\n"); 8463 *cur_column = 0; 8464 } 8465 printed = printf("%s[0x%x]", name, value); 8466 if (table == NULL) { 8467 printed += printf(" "); 8468 *cur_column += printed; 8469 return (printed); 8470 } 8471 printed_mask = 0; 8472 while (printed_mask != 0xFF) { 8473 int entry; 8474 8475 for (entry = 0; entry < num_entries; entry++) { 8476 if (((value & table[entry].mask) 8477 != table[entry].value) 8478 || ((printed_mask & table[entry].mask) 8479 == table[entry].mask)) 8480 continue; 8481 8482 printed += printf("%s%s", 8483 printed_mask == 0 ? ":(" : "|", 8484 table[entry].name); 8485 printed_mask |= table[entry].mask; 8486 8487 break; 8488 } 8489 if (entry >= num_entries) 8490 break; 8491 } 8492 if (printed_mask != 0) 8493 printed += printf(") "); 8494 else 8495 printed += printf(" "); 8496 if (cur_column != NULL) 8497 *cur_column += printed; 8498 return (printed); 8499 } 8500 8501 void 8502 ahd_dump_card_state(struct ahd_softc *ahd) 8503 { 8504 struct scb *scb; 8505 ahd_mode_state saved_modes; 8506 u_int dffstat; 8507 int paused; 8508 u_int scb_index; 8509 u_int saved_scb_index; 8510 u_int cur_col; 8511 int i; 8512 8513 if (ahd_is_paused(ahd)) { 8514 paused = 1; 8515 } else { 8516 paused = 0; 8517 ahd_pause(ahd); 8518 } 8519 saved_modes = ahd_save_modes(ahd); 8520 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 8521 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 8522 "%s: Dumping Card State at program address 0x%x Mode 0x%x\n", 8523 ahd_name(ahd), 8524 ahd_inb(ahd, CURADDR) | (ahd_inb(ahd, CURADDR+1) << 8), 8525 ahd_build_mode_state(ahd, ahd->saved_src_mode, 8526 ahd->saved_dst_mode)); 8527 if (paused) 8528 printf("Card was paused\n"); 8529 /* 8530 * Mode independent registers. 8531 */ 8532 cur_col = 0; 8533 ahd_hs_mailbox_print(ahd_inb(ahd, LOCAL_HS_MAILBOX), &cur_col, 50); 8534 ahd_intctl_print(ahd_inb(ahd, INTCTL), &cur_col, 50); 8535 ahd_seqintstat_print(ahd_inb(ahd, SEQINTSTAT), &cur_col, 50); 8536 ahd_saved_mode_print(ahd_inb(ahd, SAVED_MODE), &cur_col, 50); 8537 ahd_dffstat_print(ahd_inb(ahd, DFFSTAT), &cur_col, 50); 8538 ahd_scsisigi_print(ahd_inb(ahd, SCSISIGI), &cur_col, 50); 8539 ahd_scsiphase_print(ahd_inb(ahd, SCSIPHASE), &cur_col, 50); 8540 ahd_scsibus_print(ahd_inb(ahd, SCSIBUS), &cur_col, 50); 8541 ahd_lastphase_print(ahd_inb(ahd, LASTPHASE), &cur_col, 50); 8542 ahd_scsiseq0_print(ahd_inb(ahd, SCSISEQ0), &cur_col, 50); 8543 ahd_scsiseq1_print(ahd_inb(ahd, SCSISEQ1), &cur_col, 50); 8544 ahd_seqctl0_print(ahd_inb(ahd, SEQCTL0), &cur_col, 50); 8545 ahd_seqintctl_print(ahd_inb(ahd, SEQINTCTL), &cur_col, 50); 8546 ahd_seq_flags_print(ahd_inb(ahd, SEQ_FLAGS), &cur_col, 50); 8547 ahd_seq_flags2_print(ahd_inb(ahd, SEQ_FLAGS2), &cur_col, 50); 8548 ahd_sstat0_print(ahd_inb(ahd, SSTAT0), &cur_col, 50); 8549 ahd_sstat1_print(ahd_inb(ahd, SSTAT1), &cur_col, 50); 8550 ahd_sstat2_print(ahd_inb(ahd, SSTAT2), &cur_col, 50); 8551 ahd_sstat3_print(ahd_inb(ahd, SSTAT3), &cur_col, 50); 8552 ahd_perrdiag_print(ahd_inb(ahd, PERRDIAG), &cur_col, 50); 8553 ahd_simode1_print(ahd_inb(ahd, SIMODE1), &cur_col, 50); 8554 ahd_lqistat0_print(ahd_inb(ahd, LQISTAT0), &cur_col, 50); 8555 ahd_lqistat1_print(ahd_inb(ahd, LQISTAT1), &cur_col, 50); 8556 ahd_lqistat2_print(ahd_inb(ahd, LQISTAT2), &cur_col, 50); 8557 ahd_lqostat0_print(ahd_inb(ahd, LQOSTAT0), &cur_col, 50); 8558 ahd_lqostat1_print(ahd_inb(ahd, LQOSTAT1), &cur_col, 50); 8559 ahd_lqostat2_print(ahd_inb(ahd, LQOSTAT2), &cur_col, 50); 8560 printf("\n"); 8561 printf("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x " 8562 "CURRSCB 0x%x NEXTSCB 0x%x\n", 8563 ahd->scb_data.numscbs, ahd_inw(ahd, CMDS_PENDING), 8564 ahd_inw(ahd, LASTSCB), ahd_inw(ahd, CURRSCB), 8565 ahd_inw(ahd, NEXTSCB)); 8566 cur_col = 0; 8567 /* QINFIFO */ 8568 ahd_search_qinfifo(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, 8569 CAM_LUN_WILDCARD, SCB_LIST_NULL, 8570 ROLE_UNKNOWN, /*status*/0, SEARCH_PRINT); 8571 saved_scb_index = ahd_get_scbptr(ahd); 8572 printf("Pending list:"); 8573 i = 0; 8574 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 8575 if (i++ > AHD_SCB_MAX) 8576 break; 8577 cur_col = printf("\n%3d ", SCB_GET_TAG(scb)); 8578 ahd_set_scbptr(ahd, SCB_GET_TAG(scb)); 8579 ahd_scb_control_print(ahd_inb(ahd, SCB_CONTROL), &cur_col, 60); 8580 ahd_scb_scsiid_print(ahd_inb(ahd, SCB_SCSIID), &cur_col, 60); 8581 ahd_scb_tag_print(ahd_inb(ahd, SCB_TAG), &cur_col, 60); 8582 } 8583 printf("\nTotal %d\n", i); 8584 8585 printf("Kernel Free SCB list: "); 8586 i = 0; 8587 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 8588 struct scb *list_scb; 8589 8590 list_scb = scb; 8591 do { 8592 printf("%d ", SCB_GET_TAG(list_scb)); 8593 list_scb = LIST_NEXT(list_scb, collision_links); 8594 } while (list_scb && i++ < AHD_SCB_MAX); 8595 } 8596 8597 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { 8598 if (i++ > AHD_SCB_MAX) 8599 break; 8600 printf("%d ", SCB_GET_TAG(scb)); 8601 } 8602 printf("\n"); 8603 8604 printf("Sequencer Complete DMA-inprog list: "); 8605 scb_index = ahd_inw(ahd, COMPLETE_SCB_DMAINPROG_HEAD); 8606 i = 0; 8607 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8608 ahd_set_scbptr(ahd, scb_index); 8609 printf("%d ", scb_index); 8610 scb_index = ahd_inw(ahd, SCB_NEXT_COMPLETE); 8611 } 8612 printf("\n"); 8613 8614 printf("Sequencer Complete list: "); 8615 scb_index = ahd_inw(ahd, COMPLETE_SCB_HEAD); 8616 i = 0; 8617 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8618 ahd_set_scbptr(ahd, scb_index); 8619 printf("%d ", scb_index); 8620 scb_index = ahd_inw(ahd, SCB_NEXT_COMPLETE); 8621 } 8622 printf("\n"); 8623 8624 8625 printf("Sequencer DMA-Up and Complete list: "); 8626 scb_index = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 8627 i = 0; 8628 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8629 ahd_set_scbptr(ahd, scb_index); 8630 printf("%d ", scb_index); 8631 scb_index = ahd_inw(ahd, SCB_NEXT_COMPLETE); 8632 } 8633 printf("\n"); 8634 ahd_set_scbptr(ahd, saved_scb_index); 8635 dffstat = ahd_inb(ahd, DFFSTAT); 8636 for (i = 0; i < 2; i++) { 8637 #ifdef AHD_DEBUG 8638 struct scb *fifo_scb; 8639 #endif 8640 u_int fifo_scbptr; 8641 8642 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); 8643 fifo_scbptr = ahd_get_scbptr(ahd); 8644 printf("\n%s: FIFO%d %s, LONGJMP == 0x%x, " 8645 "SCB 0x%x, LJSCB 0x%x\n", 8646 ahd_name(ahd), i, 8647 (dffstat & (FIFO0FREE << i)) ? "Free" : "Active", 8648 ahd_inw(ahd, LONGJMP_ADDR), fifo_scbptr, 8649 ahd_inw(ahd, LONGJMP_SCB)); 8650 cur_col = 0; 8651 ahd_seqimode_print(ahd_inb(ahd, SEQIMODE), &cur_col, 50); 8652 ahd_seqintsrc_print(ahd_inb(ahd, SEQINTSRC), &cur_col, 50); 8653 ahd_dfcntrl_print(ahd_inb(ahd, DFCNTRL), &cur_col, 50); 8654 ahd_dfstatus_print(ahd_inb(ahd, DFSTATUS), &cur_col, 50); 8655 ahd_sg_cache_shadow_print(ahd_inb(ahd, SG_CACHE_SHADOW), 8656 &cur_col, 50); 8657 ahd_sg_state_print(ahd_inb(ahd, SG_STATE), &cur_col, 50); 8658 ahd_dffsxfrctl_print(ahd_inb(ahd, DFFSXFRCTL), &cur_col, 50); 8659 ahd_soffcnt_print(ahd_inb(ahd, SOFFCNT), &cur_col, 50); 8660 ahd_mdffstat_print(ahd_inb(ahd, MDFFSTAT), &cur_col, 50); 8661 if (cur_col > 50) { 8662 printf("\n"); 8663 cur_col = 0; 8664 } 8665 cur_col += printf("SHADDR = 0x%x%x, SHCNT = 0x%x ", 8666 ahd_inl(ahd, SHADDR+4), 8667 ahd_inl(ahd, SHADDR), 8668 (ahd_inb(ahd, SHCNT) 8669 | (ahd_inb(ahd, SHCNT + 1) << 8) 8670 | (ahd_inb(ahd, SHCNT + 2) << 16))); 8671 if (cur_col > 50) { 8672 printf("\n"); 8673 cur_col = 0; 8674 } 8675 cur_col += printf("HADDR = 0x%x%x, HCNT = 0x%x ", 8676 ahd_inl(ahd, HADDR+4), 8677 ahd_inl(ahd, HADDR), 8678 (ahd_inb(ahd, HCNT) 8679 | (ahd_inb(ahd, HCNT + 1) << 8) 8680 | (ahd_inb(ahd, HCNT + 2) << 16))); 8681 ahd_ccsgctl_print(ahd_inb(ahd, CCSGCTL), &cur_col, 50); 8682 #ifdef AHD_DEBUG 8683 if ((ahd_debug & AHD_SHOW_SG) != 0) { 8684 fifo_scb = ahd_lookup_scb(ahd, fifo_scbptr); 8685 if (fifo_scb != NULL) 8686 ahd_dump_sglist(fifo_scb); 8687 } 8688 #endif 8689 } 8690 printf("\nLQIN: "); 8691 for (i = 0; i < 20; i++) 8692 printf("0x%x ", ahd_inb(ahd, LQIN + i)); 8693 printf("\n"); 8694 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 8695 printf("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n", 8696 ahd_name(ahd), ahd_inb(ahd, LQISTATE), ahd_inb(ahd, LQOSTATE), 8697 ahd_inb(ahd, OPTIONMODE)); 8698 printf("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n", 8699 ahd_name(ahd), ahd_inb(ahd, OS_SPACE_CNT), 8700 ahd_inb(ahd, MAXCMDCNT)); 8701 ahd_simode0_print(ahd_inb(ahd, SIMODE0), &cur_col, 50); 8702 printf("\n"); 8703 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 8704 cur_col = 0; 8705 ahd_ccscbctl_print(ahd_inb(ahd, CCSCBCTL), &cur_col, 50); 8706 printf("\n"); 8707 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 8708 printf("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n", 8709 ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX), 8710 ahd_inw(ahd, DINDEX)); 8711 printf("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n", 8712 ahd_name(ahd), ahd_get_scbptr(ahd), ahd_inw(ahd, SCB_NEXT), 8713 ahd_inw(ahd, SCB_NEXT2)); 8714 printf("CDB %x %x %x %x %x %x\n", 8715 ahd_inb(ahd, SCB_CDB_STORE), 8716 ahd_inb(ahd, SCB_CDB_STORE+1), 8717 ahd_inb(ahd, SCB_CDB_STORE+2), 8718 ahd_inb(ahd, SCB_CDB_STORE+3), 8719 ahd_inb(ahd, SCB_CDB_STORE+4), 8720 ahd_inb(ahd, SCB_CDB_STORE+5)); 8721 printf("STACK:"); 8722 for (i = 0; i < ahd->stack_size; i++) { 8723 ahd->saved_stack[i] = 8724 ahd_inb(ahd, STACK)|(ahd_inb(ahd, STACK) << 8); 8725 printf(" 0x%x", ahd->saved_stack[i]); 8726 } 8727 for (i = ahd->stack_size-1; i >= 0; i--) { 8728 ahd_outb(ahd, STACK, ahd->saved_stack[i] & 0xFF); 8729 ahd_outb(ahd, STACK, (ahd->saved_stack[i] >> 8) & 0xFF); 8730 } 8731 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 8732 ahd_platform_dump_card_state(ahd); 8733 ahd_restore_modes(ahd, saved_modes); 8734 if (paused == 0) 8735 ahd_unpause(ahd); 8736 } 8737 8738 void 8739 ahd_dump_scbs(struct ahd_softc *ahd) 8740 { 8741 ahd_mode_state saved_modes; 8742 u_int saved_scb_index; 8743 int i; 8744 8745 saved_modes = ahd_save_modes(ahd); 8746 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 8747 saved_scb_index = ahd_get_scbptr(ahd); 8748 for (i = 0; i < AHD_SCB_MAX; i++) { 8749 ahd_set_scbptr(ahd, i); 8750 printf("%3d", i); 8751 printf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n", 8752 ahd_inb(ahd, SCB_CONTROL), 8753 ahd_inb(ahd, SCB_SCSIID), ahd_inw(ahd, SCB_NEXT), 8754 ahd_inw(ahd, SCB_NEXT2), ahd_inl(ahd, SCB_SGPTR), 8755 ahd_inl(ahd, SCB_RESIDUAL_SGPTR)); 8756 } 8757 printf("\n"); 8758 ahd_set_scbptr(ahd, saved_scb_index); 8759 ahd_restore_modes(ahd, saved_modes); 8760 } 8761 8762 /**************************** Flexport Logic **********************************/ 8763 /* 8764 * Read count 16bit words from 16bit word address start_addr from the 8765 * SEEPROM attached to the controller, into buf, using the controller's 8766 * SEEPROM reading state machine. 8767 */ 8768 int 8769 ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 8770 u_int start_addr, u_int count) 8771 { 8772 u_int cur_addr; 8773 u_int end_addr; 8774 int error; 8775 8776 /* 8777 * If we never make it through the loop even once, 8778 * we were passed invalid arguments. 8779 */ 8780 error = EINVAL; 8781 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8782 end_addr = start_addr + count; 8783 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { 8784 ahd_outb(ahd, SEEADR, cur_addr); 8785 ahd_outb(ahd, SEECTL, SEEOP_READ | SEESTART); 8786 8787 error = ahd_wait_seeprom(ahd); 8788 if (error) 8789 break; 8790 *buf++ = ahd_inw(ahd, SEEDAT); 8791 } 8792 return (error); 8793 } 8794 8795 /* 8796 * Write count 16bit words from buf, into SEEPROM attache to the 8797 * controller starting at 16bit word address start_addr, using the 8798 * controller's SEEPROM writing state machine. 8799 */ 8800 int 8801 ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 8802 u_int start_addr, u_int count) 8803 { 8804 u_int cur_addr; 8805 u_int end_addr; 8806 int error; 8807 int retval; 8808 8809 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8810 error = ENOENT; 8811 8812 /* Place the chip into write-enable mode */ 8813 ahd_outb(ahd, SEEADR, SEEOP_EWEN_ADDR); 8814 ahd_outb(ahd, SEECTL, SEEOP_EWEN | SEESTART); 8815 error = ahd_wait_seeprom(ahd); 8816 if (error) 8817 return (error); 8818 8819 /* 8820 * Write the data. If we don't get throught the loop at 8821 * least once, the arguments were invalid. 8822 */ 8823 retval = EINVAL; 8824 end_addr = start_addr + count; 8825 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { 8826 ahd_outw(ahd, SEEDAT, *buf++); 8827 ahd_outb(ahd, SEEADR, cur_addr); 8828 ahd_outb(ahd, SEECTL, SEEOP_WRITE | SEESTART); 8829 8830 retval = ahd_wait_seeprom(ahd); 8831 if (retval) 8832 break; 8833 } 8834 8835 /* 8836 * Disable writes. 8837 */ 8838 ahd_outb(ahd, SEEADR, SEEOP_EWDS_ADDR); 8839 ahd_outb(ahd, SEECTL, SEEOP_EWDS | SEESTART); 8840 error = ahd_wait_seeprom(ahd); 8841 if (error) 8842 return (error); 8843 return (retval); 8844 } 8845 8846 /* 8847 * Wait ~100us for the serial eeprom to satisfy our request. 8848 */ 8849 int 8850 ahd_wait_seeprom(struct ahd_softc *ahd) 8851 { 8852 int cnt; 8853 8854 cnt = 20; 8855 while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt) 8856 ahd_delay(5); 8857 8858 if (cnt == 0) 8859 return (ETIMEDOUT); 8860 return (0); 8861 } 8862 8863 int 8864 ahd_verify_cksum(struct seeprom_config *sc) 8865 { 8866 int i; 8867 int maxaddr; 8868 uint32_t checksum; 8869 uint16_t *scarray; 8870 8871 maxaddr = (sizeof(*sc)/2) - 1; 8872 checksum = 0; 8873 scarray = (uint16_t *)sc; 8874 8875 for (i = 0; i < maxaddr; i++) 8876 checksum = checksum + scarray[i]; 8877 if (checksum == 0 8878 || (checksum & 0xFFFF) != sc->checksum) { 8879 return (0); 8880 } else { 8881 return (1); 8882 } 8883 } 8884 8885 int 8886 ahd_acquire_seeprom(struct ahd_softc *ahd) 8887 { 8888 /* 8889 * We should be able to determine the SEEPROM type 8890 * from the flexport logic, but unfortunately not 8891 * all implementations have this logic and there is 8892 * no programatic method for determining if the logic 8893 * is present. 8894 */ 8895 return (1); 8896 #if 0 8897 uint8_t seetype; 8898 int error; 8899 8900 error = ahd_read_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, &seetype); 8901 if (error != 0 8902 || ((seetype & FLX_ROMSTAT_SEECFG) == FLX_ROMSTAT_SEE_NONE)) 8903 return (0); 8904 return (1); 8905 #endif 8906 } 8907 8908 void 8909 ahd_release_seeprom(struct ahd_softc *ahd) 8910 { 8911 /* Currently a no-op */ 8912 } 8913 8914 int 8915 ahd_write_flexport(struct ahd_softc *ahd, u_int addr, u_int value) 8916 { 8917 int error; 8918 8919 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8920 if (addr > 7) 8921 panic("ahd_write_flexport: address out of range"); 8922 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); 8923 error = ahd_wait_flexport(ahd); 8924 if (error != 0) 8925 return (error); 8926 ahd_outb(ahd, BRDDAT, value); 8927 ahd_flush_device_writes(ahd); 8928 ahd_outb(ahd, BRDCTL, BRDSTB|BRDEN|(addr << 3)); 8929 ahd_flush_device_writes(ahd); 8930 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); 8931 ahd_flush_device_writes(ahd); 8932 ahd_outb(ahd, BRDCTL, 0); 8933 ahd_flush_device_writes(ahd); 8934 return (0); 8935 } 8936 8937 int 8938 ahd_read_flexport(struct ahd_softc *ahd, u_int addr, uint8_t *value) 8939 { 8940 int error; 8941 8942 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8943 if (addr > 7) 8944 panic("ahd_read_flexport: address out of range"); 8945 ahd_outb(ahd, BRDCTL, BRDRW|BRDEN|(addr << 3)); 8946 error = ahd_wait_flexport(ahd); 8947 if (error != 0) 8948 return (error); 8949 *value = ahd_inb(ahd, BRDDAT); 8950 ahd_outb(ahd, BRDCTL, 0); 8951 ahd_flush_device_writes(ahd); 8952 return (0); 8953 } 8954 8955 /* 8956 * Wait at most 2 seconds for flexport arbitration to succeed. 8957 */ 8958 int 8959 ahd_wait_flexport(struct ahd_softc *ahd) 8960 { 8961 int cnt; 8962 8963 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8964 cnt = 1000000 * 2 / 5; 8965 while ((ahd_inb(ahd, BRDCTL) & FLXARBACK) == 0 && --cnt) 8966 ahd_delay(5); 8967 8968 if (cnt == 0) 8969 return (ETIMEDOUT); 8970 return (0); 8971 } 8972 8973 /************************* Target Mode ****************************************/ 8974 #ifdef AHD_TARGET_MODE 8975 cam_status 8976 ahd_find_tmode_devs(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb, 8977 struct ahd_tmode_tstate **tstate, 8978 struct ahd_tmode_lstate **lstate, 8979 int notfound_failure) 8980 { 8981 8982 if ((ahd->features & AHD_TARGETMODE) == 0) 8983 return (CAM_REQ_INVALID); 8984 8985 /* 8986 * Handle the 'black hole' device that sucks up 8987 * requests to unattached luns on enabled targets. 8988 */ 8989 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 8990 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 8991 *tstate = NULL; 8992 *lstate = ahd->black_hole; 8993 } else { 8994 u_int max_id; 8995 8996 max_id = (ahd->features & AHD_WIDE) ? 15 : 7; 8997 if (ccb->ccb_h.target_id > max_id) 8998 return (CAM_TID_INVALID); 8999 9000 if (ccb->ccb_h.target_lun >= AHD_NUM_LUNS) 9001 return (CAM_LUN_INVALID); 9002 9003 *tstate = ahd->enabled_targets[ccb->ccb_h.target_id]; 9004 *lstate = NULL; 9005 if (*tstate != NULL) 9006 *lstate = 9007 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 9008 } 9009 9010 if (notfound_failure != 0 && *lstate == NULL) 9011 return (CAM_PATH_INVALID); 9012 9013 return (CAM_REQ_CMP); 9014 } 9015 9016 void 9017 ahd_handle_en_lun(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb) 9018 { 9019 #if NOT_YET 9020 struct ahd_tmode_tstate *tstate; 9021 struct ahd_tmode_lstate *lstate; 9022 struct ccb_en_lun *cel; 9023 cam_status status; 9024 u_int target; 9025 u_int lun; 9026 u_int target_mask; 9027 u_long s; 9028 char channel; 9029 9030 status = ahd_find_tmode_devs(ahd, sim, ccb, &tstate, &lstate, 9031 /*notfound_failure*/FALSE); 9032 9033 if (status != CAM_REQ_CMP) { 9034 ccb->ccb_h.status = status; 9035 return; 9036 } 9037 9038 if ((ahd->features & AHD_MULTIROLE) != 0) { 9039 u_int our_id; 9040 9041 our_id = ahd->our_id; 9042 if (ccb->ccb_h.target_id != our_id) { 9043 if ((ahd->features & AHD_MULTI_TID) != 0 9044 && (ahd->flags & AHD_INITIATORROLE) != 0) { 9045 /* 9046 * Only allow additional targets if 9047 * the initiator role is disabled. 9048 * The hardware cannot handle a re-select-in 9049 * on the initiator id during a re-select-out 9050 * on a different target id. 9051 */ 9052 status = CAM_TID_INVALID; 9053 } else if ((ahd->flags & AHD_INITIATORROLE) != 0 9054 || ahd->enabled_luns > 0) { 9055 /* 9056 * Only allow our target id to change 9057 * if the initiator role is not configured 9058 * and there are no enabled luns which 9059 * are attached to the currently registered 9060 * scsi id. 9061 */ 9062 status = CAM_TID_INVALID; 9063 } 9064 } 9065 } 9066 9067 if (status != CAM_REQ_CMP) { 9068 ccb->ccb_h.status = status; 9069 return; 9070 } 9071 9072 /* 9073 * We now have an id that is valid. 9074 * If we aren't in target mode, switch modes. 9075 */ 9076 if ((ahd->flags & AHD_TARGETROLE) == 0 9077 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 9078 u_long s; 9079 9080 printf("Configuring Target Mode\n"); 9081 ahd_lock(ahd, &s); 9082 if (LIST_FIRST(&ahd->pending_scbs) != NULL) { 9083 ccb->ccb_h.status = CAM_BUSY; 9084 ahd_unlock(ahd, &s); 9085 return; 9086 } 9087 ahd->flags |= AHD_TARGETROLE; 9088 if ((ahd->features & AHD_MULTIROLE) == 0) 9089 ahd->flags &= ~AHD_INITIATORROLE; 9090 ahd_pause(ahd); 9091 ahd_loadseq(ahd); 9092 ahd_unlock(ahd, &s); 9093 } 9094 cel = &ccb->cel; 9095 target = ccb->ccb_h.target_id; 9096 lun = ccb->ccb_h.target_lun; 9097 channel = SIM_CHANNEL(ahd, sim); 9098 target_mask = 0x01 << target; 9099 if (channel == 'B') 9100 target_mask <<= 8; 9101 9102 if (cel->enable != 0) { 9103 u_int scsiseq1; 9104 9105 /* Are we already enabled?? */ 9106 if (lstate != NULL) { 9107 xpt_print_path(ccb->ccb_h.path); 9108 printf("Lun already enabled\n"); 9109 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 9110 return; 9111 } 9112 9113 if (cel->grp6_len != 0 9114 || cel->grp7_len != 0) { 9115 /* 9116 * Don't (yet?) support vendor 9117 * specific commands. 9118 */ 9119 ccb->ccb_h.status = CAM_REQ_INVALID; 9120 printf("Non-zero Group Codes\n"); 9121 return; 9122 } 9123 9124 /* 9125 * Seems to be okay. 9126 * Setup our data structures. 9127 */ 9128 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 9129 tstate = ahd_alloc_tstate(ahd, target, channel); 9130 if (tstate == NULL) { 9131 xpt_print_path(ccb->ccb_h.path); 9132 printf("Couldn't allocate tstate\n"); 9133 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9134 return; 9135 } 9136 } 9137 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 9138 if (lstate == NULL) { 9139 xpt_print_path(ccb->ccb_h.path); 9140 printf("Couldn't allocate lstate\n"); 9141 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9142 return; 9143 } 9144 memset(lstate, 0, sizeof(*lstate)); 9145 status = xpt_create_path(&lstate->path, /*periph*/NULL, 9146 xpt_path_path_id(ccb->ccb_h.path), 9147 xpt_path_target_id(ccb->ccb_h.path), 9148 xpt_path_lun_id(ccb->ccb_h.path)); 9149 if (status != CAM_REQ_CMP) { 9150 free(lstate, M_DEVBUF); 9151 xpt_print_path(ccb->ccb_h.path); 9152 printf("Couldn't allocate path\n"); 9153 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9154 return; 9155 } 9156 SLIST_INIT(&lstate->accept_tios); 9157 SLIST_INIT(&lstate->immed_notifies); 9158 ahd_lock(ahd, &s); 9159 ahd_pause(ahd); 9160 if (target != CAM_TARGET_WILDCARD) { 9161 tstate->enabled_luns[lun] = lstate; 9162 ahd->enabled_luns++; 9163 9164 if ((ahd->features & AHD_MULTI_TID) != 0) { 9165 u_int targid_mask; 9166 9167 targid_mask = ahd_inb(ahd, TARGID) 9168 | (ahd_inb(ahd, TARGID + 1) << 8); 9169 9170 targid_mask |= target_mask; 9171 ahd_outb(ahd, TARGID, targid_mask); 9172 ahd_outb(ahd, TARGID+1, (targid_mask >> 8)); 9173 9174 ahd_update_scsiid(ahd, targid_mask); 9175 } else { 9176 u_int our_id; 9177 char channel; 9178 9179 channel = SIM_CHANNEL(ahd, sim); 9180 our_id = SIM_SCSI_ID(ahd, sim); 9181 9182 /* 9183 * This can only happen if selections 9184 * are not enabled 9185 */ 9186 if (target != our_id) { 9187 u_int sblkctl; 9188 char cur_channel; 9189 int swap; 9190 9191 sblkctl = ahd_inb(ahd, SBLKCTL); 9192 cur_channel = (sblkctl & SELBUSB) 9193 ? 'B' : 'A'; 9194 if ((ahd->features & AHD_TWIN) == 0) 9195 cur_channel = 'A'; 9196 swap = cur_channel != channel; 9197 ahd->our_id = target; 9198 9199 if (swap) 9200 ahd_outb(ahd, SBLKCTL, 9201 sblkctl ^ SELBUSB); 9202 9203 ahd_outb(ahd, SCSIID, target); 9204 9205 if (swap) 9206 ahd_outb(ahd, SBLKCTL, sblkctl); 9207 } 9208 } 9209 } else 9210 ahd->black_hole = lstate; 9211 /* Allow select-in operations */ 9212 if (ahd->black_hole != NULL && ahd->enabled_luns > 0) { 9213 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 9214 scsiseq1 |= ENSELI; 9215 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); 9216 scsiseq1 = ahd_inb(ahd, SCSISEQ1); 9217 scsiseq1 |= ENSELI; 9218 ahd_outb(ahd, SCSISEQ1, scsiseq1); 9219 } 9220 ahd_unpause(ahd); 9221 ahd_unlock(ahd, &s); 9222 ccb->ccb_h.status = CAM_REQ_CMP; 9223 xpt_print_path(ccb->ccb_h.path); 9224 printf("Lun now enabled for target mode\n"); 9225 } else { 9226 struct scb *scb; 9227 int i, empty; 9228 9229 if (lstate == NULL) { 9230 ccb->ccb_h.status = CAM_LUN_INVALID; 9231 return; 9232 } 9233 9234 ahd_lock(ahd, &s); 9235 9236 ccb->ccb_h.status = CAM_REQ_CMP; 9237 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 9238 struct ccb_hdr *ccbh; 9239 9240 ccbh = &scb->io_ctx->ccb_h; 9241 if (ccbh->func_code == XPT_CONT_TARGET_IO 9242 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 9243 printf("CTIO pending\n"); 9244 ccb->ccb_h.status = CAM_REQ_INVALID; 9245 ahd_unlock(ahd, &s); 9246 return; 9247 } 9248 } 9249 9250 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 9251 printf("ATIOs pending\n"); 9252 ccb->ccb_h.status = CAM_REQ_INVALID; 9253 } 9254 9255 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 9256 printf("INOTs pending\n"); 9257 ccb->ccb_h.status = CAM_REQ_INVALID; 9258 } 9259 9260 if (ccb->ccb_h.status != CAM_REQ_CMP) { 9261 ahd_unlock(ahd, &s); 9262 return; 9263 } 9264 9265 xpt_print_path(ccb->ccb_h.path); 9266 printf("Target mode disabled\n"); 9267 xpt_free_path(lstate->path); 9268 free(lstate, M_DEVBUF); 9269 9270 ahd_pause(ahd); 9271 /* Can we clean up the target too? */ 9272 if (target != CAM_TARGET_WILDCARD) { 9273 tstate->enabled_luns[lun] = NULL; 9274 ahd->enabled_luns--; 9275 for (empty = 1, i = 0; i < 8; i++) 9276 if (tstate->enabled_luns[i] != NULL) { 9277 empty = 0; 9278 break; 9279 } 9280 9281 if (empty) { 9282 ahd_free_tstate(ahd, target, channel, 9283 /*force*/FALSE); 9284 if (ahd->features & AHD_MULTI_TID) { 9285 u_int targid_mask; 9286 9287 targid_mask = ahd_inb(ahd, TARGID) 9288 | (ahd_inb(ahd, TARGID + 1) 9289 << 8); 9290 9291 targid_mask &= ~target_mask; 9292 ahd_outb(ahd, TARGID, targid_mask); 9293 ahd_outb(ahd, TARGID+1, 9294 (targid_mask >> 8)); 9295 ahd_update_scsiid(ahd, targid_mask); 9296 } 9297 } 9298 } else { 9299 9300 ahd->black_hole = NULL; 9301 9302 /* 9303 * We can't allow selections without 9304 * our black hole device. 9305 */ 9306 empty = TRUE; 9307 } 9308 if (ahd->enabled_luns == 0) { 9309 /* Disallow select-in */ 9310 u_int scsiseq1; 9311 9312 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 9313 scsiseq1 &= ~ENSELI; 9314 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); 9315 scsiseq1 = ahd_inb(ahd, SCSISEQ1); 9316 scsiseq1 &= ~ENSELI; 9317 ahd_outb(ahd, SCSISEQ1, scsiseq1); 9318 9319 if ((ahd->features & AHD_MULTIROLE) == 0) { 9320 printf("Configuring Initiator Mode\n"); 9321 ahd->flags &= ~AHD_TARGETROLE; 9322 ahd->flags |= AHD_INITIATORROLE; 9323 ahd_pause(ahd); 9324 ahd_loadseq(ahd); 9325 } 9326 } 9327 ahd_unpause(ahd); 9328 ahd_unlock(ahd, &s); 9329 } 9330 #endif 9331 } 9332 9333 static void 9334 ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask) 9335 { 9336 #if NOT_YET 9337 u_int scsiid_mask; 9338 u_int scsiid; 9339 9340 if ((ahd->features & AHD_MULTI_TID) == 0) 9341 panic("ahd_update_scsiid called on non-multitid unit\n"); 9342 9343 /* 9344 * Since we will rely on the TARGID mask 9345 * for selection enables, ensure that OID 9346 * in SCSIID is not set to some other ID 9347 * that we don't want to allow selections on. 9348 */ 9349 if ((ahd->features & AHD_ULTRA2) != 0) 9350 scsiid = ahd_inb(ahd, SCSIID_ULTRA2); 9351 else 9352 scsiid = ahd_inb(ahd, SCSIID); 9353 scsiid_mask = 0x1 << (scsiid & OID); 9354 if ((targid_mask & scsiid_mask) == 0) { 9355 u_int our_id; 9356 9357 /* ffs counts from 1 */ 9358 our_id = ffs(targid_mask); 9359 if (our_id == 0) 9360 our_id = ahd->our_id; 9361 else 9362 our_id--; 9363 scsiid &= TID; 9364 scsiid |= our_id; 9365 } 9366 if ((ahd->features & AHD_ULTRA2) != 0) 9367 ahd_outb(ahd, SCSIID_ULTRA2, scsiid); 9368 else 9369 ahd_outb(ahd, SCSIID, scsiid); 9370 #endif 9371 } 9372 9373 void 9374 ahd_run_tqinfifo(struct ahd_softc *ahd, int paused) 9375 { 9376 struct target_cmd *cmd; 9377 9378 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_POSTREAD); 9379 while ((cmd = &ahd->targetcmds[ahd->tqinfifonext])->cmd_valid != 0) { 9380 9381 /* 9382 * Only advance through the queue if we 9383 * have the resources to process the command. 9384 */ 9385 if (ahd_handle_target_cmd(ahd, cmd) != 0) 9386 break; 9387 9388 cmd->cmd_valid = 0; 9389 ahd_dmamap_sync(ahd, ahd->shared_data_dmat, 9390 ahd->shared_data_dmamap, 9391 ahd_targetcmd_offset(ahd, ahd->tqinfifonext), 9392 sizeof(struct target_cmd), 9393 BUS_DMASYNC_PREREAD); 9394 ahd->tqinfifonext++; 9395 9396 /* 9397 * Lazily update our position in the target mode incoming 9398 * command queue as seen by the sequencer. 9399 */ 9400 if ((ahd->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 9401 u_int hs_mailbox; 9402 9403 hs_mailbox = ahd_inb(ahd, HS_MAILBOX); 9404 hs_mailbox &= ~HOST_TQINPOS; 9405 hs_mailbox |= ahd->tqinfifonext & HOST_TQINPOS; 9406 ahd_outb(ahd, HS_MAILBOX, hs_mailbox); 9407 } 9408 } 9409 } 9410 9411 static int 9412 ahd_handle_target_cmd(struct ahd_softc *ahd, struct target_cmd *cmd) 9413 { 9414 struct ahd_tmode_tstate *tstate; 9415 struct ahd_tmode_lstate *lstate; 9416 struct ccb_accept_tio *atio; 9417 uint8_t *byte; 9418 int initiator; 9419 int target; 9420 int lun; 9421 9422 initiator = SCSIID_TARGET(ahd, cmd->scsiid); 9423 target = SCSIID_OUR_ID(cmd->scsiid); 9424 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 9425 9426 byte = cmd->bytes; 9427 tstate = ahd->enabled_targets[target]; 9428 lstate = NULL; 9429 if (tstate != NULL) 9430 lstate = tstate->enabled_luns[lun]; 9431 9432 /* 9433 * Commands for disabled luns go to the black hole driver. 9434 */ 9435 if (lstate == NULL) 9436 lstate = ahd->black_hole; 9437 9438 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 9439 if (atio == NULL) { 9440 ahd->flags |= AHD_TQINFIFO_BLOCKED; 9441 /* 9442 * Wait for more ATIOs from the peripheral driver for this lun. 9443 */ 9444 return (1); 9445 } else 9446 ahd->flags &= ~AHD_TQINFIFO_BLOCKED; 9447 #ifdef AHD_DEBUG 9448 if ((ahd_debug & AHD_SHOW_TQIN) != 0) 9449 printf("Incoming command from %d for %d:%d%s\n", 9450 initiator, target, lun, 9451 lstate == ahd->black_hole ? "(Black Holed)" : ""); 9452 #endif 9453 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 9454 9455 if (lstate == ahd->black_hole) { 9456 /* Fill in the wildcards */ 9457 atio->ccb_h.target_id = target; 9458 atio->ccb_h.target_lun = lun; 9459 } 9460 9461 /* 9462 * Package it up and send it off to 9463 * whomever has this lun enabled. 9464 */ 9465 atio->sense_len = 0; 9466 atio->init_id = initiator; 9467 if (byte[0] != 0xFF) { 9468 /* Tag was included */ 9469 atio->tag_action = *byte++; 9470 atio->tag_id = *byte++; 9471 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 9472 } else { 9473 atio->ccb_h.flags = 0; 9474 } 9475 byte++; 9476 9477 /* Okay. Now determine the cdb size based on the command code */ 9478 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 9479 case 0: 9480 atio->cdb_len = 6; 9481 break; 9482 case 1: 9483 case 2: 9484 atio->cdb_len = 10; 9485 break; 9486 case 4: 9487 atio->cdb_len = 16; 9488 break; 9489 case 5: 9490 atio->cdb_len = 12; 9491 break; 9492 case 3: 9493 default: 9494 /* Only copy the opcode. */ 9495 atio->cdb_len = 1; 9496 printf("Reserved or VU command code type encountered\n"); 9497 break; 9498 } 9499 9500 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 9501 9502 atio->ccb_h.status |= CAM_CDB_RECVD; 9503 9504 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 9505 /* 9506 * We weren't allowed to disconnect. 9507 * We're hanging on the bus until a 9508 * continue target I/O comes in response 9509 * to this accept tio. 9510 */ 9511 #ifdef AHD_DEBUG 9512 if ((ahd_debug & AHD_SHOW_TQIN) != 0) 9513 printf("Received Immediate Command %d:%d:%d - %p\n", 9514 initiator, target, lun, ahd->pending_device); 9515 #endif 9516 ahd->pending_device = lstate; 9517 ahd_freeze_ccb((union ccb *)atio); 9518 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 9519 } 9520 xpt_done((union ccb*)atio); 9521 return (0); 9522 } 9523 9524 #endif 9525