1 /* 2 * Core routines and tables shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2002 Justin T. Gibbs. 5 * Copyright (c) 2000-2003 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.c#156 $ 41 * 42 * $FreeBSD$ 43 */ 44 45 #ifdef __linux__ 46 #include "aic79xx_osm.h" 47 #include "aic79xx_inline.h" 48 #include "aicasm/aicasm_insformat.h" 49 #else 50 #include <dev/aic7xxx/aic79xx_osm.h> 51 #include <dev/aic7xxx/aic79xx_inline.h> 52 #include <dev/aic7xxx/aicasm/aicasm_insformat.h> 53 #endif 54 55 /******************************** Globals *************************************/ 56 struct ahd_softc_tailq ahd_tailq = TAILQ_HEAD_INITIALIZER(ahd_tailq); 57 58 /***************************** Lookup Tables **********************************/ 59 char *ahd_chip_names[] = 60 { 61 "NONE", 62 "aic7901", 63 "aic7902", 64 "aic7901A" 65 }; 66 static const u_int num_chip_names = NUM_ELEMENTS(ahd_chip_names); 67 68 /* 69 * Hardware error codes. 70 */ 71 struct ahd_hard_error_entry { 72 uint8_t errno; 73 char *errmesg; 74 }; 75 76 static struct ahd_hard_error_entry ahd_hard_errors[] = { 77 { DSCTMOUT, "Discard Timer has timed out" }, 78 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 79 { SQPARERR, "Sequencer Parity Error" }, 80 { DPARERR, "Data-path Parity Error" }, 81 { MPARERR, "Scratch or SCB Memory Parity Error" }, 82 { CIOPARERR, "CIOBUS Parity Error" }, 83 }; 84 static const u_int num_errors = NUM_ELEMENTS(ahd_hard_errors); 85 86 static struct ahd_phase_table_entry ahd_phase_table[] = 87 { 88 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 89 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 90 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 91 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 92 { P_COMMAND, MSG_NOOP, "in Command phase" }, 93 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 94 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 95 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 96 { P_BUSFREE, MSG_NOOP, "while idle" }, 97 { 0, MSG_NOOP, "in unknown phase" } 98 }; 99 100 /* 101 * In most cases we only wish to itterate over real phases, so 102 * exclude the last element from the count. 103 */ 104 static const u_int num_phases = NUM_ELEMENTS(ahd_phase_table) - 1; 105 106 /* Our Sequencer Program */ 107 #include "aic79xx_seq.h" 108 109 /**************************** Function Declarations ***************************/ 110 static void ahd_handle_transmission_error(struct ahd_softc *ahd); 111 static void ahd_handle_lqiphase_error(struct ahd_softc *ahd, 112 u_int lqistat1); 113 static int ahd_handle_pkt_busfree(struct ahd_softc *ahd, 114 u_int busfreetime); 115 static int ahd_handle_nonpkt_busfree(struct ahd_softc *ahd); 116 static void ahd_handle_proto_violation(struct ahd_softc *ahd); 117 static void ahd_force_renegotiation(struct ahd_softc *ahd, 118 struct ahd_devinfo *devinfo); 119 120 static struct ahd_tmode_tstate* 121 ahd_alloc_tstate(struct ahd_softc *ahd, 122 u_int scsi_id, char channel); 123 #ifdef AHD_TARGET_MODE 124 static void ahd_free_tstate(struct ahd_softc *ahd, 125 u_int scsi_id, char channel, int force); 126 #endif 127 static void ahd_devlimited_syncrate(struct ahd_softc *ahd, 128 struct ahd_initiator_tinfo *, 129 u_int *period, 130 u_int *ppr_options, 131 role_t role); 132 static void ahd_update_neg_table(struct ahd_softc *ahd, 133 struct ahd_devinfo *devinfo, 134 struct ahd_transinfo *tinfo); 135 static void ahd_update_pending_scbs(struct ahd_softc *ahd); 136 static void ahd_fetch_devinfo(struct ahd_softc *ahd, 137 struct ahd_devinfo *devinfo); 138 static void ahd_scb_devinfo(struct ahd_softc *ahd, 139 struct ahd_devinfo *devinfo, 140 struct scb *scb); 141 static void ahd_setup_initiator_msgout(struct ahd_softc *ahd, 142 struct ahd_devinfo *devinfo, 143 struct scb *scb); 144 static void ahd_build_transfer_msg(struct ahd_softc *ahd, 145 struct ahd_devinfo *devinfo); 146 static void ahd_construct_sdtr(struct ahd_softc *ahd, 147 struct ahd_devinfo *devinfo, 148 u_int period, u_int offset); 149 static void ahd_construct_wdtr(struct ahd_softc *ahd, 150 struct ahd_devinfo *devinfo, 151 u_int bus_width); 152 static void ahd_construct_ppr(struct ahd_softc *ahd, 153 struct ahd_devinfo *devinfo, 154 u_int period, u_int offset, 155 u_int bus_width, u_int ppr_options); 156 static void ahd_clear_msg_state(struct ahd_softc *ahd); 157 static void ahd_handle_message_phase(struct ahd_softc *ahd); 158 typedef enum { 159 AHDMSG_1B, 160 AHDMSG_2B, 161 AHDMSG_EXT 162 } ahd_msgtype; 163 static int ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, 164 u_int msgval, int full); 165 static int ahd_parse_msg(struct ahd_softc *ahd, 166 struct ahd_devinfo *devinfo); 167 static int ahd_handle_msg_reject(struct ahd_softc *ahd, 168 struct ahd_devinfo *devinfo); 169 static void ahd_handle_ign_wide_residue(struct ahd_softc *ahd, 170 struct ahd_devinfo *devinfo); 171 static void ahd_reinitialize_dataptrs(struct ahd_softc *ahd); 172 static void ahd_handle_devreset(struct ahd_softc *ahd, 173 struct ahd_devinfo *devinfo, 174 u_int lun, cam_status status, 175 char *message, int verbose_level); 176 #if AHD_TARGET_MODE 177 static void ahd_setup_target_msgin(struct ahd_softc *ahd, 178 struct ahd_devinfo *devinfo, 179 struct scb *scb); 180 #endif 181 182 static u_int ahd_sglist_size(struct ahd_softc *ahd); 183 static u_int ahd_sglist_allocsize(struct ahd_softc *ahd); 184 static bus_dmamap_callback_t 185 ahd_dmamap_cb; 186 static void ahd_initialize_hscbs(struct ahd_softc *ahd); 187 static int ahd_init_scbdata(struct ahd_softc *ahd); 188 static void ahd_fini_scbdata(struct ahd_softc *ahd); 189 static void ahd_setup_iocell_workaround(struct ahd_softc *ahd); 190 static void ahd_iocell_first_selection(struct ahd_softc *ahd); 191 static void ahd_add_col_list(struct ahd_softc *ahd, 192 struct scb *scb, u_int col_idx); 193 static void ahd_rem_col_list(struct ahd_softc *ahd, 194 struct scb *scb); 195 static void ahd_chip_init(struct ahd_softc *ahd); 196 static void ahd_qinfifo_requeue(struct ahd_softc *ahd, 197 struct scb *prev_scb, 198 struct scb *scb); 199 static int ahd_qinfifo_count(struct ahd_softc *ahd); 200 static int ahd_search_scb_list(struct ahd_softc *ahd, int target, 201 char channel, int lun, u_int tag, 202 role_t role, uint32_t status, 203 ahd_search_action action, 204 u_int *list_head, u_int tid); 205 static void ahd_stitch_tid_list(struct ahd_softc *ahd, 206 u_int tid_prev, u_int tid_cur, 207 u_int tid_next); 208 static void ahd_add_scb_to_free_list(struct ahd_softc *ahd, 209 u_int scbid); 210 static u_int ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, 211 u_int prev, u_int next, u_int tid); 212 static void ahd_reset_current_bus(struct ahd_softc *ahd); 213 static ahd_callback_t ahd_reset_poll; 214 static ahd_callback_t ahd_stat_timer; 215 #ifdef AHD_DUMP_SEQ 216 static void ahd_dumpseq(struct ahd_softc *ahd); 217 #endif 218 static void ahd_loadseq(struct ahd_softc *ahd); 219 static int ahd_check_patch(struct ahd_softc *ahd, 220 struct patch **start_patch, 221 u_int start_instr, u_int *skip_addr); 222 static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd, 223 u_int address); 224 static void ahd_download_instr(struct ahd_softc *ahd, 225 u_int instrptr, uint8_t *dconsts); 226 static int ahd_probe_stack_size(struct ahd_softc *ahd); 227 #ifdef AHD_TARGET_MODE 228 static void ahd_queue_lstate_event(struct ahd_softc *ahd, 229 struct ahd_tmode_lstate *lstate, 230 u_int initiator_id, 231 u_int event_type, 232 u_int event_arg); 233 static void ahd_update_scsiid(struct ahd_softc *ahd, 234 u_int targid_mask); 235 static int ahd_handle_target_cmd(struct ahd_softc *ahd, 236 struct target_cmd *cmd); 237 #endif 238 239 /******************************** Private Inlines *****************************/ 240 static __inline void ahd_assert_atn(struct ahd_softc *ahd); 241 static __inline int ahd_currently_packetized(struct ahd_softc *ahd); 242 static __inline int ahd_set_active_fifo(struct ahd_softc *ahd); 243 244 static __inline void 245 ahd_assert_atn(struct ahd_softc *ahd) 246 { 247 ahd_outb(ahd, SCSISIGO, ATNO); 248 } 249 250 /* 251 * Determine if the current connection has a packetized 252 * agreement. This does not necessarily mean that we 253 * are currently in a packetized transfer. We could 254 * just as easily be sending or receiving a message. 255 */ 256 static __inline int 257 ahd_currently_packetized(struct ahd_softc *ahd) 258 { 259 ahd_mode_state saved_modes; 260 int packetized; 261 262 saved_modes = ahd_save_modes(ahd); 263 if ((ahd->bugs & AHD_PKTIZED_STATUS_BUG) != 0) { 264 /* 265 * The packetized bit refers to the last 266 * connection, not the current one. Check 267 * for non-zero LQISTATE instead. 268 */ 269 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 270 packetized = ahd_inb(ahd, LQISTATE) != 0; 271 } else { 272 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 273 packetized = ahd_inb(ahd, LQISTAT2) & PACKETIZED; 274 } 275 ahd_restore_modes(ahd, saved_modes); 276 return (packetized); 277 } 278 279 static __inline int 280 ahd_set_active_fifo(struct ahd_softc *ahd) 281 { 282 u_int active_fifo; 283 284 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 285 active_fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; 286 switch (active_fifo) { 287 case 0: 288 case 1: 289 ahd_set_modes(ahd, active_fifo, active_fifo); 290 return (1); 291 default: 292 return (0); 293 } 294 } 295 296 /************************* Sequencer Execution Control ************************/ 297 /* 298 * Restart the sequencer program from address zero 299 */ 300 void 301 ahd_restart(struct ahd_softc *ahd) 302 { 303 304 ahd_pause(ahd); 305 306 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 307 308 /* No more pending messages */ 309 ahd_clear_msg_state(ahd); 310 ahd_outb(ahd, SCSISIGO, 0); /* De-assert BSY */ 311 ahd_outb(ahd, MSG_OUT, MSG_NOOP); /* No message to send */ 312 ahd_outb(ahd, SXFRCTL1, ahd_inb(ahd, SXFRCTL1) & ~BITBUCKET); 313 ahd_outb(ahd, SEQINTCTL, 0); 314 ahd_outb(ahd, LASTPHASE, P_BUSFREE); 315 ahd_outb(ahd, SEQ_FLAGS, 0); 316 ahd_outb(ahd, SAVED_SCSIID, 0xFF); 317 ahd_outb(ahd, SAVED_LUN, 0xFF); 318 319 /* 320 * Ensure that the sequencer's idea of TQINPOS 321 * matches our own. The sequencer increments TQINPOS 322 * only after it sees a DMA complete and a reset could 323 * occur before the increment leaving the kernel to believe 324 * the command arrived but the sequencer to not. 325 */ 326 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); 327 328 /* Always allow reselection */ 329 ahd_outb(ahd, SCSISEQ1, 330 ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 331 /* Ensure that no DMA operations are in progress */ 332 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 333 ahd_outb(ahd, SCBHCNT, 0); 334 ahd_outb(ahd, CCSCBCTL, CCSCBRESET); 335 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); 336 ahd_unpause(ahd); 337 } 338 339 void 340 ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo) 341 { 342 ahd_mode_state saved_modes; 343 344 #ifdef AHD_DEBUG 345 if ((ahd_debug & AHD_SHOW_FIFOS) != 0) 346 printf("%s: Clearing FIFO %d\n", ahd_name(ahd), fifo); 347 #endif 348 saved_modes = ahd_save_modes(ahd); 349 ahd_set_modes(ahd, fifo, fifo); 350 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); 351 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) 352 ahd_outb(ahd, CCSGCTL, CCSGRESET); 353 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 354 ahd_outb(ahd, SG_STATE, 0); 355 ahd_restore_modes(ahd, saved_modes); 356 } 357 358 /************************* Input/Output Queues ********************************/ 359 /* 360 * Flush and completed commands that are sitting in the command 361 * complete queues down on the chip but have yet to be dma'ed back up. 362 */ 363 void 364 ahd_flush_qoutfifo(struct ahd_softc *ahd) 365 { 366 struct scb *scb; 367 ahd_mode_state saved_modes; 368 u_int saved_scbptr; 369 u_int ccscbctl; 370 u_int scbid; 371 u_int next_scbid; 372 373 saved_modes = ahd_save_modes(ahd); 374 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 375 saved_scbptr = ahd_get_scbptr(ahd); 376 377 /* 378 * Wait for any inprogress DMA to complete and clear DMA state 379 * if this if for an SCB in the qinfifo. 380 */ 381 while ((ccscbctl = ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0) { 382 383 if ((ccscbctl & (CCSCBDIR|CCARREN)) == (CCSCBDIR|CCARREN)) { 384 if ((ccscbctl & ARRDONE) != 0) 385 break; 386 } else if ((ccscbctl & CCSCBDONE) != 0) 387 break; 388 ahd_delay(200); 389 } 390 if ((ccscbctl & CCSCBDIR) != 0) 391 ahd_outb(ahd, CCSCBCTL, ccscbctl & ~(CCARREN|CCSCBEN)); 392 393 /* 394 * Complete any SCBs that just finished being 395 * DMA'ed into the qoutfifo. 396 */ 397 ahd_run_qoutfifo(ahd); 398 399 /* 400 * Manually update/complete any completed SCBs that are waiting to be 401 * DMA'ed back up to the host. 402 */ 403 scbid = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 404 while (!SCBID_IS_NULL(scbid)) { 405 uint8_t *hscb_ptr; 406 u_int i; 407 408 ahd_set_scbptr(ahd, scbid); 409 next_scbid = ahd_inw(ahd, SCB_NEXT_COMPLETE); 410 scb = ahd_lookup_scb(ahd, scbid); 411 if (scb == NULL) { 412 printf("%s: Warning - DMA-up and complete " 413 "SCB %d invalid\n", ahd_name(ahd), scbid); 414 continue; 415 } 416 hscb_ptr = (uint8_t *)scb->hscb; 417 for (i = 0; i < sizeof(struct hardware_scb); i++) 418 *hscb_ptr++ = ahd_inb(ahd, SCB_BASE + i); 419 420 ahd_complete_scb(ahd, scb); 421 scbid = next_scbid; 422 } 423 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); 424 425 scbid = ahd_inw(ahd, COMPLETE_SCB_HEAD); 426 while (!SCBID_IS_NULL(scbid)) { 427 428 ahd_set_scbptr(ahd, scbid); 429 next_scbid = ahd_inw(ahd, SCB_NEXT_COMPLETE); 430 scb = ahd_lookup_scb(ahd, scbid); 431 if (scb == NULL) { 432 printf("%s: Warning - Complete SCB %d invalid\n", 433 ahd_name(ahd), scbid); 434 continue; 435 } 436 437 ahd_complete_scb(ahd, scb); 438 scbid = next_scbid; 439 } 440 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); 441 ahd_set_scbptr(ahd, saved_scbptr); 442 443 /* 444 * Flush the good status FIFO for compelted packetized commands. 445 */ 446 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 447 while ((ahd_inb(ahd, LQISTAT2) & LQIGSAVAIL) != 0) { 448 scbid = (ahd_inb(ahd, GSFIFO+1) << 8) 449 | ahd_inb(ahd, GSFIFO); 450 scb = ahd_lookup_scb(ahd, scbid); 451 if (scb == NULL) { 452 printf("%s: Warning - GSFIFO SCB %d invalid\n", 453 ahd_name(ahd), scbid); 454 continue; 455 } 456 ahd_complete_scb(ahd, scb); 457 } 458 459 /* 460 * Restore state. 461 */ 462 ahd_restore_modes(ahd, saved_modes); 463 ahd->flags |= AHD_UPDATE_PEND_CMDS; 464 } 465 466 void 467 ahd_run_qoutfifo(struct ahd_softc *ahd) 468 { 469 struct scb *scb; 470 u_int scb_index; 471 472 if ((ahd->flags & AHD_RUNNING_QOUTFIFO) != 0) 473 panic("ahd_run_qoutfifo recursion"); 474 ahd->flags |= AHD_RUNNING_QOUTFIFO; 475 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD); 476 while ((ahd->qoutfifo[ahd->qoutfifonext] 477 & QOUTFIFO_ENTRY_VALID_LE) == ahd->qoutfifonext_valid_tag) { 478 479 scb_index = ahd_le16toh(ahd->qoutfifo[ahd->qoutfifonext] 480 & ~QOUTFIFO_ENTRY_VALID_LE); 481 scb = ahd_lookup_scb(ahd, scb_index); 482 if (scb == NULL) { 483 printf("%s: WARNING no command for scb %d " 484 "(cmdcmplt)\nQOUTPOS = %d\n", 485 ahd_name(ahd), scb_index, 486 ahd->qoutfifonext); 487 ahd_dump_card_state(ahd); 488 } else 489 ahd_complete_scb(ahd, scb); 490 491 ahd->qoutfifonext = (ahd->qoutfifonext+1) & (AHD_QOUT_SIZE-1); 492 if (ahd->qoutfifonext == 0) 493 ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID_LE; 494 } 495 ahd->flags &= ~AHD_RUNNING_QOUTFIFO; 496 } 497 498 /************************* Interrupt Handling *********************************/ 499 void 500 ahd_handle_hwerrint(struct ahd_softc *ahd) 501 { 502 /* 503 * Some catastrophic hardware error has occurred. 504 * Print it for the user and disable the controller. 505 */ 506 int i; 507 int error; 508 509 error = ahd_inb(ahd, ERROR); 510 for (i = 0; i < num_errors; i++) { 511 if ((error & ahd_hard_errors[i].errno) != 0) 512 printf("%s: hwerrint, %s\n", 513 ahd_name(ahd), ahd_hard_errors[i].errmesg); 514 } 515 516 ahd_dump_card_state(ahd); 517 panic("BRKADRINT"); 518 519 /* Tell everyone that this HBA is no longer availible */ 520 ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, 521 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 522 CAM_NO_HBA); 523 524 /* Tell the system that this controller has gone away. */ 525 ahd_free(ahd); 526 } 527 528 void 529 ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat) 530 { 531 u_int seqintcode; 532 533 /* 534 * Save the sequencer interrupt code and clear the SEQINT 535 * bit. We will unpause the sequencer, if appropriate, 536 * after servicing the request. 537 */ 538 seqintcode = ahd_inb(ahd, SEQINTCODE); 539 ahd_outb(ahd, CLRINT, CLRSEQINT); 540 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { 541 /* 542 * Unpause the sequencer and let it clear 543 * SEQINT by writing NO_SEQINT to it. This 544 * will cause the sequencer to be paused again, 545 * which is the expected state of this routine. 546 */ 547 ahd_unpause(ahd); 548 while (!ahd_is_paused(ahd)) 549 ; 550 ahd_outb(ahd, CLRINT, CLRSEQINT); 551 } 552 ahd_update_modes(ahd); 553 #ifdef AHD_DEBUG 554 if ((ahd_debug & AHD_SHOW_MISC) != 0) 555 printf("%s: Handle Seqint Called for code %d\n", 556 ahd_name(ahd), seqintcode); 557 #endif 558 switch (seqintcode) { 559 case ENTERING_NONPACK: 560 { 561 struct scb *scb; 562 u_int scbid; 563 564 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 565 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 566 scbid = ahd_get_scbptr(ahd); 567 scb = ahd_lookup_scb(ahd, scbid); 568 if (scb == NULL) { 569 /* 570 * Somehow need to know if this 571 * is from a selection or reselection. 572 * From that, we can termine target 573 * ID so we at least have an I_T nexus. 574 */ 575 } else { 576 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); 577 ahd_outb(ahd, SAVED_LUN, scb->hscb->lun); 578 ahd_outb(ahd, SEQ_FLAGS, 0x0); 579 } 580 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0 581 && (ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { 582 /* 583 * Phase change after read stream with 584 * CRC error with P0 asserted on last 585 * packet. 586 */ 587 #ifdef AHD_DEBUG 588 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 589 printf("%s: Assuming LQIPHASE_NLQ with " 590 "P0 assertion\n", ahd_name(ahd)); 591 #endif 592 } 593 #ifdef AHD_DEBUG 594 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 595 printf("%s: Entering NONPACK\n", ahd_name(ahd)); 596 #endif 597 break; 598 } 599 case INVALID_SEQINT: 600 printf("%s: Invalid Sequencer interrupt occurred.\n", 601 ahd_name(ahd)); 602 ahd_dump_card_state(ahd); 603 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 604 break; 605 case STATUS_OVERRUN: 606 { 607 printf("%s: Status Overrun", ahd_name(ahd)); 608 ahd_dump_card_state(ahd); 609 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 610 break; 611 } 612 case CFG4ISTAT_INTR: 613 { 614 struct scb *scb; 615 u_int scbid; 616 617 scbid = ahd_get_scbptr(ahd); 618 scb = ahd_lookup_scb(ahd, scbid); 619 if (scb == NULL) { 620 ahd_dump_card_state(ahd); 621 printf("CFG4ISTAT: Free SCB %d referenced", scbid); 622 panic("For safety"); 623 } 624 ahd_outq(ahd, HADDR, scb->sense_busaddr); 625 ahd_outw(ahd, HCNT, AHD_SENSE_BUFSIZE); 626 ahd_outb(ahd, HCNT + 2, 0); 627 ahd_outb(ahd, SG_CACHE_PRE, SG_LAST_SEG); 628 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN); 629 break; 630 } 631 case ILLEGAL_PHASE: 632 { 633 u_int bus_phase; 634 635 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 636 printf("%s: ILLEGAL_PHASE 0x%x\n", 637 ahd_name(ahd), bus_phase); 638 639 switch (bus_phase) { 640 case P_DATAOUT: 641 case P_DATAIN: 642 case P_DATAOUT_DT: 643 case P_DATAIN_DT: 644 case P_MESGOUT: 645 case P_STATUS: 646 case P_MESGIN: 647 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 648 printf("%s: Issued Bus Reset.\n", ahd_name(ahd)); 649 break; 650 case P_COMMAND: 651 { 652 struct ahd_devinfo devinfo; 653 struct scb *scb; 654 struct ahd_initiator_tinfo *targ_info; 655 struct ahd_tmode_tstate *tstate; 656 struct ahd_transinfo *tinfo; 657 u_int scbid; 658 659 /* 660 * If a target takes us into the command phase 661 * assume that it has been externally reset and 662 * has thus lost our previous packetized negotiation 663 * agreement. Since we have not sent an identify 664 * message and may not have fully qualified the 665 * connection, we change our command to TUR, assert 666 * ATN and ABORT the task when we go to message in 667 * phase. The OSM will see the REQUEUE_REQUEST 668 * status and retry the command. 669 */ 670 scbid = ahd_get_scbptr(ahd); 671 scb = ahd_lookup_scb(ahd, scbid); 672 if (scb == NULL) { 673 printf("Invalid phase with no valid SCB. " 674 "Resetting bus.\n"); 675 ahd_reset_channel(ahd, 'A', 676 /*Initiate Reset*/TRUE); 677 break; 678 } 679 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), 680 SCB_GET_TARGET(ahd, scb), 681 SCB_GET_LUN(scb), 682 SCB_GET_CHANNEL(ahd, scb), 683 ROLE_INITIATOR); 684 targ_info = ahd_fetch_transinfo(ahd, 685 devinfo.channel, 686 devinfo.our_scsiid, 687 devinfo.target, 688 &tstate); 689 tinfo = &targ_info->curr; 690 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 691 AHD_TRANS_ACTIVE, /*paused*/TRUE); 692 ahd_set_syncrate(ahd, &devinfo, /*period*/0, 693 /*offset*/0, /*ppr_options*/0, 694 AHD_TRANS_ACTIVE, /*paused*/TRUE); 695 ahd_outb(ahd, SCB_CDB_STORE, 0); 696 ahd_outb(ahd, SCB_CDB_STORE+1, 0); 697 ahd_outb(ahd, SCB_CDB_STORE+2, 0); 698 ahd_outb(ahd, SCB_CDB_STORE+3, 0); 699 ahd_outb(ahd, SCB_CDB_STORE+4, 0); 700 ahd_outb(ahd, SCB_CDB_STORE+5, 0); 701 ahd_outb(ahd, SCB_CDB_LEN, 6); 702 scb->hscb->control &= ~(TAG_ENB|SCB_TAG_TYPE); 703 scb->hscb->control |= MK_MESSAGE; 704 ahd_outb(ahd, SCB_CONTROL, scb->hscb->control); 705 ahd_outb(ahd, MSG_OUT, HOST_MSG); 706 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); 707 /* 708 * The lun is 0, regardless of the SCB's lun 709 * as we have not sent an identify message. 710 */ 711 ahd_outb(ahd, SAVED_LUN, 0); 712 ahd_outb(ahd, SEQ_FLAGS, 0); 713 ahd_assert_atn(ahd); 714 scb->flags &= ~(SCB_PACKETIZED); 715 scb->flags |= SCB_ABORT|SCB_CMDPHASE_ABORT; 716 ahd_freeze_devq(ahd, scb); 717 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ); 718 ahd_freeze_scb(scb); 719 720 /* 721 * Allow the sequencer to continue with 722 * non-pack processing. 723 */ 724 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 725 ahd_outb(ahd, CLRLQOINT1, CLRLQOPHACHGINPKT); 726 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 727 ahd_outb(ahd, CLRLQOINT1, 0); 728 } 729 #ifdef AHD_DEBUG 730 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 731 ahd_print_path(ahd, scb); 732 printf("Unexpected command phase from " 733 "packetized target\n"); 734 } 735 #endif 736 break; 737 } 738 } 739 break; 740 } 741 case CFG4OVERRUN: 742 { 743 struct scb *scb; 744 u_int scb_index; 745 746 #ifdef AHD_DEBUG 747 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 748 printf("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd), 749 ahd_inb(ahd, MODE_PTR)); 750 } 751 #endif 752 scb_index = ahd_get_scbptr(ahd); 753 scb = ahd_lookup_scb(ahd, scb_index); 754 if (scb == NULL) { 755 /* 756 * Attempt to transfer to an SCB that is 757 * not outstanding. 758 */ 759 ahd_assert_atn(ahd); 760 ahd_outb(ahd, MSG_OUT, HOST_MSG); 761 ahd->msgout_buf[0] = MSG_ABORT_TASK; 762 ahd->msgout_len = 1; 763 ahd->msgout_index = 0; 764 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 765 /* 766 * Clear status received flag to prevent any 767 * attempt to complete this bogus SCB. 768 */ 769 ahd_outb(ahd, SCB_CONTROL, 770 ahd_inb(ahd, SCB_CONTROL) & ~STATUS_RCVD); 771 } 772 break; 773 } 774 case DUMP_CARD_STATE: 775 { 776 ahd_dump_card_state(ahd); 777 break; 778 } 779 case PDATA_REINIT: 780 { 781 #ifdef AHD_DEBUG 782 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 783 printf("%s: PDATA_REINIT - DFCNTRL = 0x%x " 784 "SG_CACHE_SHADOW = 0x%x\n", 785 ahd_name(ahd), ahd_inb(ahd, DFCNTRL), 786 ahd_inb(ahd, SG_CACHE_SHADOW)); 787 } 788 #endif 789 ahd_reinitialize_dataptrs(ahd); 790 break; 791 } 792 case HOST_MSG_LOOP: 793 { 794 struct ahd_devinfo devinfo; 795 796 /* 797 * The sequencer has encountered a message phase 798 * that requires host assistance for completion. 799 * While handling the message phase(s), we will be 800 * notified by the sequencer after each byte is 801 * transfered so we can track bus phase changes. 802 * 803 * If this is the first time we've seen a HOST_MSG_LOOP 804 * interrupt, initialize the state of the host message 805 * loop. 806 */ 807 ahd_fetch_devinfo(ahd, &devinfo); 808 if (ahd->msg_type == MSG_TYPE_NONE) { 809 struct scb *scb; 810 u_int scb_index; 811 u_int bus_phase; 812 813 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 814 if (bus_phase != P_MESGIN 815 && bus_phase != P_MESGOUT) { 816 printf("ahd_intr: HOST_MSG_LOOP bad " 817 "phase 0x%x\n", bus_phase); 818 /* 819 * Probably transitioned to bus free before 820 * we got here. Just punt the message. 821 */ 822 ahd_dump_card_state(ahd); 823 ahd_clear_intstat(ahd); 824 ahd_restart(ahd); 825 return; 826 } 827 828 scb_index = ahd_get_scbptr(ahd); 829 scb = ahd_lookup_scb(ahd, scb_index); 830 if (devinfo.role == ROLE_INITIATOR) { 831 if (bus_phase == P_MESGOUT) 832 ahd_setup_initiator_msgout(ahd, 833 &devinfo, 834 scb); 835 else { 836 ahd->msg_type = 837 MSG_TYPE_INITIATOR_MSGIN; 838 ahd->msgin_index = 0; 839 } 840 } 841 #if AHD_TARGET_MODE 842 else { 843 if (bus_phase == P_MESGOUT) { 844 ahd->msg_type = 845 MSG_TYPE_TARGET_MSGOUT; 846 ahd->msgin_index = 0; 847 } 848 else 849 ahd_setup_target_msgin(ahd, 850 &devinfo, 851 scb); 852 } 853 #endif 854 } 855 856 ahd_handle_message_phase(ahd); 857 break; 858 } 859 case NO_MATCH: 860 { 861 /* Ensure we don't leave the selection hardware on */ 862 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 863 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 864 865 printf("%s:%c:%d: no active SCB for reconnecting " 866 "target - issuing BUS DEVICE RESET\n", 867 ahd_name(ahd), 'A', ahd_inb(ahd, SELID) >> 4); 868 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 869 "REG0 == 0x%x ACCUM = 0x%x\n", 870 ahd_inb(ahd, SAVED_SCSIID), ahd_inb(ahd, SAVED_LUN), 871 ahd_inw(ahd, REG0), ahd_inb(ahd, ACCUM)); 872 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 873 "SINDEX == 0x%x\n", 874 ahd_inb(ahd, SEQ_FLAGS), ahd_get_scbptr(ahd), 875 ahd_find_busy_tcl(ahd, 876 BUILD_TCL(ahd_inb(ahd, SAVED_SCSIID), 877 ahd_inb(ahd, SAVED_LUN))), 878 ahd_inw(ahd, SINDEX)); 879 printf("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 880 "SCB_CONTROL == 0x%x\n", 881 ahd_inb(ahd, SELID), ahd_inb_scbram(ahd, SCB_SCSIID), 882 ahd_inb_scbram(ahd, SCB_LUN), 883 ahd_inb_scbram(ahd, SCB_CONTROL)); 884 printf("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n", 885 ahd_inb(ahd, SCSIBUS), ahd_inb(ahd, SCSISIGI)); 886 printf("SXFRCTL0 == 0x%x\n", ahd_inb(ahd, SXFRCTL0)); 887 printf("SEQCTL0 == 0x%x\n", ahd_inb(ahd, SEQCTL0)); 888 ahd_dump_card_state(ahd); 889 ahd->msgout_buf[0] = MSG_BUS_DEV_RESET; 890 ahd->msgout_len = 1; 891 ahd->msgout_index = 0; 892 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 893 ahd_outb(ahd, MSG_OUT, HOST_MSG); 894 ahd_assert_atn(ahd); 895 break; 896 } 897 case PROTO_VIOLATION: 898 { 899 ahd_handle_proto_violation(ahd); 900 break; 901 } 902 case IGN_WIDE_RES: 903 { 904 struct ahd_devinfo devinfo; 905 906 ahd_fetch_devinfo(ahd, &devinfo); 907 ahd_handle_ign_wide_residue(ahd, &devinfo); 908 break; 909 } 910 case BAD_PHASE: 911 { 912 u_int lastphase; 913 914 lastphase = ahd_inb(ahd, LASTPHASE); 915 printf("%s:%c:%d: unknown scsi bus phase %x, " 916 "lastphase = 0x%x. Attempting to continue\n", 917 ahd_name(ahd), 'A', 918 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), 919 lastphase, ahd_inb(ahd, SCSISIGI)); 920 break; 921 } 922 case MISSED_BUSFREE: 923 { 924 u_int lastphase; 925 926 lastphase = ahd_inb(ahd, LASTPHASE); 927 printf("%s:%c:%d: Missed busfree. " 928 "Lastphase = 0x%x, Curphase = 0x%x\n", 929 ahd_name(ahd), 'A', 930 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), 931 lastphase, ahd_inb(ahd, SCSISIGI)); 932 ahd_restart(ahd); 933 return; 934 } 935 case DATA_OVERRUN: 936 { 937 /* 938 * When the sequencer detects an overrun, it 939 * places the controller in "BITBUCKET" mode 940 * and allows the target to complete its transfer. 941 * Unfortunately, none of the counters get updated 942 * when the controller is in this mode, so we have 943 * no way of knowing how large the overrun was. 944 */ 945 struct scb *scb; 946 u_int scbindex; 947 #ifdef AHD_DEBUG 948 u_int lastphase; 949 #endif 950 951 scbindex = ahd_get_scbptr(ahd); 952 scb = ahd_lookup_scb(ahd, scbindex); 953 #ifdef AHD_DEBUG 954 lastphase = ahd_inb(ahd, LASTPHASE); 955 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 956 ahd_print_path(ahd, scb); 957 printf("data overrun detected %s. Tag == 0x%x.\n", 958 ahd_lookup_phase_entry(lastphase)->phasemsg, 959 SCB_GET_TAG(scb)); 960 ahd_print_path(ahd, scb); 961 printf("%s seen Data Phase. Length = %ld. " 962 "NumSGs = %d.\n", 963 ahd_inb(ahd, SEQ_FLAGS) & DPHASE 964 ? "Have" : "Haven't", 965 ahd_get_transfer_length(scb), scb->sg_count); 966 ahd_dump_sglist(scb); 967 } 968 #endif 969 970 /* 971 * Set this and it will take effect when the 972 * target does a command complete. 973 */ 974 ahd_freeze_devq(ahd, scb); 975 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR); 976 ahd_freeze_scb(scb); 977 break; 978 } 979 case MKMSG_FAILED: 980 { 981 struct ahd_devinfo devinfo; 982 struct scb *scb; 983 u_int scbid; 984 985 ahd_fetch_devinfo(ahd, &devinfo); 986 printf("%s:%c:%d:%d: Attempt to issue message failed\n", 987 ahd_name(ahd), devinfo.channel, devinfo.target, 988 devinfo.lun); 989 scbid = ahd_get_scbptr(ahd); 990 scb = ahd_lookup_scb(ahd, scbid); 991 if (scb != NULL 992 && (scb->flags & SCB_RECOVERY_SCB) != 0) 993 /* 994 * Ensure that we didn't put a second instance of this 995 * SCB into the QINFIFO. 996 */ 997 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 998 SCB_GET_CHANNEL(ahd, scb), 999 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1000 ROLE_INITIATOR, /*status*/0, 1001 SEARCH_REMOVE); 1002 ahd_outb(ahd, SCB_CONTROL, 1003 ahd_inb(ahd, SCB_CONTROL) & ~MK_MESSAGE); 1004 break; 1005 } 1006 case TASKMGMT_FUNC_COMPLETE: 1007 { 1008 u_int scbid; 1009 struct scb *scb; 1010 1011 scbid = ahd_get_scbptr(ahd); 1012 scb = ahd_lookup_scb(ahd, scbid); 1013 if (scb != NULL) { 1014 u_int lun; 1015 u_int tag; 1016 cam_status error; 1017 1018 ahd_print_path(ahd, scb); 1019 printf("Task Management Func 0x%x Complete\n", 1020 scb->hscb->task_management); 1021 lun = CAM_LUN_WILDCARD; 1022 tag = SCB_LIST_NULL; 1023 1024 switch (scb->hscb->task_management) { 1025 case SIU_TASKMGMT_ABORT_TASK: 1026 tag = scb->hscb->tag; 1027 case SIU_TASKMGMT_ABORT_TASK_SET: 1028 case SIU_TASKMGMT_CLEAR_TASK_SET: 1029 lun = scb->hscb->lun; 1030 error = CAM_REQ_ABORTED; 1031 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 1032 'A', lun, tag, ROLE_INITIATOR, 1033 error); 1034 break; 1035 case SIU_TASKMGMT_LUN_RESET: 1036 lun = scb->hscb->lun; 1037 case SIU_TASKMGMT_TARGET_RESET: 1038 { 1039 struct ahd_devinfo devinfo; 1040 1041 ahd_scb_devinfo(ahd, &devinfo, scb); 1042 error = CAM_BDR_SENT; 1043 ahd_handle_devreset(ahd, &devinfo, lun, 1044 CAM_BDR_SENT, 1045 lun != CAM_LUN_WILDCARD 1046 ? "Lun Reset" 1047 : "Target Reset", 1048 /*verbose_level*/0); 1049 break; 1050 } 1051 default: 1052 panic("Unexpected TaskMgmt Func\n"); 1053 break; 1054 } 1055 } 1056 break; 1057 } 1058 case TASKMGMT_CMD_CMPLT_OKAY: 1059 { 1060 u_int scbid; 1061 struct scb *scb; 1062 1063 /* 1064 * An ABORT TASK TMF failed to be delivered before 1065 * the targeted command completed normally. 1066 */ 1067 scbid = ahd_get_scbptr(ahd); 1068 scb = ahd_lookup_scb(ahd, scbid); 1069 if (scb != NULL) { 1070 /* 1071 * Remove the second instance of this SCB from 1072 * the QINFIFO if it is still there. 1073 */ 1074 ahd_print_path(ahd, scb); 1075 printf("SCB completes before TMF\n"); 1076 /* 1077 * Handle losing the race. Wait until any 1078 * current selection completes. We will then 1079 * set the TMF back to zero in this SCB so that 1080 * the sequencer doesn't bother to issue another 1081 * sequencer interrupt for its completion. 1082 */ 1083 while ((ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0 1084 && (ahd_inb(ahd, SSTAT0) & SELDO) == 0 1085 && (ahd_inb(ahd, SSTAT1) & SELTO) == 0) 1086 ; 1087 ahd_outb(ahd, SCB_TASK_MANAGEMENT, 0); 1088 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 1089 SCB_GET_CHANNEL(ahd, scb), 1090 SCB_GET_LUN(scb), scb->hscb->tag, 1091 ROLE_INITIATOR, /*status*/0, 1092 SEARCH_REMOVE); 1093 } 1094 break; 1095 } 1096 case TRACEPOINT0: 1097 case TRACEPOINT1: 1098 case TRACEPOINT2: 1099 case TRACEPOINT3: 1100 printf("%s: Tracepoint %d\n", ahd_name(ahd), 1101 seqintcode - TRACEPOINT0); 1102 break; 1103 case NO_SEQINT: 1104 break; 1105 case SAW_HWERR: 1106 ahd_handle_hwerrint(ahd); 1107 break; 1108 default: 1109 printf("%s: Unexpected SEQINTCODE %d\n", ahd_name(ahd), 1110 seqintcode); 1111 break; 1112 } 1113 /* 1114 * The sequencer is paused immediately on 1115 * a SEQINT, so we should restart it when 1116 * we're done. 1117 */ 1118 ahd_unpause(ahd); 1119 } 1120 1121 void 1122 ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat) 1123 { 1124 struct scb *scb; 1125 u_int status0; 1126 u_int status3; 1127 u_int status; 1128 u_int lqistat1; 1129 u_int lqostat0; 1130 u_int scbid; 1131 u_int busfreetime; 1132 1133 ahd_update_modes(ahd); 1134 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1135 1136 status3 = ahd_inb(ahd, SSTAT3) & (NTRAMPERR|OSRAMPERR); 1137 status0 = ahd_inb(ahd, SSTAT0) & (IOERR|OVERRUN|SELDI|SELDO); 1138 status = ahd_inb(ahd, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 1139 lqistat1 = ahd_inb(ahd, LQISTAT1); 1140 lqostat0 = ahd_inb(ahd, LQOSTAT0); 1141 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; 1142 if ((status0 & (SELDI|SELDO)) != 0) { 1143 u_int simode0; 1144 1145 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 1146 simode0 = ahd_inb(ahd, SIMODE0); 1147 status0 &= simode0 & (IOERR|OVERRUN|SELDI|SELDO); 1148 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1149 } 1150 scbid = ahd_get_scbptr(ahd); 1151 scb = ahd_lookup_scb(ahd, scbid); 1152 if (scb != NULL 1153 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1154 scb = NULL; 1155 1156 /* Make sure the sequencer is in a safe location. */ 1157 ahd_clear_critical_section(ahd); 1158 1159 if ((status0 & IOERR) != 0) { 1160 u_int now_lvd; 1161 1162 now_lvd = ahd_inb(ahd, SBLKCTL) & ENAB40; 1163 printf("%s: Transceiver State Has Changed to %s mode\n", 1164 ahd_name(ahd), now_lvd ? "LVD" : "SE"); 1165 ahd_outb(ahd, CLRSINT0, CLRIOERR); 1166 /* 1167 * A change in I/O mode is equivalent to a bus reset. 1168 */ 1169 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE); 1170 ahd_pause(ahd); 1171 ahd_setup_iocell_workaround(ahd); 1172 ahd_unpause(ahd); 1173 } else if ((status0 & OVERRUN) != 0) { 1174 printf("%s: SCSI offset overrun detected. Resetting bus.\n", 1175 ahd_name(ahd)); 1176 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1177 } else if ((status & SCSIRSTI) != 0) { 1178 printf("%s: Someone reset channel A\n", ahd_name(ahd)); 1179 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE); 1180 } else if ((status & SCSIPERR) != 0) { 1181 ahd_handle_transmission_error(ahd); 1182 } else if (lqostat0 != 0) { 1183 printf("%s: lqostat0 == 0x%x!\n", ahd_name(ahd), lqostat0); 1184 ahd_outb(ahd, CLRLQOINT0, lqostat0); 1185 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 1186 ahd_outb(ahd, CLRLQOINT1, 0); 1187 } 1188 } else if ((status & SELTO) != 0) { 1189 u_int scbid; 1190 1191 /* Stop the selection */ 1192 ahd_outb(ahd, SCSISEQ0, 0); 1193 1194 /* No more pending messages */ 1195 ahd_clear_msg_state(ahd); 1196 1197 /* Clear interrupt state */ 1198 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1199 1200 /* 1201 * Although the driver does not care about the 1202 * 'Selection in Progress' status bit, the busy 1203 * LED does. SELINGO is only cleared by a sucessfull 1204 * selection, so we must manually clear it to insure 1205 * the LED turns off just incase no future successful 1206 * selections occur (e.g. no devices on the bus). 1207 */ 1208 ahd_outb(ahd, CLRSINT0, CLRSELINGO); 1209 1210 scbid = ahd_inw(ahd, WAITING_TID_HEAD); 1211 scb = ahd_lookup_scb(ahd, scbid); 1212 if (scb == NULL) { 1213 printf("%s: ahd_intr - referenced scb not " 1214 "valid during SELTO scb(0x%x)\n", 1215 ahd_name(ahd), scbid); 1216 ahd_dump_card_state(ahd); 1217 } else { 1218 struct ahd_devinfo devinfo; 1219 #ifdef AHD_DEBUG 1220 if ((ahd_debug & AHD_SHOW_SELTO) != 0) { 1221 ahd_print_path(ahd, scb); 1222 printf("Saw Selection Timeout for SCB 0x%x\n", 1223 scbid); 1224 } 1225 #endif 1226 /* 1227 * Force a renegotiation with this target just in 1228 * case the cable was pulled and will later be 1229 * re-attached. The target may forget its negotiation 1230 * settings with us should it attempt to reselect 1231 * during the interruption. The target will not issue 1232 * a unit attention in this case, so we must always 1233 * renegotiate. 1234 */ 1235 ahd_scb_devinfo(ahd, &devinfo, scb); 1236 ahd_force_renegotiation(ahd, &devinfo); 1237 ahd_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1238 ahd_freeze_devq(ahd, scb); 1239 } 1240 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1241 ahd_iocell_first_selection(ahd); 1242 ahd_unpause(ahd); 1243 } else if ((status0 & (SELDI|SELDO)) != 0) { 1244 ahd_iocell_first_selection(ahd); 1245 ahd_unpause(ahd); 1246 } else if (status3 != 0) { 1247 printf("%s: SCSI Cell parity error SSTAT3 == 0x%x\n", 1248 ahd_name(ahd), status3); 1249 ahd_outb(ahd, CLRSINT3, status3); 1250 } else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) { 1251 ahd_handle_lqiphase_error(ahd, lqistat1); 1252 } else if ((status & BUSFREE) != 0) { 1253 u_int lqostat1; 1254 int restart; 1255 int clear_fifo; 1256 int packetized; 1257 u_int mode; 1258 1259 /* 1260 * Clear our selection hardware as soon as possible. 1261 * We may have an entry in the waiting Q for this target, 1262 * that is affected by this busfree and we don't want to 1263 * go about selecting the target while we handle the event. 1264 */ 1265 ahd_outb(ahd, SCSISEQ0, 0); 1266 1267 /* 1268 * Determine what we were up to at the time of 1269 * the busfree. 1270 */ 1271 mode = AHD_MODE_SCSI; 1272 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; 1273 lqostat1 = ahd_inb(ahd, LQOSTAT1); 1274 switch (busfreetime) { 1275 case BUSFREE_DFF0: 1276 case BUSFREE_DFF1: 1277 { 1278 u_int scbid; 1279 struct scb *scb; 1280 1281 mode = busfreetime == BUSFREE_DFF0 1282 ? AHD_MODE_DFF0 : AHD_MODE_DFF1; 1283 ahd_set_modes(ahd, mode, mode); 1284 scbid = ahd_get_scbptr(ahd); 1285 scb = ahd_lookup_scb(ahd, scbid); 1286 if (scb == NULL) { 1287 printf("%s: Invalid SCB in DFF%d " 1288 "during unexpected busfree\n", 1289 ahd_name(ahd), mode); 1290 packetized = 0; 1291 } else 1292 packetized = (scb->flags & SCB_PACKETIZED) != 0; 1293 clear_fifo = 1; 1294 break; 1295 } 1296 case BUSFREE_LQO: 1297 clear_fifo = 0; 1298 packetized = 1; 1299 break; 1300 default: 1301 clear_fifo = 0; 1302 packetized = (lqostat1 & LQOBUSFREE) != 0; 1303 if (!packetized 1304 && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) 1305 packetized = 1; 1306 break; 1307 } 1308 1309 #ifdef AHD_DEBUG 1310 if ((ahd_debug & AHD_SHOW_MISC) != 0) 1311 printf("Saw Busfree. Busfreetime = 0x%x.\n", 1312 busfreetime); 1313 #endif 1314 /* 1315 * Busfrees that occur in non-packetized phases are 1316 * handled by the nonpkt_busfree handler. 1317 */ 1318 if (packetized && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) { 1319 restart = ahd_handle_pkt_busfree(ahd, busfreetime); 1320 } else { 1321 packetized = 0; 1322 restart = ahd_handle_nonpkt_busfree(ahd); 1323 } 1324 /* 1325 * Clear the busfree interrupt status. The setting of 1326 * the interrupt is a pulse, so in a perfect world, we 1327 * would not need to muck with the ENBUSFREE logic. This 1328 * would ensure that if the bus moves on to another 1329 * connection, busfree protection is still in force. If 1330 * BUSFREEREV is broken, however, we must manually clear 1331 * the ENBUSFREE if the busfree occurred during a non-pack 1332 * connection so that we don't get false positives during 1333 * future, packetized, connections. 1334 */ 1335 ahd_outb(ahd, CLRSINT1, CLRBUSFREE); 1336 if (packetized == 0 1337 && (ahd->bugs & AHD_BUSFREEREV_BUG) != 0) 1338 ahd_outb(ahd, SIMODE1, 1339 ahd_inb(ahd, SIMODE1) & ~ENBUSFREE); 1340 1341 if (clear_fifo) 1342 ahd_clear_fifo(ahd, mode); 1343 1344 ahd_clear_msg_state(ahd); 1345 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1346 if (restart) { 1347 ahd_restart(ahd); 1348 } else { 1349 ahd_unpause(ahd); 1350 } 1351 } else { 1352 printf("%s: Missing case in ahd_handle_scsiint. status = %x\n", 1353 ahd_name(ahd), status); 1354 ahd_dump_card_state(ahd); 1355 ahd_clear_intstat(ahd); 1356 ahd_unpause(ahd); 1357 } 1358 } 1359 1360 static void 1361 ahd_handle_transmission_error(struct ahd_softc *ahd) 1362 { 1363 struct scb *scb; 1364 u_int scbid; 1365 u_int lqistat1; 1366 u_int lqistat2; 1367 u_int msg_out; 1368 u_int curphase; 1369 u_int lastphase; 1370 u_int perrdiag; 1371 u_int cur_col; 1372 int silent; 1373 1374 scb = NULL; 1375 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1376 lqistat1 = ahd_inb(ahd, LQISTAT1) & ~(LQIPHASE_LQ|LQIPHASE_NLQ); 1377 lqistat2 = ahd_inb(ahd, LQISTAT2); 1378 if ((lqistat1 & (LQICRCI_NLQ|LQICRCI_LQ)) == 0 1379 && (ahd->bugs & AHD_NLQICRC_DELAYED_BUG) != 0) { 1380 u_int lqistate; 1381 1382 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 1383 lqistate = ahd_inb(ahd, LQISTATE); 1384 if ((lqistate >= 0x1E && lqistate <= 0x24) 1385 || (lqistate == 0x29)) { 1386 #ifdef AHD_DEBUG 1387 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1388 printf("%s: NLQCRC found via LQISTATE\n", 1389 ahd_name(ahd)); 1390 } 1391 #endif 1392 lqistat1 |= LQICRCI_NLQ; 1393 } 1394 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1395 } 1396 1397 ahd_outb(ahd, CLRLQIINT1, lqistat1); 1398 lastphase = ahd_inb(ahd, LASTPHASE); 1399 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1400 perrdiag = ahd_inb(ahd, PERRDIAG); 1401 msg_out = MSG_INITIATOR_DET_ERR; 1402 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR); 1403 1404 /* 1405 * Try to find the SCB associated with this error. 1406 */ 1407 silent = FALSE; 1408 if (lqistat1 == 0 1409 || (lqistat1 & LQICRCI_NLQ) != 0) { 1410 if ((lqistat1 & (LQICRCI_NLQ|LQIOVERI_NLQ)) != 0) 1411 ahd_set_active_fifo(ahd); 1412 scbid = ahd_get_scbptr(ahd); 1413 scb = ahd_lookup_scb(ahd, scbid); 1414 if (scb != NULL && SCB_IS_SILENT(scb)) 1415 silent = TRUE; 1416 } 1417 1418 cur_col = 0; 1419 if (silent == FALSE) { 1420 printf("%s: Transmission error detected\n", ahd_name(ahd)); 1421 ahd_lqistat1_print(lqistat1, &cur_col, 50); 1422 ahd_lastphase_print(lastphase, &cur_col, 50); 1423 ahd_scsisigi_print(curphase, &cur_col, 50); 1424 ahd_perrdiag_print(perrdiag, &cur_col, 50); 1425 printf("\n"); 1426 ahd_dump_card_state(ahd); 1427 } 1428 1429 if ((lqistat1 & (LQIOVERI_LQ|LQIOVERI_NLQ)) != 0) { 1430 if (silent == FALSE) { 1431 printf("%s: Gross protocol error during incoming " 1432 "packet. lqistat1 == 0x%x. Resetting bus.\n", 1433 ahd_name(ahd), lqistat1); 1434 } 1435 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1436 return; 1437 } else if ((lqistat1 & LQICRCI_LQ) != 0) { 1438 /* 1439 * A CRC error has been detected on an incoming LQ. 1440 * The bus is currently hung on the last ACK. 1441 * Hit LQIRETRY to release the last ack, and 1442 * wait for the sequencer to determine that ATNO 1443 * is asserted while in message out to take us 1444 * to our host message loop. No NONPACKREQ or 1445 * LQIPHASE type errors will occur in this 1446 * scenario. After this first LQIRETRY, the LQI 1447 * manager will be in ISELO where it will 1448 * happily sit until another packet phase begins. 1449 * Unexpected bus free detection is enabled 1450 * through any phases that occur after we release 1451 * this last ack until the LQI manager sees a 1452 * packet phase. This implies we may have to 1453 * ignore a perfectly valid "unexected busfree" 1454 * after our "initiator detected error" message is 1455 * sent. A busfree is the expected response after 1456 * we tell the target that it's L_Q was corrupted. 1457 * (SPI4R09 10.7.3.3.3) 1458 */ 1459 ahd_outb(ahd, LQCTL2, LQIRETRY); 1460 printf("LQIRetry for LQICRCI_LQ to release ACK\n"); 1461 } else if ((lqistat1 & LQICRCI_NLQ) != 0) { 1462 /* 1463 * We detected a CRC error in a NON-LQ packet. 1464 * The hardware has varying behavior in this situation 1465 * depending on whether this packet was part of a 1466 * stream or not. 1467 * 1468 * PKT by PKT mode: 1469 * The hardware has already acked the complete packet. 1470 * If the target honors our outstanding ATN condition, 1471 * we should be (or soon will be) in MSGOUT phase. 1472 * This will trigger the LQIPHASE_LQ status bit as the 1473 * hardware was expecting another LQ. Unexpected 1474 * busfree detection is enabled. Once LQIPHASE_LQ is 1475 * true (first entry into host message loop is much 1476 * the same), we must clear LQIPHASE_LQ and hit 1477 * LQIRETRY so the hardware is ready to handle 1478 * a future LQ. NONPACKREQ will not be asserted again 1479 * once we hit LQIRETRY until another packet is 1480 * processed. The target may either go busfree 1481 * or start another packet in response to our message. 1482 * 1483 * Read Streaming P0 asserted: 1484 * If we raise ATN and the target completes the entire 1485 * stream (P0 asserted during the last packet), the 1486 * hardware will ack all data and return to the ISTART 1487 * state. When the target reponds to our ATN condition, 1488 * LQIPHASE_LQ will be asserted. We should respond to 1489 * this with an LQIRETRY to prepare for any future 1490 * packets. NONPACKREQ will not be asserted again 1491 * once we hit LQIRETRY until another packet is 1492 * processed. The target may either go busfree or 1493 * start another packet in response to our message. 1494 * Busfree detection is enabled. 1495 * 1496 * Read Streaming P0 not asserted: 1497 * If we raise ATN and the target transitions to 1498 * MSGOUT in or after a packet where P0 is not 1499 * asserted, the hardware will assert LQIPHASE_NLQ. 1500 * We should respond to the LQIPHASE_NLQ with an 1501 * LQIRETRY. Should the target stay in a non-pkt 1502 * phase after we send our message, the hardware 1503 * will assert LQIPHASE_LQ. Recovery is then just as 1504 * listed above for the read streaming with P0 asserted. 1505 * Busfree detection is enabled. 1506 */ 1507 if (silent == FALSE) 1508 printf("LQICRC_NLQ\n"); 1509 if (scb == NULL) { 1510 printf("%s: No SCB valid for LQICRC_NLQ. " 1511 "Resetting bus\n", ahd_name(ahd)); 1512 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1513 return; 1514 } 1515 } else if ((lqistat1 & LQIBADLQI) != 0) { 1516 printf("Need to handle BADLQI!\n"); 1517 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1518 return; 1519 } else if ((perrdiag & (PARITYERR|PREVPHASE)) == PARITYERR) { 1520 if ((curphase & ~P_DATAIN_DT) != 0) { 1521 /* Ack the byte. So we can continue. */ 1522 if (silent == FALSE) 1523 printf("Acking %s to clear perror\n", 1524 ahd_lookup_phase_entry(curphase)->phasemsg); 1525 ahd_inb(ahd, SCSIDAT); 1526 } 1527 1528 if (curphase == P_MESGIN) 1529 msg_out = MSG_PARITY_ERROR; 1530 } 1531 1532 /* 1533 * We've set the hardware to assert ATN if we 1534 * get a parity error on "in" phases, so all we 1535 * need to do is stuff the message buffer with 1536 * the appropriate message. "In" phases have set 1537 * mesg_out to something other than MSG_NOP. 1538 */ 1539 ahd->send_msg_perror = msg_out; 1540 if (scb != NULL && msg_out == MSG_INITIATOR_DET_ERR) 1541 scb->flags |= SCB_TRANSMISSION_ERROR; 1542 ahd_outb(ahd, MSG_OUT, HOST_MSG); 1543 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1544 ahd_unpause(ahd); 1545 } 1546 1547 static void 1548 ahd_handle_lqiphase_error(struct ahd_softc *ahd, u_int lqistat1) 1549 { 1550 /* 1551 * Clear the sources of the interrupts. 1552 */ 1553 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1554 ahd_outb(ahd, CLRLQIINT1, lqistat1); 1555 1556 /* 1557 * If the "illegal" phase changes were in response 1558 * to our ATN to flag a CRC error, AND we ended up 1559 * on packet boundaries, clear the error, restart the 1560 * LQI manager as appropriate, and go on our merry 1561 * way toward sending the message. Otherwise, reset 1562 * the bus to clear the error. 1563 */ 1564 ahd_set_active_fifo(ahd); 1565 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0 1566 && (ahd_inb(ahd, MDFFSTAT) & DLZERO) != 0) { 1567 if ((lqistat1 & LQIPHASE_LQ) != 0) { 1568 printf("LQIRETRY for LQIPHASE_LQ\n"); 1569 ahd_outb(ahd, LQCTL2, LQIRETRY); 1570 } else if ((lqistat1 & LQIPHASE_NLQ) != 0) { 1571 printf("LQIRETRY for LQIPHASE_NLQ\n"); 1572 ahd_outb(ahd, LQCTL2, LQIRETRY); 1573 } else 1574 panic("ahd_handle_lqiphase_error: No phase errors\n"); 1575 ahd_dump_card_state(ahd); 1576 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1577 ahd_unpause(ahd); 1578 } else { 1579 printf("Reseting Channel for LQI Phase error\n"); 1580 ahd_dump_card_state(ahd); 1581 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1582 } 1583 } 1584 1585 /* 1586 * Packetized unexpected or expected busfree. 1587 * Entered in mode based on busfreetime. 1588 */ 1589 static int 1590 ahd_handle_pkt_busfree(struct ahd_softc *ahd, u_int busfreetime) 1591 { 1592 u_int lqostat1; 1593 1594 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 1595 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 1596 lqostat1 = ahd_inb(ahd, LQOSTAT1); 1597 if ((lqostat1 & LQOBUSFREE) != 0) { 1598 struct scb *scb; 1599 u_int scbid; 1600 u_int saved_scbptr; 1601 u_int waiting_h; 1602 u_int waiting_t; 1603 u_int next; 1604 1605 if ((busfreetime & BUSFREE_LQO) == 0) 1606 printf("%s: Warning, BUSFREE time is 0x%x. " 1607 "Expected BUSFREE_LQO.\n", 1608 ahd_name(ahd), busfreetime); 1609 /* 1610 * The LQO manager detected an unexpected busfree 1611 * either: 1612 * 1613 * 1) During an outgoing LQ. 1614 * 2) After an outgoing LQ but before the first 1615 * REQ of the command packet. 1616 * 3) During an outgoing command packet. 1617 * 1618 * In all cases, CURRSCB is pointing to the 1619 * SCB that encountered the failure. Clean 1620 * up the queue, clear SELDO and LQOBUSFREE, 1621 * and allow the sequencer to restart the select 1622 * out at its lesure. 1623 */ 1624 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1625 scbid = ahd_inw(ahd, CURRSCB); 1626 scb = ahd_lookup_scb(ahd, scbid); 1627 if (scb == NULL) 1628 panic("SCB not valid during LQOBUSFREE"); 1629 /* 1630 * Return the LQO manager to its idle loop. It will 1631 * not do this automatically if the busfree occurs 1632 * after the first REQ of either the LQ or command 1633 * packet or between the LQ and command packet. 1634 */ 1635 ahd_outb(ahd, LQCTL2, ahd_inb(ahd, LQCTL2) | LQOTOIDLE); 1636 1637 /* 1638 * Clear the status. 1639 */ 1640 ahd_outb(ahd, CLRLQOINT1, CLRLQOBUSFREE); 1641 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) 1642 ahd_outb(ahd, CLRLQOINT1, 0); 1643 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 1644 ahd_outb(ahd, CLRSINT0, CLRSELDO); 1645 1646 /* 1647 * Update the waiting for selection queue so 1648 * we restart on the correct SCB. 1649 */ 1650 waiting_h = ahd_inw(ahd, WAITING_TID_HEAD); 1651 saved_scbptr = ahd_get_scbptr(ahd); 1652 if (waiting_h != scbid) { 1653 1654 ahd_outw(ahd, WAITING_TID_HEAD, scbid); 1655 waiting_t = ahd_inw(ahd, WAITING_TID_TAIL); 1656 next = SCB_LIST_NULL; 1657 if (waiting_t == waiting_h) { 1658 ahd_outw(ahd, WAITING_TID_TAIL, scbid); 1659 } else { 1660 ahd_set_scbptr(ahd, waiting_h); 1661 next = ahd_inw(ahd, SCB_NEXT2); 1662 } 1663 ahd_set_scbptr(ahd, scbid); 1664 ahd_outw(ahd, SCB_NEXT2, next); 1665 } 1666 ahd_set_scbptr(ahd, saved_scbptr); 1667 if (scb->crc_retry_count < AHD_MAX_LQ_CRC_ERRORS) { 1668 if (SCB_IS_SILENT(scb) == FALSE) { 1669 ahd_print_path(ahd, scb); 1670 printf("Probable outgoing LQ CRC error. " 1671 "Retrying command\n"); 1672 } 1673 scb->crc_retry_count++; 1674 } else { 1675 ahd_set_transaction_status(scb, CAM_UNCOR_PARITY); 1676 ahd_freeze_scb(scb); 1677 ahd_freeze_devq(ahd, scb); 1678 } 1679 /* Return unpausing the sequencer. */ 1680 return (0); 1681 } else if ((ahd_inb(ahd, PERRDIAG) & PARITYERR) != 0) { 1682 /* 1683 * Ignore what are really parity errors that 1684 * occur on the last REQ of a free running 1685 * clock prior to going busfree. Some drives 1686 * do not properly active negate just before 1687 * going busfree resulting in a parity glitch. 1688 */ 1689 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR|CLRBUSFREE); 1690 #ifdef AHD_DEBUG 1691 if ((ahd_debug & AHD_SHOW_MASKED_ERRORS) != 0) 1692 printf("%s: Parity on last REQ detected " 1693 "during busfree phase.\n", 1694 ahd_name(ahd)); 1695 #endif 1696 /* Return unpausing the sequencer. */ 1697 return (0); 1698 } 1699 if (ahd->src_mode != AHD_MODE_SCSI) { 1700 u_int scbid; 1701 struct scb *scb; 1702 1703 scbid = ahd_get_scbptr(ahd); 1704 scb = ahd_lookup_scb(ahd, scbid); 1705 ahd_print_path(ahd, scb); 1706 printf("Unexpected PKT busfree condition\n"); 1707 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 'A', 1708 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1709 ROLE_INITIATOR, CAM_UNEXP_BUSFREE); 1710 1711 /* Return restarting the sequencer. */ 1712 return (1); 1713 } 1714 printf("%s: Unexpected PKT busfree condition\n", ahd_name(ahd)); 1715 ahd_dump_card_state(ahd); 1716 /* Restart the sequencer. */ 1717 return (1); 1718 } 1719 1720 /* 1721 * Non-packetized unexpected or expected busfree. 1722 */ 1723 static int 1724 ahd_handle_nonpkt_busfree(struct ahd_softc *ahd) 1725 { 1726 struct ahd_devinfo devinfo; 1727 struct scb *scb; 1728 u_int lastphase; 1729 u_int saved_scsiid; 1730 u_int saved_lun; 1731 u_int target; 1732 u_int initiator_role_id; 1733 u_int scbid; 1734 u_int ppr_busfree; 1735 int printerror; 1736 1737 /* 1738 * Look at what phase we were last in. If its message out, 1739 * chances are pretty good that the busfree was in response 1740 * to one of our abort requests. 1741 */ 1742 lastphase = ahd_inb(ahd, LASTPHASE); 1743 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); 1744 saved_lun = ahd_inb(ahd, SAVED_LUN); 1745 target = SCSIID_TARGET(ahd, saved_scsiid); 1746 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 1747 ahd_compile_devinfo(&devinfo, initiator_role_id, 1748 target, saved_lun, 'A', ROLE_INITIATOR); 1749 printerror = 1; 1750 1751 scbid = ahd_get_scbptr(ahd); 1752 scb = ahd_lookup_scb(ahd, scbid); 1753 if (scb != NULL 1754 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1755 scb = NULL; 1756 1757 ppr_busfree = (ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0; 1758 if (lastphase == P_MESGOUT) { 1759 u_int tag; 1760 1761 tag = SCB_LIST_NULL; 1762 if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT_TAG, TRUE) 1763 || ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT, TRUE)) { 1764 int found; 1765 int sent_msg; 1766 1767 if (scb == NULL) { 1768 ahd_print_devinfo(ahd, &devinfo); 1769 printf("Abort for unidentified " 1770 "connection completed.\n"); 1771 /* restart the sequencer. */ 1772 return (1); 1773 } 1774 sent_msg = ahd->msgout_buf[ahd->msgout_index - 1]; 1775 ahd_print_path(ahd, scb); 1776 printf("SCB %d - Abort%s Completed.\n", 1777 SCB_GET_TAG(scb), 1778 sent_msg == MSG_ABORT_TAG ? "" : " Tag"); 1779 1780 if (sent_msg == MSG_ABORT_TAG) 1781 tag = SCB_GET_TAG(scb); 1782 1783 if ((scb->flags & SCB_CMDPHASE_ABORT) != 0) { 1784 /* 1785 * This abort is in response to an 1786 * unexpected switch to command phase 1787 * for a packetized connection. Since 1788 * the identify message was never sent, 1789 * "saved lun" is 0. We really want to 1790 * abort only the SCB that encountered 1791 * this error, which could have a different 1792 * lun. The SCB will be retried so the OS 1793 * will see the UA after renegotiating to 1794 * packetized. 1795 */ 1796 tag = SCB_GET_TAG(scb); 1797 saved_lun = scb->hscb->lun; 1798 } 1799 found = ahd_abort_scbs(ahd, target, 'A', saved_lun, 1800 tag, ROLE_INITIATOR, 1801 CAM_REQ_ABORTED); 1802 printf("found == 0x%x\n", found); 1803 printerror = 0; 1804 } else if (ahd_sent_msg(ahd, AHDMSG_1B, 1805 MSG_BUS_DEV_RESET, TRUE)) { 1806 #ifdef __FreeBSD__ 1807 /* 1808 * Don't mark the user's request for this BDR 1809 * as completing with CAM_BDR_SENT. CAM3 1810 * specifies CAM_REQ_CMP. 1811 */ 1812 if (scb != NULL 1813 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 1814 && ahd_match_scb(ahd, scb, target, 'A', 1815 CAM_LUN_WILDCARD, SCB_LIST_NULL, 1816 ROLE_INITIATOR)) 1817 ahd_set_transaction_status(scb, CAM_REQ_CMP); 1818 #endif 1819 ahd_handle_devreset(ahd, &devinfo, CAM_LUN_WILDCARD, 1820 CAM_BDR_SENT, "Bus Device Reset", 1821 /*verbose_level*/0); 1822 printerror = 0; 1823 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, FALSE) 1824 && ppr_busfree == 0) { 1825 struct ahd_initiator_tinfo *tinfo; 1826 struct ahd_tmode_tstate *tstate; 1827 1828 /* 1829 * PPR Rejected. Try non-ppr negotiation 1830 * and retry command. 1831 */ 1832 #ifdef AHD_DEBUG 1833 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1834 printf("PPR negotiation rejected busfree.\n"); 1835 #endif 1836 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel, 1837 devinfo.our_scsiid, 1838 devinfo.target, &tstate); 1839 tinfo->curr.transport_version = 2; 1840 tinfo->goal.transport_version = 2; 1841 tinfo->goal.ppr_options = 0; 1842 ahd_qinfifo_requeue_tail(ahd, scb); 1843 printerror = 0; 1844 } else if ((ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, FALSE) 1845 || ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, FALSE)) 1846 && ppr_busfree == 0) { 1847 /* 1848 * Negotiation Rejected. Go-async and 1849 * retry command. 1850 */ 1851 #ifdef AHD_DEBUG 1852 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1853 printf("Negotiation rejected busfree.\n"); 1854 #endif 1855 ahd_set_width(ahd, &devinfo, 1856 MSG_EXT_WDTR_BUS_8_BIT, 1857 AHD_TRANS_CUR|AHD_TRANS_GOAL, 1858 /*paused*/TRUE); 1859 ahd_set_syncrate(ahd, &devinfo, 1860 /*period*/0, /*offset*/0, 1861 /*ppr_options*/0, 1862 AHD_TRANS_CUR|AHD_TRANS_GOAL, 1863 /*paused*/TRUE); 1864 ahd_qinfifo_requeue_tail(ahd, scb); 1865 printerror = 0; 1866 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_IDE_BUSFREE) != 0 1867 && ahd_sent_msg(ahd, AHDMSG_1B, 1868 MSG_INITIATOR_DET_ERR, TRUE)) { 1869 1870 #ifdef AHD_DEBUG 1871 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1872 printf("Expected IDE Busfree\n"); 1873 #endif 1874 printerror = 0; 1875 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_QASREJ_BUSFREE) 1876 && ahd_sent_msg(ahd, AHDMSG_1B, 1877 MSG_MESSAGE_REJECT, TRUE)) { 1878 1879 #ifdef AHD_DEBUG 1880 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1881 printf("Expected QAS Reject Busfree\n"); 1882 #endif 1883 printerror = 0; 1884 } 1885 } 1886 1887 /* 1888 * The busfree required flag is honored at the end of 1889 * the message phases. We check it last in case we 1890 * had to send some other message that caused a busfree. 1891 */ 1892 if (printerror != 0 1893 && (lastphase == P_MESGIN || lastphase == P_MESGOUT) 1894 && ((ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0)) { 1895 1896 ahd_freeze_devq(ahd, scb); 1897 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ); 1898 ahd_freeze_scb(scb); 1899 if ((ahd->msg_flags & MSG_FLAG_IU_REQ_CHANGED) != 0) { 1900 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 1901 SCB_GET_CHANNEL(ahd, scb), 1902 SCB_GET_LUN(scb), SCB_LIST_NULL, 1903 ROLE_INITIATOR, CAM_REQ_ABORTED); 1904 } else { 1905 #ifdef AHD_DEBUG 1906 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 1907 printf("PPR Negotiation Busfree.\n"); 1908 #endif 1909 ahd_done(ahd, scb); 1910 } 1911 printerror = 0; 1912 } 1913 if (printerror != 0) { 1914 int aborted; 1915 1916 aborted = 0; 1917 if (scb != NULL) { 1918 u_int tag; 1919 1920 if ((scb->hscb->control & TAG_ENB) != 0) 1921 tag = SCB_GET_TAG(scb); 1922 else 1923 tag = SCB_LIST_NULL; 1924 ahd_print_path(ahd, scb); 1925 aborted = ahd_abort_scbs(ahd, target, 'A', 1926 SCB_GET_LUN(scb), tag, 1927 ROLE_INITIATOR, 1928 CAM_UNEXP_BUSFREE); 1929 } else { 1930 /* 1931 * We had not fully identified this connection, 1932 * so we cannot abort anything. 1933 */ 1934 printf("%s: ", ahd_name(ahd)); 1935 } 1936 if (lastphase != P_BUSFREE) 1937 ahd_force_renegotiation(ahd, &devinfo); 1938 printf("Unexpected busfree %s, %d SCBs aborted, " 1939 "PRGMCNT == 0x%x\n", 1940 ahd_lookup_phase_entry(lastphase)->phasemsg, 1941 aborted, 1942 ahd_inb(ahd, PRGMCNT) 1943 | (ahd_inb(ahd, PRGMCNT+1) << 8)); 1944 ahd_dump_card_state(ahd); 1945 } 1946 /* Always restart the sequencer. */ 1947 return (1); 1948 } 1949 1950 static void 1951 ahd_handle_proto_violation(struct ahd_softc *ahd) 1952 { 1953 struct ahd_devinfo devinfo; 1954 struct scb *scb; 1955 u_int scbid; 1956 u_int seq_flags; 1957 u_int curphase; 1958 u_int lastphase; 1959 int found; 1960 1961 ahd_fetch_devinfo(ahd, &devinfo); 1962 scbid = ahd_get_scbptr(ahd); 1963 scb = ahd_lookup_scb(ahd, scbid); 1964 seq_flags = ahd_inb(ahd, SEQ_FLAGS); 1965 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1966 lastphase = ahd_inb(ahd, LASTPHASE); 1967 if ((seq_flags & NOT_IDENTIFIED) != 0) { 1968 1969 /* 1970 * The reconnecting target either did not send an 1971 * identify message, or did, but we didn't find an SCB 1972 * to match. 1973 */ 1974 ahd_print_devinfo(ahd, &devinfo); 1975 printf("Target did not send an IDENTIFY message. " 1976 "LASTPHASE = 0x%x.\n", lastphase); 1977 scb = NULL; 1978 } else if (scb == NULL) { 1979 /* 1980 * We don't seem to have an SCB active for this 1981 * transaction. Print an error and reset the bus. 1982 */ 1983 ahd_print_devinfo(ahd, &devinfo); 1984 printf("No SCB found during protocol violation\n"); 1985 goto proto_violation_reset; 1986 } else { 1987 ahd_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 1988 if ((seq_flags & NO_CDB_SENT) != 0) { 1989 ahd_print_path(ahd, scb); 1990 printf("No or incomplete CDB sent to device.\n"); 1991 } else if ((ahd_inb(ahd, SCB_CONTROL) & STATUS_RCVD) == 0) { 1992 /* 1993 * The target never bothered to provide status to 1994 * us prior to completing the command. Since we don't 1995 * know the disposition of this command, we must attempt 1996 * to abort it. Assert ATN and prepare to send an abort 1997 * message. 1998 */ 1999 ahd_print_path(ahd, scb); 2000 printf("Completed command without status.\n"); 2001 } else { 2002 ahd_print_path(ahd, scb); 2003 printf("Unknown protocol violation.\n"); 2004 ahd_dump_card_state(ahd); 2005 } 2006 } 2007 if ((lastphase & ~P_DATAIN_DT) == 0 2008 || lastphase == P_COMMAND) { 2009 proto_violation_reset: 2010 /* 2011 * Target either went directly to data 2012 * phase or didn't respond to our ATN. 2013 * The only safe thing to do is to blow 2014 * it away with a bus reset. 2015 */ 2016 found = ahd_reset_channel(ahd, 'A', TRUE); 2017 printf("%s: Issued Channel %c Bus Reset. " 2018 "%d SCBs aborted\n", ahd_name(ahd), 'A', found); 2019 } else { 2020 /* 2021 * Leave the selection hardware off in case 2022 * this abort attempt will affect yet to 2023 * be sent commands. 2024 */ 2025 ahd_outb(ahd, SCSISEQ0, 2026 ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 2027 ahd_assert_atn(ahd); 2028 ahd_outb(ahd, MSG_OUT, HOST_MSG); 2029 if (scb == NULL) { 2030 ahd_print_devinfo(ahd, &devinfo); 2031 ahd->msgout_buf[0] = MSG_ABORT_TASK; 2032 ahd->msgout_len = 1; 2033 ahd->msgout_index = 0; 2034 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2035 } else { 2036 ahd_print_path(ahd, scb); 2037 scb->flags |= SCB_ABORT; 2038 } 2039 printf("Protocol violation %s. Attempting to abort.\n", 2040 ahd_lookup_phase_entry(curphase)->phasemsg); 2041 } 2042 } 2043 2044 /* 2045 * Force renegotiation to occur the next time we initiate 2046 * a command to the current device. 2047 */ 2048 static void 2049 ahd_force_renegotiation(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 2050 { 2051 struct ahd_initiator_tinfo *targ_info; 2052 struct ahd_tmode_tstate *tstate; 2053 2054 #ifdef AHD_DEBUG 2055 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 2056 ahd_print_devinfo(ahd, devinfo); 2057 printf("Forcing renegotiation\n"); 2058 } 2059 #endif 2060 targ_info = ahd_fetch_transinfo(ahd, 2061 devinfo->channel, 2062 devinfo->our_scsiid, 2063 devinfo->target, 2064 &tstate); 2065 ahd_update_neg_request(ahd, devinfo, tstate, 2066 targ_info, AHD_NEG_IF_NON_ASYNC); 2067 } 2068 2069 #define AHD_MAX_STEPS 2000 2070 void 2071 ahd_clear_critical_section(struct ahd_softc *ahd) 2072 { 2073 ahd_mode_state saved_modes; 2074 int stepping; 2075 int steps; 2076 int first_instr; 2077 u_int simode0; 2078 u_int simode1; 2079 u_int simode3; 2080 u_int lqimode0; 2081 u_int lqimode1; 2082 u_int lqomode0; 2083 u_int lqomode1; 2084 2085 if (ahd->num_critical_sections == 0) 2086 return; 2087 2088 stepping = FALSE; 2089 steps = 0; 2090 first_instr = 0; 2091 simode0 = 0; 2092 simode1 = 0; 2093 simode3 = 0; 2094 lqimode0 = 0; 2095 lqimode1 = 0; 2096 lqomode0 = 0; 2097 lqomode1 = 0; 2098 saved_modes = ahd_save_modes(ahd); 2099 for (;;) { 2100 struct cs *cs; 2101 u_int seqaddr; 2102 u_int i; 2103 2104 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2105 seqaddr = ahd_inb(ahd, CURADDR) 2106 | (ahd_inb(ahd, CURADDR+1) << 8); 2107 2108 cs = ahd->critical_sections; 2109 for (i = 0; i < ahd->num_critical_sections; i++, cs++) { 2110 2111 if (cs->begin < seqaddr && cs->end >= seqaddr) 2112 break; 2113 } 2114 2115 if (i == ahd->num_critical_sections) 2116 break; 2117 2118 if (steps > AHD_MAX_STEPS) { 2119 printf("%s: Infinite loop in critical section\n" 2120 "%s: First Instruction 0x%x now 0x%x\n", 2121 ahd_name(ahd), ahd_name(ahd), first_instr, 2122 seqaddr); 2123 ahd_dump_card_state(ahd); 2124 panic("critical section loop"); 2125 } 2126 2127 steps++; 2128 #ifdef AHD_DEBUG 2129 if ((ahd_debug & AHD_SHOW_MISC) != 0) 2130 printf("%s: Single stepping at 0x%x\n", ahd_name(ahd), 2131 seqaddr); 2132 #endif 2133 if (stepping == FALSE) { 2134 2135 first_instr = seqaddr; 2136 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 2137 simode0 = ahd_inb(ahd, SIMODE0); 2138 simode3 = ahd_inb(ahd, SIMODE3); 2139 lqimode0 = ahd_inb(ahd, LQIMODE0); 2140 lqimode1 = ahd_inb(ahd, LQIMODE1); 2141 lqomode0 = ahd_inb(ahd, LQOMODE0); 2142 lqomode1 = ahd_inb(ahd, LQOMODE1); 2143 ahd_outb(ahd, SIMODE0, 0); 2144 ahd_outb(ahd, SIMODE3, 0); 2145 ahd_outb(ahd, LQIMODE0, 0); 2146 ahd_outb(ahd, LQIMODE1, 0); 2147 ahd_outb(ahd, LQOMODE0, 0); 2148 ahd_outb(ahd, LQOMODE1, 0); 2149 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2150 simode1 = ahd_inb(ahd, SIMODE1); 2151 ahd_outb(ahd, SIMODE1, ENBUSFREE); 2152 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) | STEP); 2153 stepping = TRUE; 2154 } 2155 ahd_outb(ahd, CLRSINT1, CLRBUSFREE); 2156 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2157 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 2158 ahd_outb(ahd, HCNTRL, ahd->unpause); 2159 do { 2160 ahd_delay(200); 2161 } while (!ahd_is_paused(ahd)); 2162 ahd_update_modes(ahd); 2163 } 2164 if (stepping) { 2165 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 2166 ahd_outb(ahd, SIMODE0, simode0); 2167 ahd_outb(ahd, SIMODE3, simode3); 2168 ahd_outb(ahd, LQIMODE0, lqimode0); 2169 ahd_outb(ahd, LQIMODE1, lqimode1); 2170 ahd_outb(ahd, LQOMODE0, lqomode0); 2171 ahd_outb(ahd, LQOMODE1, lqomode1); 2172 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2173 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP); 2174 ahd_outb(ahd, SIMODE1, simode1); 2175 } 2176 ahd_restore_modes(ahd, saved_modes); 2177 } 2178 2179 /* 2180 * Clear any pending interrupt status. 2181 */ 2182 void 2183 ahd_clear_intstat(struct ahd_softc *ahd) 2184 { 2185 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 2186 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 2187 /* Clear any interrupt conditions this may have caused */ 2188 ahd_outb(ahd, CLRLQIINT0, CLRLQIATNQAS|CLRLQICRCT1|CLRLQICRCT2 2189 |CLRLQIBADLQT|CLRLQIATNLQ|CLRLQIATNCMD); 2190 ahd_outb(ahd, CLRLQIINT1, CLRLQIPHASE_LQ|CLRLQIPHASE_NLQ|CLRLIQABORT 2191 |CLRLQICRCI_LQ|CLRLQICRCI_NLQ|CLRLQIBADLQI 2192 |CLRLQIOVERI_LQ|CLRLQIOVERI_NLQ|CLRNONPACKREQ); 2193 ahd_outb(ahd, CLRLQOINT0, CLRLQOTARGSCBPERR|CLRLQOSTOPT2|CLRLQOATNLQ 2194 |CLRLQOATNPKT|CLRLQOTCRC); 2195 ahd_outb(ahd, CLRLQOINT1, CLRLQOINITSCBPERR|CLRLQOSTOPI2|CLRLQOBADQAS 2196 |CLRLQOBUSFREE|CLRLQOPHACHGINPKT); 2197 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 2198 ahd_outb(ahd, CLRLQOINT0, 0); 2199 ahd_outb(ahd, CLRLQOINT1, 0); 2200 } 2201 ahd_outb(ahd, CLRSINT3, CLRNTRAMPERR|CLROSRAMPERR); 2202 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 2203 |CLRBUSFREE|CLRSCSIPERR|CLRREQINIT); 2204 ahd_outb(ahd, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO 2205 |CLRIOERR|CLROVERRUN); 2206 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2207 } 2208 2209 /**************************** Debugging Routines ******************************/ 2210 #ifdef AHD_DEBUG 2211 uint32_t ahd_debug = AHD_DEBUG_OPTS; 2212 #endif 2213 void 2214 ahd_print_scb(struct scb *scb) 2215 { 2216 struct hardware_scb *hscb; 2217 int i; 2218 2219 hscb = scb->hscb; 2220 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 2221 (void *)scb, 2222 hscb->control, 2223 hscb->scsiid, 2224 hscb->lun, 2225 hscb->cdb_len); 2226 printf("Shared Data: "); 2227 for (i = 0; i < sizeof(hscb->shared_data.idata.cdb); i++) 2228 printf("%#02x", hscb->shared_data.idata.cdb[i]); 2229 printf(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n", 2230 (uint32_t)((ahd_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF), 2231 (uint32_t)(ahd_le64toh(hscb->dataptr) & 0xFFFFFFFF), 2232 ahd_le32toh(hscb->datacnt), 2233 ahd_le32toh(hscb->sgptr), 2234 SCB_GET_TAG(scb)); 2235 ahd_dump_sglist(scb); 2236 } 2237 2238 void 2239 ahd_dump_sglist(struct scb *scb) 2240 { 2241 int i; 2242 2243 if (scb->sg_count > 0) { 2244 if ((scb->ahd_softc->flags & AHD_64BIT_ADDRESSING) != 0) { 2245 struct ahd_dma64_seg *sg_list; 2246 2247 sg_list = (struct ahd_dma64_seg*)scb->sg_list; 2248 for (i = 0; i < scb->sg_count; i++) { 2249 uint64_t addr; 2250 uint32_t len; 2251 2252 addr = ahd_le64toh(sg_list[i].addr); 2253 len = ahd_le32toh(sg_list[i].len); 2254 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n", 2255 i, 2256 (uint32_t)((addr >> 32) & 0xFFFFFFFF), 2257 (uint32_t)(addr & 0xFFFFFFFF), 2258 sg_list[i].len & AHD_SG_LEN_MASK, 2259 (sg_list[i].len & AHD_DMA_LAST_SEG) 2260 ? " Last" : ""); 2261 } 2262 } else { 2263 struct ahd_dma_seg *sg_list; 2264 2265 sg_list = (struct ahd_dma_seg*)scb->sg_list; 2266 for (i = 0; i < scb->sg_count; i++) { 2267 uint32_t len; 2268 2269 len = ahd_le32toh(sg_list[i].len); 2270 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n", 2271 i, 2272 (len >> 24) & SG_HIGH_ADDR_BITS, 2273 ahd_le32toh(sg_list[i].addr), 2274 len & AHD_SG_LEN_MASK, 2275 len & AHD_DMA_LAST_SEG ? " Last" : ""); 2276 } 2277 } 2278 } 2279 } 2280 2281 /************************* Transfer Negotiation *******************************/ 2282 /* 2283 * Allocate per target mode instance (ID we respond to as a target) 2284 * transfer negotiation data structures. 2285 */ 2286 static struct ahd_tmode_tstate * 2287 ahd_alloc_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel) 2288 { 2289 struct ahd_tmode_tstate *master_tstate; 2290 struct ahd_tmode_tstate *tstate; 2291 int i; 2292 2293 master_tstate = ahd->enabled_targets[ahd->our_id]; 2294 if (ahd->enabled_targets[scsi_id] != NULL 2295 && ahd->enabled_targets[scsi_id] != master_tstate) 2296 panic("%s: ahd_alloc_tstate - Target already allocated", 2297 ahd_name(ahd)); 2298 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); 2299 if (tstate == NULL) 2300 return (NULL); 2301 2302 /* 2303 * If we have allocated a master tstate, copy user settings from 2304 * the master tstate (taken from SRAM or the EEPROM) for this 2305 * channel, but reset our current and goal settings to async/narrow 2306 * until an initiator talks to us. 2307 */ 2308 if (master_tstate != NULL) { 2309 memcpy(tstate, master_tstate, sizeof(*tstate)); 2310 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 2311 for (i = 0; i < 16; i++) { 2312 memset(&tstate->transinfo[i].curr, 0, 2313 sizeof(tstate->transinfo[i].curr)); 2314 memset(&tstate->transinfo[i].goal, 0, 2315 sizeof(tstate->transinfo[i].goal)); 2316 } 2317 } else 2318 memset(tstate, 0, sizeof(*tstate)); 2319 ahd->enabled_targets[scsi_id] = tstate; 2320 return (tstate); 2321 } 2322 2323 #ifdef AHD_TARGET_MODE 2324 /* 2325 * Free per target mode instance (ID we respond to as a target) 2326 * transfer negotiation data structures. 2327 */ 2328 static void 2329 ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force) 2330 { 2331 struct ahd_tmode_tstate *tstate; 2332 2333 /* 2334 * Don't clean up our "master" tstate. 2335 * It has our default user settings. 2336 */ 2337 if (scsi_id == ahd->our_id 2338 && force == FALSE) 2339 return; 2340 2341 tstate = ahd->enabled_targets[scsi_id]; 2342 if (tstate != NULL) 2343 free(tstate, M_DEVBUF); 2344 ahd->enabled_targets[scsi_id] = NULL; 2345 } 2346 #endif 2347 2348 /* 2349 * Called when we have an active connection to a target on the bus, 2350 * this function finds the nearest period to the input period limited 2351 * by the capabilities of the bus connectivity of and sync settings for 2352 * the target. 2353 */ 2354 void 2355 ahd_devlimited_syncrate(struct ahd_softc *ahd, 2356 struct ahd_initiator_tinfo *tinfo, 2357 u_int *period, u_int *ppr_options, role_t role) 2358 { 2359 struct ahd_transinfo *transinfo; 2360 u_int maxsync; 2361 2362 if ((ahd_inb(ahd, SBLKCTL) & ENAB40) != 0 2363 && (ahd_inb(ahd, SSTAT2) & EXP_ACTIVE) == 0) { 2364 maxsync = AHD_SYNCRATE_PACED; 2365 } else { 2366 maxsync = AHD_SYNCRATE_ULTRA; 2367 /* Can't do DT related options on an SE bus */ 2368 *ppr_options &= MSG_EXT_PPR_QAS_REQ; 2369 } 2370 /* 2371 * Never allow a value higher than our current goal 2372 * period otherwise we may allow a target initiated 2373 * negotiation to go above the limit as set by the 2374 * user. In the case of an initiator initiated 2375 * sync negotiation, we limit based on the user 2376 * setting. This allows the system to still accept 2377 * incoming negotiations even if target initiated 2378 * negotiation is not performed. 2379 */ 2380 if (role == ROLE_TARGET) 2381 transinfo = &tinfo->user; 2382 else 2383 transinfo = &tinfo->goal; 2384 *ppr_options &= (transinfo->ppr_options|MSG_EXT_PPR_PCOMP_EN); 2385 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 2386 maxsync = MAX(maxsync, AHD_SYNCRATE_ULTRA2); 2387 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2388 } 2389 if (transinfo->period == 0) { 2390 *period = 0; 2391 *ppr_options = 0; 2392 } else { 2393 *period = MAX(*period, transinfo->period); 2394 ahd_find_syncrate(ahd, period, ppr_options, maxsync); 2395 } 2396 } 2397 2398 /* 2399 * Look up the valid period to SCSIRATE conversion in our table. 2400 * Return the period and offset that should be sent to the target 2401 * if this was the beginning of an SDTR. 2402 */ 2403 void 2404 ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 2405 u_int *ppr_options, u_int maxsync) 2406 { 2407 if (*period < maxsync) 2408 *period = maxsync; 2409 2410 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) != 0 2411 && *period > AHD_SYNCRATE_MIN_DT) 2412 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2413 2414 if (*period > AHD_SYNCRATE_MIN) 2415 *period = 0; 2416 2417 /* Honor PPR option conformance rules. */ 2418 if (*period > AHD_SYNCRATE_PACED) 2419 *ppr_options &= ~MSG_EXT_PPR_RTI; 2420 2421 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0) 2422 *ppr_options &= (MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_QAS_REQ); 2423 2424 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0) 2425 *ppr_options &= MSG_EXT_PPR_QAS_REQ; 2426 2427 /* Skip all PACED only entries if IU is not available */ 2428 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0 2429 && *period < AHD_SYNCRATE_DT) 2430 *period = AHD_SYNCRATE_DT; 2431 2432 /* Skip all DT only entries if DT is not available */ 2433 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 2434 && *period < AHD_SYNCRATE_ULTRA2) 2435 *period = AHD_SYNCRATE_ULTRA2; 2436 } 2437 2438 /* 2439 * Truncate the given synchronous offset to a value the 2440 * current adapter type and syncrate are capable of. 2441 */ 2442 void 2443 ahd_validate_offset(struct ahd_softc *ahd, 2444 struct ahd_initiator_tinfo *tinfo, 2445 u_int period, u_int *offset, int wide, 2446 role_t role) 2447 { 2448 u_int maxoffset; 2449 2450 /* Limit offset to what we can do */ 2451 if (period == 0) 2452 maxoffset = 0; 2453 else if (period <= AHD_SYNCRATE_PACED) { 2454 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) 2455 maxoffset = MAX_OFFSET_PACED_BUG; 2456 else 2457 maxoffset = MAX_OFFSET_PACED; 2458 } else 2459 maxoffset = MAX_OFFSET_NON_PACED; 2460 *offset = MIN(*offset, maxoffset); 2461 if (tinfo != NULL) { 2462 if (role == ROLE_TARGET) 2463 *offset = MIN(*offset, tinfo->user.offset); 2464 else 2465 *offset = MIN(*offset, tinfo->goal.offset); 2466 } 2467 } 2468 2469 /* 2470 * Truncate the given transfer width parameter to a value the 2471 * current adapter type is capable of. 2472 */ 2473 void 2474 ahd_validate_width(struct ahd_softc *ahd, struct ahd_initiator_tinfo *tinfo, 2475 u_int *bus_width, role_t role) 2476 { 2477 switch (*bus_width) { 2478 default: 2479 if (ahd->features & AHD_WIDE) { 2480 /* Respond Wide */ 2481 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 2482 break; 2483 } 2484 /* FALLTHROUGH */ 2485 case MSG_EXT_WDTR_BUS_8_BIT: 2486 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 2487 break; 2488 } 2489 if (tinfo != NULL) { 2490 if (role == ROLE_TARGET) 2491 *bus_width = MIN(tinfo->user.width, *bus_width); 2492 else 2493 *bus_width = MIN(tinfo->goal.width, *bus_width); 2494 } 2495 } 2496 2497 /* 2498 * Update the bitmask of targets for which the controller should 2499 * negotiate with at the next convenient oportunity. This currently 2500 * means the next time we send the initial identify messages for 2501 * a new transaction. 2502 */ 2503 int 2504 ahd_update_neg_request(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2505 struct ahd_tmode_tstate *tstate, 2506 struct ahd_initiator_tinfo *tinfo, ahd_neg_type neg_type) 2507 { 2508 u_int auto_negotiate_orig; 2509 2510 auto_negotiate_orig = tstate->auto_negotiate; 2511 if (neg_type == AHD_NEG_ALWAYS) { 2512 /* 2513 * Force our "current" settings to be 2514 * unknown so that unless a bus reset 2515 * occurs the need to renegotiate is 2516 * recorded persistently. 2517 */ 2518 if ((ahd->features & AHD_WIDE) != 0) 2519 tinfo->curr.width = AHD_WIDTH_UNKNOWN; 2520 tinfo->curr.period = AHD_PERIOD_UNKNOWN; 2521 tinfo->curr.offset = AHD_OFFSET_UNKNOWN; 2522 } 2523 if (tinfo->curr.period != tinfo->goal.period 2524 || tinfo->curr.width != tinfo->goal.width 2525 || tinfo->curr.offset != tinfo->goal.offset 2526 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 2527 || (neg_type == AHD_NEG_IF_NON_ASYNC 2528 && (tinfo->goal.offset != 0 2529 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 2530 || tinfo->goal.ppr_options != 0))) 2531 tstate->auto_negotiate |= devinfo->target_mask; 2532 else 2533 tstate->auto_negotiate &= ~devinfo->target_mask; 2534 2535 return (auto_negotiate_orig != tstate->auto_negotiate); 2536 } 2537 2538 /* 2539 * Update the user/goal/curr tables of synchronous negotiation 2540 * parameters as well as, in the case of a current or active update, 2541 * any data structures on the host controller. In the case of an 2542 * active update, the specified target is currently talking to us on 2543 * the bus, so the transfer parameter update must take effect 2544 * immediately. 2545 */ 2546 void 2547 ahd_set_syncrate(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2548 u_int period, u_int offset, u_int ppr_options, 2549 u_int type, int paused) 2550 { 2551 struct ahd_initiator_tinfo *tinfo; 2552 struct ahd_tmode_tstate *tstate; 2553 u_int old_period; 2554 u_int old_offset; 2555 u_int old_ppr; 2556 int active; 2557 int update_needed; 2558 2559 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; 2560 update_needed = 0; 2561 2562 if (period == 0 || offset == 0) { 2563 period = 0; 2564 offset = 0; 2565 } 2566 2567 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 2568 devinfo->target, &tstate); 2569 2570 if ((type & AHD_TRANS_USER) != 0) { 2571 tinfo->user.period = period; 2572 tinfo->user.offset = offset; 2573 tinfo->user.ppr_options = ppr_options; 2574 } 2575 2576 if ((type & AHD_TRANS_GOAL) != 0) { 2577 tinfo->goal.period = period; 2578 tinfo->goal.offset = offset; 2579 tinfo->goal.ppr_options = ppr_options; 2580 } 2581 2582 old_period = tinfo->curr.period; 2583 old_offset = tinfo->curr.offset; 2584 old_ppr = tinfo->curr.ppr_options; 2585 2586 if ((type & AHD_TRANS_CUR) != 0 2587 && (old_period != period 2588 || old_offset != offset 2589 || old_ppr != ppr_options)) { 2590 2591 update_needed++; 2592 2593 tinfo->curr.period = period; 2594 tinfo->curr.offset = offset; 2595 tinfo->curr.ppr_options = ppr_options; 2596 2597 ahd_send_async(ahd, devinfo->channel, devinfo->target, 2598 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2599 if (bootverbose) { 2600 if (offset != 0) { 2601 int options; 2602 2603 printf("%s: target %d synchronous with " 2604 "period = 0x%x, offset = 0x%x", 2605 ahd_name(ahd), devinfo->target, 2606 period, offset); 2607 options = 0; 2608 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) { 2609 printf("(DT"); 2610 options++; 2611 } 2612 if ((ppr_options & MSG_EXT_PPR_IU_REQ) != 0) { 2613 printf("%s", options ? "|IU" : "(IU"); 2614 options++; 2615 } 2616 if ((ppr_options & MSG_EXT_PPR_RTI) != 0) { 2617 printf("%s", options ? "|RTI" : "(RTI"); 2618 options++; 2619 } 2620 if ((ppr_options & MSG_EXT_PPR_QAS_REQ) != 0) { 2621 printf("%s", options ? "|QAS" : "(QAS"); 2622 options++; 2623 } 2624 if (options != 0) 2625 printf(")\n"); 2626 else 2627 printf("\n"); 2628 } else { 2629 printf("%s: target %d using " 2630 "asynchronous transfers%s\n", 2631 ahd_name(ahd), devinfo->target, 2632 (ppr_options & MSG_EXT_PPR_QAS_REQ) != 0 2633 ? "(QAS)" : ""); 2634 } 2635 } 2636 } 2637 /* 2638 * Always refresh the neg-table to handle the case of the 2639 * sequencer setting the ENATNO bit for a MK_MESSAGE request. 2640 * We will always renegotiate in that case if this is a 2641 * packetized request. Also manage the busfree expected flag 2642 * from this common routine so that we catch changes due to 2643 * WDTR or SDTR messages. 2644 */ 2645 if ((type & AHD_TRANS_CUR) != 0) { 2646 if (!paused) 2647 ahd_pause(ahd); 2648 ahd_update_neg_table(ahd, devinfo, &tinfo->curr); 2649 if (!paused) 2650 ahd_unpause(ahd); 2651 if (ahd->msg_type != MSG_TYPE_NONE) { 2652 if ((old_ppr & MSG_EXT_PPR_IU_REQ) 2653 != (ppr_options & MSG_EXT_PPR_IU_REQ)) { 2654 #ifdef AHD_DEBUG 2655 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 2656 ahd_print_devinfo(ahd, devinfo); 2657 printf("Expecting IU Change busfree\n"); 2658 } 2659 #endif 2660 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE 2661 | MSG_FLAG_IU_REQ_CHANGED; 2662 } 2663 if ((old_ppr & MSG_EXT_PPR_IU_REQ) != 0) { 2664 #ifdef AHD_DEBUG 2665 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2666 printf("PPR with IU_REQ outstanding\n"); 2667 #endif 2668 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE; 2669 } 2670 } 2671 } 2672 2673 update_needed += ahd_update_neg_request(ahd, devinfo, tstate, 2674 tinfo, AHD_NEG_TO_GOAL); 2675 2676 if (update_needed && active) 2677 ahd_update_pending_scbs(ahd); 2678 } 2679 2680 /* 2681 * Update the user/goal/curr tables of wide negotiation 2682 * parameters as well as, in the case of a current or active update, 2683 * any data structures on the host controller. In the case of an 2684 * active update, the specified target is currently talking to us on 2685 * the bus, so the transfer parameter update must take effect 2686 * immediately. 2687 */ 2688 void 2689 ahd_set_width(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2690 u_int width, u_int type, int paused) 2691 { 2692 struct ahd_initiator_tinfo *tinfo; 2693 struct ahd_tmode_tstate *tstate; 2694 u_int oldwidth; 2695 int active; 2696 int update_needed; 2697 2698 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; 2699 update_needed = 0; 2700 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 2701 devinfo->target, &tstate); 2702 2703 if ((type & AHD_TRANS_USER) != 0) 2704 tinfo->user.width = width; 2705 2706 if ((type & AHD_TRANS_GOAL) != 0) 2707 tinfo->goal.width = width; 2708 2709 oldwidth = tinfo->curr.width; 2710 if ((type & AHD_TRANS_CUR) != 0 && oldwidth != width) { 2711 2712 update_needed++; 2713 2714 tinfo->curr.width = width; 2715 ahd_send_async(ahd, devinfo->channel, devinfo->target, 2716 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 2717 if (bootverbose) { 2718 printf("%s: target %d using %dbit transfers\n", 2719 ahd_name(ahd), devinfo->target, 2720 8 * (0x01 << width)); 2721 } 2722 } 2723 2724 if ((type & AHD_TRANS_CUR) != 0) { 2725 if (!paused) 2726 ahd_pause(ahd); 2727 ahd_update_neg_table(ahd, devinfo, &tinfo->curr); 2728 if (!paused) 2729 ahd_unpause(ahd); 2730 } 2731 2732 update_needed += ahd_update_neg_request(ahd, devinfo, tstate, 2733 tinfo, AHD_NEG_TO_GOAL); 2734 if (update_needed && active) 2735 ahd_update_pending_scbs(ahd); 2736 2737 } 2738 2739 /* 2740 * Update the current state of tagged queuing for a given target. 2741 */ 2742 void 2743 ahd_set_tags(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2744 ahd_queue_alg alg) 2745 { 2746 ahd_platform_set_tags(ahd, devinfo, alg); 2747 ahd_send_async(ahd, devinfo->channel, devinfo->target, 2748 devinfo->lun, AC_TRANSFER_NEG, &alg); 2749 } 2750 2751 static void 2752 ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2753 struct ahd_transinfo *tinfo) 2754 { 2755 ahd_mode_state saved_modes; 2756 u_int period; 2757 u_int ppr_opts; 2758 u_int con_opts; 2759 u_int offset; 2760 u_int saved_negoaddr; 2761 uint8_t iocell_opts[sizeof(ahd->iocell_opts)]; 2762 2763 saved_modes = ahd_save_modes(ahd); 2764 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2765 2766 saved_negoaddr = ahd_inb(ahd, NEGOADDR); 2767 ahd_outb(ahd, NEGOADDR, devinfo->target); 2768 period = tinfo->period; 2769 offset = tinfo->offset; 2770 memcpy(iocell_opts, ahd->iocell_opts, sizeof(ahd->iocell_opts)); 2771 ppr_opts = tinfo->ppr_options & (MSG_EXT_PPR_QAS_REQ|MSG_EXT_PPR_DT_REQ 2772 |MSG_EXT_PPR_IU_REQ|MSG_EXT_PPR_RTI); 2773 con_opts = 0; 2774 if (period == 0) 2775 period = AHD_SYNCRATE_ASYNC; 2776 if (period == AHD_SYNCRATE_160) { 2777 2778 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) { 2779 /* 2780 * When the SPI4 spec was finalized, PACE transfers 2781 * was not made a configurable option in the PPR 2782 * message. Instead it is assumed to be enabled for 2783 * any syncrate faster than 80MHz. Nevertheless, 2784 * Harpoon2A4 allows this to be configurable. 2785 * 2786 * Harpoon2A4 also assumes at most 2 data bytes per 2787 * negotiated REQ/ACK offset. Paced transfers take 2788 * 4, so we must adjust our offset. 2789 */ 2790 ppr_opts |= PPROPT_PACE; 2791 offset *= 2; 2792 2793 /* 2794 * Harpoon2A assumed that there would be a 2795 * fallback rate between 160MHz and 80Mhz, 2796 * so 7 is used as the period factor rather 2797 * than 8 for 160MHz. 2798 */ 2799 period = AHD_SYNCRATE_REVA_160; 2800 } 2801 if ((tinfo->ppr_options & MSG_EXT_PPR_PCOMP_EN) == 0) 2802 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= 2803 ~AHD_PRECOMP_MASK; 2804 } else { 2805 /* 2806 * Precomp should be disabled for non-paced transfers. 2807 */ 2808 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; 2809 2810 if ((ahd->features & AHD_NEW_IOCELL_OPTS) != 0 2811 && (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0) { 2812 /* 2813 * Slow down our CRC interval to be 2814 * compatible with devices that can't 2815 * handle a CRC at full speed. 2816 */ 2817 con_opts |= ENSLOWCRC; 2818 } 2819 } 2820 2821 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP_SLEW); 2822 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_PRECOMP_SLEW_INDEX]); 2823 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_AMPLITUDE); 2824 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_AMPLITUDE_INDEX]); 2825 2826 ahd_outb(ahd, NEGPERIOD, period); 2827 ahd_outb(ahd, NEGPPROPTS, ppr_opts); 2828 ahd_outb(ahd, NEGOFFSET, offset); 2829 2830 if (tinfo->width == MSG_EXT_WDTR_BUS_16_BIT) 2831 con_opts |= WIDEXFER; 2832 2833 /* 2834 * During packetized transfers, the target will 2835 * give us the oportunity to send command packets 2836 * without us asserting attention. 2837 */ 2838 if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0) 2839 con_opts |= ENAUTOATNO; 2840 ahd_outb(ahd, NEGCONOPTS, con_opts); 2841 ahd_outb(ahd, NEGOADDR, saved_negoaddr); 2842 ahd_restore_modes(ahd, saved_modes); 2843 } 2844 2845 /* 2846 * When the transfer settings for a connection change, setup for 2847 * negotiation in pending SCBs to effect the change as quickly as 2848 * possible. We also cancel any negotiations that are scheduled 2849 * for inflight SCBs that have not been started yet. 2850 */ 2851 static void 2852 ahd_update_pending_scbs(struct ahd_softc *ahd) 2853 { 2854 struct scb *pending_scb; 2855 int pending_scb_count; 2856 int i; 2857 int paused; 2858 u_int saved_scbptr; 2859 ahd_mode_state saved_modes; 2860 2861 /* 2862 * Traverse the pending SCB list and ensure that all of the 2863 * SCBs there have the proper settings. We can only safely 2864 * clear the negotiation required flag (setting requires the 2865 * execution queue to be modified) and this is only possible 2866 * if we are not already attempting to select out for this 2867 * SCB. For this reason, all callers only call this routine 2868 * if we are changing the negotiation settings for the currently 2869 * active transaction on the bus. 2870 */ 2871 pending_scb_count = 0; 2872 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) { 2873 struct ahd_devinfo devinfo; 2874 struct hardware_scb *pending_hscb; 2875 struct ahd_initiator_tinfo *tinfo; 2876 struct ahd_tmode_tstate *tstate; 2877 2878 ahd_scb_devinfo(ahd, &devinfo, pending_scb); 2879 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel, 2880 devinfo.our_scsiid, 2881 devinfo.target, &tstate); 2882 pending_hscb = pending_scb->hscb; 2883 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 2884 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 2885 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 2886 pending_hscb->control &= ~MK_MESSAGE; 2887 } 2888 ahd_sync_scb(ahd, pending_scb, 2889 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2890 pending_scb_count++; 2891 } 2892 2893 if (pending_scb_count == 0) 2894 return; 2895 2896 if (ahd_is_paused(ahd)) { 2897 paused = 1; 2898 } else { 2899 paused = 0; 2900 ahd_pause(ahd); 2901 } 2902 2903 /* 2904 * Force the sequencer to reinitialize the selection for 2905 * the command at the head of the execution queue if it 2906 * has already been setup. The negotiation changes may 2907 * effect whether we select-out with ATN. 2908 */ 2909 saved_modes = ahd_save_modes(ahd); 2910 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2911 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 2912 saved_scbptr = ahd_get_scbptr(ahd); 2913 /* Ensure that the hscbs down on the card match the new information */ 2914 for (i = 0; i < ahd->scb_data.maxhscbs; i++) { 2915 struct hardware_scb *pending_hscb; 2916 u_int control; 2917 u_int scb_tag; 2918 2919 ahd_set_scbptr(ahd, i); 2920 scb_tag = i; 2921 pending_scb = ahd_lookup_scb(ahd, scb_tag); 2922 if (pending_scb == NULL) 2923 continue; 2924 2925 pending_hscb = pending_scb->hscb; 2926 control = ahd_inb_scbram(ahd, SCB_CONTROL); 2927 control &= ~MK_MESSAGE; 2928 control |= pending_hscb->control & MK_MESSAGE; 2929 ahd_outb(ahd, SCB_CONTROL, control); 2930 } 2931 ahd_set_scbptr(ahd, saved_scbptr); 2932 ahd_restore_modes(ahd, saved_modes); 2933 2934 if (paused == 0) 2935 ahd_unpause(ahd); 2936 } 2937 2938 /**************************** Pathing Information *****************************/ 2939 static void 2940 ahd_fetch_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 2941 { 2942 ahd_mode_state saved_modes; 2943 u_int saved_scsiid; 2944 role_t role; 2945 int our_id; 2946 2947 saved_modes = ahd_save_modes(ahd); 2948 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2949 2950 if (ahd_inb(ahd, SSTAT0) & TARGET) 2951 role = ROLE_TARGET; 2952 else 2953 role = ROLE_INITIATOR; 2954 2955 if (role == ROLE_TARGET 2956 && (ahd_inb(ahd, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 2957 /* We were selected, so pull our id from TARGIDIN */ 2958 our_id = ahd_inb(ahd, TARGIDIN) & OID; 2959 } else if (role == ROLE_TARGET) 2960 our_id = ahd_inb(ahd, TOWNID); 2961 else 2962 our_id = ahd_inb(ahd, IOWNID); 2963 2964 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); 2965 ahd_compile_devinfo(devinfo, 2966 our_id, 2967 SCSIID_TARGET(ahd, saved_scsiid), 2968 ahd_inb(ahd, SAVED_LUN), 2969 SCSIID_CHANNEL(ahd, saved_scsiid), 2970 role); 2971 ahd_restore_modes(ahd, saved_modes); 2972 } 2973 2974 void 2975 ahd_print_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 2976 { 2977 printf("%s:%c:%d:%d: ", ahd_name(ahd), 'A', 2978 devinfo->target, devinfo->lun); 2979 } 2980 2981 struct ahd_phase_table_entry* 2982 ahd_lookup_phase_entry(int phase) 2983 { 2984 struct ahd_phase_table_entry *entry; 2985 struct ahd_phase_table_entry *last_entry; 2986 2987 /* 2988 * num_phases doesn't include the default entry which 2989 * will be returned if the phase doesn't match. 2990 */ 2991 last_entry = &ahd_phase_table[num_phases]; 2992 for (entry = ahd_phase_table; entry < last_entry; entry++) { 2993 if (phase == entry->phase) 2994 break; 2995 } 2996 return (entry); 2997 } 2998 2999 void 3000 ahd_compile_devinfo(struct ahd_devinfo *devinfo, u_int our_id, u_int target, 3001 u_int lun, char channel, role_t role) 3002 { 3003 devinfo->our_scsiid = our_id; 3004 devinfo->target = target; 3005 devinfo->lun = lun; 3006 devinfo->target_offset = target; 3007 devinfo->channel = channel; 3008 devinfo->role = role; 3009 if (channel == 'B') 3010 devinfo->target_offset += 8; 3011 devinfo->target_mask = (0x01 << devinfo->target_offset); 3012 } 3013 3014 static void 3015 ahd_scb_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3016 struct scb *scb) 3017 { 3018 role_t role; 3019 int our_id; 3020 3021 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 3022 role = ROLE_INITIATOR; 3023 if ((scb->hscb->control & TARGET_SCB) != 0) 3024 role = ROLE_TARGET; 3025 ahd_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahd, scb), 3026 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahd, scb), role); 3027 } 3028 3029 3030 /************************ Message Phase Processing ****************************/ 3031 /* 3032 * When an initiator transaction with the MK_MESSAGE flag either reconnects 3033 * or enters the initial message out phase, we are interrupted. Fill our 3034 * outgoing message buffer with the appropriate message and beging handing 3035 * the message phase(s) manually. 3036 */ 3037 static void 3038 ahd_setup_initiator_msgout(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3039 struct scb *scb) 3040 { 3041 /* 3042 * To facilitate adding multiple messages together, 3043 * each routine should increment the index and len 3044 * variables instead of setting them explicitly. 3045 */ 3046 ahd->msgout_index = 0; 3047 ahd->msgout_len = 0; 3048 3049 if (ahd_currently_packetized(ahd)) 3050 ahd->msg_flags |= MSG_FLAG_PACKETIZED; 3051 3052 if (ahd->send_msg_perror 3053 && ahd_inb(ahd, MSG_OUT) == HOST_MSG) { 3054 ahd->msgout_buf[ahd->msgout_index++] = ahd->send_msg_perror; 3055 ahd->msgout_len++; 3056 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3057 #ifdef AHD_DEBUG 3058 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3059 printf("Setting up for Parity Error delivery\n"); 3060 #endif 3061 return; 3062 } else if (scb == NULL) { 3063 printf("%s: WARNING. No pending message for " 3064 "I_T msgin. Issuing NO-OP\n", ahd_name(ahd)); 3065 ahd->msgout_buf[ahd->msgout_index++] = MSG_NOOP; 3066 ahd->msgout_len++; 3067 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3068 return; 3069 } 3070 3071 if ((scb->flags & SCB_DEVICE_RESET) == 0 3072 && (scb->flags & SCB_PACKETIZED) == 0 3073 && ahd_inb(ahd, MSG_OUT) == MSG_IDENTIFYFLAG) { 3074 u_int identify_msg; 3075 3076 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 3077 if ((scb->hscb->control & DISCENB) != 0) 3078 identify_msg |= MSG_IDENTIFY_DISCFLAG; 3079 ahd->msgout_buf[ahd->msgout_index++] = identify_msg; 3080 ahd->msgout_len++; 3081 3082 if ((scb->hscb->control & TAG_ENB) != 0) { 3083 ahd->msgout_buf[ahd->msgout_index++] = 3084 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 3085 ahd->msgout_buf[ahd->msgout_index++] = SCB_GET_TAG(scb); 3086 ahd->msgout_len += 2; 3087 } 3088 } 3089 3090 if (scb->flags & SCB_DEVICE_RESET) { 3091 ahd->msgout_buf[ahd->msgout_index++] = MSG_BUS_DEV_RESET; 3092 ahd->msgout_len++; 3093 ahd_print_path(ahd, scb); 3094 printf("Bus Device Reset Message Sent\n"); 3095 /* 3096 * Clear our selection hardware in advance of 3097 * the busfree. We may have an entry in the waiting 3098 * Q for this target, and we don't want to go about 3099 * selecting while we handle the busfree and blow it 3100 * away. 3101 */ 3102 ahd_outb(ahd, SCSISEQ0, 0); 3103 } else if ((scb->flags & SCB_ABORT) != 0) { 3104 3105 if ((scb->hscb->control & TAG_ENB) != 0) { 3106 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT_TAG; 3107 } else { 3108 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT; 3109 } 3110 ahd->msgout_len++; 3111 ahd_print_path(ahd, scb); 3112 printf("Abort%s Message Sent\n", 3113 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 3114 /* 3115 * Clear our selection hardware in advance of 3116 * the busfree. We may have an entry in the waiting 3117 * Q for this target, and we don't want to go about 3118 * selecting while we handle the busfree and blow it 3119 * away. 3120 */ 3121 ahd_outb(ahd, SCSISEQ0, 0); 3122 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 3123 ahd_build_transfer_msg(ahd, devinfo); 3124 /* 3125 * Clear our selection hardware in advance of potential 3126 * PPR IU status change busfree. We may have an entry in 3127 * the waiting Q for this target, and we don't want to go 3128 * about selecting while we handle the busfree and blow 3129 * it away. 3130 */ 3131 ahd_outb(ahd, SCSISEQ0, 0); 3132 } else { 3133 printf("ahd_intr: AWAITING_MSG for an SCB that " 3134 "does not have a waiting message\n"); 3135 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 3136 devinfo->target_mask); 3137 panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x " 3138 "SCB flags = %x", SCB_GET_TAG(scb), scb->hscb->control, 3139 ahd_inb(ahd, SCB_CONTROL), ahd_inb(ahd, MSG_OUT), 3140 scb->flags); 3141 } 3142 3143 /* 3144 * Clear the MK_MESSAGE flag from the SCB so we aren't 3145 * asked to send this message again. 3146 */ 3147 ahd_outb(ahd, SCB_CONTROL, 3148 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE); 3149 scb->hscb->control &= ~MK_MESSAGE; 3150 ahd->msgout_index = 0; 3151 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3152 } 3153 3154 /* 3155 * Build an appropriate transfer negotiation message for the 3156 * currently active target. 3157 */ 3158 static void 3159 ahd_build_transfer_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3160 { 3161 /* 3162 * We need to initiate transfer negotiations. 3163 * If our current and goal settings are identical, 3164 * we want to renegotiate due to a check condition. 3165 */ 3166 struct ahd_initiator_tinfo *tinfo; 3167 struct ahd_tmode_tstate *tstate; 3168 int dowide; 3169 int dosync; 3170 int doppr; 3171 u_int period; 3172 u_int ppr_options; 3173 u_int offset; 3174 3175 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3176 devinfo->target, &tstate); 3177 /* 3178 * Filter our period based on the current connection. 3179 * If we can't perform DT transfers on this segment (not in LVD 3180 * mode for instance), then our decision to issue a PPR message 3181 * may change. 3182 */ 3183 period = tinfo->goal.period; 3184 ppr_options = tinfo->goal.ppr_options; 3185 /* Target initiated PPR is not allowed in the SCSI spec */ 3186 if (devinfo->role == ROLE_TARGET) 3187 ppr_options = 0; 3188 ahd_devlimited_syncrate(ahd, tinfo, &period, 3189 &ppr_options, devinfo->role); 3190 dowide = tinfo->curr.width != tinfo->goal.width; 3191 dosync = tinfo->curr.period != period; 3192 /* 3193 * Only use PPR if we have options that need it, even if the device 3194 * claims to support it. There might be an expander in the way 3195 * that doesn't. 3196 */ 3197 doppr = ppr_options != 0; 3198 3199 if (!dowide && !dosync && !doppr) { 3200 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 3201 dosync = tinfo->goal.period != 0; 3202 } 3203 3204 if (!dowide && !dosync && !doppr) { 3205 /* 3206 * Force async with a WDTR message if we have a wide bus, 3207 * or just issue an SDTR with a 0 offset. 3208 */ 3209 if ((ahd->features & AHD_WIDE) != 0) 3210 dowide = 1; 3211 else 3212 dosync = 1; 3213 3214 if (bootverbose) { 3215 ahd_print_devinfo(ahd, devinfo); 3216 printf("Ensuring async\n"); 3217 } 3218 } 3219 /* Target initiated PPR is not allowed in the SCSI spec */ 3220 if (devinfo->role == ROLE_TARGET) 3221 doppr = 0; 3222 3223 /* 3224 * Both the PPR message and SDTR message require the 3225 * goal syncrate to be limited to what the target device 3226 * is capable of handling (based on whether an LVD->SE 3227 * expander is on the bus), so combine these two cases. 3228 * Regardless, guarantee that if we are using WDTR and SDTR 3229 * messages that WDTR comes first. 3230 */ 3231 if (doppr || (dosync && !dowide)) { 3232 3233 offset = tinfo->goal.offset; 3234 ahd_validate_offset(ahd, tinfo, period, &offset, 3235 doppr ? tinfo->goal.width 3236 : tinfo->curr.width, 3237 devinfo->role); 3238 if (doppr) { 3239 ahd_construct_ppr(ahd, devinfo, period, offset, 3240 tinfo->goal.width, ppr_options); 3241 } else { 3242 ahd_construct_sdtr(ahd, devinfo, period, offset); 3243 } 3244 } else { 3245 ahd_construct_wdtr(ahd, devinfo, tinfo->goal.width); 3246 } 3247 } 3248 3249 /* 3250 * Build a synchronous negotiation message in our message 3251 * buffer based on the input parameters. 3252 */ 3253 static void 3254 ahd_construct_sdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3255 u_int period, u_int offset) 3256 { 3257 if (offset == 0) 3258 period = AHD_ASYNC_XFER_PERIOD; 3259 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3260 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR_LEN; 3261 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR; 3262 ahd->msgout_buf[ahd->msgout_index++] = period; 3263 ahd->msgout_buf[ahd->msgout_index++] = offset; 3264 ahd->msgout_len += 5; 3265 if (bootverbose) { 3266 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 3267 ahd_name(ahd), devinfo->channel, devinfo->target, 3268 devinfo->lun, period, offset); 3269 } 3270 } 3271 3272 /* 3273 * Build a wide negotiateion message in our message 3274 * buffer based on the input parameters. 3275 */ 3276 static void 3277 ahd_construct_wdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3278 u_int bus_width) 3279 { 3280 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3281 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR_LEN; 3282 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR; 3283 ahd->msgout_buf[ahd->msgout_index++] = bus_width; 3284 ahd->msgout_len += 4; 3285 if (bootverbose) { 3286 printf("(%s:%c:%d:%d): Sending WDTR %x\n", 3287 ahd_name(ahd), devinfo->channel, devinfo->target, 3288 devinfo->lun, bus_width); 3289 } 3290 } 3291 3292 /* 3293 * Build a parallel protocol request message in our message 3294 * buffer based on the input parameters. 3295 */ 3296 static void 3297 ahd_construct_ppr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3298 u_int period, u_int offset, u_int bus_width, 3299 u_int ppr_options) 3300 { 3301 /* 3302 * Always request precompensation from 3303 * the other target if we are running 3304 * at paced syncrates. 3305 */ 3306 if (period <= AHD_SYNCRATE_PACED) 3307 ppr_options |= MSG_EXT_PPR_PCOMP_EN; 3308 if (offset == 0) 3309 period = AHD_ASYNC_XFER_PERIOD; 3310 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3311 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR_LEN; 3312 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR; 3313 ahd->msgout_buf[ahd->msgout_index++] = period; 3314 ahd->msgout_buf[ahd->msgout_index++] = 0; 3315 ahd->msgout_buf[ahd->msgout_index++] = offset; 3316 ahd->msgout_buf[ahd->msgout_index++] = bus_width; 3317 ahd->msgout_buf[ahd->msgout_index++] = ppr_options; 3318 ahd->msgout_len += 8; 3319 if (bootverbose) { 3320 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, " 3321 "offset %x, ppr_options %x\n", ahd_name(ahd), 3322 devinfo->channel, devinfo->target, devinfo->lun, 3323 bus_width, period, offset, ppr_options); 3324 } 3325 } 3326 3327 /* 3328 * Clear any active message state. 3329 */ 3330 static void 3331 ahd_clear_msg_state(struct ahd_softc *ahd) 3332 { 3333 ahd_mode_state saved_modes; 3334 3335 saved_modes = ahd_save_modes(ahd); 3336 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3337 ahd->send_msg_perror = 0; 3338 ahd->msg_flags = MSG_FLAG_NONE; 3339 ahd->msgout_len = 0; 3340 ahd->msgin_index = 0; 3341 ahd->msg_type = MSG_TYPE_NONE; 3342 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { 3343 /* 3344 * The target didn't care to respond to our 3345 * message request, so clear ATN. 3346 */ 3347 ahd_outb(ahd, CLRSINT1, CLRATNO); 3348 } 3349 ahd_outb(ahd, MSG_OUT, MSG_NOOP); 3350 ahd_outb(ahd, SEQ_FLAGS2, 3351 ahd_inb(ahd, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 3352 ahd_restore_modes(ahd, saved_modes); 3353 } 3354 3355 /* 3356 * Manual message loop handler. 3357 */ 3358 static void 3359 ahd_handle_message_phase(struct ahd_softc *ahd) 3360 { 3361 struct ahd_devinfo devinfo; 3362 u_int bus_phase; 3363 int end_session; 3364 3365 ahd_fetch_devinfo(ahd, &devinfo); 3366 end_session = FALSE; 3367 bus_phase = ahd_inb(ahd, LASTPHASE); 3368 3369 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0) { 3370 printf("LQIRETRY for LQIPHASE_OUTPKT\n"); 3371 ahd_outb(ahd, LQCTL2, LQIRETRY); 3372 } 3373 reswitch: 3374 switch (ahd->msg_type) { 3375 case MSG_TYPE_INITIATOR_MSGOUT: 3376 { 3377 int lastbyte; 3378 int phasemis; 3379 int msgdone; 3380 3381 if (ahd->msgout_len == 0 && ahd->send_msg_perror == 0) 3382 panic("HOST_MSG_LOOP interrupt with no active message"); 3383 3384 #ifdef AHD_DEBUG 3385 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3386 ahd_print_devinfo(ahd, &devinfo); 3387 printf("INITIATOR_MSG_OUT"); 3388 } 3389 #endif 3390 phasemis = bus_phase != P_MESGOUT; 3391 if (phasemis) { 3392 #ifdef AHD_DEBUG 3393 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3394 printf(" PHASEMIS %s\n", 3395 ahd_lookup_phase_entry(bus_phase) 3396 ->phasemsg); 3397 } 3398 #endif 3399 if (bus_phase == P_MESGIN) { 3400 /* 3401 * Change gears and see if 3402 * this messages is of interest to 3403 * us or should be passed back to 3404 * the sequencer. 3405 */ 3406 ahd_outb(ahd, CLRSINT1, CLRATNO); 3407 ahd->send_msg_perror = 0; 3408 ahd->msg_type = MSG_TYPE_INITIATOR_MSGIN; 3409 ahd->msgin_index = 0; 3410 goto reswitch; 3411 } 3412 end_session = TRUE; 3413 break; 3414 } 3415 3416 if (ahd->send_msg_perror) { 3417 ahd_outb(ahd, CLRSINT1, CLRATNO); 3418 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3419 #ifdef AHD_DEBUG 3420 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3421 printf(" byte 0x%x\n", ahd->send_msg_perror); 3422 #endif 3423 /* 3424 * If we are notifying the target of a CRC error 3425 * during packetized operations, the target is 3426 * within its rights to acknowledge our message 3427 * with a busfree. 3428 */ 3429 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0 3430 && ahd->send_msg_perror == MSG_INITIATOR_DET_ERR) 3431 ahd->msg_flags |= MSG_FLAG_EXPECT_IDE_BUSFREE; 3432 3433 ahd_outb(ahd, RETURN_2, ahd->send_msg_perror); 3434 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); 3435 break; 3436 } 3437 3438 msgdone = ahd->msgout_index == ahd->msgout_len; 3439 if (msgdone) { 3440 /* 3441 * The target has requested a retry. 3442 * Re-assert ATN, reset our message index to 3443 * 0, and try again. 3444 */ 3445 ahd->msgout_index = 0; 3446 ahd_assert_atn(ahd); 3447 } 3448 3449 lastbyte = ahd->msgout_index == (ahd->msgout_len - 1); 3450 if (lastbyte) { 3451 /* Last byte is signified by dropping ATN */ 3452 ahd_outb(ahd, CLRSINT1, CLRATNO); 3453 } 3454 3455 /* 3456 * Clear our interrupt status and present 3457 * the next byte on the bus. 3458 */ 3459 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3460 #ifdef AHD_DEBUG 3461 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3462 printf(" byte 0x%x\n", 3463 ahd->msgout_buf[ahd->msgout_index]); 3464 #endif 3465 ahd_outb(ahd, RETURN_2, ahd->msgout_buf[ahd->msgout_index++]); 3466 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); 3467 break; 3468 } 3469 case MSG_TYPE_INITIATOR_MSGIN: 3470 { 3471 int phasemis; 3472 int message_done; 3473 3474 #ifdef AHD_DEBUG 3475 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3476 ahd_print_devinfo(ahd, &devinfo); 3477 printf("INITIATOR_MSG_IN"); 3478 } 3479 #endif 3480 phasemis = bus_phase != P_MESGIN; 3481 if (phasemis) { 3482 #ifdef AHD_DEBUG 3483 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3484 printf(" PHASEMIS %s\n", 3485 ahd_lookup_phase_entry(bus_phase) 3486 ->phasemsg); 3487 } 3488 #endif 3489 ahd->msgin_index = 0; 3490 if (bus_phase == P_MESGOUT 3491 && (ahd->send_msg_perror != 0 3492 || (ahd->msgout_len != 0 3493 && ahd->msgout_index == 0))) { 3494 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3495 goto reswitch; 3496 } 3497 end_session = TRUE; 3498 break; 3499 } 3500 3501 /* Pull the byte in without acking it */ 3502 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIBUS); 3503 #ifdef AHD_DEBUG 3504 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3505 printf(" byte 0x%x\n", 3506 ahd->msgin_buf[ahd->msgin_index]); 3507 #endif 3508 3509 message_done = ahd_parse_msg(ahd, &devinfo); 3510 3511 if (message_done) { 3512 /* 3513 * Clear our incoming message buffer in case there 3514 * is another message following this one. 3515 */ 3516 ahd->msgin_index = 0; 3517 3518 /* 3519 * If this message illicited a response, 3520 * assert ATN so the target takes us to the 3521 * message out phase. 3522 */ 3523 if (ahd->msgout_len != 0) { 3524 #ifdef AHD_DEBUG 3525 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3526 ahd_print_devinfo(ahd, &devinfo); 3527 printf("Asserting ATN for response\n"); 3528 } 3529 #endif 3530 ahd_assert_atn(ahd); 3531 } 3532 } else 3533 ahd->msgin_index++; 3534 3535 if (message_done == MSGLOOP_TERMINATED) { 3536 end_session = TRUE; 3537 } else { 3538 /* Ack the byte */ 3539 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3540 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_READ); 3541 } 3542 break; 3543 } 3544 case MSG_TYPE_TARGET_MSGIN: 3545 { 3546 int msgdone; 3547 int msgout_request; 3548 3549 /* 3550 * By default, the message loop will continue. 3551 */ 3552 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); 3553 3554 if (ahd->msgout_len == 0) 3555 panic("Target MSGIN with no active message"); 3556 3557 /* 3558 * If we interrupted a mesgout session, the initiator 3559 * will not know this until our first REQ. So, we 3560 * only honor mesgout requests after we've sent our 3561 * first byte. 3562 */ 3563 if ((ahd_inb(ahd, SCSISIGI) & ATNI) != 0 3564 && ahd->msgout_index > 0) 3565 msgout_request = TRUE; 3566 else 3567 msgout_request = FALSE; 3568 3569 if (msgout_request) { 3570 3571 /* 3572 * Change gears and see if 3573 * this messages is of interest to 3574 * us or should be passed back to 3575 * the sequencer. 3576 */ 3577 ahd->msg_type = MSG_TYPE_TARGET_MSGOUT; 3578 ahd_outb(ahd, SCSISIGO, P_MESGOUT | BSYO); 3579 ahd->msgin_index = 0; 3580 /* Dummy read to REQ for first byte */ 3581 ahd_inb(ahd, SCSIDAT); 3582 ahd_outb(ahd, SXFRCTL0, 3583 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3584 break; 3585 } 3586 3587 msgdone = ahd->msgout_index == ahd->msgout_len; 3588 if (msgdone) { 3589 ahd_outb(ahd, SXFRCTL0, 3590 ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); 3591 end_session = TRUE; 3592 break; 3593 } 3594 3595 /* 3596 * Present the next byte on the bus. 3597 */ 3598 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3599 ahd_outb(ahd, SCSIDAT, ahd->msgout_buf[ahd->msgout_index++]); 3600 break; 3601 } 3602 case MSG_TYPE_TARGET_MSGOUT: 3603 { 3604 int lastbyte; 3605 int msgdone; 3606 3607 /* 3608 * By default, the message loop will continue. 3609 */ 3610 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); 3611 3612 /* 3613 * The initiator signals that this is 3614 * the last byte by dropping ATN. 3615 */ 3616 lastbyte = (ahd_inb(ahd, SCSISIGI) & ATNI) == 0; 3617 3618 /* 3619 * Read the latched byte, but turn off SPIOEN first 3620 * so that we don't inadvertently cause a REQ for the 3621 * next byte. 3622 */ 3623 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); 3624 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIDAT); 3625 msgdone = ahd_parse_msg(ahd, &devinfo); 3626 if (msgdone == MSGLOOP_TERMINATED) { 3627 /* 3628 * The message is *really* done in that it caused 3629 * us to go to bus free. The sequencer has already 3630 * been reset at this point, so pull the ejection 3631 * handle. 3632 */ 3633 return; 3634 } 3635 3636 ahd->msgin_index++; 3637 3638 /* 3639 * XXX Read spec about initiator dropping ATN too soon 3640 * and use msgdone to detect it. 3641 */ 3642 if (msgdone == MSGLOOP_MSGCOMPLETE) { 3643 ahd->msgin_index = 0; 3644 3645 /* 3646 * If this message illicited a response, transition 3647 * to the Message in phase and send it. 3648 */ 3649 if (ahd->msgout_len != 0) { 3650 ahd_outb(ahd, SCSISIGO, P_MESGIN | BSYO); 3651 ahd_outb(ahd, SXFRCTL0, 3652 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3653 ahd->msg_type = MSG_TYPE_TARGET_MSGIN; 3654 ahd->msgin_index = 0; 3655 break; 3656 } 3657 } 3658 3659 if (lastbyte) 3660 end_session = TRUE; 3661 else { 3662 /* Ask for the next byte. */ 3663 ahd_outb(ahd, SXFRCTL0, 3664 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 3665 } 3666 3667 break; 3668 } 3669 default: 3670 panic("Unknown REQINIT message type"); 3671 } 3672 3673 if (end_session) { 3674 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0) { 3675 printf("%s: Returning to Idle Loop\n", 3676 ahd_name(ahd)); 3677 ahd_outb(ahd, LASTPHASE, P_BUSFREE); 3678 ahd_clear_msg_state(ahd); 3679 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); 3680 } else { 3681 ahd_clear_msg_state(ahd); 3682 ahd_outb(ahd, RETURN_1, EXIT_MSG_LOOP); 3683 } 3684 } 3685 } 3686 3687 /* 3688 * See if we sent a particular extended message to the target. 3689 * If "full" is true, return true only if the target saw the full 3690 * message. If "full" is false, return true if the target saw at 3691 * least the first byte of the message. 3692 */ 3693 static int 3694 ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, u_int msgval, int full) 3695 { 3696 int found; 3697 u_int index; 3698 3699 found = FALSE; 3700 index = 0; 3701 3702 while (index < ahd->msgout_len) { 3703 if (ahd->msgout_buf[index] == MSG_EXTENDED) { 3704 u_int end_index; 3705 3706 end_index = index + 1 + ahd->msgout_buf[index + 1]; 3707 if (ahd->msgout_buf[index+2] == msgval 3708 && type == AHDMSG_EXT) { 3709 3710 if (full) { 3711 if (ahd->msgout_index > end_index) 3712 found = TRUE; 3713 } else if (ahd->msgout_index > index) 3714 found = TRUE; 3715 } 3716 index = end_index; 3717 } else if (ahd->msgout_buf[index] >= MSG_SIMPLE_TASK 3718 && ahd->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 3719 3720 /* Skip tag type and tag id or residue param*/ 3721 index += 2; 3722 } else { 3723 /* Single byte message */ 3724 if (type == AHDMSG_1B 3725 && ahd->msgout_index > index 3726 && (ahd->msgout_buf[index] == msgval 3727 || ((ahd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0 3728 && msgval == MSG_IDENTIFYFLAG))) 3729 found = TRUE; 3730 index++; 3731 } 3732 3733 if (found) 3734 break; 3735 } 3736 return (found); 3737 } 3738 3739 /* 3740 * Wait for a complete incoming message, parse it, and respond accordingly. 3741 */ 3742 static int 3743 ahd_parse_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3744 { 3745 struct ahd_initiator_tinfo *tinfo; 3746 struct ahd_tmode_tstate *tstate; 3747 int reject; 3748 int done; 3749 int response; 3750 3751 done = MSGLOOP_IN_PROG; 3752 response = FALSE; 3753 reject = FALSE; 3754 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3755 devinfo->target, &tstate); 3756 3757 /* 3758 * Parse as much of the message as is availible, 3759 * rejecting it if we don't support it. When 3760 * the entire message is availible and has been 3761 * handled, return MSGLOOP_MSGCOMPLETE, indicating 3762 * that we have parsed an entire message. 3763 * 3764 * In the case of extended messages, we accept the length 3765 * byte outright and perform more checking once we know the 3766 * extended message type. 3767 */ 3768 switch (ahd->msgin_buf[0]) { 3769 case MSG_DISCONNECT: 3770 case MSG_SAVEDATAPOINTER: 3771 case MSG_CMDCOMPLETE: 3772 case MSG_RESTOREPOINTERS: 3773 case MSG_IGN_WIDE_RESIDUE: 3774 /* 3775 * End our message loop as these are messages 3776 * the sequencer handles on its own. 3777 */ 3778 done = MSGLOOP_TERMINATED; 3779 break; 3780 case MSG_MESSAGE_REJECT: 3781 response = ahd_handle_msg_reject(ahd, devinfo); 3782 /* FALLTHROUGH */ 3783 case MSG_NOOP: 3784 done = MSGLOOP_MSGCOMPLETE; 3785 break; 3786 case MSG_EXTENDED: 3787 { 3788 /* Wait for enough of the message to begin validation */ 3789 if (ahd->msgin_index < 2) 3790 break; 3791 switch (ahd->msgin_buf[2]) { 3792 case MSG_EXT_SDTR: 3793 { 3794 u_int period; 3795 u_int ppr_options; 3796 u_int offset; 3797 u_int saved_offset; 3798 3799 if (ahd->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 3800 reject = TRUE; 3801 break; 3802 } 3803 3804 /* 3805 * Wait until we have both args before validating 3806 * and acting on this message. 3807 * 3808 * Add one to MSG_EXT_SDTR_LEN to account for 3809 * the extended message preamble. 3810 */ 3811 if (ahd->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 3812 break; 3813 3814 period = ahd->msgin_buf[3]; 3815 ppr_options = 0; 3816 saved_offset = offset = ahd->msgin_buf[4]; 3817 ahd_devlimited_syncrate(ahd, tinfo, &period, 3818 &ppr_options, devinfo->role); 3819 ahd_validate_offset(ahd, tinfo, period, &offset, 3820 tinfo->curr.width, devinfo->role); 3821 if (bootverbose) { 3822 printf("(%s:%c:%d:%d): Received " 3823 "SDTR period %x, offset %x\n\t" 3824 "Filtered to period %x, offset %x\n", 3825 ahd_name(ahd), devinfo->channel, 3826 devinfo->target, devinfo->lun, 3827 ahd->msgin_buf[3], saved_offset, 3828 period, offset); 3829 } 3830 ahd_set_syncrate(ahd, devinfo, period, 3831 offset, ppr_options, 3832 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 3833 /*paused*/TRUE); 3834 3835 /* 3836 * See if we initiated Sync Negotiation 3837 * and didn't have to fall down to async 3838 * transfers. 3839 */ 3840 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, TRUE)) { 3841 /* We started it */ 3842 if (saved_offset != offset) { 3843 /* Went too low - force async */ 3844 reject = TRUE; 3845 } 3846 } else { 3847 /* 3848 * Send our own SDTR in reply 3849 */ 3850 if (bootverbose 3851 && devinfo->role == ROLE_INITIATOR) { 3852 printf("(%s:%c:%d:%d): Target " 3853 "Initiated SDTR\n", 3854 ahd_name(ahd), devinfo->channel, 3855 devinfo->target, devinfo->lun); 3856 } 3857 ahd->msgout_index = 0; 3858 ahd->msgout_len = 0; 3859 ahd_construct_sdtr(ahd, devinfo, 3860 period, offset); 3861 ahd->msgout_index = 0; 3862 response = TRUE; 3863 } 3864 done = MSGLOOP_MSGCOMPLETE; 3865 break; 3866 } 3867 case MSG_EXT_WDTR: 3868 { 3869 u_int bus_width; 3870 u_int saved_width; 3871 u_int sending_reply; 3872 3873 sending_reply = FALSE; 3874 if (ahd->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3875 reject = TRUE; 3876 break; 3877 } 3878 3879 /* 3880 * Wait until we have our arg before validating 3881 * and acting on this message. 3882 * 3883 * Add one to MSG_EXT_WDTR_LEN to account for 3884 * the extended message preamble. 3885 */ 3886 if (ahd->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3887 break; 3888 3889 bus_width = ahd->msgin_buf[3]; 3890 saved_width = bus_width; 3891 ahd_validate_width(ahd, tinfo, &bus_width, 3892 devinfo->role); 3893 if (bootverbose) { 3894 printf("(%s:%c:%d:%d): Received WDTR " 3895 "%x filtered to %x\n", 3896 ahd_name(ahd), devinfo->channel, 3897 devinfo->target, devinfo->lun, 3898 saved_width, bus_width); 3899 } 3900 3901 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, TRUE)) { 3902 /* 3903 * Don't send a WDTR back to the 3904 * target, since we asked first. 3905 * If the width went higher than our 3906 * request, reject it. 3907 */ 3908 if (saved_width > bus_width) { 3909 reject = TRUE; 3910 printf("(%s:%c:%d:%d): requested %dBit " 3911 "transfers. Rejecting...\n", 3912 ahd_name(ahd), devinfo->channel, 3913 devinfo->target, devinfo->lun, 3914 8 * (0x01 << bus_width)); 3915 bus_width = 0; 3916 } 3917 } else { 3918 /* 3919 * Send our own WDTR in reply 3920 */ 3921 if (bootverbose 3922 && devinfo->role == ROLE_INITIATOR) { 3923 printf("(%s:%c:%d:%d): Target " 3924 "Initiated WDTR\n", 3925 ahd_name(ahd), devinfo->channel, 3926 devinfo->target, devinfo->lun); 3927 } 3928 ahd->msgout_index = 0; 3929 ahd->msgout_len = 0; 3930 ahd_construct_wdtr(ahd, devinfo, bus_width); 3931 ahd->msgout_index = 0; 3932 response = TRUE; 3933 sending_reply = TRUE; 3934 } 3935 ahd_set_width(ahd, devinfo, bus_width, 3936 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 3937 /*paused*/TRUE); 3938 /* After a wide message, we are async */ 3939 ahd_set_syncrate(ahd, devinfo, /*period*/0, 3940 /*offset*/0, /*ppr_options*/0, 3941 AHD_TRANS_ACTIVE, /*paused*/TRUE); 3942 if (sending_reply == FALSE && reject == FALSE) { 3943 3944 if (tinfo->goal.offset) { 3945 ahd->msgout_index = 0; 3946 ahd->msgout_len = 0; 3947 ahd_build_transfer_msg(ahd, devinfo); 3948 ahd->msgout_index = 0; 3949 response = TRUE; 3950 } 3951 } 3952 done = MSGLOOP_MSGCOMPLETE; 3953 break; 3954 } 3955 case MSG_EXT_PPR: 3956 { 3957 u_int period; 3958 u_int offset; 3959 u_int bus_width; 3960 u_int ppr_options; 3961 u_int saved_width; 3962 u_int saved_offset; 3963 u_int saved_ppr_options; 3964 3965 if (ahd->msgin_buf[1] != MSG_EXT_PPR_LEN) { 3966 reject = TRUE; 3967 break; 3968 } 3969 3970 /* 3971 * Wait until we have all args before validating 3972 * and acting on this message. 3973 * 3974 * Add one to MSG_EXT_PPR_LEN to account for 3975 * the extended message preamble. 3976 */ 3977 if (ahd->msgin_index < (MSG_EXT_PPR_LEN + 1)) 3978 break; 3979 3980 period = ahd->msgin_buf[3]; 3981 offset = ahd->msgin_buf[5]; 3982 bus_width = ahd->msgin_buf[6]; 3983 saved_width = bus_width; 3984 ppr_options = ahd->msgin_buf[7]; 3985 /* 3986 * According to the spec, a DT only 3987 * period factor with no DT option 3988 * set implies async. 3989 */ 3990 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 3991 && period <= 9) 3992 offset = 0; 3993 saved_ppr_options = ppr_options; 3994 saved_offset = offset; 3995 3996 /* 3997 * Transfer options are only available if we 3998 * are negotiating wide. 3999 */ 4000 if (bus_width == 0) 4001 ppr_options &= MSG_EXT_PPR_QAS_REQ; 4002 4003 ahd_validate_width(ahd, tinfo, &bus_width, 4004 devinfo->role); 4005 ahd_devlimited_syncrate(ahd, tinfo, &period, 4006 &ppr_options, devinfo->role); 4007 ahd_validate_offset(ahd, tinfo, period, &offset, 4008 bus_width, devinfo->role); 4009 4010 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, TRUE)) { 4011 /* 4012 * If we are unable to do any of the 4013 * requested options (we went too low), 4014 * then we'll have to reject the message. 4015 */ 4016 if (saved_width > bus_width 4017 || saved_offset != offset 4018 || saved_ppr_options != ppr_options) { 4019 reject = TRUE; 4020 period = 0; 4021 offset = 0; 4022 bus_width = 0; 4023 ppr_options = 0; 4024 } 4025 } else { 4026 if (devinfo->role != ROLE_TARGET) 4027 printf("(%s:%c:%d:%d): Target " 4028 "Initiated PPR\n", 4029 ahd_name(ahd), devinfo->channel, 4030 devinfo->target, devinfo->lun); 4031 else 4032 printf("(%s:%c:%d:%d): Initiator " 4033 "Initiated PPR\n", 4034 ahd_name(ahd), devinfo->channel, 4035 devinfo->target, devinfo->lun); 4036 ahd->msgout_index = 0; 4037 ahd->msgout_len = 0; 4038 ahd_construct_ppr(ahd, devinfo, period, offset, 4039 bus_width, ppr_options); 4040 ahd->msgout_index = 0; 4041 response = TRUE; 4042 } 4043 if (bootverbose) { 4044 printf("(%s:%c:%d:%d): Received PPR width %x, " 4045 "period %x, offset %x,options %x\n" 4046 "\tFiltered to width %x, period %x, " 4047 "offset %x, options %x\n", 4048 ahd_name(ahd), devinfo->channel, 4049 devinfo->target, devinfo->lun, 4050 saved_width, ahd->msgin_buf[3], 4051 saved_offset, saved_ppr_options, 4052 bus_width, period, offset, ppr_options); 4053 } 4054 ahd_set_width(ahd, devinfo, bus_width, 4055 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4056 /*paused*/TRUE); 4057 ahd_set_syncrate(ahd, devinfo, period, 4058 offset, ppr_options, 4059 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4060 /*paused*/TRUE); 4061 4062 done = MSGLOOP_MSGCOMPLETE; 4063 break; 4064 } 4065 default: 4066 /* Unknown extended message. Reject it. */ 4067 reject = TRUE; 4068 break; 4069 } 4070 break; 4071 } 4072 #ifdef AHD_TARGET_MODE 4073 case MSG_BUS_DEV_RESET: 4074 ahd_handle_devreset(ahd, devinfo, CAM_LUN_WILDCARD, 4075 CAM_BDR_SENT, 4076 "Bus Device Reset Received", 4077 /*verbose_level*/0); 4078 ahd_restart(ahd); 4079 done = MSGLOOP_TERMINATED; 4080 break; 4081 case MSG_ABORT_TAG: 4082 case MSG_ABORT: 4083 case MSG_CLEAR_QUEUE: 4084 { 4085 int tag; 4086 4087 /* Target mode messages */ 4088 if (devinfo->role != ROLE_TARGET) { 4089 reject = TRUE; 4090 break; 4091 } 4092 tag = SCB_LIST_NULL; 4093 if (ahd->msgin_buf[0] == MSG_ABORT_TAG) 4094 tag = ahd_inb(ahd, INITIATOR_TAG); 4095 ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, 4096 devinfo->lun, tag, ROLE_TARGET, 4097 CAM_REQ_ABORTED); 4098 4099 tstate = ahd->enabled_targets[devinfo->our_scsiid]; 4100 if (tstate != NULL) { 4101 struct ahd_tmode_lstate* lstate; 4102 4103 lstate = tstate->enabled_luns[devinfo->lun]; 4104 if (lstate != NULL) { 4105 ahd_queue_lstate_event(ahd, lstate, 4106 devinfo->our_scsiid, 4107 ahd->msgin_buf[0], 4108 /*arg*/tag); 4109 ahd_send_lstate_events(ahd, lstate); 4110 } 4111 } 4112 ahd_restart(ahd); 4113 done = MSGLOOP_TERMINATED; 4114 break; 4115 } 4116 #endif 4117 case MSG_QAS_REQUEST: 4118 #ifdef AHD_DEBUG 4119 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 4120 printf("%s: QAS request. SCSISIGI == 0x%x\n", 4121 ahd_name(ahd), ahd_inb(ahd, SCSISIGI)); 4122 #endif 4123 ahd->msg_flags |= MSG_FLAG_EXPECT_QASREJ_BUSFREE; 4124 /* FALLTHROUGH */ 4125 case MSG_TERM_IO_PROC: 4126 default: 4127 reject = TRUE; 4128 break; 4129 } 4130 4131 if (reject) { 4132 /* 4133 * Setup to reject the message. 4134 */ 4135 ahd->msgout_index = 0; 4136 ahd->msgout_len = 1; 4137 ahd->msgout_buf[0] = MSG_MESSAGE_REJECT; 4138 done = MSGLOOP_MSGCOMPLETE; 4139 response = TRUE; 4140 } 4141 4142 if (done != MSGLOOP_IN_PROG && !response) 4143 /* Clear the outgoing message buffer */ 4144 ahd->msgout_len = 0; 4145 4146 return (done); 4147 } 4148 4149 /* 4150 * Process a message reject message. 4151 */ 4152 static int 4153 ahd_handle_msg_reject(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4154 { 4155 /* 4156 * What we care about here is if we had an 4157 * outstanding SDTR or WDTR message for this 4158 * target. If we did, this is a signal that 4159 * the target is refusing negotiation. 4160 */ 4161 struct scb *scb; 4162 struct ahd_initiator_tinfo *tinfo; 4163 struct ahd_tmode_tstate *tstate; 4164 u_int scb_index; 4165 u_int last_msg; 4166 int response = 0; 4167 4168 scb_index = ahd_get_scbptr(ahd); 4169 scb = ahd_lookup_scb(ahd, scb_index); 4170 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, 4171 devinfo->our_scsiid, 4172 devinfo->target, &tstate); 4173 /* Might be necessary */ 4174 last_msg = ahd_inb(ahd, LAST_MSG); 4175 4176 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 4177 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/TRUE) 4178 && tinfo->goal.period <= AHD_SYNCRATE_PACED) { 4179 /* 4180 * Target may not like our SPI-4 PPR Options. 4181 * Attempt to negotiate 80MHz which will turn 4182 * off these options. 4183 */ 4184 if (bootverbose) { 4185 printf("(%s:%c:%d:%d): PPR Rejected. " 4186 "Trying simple U160 PPR\n", 4187 ahd_name(ahd), devinfo->channel, 4188 devinfo->target, devinfo->lun); 4189 } 4190 tinfo->goal.period = AHD_SYNCRATE_DT; 4191 tinfo->goal.ppr_options &= MSG_EXT_PPR_IU_REQ 4192 | MSG_EXT_PPR_QAS_REQ 4193 | MSG_EXT_PPR_DT_REQ; 4194 } else { 4195 /* 4196 * Target does not support the PPR message. 4197 * Attempt to negotiate SPI-2 style. 4198 */ 4199 if (bootverbose) { 4200 printf("(%s:%c:%d:%d): PPR Rejected. " 4201 "Trying WDTR/SDTR\n", 4202 ahd_name(ahd), devinfo->channel, 4203 devinfo->target, devinfo->lun); 4204 } 4205 tinfo->goal.ppr_options = 0; 4206 tinfo->curr.transport_version = 2; 4207 tinfo->goal.transport_version = 2; 4208 } 4209 ahd->msgout_index = 0; 4210 ahd->msgout_len = 0; 4211 ahd_build_transfer_msg(ahd, devinfo); 4212 ahd->msgout_index = 0; 4213 response = 1; 4214 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 4215 4216 /* note 8bit xfers */ 4217 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 4218 "8bit transfers\n", ahd_name(ahd), 4219 devinfo->channel, devinfo->target, devinfo->lun); 4220 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 4221 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4222 /*paused*/TRUE); 4223 /* 4224 * No need to clear the sync rate. If the target 4225 * did not accept the command, our syncrate is 4226 * unaffected. If the target started the negotiation, 4227 * but rejected our response, we already cleared the 4228 * sync rate before sending our WDTR. 4229 */ 4230 if (tinfo->goal.offset != tinfo->curr.offset) { 4231 4232 /* Start the sync negotiation */ 4233 ahd->msgout_index = 0; 4234 ahd->msgout_len = 0; 4235 ahd_build_transfer_msg(ahd, devinfo); 4236 ahd->msgout_index = 0; 4237 response = 1; 4238 } 4239 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 4240 /* note asynch xfers and clear flag */ 4241 ahd_set_syncrate(ahd, devinfo, /*period*/0, 4242 /*offset*/0, /*ppr_options*/0, 4243 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4244 /*paused*/TRUE); 4245 printf("(%s:%c:%d:%d): refuses synchronous negotiation. " 4246 "Using asynchronous transfers\n", 4247 ahd_name(ahd), devinfo->channel, 4248 devinfo->target, devinfo->lun); 4249 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 4250 int tag_type; 4251 int mask; 4252 4253 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 4254 4255 if (tag_type == MSG_SIMPLE_TASK) { 4256 printf("(%s:%c:%d:%d): refuses tagged commands. " 4257 "Performing non-tagged I/O\n", ahd_name(ahd), 4258 devinfo->channel, devinfo->target, devinfo->lun); 4259 ahd_set_tags(ahd, devinfo, AHD_QUEUE_NONE); 4260 mask = ~0x23; 4261 } else { 4262 printf("(%s:%c:%d:%d): refuses %s tagged commands. " 4263 "Performing simple queue tagged I/O only\n", 4264 ahd_name(ahd), devinfo->channel, devinfo->target, 4265 devinfo->lun, tag_type == MSG_ORDERED_TASK 4266 ? "ordered" : "head of queue"); 4267 ahd_set_tags(ahd, devinfo, AHD_QUEUE_BASIC); 4268 mask = ~0x03; 4269 } 4270 4271 /* 4272 * Resend the identify for this CCB as the target 4273 * may believe that the selection is invalid otherwise. 4274 */ 4275 ahd_outb(ahd, SCB_CONTROL, 4276 ahd_inb_scbram(ahd, SCB_CONTROL) & mask); 4277 scb->hscb->control &= mask; 4278 ahd_set_transaction_tag(scb, /*enabled*/FALSE, 4279 /*type*/MSG_SIMPLE_TASK); 4280 ahd_outb(ahd, MSG_OUT, MSG_IDENTIFYFLAG); 4281 ahd_assert_atn(ahd); 4282 ahd_busy_tcl(ahd, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 4283 SCB_GET_TAG(scb)); 4284 4285 /* 4286 * Requeue all tagged commands for this target 4287 * currently in our posession so they can be 4288 * converted to untagged commands. 4289 */ 4290 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 4291 SCB_GET_CHANNEL(ahd, scb), 4292 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 4293 ROLE_INITIATOR, CAM_REQUEUE_REQ, 4294 SEARCH_COMPLETE); 4295 } else if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_IDENTIFYFLAG, TRUE)) { 4296 /* 4297 * Most likely the device believes that we had 4298 * previously negotiated packetized. 4299 */ 4300 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE 4301 | MSG_FLAG_IU_REQ_CHANGED; 4302 4303 ahd_force_renegotiation(ahd, devinfo); 4304 ahd->msgout_index = 0; 4305 ahd->msgout_len = 0; 4306 ahd_build_transfer_msg(ahd, devinfo); 4307 ahd->msgout_index = 0; 4308 response = 1; 4309 } else { 4310 /* 4311 * Otherwise, we ignore it. 4312 */ 4313 printf("%s:%c:%d: Message reject for %x -- ignored\n", 4314 ahd_name(ahd), devinfo->channel, devinfo->target, 4315 last_msg); 4316 } 4317 return (response); 4318 } 4319 4320 /* 4321 * Process an ingnore wide residue message. 4322 */ 4323 static void 4324 ahd_handle_ign_wide_residue(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4325 { 4326 u_int scb_index; 4327 struct scb *scb; 4328 4329 scb_index = ahd_get_scbptr(ahd); 4330 scb = ahd_lookup_scb(ahd, scb_index); 4331 /* 4332 * XXX Actually check data direction in the sequencer? 4333 * Perhaps add datadir to some spare bits in the hscb? 4334 */ 4335 if ((ahd_inb(ahd, SEQ_FLAGS) & DPHASE) == 0 4336 || ahd_get_transfer_dir(scb) != CAM_DIR_IN) { 4337 /* 4338 * Ignore the message if we haven't 4339 * seen an appropriate data phase yet. 4340 */ 4341 } else { 4342 /* 4343 * If the residual occurred on the last 4344 * transfer and the transfer request was 4345 * expected to end on an odd count, do 4346 * nothing. Otherwise, subtract a byte 4347 * and update the residual count accordingly. 4348 */ 4349 uint32_t sgptr; 4350 4351 sgptr = ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR); 4352 if ((sgptr & SG_LIST_NULL) != 0 4353 && ahd_inb(ahd, DATA_COUNT_ODD) == 1) { 4354 /* 4355 * If the residual occurred on the last 4356 * transfer and the transfer request was 4357 * expected to end on an odd count, do 4358 * nothing. 4359 */ 4360 } else { 4361 uint32_t data_cnt; 4362 uint64_t data_addr; 4363 uint32_t sglen; 4364 4365 /* Pull in the rest of the sgptr */ 4366 sgptr |= 4367 (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 3) << 24) 4368 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 2) << 16) 4369 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 1) << 8); 4370 sgptr &= SG_PTR_MASK; 4371 data_cnt = 4372 (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+3) << 24) 4373 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+2) << 16) 4374 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+1) << 8) 4375 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT)); 4376 4377 data_addr = (((uint64_t)ahd_inb(ahd, SHADDR + 7)) << 56) 4378 | (((uint64_t)ahd_inb(ahd, SHADDR + 6)) << 48) 4379 | (((uint64_t)ahd_inb(ahd, SHADDR + 5)) << 40) 4380 | (((uint64_t)ahd_inb(ahd, SHADDR + 4)) << 32) 4381 | (ahd_inb(ahd, SHADDR + 3) << 24) 4382 | (ahd_inb(ahd, SHADDR + 2) << 16) 4383 | (ahd_inb(ahd, SHADDR + 1) << 8) 4384 | (ahd_inb(ahd, SHADDR)); 4385 4386 data_cnt += 1; 4387 data_addr -= 1; 4388 4389 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 4390 struct ahd_dma64_seg *sg; 4391 4392 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4393 4394 /* 4395 * The residual sg ptr points to the next S/G 4396 * to load so we must go back one. 4397 */ 4398 sg--; 4399 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 4400 if (sg != scb->sg_list 4401 && sglen < (data_cnt & AHD_SG_LEN_MASK)) { 4402 4403 sg--; 4404 sglen = ahd_le32toh(sg->len); 4405 /* 4406 * Preserve High Address and SG_LIST 4407 * bits while setting the count to 1. 4408 */ 4409 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); 4410 data_addr = ahd_le64toh(sg->addr) 4411 + (sglen & AHD_SG_LEN_MASK) 4412 - 1; 4413 4414 /* 4415 * Increment sg so it points to the 4416 * "next" sg. 4417 */ 4418 sg++; 4419 sgptr = ahd_sg_virt_to_bus(ahd, scb, 4420 sg); 4421 } 4422 } else { 4423 struct ahd_dma_seg *sg; 4424 4425 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4426 4427 /* 4428 * The residual sg ptr points to the next S/G 4429 * to load so we must go back one. 4430 */ 4431 sg--; 4432 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 4433 if (sg != scb->sg_list 4434 && sglen < (data_cnt & AHD_SG_LEN_MASK)) { 4435 4436 sg--; 4437 sglen = ahd_le32toh(sg->len); 4438 /* 4439 * Preserve High Address and SG_LIST 4440 * bits while setting the count to 1. 4441 */ 4442 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); 4443 data_addr = ahd_le32toh(sg->addr) 4444 + (sglen & AHD_SG_LEN_MASK) 4445 - 1; 4446 4447 /* 4448 * Increment sg so it points to the 4449 * "next" sg. 4450 */ 4451 sg++; 4452 sgptr = ahd_sg_virt_to_bus(ahd, scb, 4453 sg); 4454 } 4455 } 4456 ahd_outb(ahd, SCB_RESIDUAL_SGPTR + 3, sgptr >> 24); 4457 ahd_outb(ahd, SCB_RESIDUAL_SGPTR + 2, sgptr >> 16); 4458 ahd_outb(ahd, SCB_RESIDUAL_SGPTR + 1, sgptr >> 8); 4459 ahd_outb(ahd, SCB_RESIDUAL_SGPTR, sgptr); 4460 4461 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 3, data_cnt >> 24); 4462 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 2, data_cnt >> 16); 4463 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 1, data_cnt >> 8); 4464 ahd_outb(ahd, SCB_RESIDUAL_DATACNT, data_cnt); 4465 4466 /* 4467 * The FIFO's pointers will be updated if/when the 4468 * sequencer re-enters a data phase. 4469 */ 4470 } 4471 } 4472 } 4473 4474 4475 /* 4476 * Reinitialize the data pointers for the active transfer 4477 * based on its current residual. 4478 */ 4479 static void 4480 ahd_reinitialize_dataptrs(struct ahd_softc *ahd) 4481 { 4482 struct scb *scb; 4483 ahd_mode_state saved_modes; 4484 u_int scb_index; 4485 u_int wait; 4486 uint32_t sgptr; 4487 uint32_t resid; 4488 uint64_t dataptr; 4489 4490 AHD_ASSERT_MODES(ahd, AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK, 4491 AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK); 4492 4493 scb_index = ahd_get_scbptr(ahd); 4494 scb = ahd_lookup_scb(ahd, scb_index); 4495 4496 /* 4497 * Release and reacquire the FIFO so we 4498 * have a clean slate. 4499 */ 4500 ahd_outb(ahd, DFFSXFRCTL, CLRCHN); 4501 wait = 1000; 4502 do { 4503 ahd_delay(100); 4504 } while (--wait && !(ahd_inb(ahd, MDFFSTAT) & FIFOFREE)); 4505 if (wait == 0) { 4506 ahd_print_path(ahd, scb); 4507 printf("ahd_reinitialize_dataptrs: Forcing FIFO free.\n"); 4508 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); 4509 } 4510 saved_modes = ahd_save_modes(ahd); 4511 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 4512 ahd_outb(ahd, DFFSTAT, 4513 ahd_inb(ahd, DFFSTAT) 4514 | (saved_modes == 0x11 ? CURRFIFO_1 : CURRFIFO_0)); 4515 4516 /* 4517 * Determine initial values for data_addr and data_cnt 4518 * for resuming the data phase. 4519 */ 4520 sgptr = (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 3) << 24) 4521 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 2) << 16) 4522 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR + 1) << 8) 4523 | ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR); 4524 sgptr &= SG_PTR_MASK; 4525 4526 resid = (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 2) << 16) 4527 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 1) << 8) 4528 | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT); 4529 4530 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 4531 struct ahd_dma64_seg *sg; 4532 4533 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4534 4535 /* The residual sg_ptr always points to the next sg */ 4536 sg--; 4537 4538 dataptr = ahd_le64toh(sg->addr) 4539 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK) 4540 - resid; 4541 ahd_outb(ahd, HADDR + 7, dataptr >> 56); 4542 ahd_outb(ahd, HADDR + 6, dataptr >> 48); 4543 ahd_outb(ahd, HADDR + 5, dataptr >> 40); 4544 ahd_outb(ahd, HADDR + 4, dataptr >> 32); 4545 } else { 4546 struct ahd_dma_seg *sg; 4547 4548 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4549 4550 /* The residual sg_ptr always points to the next sg */ 4551 sg--; 4552 4553 dataptr = ahd_le32toh(sg->addr) 4554 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK) 4555 - resid; 4556 ahd_outb(ahd, HADDR + 4, 4557 (ahd_le32toh(sg->len) & ~AHD_SG_LEN_MASK) >> 24); 4558 } 4559 ahd_outb(ahd, HADDR + 3, dataptr >> 24); 4560 ahd_outb(ahd, HADDR + 2, dataptr >> 16); 4561 ahd_outb(ahd, HADDR + 1, dataptr >> 8); 4562 ahd_outb(ahd, HADDR, dataptr); 4563 ahd_outb(ahd, HCNT + 2, resid >> 16); 4564 ahd_outb(ahd, HCNT + 1, resid >> 8); 4565 ahd_outb(ahd, HCNT, resid); 4566 } 4567 4568 /* 4569 * Handle the effects of issuing a bus device reset message. 4570 */ 4571 static void 4572 ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 4573 u_int lun, cam_status status, char *message, 4574 int verbose_level) 4575 { 4576 #ifdef AHD_TARGET_MODE 4577 struct ahd_tmode_tstate* tstate; 4578 #endif 4579 int found; 4580 4581 found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, 4582 lun, SCB_LIST_NULL, devinfo->role, 4583 status); 4584 4585 #ifdef AHD_TARGET_MODE 4586 /* 4587 * Send an immediate notify ccb to all target mord peripheral 4588 * drivers affected by this action. 4589 */ 4590 tstate = ahd->enabled_targets[devinfo->our_scsiid]; 4591 if (tstate != NULL) { 4592 u_int cur_lun; 4593 u_int max_lun; 4594 4595 if (lun != CAM_LUN_WILDCARD) { 4596 cur_lun = 0; 4597 max_lun = AHD_NUM_LUNS - 1; 4598 } else { 4599 cur_lun = lun; 4600 max_lun = lun; 4601 } 4602 for (cur_lun <= max_lun; cur_lun++) { 4603 struct ahd_tmode_lstate* lstate; 4604 4605 lstate = tstate->enabled_luns[cur_lun]; 4606 if (lstate == NULL) 4607 continue; 4608 4609 ahd_queue_lstate_event(ahd, lstate, devinfo->our_scsiid, 4610 MSG_BUS_DEV_RESET, /*arg*/0); 4611 ahd_send_lstate_events(ahd, lstate); 4612 } 4613 } 4614 #endif 4615 4616 /* 4617 * Go back to async/narrow transfers and renegotiate. 4618 */ 4619 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 4620 AHD_TRANS_CUR, /*paused*/TRUE); 4621 ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0, 4622 /*ppr_options*/0, AHD_TRANS_CUR, /*paused*/TRUE); 4623 4624 ahd_send_async(ahd, devinfo->channel, devinfo->target, 4625 lun, AC_SENT_BDR, NULL); 4626 4627 if (message != NULL 4628 && (verbose_level <= bootverbose)) 4629 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd), 4630 message, devinfo->channel, devinfo->target, found); 4631 } 4632 4633 #ifdef AHD_TARGET_MODE 4634 static void 4635 ahd_setup_target_msgin(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 4636 struct scb *scb) 4637 { 4638 4639 /* 4640 * To facilitate adding multiple messages together, 4641 * each routine should increment the index and len 4642 * variables instead of setting them explicitly. 4643 */ 4644 ahd->msgout_index = 0; 4645 ahd->msgout_len = 0; 4646 4647 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 4648 ahd_build_transfer_msg(ahd, devinfo); 4649 else 4650 panic("ahd_intr: AWAITING target message with no message"); 4651 4652 ahd->msgout_index = 0; 4653 ahd->msg_type = MSG_TYPE_TARGET_MSGIN; 4654 } 4655 #endif 4656 /**************************** Initialization **********************************/ 4657 static u_int 4658 ahd_sglist_size(struct ahd_softc *ahd) 4659 { 4660 bus_size_t list_size; 4661 4662 list_size = sizeof(struct ahd_dma_seg) * AHD_NSEG; 4663 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 4664 list_size = sizeof(struct ahd_dma64_seg) * AHD_NSEG; 4665 return (list_size); 4666 } 4667 4668 /* 4669 * Calculate the optimum S/G List allocation size. S/G elements used 4670 * for a given transaction must be physically contiguous. Assume the 4671 * OS will allocate full pages to us, so it doesn't make sense to request 4672 * less than a page. 4673 */ 4674 static u_int 4675 ahd_sglist_allocsize(struct ahd_softc *ahd) 4676 { 4677 bus_size_t sg_list_increment; 4678 bus_size_t sg_list_size; 4679 bus_size_t max_list_size; 4680 bus_size_t best_list_size; 4681 4682 /* Start out with the minimum required for AHD_NSEG. */ 4683 sg_list_increment = ahd_sglist_size(ahd); 4684 sg_list_size = sg_list_increment; 4685 4686 /* Get us as close as possible to a page in size. */ 4687 while ((sg_list_size + sg_list_increment) <= PAGE_SIZE) 4688 sg_list_size += sg_list_increment; 4689 4690 /* 4691 * Try to reduce the amount of wastage by allocating 4692 * multiple pages. 4693 */ 4694 best_list_size = sg_list_size; 4695 max_list_size = roundup(sg_list_increment, PAGE_SIZE); 4696 if (max_list_size < 4 * PAGE_SIZE) 4697 max_list_size = 4 * PAGE_SIZE; 4698 if (max_list_size > (AHD_SCB_MAX_ALLOC * sg_list_increment)) 4699 max_list_size = (AHD_SCB_MAX_ALLOC * sg_list_increment); 4700 while ((sg_list_size + sg_list_increment) <= max_list_size 4701 && (sg_list_size % PAGE_SIZE) != 0) { 4702 bus_size_t new_mod; 4703 bus_size_t best_mod; 4704 4705 sg_list_size += sg_list_increment; 4706 new_mod = sg_list_size % PAGE_SIZE; 4707 best_mod = best_list_size % PAGE_SIZE; 4708 if (new_mod > best_mod || new_mod == 0) { 4709 best_list_size = sg_list_size; 4710 } 4711 } 4712 return (best_list_size); 4713 } 4714 4715 /* 4716 * Allocate a controller structure for a new device 4717 * and perform initial initializion. 4718 */ 4719 struct ahd_softc * 4720 ahd_alloc(void *platform_arg, char *name) 4721 { 4722 struct ahd_softc *ahd; 4723 4724 #ifndef __FreeBSD__ 4725 ahd = malloc(sizeof(*ahd), M_DEVBUF, M_NOWAIT); 4726 if (!ahd) { 4727 printf("aic7xxx: cannot malloc softc!\n"); 4728 free(name, M_DEVBUF); 4729 return NULL; 4730 } 4731 #else 4732 ahd = device_get_softc((device_t)platform_arg); 4733 #endif 4734 memset(ahd, 0, sizeof(*ahd)); 4735 ahd->seep_config = malloc(sizeof(*ahd->seep_config), 4736 M_DEVBUF, M_NOWAIT); 4737 if (ahd->seep_config == NULL) { 4738 #ifndef __FreeBSD__ 4739 free(ahd, M_DEVBUF); 4740 #endif 4741 free(name, M_DEVBUF); 4742 return (NULL); 4743 } 4744 LIST_INIT(&ahd->pending_scbs); 4745 /* We don't know our unit number until the OSM sets it */ 4746 ahd->name = name; 4747 ahd->unit = -1; 4748 ahd->description = NULL; 4749 ahd->bus_description = NULL; 4750 ahd->channel = 'A'; 4751 ahd->chip = AHD_NONE; 4752 ahd->features = AHD_FENONE; 4753 ahd->bugs = AHD_BUGNONE; 4754 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A 4755 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A; 4756 ahd_timer_init(&ahd->reset_timer); 4757 ahd_timer_init(&ahd->stat_timer); 4758 ahd->int_coalessing_timer = AHD_INT_COALESSING_TIMER_DEFAULT; 4759 ahd->int_coalessing_maxcmds = AHD_INT_COALESSING_MAXCMDS_DEFAULT; 4760 ahd->int_coalessing_mincmds = AHD_INT_COALESSING_MINCMDS_DEFAULT; 4761 ahd->int_coalessing_threshold = AHD_INT_COALESSING_THRESHOLD_DEFAULT; 4762 ahd->int_coalessing_stop_threshold = 4763 AHD_INT_COALESSING_STOP_THRESHOLD_DEFAULT; 4764 4765 if (ahd_platform_alloc(ahd, platform_arg) != 0) { 4766 ahd_free(ahd); 4767 ahd = NULL; 4768 } 4769 #ifdef AHD_DEBUG 4770 if ((ahd_debug & AHD_SHOW_MEMORY) != 0) { 4771 printf("%s: scb size = 0x%x, hscb size = 0x%x\n", 4772 ahd_name(ahd), (u_int)sizeof(struct scb), 4773 (u_int)sizeof(struct hardware_scb)); 4774 } 4775 #endif 4776 return (ahd); 4777 } 4778 4779 int 4780 ahd_softc_init(struct ahd_softc *ahd) 4781 { 4782 4783 ahd->unpause = 0; 4784 ahd->pause = PAUSE; 4785 return (0); 4786 } 4787 4788 void 4789 ahd_softc_insert(struct ahd_softc *ahd) 4790 { 4791 struct ahd_softc *list_ahd; 4792 4793 #if AHD_PCI_CONFIG > 0 4794 /* 4795 * Second Function PCI devices need to inherit some 4796 * settings from function 0. 4797 */ 4798 if ((ahd->features & AHD_MULTI_FUNC) != 0) { 4799 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) { 4800 ahd_dev_softc_t list_pci; 4801 ahd_dev_softc_t pci; 4802 4803 list_pci = list_ahd->dev_softc; 4804 pci = ahd->dev_softc; 4805 if (ahd_get_pci_slot(list_pci) == ahd_get_pci_slot(pci) 4806 && ahd_get_pci_bus(list_pci) == ahd_get_pci_bus(pci)) { 4807 struct ahd_softc *master; 4808 struct ahd_softc *slave; 4809 4810 if (ahd_get_pci_function(list_pci) == 0) { 4811 master = list_ahd; 4812 slave = ahd; 4813 } else { 4814 master = ahd; 4815 slave = list_ahd; 4816 } 4817 slave->flags &= ~AHD_BIOS_ENABLED; 4818 slave->flags |= 4819 master->flags & AHD_BIOS_ENABLED; 4820 slave->flags &= ~AHD_PRIMARY_CHANNEL; 4821 slave->flags |= 4822 master->flags & AHD_PRIMARY_CHANNEL; 4823 break; 4824 } 4825 } 4826 } 4827 #endif 4828 4829 /* 4830 * Insertion sort into our list of softcs. 4831 */ 4832 list_ahd = TAILQ_FIRST(&ahd_tailq); 4833 while (list_ahd != NULL 4834 && ahd_softc_comp(list_ahd, ahd) <= 0) 4835 list_ahd = TAILQ_NEXT(list_ahd, links); 4836 if (list_ahd != NULL) 4837 TAILQ_INSERT_BEFORE(list_ahd, ahd, links); 4838 else 4839 TAILQ_INSERT_TAIL(&ahd_tailq, ahd, links); 4840 ahd->init_level++; 4841 } 4842 4843 /* 4844 * Verify that the passed in softc pointer is for a 4845 * controller that is still configured. 4846 */ 4847 struct ahd_softc * 4848 ahd_find_softc(struct ahd_softc *ahd) 4849 { 4850 struct ahd_softc *list_ahd; 4851 4852 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) { 4853 if (list_ahd == ahd) 4854 return (ahd); 4855 } 4856 return (NULL); 4857 } 4858 4859 void 4860 ahd_set_unit(struct ahd_softc *ahd, int unit) 4861 { 4862 ahd->unit = unit; 4863 } 4864 4865 void 4866 ahd_set_name(struct ahd_softc *ahd, char *name) 4867 { 4868 if (ahd->name != NULL) 4869 free(ahd->name, M_DEVBUF); 4870 ahd->name = name; 4871 } 4872 4873 void 4874 ahd_free(struct ahd_softc *ahd) 4875 { 4876 int i; 4877 4878 ahd_fini_scbdata(ahd); 4879 switch (ahd->init_level) { 4880 default: 4881 case 5: 4882 ahd_shutdown(ahd); 4883 TAILQ_REMOVE(&ahd_tailq, ahd, links); 4884 /* FALLTHROUGH */ 4885 case 4: 4886 ahd_dmamap_unload(ahd, ahd->shared_data_dmat, 4887 ahd->shared_data_dmamap); 4888 /* FALLTHROUGH */ 4889 case 3: 4890 ahd_dmamem_free(ahd, ahd->shared_data_dmat, ahd->qoutfifo, 4891 ahd->shared_data_dmamap); 4892 ahd_dmamap_destroy(ahd, ahd->shared_data_dmat, 4893 ahd->shared_data_dmamap); 4894 /* FALLTHROUGH */ 4895 case 2: 4896 ahd_dma_tag_destroy(ahd, ahd->shared_data_dmat); 4897 case 1: 4898 #ifndef __linux__ 4899 ahd_dma_tag_destroy(ahd, ahd->buffer_dmat); 4900 #endif 4901 break; 4902 case 0: 4903 break; 4904 } 4905 4906 #ifndef __linux__ 4907 ahd_dma_tag_destroy(ahd, ahd->parent_dmat); 4908 #endif 4909 ahd_platform_free(ahd); 4910 for (i = 0; i < AHD_NUM_TARGETS; i++) { 4911 struct ahd_tmode_tstate *tstate; 4912 4913 tstate = ahd->enabled_targets[i]; 4914 if (tstate != NULL) { 4915 #if AHD_TARGET_MODE 4916 int j; 4917 4918 for (j = 0; j < AHD_NUM_LUNS; j++) { 4919 struct ahd_tmode_lstate *lstate; 4920 4921 lstate = tstate->enabled_luns[j]; 4922 if (lstate != NULL) { 4923 xpt_free_path(lstate->path); 4924 free(lstate, M_DEVBUF); 4925 } 4926 } 4927 #endif 4928 free(tstate, M_DEVBUF); 4929 } 4930 } 4931 #if AHD_TARGET_MODE 4932 if (ahd->black_hole != NULL) { 4933 xpt_free_path(ahd->black_hole->path); 4934 free(ahd->black_hole, M_DEVBUF); 4935 } 4936 #endif 4937 if (ahd->name != NULL) 4938 free(ahd->name, M_DEVBUF); 4939 if (ahd->seep_config != NULL) 4940 free(ahd->seep_config, M_DEVBUF); 4941 if (ahd->saved_stack != NULL) 4942 free(ahd->saved_stack, M_DEVBUF); 4943 #ifndef __FreeBSD__ 4944 free(ahd, M_DEVBUF); 4945 #endif 4946 return; 4947 } 4948 4949 void 4950 ahd_shutdown(void *arg) 4951 { 4952 struct ahd_softc *ahd; 4953 4954 ahd = (struct ahd_softc *)arg; 4955 4956 /* 4957 * Stop periodic timer callbacks. 4958 */ 4959 ahd_timer_stop(&ahd->reset_timer); 4960 ahd_timer_stop(&ahd->stat_timer); 4961 4962 /* This will reset most registers to 0, but not all */ 4963 ahd_reset(ahd); 4964 } 4965 4966 /* 4967 * Reset the controller and record some information about it 4968 * that is only available just after a reset. 4969 */ 4970 int 4971 ahd_reset(struct ahd_softc *ahd) 4972 { 4973 u_int sxfrctl1; 4974 int wait; 4975 uint32_t cmd; 4976 4977 /* 4978 * Preserve the value of the SXFRCTL1 register for all channels. 4979 * It contains settings that affect termination and we don't want 4980 * to disturb the integrity of the bus. 4981 */ 4982 ahd_pause(ahd); 4983 sxfrctl1 = ahd_inb(ahd, SXFRCTL1); 4984 4985 cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 4986 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { 4987 uint32_t mod_cmd; 4988 4989 /* 4990 * A4 Razor #632 4991 * During the assertion of CHIPRST, the chip 4992 * does not disable its parity logic prior to 4993 * the start of the reset. This may cause a 4994 * parity error to be detected and thus a 4995 * spurious SERR or PERR assertion. Disble 4996 * PERR and SERR responses during the CHIPRST. 4997 */ 4998 mod_cmd = cmd & ~(PCIM_CMD_PERRESPEN|PCIM_CMD_SERRESPEN); 4999 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 5000 mod_cmd, /*bytes*/2); 5001 } 5002 ahd_outb(ahd, HCNTRL, CHIPRST | ahd->pause); 5003 5004 /* 5005 * Ensure that the reset has finished. We delay 1000us 5006 * prior to reading the register to make sure the chip 5007 * has sufficiently completed its reset to handle register 5008 * accesses. 5009 */ 5010 wait = 1000; 5011 do { 5012 ahd_delay(1000); 5013 } while (--wait && !(ahd_inb(ahd, HCNTRL) & CHIPRSTACK)); 5014 5015 if (wait == 0) { 5016 printf("%s: WARNING - Failed chip reset! " 5017 "Trying to initialize anyway.\n", ahd_name(ahd)); 5018 } 5019 ahd_outb(ahd, HCNTRL, ahd->pause); 5020 5021 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { 5022 /* 5023 * Clear any latched PCI error status and restore 5024 * previous SERR and PERR response enables. 5025 */ 5026 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 5027 0xFF, /*bytes*/1); 5028 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 5029 cmd, /*bytes*/2); 5030 } 5031 /* After a reset, we know the state of the mode register. */ 5032 ahd_known_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5033 5034 /* Determine chip configuration */ 5035 ahd->features &= ~AHD_WIDE; 5036 if ((ahd_inb(ahd, SBLKCTL) & SELWIDE) != 0) 5037 ahd->features |= AHD_WIDE; 5038 5039 /* 5040 * Restore SXFRCTL1. 5041 * 5042 * We must always initialize STPWEN to 1 before we 5043 * restore the saved values. STPWEN is initialized 5044 * to a tri-state condition which can only be cleared 5045 * by turning it on. 5046 */ 5047 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 5048 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 5049 5050 /* 5051 * If a recovery action has forced a chip reset, 5052 * re-initialize the chip to our likeing. 5053 */ 5054 if (ahd->init_level > 0) 5055 ahd_chip_init(ahd); 5056 5057 return (0); 5058 } 5059 5060 /* 5061 * Determine the number of SCBs available on the controller 5062 */ 5063 int 5064 ahd_probe_scbs(struct ahd_softc *ahd) { 5065 int i; 5066 5067 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 5068 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 5069 for (i = 0; i < AHD_SCB_MAX; i++) { 5070 int j; 5071 5072 ahd_set_scbptr(ahd, i); 5073 ahd_outw(ahd, SCB_BASE, i); 5074 for (j = 2; j < 64; j++) 5075 ahd_outb(ahd, SCB_BASE+j, 0); 5076 /* Start out life as unallocated (needing an abort) */ 5077 ahd_outb(ahd, SCB_CONTROL, MK_MESSAGE); 5078 if (ahd_inw_scbram(ahd, SCB_BASE) != i) 5079 break; 5080 ahd_set_scbptr(ahd, 0); 5081 if (ahd_inw_scbram(ahd, SCB_BASE) != 0) 5082 break; 5083 } 5084 return (i); 5085 } 5086 5087 static void 5088 ahd_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 5089 { 5090 bus_addr_t *baddr; 5091 5092 baddr = (bus_addr_t *)arg; 5093 *baddr = segs->ds_addr; 5094 } 5095 5096 static void 5097 ahd_initialize_hscbs(struct ahd_softc *ahd) 5098 { 5099 int i; 5100 5101 for (i = 0; i < ahd->scb_data.maxhscbs; i++) { 5102 ahd_set_scbptr(ahd, i); 5103 5104 /* Clear the control byte. */ 5105 ahd_outb(ahd, SCB_CONTROL, 0); 5106 5107 /* Set the next pointer */ 5108 ahd_outw(ahd, SCB_NEXT, SCB_LIST_NULL); 5109 } 5110 } 5111 5112 static int 5113 ahd_init_scbdata(struct ahd_softc *ahd) 5114 { 5115 struct scb_data *scb_data; 5116 int i; 5117 5118 scb_data = &ahd->scb_data; 5119 TAILQ_INIT(&scb_data->free_scbs); 5120 for (i = 0; i < AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT; i++) 5121 LIST_INIT(&scb_data->free_scb_lists[i]); 5122 LIST_INIT(&scb_data->any_dev_free_scb_list); 5123 SLIST_INIT(&scb_data->hscb_maps); 5124 SLIST_INIT(&scb_data->sg_maps); 5125 SLIST_INIT(&scb_data->sense_maps); 5126 5127 /* Determine the number of hardware SCBs and initialize them */ 5128 scb_data->maxhscbs = ahd_probe_scbs(ahd); 5129 if (scb_data->maxhscbs == 0) { 5130 printf("%s: No SCB space found\n", ahd_name(ahd)); 5131 return (ENXIO); 5132 } 5133 5134 ahd_initialize_hscbs(ahd); 5135 5136 /* 5137 * Create our DMA tags. These tags define the kinds of device 5138 * accessible memory allocations and memory mappings we will 5139 * need to perform during normal operation. 5140 * 5141 * Unless we need to further restrict the allocation, we rely 5142 * on the restrictions of the parent dmat, hence the common 5143 * use of MAXADDR and MAXSIZE. 5144 */ 5145 5146 /* DMA tag for our hardware scb structures */ 5147 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1, 5148 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 5149 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 5150 /*highaddr*/BUS_SPACE_MAXADDR, 5151 /*filter*/NULL, /*filterarg*/NULL, 5152 PAGE_SIZE, /*nsegments*/1, 5153 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 5154 /*flags*/0, &scb_data->hscb_dmat) != 0) { 5155 goto error_exit; 5156 } 5157 5158 scb_data->init_level++; 5159 5160 /* DMA tag for our S/G structures. */ 5161 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1, 5162 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 5163 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 5164 /*highaddr*/BUS_SPACE_MAXADDR, 5165 /*filter*/NULL, /*filterarg*/NULL, 5166 ahd_sglist_allocsize(ahd), /*nsegments*/1, 5167 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 5168 /*flags*/0, &scb_data->sg_dmat) != 0) { 5169 goto error_exit; 5170 } 5171 #ifdef AHD_DEBUG 5172 if ((ahd_debug & AHD_SHOW_MEMORY) != 0) 5173 printf("%s: ahd_sglist_allocsize = 0x%x\n", ahd_name(ahd), 5174 ahd_sglist_allocsize(ahd)); 5175 #endif 5176 5177 scb_data->init_level++; 5178 5179 /* DMA tag for our sense buffers. We allocate in page sized chunks */ 5180 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1, 5181 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 5182 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 5183 /*highaddr*/BUS_SPACE_MAXADDR, 5184 /*filter*/NULL, /*filterarg*/NULL, 5185 PAGE_SIZE, /*nsegments*/1, 5186 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 5187 /*flags*/0, &scb_data->sense_dmat) != 0) { 5188 goto error_exit; 5189 } 5190 5191 scb_data->init_level++; 5192 5193 /* Perform initial CCB allocation */ 5194 ahd_alloc_scbs(ahd); 5195 5196 if (scb_data->numscbs == 0) { 5197 printf("%s: ahd_init_scbdata - " 5198 "Unable to allocate initial scbs\n", 5199 ahd_name(ahd)); 5200 goto error_exit; 5201 } 5202 5203 /* 5204 * Note that we were successfull 5205 */ 5206 return (0); 5207 5208 error_exit: 5209 5210 return (ENOMEM); 5211 } 5212 5213 static struct scb * 5214 ahd_find_scb_by_tag(struct ahd_softc *ahd, u_int tag) 5215 { 5216 struct scb *scb; 5217 5218 /* 5219 * Look on the pending list. 5220 */ 5221 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 5222 if (SCB_GET_TAG(scb) == tag) 5223 return (scb); 5224 } 5225 5226 /* 5227 * Then on all of the collision free lists. 5228 */ 5229 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 5230 struct scb *list_scb; 5231 5232 list_scb = scb; 5233 do { 5234 if (SCB_GET_TAG(list_scb) == tag) 5235 return (list_scb); 5236 list_scb = LIST_NEXT(list_scb, collision_links); 5237 } while (list_scb); 5238 } 5239 5240 /* 5241 * And finally on the generic free list. 5242 */ 5243 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { 5244 if (SCB_GET_TAG(scb) == tag) 5245 return (scb); 5246 } 5247 5248 return (NULL); 5249 } 5250 5251 static void 5252 ahd_fini_scbdata(struct ahd_softc *ahd) 5253 { 5254 struct scb_data *scb_data; 5255 5256 scb_data = &ahd->scb_data; 5257 if (scb_data == NULL) 5258 return; 5259 5260 switch (scb_data->init_level) { 5261 default: 5262 case 7: 5263 { 5264 struct map_node *sns_map; 5265 5266 while ((sns_map = SLIST_FIRST(&scb_data->sense_maps)) != NULL) { 5267 SLIST_REMOVE_HEAD(&scb_data->sense_maps, links); 5268 ahd_dmamap_unload(ahd, scb_data->sense_dmat, 5269 sns_map->dmamap); 5270 ahd_dmamem_free(ahd, scb_data->sense_dmat, 5271 sns_map->vaddr, sns_map->dmamap); 5272 free(sns_map, M_DEVBUF); 5273 } 5274 ahd_dma_tag_destroy(ahd, scb_data->sense_dmat); 5275 /* FALLTHROUGH */ 5276 } 5277 case 6: 5278 { 5279 struct map_node *sg_map; 5280 5281 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)) != NULL) { 5282 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 5283 ahd_dmamap_unload(ahd, scb_data->sg_dmat, 5284 sg_map->dmamap); 5285 ahd_dmamem_free(ahd, scb_data->sg_dmat, 5286 sg_map->vaddr, sg_map->dmamap); 5287 free(sg_map, M_DEVBUF); 5288 } 5289 ahd_dma_tag_destroy(ahd, scb_data->sg_dmat); 5290 /* FALLTHROUGH */ 5291 } 5292 case 5: 5293 { 5294 struct map_node *hscb_map; 5295 5296 while ((hscb_map = SLIST_FIRST(&scb_data->hscb_maps)) != NULL) { 5297 SLIST_REMOVE_HEAD(&scb_data->hscb_maps, links); 5298 ahd_dmamap_unload(ahd, scb_data->hscb_dmat, 5299 hscb_map->dmamap); 5300 ahd_dmamem_free(ahd, scb_data->hscb_dmat, 5301 hscb_map->vaddr, hscb_map->dmamap); 5302 free(hscb_map, M_DEVBUF); 5303 } 5304 ahd_dma_tag_destroy(ahd, scb_data->hscb_dmat); 5305 /* FALLTHROUGH */ 5306 } 5307 case 4: 5308 case 3: 5309 case 2: 5310 case 1: 5311 case 0: 5312 break; 5313 } 5314 } 5315 5316 /* 5317 * DSP filter Bypass must be enabled until the first selection 5318 * after a change in bus mode (Razor #491 and #493). 5319 */ 5320 static void 5321 ahd_setup_iocell_workaround(struct ahd_softc *ahd) 5322 { 5323 ahd_mode_state saved_modes; 5324 5325 saved_modes = ahd_save_modes(ahd); 5326 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5327 ahd_outb(ahd, DSPDATACTL, ahd_inb(ahd, DSPDATACTL) 5328 | BYPASSENAB | RCVROFFSTDIS | XMITOFFSTDIS); 5329 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) | (ENSELDO|ENSELDI)); 5330 #ifdef AHD_DEBUG 5331 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5332 printf("%s: Setting up iocell workaround\n", ahd_name(ahd)); 5333 #endif 5334 ahd_restore_modes(ahd, saved_modes); 5335 } 5336 5337 static void 5338 ahd_iocell_first_selection(struct ahd_softc *ahd) 5339 { 5340 ahd_mode_state saved_modes; 5341 u_int sblkctl; 5342 5343 saved_modes = ahd_save_modes(ahd); 5344 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5345 sblkctl = ahd_inb(ahd, SBLKCTL); 5346 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5347 #ifdef AHD_DEBUG 5348 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5349 printf("%s: iocell first selection\n", ahd_name(ahd)); 5350 #endif 5351 if ((sblkctl & ENAB40) != 0) { 5352 ahd_outb(ahd, DSPDATACTL, 5353 ahd_inb(ahd, DSPDATACTL) & ~BYPASSENAB); 5354 #ifdef AHD_DEBUG 5355 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5356 printf("%s: BYPASS now disabled\n", ahd_name(ahd)); 5357 #endif 5358 } 5359 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) & ~(ENSELDO|ENSELDI)); 5360 ahd_outb(ahd, CLRINT, CLRSCSIINT); 5361 ahd_restore_modes(ahd, saved_modes); 5362 } 5363 5364 /*************************** SCB Management ***********************************/ 5365 static void 5366 ahd_add_col_list(struct ahd_softc *ahd, struct scb *scb, u_int col_idx) 5367 { 5368 struct scb_list *free_list; 5369 struct scb_tailq *free_tailq; 5370 struct scb *first_scb; 5371 5372 scb->flags |= SCB_ON_COL_LIST; 5373 AHD_SET_SCB_COL_IDX(scb, col_idx); 5374 free_list = &ahd->scb_data.free_scb_lists[col_idx]; 5375 free_tailq = &ahd->scb_data.free_scbs; 5376 first_scb = LIST_FIRST(free_list); 5377 if (first_scb != NULL) { 5378 LIST_INSERT_AFTER(first_scb, scb, collision_links); 5379 } else { 5380 LIST_INSERT_HEAD(free_list, scb, collision_links); 5381 TAILQ_INSERT_TAIL(free_tailq, scb, links.tqe); 5382 } 5383 } 5384 5385 static void 5386 ahd_rem_col_list(struct ahd_softc *ahd, struct scb *scb) 5387 { 5388 struct scb_list *free_list; 5389 struct scb_tailq *free_tailq; 5390 struct scb *first_scb; 5391 u_int col_idx; 5392 5393 scb->flags &= ~SCB_ON_COL_LIST; 5394 col_idx = AHD_GET_SCB_COL_IDX(ahd, scb); 5395 free_list = &ahd->scb_data.free_scb_lists[col_idx]; 5396 free_tailq = &ahd->scb_data.free_scbs; 5397 first_scb = LIST_FIRST(free_list); 5398 if (first_scb == scb) { 5399 struct scb *next_scb; 5400 5401 /* 5402 * Maintain order in the collision free 5403 * lists for fairness if this device has 5404 * other colliding tags active. 5405 */ 5406 next_scb = LIST_NEXT(scb, collision_links); 5407 if (next_scb != NULL) { 5408 TAILQ_INSERT_AFTER(free_tailq, scb, 5409 next_scb, links.tqe); 5410 } 5411 TAILQ_REMOVE(free_tailq, scb, links.tqe); 5412 } 5413 LIST_REMOVE(scb, collision_links); 5414 } 5415 5416 /* 5417 * Get a free scb. If there are none, see if we can allocate a new SCB. 5418 */ 5419 struct scb * 5420 ahd_get_scb(struct ahd_softc *ahd, u_int col_idx) 5421 { 5422 struct scb *scb; 5423 int tries; 5424 5425 tries = 0; 5426 look_again: 5427 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 5428 if (AHD_GET_SCB_COL_IDX(ahd, scb) != col_idx) { 5429 ahd_rem_col_list(ahd, scb); 5430 goto found; 5431 } 5432 } 5433 if ((scb = LIST_FIRST(&ahd->scb_data.any_dev_free_scb_list)) == NULL) { 5434 5435 if (tries++ != 0) 5436 return (NULL); 5437 ahd_alloc_scbs(ahd); 5438 goto look_again; 5439 } 5440 LIST_REMOVE(scb, links.le); 5441 if (col_idx != AHD_NEVER_COL_IDX 5442 && (scb->col_scb != NULL) 5443 && (scb->col_scb->flags & SCB_ACTIVE) == 0) { 5444 LIST_REMOVE(scb->col_scb, links.le); 5445 ahd_add_col_list(ahd, scb->col_scb, col_idx); 5446 } 5447 found: 5448 scb->flags |= SCB_ACTIVE; 5449 return (scb); 5450 } 5451 5452 /* 5453 * Return an SCB resource to the free list. 5454 */ 5455 void 5456 ahd_free_scb(struct ahd_softc *ahd, struct scb *scb) 5457 { 5458 5459 /* Clean up for the next user */ 5460 scb->flags = SCB_FLAG_NONE; 5461 scb->hscb->control = 0; 5462 ahd->scb_data.scbindex[scb->hscb->tag] = NULL; 5463 5464 if (scb->col_scb == NULL) { 5465 5466 /* 5467 * No collision possible. Just free normally. 5468 */ 5469 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5470 scb, links.le); 5471 } else if ((scb->col_scb->flags & SCB_ON_COL_LIST) != 0) { 5472 5473 /* 5474 * The SCB we might have collided with is on 5475 * a free collision list. Put both SCBs on 5476 * the generic list. 5477 */ 5478 ahd_rem_col_list(ahd, scb->col_scb); 5479 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5480 scb, links.le); 5481 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5482 scb->col_scb, links.le); 5483 } else if ((scb->col_scb->flags 5484 & (SCB_PACKETIZED|SCB_ACTIVE)) == SCB_ACTIVE 5485 && (scb->col_scb->hscb->control & TAG_ENB) != 0) { 5486 5487 /* 5488 * The SCB we might collide with on the next allocation 5489 * is still active in a non-packetized, tagged, context. 5490 * Put us on the SCB collision list. 5491 */ 5492 ahd_add_col_list(ahd, scb, 5493 AHD_GET_SCB_COL_IDX(ahd, scb->col_scb)); 5494 } else { 5495 /* 5496 * The SCB we might collide with on the next allocation 5497 * is either active in a packetized context, or free. 5498 * Since we can't collide, put this SCB on the generic 5499 * free list. 5500 */ 5501 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5502 scb, links.le); 5503 } 5504 5505 ahd_platform_scb_free(ahd, scb); 5506 } 5507 5508 void 5509 ahd_alloc_scbs(struct ahd_softc *ahd) 5510 { 5511 struct scb_data *scb_data; 5512 struct scb *next_scb; 5513 struct hardware_scb *hscb; 5514 struct map_node *hscb_map; 5515 struct map_node *sg_map; 5516 struct map_node *sense_map; 5517 uint8_t *segs; 5518 uint8_t *sense_data; 5519 bus_addr_t hscb_busaddr; 5520 bus_addr_t sg_busaddr; 5521 bus_addr_t sense_busaddr; 5522 int newcount; 5523 int i; 5524 5525 scb_data = &ahd->scb_data; 5526 if (scb_data->numscbs >= AHD_SCB_MAX_ALLOC) 5527 /* Can't allocate any more */ 5528 return; 5529 5530 if (scb_data->scbs_left != 0) { 5531 int offset; 5532 5533 offset = (PAGE_SIZE / sizeof(*hscb)) - scb_data->scbs_left; 5534 hscb_map = SLIST_FIRST(&scb_data->hscb_maps); 5535 hscb = &((struct hardware_scb *)hscb_map->vaddr)[offset]; 5536 hscb_busaddr = hscb_map->physaddr + (offset * sizeof(*hscb)); 5537 } else { 5538 hscb_map = malloc(sizeof(*hscb_map), M_DEVBUF, M_NOWAIT); 5539 5540 if (hscb_map == NULL) 5541 return; 5542 5543 /* Allocate the next batch of hardware SCBs */ 5544 if (ahd_dmamem_alloc(ahd, scb_data->hscb_dmat, 5545 (void **)&hscb_map->vaddr, 5546 BUS_DMA_NOWAIT, &hscb_map->dmamap) != 0) { 5547 free(hscb_map, M_DEVBUF); 5548 return; 5549 } 5550 5551 SLIST_INSERT_HEAD(&scb_data->hscb_maps, hscb_map, links); 5552 5553 ahd_dmamap_load(ahd, scb_data->hscb_dmat, hscb_map->dmamap, 5554 hscb_map->vaddr, PAGE_SIZE, ahd_dmamap_cb, 5555 &hscb_map->physaddr, /*flags*/0); 5556 5557 hscb = (struct hardware_scb *)hscb_map->vaddr; 5558 hscb_busaddr = hscb_map->physaddr; 5559 scb_data->scbs_left = PAGE_SIZE / sizeof(*hscb); 5560 } 5561 5562 if (scb_data->sgs_left != 0) { 5563 int offset; 5564 5565 offset = ahd_sglist_allocsize(ahd) 5566 - (scb_data->sgs_left * ahd_sglist_size(ahd)); 5567 sg_map = SLIST_FIRST(&scb_data->sg_maps); 5568 segs = sg_map->vaddr + offset; 5569 sg_busaddr = sg_map->physaddr + offset; 5570 } else { 5571 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 5572 5573 if (sg_map == NULL) 5574 return; 5575 5576 /* Allocate the next batch of S/G lists */ 5577 if (ahd_dmamem_alloc(ahd, scb_data->sg_dmat, 5578 (void **)&sg_map->vaddr, 5579 BUS_DMA_NOWAIT, &sg_map->dmamap) != 0) { 5580 free(sg_map, M_DEVBUF); 5581 return; 5582 } 5583 5584 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 5585 5586 ahd_dmamap_load(ahd, scb_data->sg_dmat, sg_map->dmamap, 5587 sg_map->vaddr, ahd_sglist_allocsize(ahd), 5588 ahd_dmamap_cb, &sg_map->physaddr, /*flags*/0); 5589 5590 segs = sg_map->vaddr; 5591 sg_busaddr = sg_map->physaddr; 5592 scb_data->sgs_left = 5593 ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd); 5594 #ifdef AHD_DEBUG 5595 if (ahd_debug & AHD_SHOW_MEMORY) 5596 printf("Mapped SG data\n"); 5597 #endif 5598 } 5599 5600 if (scb_data->sense_left != 0) { 5601 int offset; 5602 5603 offset = PAGE_SIZE - (AHD_SENSE_BUFSIZE * scb_data->sense_left); 5604 sense_map = SLIST_FIRST(&scb_data->sense_maps); 5605 sense_data = sense_map->vaddr + offset; 5606 sense_busaddr = sense_map->physaddr + offset; 5607 } else { 5608 sense_map = malloc(sizeof(*sense_map), M_DEVBUF, M_NOWAIT); 5609 5610 if (sense_map == NULL) 5611 return; 5612 5613 /* Allocate the next batch of sense buffers */ 5614 if (ahd_dmamem_alloc(ahd, scb_data->sense_dmat, 5615 (void **)&sense_map->vaddr, 5616 BUS_DMA_NOWAIT, &sense_map->dmamap) != 0) { 5617 free(sense_map, M_DEVBUF); 5618 return; 5619 } 5620 5621 SLIST_INSERT_HEAD(&scb_data->sense_maps, sense_map, links); 5622 5623 ahd_dmamap_load(ahd, scb_data->sense_dmat, sense_map->dmamap, 5624 sense_map->vaddr, PAGE_SIZE, ahd_dmamap_cb, 5625 &sense_map->physaddr, /*flags*/0); 5626 5627 sense_data = sense_map->vaddr; 5628 sense_busaddr = sense_map->physaddr; 5629 scb_data->sense_left = PAGE_SIZE / AHD_SENSE_BUFSIZE; 5630 #ifdef AHD_DEBUG 5631 if (ahd_debug & AHD_SHOW_MEMORY) 5632 printf("Mapped sense data\n"); 5633 #endif 5634 } 5635 5636 newcount = MIN(scb_data->sense_left, scb_data->scbs_left); 5637 newcount = MIN(newcount, scb_data->sgs_left); 5638 newcount = MIN(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs)); 5639 scb_data->sense_left -= newcount; 5640 scb_data->scbs_left -= newcount; 5641 scb_data->sgs_left -= newcount; 5642 for (i = 0; i < newcount; i++) { 5643 u_int col_tag; 5644 5645 struct scb_platform_data *pdata; 5646 #ifndef __linux__ 5647 int error; 5648 #endif 5649 next_scb = (struct scb *)malloc(sizeof(*next_scb), 5650 M_DEVBUF, M_NOWAIT); 5651 if (next_scb == NULL) 5652 break; 5653 5654 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), 5655 M_DEVBUF, M_NOWAIT); 5656 if (pdata == NULL) { 5657 free(next_scb, M_DEVBUF); 5658 break; 5659 } 5660 next_scb->platform_data = pdata; 5661 next_scb->hscb_map = hscb_map; 5662 next_scb->sg_map = sg_map; 5663 next_scb->sense_map = sense_map; 5664 next_scb->sg_list = segs; 5665 next_scb->sense_data = sense_data; 5666 next_scb->sense_busaddr = sense_busaddr; 5667 next_scb->hscb = hscb; 5668 hscb->hscb_busaddr = ahd_htole32(hscb_busaddr); 5669 5670 /* 5671 * The sequencer always starts with the second entry. 5672 * The first entry is embedded in the scb. 5673 */ 5674 next_scb->sg_list_busaddr = sg_busaddr; 5675 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 5676 next_scb->sg_list_busaddr 5677 += sizeof(struct ahd_dma64_seg); 5678 else 5679 next_scb->sg_list_busaddr += sizeof(struct ahd_dma_seg); 5680 next_scb->ahd_softc = ahd; 5681 next_scb->flags = SCB_FLAG_NONE; 5682 #ifndef __linux__ 5683 error = ahd_dmamap_create(ahd, ahd->buffer_dmat, /*flags*/0, 5684 &next_scb->dmamap); 5685 if (error != 0) { 5686 free(next_scb, M_DEVBUF); 5687 free(pdata, M_DEVBUF); 5688 break; 5689 } 5690 #endif 5691 next_scb->hscb->tag = ahd_htole16(scb_data->numscbs); 5692 col_tag = scb_data->numscbs ^ 0x100; 5693 next_scb->col_scb = ahd_find_scb_by_tag(ahd, col_tag); 5694 if (next_scb->col_scb != NULL) 5695 next_scb->col_scb->col_scb = next_scb; 5696 ahd_free_scb(ahd, next_scb); 5697 hscb++; 5698 hscb_busaddr += sizeof(*hscb); 5699 segs += ahd_sglist_size(ahd); 5700 sg_busaddr += ahd_sglist_size(ahd); 5701 sense_data += AHD_SENSE_BUFSIZE; 5702 sense_busaddr += AHD_SENSE_BUFSIZE; 5703 scb_data->numscbs++; 5704 } 5705 } 5706 5707 void 5708 ahd_controller_info(struct ahd_softc *ahd, char *buf) 5709 { 5710 const char *speed; 5711 const char *type; 5712 int len; 5713 5714 len = sprintf(buf, "%s: ", ahd_chip_names[ahd->chip & AHD_CHIPID_MASK]); 5715 buf += len; 5716 5717 speed = "Ultra320 "; 5718 if ((ahd->features & AHD_WIDE) != 0) { 5719 type = "Wide "; 5720 } else { 5721 type = "Single "; 5722 } 5723 len = sprintf(buf, "%s%sChannel %c, SCSI Id=%d, ", 5724 speed, type, ahd->channel, ahd->our_id); 5725 buf += len; 5726 5727 sprintf(buf, "%s, %d SCBs", ahd->bus_description, 5728 ahd->scb_data.maxhscbs); 5729 } 5730 5731 static const char *channel_strings[] = { 5732 "Primary Low", 5733 "Primary High", 5734 "Secondary Low", 5735 "Secondary High" 5736 }; 5737 5738 static const char *termstat_strings[] = { 5739 "Terminated Correctly", 5740 "Over Terminated", 5741 "Under Terminated", 5742 "Not Configured" 5743 }; 5744 5745 /* 5746 * Start the board, ready for normal operation 5747 */ 5748 int 5749 ahd_init(struct ahd_softc *ahd) 5750 { 5751 uint8_t *base_vaddr; 5752 uint8_t *next_vaddr; 5753 bus_addr_t next_baddr; 5754 size_t driver_data_size; 5755 int i; 5756 int error; 5757 u_int warn_user; 5758 uint8_t current_sensing; 5759 uint8_t fstat; 5760 5761 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 5762 5763 ahd->stack_size = ahd_probe_stack_size(ahd); 5764 ahd->saved_stack = malloc(ahd->stack_size * sizeof(uint16_t), 5765 M_DEVBUF, M_NOWAIT); 5766 if (ahd->saved_stack == NULL) 5767 return (ENOMEM); 5768 5769 /* 5770 * Verify that the compiler hasn't over-agressively 5771 * padded important structures. 5772 */ 5773 if (sizeof(struct hardware_scb) != 64) 5774 panic("Hardware SCB size is incorrect"); 5775 5776 #ifdef AHD_DEBUG 5777 if ((ahd_debug & AHD_DEBUG_SEQUENCER) != 0) 5778 ahd->flags |= AHD_SEQUENCER_DEBUG; 5779 #endif 5780 5781 /* 5782 * Default to allowing initiator operations. 5783 */ 5784 ahd->flags |= AHD_INITIATORROLE; 5785 5786 /* 5787 * Only allow target mode features if this unit has them enabled. 5788 */ 5789 if ((AHD_TMODE_ENABLE & (0x1 << ahd->unit)) == 0) 5790 ahd->features &= ~AHD_TARGETMODE; 5791 5792 #ifndef __linux__ 5793 /* DMA tag for mapping buffers into device visible space. */ 5794 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1, 5795 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 5796 /*lowaddr*/BUS_SPACE_MAXADDR, 5797 /*highaddr*/BUS_SPACE_MAXADDR, 5798 /*filter*/NULL, /*filterarg*/NULL, 5799 /*maxsize*/(AHD_NSEG - 1) * PAGE_SIZE, 5800 /*nsegments*/AHD_NSEG, 5801 /*maxsegsz*/AHD_MAXTRANSFER_SIZE, 5802 /*flags*/BUS_DMA_ALLOCNOW, 5803 &ahd->buffer_dmat) != 0) { 5804 return (ENOMEM); 5805 } 5806 #endif 5807 5808 ahd->init_level++; 5809 5810 /* 5811 * DMA tag for our command fifos and other data in system memory 5812 * the card's sequencer must be able to access. For initiator 5813 * roles, we need to allocate space for the qoutfifo. When providing 5814 * for the target mode role, we must additionally provide space for 5815 * the incoming target command fifo. 5816 */ 5817 driver_data_size = AHD_SCB_MAX * sizeof(uint16_t) 5818 + sizeof(struct hardware_scb); 5819 if ((ahd->features & AHD_TARGETMODE) != 0) 5820 driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd); 5821 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) 5822 driver_data_size += PKT_OVERRUN_BUFSIZE; 5823 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1, 5824 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 5825 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 5826 /*highaddr*/BUS_SPACE_MAXADDR, 5827 /*filter*/NULL, /*filterarg*/NULL, 5828 driver_data_size, 5829 /*nsegments*/1, 5830 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 5831 /*flags*/0, &ahd->shared_data_dmat) != 0) { 5832 return (ENOMEM); 5833 } 5834 5835 ahd->init_level++; 5836 5837 /* Allocation of driver data */ 5838 if (ahd_dmamem_alloc(ahd, ahd->shared_data_dmat, 5839 (void **)&base_vaddr, 5840 BUS_DMA_NOWAIT, &ahd->shared_data_dmamap) != 0) { 5841 return (ENOMEM); 5842 } 5843 5844 ahd->init_level++; 5845 5846 /* And permanently map it in */ 5847 ahd_dmamap_load(ahd, ahd->shared_data_dmat, ahd->shared_data_dmamap, 5848 base_vaddr, driver_data_size, ahd_dmamap_cb, 5849 &ahd->shared_data_busaddr, /*flags*/0); 5850 ahd->qoutfifo = (uint16_t *)base_vaddr; 5851 next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE]; 5852 next_baddr = ahd->shared_data_busaddr + AHD_QOUT_SIZE*sizeof(uint16_t); 5853 if ((ahd->features & AHD_TARGETMODE) != 0) { 5854 ahd->targetcmds = (struct target_cmd *)next_vaddr; 5855 next_vaddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); 5856 next_baddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); 5857 } 5858 5859 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) { 5860 ahd->overrun_buf = next_vaddr; 5861 next_vaddr += PKT_OVERRUN_BUFSIZE; 5862 next_baddr += PKT_OVERRUN_BUFSIZE; 5863 } 5864 5865 /* 5866 * We need one SCB to serve as the "next SCB". Since the 5867 * tag identifier in this SCB will never be used, there is 5868 * no point in using a valid HSCB tag from an SCB pulled from 5869 * the standard free pool. So, we allocate this "sentinel" 5870 * specially from the DMA safe memory chunk used for the QOUTFIFO. 5871 */ 5872 ahd->next_queued_hscb = (struct hardware_scb *)next_vaddr; 5873 ahd->next_queued_hscb->hscb_busaddr = next_baddr; 5874 5875 ahd->init_level++; 5876 5877 /* Allocate SCB data now that buffer_dmat is initialized */ 5878 if (ahd_init_scbdata(ahd) != 0) 5879 return (ENOMEM); 5880 5881 if ((ahd->flags & AHD_INITIATORROLE) == 0) 5882 ahd->flags &= ~AHD_RESET_BUS_A; 5883 5884 /* 5885 * Before committing these settings to the chip, give 5886 * the OSM one last chance to modify our configuration. 5887 */ 5888 ahd_platform_init(ahd); 5889 5890 /* Bring up the chip. */ 5891 ahd_chip_init(ahd); 5892 5893 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 5894 5895 if ((ahd->flags & AHD_CURRENT_SENSING) == 0) 5896 goto init_done; 5897 5898 /* 5899 * Verify termination based on current draw and 5900 * warn user if the bus is over/under terminated. 5901 */ 5902 error = ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 5903 CURSENSE_ENB); 5904 if (error != 0) { 5905 printf("%s: current sensing timeout 1\n", ahd_name(ahd)); 5906 goto init_done; 5907 } 5908 for (i = 20, fstat = FLX_FSTAT_BUSY; 5909 (fstat & FLX_FSTAT_BUSY) != 0 && i; i--) { 5910 error = ahd_read_flexport(ahd, FLXADDR_FLEXSTAT, &fstat); 5911 if (error != 0) { 5912 printf("%s: current sensing timeout 2\n", 5913 ahd_name(ahd)); 5914 goto init_done; 5915 } 5916 } 5917 if (i == 0) { 5918 printf("%s: Timedout during current-sensing test\n", 5919 ahd_name(ahd)); 5920 goto init_done; 5921 } 5922 5923 /* Latch Current Sensing status. */ 5924 error = ahd_read_flexport(ahd, FLXADDR_CURRENT_STAT, ¤t_sensing); 5925 if (error != 0) { 5926 printf("%s: current sensing timeout 3\n", ahd_name(ahd)); 5927 goto init_done; 5928 } 5929 5930 /* Diable current sensing. */ 5931 ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 5932 5933 #ifdef AHD_DEBUG 5934 if ((ahd_debug & AHD_SHOW_TERMCTL) != 0) { 5935 printf("%s: current_sensing == 0x%x\n", 5936 ahd_name(ahd), current_sensing); 5937 } 5938 #endif 5939 warn_user = 0; 5940 for (i = 0; i < 4; i++, current_sensing >>= FLX_CSTAT_SHIFT) { 5941 u_int term_stat; 5942 5943 term_stat = (current_sensing & FLX_CSTAT_MASK); 5944 switch (term_stat) { 5945 case FLX_CSTAT_OVER: 5946 case FLX_CSTAT_UNDER: 5947 warn_user++; 5948 case FLX_CSTAT_INVALID: 5949 case FLX_CSTAT_OKAY: 5950 if (warn_user == 0 && bootverbose == 0) 5951 break; 5952 printf("%s: %s Channel %s\n", ahd_name(ahd), 5953 channel_strings[i], termstat_strings[term_stat]); 5954 break; 5955 } 5956 } 5957 if (warn_user) { 5958 printf("%s: WARNING. Termination is not configured correctly.\n" 5959 "%s: WARNING. SCSI bus operations may FAIL.\n", 5960 ahd_name(ahd), ahd_name(ahd)); 5961 } 5962 init_done: 5963 ahd_restart(ahd); 5964 ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US, 5965 ahd_stat_timer, ahd); 5966 return (0); 5967 } 5968 5969 /* 5970 * (Re)initialize chip state after a chip reset. 5971 */ 5972 static void 5973 ahd_chip_init(struct ahd_softc *ahd) 5974 { 5975 uint32_t busaddr; 5976 u_int sxfrctl1; 5977 u_int scsiseq_template; 5978 u_int wait; 5979 u_int i; 5980 u_int target; 5981 5982 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5983 /* 5984 * Take the LED out of diagnostic mode 5985 */ 5986 ahd_outb(ahd, SBLKCTL, ahd_inb(ahd, SBLKCTL) & ~(DIAGLEDEN|DIAGLEDON)); 5987 5988 /* 5989 * Return HS_MAILBOX to its default value. 5990 */ 5991 ahd->hs_mailbox = 0; 5992 ahd_outb(ahd, HS_MAILBOX, 0); 5993 5994 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */ 5995 ahd_outb(ahd, IOWNID, ahd->our_id); 5996 ahd_outb(ahd, TOWNID, ahd->our_id); 5997 sxfrctl1 = (ahd->flags & AHD_TERM_ENB_A) != 0 ? STPWEN : 0; 5998 sxfrctl1 |= (ahd->flags & AHD_SPCHK_ENB_A) != 0 ? ENSPCHK : 0; 5999 if ((ahd->bugs & AHD_LONG_SETIMO_BUG) 6000 && (ahd->seltime != STIMESEL_MIN)) { 6001 /* 6002 * The selection timer duration is twice as long 6003 * as it should be. Halve it by adding "1" to 6004 * the user specified setting. 6005 */ 6006 sxfrctl1 |= ahd->seltime + STIMESEL_BUG_ADJ; 6007 } else { 6008 sxfrctl1 |= ahd->seltime; 6009 } 6010 6011 ahd_outb(ahd, SXFRCTL0, DFON); 6012 ahd_outb(ahd, SXFRCTL1, sxfrctl1|ahd->seltime|ENSTIMER|ACTNEGEN); 6013 ahd_outb(ahd, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 6014 6015 /* 6016 * Now that termination is set, wait for up 6017 * to 500ms for our transceivers to settle. If 6018 * the adapter does not have a cable attached, 6019 * the tranceivers may never settle, so don't 6020 * complain if we fail here. 6021 */ 6022 for (wait = 10000; 6023 (ahd_inb(ahd, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 6024 wait--) 6025 ahd_delay(100); 6026 6027 /* Clear any false bus resets due to the transceivers settling */ 6028 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); 6029 ahd_outb(ahd, CLRINT, CLRSCSIINT); 6030 6031 /* Initialize mode specific S/G state. */ 6032 for (i = 0; i < 2; i++) { 6033 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); 6034 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 6035 ahd_outw(ahd, LONGJMP_SCB, SCB_LIST_NULL); 6036 ahd_outb(ahd, SG_STATE, 0); 6037 ahd_outb(ahd, CLRSEQINTSRC, 0xFF); 6038 ahd_outb(ahd, SEQIMODE, 6039 ENSAVEPTRS|ENCFG4DATA|ENCFG4ISTAT 6040 |ENCFG4TSTAT|ENCFG4ICMD|ENCFG4TCMD); 6041 } 6042 6043 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 6044 ahd_outb(ahd, DSCOMMAND0, ahd_inb(ahd, DSCOMMAND0)|MPARCKEN|CACHETHEN); 6045 ahd_outb(ahd, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 6046 ahd_outb(ahd, SIMODE0, ENIOERR|ENOVERRUN); 6047 ahd_outb(ahd, SIMODE3, ENNTRAMPERR|ENOSRAMPERR); 6048 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) { 6049 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|AUTO_MSGOUT_DE); 6050 } else { 6051 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|BUSFREEREV|AUTO_MSGOUT_DE); 6052 } 6053 ahd_outb(ahd, SCSCHKN, CURRFIFODEF|WIDERESEN); 6054 if ((ahd->chip & AHD_BUS_MASK) == AHD_PCIX) 6055 /* 6056 * Do not issue a target abort when a split completion 6057 * error occurs. Let our PCIX interrupt handler deal 6058 * with it instead. H2A4 Razor #625 6059 */ 6060 ahd_outb(ahd, PCIXCTL, ahd_inb(ahd, PCIXCTL) | SPLTSTADIS); 6061 6062 if ((ahd->bugs & AHD_LQOOVERRUN_BUG) != 0) 6063 ahd_outb(ahd, LQOSCSCTL, LQONOCHKOVER); 6064 6065 /* 6066 * Tweak IOCELL settings. 6067 */ 6068 if ((ahd->flags & AHD_HP_BOARD) != 0) { 6069 for (i = 0; i < NUMDSPS; i++) { 6070 ahd_outb(ahd, DSPSELECT, i); 6071 ahd_outb(ahd, WRTBIASCTL, WRTBIASCTL_HP_DEFAULT); 6072 } 6073 #ifdef AHD_DEBUG 6074 if ((ahd_debug & AHD_SHOW_MISC) != 0) 6075 printf("%s: WRTBIASCTL now 0x%x\n", ahd_name(ahd), 6076 WRTBIASCTL_HP_DEFAULT); 6077 #endif 6078 } 6079 ahd_setup_iocell_workaround(ahd); 6080 6081 /* 6082 * Enable LQI Manager interrupts. 6083 */ 6084 ahd_outb(ahd, LQIMODE1, ENLQIPHASE_LQ|ENLQIPHASE_NLQ|ENLIQABORT 6085 | ENLQICRCI_LQ|ENLQICRCI_NLQ|ENLQIBADLQI 6086 | ENLQIOVERI_LQ|ENLQIOVERI_NLQ); 6087 ahd_outb(ahd, LQOMODE0, ENLQOATNLQ|ENLQOATNPKT|ENLQOTCRC); 6088 /* 6089 * An interrupt from LQOBUSFREE is made redundant by the 6090 * BUSFREE interrupt. We choose to have the sequencer catch 6091 * LQOPHCHGINPKT errors manually for the command phase at the 6092 * start of a packetized selection case. 6093 ahd_outb(ahd, LQOMODE1, ENLQOBUSFREE|ENLQOPHACHGINPKT); 6094 */ 6095 ahd_outb(ahd, LQOMODE1, 0); 6096 6097 /* 6098 * Setup sequencer interrupt handlers. 6099 */ 6100 ahd_outw(ahd, INTVEC1_ADDR, ahd_resolve_seqaddr(ahd, LABEL_seq_isr)); 6101 ahd_outw(ahd, INTVEC2_ADDR, ahd_resolve_seqaddr(ahd, LABEL_timer_isr)); 6102 6103 /* 6104 * Setup SCB Offset registers. 6105 */ 6106 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { 6107 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, 6108 pkt_long_lun)); 6109 } else { 6110 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, lun)); 6111 } 6112 ahd_outb(ahd, CMDLENPTR, offsetof(struct hardware_scb, cdb_len)); 6113 ahd_outb(ahd, ATTRPTR, offsetof(struct hardware_scb, task_attribute)); 6114 ahd_outb(ahd, FLAGPTR, offsetof(struct hardware_scb, task_management)); 6115 ahd_outb(ahd, CMDPTR, offsetof(struct hardware_scb, 6116 shared_data.idata.cdb)); 6117 ahd_outb(ahd, QNEXTPTR, 6118 offsetof(struct hardware_scb, next_hscb_busaddr)); 6119 ahd_outb(ahd, ABRTBITPTR, MK_MESSAGE_BIT_OFFSET); 6120 ahd_outb(ahd, ABRTBYTEPTR, offsetof(struct hardware_scb, control)); 6121 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { 6122 ahd_outb(ahd, LUNLEN, 6123 sizeof(ahd->next_queued_hscb->pkt_long_lun) - 1); 6124 } else { 6125 ahd_outb(ahd, LUNLEN, sizeof(ahd->next_queued_hscb->lun) - 1); 6126 } 6127 ahd_outb(ahd, CDBLIMIT, SCB_CDB_LEN_PTR - 1); 6128 ahd_outb(ahd, MAXCMD, 0xFF); 6129 ahd_outb(ahd, SCBAUTOPTR, 6130 AUSCBPTR_EN | offsetof(struct hardware_scb, tag)); 6131 6132 /* We haven't been enabled for target mode yet. */ 6133 ahd_outb(ahd, MULTARGID, 0); 6134 ahd_outb(ahd, MULTARGID + 1, 0); 6135 6136 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6137 /* Initialize the negotiation table. */ 6138 if ((ahd->features & AHD_NEW_IOCELL_OPTS) == 0) { 6139 /* 6140 * Clear the spare bytes in the neg table to avoid 6141 * spurious parity errors. 6142 */ 6143 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6144 ahd_outb(ahd, NEGOADDR, target); 6145 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PER_DEV0); 6146 for (i = 0; i < AHD_NUM_PER_DEV_ANNEXCOLS; i++) 6147 ahd_outb(ahd, ANNEXDAT, 0); 6148 } 6149 } 6150 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6151 struct ahd_devinfo devinfo; 6152 struct ahd_initiator_tinfo *tinfo; 6153 struct ahd_tmode_tstate *tstate; 6154 6155 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6156 target, &tstate); 6157 ahd_compile_devinfo(&devinfo, ahd->our_id, 6158 target, CAM_LUN_WILDCARD, 6159 'A', ROLE_INITIATOR); 6160 ahd_update_neg_table(ahd, &devinfo, &tinfo->curr); 6161 } 6162 6163 ahd_outb(ahd, CLRSINT3, NTRAMPERR|OSRAMPERR); 6164 ahd_outb(ahd, CLRINT, CLRSCSIINT); 6165 6166 /* 6167 * Always enable abort on incoming L_Qs if this feature is 6168 * supported. We use this to catch invalid SCB references. 6169 */ 6170 if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0) 6171 ahd_outb(ahd, LQCTL1, ABORTPENDING); 6172 else 6173 ahd_outb(ahd, LQCTL1, 0); 6174 6175 /* All of our queues are empty */ 6176 ahd->qoutfifonext = 0; 6177 ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID_LE; 6178 ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID >> 8); 6179 for (i = 0; i < AHD_QOUT_SIZE; i++) 6180 ahd->qoutfifo[i] = 0; 6181 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD); 6182 6183 ahd->qinfifonext = 0; 6184 for (i = 0; i < AHD_QIN_SIZE; i++) 6185 ahd->qinfifo[i] = SCB_LIST_NULL; 6186 6187 if ((ahd->features & AHD_TARGETMODE) != 0) { 6188 /* All target command blocks start out invalid. */ 6189 for (i = 0; i < AHD_TMODE_CMDS; i++) 6190 ahd->targetcmds[i].cmd_valid = 0; 6191 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_PREREAD); 6192 ahd->tqinfifonext = 1; 6193 ahd_outb(ahd, KERNEL_TQINPOS, ahd->tqinfifonext - 1); 6194 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); 6195 } 6196 6197 /* Initialize Scratch Ram. */ 6198 ahd_outb(ahd, SEQ_FLAGS, 0); 6199 ahd_outb(ahd, SEQ_FLAGS2, 0); 6200 6201 /* We don't have any waiting selections */ 6202 ahd_outw(ahd, WAITING_TID_HEAD, SCB_LIST_NULL); 6203 ahd_outw(ahd, WAITING_TID_TAIL, SCB_LIST_NULL); 6204 for (i = 0; i < AHD_NUM_TARGETS; i++) 6205 ahd_outw(ahd, WAITING_SCB_TAILS + (2 * i), SCB_LIST_NULL); 6206 6207 /* 6208 * Nobody is waiting to be DMAed into the QOUTFIFO. 6209 */ 6210 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); 6211 ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL); 6212 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); 6213 6214 /* 6215 * The Freeze Count is 0. 6216 */ 6217 ahd_outw(ahd, QFREEZE_COUNT, 0); 6218 6219 /* 6220 * Tell the sequencer where it can find our arrays in memory. 6221 */ 6222 busaddr = ahd->shared_data_busaddr; 6223 ahd_outb(ahd, SHARED_DATA_ADDR, busaddr & 0xFF); 6224 ahd_outb(ahd, SHARED_DATA_ADDR + 1, (busaddr >> 8) & 0xFF); 6225 ahd_outb(ahd, SHARED_DATA_ADDR + 2, (busaddr >> 16) & 0xFF); 6226 ahd_outb(ahd, SHARED_DATA_ADDR + 3, (busaddr >> 24) & 0xFF); 6227 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR, busaddr & 0xFF); 6228 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 1, (busaddr >> 8) & 0xFF); 6229 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 2, (busaddr >> 16) & 0xFF); 6230 ahd_outb(ahd, QOUTFIFO_NEXT_ADDR + 3, (busaddr >> 24) & 0xFF); 6231 6232 /* 6233 * Setup the allowed SCSI Sequences based on operational mode. 6234 * If we are a target, we'll enable select in operations once 6235 * we've had a lun enabled. 6236 */ 6237 scsiseq_template = ENAUTOATNP; 6238 if ((ahd->flags & AHD_INITIATORROLE) != 0) 6239 scsiseq_template |= ENRSELI; 6240 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq_template); 6241 6242 /* There are no busy SCBs yet. */ 6243 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6244 int lun; 6245 6246 for (lun = 0; lun < AHD_NUM_LUNS_NONPKT; lun++) 6247 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(target, 'A', lun)); 6248 } 6249 6250 /* 6251 * Initialize the group code to command length table. 6252 * Vendor Unique codes are set to 0 so we only capture 6253 * the first byte of the cdb. These can be overridden 6254 * when target mode is enabled. 6255 */ 6256 ahd_outb(ahd, CMDSIZE_TABLE, 5); 6257 ahd_outb(ahd, CMDSIZE_TABLE + 1, 9); 6258 ahd_outb(ahd, CMDSIZE_TABLE + 2, 9); 6259 ahd_outb(ahd, CMDSIZE_TABLE + 3, 0); 6260 ahd_outb(ahd, CMDSIZE_TABLE + 4, 15); 6261 ahd_outb(ahd, CMDSIZE_TABLE + 5, 11); 6262 ahd_outb(ahd, CMDSIZE_TABLE + 6, 0); 6263 ahd_outb(ahd, CMDSIZE_TABLE + 7, 0); 6264 6265 /* Tell the sequencer of our initial queue positions */ 6266 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6267 ahd_outb(ahd, QOFF_CTLSTA, SCB_QSIZE_512); 6268 ahd->qinfifonext = 0; 6269 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 6270 ahd_set_hescb_qoff(ahd, 0); 6271 ahd_set_snscb_qoff(ahd, 0); 6272 ahd_set_sescb_qoff(ahd, 0); 6273 ahd_set_sdscb_qoff(ahd, 0); 6274 6275 /* 6276 * Tell the sequencer which SCB will be the next one it receives. 6277 */ 6278 busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr); 6279 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); 6280 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); 6281 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); 6282 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); 6283 6284 /* 6285 * Default to coalessing disabled. 6286 */ 6287 ahd_outw(ahd, INT_COALESSING_CMDCOUNT, 0); 6288 ahd_outw(ahd, CMDS_PENDING, 0); 6289 ahd_update_coalessing_values(ahd, ahd->int_coalessing_timer, 6290 ahd->int_coalessing_maxcmds, 6291 ahd->int_coalessing_mincmds); 6292 ahd_enable_coalessing(ahd, FALSE); 6293 6294 ahd_loadseq(ahd); 6295 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6296 } 6297 6298 /* 6299 * Setup default device and controller settings. 6300 * This should only be called if our probe has 6301 * determined that no configuration data is available. 6302 */ 6303 int 6304 ahd_default_config(struct ahd_softc *ahd) 6305 { 6306 int targ; 6307 6308 ahd->our_id = 7; 6309 6310 /* 6311 * Allocate a tstate to house information for our 6312 * initiator presence on the bus as well as the user 6313 * data for any target mode initiator. 6314 */ 6315 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { 6316 printf("%s: unable to allocate ahd_tmode_tstate. " 6317 "Failing attach\n", ahd_name(ahd)); 6318 return (ENOMEM); 6319 } 6320 6321 for (targ = 0; targ < AHD_NUM_TARGETS; targ++) { 6322 struct ahd_devinfo devinfo; 6323 struct ahd_initiator_tinfo *tinfo; 6324 struct ahd_tmode_tstate *tstate; 6325 uint16_t target_mask; 6326 6327 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6328 targ, &tstate); 6329 /* 6330 * We support SPC2 and SPI4. 6331 */ 6332 tinfo->user.protocol_version = 4; 6333 tinfo->user.transport_version = 4; 6334 6335 target_mask = 0x01 << targ; 6336 ahd->user_discenable |= target_mask; 6337 tstate->discenable |= target_mask; 6338 ahd->user_tagenable |= target_mask; 6339 #ifdef AHD_FORCE_160 6340 tinfo->user.period = AHD_SYNCRATE_DT; 6341 #else 6342 tinfo->user.period = AHD_SYNCRATE_160; 6343 #endif 6344 tinfo->user.offset= ~0; 6345 tinfo->user.ppr_options = MSG_EXT_PPR_RD_STRM 6346 | MSG_EXT_PPR_WR_FLOW 6347 | MSG_EXT_PPR_HOLD_MCS 6348 | MSG_EXT_PPR_IU_REQ 6349 | MSG_EXT_PPR_QAS_REQ 6350 | MSG_EXT_PPR_DT_REQ; 6351 if ((ahd->features & AHD_RTI) != 0) 6352 tinfo->user.ppr_options |= MSG_EXT_PPR_RTI; 6353 6354 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 6355 6356 /* 6357 * Start out Async/Narrow/Untagged and with 6358 * conservative protocol support. 6359 */ 6360 tinfo->goal.protocol_version = 2; 6361 tinfo->goal.transport_version = 2; 6362 tinfo->curr.protocol_version = 2; 6363 tinfo->curr.transport_version = 2; 6364 ahd_compile_devinfo(&devinfo, ahd->our_id, 6365 targ, CAM_LUN_WILDCARD, 6366 'A', ROLE_INITIATOR); 6367 tstate->tagenable &= ~target_mask; 6368 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6369 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); 6370 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, 6371 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, 6372 /*paused*/TRUE); 6373 } 6374 return (0); 6375 } 6376 6377 /* 6378 * Parse device configuration information. 6379 */ 6380 int 6381 ahd_parse_cfgdata(struct ahd_softc *ahd, struct seeprom_config *sc) 6382 { 6383 int targ; 6384 int max_targ; 6385 6386 max_targ = sc->max_targets & CFMAXTARG; 6387 ahd->our_id = sc->brtime_id & CFSCSIID; 6388 6389 /* 6390 * Allocate a tstate to house information for our 6391 * initiator presence on the bus as well as the user 6392 * data for any target mode initiator. 6393 */ 6394 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { 6395 printf("%s: unable to allocate ahd_tmode_tstate. " 6396 "Failing attach\n", ahd_name(ahd)); 6397 return (ENOMEM); 6398 } 6399 6400 for (targ = 0; targ < max_targ; targ++) { 6401 struct ahd_devinfo devinfo; 6402 struct ahd_initiator_tinfo *tinfo; 6403 struct ahd_transinfo *user_tinfo; 6404 struct ahd_tmode_tstate *tstate; 6405 uint16_t target_mask; 6406 6407 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6408 targ, &tstate); 6409 user_tinfo = &tinfo->user; 6410 6411 /* 6412 * We support SPC2 and SPI4. 6413 */ 6414 tinfo->user.protocol_version = 4; 6415 tinfo->user.transport_version = 4; 6416 6417 target_mask = 0x01 << targ; 6418 ahd->user_discenable &= ~target_mask; 6419 tstate->discenable &= ~target_mask; 6420 ahd->user_tagenable &= ~target_mask; 6421 if (sc->device_flags[targ] & CFDISC) { 6422 tstate->discenable |= target_mask; 6423 ahd->user_discenable |= target_mask; 6424 ahd->user_tagenable |= target_mask; 6425 } else { 6426 /* 6427 * Cannot be packetized without disconnection. 6428 */ 6429 sc->device_flags[targ] &= ~CFPACKETIZED; 6430 } 6431 6432 user_tinfo->ppr_options = 0; 6433 user_tinfo->period = (sc->device_flags[targ] & CFXFER); 6434 if (user_tinfo->period < CFXFER_ASYNC) { 6435 if (user_tinfo->period <= AHD_PERIOD_10MHz) 6436 user_tinfo->ppr_options |= MSG_EXT_PPR_DT_REQ; 6437 user_tinfo->offset = MAX_OFFSET; 6438 } else { 6439 user_tinfo->offset = 0; 6440 user_tinfo->period = AHD_ASYNC_XFER_PERIOD; 6441 } 6442 #ifdef AHD_FORCE_160 6443 if (user_tinfo->period <= AHD_SYNCRATE_160) 6444 user_tinfo->period = AHD_SYNCRATE_DT; 6445 #endif 6446 6447 if ((sc->device_flags[targ] & CFPACKETIZED) != 0) { 6448 user_tinfo->ppr_options |= MSG_EXT_PPR_RD_STRM 6449 | MSG_EXT_PPR_WR_FLOW 6450 | MSG_EXT_PPR_HOLD_MCS 6451 | MSG_EXT_PPR_IU_REQ; 6452 if ((ahd->features & AHD_RTI) != 0) 6453 user_tinfo->ppr_options |= MSG_EXT_PPR_RTI; 6454 } 6455 6456 if ((sc->device_flags[targ] & CFQAS) != 0) 6457 user_tinfo->ppr_options |= MSG_EXT_PPR_QAS_REQ; 6458 6459 if ((sc->device_flags[targ] & CFWIDEB) != 0) 6460 user_tinfo->width = MSG_EXT_WDTR_BUS_16_BIT; 6461 else 6462 user_tinfo->width = MSG_EXT_WDTR_BUS_8_BIT; 6463 #ifdef AHD_DEBUG 6464 if ((ahd_debug & AHD_SHOW_MISC) != 0) 6465 printf("(%d): %x:%x:%x:%x\n", targ, user_tinfo->width, 6466 user_tinfo->period, user_tinfo->offset, 6467 user_tinfo->ppr_options); 6468 #endif 6469 /* 6470 * Start out Async/Narrow/Untagged and with 6471 * conservative protocol support. 6472 */ 6473 tstate->tagenable &= ~target_mask; 6474 tinfo->goal.protocol_version = 2; 6475 tinfo->goal.transport_version = 2; 6476 tinfo->curr.protocol_version = 2; 6477 tinfo->curr.transport_version = 2; 6478 ahd_compile_devinfo(&devinfo, ahd->our_id, 6479 targ, CAM_LUN_WILDCARD, 6480 'A', ROLE_INITIATOR); 6481 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6482 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); 6483 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, 6484 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, 6485 /*paused*/TRUE); 6486 } 6487 6488 ahd->flags &= ~AHD_SPCHK_ENB_A; 6489 if (sc->bios_control & CFSPARITY) 6490 ahd->flags |= AHD_SPCHK_ENB_A; 6491 6492 ahd->flags &= ~AHD_RESET_BUS_A; 6493 if (sc->bios_control & CFRESETB) 6494 ahd->flags |= AHD_RESET_BUS_A; 6495 6496 ahd->flags &= ~AHD_EXTENDED_TRANS_A; 6497 if (sc->bios_control & CFEXTEND) 6498 ahd->flags |= AHD_EXTENDED_TRANS_A; 6499 6500 ahd->flags &= ~AHD_BIOS_ENABLED; 6501 if ((sc->bios_control & CFBIOSSTATE) == CFBS_ENABLED) 6502 ahd->flags |= AHD_BIOS_ENABLED; 6503 6504 ahd->flags &= ~AHD_STPWLEVEL_A; 6505 if ((sc->adapter_control & CFSTPWLEVEL) != 0) 6506 ahd->flags |= AHD_STPWLEVEL_A; 6507 6508 return (0); 6509 } 6510 6511 void 6512 ahd_intr_enable(struct ahd_softc *ahd, int enable) 6513 { 6514 u_int hcntrl; 6515 6516 hcntrl = ahd_inb(ahd, HCNTRL); 6517 hcntrl &= ~INTEN; 6518 ahd->pause &= ~INTEN; 6519 ahd->unpause &= ~INTEN; 6520 if (enable) { 6521 hcntrl |= INTEN; 6522 ahd->pause |= INTEN; 6523 ahd->unpause |= INTEN; 6524 } 6525 ahd_outb(ahd, HCNTRL, hcntrl); 6526 } 6527 6528 void 6529 ahd_update_coalessing_values(struct ahd_softc *ahd, u_int timer, u_int maxcmds, 6530 u_int mincmds) 6531 { 6532 if (timer > AHD_TIMER_MAX_US) 6533 timer = AHD_TIMER_MAX_US; 6534 ahd->int_coalessing_timer = timer; 6535 6536 if (maxcmds > AHD_INT_COALESSING_MAXCMDS_MAX) 6537 maxcmds = AHD_INT_COALESSING_MAXCMDS_MAX; 6538 if (mincmds > AHD_INT_COALESSING_MINCMDS_MAX) 6539 mincmds = AHD_INT_COALESSING_MINCMDS_MAX; 6540 ahd->int_coalessing_maxcmds = maxcmds; 6541 ahd_outw(ahd, INT_COALESSING_TIMER, timer / AHD_TIMER_US_PER_TICK); 6542 ahd_outb(ahd, INT_COALESSING_MAXCMDS, -maxcmds); 6543 ahd_outb(ahd, INT_COALESSING_MINCMDS, -mincmds); 6544 } 6545 6546 void 6547 ahd_enable_coalessing(struct ahd_softc *ahd, int enable) 6548 { 6549 6550 ahd->hs_mailbox &= ~ENINT_COALESS; 6551 if (enable) 6552 ahd->hs_mailbox |= ENINT_COALESS; 6553 ahd_outb(ahd, HS_MAILBOX, ahd->hs_mailbox); 6554 ahd_flush_device_writes(ahd); 6555 ahd_run_qoutfifo(ahd); 6556 } 6557 6558 /* 6559 * Ensure that the card is paused in a location 6560 * outside of all critical sections and that all 6561 * pending work is completed prior to returning. 6562 * This routine should only be called from outside 6563 * an interrupt context. 6564 */ 6565 void 6566 ahd_pause_and_flushwork(struct ahd_softc *ahd) 6567 { 6568 u_int intstat; 6569 u_int maxloops; 6570 int paused; 6571 6572 maxloops = 1000; 6573 ahd->flags |= AHD_ALL_INTERRUPTS; 6574 intstat = 0; 6575 paused = FALSE; 6576 do { 6577 struct scb *waiting_scb; 6578 6579 if (paused) 6580 ahd_unpause(ahd); 6581 ahd_intr(ahd); 6582 ahd_pause(ahd); 6583 paused = TRUE; 6584 ahd_clear_critical_section(ahd); 6585 if ((ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0) 6586 ahd_outb(ahd, SCSISEQ0, 6587 ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 6588 /* 6589 * In the non-packetized case, the sequencer (for Rev A), 6590 * relies on ENSELO remaining set after SELDO. The hardware 6591 * auto-clears ENSELO in the packetized case. 6592 */ 6593 waiting_scb = ahd_lookup_scb(ahd, 6594 ahd_inw(ahd, WAITING_TID_HEAD)); 6595 if (waiting_scb != NULL 6596 && (waiting_scb->flags & SCB_PACKETIZED) == 0 6597 && (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0) 6598 ahd_outb(ahd, SCSISEQ0, 6599 ahd_inb(ahd, SCSISEQ0) | ENSELO); 6600 6601 if (intstat == 0xFF && (ahd->features & AHD_REMOVABLE) != 0) 6602 break; 6603 } while (--maxloops 6604 && (((intstat = ahd_inb(ahd, INTSTAT)) & INT_PEND) != 0 6605 || (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)))); 6606 if (maxloops == 0) { 6607 printf("Infinite interrupt loop, INTSTAT = %x", 6608 ahd_inb(ahd, INTSTAT)); 6609 } 6610 6611 ahd_flush_qoutfifo(ahd); 6612 6613 ahd_platform_flushwork(ahd); 6614 ahd->flags &= ~AHD_ALL_INTERRUPTS; 6615 } 6616 6617 int 6618 ahd_suspend(struct ahd_softc *ahd) 6619 { 6620 #if 0 6621 uint8_t *ptr; 6622 int i; 6623 6624 ahd_pause_and_flushwork(ahd); 6625 6626 if (LIST_FIRST(&ahd->pending_scbs) != NULL) 6627 return (EBUSY); 6628 6629 #if AHD_TARGET_MODE 6630 /* 6631 * XXX What about ATIOs that have not yet been serviced? 6632 * Perhaps we should just refuse to be suspended if we 6633 * are acting in a target role. 6634 */ 6635 if (ahd->pending_device != NULL) 6636 return (EBUSY); 6637 #endif 6638 6639 /* Save volatile registers */ 6640 ahd->suspend_state.channel[0].scsiseq = ahd_inb(ahd, SCSISEQ0); 6641 ahd->suspend_state.channel[0].sxfrctl0 = ahd_inb(ahd, SXFRCTL0); 6642 ahd->suspend_state.channel[0].sxfrctl1 = ahd_inb(ahd, SXFRCTL1); 6643 ahd->suspend_state.channel[0].simode0 = ahd_inb(ahd, SIMODE0); 6644 ahd->suspend_state.channel[0].simode1 = ahd_inb(ahd, SIMODE1); 6645 ahd->suspend_state.channel[0].seltimer = ahd_inb(ahd, SELTIMER); 6646 ahd->suspend_state.channel[0].seqctl = ahd_inb(ahd, SEQCTL0); 6647 ahd->suspend_state.dscommand0 = ahd_inb(ahd, DSCOMMAND0); 6648 ahd->suspend_state.dspcistatus = ahd_inb(ahd, DSPCISTATUS); 6649 6650 if ((ahd->features & AHD_DT) != 0) { 6651 u_int sfunct; 6652 6653 sfunct = ahd_inb(ahd, SFUNCT) & ~ALT_MODE; 6654 ahd_outb(ahd, SFUNCT, sfunct | ALT_MODE); 6655 ahd->suspend_state.optionmode = ahd_inb(ahd, OPTIONMODE); 6656 ahd_outb(ahd, SFUNCT, sfunct); 6657 ahd->suspend_state.crccontrol1 = ahd_inb(ahd, CRCCONTROL1); 6658 } 6659 6660 if ((ahd->features & AHD_MULTI_FUNC) != 0) 6661 ahd->suspend_state.scbbaddr = ahd_inb(ahd, SCBBADDR); 6662 6663 if ((ahd->features & AHD_ULTRA2) != 0) 6664 ahd->suspend_state.dff_thrsh = ahd_inb(ahd, DFF_THRSH); 6665 6666 ptr = ahd->suspend_state.scratch_ram; 6667 for (i = 0; i < 64; i++) 6668 *ptr++ = ahd_inb(ahd, SRAM_BASE + i); 6669 6670 if ((ahd->features & AHD_MORE_SRAM) != 0) { 6671 for (i = 0; i < 16; i++) 6672 *ptr++ = ahd_inb(ahd, TARG_OFFSET + i); 6673 } 6674 6675 ptr = ahd->suspend_state.btt; 6676 for (i = 0;i < AHD_NUM_TARGETS; i++) { 6677 int j; 6678 6679 for (j = 0;j < AHD_NUM_LUNS_NONPKT; j++) { 6680 u_int tcl; 6681 6682 tcl = BUILD_TCL_RAW(i, 'A', j); 6683 *ptr = ahd_find_busy_tcl(ahd, tcl); 6684 } 6685 } 6686 ahd_shutdown(ahd); 6687 #endif 6688 return (0); 6689 } 6690 6691 int 6692 ahd_resume(struct ahd_softc *ahd) 6693 { 6694 #if 0 6695 uint8_t *ptr; 6696 int i; 6697 6698 ahd_reset(ahd); 6699 6700 ahd_build_free_scb_list(ahd); 6701 6702 /* Restore volatile registers */ 6703 ahd_outb(ahd, SCSISEQ0, ahd->suspend_state.channel[0].scsiseq); 6704 ahd_outb(ahd, SXFRCTL0, ahd->suspend_state.channel[0].sxfrctl0); 6705 ahd_outb(ahd, SXFRCTL1, ahd->suspend_state.channel[0].sxfrctl1); 6706 ahd_outb(ahd, SIMODE0, ahd->suspend_state.channel[0].simode0); 6707 ahd_outb(ahd, SIMODE1, ahd->suspend_state.channel[0].simode1); 6708 ahd_outb(ahd, SELTIMER, ahd->suspend_state.channel[0].seltimer); 6709 ahd_outb(ahd, SEQCTL0, ahd->suspend_state.channel[0].seqctl); 6710 if ((ahd->features & AHD_ULTRA2) != 0) 6711 ahd_outb(ahd, SCSIID_ULTRA2, ahd->our_id); 6712 else 6713 ahd_outb(ahd, SCSIID, ahd->our_id); 6714 6715 ahd_outb(ahd, DSCOMMAND0, ahd->suspend_state.dscommand0); 6716 ahd_outb(ahd, DSPCISTATUS, ahd->suspend_state.dspcistatus); 6717 6718 if ((ahd->features & AHD_DT) != 0) { 6719 u_int sfunct; 6720 6721 sfunct = ahd_inb(ahd, SFUNCT) & ~ALT_MODE; 6722 ahd_outb(ahd, SFUNCT, sfunct | ALT_MODE); 6723 ahd_outb(ahd, OPTIONMODE, ahd->suspend_state.optionmode); 6724 ahd_outb(ahd, SFUNCT, sfunct); 6725 ahd_outb(ahd, CRCCONTROL1, ahd->suspend_state.crccontrol1); 6726 } 6727 6728 if ((ahd->features & AHD_MULTI_FUNC) != 0) 6729 ahd_outb(ahd, SCBBADDR, ahd->suspend_state.scbbaddr); 6730 6731 if ((ahd->features & AHD_ULTRA2) != 0) 6732 ahd_outb(ahd, DFF_THRSH, ahd->suspend_state.dff_thrsh); 6733 6734 ptr = ahd->suspend_state.scratch_ram; 6735 for (i = 0; i < 64; i++) 6736 ahd_outb(ahd, SRAM_BASE + i, *ptr++); 6737 6738 if ((ahd->features & AHD_MORE_SRAM) != 0) { 6739 for (i = 0; i < 16; i++) 6740 ahd_outb(ahd, TARG_OFFSET + i, *ptr++); 6741 } 6742 6743 ptr = ahd->suspend_state.btt; 6744 for (i = 0;i < AHD_NUM_TARGETS; i++) { 6745 int j; 6746 6747 for (j = 0;j < AHD_NUM_LUNS; j++) { 6748 u_int tcl; 6749 6750 tcl = BUILD_TCL(i << 4, j); 6751 ahd_busy_tcl(ahd, tcl, *ptr); 6752 } 6753 } 6754 #endif 6755 return (0); 6756 } 6757 6758 /************************** Busy Target Table *********************************/ 6759 /* 6760 * Set SCBPTR to the SCB that contains the busy 6761 * table entry for TCL. Return the offset into 6762 * the SCB that contains the entry for TCL. 6763 * saved_scbid is dereferenced and set to the 6764 * scbid that should be restored once manipualtion 6765 * of the TCL entry is complete. 6766 */ 6767 static __inline u_int 6768 ahd_index_busy_tcl(struct ahd_softc *ahd, u_int *saved_scbid, u_int tcl) 6769 { 6770 /* 6771 * Index to the SCB that contains the busy entry. 6772 */ 6773 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 6774 *saved_scbid = ahd_get_scbptr(ahd); 6775 ahd_set_scbptr(ahd, TCL_LUN(tcl) 6776 | ((TCL_TARGET_OFFSET(tcl) & 0xC) << 4)); 6777 6778 /* 6779 * And now calculate the SCB offset to the entry. 6780 * Each entry is 2 bytes wide, hence the 6781 * multiplication by 2. 6782 */ 6783 return (((TCL_TARGET_OFFSET(tcl) & 0x3) << 1) + SCB_DISCONNECTED_LISTS); 6784 } 6785 6786 /* 6787 * Return the untagged transaction id for a given target/channel lun. 6788 * Optionally, clear the entry. 6789 */ 6790 u_int 6791 ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl) 6792 { 6793 u_int scbid; 6794 u_int scb_offset; 6795 u_int saved_scbptr; 6796 6797 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); 6798 scbid = ahd_inw_scbram(ahd, scb_offset); 6799 ahd_set_scbptr(ahd, saved_scbptr); 6800 return (scbid); 6801 } 6802 6803 void 6804 ahd_busy_tcl(struct ahd_softc *ahd, u_int tcl, u_int scbid) 6805 { 6806 u_int scb_offset; 6807 u_int saved_scbptr; 6808 6809 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); 6810 ahd_outw(ahd, scb_offset, scbid); 6811 ahd_set_scbptr(ahd, saved_scbptr); 6812 } 6813 6814 /************************** SCB and SCB queue management **********************/ 6815 int 6816 ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, int target, 6817 char channel, int lun, u_int tag, role_t role) 6818 { 6819 int targ = SCB_GET_TARGET(ahd, scb); 6820 char chan = SCB_GET_CHANNEL(ahd, scb); 6821 int slun = SCB_GET_LUN(scb); 6822 int match; 6823 6824 match = ((chan == channel) || (channel == ALL_CHANNELS)); 6825 if (match != 0) 6826 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 6827 if (match != 0) 6828 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 6829 if (match != 0) { 6830 #if AHD_TARGET_MODE 6831 int group; 6832 6833 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 6834 if (role == ROLE_INITIATOR) { 6835 match = (group != XPT_FC_GROUP_TMODE) 6836 && ((tag == SCB_GET_TAG(scb)) 6837 || (tag == SCB_LIST_NULL)); 6838 } else if (role == ROLE_TARGET) { 6839 match = (group == XPT_FC_GROUP_TMODE) 6840 && ((tag == scb->io_ctx->csio.tag_id) 6841 || (tag == SCB_LIST_NULL)); 6842 } 6843 #else /* !AHD_TARGET_MODE */ 6844 match = ((tag == SCB_GET_TAG(scb)) || (tag == SCB_LIST_NULL)); 6845 #endif /* AHD_TARGET_MODE */ 6846 } 6847 6848 return match; 6849 } 6850 6851 void 6852 ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb) 6853 { 6854 int target; 6855 char channel; 6856 int lun; 6857 6858 target = SCB_GET_TARGET(ahd, scb); 6859 lun = SCB_GET_LUN(scb); 6860 channel = SCB_GET_CHANNEL(ahd, scb); 6861 6862 ahd_search_qinfifo(ahd, target, channel, lun, 6863 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 6864 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 6865 6866 ahd_platform_freeze_devq(ahd, scb); 6867 } 6868 6869 void 6870 ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, struct scb *scb) 6871 { 6872 struct scb *prev_scb; 6873 ahd_mode_state saved_modes; 6874 6875 saved_modes = ahd_save_modes(ahd); 6876 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6877 prev_scb = NULL; 6878 if (ahd_qinfifo_count(ahd) != 0) { 6879 u_int prev_tag; 6880 u_int prev_pos; 6881 6882 prev_pos = AHD_QIN_WRAP(ahd->qinfifonext - 1); 6883 prev_tag = ahd->qinfifo[prev_pos]; 6884 prev_scb = ahd_lookup_scb(ahd, prev_tag); 6885 } 6886 ahd_qinfifo_requeue(ahd, prev_scb, scb); 6887 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 6888 ahd_restore_modes(ahd, saved_modes); 6889 } 6890 6891 static void 6892 ahd_qinfifo_requeue(struct ahd_softc *ahd, struct scb *prev_scb, 6893 struct scb *scb) 6894 { 6895 if (prev_scb == NULL) { 6896 uint32_t busaddr; 6897 6898 busaddr = ahd_le32toh(scb->hscb->hscb_busaddr); 6899 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); 6900 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); 6901 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); 6902 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); 6903 } else { 6904 prev_scb->hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr; 6905 ahd_sync_scb(ahd, prev_scb, 6906 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 6907 } 6908 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb); 6909 ahd->qinfifonext++; 6910 scb->hscb->next_hscb_busaddr = ahd->next_queued_hscb->hscb_busaddr; 6911 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 6912 } 6913 6914 static int 6915 ahd_qinfifo_count(struct ahd_softc *ahd) 6916 { 6917 u_int qinpos; 6918 u_int wrap_qinpos; 6919 u_int wrap_qinfifonext; 6920 6921 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 6922 qinpos = ahd_get_snscb_qoff(ahd); 6923 wrap_qinpos = AHD_QIN_WRAP(qinpos); 6924 wrap_qinfifonext = AHD_QIN_WRAP(ahd->qinfifonext); 6925 if (wrap_qinfifonext >= wrap_qinpos) 6926 return (wrap_qinfifonext - wrap_qinpos); 6927 else 6928 return (wrap_qinfifonext 6929 + NUM_ELEMENTS(ahd->qinfifo) - wrap_qinpos); 6930 } 6931 6932 void 6933 ahd_reset_cmds_pending(struct ahd_softc *ahd) 6934 { 6935 struct scb *scb; 6936 ahd_mode_state saved_modes; 6937 u_int pending_cmds; 6938 6939 saved_modes = ahd_save_modes(ahd); 6940 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6941 6942 /* 6943 * Don't count any commands as outstanding that the 6944 * sequencer has already marked for completion. 6945 */ 6946 ahd_flush_qoutfifo(ahd); 6947 6948 pending_cmds = 0; 6949 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 6950 pending_cmds++; 6951 } 6952 ahd_outw(ahd, CMDS_PENDING, pending_cmds - ahd_qinfifo_count(ahd)); 6953 ahd_restore_modes(ahd, saved_modes); 6954 ahd->flags &= ~AHD_UPDATE_PEND_CMDS; 6955 } 6956 6957 int 6958 ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel, 6959 int lun, u_int tag, role_t role, uint32_t status, 6960 ahd_search_action action) 6961 { 6962 struct scb *scb; 6963 struct scb *prev_scb; 6964 ahd_mode_state saved_modes; 6965 u_int qinstart; 6966 u_int qinpos; 6967 u_int qintail; 6968 u_int tid_next; 6969 u_int tid_prev; 6970 u_int scbid; 6971 u_int savedscbptr; 6972 uint32_t busaddr; 6973 int found; 6974 int targets; 6975 6976 /* Must be in CCHAN mode */ 6977 saved_modes = ahd_save_modes(ahd); 6978 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6979 6980 /* 6981 * Halt any pending SCB DMA. The sequencer will reinitiate 6982 * this dma if the qinfifo is not empty once we unpause. 6983 */ 6984 if ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN|CCSCBDIR)) 6985 == (CCARREN|CCSCBEN|CCSCBDIR)) { 6986 ahd_outb(ahd, CCSCBCTL, 6987 ahd_inb(ahd, CCSCBCTL) & ~(CCARREN|CCSCBEN)); 6988 while ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0) 6989 ; 6990 } 6991 /* Determine sequencer's position in the qinfifo. */ 6992 qintail = AHD_QIN_WRAP(ahd->qinfifonext); 6993 qinstart = ahd_get_snscb_qoff(ahd); 6994 qinpos = AHD_QIN_WRAP(qinstart); 6995 found = 0; 6996 prev_scb = NULL; 6997 6998 if (action == SEARCH_PRINT) { 6999 printf("qinstart = %d qinfifonext = %d\nQINFIFO:", 7000 qinstart, ahd->qinfifonext); 7001 } 7002 7003 /* 7004 * Start with an empty queue. Entries that are not chosen 7005 * for removal will be re-added to the queue as we go. 7006 */ 7007 ahd->qinfifonext = qinstart; 7008 busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr); 7009 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 0, busaddr & 0xFF); 7010 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 1, (busaddr >> 8) & 0xFF); 7011 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 2, (busaddr >> 16) & 0xFF); 7012 ahd_outb(ahd, NEXT_QUEUED_SCB_ADDR + 3, (busaddr >> 24) & 0xFF); 7013 7014 while (qinpos != qintail) { 7015 scb = ahd_lookup_scb(ahd, ahd->qinfifo[qinpos]); 7016 if (scb == NULL) { 7017 printf("qinpos = %d, SCB index = %d\n", 7018 qinpos, ahd->qinfifo[qinpos]); 7019 panic("Loop 1\n"); 7020 } 7021 7022 if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) { 7023 /* 7024 * We found an scb that needs to be acted on. 7025 */ 7026 found++; 7027 switch (action) { 7028 case SEARCH_COMPLETE: 7029 { 7030 cam_status ostat; 7031 cam_status cstat; 7032 7033 ostat = ahd_get_transaction_status(scb); 7034 if (ostat == CAM_REQ_INPROG) 7035 ahd_set_transaction_status(scb, 7036 status); 7037 cstat = ahd_get_transaction_status(scb); 7038 if (cstat != CAM_REQ_CMP) 7039 ahd_freeze_scb(scb); 7040 if ((scb->flags & SCB_ACTIVE) == 0) 7041 printf("Inactive SCB in qinfifo\n"); 7042 ahd_done(ahd, scb); 7043 7044 /* FALLTHROUGH */ 7045 } 7046 case SEARCH_REMOVE: 7047 break; 7048 case SEARCH_PRINT: 7049 printf(" 0x%x", ahd->qinfifo[qinpos]); 7050 /* FALLTHROUGH */ 7051 case SEARCH_COUNT: 7052 ahd_qinfifo_requeue(ahd, prev_scb, scb); 7053 prev_scb = scb; 7054 break; 7055 } 7056 } else { 7057 ahd_qinfifo_requeue(ahd, prev_scb, scb); 7058 prev_scb = scb; 7059 } 7060 qinpos = AHD_QIN_WRAP(qinpos+1); 7061 } 7062 7063 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 7064 7065 if (action == SEARCH_PRINT) 7066 printf("\nWAITING_TID_QUEUES:\n"); 7067 7068 /* 7069 * Search waiting for selection lists. We traverse the 7070 * list of "their ids" waiting for selection and, if 7071 * appropriate, traverse the SCBs of each "their id" 7072 * looking for matches. 7073 */ 7074 savedscbptr = ahd_get_scbptr(ahd); 7075 tid_next = ahd_inw(ahd, WAITING_TID_HEAD); 7076 tid_prev = SCB_LIST_NULL; 7077 targets = 0; 7078 for (scbid = tid_next; !SCBID_IS_NULL(scbid); scbid = tid_next) { 7079 u_int tid_head; 7080 7081 /* 7082 * We limit based on the number of SCBs since 7083 * MK_MESSAGE SCBs are not in the per-tid lists. 7084 */ 7085 targets++; 7086 if (targets > AHD_SCB_MAX) { 7087 panic("TID LIST LOOP"); 7088 } 7089 if (scbid >= ahd->scb_data.numscbs) { 7090 printf("%s: Waiting TID List inconsistency. " 7091 "SCB index == 0x%x, yet numscbs == 0x%x.", 7092 ahd_name(ahd), scbid, ahd->scb_data.numscbs); 7093 ahd_dump_card_state(ahd); 7094 panic("for safety"); 7095 } 7096 scb = ahd_lookup_scb(ahd, scbid); 7097 if (scb == NULL) { 7098 printf("%s: SCB = 0x%x Not Active!\n", 7099 ahd_name(ahd), scbid); 7100 panic("Waiting TID List traversal\n"); 7101 } 7102 ahd_set_scbptr(ahd, scbid); 7103 tid_next = ahd_inw_scbram(ahd, SCB_NEXT2); 7104 if (ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD, 7105 SCB_LIST_NULL, ROLE_UNKNOWN) == 0) { 7106 tid_prev = scbid; 7107 continue; 7108 } 7109 7110 /* 7111 * We found a list of scbs that needs to be searched. 7112 */ 7113 if (action == SEARCH_PRINT) 7114 printf(" %d ( ", SCB_GET_TARGET(ahd, scb)); 7115 tid_head = scbid; 7116 found += ahd_search_scb_list(ahd, target, channel, 7117 lun, tag, role, status, 7118 action, &tid_head, 7119 SCB_GET_TARGET(ahd, scb)); 7120 if (tid_head != scbid) 7121 ahd_stitch_tid_list(ahd, tid_prev, tid_head, tid_next); 7122 if (!SCBID_IS_NULL(tid_head)) 7123 tid_prev = tid_head; 7124 if (action == SEARCH_PRINT) 7125 printf(")\n"); 7126 } 7127 ahd_set_scbptr(ahd, savedscbptr); 7128 ahd_restore_modes(ahd, saved_modes); 7129 return (found); 7130 } 7131 7132 static int 7133 ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel, 7134 int lun, u_int tag, role_t role, uint32_t status, 7135 ahd_search_action action, u_int *list_head, u_int tid) 7136 { 7137 struct scb *scb; 7138 u_int scbid; 7139 u_int next; 7140 u_int prev; 7141 int found; 7142 7143 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7144 found = 0; 7145 prev = SCB_LIST_NULL; 7146 next = *list_head; 7147 for (scbid = next; !SCBID_IS_NULL(scbid); scbid = next) { 7148 if (scbid >= ahd->scb_data.numscbs) { 7149 printf("%s:SCB List inconsistency. " 7150 "SCB == 0x%x, yet numscbs == 0x%x.", 7151 ahd_name(ahd), scbid, ahd->scb_data.numscbs); 7152 ahd_dump_card_state(ahd); 7153 panic("for safety"); 7154 } 7155 scb = ahd_lookup_scb(ahd, scbid); 7156 if (scb == NULL) { 7157 printf("%s: SCB = %d Not Active!\n", 7158 ahd_name(ahd), scbid); 7159 panic("Waiting List traversal\n"); 7160 } 7161 ahd_set_scbptr(ahd, scbid); 7162 next = ahd_inw_scbram(ahd, SCB_NEXT); 7163 if (ahd_match_scb(ahd, scb, target, channel, 7164 lun, SCB_LIST_NULL, role) == 0) { 7165 prev = scbid; 7166 continue; 7167 } 7168 found++; 7169 switch (action) { 7170 case SEARCH_COMPLETE: 7171 { 7172 cam_status ostat; 7173 cam_status cstat; 7174 7175 ostat = ahd_get_transaction_status(scb); 7176 if (ostat == CAM_REQ_INPROG) 7177 ahd_set_transaction_status(scb, status); 7178 cstat = ahd_get_transaction_status(scb); 7179 if (cstat != CAM_REQ_CMP) 7180 ahd_freeze_scb(scb); 7181 if ((scb->flags & SCB_ACTIVE) == 0) 7182 printf("Inactive SCB in Waiting List\n"); 7183 ahd_done(ahd, scb); 7184 /* FALLTHROUGH */ 7185 } 7186 case SEARCH_REMOVE: 7187 ahd_rem_wscb(ahd, scbid, prev, next, tid); 7188 if (prev == SCB_LIST_NULL) 7189 *list_head = next; 7190 break; 7191 case SEARCH_PRINT: 7192 printf("0x%x ", scbid); 7193 case SEARCH_COUNT: 7194 prev = scbid; 7195 break; 7196 } 7197 if (found > AHD_SCB_MAX) 7198 panic("SCB LIST LOOP"); 7199 } 7200 if (action == SEARCH_COMPLETE 7201 || action == SEARCH_REMOVE) 7202 ahd_outw(ahd, CMDS_PENDING, ahd_inw(ahd, CMDS_PENDING) - found); 7203 return (found); 7204 } 7205 7206 static void 7207 ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev, 7208 u_int tid_cur, u_int tid_next) 7209 { 7210 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7211 7212 if (SCBID_IS_NULL(tid_cur)) { 7213 7214 /* Bypass current TID list */ 7215 if (SCBID_IS_NULL(tid_prev)) { 7216 ahd_outw(ahd, WAITING_TID_HEAD, tid_next); 7217 } else { 7218 ahd_set_scbptr(ahd, tid_prev); 7219 ahd_outw(ahd, SCB_NEXT2, tid_next); 7220 } 7221 if (SCBID_IS_NULL(tid_next)) 7222 ahd_outw(ahd, WAITING_TID_TAIL, tid_prev); 7223 } else { 7224 7225 /* Stitch through tid_cur */ 7226 if (SCBID_IS_NULL(tid_prev)) { 7227 ahd_outw(ahd, WAITING_TID_HEAD, tid_cur); 7228 } else { 7229 ahd_set_scbptr(ahd, tid_prev); 7230 ahd_outw(ahd, SCB_NEXT2, tid_cur); 7231 } 7232 ahd_set_scbptr(ahd, tid_cur); 7233 ahd_outw(ahd, SCB_NEXT2, tid_next); 7234 7235 if (SCBID_IS_NULL(tid_next)) 7236 ahd_outw(ahd, WAITING_TID_TAIL, tid_cur); 7237 } 7238 } 7239 7240 /* 7241 * Manipulate the waiting for selection list and return the 7242 * scb that follows the one that we remove. 7243 */ 7244 static u_int 7245 ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, 7246 u_int prev, u_int next, u_int tid) 7247 { 7248 u_int tail_offset; 7249 7250 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7251 if (!SCBID_IS_NULL(prev)) { 7252 ahd_set_scbptr(ahd, prev); 7253 ahd_outw(ahd, SCB_NEXT, next); 7254 } 7255 7256 /* 7257 * SCBs that had MK_MESSAGE set in them will not 7258 * be queued to the per-target lists, so don't 7259 * blindly clear the tail pointer. 7260 */ 7261 tail_offset = WAITING_SCB_TAILS + (2 * tid); 7262 if (SCBID_IS_NULL(next) 7263 && ahd_inw(ahd, tail_offset) == scbid) 7264 ahd_outw(ahd, tail_offset, prev); 7265 ahd_add_scb_to_free_list(ahd, scbid); 7266 return (next); 7267 } 7268 7269 /* 7270 * Add the SCB as selected by SCBPTR onto the on chip list of 7271 * free hardware SCBs. This list is empty/unused if we are not 7272 * performing SCB paging. 7273 */ 7274 static void 7275 ahd_add_scb_to_free_list(struct ahd_softc *ahd, u_int scbid) 7276 { 7277 /* XXX Need some other mechanism to designate "free". */ 7278 /* 7279 * Invalidate the tag so that our abort 7280 * routines don't think it's active. 7281 ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL); 7282 */ 7283 } 7284 7285 /******************************** Error Handling ******************************/ 7286 /* 7287 * Abort all SCBs that match the given description (target/channel/lun/tag), 7288 * setting their status to the passed in status if the status has not already 7289 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 7290 * is paused before it is called. 7291 */ 7292 int 7293 ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel, 7294 int lun, u_int tag, role_t role, uint32_t status) 7295 { 7296 struct scb *scbp; 7297 struct scb *scbp_next; 7298 u_int active_scb; 7299 u_int i, j; 7300 u_int maxtarget; 7301 u_int minlun; 7302 u_int maxlun; 7303 int found; 7304 ahd_mode_state saved_modes; 7305 7306 /* restore these when we're done */ 7307 active_scb = ahd_get_scbptr(ahd); 7308 saved_modes = ahd_save_modes(ahd); 7309 7310 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7311 found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL, 7312 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 7313 7314 /* 7315 * Clean out the busy target table for any untagged commands. 7316 */ 7317 i = 0; 7318 maxtarget = 16; 7319 if (target != CAM_TARGET_WILDCARD) { 7320 i = target; 7321 if (channel == 'B') 7322 i += 8; 7323 maxtarget = i + 1; 7324 } 7325 7326 if (lun == CAM_LUN_WILDCARD) { 7327 minlun = 0; 7328 maxlun = AHD_NUM_LUNS_NONPKT; 7329 } else if (lun >= AHD_NUM_LUNS_NONPKT) { 7330 minlun = maxlun = 0; 7331 } else { 7332 minlun = lun; 7333 maxlun = lun + 1; 7334 } 7335 7336 if (role != ROLE_TARGET) { 7337 for (;i < maxtarget; i++) { 7338 for (j = minlun;j < maxlun; j++) { 7339 u_int scbid; 7340 u_int tcl; 7341 7342 tcl = BUILD_TCL_RAW(i, 'A', j); 7343 scbid = ahd_find_busy_tcl(ahd, tcl); 7344 scbp = ahd_lookup_scb(ahd, scbid); 7345 if (scbp == NULL 7346 || ahd_match_scb(ahd, scbp, target, channel, 7347 lun, tag, role) == 0) 7348 continue; 7349 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(i, 'A', j)); 7350 } 7351 } 7352 } 7353 7354 /* 7355 * Don't abort commands that have already completed, 7356 * but haven't quite made it up to the host yet. 7357 */ 7358 ahd_flush_qoutfifo(ahd); 7359 7360 /* 7361 * Go through the pending CCB list and look for 7362 * commands for this target that are still active. 7363 * These are other tagged commands that were 7364 * disconnected when the reset occurred. 7365 */ 7366 scbp_next = LIST_FIRST(&ahd->pending_scbs); 7367 while (scbp_next != NULL) { 7368 scbp = scbp_next; 7369 scbp_next = LIST_NEXT(scbp, pending_links); 7370 if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) { 7371 cam_status ostat; 7372 7373 ostat = ahd_get_transaction_status(scbp); 7374 if (ostat == CAM_REQ_INPROG) 7375 ahd_set_transaction_status(scbp, status); 7376 if (ahd_get_transaction_status(scbp) != CAM_REQ_CMP) 7377 ahd_freeze_scb(scbp); 7378 if ((scbp->flags & SCB_ACTIVE) == 0) 7379 printf("Inactive SCB on pending list\n"); 7380 ahd_done(ahd, scbp); 7381 found++; 7382 } 7383 } 7384 ahd_set_scbptr(ahd, active_scb); 7385 ahd_restore_modes(ahd, saved_modes); 7386 ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status); 7387 ahd->flags |= AHD_UPDATE_PEND_CMDS; 7388 return found; 7389 } 7390 7391 static void 7392 ahd_reset_current_bus(struct ahd_softc *ahd) 7393 { 7394 uint8_t scsiseq; 7395 7396 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7397 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENSCSIRST); 7398 scsiseq = ahd_inb(ahd, SCSISEQ0) & ~(ENSELO|ENARBO|SCSIRSTO); 7399 ahd_outb(ahd, SCSISEQ0, scsiseq | SCSIRSTO); 7400 ahd_delay(AHD_BUSRESET_DELAY); 7401 /* Turn off the bus reset */ 7402 ahd_outb(ahd, SCSISEQ0, scsiseq); 7403 if ((ahd->bugs & AHD_SCSIRST_BUG) != 0) { 7404 /* 7405 * 2A Razor #474 7406 * Certain chip state is not cleared for 7407 * SCSI bus resets that we initiate, so 7408 * we must reset the chip. 7409 */ 7410 ahd_delay(AHD_BUSRESET_DELAY); 7411 ahd_reset(ahd); 7412 ahd_intr_enable(ahd, /*enable*/TRUE); 7413 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7414 } 7415 7416 ahd_clear_intstat(ahd); 7417 } 7418 7419 int 7420 ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset) 7421 { 7422 struct ahd_devinfo devinfo; 7423 u_int initiator; 7424 u_int target; 7425 u_int max_scsiid; 7426 int found; 7427 u_int fifo; 7428 u_int next_fifo; 7429 7430 ahd->pending_device = NULL; 7431 7432 ahd_compile_devinfo(&devinfo, 7433 CAM_TARGET_WILDCARD, 7434 CAM_TARGET_WILDCARD, 7435 CAM_LUN_WILDCARD, 7436 channel, ROLE_UNKNOWN); 7437 ahd_pause(ahd); 7438 7439 /* Make sure the sequencer is in a safe location. */ 7440 ahd_clear_critical_section(ahd); 7441 7442 #if AHD_TARGET_MODE 7443 if ((ahd->flags & AHD_TARGETROLE) != 0) { 7444 ahd_run_tqinfifo(ahd, /*paused*/TRUE); 7445 } 7446 #endif 7447 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7448 7449 /* 7450 * Disable selections so no automatic hardware 7451 * functions will modify chip state. 7452 */ 7453 ahd_outb(ahd, SCSISEQ0, 0); 7454 ahd_outb(ahd, SCSISEQ1, 0); 7455 7456 /* 7457 * Safely shut down our DMA engines. Always start with 7458 * the FIFO that is not currently active (if any are 7459 * actively connected). 7460 */ 7461 next_fifo = fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; 7462 if (next_fifo > CURRFIFO_1) 7463 /* If disconneced, arbitrarily start with FIFO1. */ 7464 next_fifo = fifo = 0; 7465 do { 7466 next_fifo ^= CURRFIFO_1; 7467 ahd_set_modes(ahd, next_fifo, next_fifo); 7468 ahd_outb(ahd, DFCNTRL, 7469 ahd_inb(ahd, DFCNTRL) & ~(SCSIEN|HDMAEN)); 7470 while ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) 7471 ahd_delay(10); 7472 /* 7473 * Set CURRFIFO to the now inactive channel. 7474 */ 7475 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7476 ahd_outb(ahd, DFFSTAT, next_fifo); 7477 } while (next_fifo != fifo); 7478 /* 7479 * Reset the bus if we are initiating this reset 7480 */ 7481 ahd_clear_msg_state(ahd); 7482 ahd_outb(ahd, SIMODE1, 7483 ahd_inb(ahd, SIMODE1) & ~(ENBUSFREE|ENSCSIRST|ENBUSFREE)); 7484 if (initiate_reset) 7485 ahd_reset_current_bus(ahd); 7486 ahd_clear_intstat(ahd); 7487 7488 /* 7489 * Clean up all the state information for the 7490 * pending transactions on this bus. 7491 */ 7492 found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel, 7493 CAM_LUN_WILDCARD, SCB_LIST_NULL, 7494 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 7495 7496 /* 7497 * Cleanup anything left in the FIFOs. 7498 */ 7499 ahd_clear_fifo(ahd, 0); 7500 ahd_clear_fifo(ahd, 1); 7501 7502 /* 7503 * Revert to async/narrow transfers until we renegotiate. 7504 */ 7505 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7; 7506 for (target = 0; target <= max_scsiid; target++) { 7507 7508 if (ahd->enabled_targets[target] == NULL) 7509 continue; 7510 for (initiator = 0; initiator <= max_scsiid; initiator++) { 7511 struct ahd_devinfo devinfo; 7512 7513 ahd_compile_devinfo(&devinfo, target, initiator, 7514 CAM_LUN_WILDCARD, 7515 'A', ROLE_UNKNOWN); 7516 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 7517 AHD_TRANS_CUR, /*paused*/TRUE); 7518 ahd_set_syncrate(ahd, &devinfo, /*period*/0, 7519 /*offset*/0, /*ppr_options*/0, 7520 AHD_TRANS_CUR, /*paused*/TRUE); 7521 } 7522 } 7523 7524 #ifdef AHD_TARGET_MODE 7525 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7; 7526 7527 /* 7528 * Send an immediate notify ccb to all target more peripheral 7529 * drivers affected by this action. 7530 */ 7531 for (target = 0; target <= max_scsiid; target++) { 7532 struct ahd_tmode_tstate* tstate; 7533 u_int lun; 7534 7535 tstate = ahd->enabled_targets[target]; 7536 if (tstate == NULL) 7537 continue; 7538 for (lun = 0; lun < AHD_NUM_LUNS; lun++) { 7539 struct ahd_tmode_lstate* lstate; 7540 7541 lstate = tstate->enabled_luns[lun]; 7542 if (lstate == NULL) 7543 continue; 7544 7545 ahd_queue_lstate_event(ahd, lstate, CAM_TARGET_WILDCARD, 7546 EVENT_TYPE_BUS_RESET, /*arg*/0); 7547 ahd_send_lstate_events(ahd, lstate); 7548 } 7549 } 7550 #endif 7551 /* Notify the XPT that a bus reset occurred */ 7552 ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD, 7553 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL); 7554 ahd_restart(ahd); 7555 /* 7556 * Freeze the SIMQ until our poller can determine that 7557 * the bus reset has really gone away. We set the initial 7558 * timer to 0 to have the check performed as soon as possible 7559 * from the timer context. 7560 */ 7561 if ((ahd->flags & AHD_RESET_POLL_ACTIVE) == 0) { 7562 ahd->flags |= AHD_RESET_POLL_ACTIVE; 7563 ahd_freeze_simq(ahd); 7564 ahd_timer_reset(&ahd->reset_timer, 0, ahd_reset_poll, ahd); 7565 } 7566 return (found); 7567 } 7568 7569 7570 #define AHD_RESET_POLL_US 1000 7571 static void 7572 ahd_reset_poll(void *arg) 7573 { 7574 struct ahd_softc *ahd; 7575 u_int scsiseq1; 7576 u_long l; 7577 u_long s; 7578 7579 ahd_list_lock(&l); 7580 ahd = ahd_find_softc((struct ahd_softc *)arg); 7581 if (ahd == NULL) { 7582 printf("ahd_reset_poll: Instance %p no longer exists\n", arg); 7583 ahd_list_unlock(&l); 7584 return; 7585 } 7586 ahd_lock(ahd, &s); 7587 ahd_pause(ahd); 7588 ahd_update_modes(ahd); 7589 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7590 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); 7591 if ((ahd_inb(ahd, SSTAT1) & SCSIRSTI) != 0) { 7592 ahd_timer_reset(&ahd->reset_timer, AHD_RESET_POLL_US, 7593 ahd_reset_poll, ahd); 7594 ahd_unpause(ahd); 7595 ahd_unlock(ahd, &s); 7596 ahd_list_unlock(&l); 7597 return; 7598 } 7599 7600 /* Reset is now low. Complete chip reinitialization. */ 7601 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST); 7602 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 7603 ahd_outb(ahd, SCSISEQ1, scsiseq1 & (ENSELI|ENRSELI|ENAUTOATNP)); 7604 ahd_unpause(ahd); 7605 ahd->flags &= ~AHD_RESET_POLL_ACTIVE; 7606 ahd_unlock(ahd, &s); 7607 ahd_release_simq(ahd); 7608 ahd_list_unlock(&l); 7609 } 7610 7611 /**************************** Statistics Processing ***************************/ 7612 static void 7613 ahd_stat_timer(void *arg) 7614 { 7615 struct ahd_softc *ahd; 7616 u_long l; 7617 u_long s; 7618 int enint_coal; 7619 7620 ahd_list_lock(&l); 7621 ahd = ahd_find_softc((struct ahd_softc *)arg); 7622 if (ahd == NULL) { 7623 printf("ahd_stat_timer: Instance %p no longer exists\n", arg); 7624 ahd_list_unlock(&l); 7625 return; 7626 } 7627 ahd_lock(ahd, &s); 7628 7629 enint_coal = ahd->hs_mailbox & ENINT_COALESS; 7630 if (ahd->cmdcmplt_total > ahd->int_coalessing_threshold) 7631 enint_coal |= ENINT_COALESS; 7632 else if (ahd->cmdcmplt_total < ahd->int_coalessing_stop_threshold) 7633 enint_coal &= ~ENINT_COALESS; 7634 7635 if (enint_coal != (ahd->hs_mailbox & ENINT_COALESS)) { 7636 ahd_enable_coalessing(ahd, enint_coal); 7637 #ifdef AHD_DEBUG 7638 if ((ahd_debug & AHD_SHOW_INT_COALESSING) != 0) 7639 printf("%s: Interrupt coalessing " 7640 "now %sabled. Cmds %d\n", 7641 ahd_name(ahd), 7642 (enint_coal & ENINT_COALESS) ? "en" : "dis", 7643 ahd->cmdcmplt_total); 7644 #endif 7645 } 7646 7647 ahd->cmdcmplt_bucket = (ahd->cmdcmplt_bucket+1) & (AHD_STAT_BUCKETS-1); 7648 ahd->cmdcmplt_total -= ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket]; 7649 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket] = 0; 7650 ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US, 7651 ahd_stat_timer, ahd); 7652 ahd_unlock(ahd, &s); 7653 ahd_list_unlock(&l); 7654 } 7655 7656 /****************************** Status Processing *****************************/ 7657 void 7658 ahd_handle_scb_status(struct ahd_softc *ahd, struct scb *scb) 7659 { 7660 if (scb->hscb->shared_data.istatus.scsi_status != 0) { 7661 ahd_handle_scsi_status(ahd, scb); 7662 } else { 7663 ahd_calc_residual(ahd, scb); 7664 ahd_done(ahd, scb); 7665 } 7666 } 7667 7668 void 7669 ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb) 7670 { 7671 struct hardware_scb *hscb; 7672 u_int qfreeze_cnt; 7673 ahd_mode_state saved_modes; 7674 7675 /* 7676 * The sequencer freezes its select-out queue 7677 * anytime a SCSI status error occurs. We must 7678 * handle the error and decrement the QFREEZE count 7679 * to allow the sequencer to continue. 7680 */ 7681 hscb = scb->hscb; 7682 7683 /* Freeze the queue until the client sees the error. */ 7684 ahd_pause(ahd); 7685 saved_modes = ahd_save_modes(ahd); 7686 ahd_clear_critical_section(ahd); 7687 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7688 ahd_freeze_devq(ahd, scb); 7689 ahd_freeze_scb(scb); 7690 qfreeze_cnt = ahd_inw(ahd, QFREEZE_COUNT); 7691 if (qfreeze_cnt == 0) { 7692 printf("%s: Bad status with 0 qfreeze count!\n", ahd_name(ahd)); 7693 } else { 7694 qfreeze_cnt--; 7695 ahd_outw(ahd, QFREEZE_COUNT, qfreeze_cnt); 7696 } 7697 if (qfreeze_cnt == 0) 7698 ahd_outb(ahd, SEQ_FLAGS2, 7699 ahd_inb(ahd, SEQ_FLAGS2) & ~SELECTOUT_QFROZEN); 7700 ahd_unpause(ahd); 7701 /* Don't want to clobber the original sense code */ 7702 if ((scb->flags & SCB_SENSE) != 0) { 7703 /* 7704 * Clear the SCB_SENSE Flag and perform 7705 * a normal command completion. 7706 */ 7707 scb->flags &= ~SCB_SENSE; 7708 ahd_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 7709 ahd_done(ahd, scb); 7710 return; 7711 } 7712 ahd_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR); 7713 ahd_set_scsi_status(scb, hscb->shared_data.istatus.scsi_status); 7714 switch (hscb->shared_data.istatus.scsi_status) { 7715 case STATUS_PKT_SENSE: 7716 { 7717 struct scsi_status_iu_header *siu; 7718 7719 ahd_sync_sense(ahd, scb, BUS_DMASYNC_POSTREAD); 7720 siu = (struct scsi_status_iu_header *)scb->sense_data; 7721 ahd_set_scsi_status(scb, siu->status); 7722 #ifdef AHD_DEBUG 7723 if ((ahd_debug & AHD_SHOW_SENSE) != 0) { 7724 ahd_print_path(ahd, scb); 7725 printf("SCB 0x%x Received PKT Status of 0x%x\n", 7726 SCB_GET_TAG(scb), siu->status); 7727 printf("\tflags = 0x%x, sense len = 0x%x, " 7728 "pktfail = 0x%x\n", 7729 siu->flags, scsi_4btoul(siu->sense_length), 7730 scsi_4btoul(siu->pkt_failures_length)); 7731 } 7732 #endif 7733 if ((siu->flags & SIU_RSPVALID) != 0) { 7734 ahd_print_path(ahd, scb); 7735 if (scsi_4btoul(siu->pkt_failures_length) < 4) { 7736 printf("Unable to parse pkt_failures\n"); 7737 } else { 7738 7739 switch (SIU_PKTFAIL_CODE(siu)) { 7740 case SIU_PFC_NONE: 7741 printf("No packet failure found\n"); 7742 break; 7743 case SIU_PFC_CIU_FIELDS_INVALID: 7744 printf("Invalid Command IU Field\n"); 7745 break; 7746 case SIU_PFC_TMF_NOT_SUPPORTED: 7747 printf("TMF not supportd\n"); 7748 break; 7749 case SIU_PFC_TMF_FAILED: 7750 printf("TMF failed\n"); 7751 break; 7752 case SIU_PFC_INVALID_TYPE_CODE: 7753 printf("Invalid L_Q Type code\n"); 7754 break; 7755 case SIU_PFC_ILLEGAL_REQUEST: 7756 printf("Illegal request\n"); 7757 default: 7758 break; 7759 } 7760 } 7761 if (siu->status == SCSI_STATUS_OK) 7762 ahd_set_transaction_status(scb, 7763 CAM_REQ_CMP_ERR); 7764 } 7765 if ((siu->flags & SIU_SNSVALID) != 0) { 7766 scb->flags |= SCB_PKT_SENSE; 7767 #ifdef AHD_DEBUG 7768 if ((ahd_debug & AHD_SHOW_SENSE) != 0) 7769 printf("Sense data available\n"); 7770 #endif 7771 } 7772 ahd_done(ahd, scb); 7773 break; 7774 } 7775 case SCSI_STATUS_CMD_TERMINATED: 7776 case SCSI_STATUS_CHECK_COND: 7777 { 7778 struct ahd_devinfo devinfo; 7779 struct ahd_dma_seg *sg; 7780 struct scsi_sense *sc; 7781 struct ahd_initiator_tinfo *targ_info; 7782 struct ahd_tmode_tstate *tstate; 7783 struct ahd_transinfo *tinfo; 7784 #ifdef AHD_DEBUG 7785 if (ahd_debug & AHD_SHOW_SENSE) { 7786 ahd_print_path(ahd, scb); 7787 printf("SCB %d: requests Check Status\n", 7788 SCB_GET_TAG(scb)); 7789 } 7790 #endif 7791 7792 if (ahd_perform_autosense(scb) == 0) 7793 break; 7794 7795 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), 7796 SCB_GET_TARGET(ahd, scb), 7797 SCB_GET_LUN(scb), 7798 SCB_GET_CHANNEL(ahd, scb), 7799 ROLE_INITIATOR); 7800 targ_info = ahd_fetch_transinfo(ahd, 7801 devinfo.channel, 7802 devinfo.our_scsiid, 7803 devinfo.target, 7804 &tstate); 7805 tinfo = &targ_info->curr; 7806 sg = scb->sg_list; 7807 sc = (struct scsi_sense *)hscb->shared_data.idata.cdb; 7808 /* 7809 * Save off the residual if there is one. 7810 */ 7811 ahd_update_residual(ahd, scb); 7812 #ifdef AHD_DEBUG 7813 if (ahd_debug & AHD_SHOW_SENSE) { 7814 ahd_print_path(ahd, scb); 7815 printf("Sending Sense\n"); 7816 } 7817 #endif 7818 scb->sg_count = 0; 7819 sg = ahd_sg_setup(ahd, scb, sg, ahd_get_sense_bufaddr(ahd, scb), 7820 ahd_get_sense_bufsize(ahd, scb), 7821 /*last*/TRUE); 7822 sc->opcode = REQUEST_SENSE; 7823 sc->byte2 = 0; 7824 if (tinfo->protocol_version <= SCSI_REV_2 7825 && SCB_GET_LUN(scb) < 8) 7826 sc->byte2 = SCB_GET_LUN(scb) << 5; 7827 sc->unused[0] = 0; 7828 sc->unused[1] = 0; 7829 sc->length = ahd_get_sense_bufsize(ahd, scb); 7830 sc->control = 0; 7831 7832 /* 7833 * We can't allow the target to disconnect. 7834 * This will be an untagged transaction and 7835 * having the target disconnect will make this 7836 * transaction indestinguishable from outstanding 7837 * tagged transactions. 7838 */ 7839 hscb->control = 0; 7840 7841 /* 7842 * This request sense could be because the 7843 * the device lost power or in some other 7844 * way has lost our transfer negotiations. 7845 * Renegotiate if appropriate. Unit attention 7846 * errors will be reported before any data 7847 * phases occur. 7848 */ 7849 if (ahd_get_residual(scb) == ahd_get_transfer_length(scb)) { 7850 ahd_update_neg_request(ahd, &devinfo, 7851 tstate, targ_info, 7852 AHD_NEG_IF_NON_ASYNC); 7853 } 7854 if (tstate->auto_negotiate & devinfo.target_mask) { 7855 hscb->control |= MK_MESSAGE; 7856 scb->flags &= 7857 ~(SCB_NEGOTIATE|SCB_ABORT|SCB_DEVICE_RESET); 7858 scb->flags |= SCB_AUTO_NEGOTIATE; 7859 } 7860 hscb->cdb_len = sizeof(*sc); 7861 ahd_setup_data_scb(ahd, scb); 7862 scb->flags |= SCB_SENSE; 7863 ahd_queue_scb(ahd, scb); 7864 /* 7865 * Ensure we have enough time to actually 7866 * retrieve the sense. 7867 */ 7868 ahd_scb_timer_reset(scb, 5 * 1000000); 7869 break; 7870 } 7871 case SCSI_STATUS_OK: 7872 printf("%s: Interrupted for staus of 0???\n", 7873 ahd_name(ahd)); 7874 /* FALLTHROUGH */ 7875 default: 7876 ahd_done(ahd, scb); 7877 break; 7878 } 7879 } 7880 7881 /* 7882 * Calculate the residual for a just completed SCB. 7883 */ 7884 void 7885 ahd_calc_residual(struct ahd_softc *ahd, struct scb *scb) 7886 { 7887 struct hardware_scb *hscb; 7888 struct initiator_status *spkt; 7889 uint32_t sgptr; 7890 uint32_t resid_sgptr; 7891 uint32_t resid; 7892 7893 /* 7894 * 5 cases. 7895 * 1) No residual. 7896 * SG_STATUS_VALID clear in sgptr. 7897 * 2) Transferless command 7898 * 3) Never performed any transfers. 7899 * sgptr has SG_FULL_RESID set. 7900 * 4) No residual but target did not 7901 * save data pointers after the 7902 * last transfer, so sgptr was 7903 * never updated. 7904 * 5) We have a partial residual. 7905 * Use residual_sgptr to determine 7906 * where we are. 7907 */ 7908 7909 hscb = scb->hscb; 7910 sgptr = ahd_le32toh(hscb->sgptr); 7911 if ((sgptr & SG_STATUS_VALID) == 0) 7912 /* Case 1 */ 7913 return; 7914 sgptr &= ~SG_STATUS_VALID; 7915 7916 if ((sgptr & SG_LIST_NULL) != 0) 7917 /* Case 2 */ 7918 return; 7919 7920 /* 7921 * Residual fields are the same in both 7922 * target and initiator status packets, 7923 * so we can always use the initiator fields 7924 * regardless of the role for this SCB. 7925 */ 7926 spkt = &hscb->shared_data.istatus; 7927 resid_sgptr = ahd_le32toh(spkt->residual_sgptr); 7928 if ((sgptr & SG_FULL_RESID) != 0) { 7929 /* Case 3 */ 7930 resid = ahd_get_transfer_length(scb); 7931 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 7932 /* Case 4 */ 7933 return; 7934 } else if ((resid_sgptr & SG_OVERRUN_RESID) != 0) { 7935 ahd_print_path(ahd, scb); 7936 printf("data overrun detected Tag == 0x%x.\n", 7937 SCB_GET_TAG(scb)); 7938 ahd_freeze_devq(ahd, scb); 7939 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR); 7940 ahd_freeze_scb(scb); 7941 return; 7942 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 7943 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 7944 /* NOTREACHED */ 7945 } else { 7946 struct ahd_dma_seg *sg; 7947 7948 /* 7949 * Remainder of the SG where the transfer 7950 * stopped. 7951 */ 7952 resid = ahd_le32toh(spkt->residual_datacnt) & AHD_SG_LEN_MASK; 7953 sg = ahd_sg_bus_to_virt(ahd, scb, resid_sgptr & SG_PTR_MASK); 7954 7955 /* The residual sg_ptr always points to the next sg */ 7956 sg--; 7957 7958 /* 7959 * Add up the contents of all residual 7960 * SG segments that are after the SG where 7961 * the transfer stopped. 7962 */ 7963 while ((ahd_le32toh(sg->len) & AHD_DMA_LAST_SEG) == 0) { 7964 sg++; 7965 resid += ahd_le32toh(sg->len) & AHD_SG_LEN_MASK; 7966 } 7967 } 7968 if ((scb->flags & SCB_SENSE) == 0) 7969 ahd_set_residual(scb, resid); 7970 else 7971 ahd_set_sense_residual(scb, resid); 7972 7973 #ifdef AHD_DEBUG 7974 if ((ahd_debug & AHD_SHOW_MISC) != 0) { 7975 ahd_print_path(ahd, scb); 7976 printf("Handled %sResidual of %d bytes\n", 7977 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 7978 } 7979 #endif 7980 } 7981 7982 /******************************* Target Mode **********************************/ 7983 #ifdef AHD_TARGET_MODE 7984 /* 7985 * Add a target mode event to this lun's queue 7986 */ 7987 static void 7988 ahd_queue_lstate_event(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate, 7989 u_int initiator_id, u_int event_type, u_int event_arg) 7990 { 7991 struct ahd_tmode_event *event; 7992 int pending; 7993 7994 xpt_freeze_devq(lstate->path, /*count*/1); 7995 if (lstate->event_w_idx >= lstate->event_r_idx) 7996 pending = lstate->event_w_idx - lstate->event_r_idx; 7997 else 7998 pending = AHD_TMODE_EVENT_BUFFER_SIZE + 1 7999 - (lstate->event_r_idx - lstate->event_w_idx); 8000 8001 if (event_type == EVENT_TYPE_BUS_RESET 8002 || event_type == MSG_BUS_DEV_RESET) { 8003 /* 8004 * Any earlier events are irrelevant, so reset our buffer. 8005 * This has the effect of allowing us to deal with reset 8006 * floods (an external device holding down the reset line) 8007 * without losing the event that is really interesting. 8008 */ 8009 lstate->event_r_idx = 0; 8010 lstate->event_w_idx = 0; 8011 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 8012 } 8013 8014 if (pending == AHD_TMODE_EVENT_BUFFER_SIZE) { 8015 xpt_print_path(lstate->path); 8016 printf("immediate event %x:%x lost\n", 8017 lstate->event_buffer[lstate->event_r_idx].event_type, 8018 lstate->event_buffer[lstate->event_r_idx].event_arg); 8019 lstate->event_r_idx++; 8020 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 8021 lstate->event_r_idx = 0; 8022 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 8023 } 8024 8025 event = &lstate->event_buffer[lstate->event_w_idx]; 8026 event->initiator_id = initiator_id; 8027 event->event_type = event_type; 8028 event->event_arg = event_arg; 8029 lstate->event_w_idx++; 8030 if (lstate->event_w_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 8031 lstate->event_w_idx = 0; 8032 } 8033 8034 /* 8035 * Send any target mode events queued up waiting 8036 * for immediate notify resources. 8037 */ 8038 void 8039 ahd_send_lstate_events(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate) 8040 { 8041 struct ccb_hdr *ccbh; 8042 struct ccb_immed_notify *inot; 8043 8044 while (lstate->event_r_idx != lstate->event_w_idx 8045 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 8046 struct ahd_tmode_event *event; 8047 8048 event = &lstate->event_buffer[lstate->event_r_idx]; 8049 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 8050 inot = (struct ccb_immed_notify *)ccbh; 8051 switch (event->event_type) { 8052 case EVENT_TYPE_BUS_RESET: 8053 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 8054 break; 8055 default: 8056 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 8057 inot->message_args[0] = event->event_type; 8058 inot->message_args[1] = event->event_arg; 8059 break; 8060 } 8061 inot->initiator_id = event->initiator_id; 8062 inot->sense_len = 0; 8063 xpt_done((union ccb *)inot); 8064 lstate->event_r_idx++; 8065 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 8066 lstate->event_r_idx = 0; 8067 } 8068 } 8069 #endif 8070 8071 /******************** Sequencer Program Patching/Download *********************/ 8072 8073 #ifdef AHD_DUMP_SEQ 8074 void 8075 ahd_dumpseq(struct ahd_softc* ahd) 8076 { 8077 int i; 8078 int max_prog; 8079 8080 max_prog = 2048; 8081 8082 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 8083 ahd_outb(ahd, PRGMCNT, 0); 8084 ahd_outb(ahd, PRGMCNT+1, 0); 8085 for (i = 0; i < max_prog; i++) { 8086 uint8_t ins_bytes[4]; 8087 8088 ahd_insb(ahd, SEQRAM, ins_bytes, 4); 8089 printf("0x%08x\n", ins_bytes[0] << 24 8090 | ins_bytes[1] << 16 8091 | ins_bytes[2] << 8 8092 | ins_bytes[3]); 8093 } 8094 } 8095 #endif 8096 8097 static void 8098 ahd_loadseq(struct ahd_softc *ahd) 8099 { 8100 struct cs cs_table[num_critical_sections]; 8101 u_int begin_set[num_critical_sections]; 8102 u_int end_set[num_critical_sections]; 8103 struct patch *cur_patch; 8104 u_int cs_count; 8105 u_int cur_cs; 8106 u_int i; 8107 int downloaded; 8108 u_int skip_addr; 8109 u_int sg_prefetch_cnt; 8110 u_int sg_prefetch_cnt_limit; 8111 u_int sg_prefetch_align; 8112 u_int sg_size; 8113 uint8_t download_consts[DOWNLOAD_CONST_COUNT]; 8114 8115 if (bootverbose) 8116 printf("%s: Downloading Sequencer Program...", 8117 ahd_name(ahd)); 8118 8119 #if DOWNLOAD_CONST_COUNT != 7 8120 #error "Download Const Mismatch" 8121 #endif 8122 /* 8123 * Start out with 0 critical sections 8124 * that apply to this firmware load. 8125 */ 8126 cs_count = 0; 8127 cur_cs = 0; 8128 memset(begin_set, 0, sizeof(begin_set)); 8129 memset(end_set, 0, sizeof(end_set)); 8130 8131 /* 8132 * Setup downloadable constant table. 8133 * 8134 * The computation for the S/G prefetch variables is 8135 * a bit complicated. We would like to always fetch 8136 * in terms of cachelined sized increments. However, 8137 * if the cacheline is not an even multiple of the 8138 * SG element size or is larger than our SG RAM, using 8139 * just the cache size might leave us with only a portion 8140 * of an SG element at the tail of a prefetch. If the 8141 * cacheline is larger than our S/G prefetch buffer less 8142 * the size of an SG element, we may round down to a cacheline 8143 * that doesn't contain any or all of the S/G of interest 8144 * within the bounds of our S/G ram. Provide variables to 8145 * the sequencer that will allow it to handle these edge 8146 * cases. 8147 */ 8148 /* Start by aligning to the nearest cacheline. */ 8149 sg_prefetch_align = ahd->pci_cachesize; 8150 if (sg_prefetch_align == 0) 8151 sg_prefetch_cnt = 8; 8152 /* Round down to the nearest power of 2. */ 8153 while (powerof2(sg_prefetch_align) == 0) 8154 sg_prefetch_align--; 8155 /* 8156 * If the cacheline boundary is greater than half our prefetch RAM 8157 * we risk not being able to fetch even a single complete S/G 8158 * segment if we align to that boundary. 8159 */ 8160 if (sg_prefetch_align > CCSGADDR_MAX/2) 8161 sg_prefetch_align = CCSGADDR_MAX/2; 8162 /* Start by fetching a single cacheline. */ 8163 sg_prefetch_cnt = sg_prefetch_align; 8164 /* 8165 * Increment the prefetch count by cachelines until 8166 * at least one S/G element will fit. 8167 */ 8168 sg_size = sizeof(struct ahd_dma_seg); 8169 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 8170 sg_size = sizeof(struct ahd_dma64_seg); 8171 while (sg_prefetch_cnt < sg_size) 8172 sg_prefetch_cnt += sg_prefetch_align; 8173 /* 8174 * If the cacheline is not an even multiple of 8175 * the S/G size, we may only get a partial S/G when 8176 * we align. Add a cacheline if this is the case. 8177 */ 8178 if ((sg_prefetch_align % sg_size) != 0 8179 && (sg_prefetch_cnt < CCSGADDR_MAX)) 8180 sg_prefetch_cnt += sg_prefetch_align; 8181 /* 8182 * Lastly, compute a value that the sequencer can use 8183 * to determine if the remainder of the CCSGRAM buffer 8184 * has a full S/G element in it. 8185 */ 8186 sg_prefetch_cnt_limit = -(sg_prefetch_cnt - sg_size + 1); 8187 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 8188 download_consts[SG_PREFETCH_CNT_LIMIT] = sg_prefetch_cnt_limit; 8189 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_align - 1); 8190 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_align - 1); 8191 download_consts[SG_SIZEOF] = sg_size; 8192 download_consts[PKT_OVERRUN_BUFOFFSET] = 8193 (ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256; 8194 download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_1BYTE_LUN; 8195 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) 8196 download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_FULL_LUN; 8197 cur_patch = patches; 8198 downloaded = 0; 8199 skip_addr = 0; 8200 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 8201 ahd_outb(ahd, PRGMCNT, 0); 8202 ahd_outb(ahd, PRGMCNT+1, 0); 8203 8204 for (i = 0; i < sizeof(seqprog)/4; i++) { 8205 if (ahd_check_patch(ahd, &cur_patch, i, &skip_addr) == 0) { 8206 /* 8207 * Don't download this instruction as it 8208 * is in a patch that was removed. 8209 */ 8210 continue; 8211 } 8212 /* 8213 * Move through the CS table until we find a CS 8214 * that might apply to this instruction. 8215 */ 8216 for (; cur_cs < num_critical_sections; cur_cs++) { 8217 if (critical_sections[cur_cs].end <= i) { 8218 if (begin_set[cs_count] == TRUE 8219 && end_set[cs_count] == FALSE) { 8220 cs_table[cs_count].end = downloaded; 8221 end_set[cs_count] = TRUE; 8222 cs_count++; 8223 } 8224 continue; 8225 } 8226 if (critical_sections[cur_cs].begin <= i 8227 && begin_set[cs_count] == FALSE) { 8228 cs_table[cs_count].begin = downloaded; 8229 begin_set[cs_count] = TRUE; 8230 } 8231 break; 8232 } 8233 ahd_download_instr(ahd, i, download_consts); 8234 downloaded++; 8235 } 8236 8237 ahd->num_critical_sections = cs_count; 8238 if (cs_count != 0) { 8239 8240 cs_count *= sizeof(struct cs); 8241 ahd->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 8242 if (ahd->critical_sections == NULL) 8243 panic("ahd_loadseq: Could not malloc"); 8244 memcpy(ahd->critical_sections, cs_table, cs_count); 8245 } 8246 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE); 8247 8248 if (bootverbose) { 8249 printf(" %d instructions downloaded\n", downloaded); 8250 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 8251 ahd_name(ahd), ahd->features, ahd->bugs, ahd->flags); 8252 } 8253 } 8254 8255 static int 8256 ahd_check_patch(struct ahd_softc *ahd, struct patch **start_patch, 8257 u_int start_instr, u_int *skip_addr) 8258 { 8259 struct patch *cur_patch; 8260 struct patch *last_patch; 8261 u_int num_patches; 8262 8263 num_patches = sizeof(patches)/sizeof(struct patch); 8264 last_patch = &patches[num_patches]; 8265 cur_patch = *start_patch; 8266 8267 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 8268 8269 if (cur_patch->patch_func(ahd) == 0) { 8270 8271 /* Start rejecting code */ 8272 *skip_addr = start_instr + cur_patch->skip_instr; 8273 cur_patch += cur_patch->skip_patch; 8274 } else { 8275 /* Accepted this patch. Advance to the next 8276 * one and wait for our intruction pointer to 8277 * hit this point. 8278 */ 8279 cur_patch++; 8280 } 8281 } 8282 8283 *start_patch = cur_patch; 8284 if (start_instr < *skip_addr) 8285 /* Still skipping */ 8286 return (0); 8287 8288 return (1); 8289 } 8290 8291 static u_int 8292 ahd_resolve_seqaddr(struct ahd_softc *ahd, u_int address) 8293 { 8294 struct patch *cur_patch; 8295 int address_offset; 8296 u_int skip_addr; 8297 u_int i; 8298 8299 address_offset = 0; 8300 cur_patch = patches; 8301 skip_addr = 0; 8302 8303 for (i = 0; i < address;) { 8304 8305 ahd_check_patch(ahd, &cur_patch, i, &skip_addr); 8306 8307 if (skip_addr > i) { 8308 int end_addr; 8309 8310 end_addr = MIN(address, skip_addr); 8311 address_offset += end_addr - i; 8312 i = skip_addr; 8313 } else { 8314 i++; 8315 } 8316 } 8317 return (address - address_offset); 8318 } 8319 8320 static void 8321 ahd_download_instr(struct ahd_softc *ahd, u_int instrptr, uint8_t *dconsts) 8322 { 8323 union ins_formats instr; 8324 struct ins_format1 *fmt1_ins; 8325 struct ins_format3 *fmt3_ins; 8326 u_int opcode; 8327 8328 /* 8329 * The firmware is always compiled into a little endian format. 8330 */ 8331 instr.integer = ahd_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 8332 8333 fmt1_ins = &instr.format1; 8334 fmt3_ins = NULL; 8335 8336 /* Pull the opcode */ 8337 opcode = instr.format1.opcode; 8338 switch (opcode) { 8339 case AIC_OP_JMP: 8340 case AIC_OP_JC: 8341 case AIC_OP_JNC: 8342 case AIC_OP_CALL: 8343 case AIC_OP_JNE: 8344 case AIC_OP_JNZ: 8345 case AIC_OP_JE: 8346 case AIC_OP_JZ: 8347 { 8348 fmt3_ins = &instr.format3; 8349 fmt3_ins->address = ahd_resolve_seqaddr(ahd, fmt3_ins->address); 8350 /* FALLTHROUGH */ 8351 } 8352 case AIC_OP_OR: 8353 case AIC_OP_AND: 8354 case AIC_OP_XOR: 8355 case AIC_OP_ADD: 8356 case AIC_OP_ADC: 8357 case AIC_OP_BMOV: 8358 if (fmt1_ins->parity != 0) { 8359 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 8360 } 8361 fmt1_ins->parity = 0; 8362 /* FALLTHROUGH */ 8363 case AIC_OP_ROL: 8364 { 8365 int i, count; 8366 8367 /* Calculate odd parity for the instruction */ 8368 for (i = 0, count = 0; i < 31; i++) { 8369 uint32_t mask; 8370 8371 mask = 0x01 << i; 8372 if ((instr.integer & mask) != 0) 8373 count++; 8374 } 8375 if ((count & 0x01) == 0) 8376 instr.format1.parity = 1; 8377 8378 /* The sequencer is a little endian cpu */ 8379 instr.integer = ahd_htole32(instr.integer); 8380 ahd_outsb(ahd, SEQRAM, instr.bytes, 4); 8381 break; 8382 } 8383 default: 8384 panic("Unknown opcode encountered in seq program"); 8385 break; 8386 } 8387 } 8388 8389 static int 8390 ahd_probe_stack_size(struct ahd_softc *ahd) 8391 { 8392 int last_probe; 8393 8394 last_probe = 0; 8395 while (1) { 8396 int i; 8397 8398 /* 8399 * We avoid using 0 as a pattern to avoid 8400 * confusion if the stack implementation 8401 * "back-fills" with zeros when "poping' 8402 * entries. 8403 */ 8404 for (i = 1; i <= last_probe+1; i++) { 8405 ahd_outb(ahd, STACK, i & 0xFF); 8406 ahd_outb(ahd, STACK, (i >> 8) & 0xFF); 8407 } 8408 8409 /* Verify */ 8410 for (i = last_probe+1; i > 0; i--) { 8411 u_int stack_entry; 8412 8413 stack_entry = ahd_inb(ahd, STACK) 8414 |(ahd_inb(ahd, STACK) << 8); 8415 if (stack_entry != i) 8416 goto sized; 8417 } 8418 last_probe++; 8419 } 8420 sized: 8421 return (last_probe); 8422 } 8423 8424 void 8425 ahd_dump_all_cards_state() 8426 { 8427 struct ahd_softc *list_ahd; 8428 8429 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) { 8430 ahd_dump_card_state(list_ahd); 8431 } 8432 } 8433 8434 int 8435 ahd_print_register(ahd_reg_parse_entry_t *table, u_int num_entries, 8436 const char *name, u_int address, u_int value, 8437 u_int *cur_column, u_int wrap_point) 8438 { 8439 int printed; 8440 u_int printed_mask; 8441 8442 if (cur_column != NULL && *cur_column >= wrap_point) { 8443 printf("\n"); 8444 *cur_column = 0; 8445 } 8446 printed = printf("%s[0x%x]", name, value); 8447 if (table == NULL) { 8448 printed += printf(" "); 8449 *cur_column += printed; 8450 return (printed); 8451 } 8452 printed_mask = 0; 8453 while (printed_mask != 0xFF) { 8454 int entry; 8455 8456 for (entry = 0; entry < num_entries; entry++) { 8457 if (((value & table[entry].mask) 8458 != table[entry].value) 8459 || ((printed_mask & table[entry].mask) 8460 == table[entry].mask)) 8461 continue; 8462 8463 printed += printf("%s%s", 8464 printed_mask == 0 ? ":(" : "|", 8465 table[entry].name); 8466 printed_mask |= table[entry].mask; 8467 8468 break; 8469 } 8470 if (entry >= num_entries) 8471 break; 8472 } 8473 if (printed_mask != 0) 8474 printed += printf(") "); 8475 else 8476 printed += printf(" "); 8477 if (cur_column != NULL) 8478 *cur_column += printed; 8479 return (printed); 8480 } 8481 8482 void 8483 ahd_dump_card_state(struct ahd_softc *ahd) 8484 { 8485 struct scb *scb; 8486 ahd_mode_state saved_modes; 8487 u_int dffstat; 8488 int paused; 8489 u_int scb_index; 8490 u_int saved_scb_index; 8491 u_int cur_col; 8492 int i; 8493 8494 if (ahd_is_paused(ahd)) { 8495 paused = 1; 8496 } else { 8497 paused = 0; 8498 ahd_pause(ahd); 8499 } 8500 saved_modes = ahd_save_modes(ahd); 8501 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 8502 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 8503 "%s: Dumping Card State at program address 0x%x Mode 0x%x\n", 8504 ahd_name(ahd), 8505 ahd_inb(ahd, CURADDR) | (ahd_inb(ahd, CURADDR+1) << 8), 8506 ahd_build_mode_state(ahd, ahd->saved_src_mode, 8507 ahd->saved_dst_mode)); 8508 if (paused) 8509 printf("Card was paused\n"); 8510 /* 8511 * Mode independent registers. 8512 */ 8513 cur_col = 0; 8514 ahd_hs_mailbox_print(ahd_inb(ahd, LOCAL_HS_MAILBOX), &cur_col, 50); 8515 ahd_intctl_print(ahd_inb(ahd, INTCTL), &cur_col, 50); 8516 ahd_seqintstat_print(ahd_inb(ahd, SEQINTSTAT), &cur_col, 50); 8517 ahd_saved_mode_print(ahd_inb(ahd, SAVED_MODE), &cur_col, 50); 8518 ahd_dffstat_print(ahd_inb(ahd, DFFSTAT), &cur_col, 50); 8519 ahd_scsisigi_print(ahd_inb(ahd, SCSISIGI), &cur_col, 50); 8520 ahd_scsiphase_print(ahd_inb(ahd, SCSIPHASE), &cur_col, 50); 8521 ahd_scsibus_print(ahd_inb(ahd, SCSIBUS), &cur_col, 50); 8522 ahd_lastphase_print(ahd_inb(ahd, LASTPHASE), &cur_col, 50); 8523 ahd_scsiseq0_print(ahd_inb(ahd, SCSISEQ0), &cur_col, 50); 8524 ahd_scsiseq1_print(ahd_inb(ahd, SCSISEQ1), &cur_col, 50); 8525 ahd_seqctl0_print(ahd_inb(ahd, SEQCTL0), &cur_col, 50); 8526 ahd_seqintctl_print(ahd_inb(ahd, SEQINTCTL), &cur_col, 50); 8527 ahd_seq_flags_print(ahd_inb(ahd, SEQ_FLAGS), &cur_col, 50); 8528 ahd_seq_flags2_print(ahd_inb(ahd, SEQ_FLAGS2), &cur_col, 50); 8529 ahd_sstat0_print(ahd_inb(ahd, SSTAT0), &cur_col, 50); 8530 ahd_sstat1_print(ahd_inb(ahd, SSTAT1), &cur_col, 50); 8531 ahd_sstat2_print(ahd_inb(ahd, SSTAT2), &cur_col, 50); 8532 ahd_sstat3_print(ahd_inb(ahd, SSTAT3), &cur_col, 50); 8533 ahd_perrdiag_print(ahd_inb(ahd, PERRDIAG), &cur_col, 50); 8534 ahd_simode1_print(ahd_inb(ahd, SIMODE1), &cur_col, 50); 8535 ahd_lqistat0_print(ahd_inb(ahd, LQISTAT0), &cur_col, 50); 8536 ahd_lqistat1_print(ahd_inb(ahd, LQISTAT1), &cur_col, 50); 8537 ahd_lqistat2_print(ahd_inb(ahd, LQISTAT2), &cur_col, 50); 8538 ahd_lqostat0_print(ahd_inb(ahd, LQOSTAT0), &cur_col, 50); 8539 ahd_lqostat1_print(ahd_inb(ahd, LQOSTAT1), &cur_col, 50); 8540 ahd_lqostat2_print(ahd_inb(ahd, LQOSTAT2), &cur_col, 50); 8541 printf("\n"); 8542 printf("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x " 8543 "CURRSCB 0x%x NEXTSCB 0x%x\n", 8544 ahd->scb_data.numscbs, ahd_inw(ahd, CMDS_PENDING), 8545 ahd_inw(ahd, LASTSCB), ahd_inw(ahd, CURRSCB), 8546 ahd_inw(ahd, NEXTSCB)); 8547 cur_col = 0; 8548 /* QINFIFO */ 8549 ahd_search_qinfifo(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, 8550 CAM_LUN_WILDCARD, SCB_LIST_NULL, 8551 ROLE_UNKNOWN, /*status*/0, SEARCH_PRINT); 8552 saved_scb_index = ahd_get_scbptr(ahd); 8553 printf("Pending list:"); 8554 i = 0; 8555 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 8556 if (i++ > AHD_SCB_MAX) 8557 break; 8558 cur_col = printf("\n%3d ", SCB_GET_TAG(scb)); 8559 ahd_set_scbptr(ahd, SCB_GET_TAG(scb)); 8560 ahd_scb_control_print(ahd_inb(ahd, SCB_CONTROL), &cur_col, 60); 8561 ahd_scb_scsiid_print(ahd_inb(ahd, SCB_SCSIID), &cur_col, 60); 8562 ahd_scb_tag_print(ahd_inb(ahd, SCB_TAG), &cur_col, 60); 8563 } 8564 printf("\nTotal %d\n", i); 8565 8566 printf("Kernel Free SCB list: "); 8567 i = 0; 8568 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 8569 struct scb *list_scb; 8570 8571 list_scb = scb; 8572 do { 8573 printf("%d ", SCB_GET_TAG(list_scb)); 8574 list_scb = LIST_NEXT(list_scb, collision_links); 8575 } while (list_scb && i++ < AHD_SCB_MAX); 8576 } 8577 8578 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { 8579 if (i++ > AHD_SCB_MAX) 8580 break; 8581 printf("%d ", SCB_GET_TAG(scb)); 8582 } 8583 printf("\n"); 8584 8585 printf("Sequencer Complete DMA-inprog list: "); 8586 scb_index = ahd_inw(ahd, COMPLETE_SCB_DMAINPROG_HEAD); 8587 i = 0; 8588 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8589 ahd_set_scbptr(ahd, scb_index); 8590 printf("%d ", scb_index); 8591 scb_index = ahd_inw(ahd, SCB_NEXT_COMPLETE); 8592 } 8593 printf("\n"); 8594 8595 printf("Sequencer Complete list: "); 8596 scb_index = ahd_inw(ahd, COMPLETE_SCB_HEAD); 8597 i = 0; 8598 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8599 ahd_set_scbptr(ahd, scb_index); 8600 printf("%d ", scb_index); 8601 scb_index = ahd_inw(ahd, SCB_NEXT_COMPLETE); 8602 } 8603 printf("\n"); 8604 8605 8606 printf("Sequencer DMA-Up and Complete list: "); 8607 scb_index = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 8608 i = 0; 8609 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8610 ahd_set_scbptr(ahd, scb_index); 8611 printf("%d ", scb_index); 8612 scb_index = ahd_inw(ahd, SCB_NEXT_COMPLETE); 8613 } 8614 printf("\n"); 8615 ahd_set_scbptr(ahd, saved_scb_index); 8616 dffstat = ahd_inb(ahd, DFFSTAT); 8617 for (i = 0; i < 2; i++) { 8618 #ifdef AHD_DEBUG 8619 struct scb *fifo_scb; 8620 #endif 8621 u_int fifo_scbptr; 8622 8623 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); 8624 fifo_scbptr = ahd_get_scbptr(ahd); 8625 printf("\n%s: FIFO%d %s, LONGJMP == 0x%x, " 8626 "SCB 0x%x, LJSCB 0x%x\n", 8627 ahd_name(ahd), i, 8628 (dffstat & (FIFO0FREE << i)) ? "Free" : "Active", 8629 ahd_inw(ahd, LONGJMP_ADDR), fifo_scbptr, 8630 ahd_inw(ahd, LONGJMP_SCB)); 8631 cur_col = 0; 8632 ahd_seqimode_print(ahd_inb(ahd, SEQIMODE), &cur_col, 50); 8633 ahd_seqintsrc_print(ahd_inb(ahd, SEQINTSRC), &cur_col, 50); 8634 ahd_dfcntrl_print(ahd_inb(ahd, DFCNTRL), &cur_col, 50); 8635 ahd_dfstatus_print(ahd_inb(ahd, DFSTATUS), &cur_col, 50); 8636 ahd_sg_cache_shadow_print(ahd_inb(ahd, SG_CACHE_SHADOW), 8637 &cur_col, 50); 8638 ahd_sg_state_print(ahd_inb(ahd, SG_STATE), &cur_col, 50); 8639 ahd_dffsxfrctl_print(ahd_inb(ahd, DFFSXFRCTL), &cur_col, 50); 8640 ahd_soffcnt_print(ahd_inb(ahd, SOFFCNT), &cur_col, 50); 8641 ahd_mdffstat_print(ahd_inb(ahd, MDFFSTAT), &cur_col, 50); 8642 if (cur_col > 50) { 8643 printf("\n"); 8644 cur_col = 0; 8645 } 8646 cur_col += printf("SHADDR = 0x%x%x, SHCNT = 0x%x ", 8647 ahd_inl(ahd, SHADDR+4), 8648 ahd_inl(ahd, SHADDR), 8649 (ahd_inb(ahd, SHCNT) 8650 | (ahd_inb(ahd, SHCNT + 1) << 8) 8651 | (ahd_inb(ahd, SHCNT + 2) << 16))); 8652 if (cur_col > 50) { 8653 printf("\n"); 8654 cur_col = 0; 8655 } 8656 cur_col += printf("HADDR = 0x%x%x, HCNT = 0x%x ", 8657 ahd_inl(ahd, HADDR+4), 8658 ahd_inl(ahd, HADDR), 8659 (ahd_inb(ahd, HCNT) 8660 | (ahd_inb(ahd, HCNT + 1) << 8) 8661 | (ahd_inb(ahd, HCNT + 2) << 16))); 8662 ahd_ccsgctl_print(ahd_inb(ahd, CCSGCTL), &cur_col, 50); 8663 #ifdef AHD_DEBUG 8664 if ((ahd_debug & AHD_SHOW_SG) != 0) { 8665 fifo_scb = ahd_lookup_scb(ahd, fifo_scbptr); 8666 if (fifo_scb != NULL) 8667 ahd_dump_sglist(fifo_scb); 8668 } 8669 #endif 8670 } 8671 printf("\nLQIN: "); 8672 for (i = 0; i < 20; i++) 8673 printf("0x%x ", ahd_inb(ahd, LQIN + i)); 8674 printf("\n"); 8675 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 8676 printf("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n", 8677 ahd_name(ahd), ahd_inb(ahd, LQISTATE), ahd_inb(ahd, LQOSTATE), 8678 ahd_inb(ahd, OPTIONMODE)); 8679 printf("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n", 8680 ahd_name(ahd), ahd_inb(ahd, OS_SPACE_CNT), 8681 ahd_inb(ahd, MAXCMDCNT)); 8682 ahd_simode0_print(ahd_inb(ahd, SIMODE0), &cur_col, 50); 8683 printf("\n"); 8684 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 8685 cur_col = 0; 8686 ahd_ccscbctl_print(ahd_inb(ahd, CCSCBCTL), &cur_col, 50); 8687 printf("\n"); 8688 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 8689 printf("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n", 8690 ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX), 8691 ahd_inw(ahd, DINDEX)); 8692 printf("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n", 8693 ahd_name(ahd), ahd_get_scbptr(ahd), ahd_inw(ahd, SCB_NEXT), 8694 ahd_inw(ahd, SCB_NEXT2)); 8695 printf("CDB %x %x %x %x %x %x\n", 8696 ahd_inb(ahd, SCB_CDB_STORE), 8697 ahd_inb(ahd, SCB_CDB_STORE+1), 8698 ahd_inb(ahd, SCB_CDB_STORE+2), 8699 ahd_inb(ahd, SCB_CDB_STORE+3), 8700 ahd_inb(ahd, SCB_CDB_STORE+4), 8701 ahd_inb(ahd, SCB_CDB_STORE+5)); 8702 printf("STACK:"); 8703 for (i = 0; i < ahd->stack_size; i++) { 8704 ahd->saved_stack[i] = 8705 ahd_inb(ahd, STACK)|(ahd_inb(ahd, STACK) << 8); 8706 printf(" 0x%x", ahd->saved_stack[i]); 8707 } 8708 for (i = ahd->stack_size-1; i >= 0; i--) { 8709 ahd_outb(ahd, STACK, ahd->saved_stack[i] & 0xFF); 8710 ahd_outb(ahd, STACK, (ahd->saved_stack[i] >> 8) & 0xFF); 8711 } 8712 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 8713 ahd_platform_dump_card_state(ahd); 8714 ahd_restore_modes(ahd, saved_modes); 8715 if (paused == 0) 8716 ahd_unpause(ahd); 8717 } 8718 8719 void 8720 ahd_dump_scbs(struct ahd_softc *ahd) 8721 { 8722 ahd_mode_state saved_modes; 8723 u_int saved_scb_index; 8724 int i; 8725 8726 saved_modes = ahd_save_modes(ahd); 8727 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 8728 saved_scb_index = ahd_get_scbptr(ahd); 8729 for (i = 0; i < AHD_SCB_MAX; i++) { 8730 ahd_set_scbptr(ahd, i); 8731 printf("%3d", i); 8732 printf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n", 8733 ahd_inb(ahd, SCB_CONTROL), 8734 ahd_inb(ahd, SCB_SCSIID), ahd_inw(ahd, SCB_NEXT), 8735 ahd_inw(ahd, SCB_NEXT2), ahd_inl(ahd, SCB_SGPTR), 8736 ahd_inl(ahd, SCB_RESIDUAL_SGPTR)); 8737 } 8738 printf("\n"); 8739 ahd_set_scbptr(ahd, saved_scb_index); 8740 ahd_restore_modes(ahd, saved_modes); 8741 } 8742 8743 /**************************** Flexport Logic **********************************/ 8744 /* 8745 * Read count 16bit words from 16bit word address start_addr from the 8746 * SEEPROM attached to the controller, into buf, using the controller's 8747 * SEEPROM reading state machine. 8748 */ 8749 int 8750 ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 8751 u_int start_addr, u_int count) 8752 { 8753 u_int cur_addr; 8754 u_int end_addr; 8755 int error; 8756 8757 /* 8758 * If we never make it through the loop even once, 8759 * we were passed invalid arguments. 8760 */ 8761 error = EINVAL; 8762 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8763 end_addr = start_addr + count; 8764 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { 8765 ahd_outb(ahd, SEEADR, cur_addr); 8766 ahd_outb(ahd, SEECTL, SEEOP_READ | SEESTART); 8767 8768 error = ahd_wait_seeprom(ahd); 8769 if (error) 8770 break; 8771 *buf++ = ahd_inw(ahd, SEEDAT); 8772 } 8773 return (error); 8774 } 8775 8776 /* 8777 * Write count 16bit words from buf, into SEEPROM attache to the 8778 * controller starting at 16bit word address start_addr, using the 8779 * controller's SEEPROM writing state machine. 8780 */ 8781 int 8782 ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 8783 u_int start_addr, u_int count) 8784 { 8785 u_int cur_addr; 8786 u_int end_addr; 8787 int error; 8788 int retval; 8789 8790 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8791 error = ENOENT; 8792 8793 /* Place the chip into write-enable mode */ 8794 ahd_outb(ahd, SEEADR, SEEOP_EWEN_ADDR); 8795 ahd_outb(ahd, SEECTL, SEEOP_EWEN | SEESTART); 8796 error = ahd_wait_seeprom(ahd); 8797 if (error) 8798 return (error); 8799 8800 /* 8801 * Write the data. If we don't get throught the loop at 8802 * least once, the arguments were invalid. 8803 */ 8804 retval = EINVAL; 8805 end_addr = start_addr + count; 8806 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { 8807 ahd_outw(ahd, SEEDAT, *buf++); 8808 ahd_outb(ahd, SEEADR, cur_addr); 8809 ahd_outb(ahd, SEECTL, SEEOP_WRITE | SEESTART); 8810 8811 retval = ahd_wait_seeprom(ahd); 8812 if (retval) 8813 break; 8814 } 8815 8816 /* 8817 * Disable writes. 8818 */ 8819 ahd_outb(ahd, SEEADR, SEEOP_EWDS_ADDR); 8820 ahd_outb(ahd, SEECTL, SEEOP_EWDS | SEESTART); 8821 error = ahd_wait_seeprom(ahd); 8822 if (error) 8823 return (error); 8824 return (retval); 8825 } 8826 8827 /* 8828 * Wait ~100us for the serial eeprom to satisfy our request. 8829 */ 8830 int 8831 ahd_wait_seeprom(struct ahd_softc *ahd) 8832 { 8833 int cnt; 8834 8835 cnt = 20; 8836 while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt) 8837 ahd_delay(5); 8838 8839 if (cnt == 0) 8840 return (ETIMEDOUT); 8841 return (0); 8842 } 8843 8844 int 8845 ahd_verify_cksum(struct seeprom_config *sc) 8846 { 8847 int i; 8848 int maxaddr; 8849 uint32_t checksum; 8850 uint16_t *scarray; 8851 8852 maxaddr = (sizeof(*sc)/2) - 1; 8853 checksum = 0; 8854 scarray = (uint16_t *)sc; 8855 8856 for (i = 0; i < maxaddr; i++) 8857 checksum = checksum + scarray[i]; 8858 if (checksum == 0 8859 || (checksum & 0xFFFF) != sc->checksum) { 8860 return (0); 8861 } else { 8862 return (1); 8863 } 8864 } 8865 8866 int 8867 ahd_acquire_seeprom(struct ahd_softc *ahd) 8868 { 8869 /* 8870 * We should be able to determine the SEEPROM type 8871 * from the flexport logic, but unfortunately not 8872 * all implementations have this logic and there is 8873 * no programatic method for determining if the logic 8874 * is present. 8875 */ 8876 return (1); 8877 #if 0 8878 uint8_t seetype; 8879 int error; 8880 8881 error = ahd_read_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, &seetype); 8882 if (error != 0 8883 || ((seetype & FLX_ROMSTAT_SEECFG) == FLX_ROMSTAT_SEE_NONE)) 8884 return (0); 8885 return (1); 8886 #endif 8887 } 8888 8889 void 8890 ahd_release_seeprom(struct ahd_softc *ahd) 8891 { 8892 /* Currently a no-op */ 8893 } 8894 8895 int 8896 ahd_write_flexport(struct ahd_softc *ahd, u_int addr, u_int value) 8897 { 8898 int error; 8899 8900 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8901 if (addr > 7) 8902 panic("ahd_write_flexport: address out of range"); 8903 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); 8904 error = ahd_wait_flexport(ahd); 8905 if (error != 0) 8906 return (error); 8907 ahd_outb(ahd, BRDDAT, value); 8908 ahd_flush_device_writes(ahd); 8909 ahd_outb(ahd, BRDCTL, BRDSTB|BRDEN|(addr << 3)); 8910 ahd_flush_device_writes(ahd); 8911 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); 8912 ahd_flush_device_writes(ahd); 8913 ahd_outb(ahd, BRDCTL, 0); 8914 ahd_flush_device_writes(ahd); 8915 return (0); 8916 } 8917 8918 int 8919 ahd_read_flexport(struct ahd_softc *ahd, u_int addr, uint8_t *value) 8920 { 8921 int error; 8922 8923 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8924 if (addr > 7) 8925 panic("ahd_read_flexport: address out of range"); 8926 ahd_outb(ahd, BRDCTL, BRDRW|BRDEN|(addr << 3)); 8927 error = ahd_wait_flexport(ahd); 8928 if (error != 0) 8929 return (error); 8930 *value = ahd_inb(ahd, BRDDAT); 8931 ahd_outb(ahd, BRDCTL, 0); 8932 ahd_flush_device_writes(ahd); 8933 return (0); 8934 } 8935 8936 /* 8937 * Wait at most 2 seconds for flexport arbitration to succeed. 8938 */ 8939 int 8940 ahd_wait_flexport(struct ahd_softc *ahd) 8941 { 8942 int cnt; 8943 8944 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 8945 cnt = 1000000 * 2 / 5; 8946 while ((ahd_inb(ahd, BRDCTL) & FLXARBACK) == 0 && --cnt) 8947 ahd_delay(5); 8948 8949 if (cnt == 0) 8950 return (ETIMEDOUT); 8951 return (0); 8952 } 8953 8954 /************************* Target Mode ****************************************/ 8955 #ifdef AHD_TARGET_MODE 8956 cam_status 8957 ahd_find_tmode_devs(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb, 8958 struct ahd_tmode_tstate **tstate, 8959 struct ahd_tmode_lstate **lstate, 8960 int notfound_failure) 8961 { 8962 8963 if ((ahd->features & AHD_TARGETMODE) == 0) 8964 return (CAM_REQ_INVALID); 8965 8966 /* 8967 * Handle the 'black hole' device that sucks up 8968 * requests to unattached luns on enabled targets. 8969 */ 8970 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 8971 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 8972 *tstate = NULL; 8973 *lstate = ahd->black_hole; 8974 } else { 8975 u_int max_id; 8976 8977 max_id = (ahd->features & AHD_WIDE) ? 15 : 7; 8978 if (ccb->ccb_h.target_id > max_id) 8979 return (CAM_TID_INVALID); 8980 8981 if (ccb->ccb_h.target_lun >= AHD_NUM_LUNS) 8982 return (CAM_LUN_INVALID); 8983 8984 *tstate = ahd->enabled_targets[ccb->ccb_h.target_id]; 8985 *lstate = NULL; 8986 if (*tstate != NULL) 8987 *lstate = 8988 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 8989 } 8990 8991 if (notfound_failure != 0 && *lstate == NULL) 8992 return (CAM_PATH_INVALID); 8993 8994 return (CAM_REQ_CMP); 8995 } 8996 8997 void 8998 ahd_handle_en_lun(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb) 8999 { 9000 #if NOT_YET 9001 struct ahd_tmode_tstate *tstate; 9002 struct ahd_tmode_lstate *lstate; 9003 struct ccb_en_lun *cel; 9004 cam_status status; 9005 u_int target; 9006 u_int lun; 9007 u_int target_mask; 9008 u_long s; 9009 char channel; 9010 9011 status = ahd_find_tmode_devs(ahd, sim, ccb, &tstate, &lstate, 9012 /*notfound_failure*/FALSE); 9013 9014 if (status != CAM_REQ_CMP) { 9015 ccb->ccb_h.status = status; 9016 return; 9017 } 9018 9019 if ((ahd->features & AHD_MULTIROLE) != 0) { 9020 u_int our_id; 9021 9022 our_id = ahd->our_id; 9023 if (ccb->ccb_h.target_id != our_id) { 9024 if ((ahd->features & AHD_MULTI_TID) != 0 9025 && (ahd->flags & AHD_INITIATORROLE) != 0) { 9026 /* 9027 * Only allow additional targets if 9028 * the initiator role is disabled. 9029 * The hardware cannot handle a re-select-in 9030 * on the initiator id during a re-select-out 9031 * on a different target id. 9032 */ 9033 status = CAM_TID_INVALID; 9034 } else if ((ahd->flags & AHD_INITIATORROLE) != 0 9035 || ahd->enabled_luns > 0) { 9036 /* 9037 * Only allow our target id to change 9038 * if the initiator role is not configured 9039 * and there are no enabled luns which 9040 * are attached to the currently registered 9041 * scsi id. 9042 */ 9043 status = CAM_TID_INVALID; 9044 } 9045 } 9046 } 9047 9048 if (status != CAM_REQ_CMP) { 9049 ccb->ccb_h.status = status; 9050 return; 9051 } 9052 9053 /* 9054 * We now have an id that is valid. 9055 * If we aren't in target mode, switch modes. 9056 */ 9057 if ((ahd->flags & AHD_TARGETROLE) == 0 9058 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 9059 u_long s; 9060 9061 printf("Configuring Target Mode\n"); 9062 ahd_lock(ahd, &s); 9063 if (LIST_FIRST(&ahd->pending_scbs) != NULL) { 9064 ccb->ccb_h.status = CAM_BUSY; 9065 ahd_unlock(ahd, &s); 9066 return; 9067 } 9068 ahd->flags |= AHD_TARGETROLE; 9069 if ((ahd->features & AHD_MULTIROLE) == 0) 9070 ahd->flags &= ~AHD_INITIATORROLE; 9071 ahd_pause(ahd); 9072 ahd_loadseq(ahd); 9073 ahd_unlock(ahd, &s); 9074 } 9075 cel = &ccb->cel; 9076 target = ccb->ccb_h.target_id; 9077 lun = ccb->ccb_h.target_lun; 9078 channel = SIM_CHANNEL(ahd, sim); 9079 target_mask = 0x01 << target; 9080 if (channel == 'B') 9081 target_mask <<= 8; 9082 9083 if (cel->enable != 0) { 9084 u_int scsiseq1; 9085 9086 /* Are we already enabled?? */ 9087 if (lstate != NULL) { 9088 xpt_print_path(ccb->ccb_h.path); 9089 printf("Lun already enabled\n"); 9090 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 9091 return; 9092 } 9093 9094 if (cel->grp6_len != 0 9095 || cel->grp7_len != 0) { 9096 /* 9097 * Don't (yet?) support vendor 9098 * specific commands. 9099 */ 9100 ccb->ccb_h.status = CAM_REQ_INVALID; 9101 printf("Non-zero Group Codes\n"); 9102 return; 9103 } 9104 9105 /* 9106 * Seems to be okay. 9107 * Setup our data structures. 9108 */ 9109 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 9110 tstate = ahd_alloc_tstate(ahd, target, channel); 9111 if (tstate == NULL) { 9112 xpt_print_path(ccb->ccb_h.path); 9113 printf("Couldn't allocate tstate\n"); 9114 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9115 return; 9116 } 9117 } 9118 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 9119 if (lstate == NULL) { 9120 xpt_print_path(ccb->ccb_h.path); 9121 printf("Couldn't allocate lstate\n"); 9122 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9123 return; 9124 } 9125 memset(lstate, 0, sizeof(*lstate)); 9126 status = xpt_create_path(&lstate->path, /*periph*/NULL, 9127 xpt_path_path_id(ccb->ccb_h.path), 9128 xpt_path_target_id(ccb->ccb_h.path), 9129 xpt_path_lun_id(ccb->ccb_h.path)); 9130 if (status != CAM_REQ_CMP) { 9131 free(lstate, M_DEVBUF); 9132 xpt_print_path(ccb->ccb_h.path); 9133 printf("Couldn't allocate path\n"); 9134 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9135 return; 9136 } 9137 SLIST_INIT(&lstate->accept_tios); 9138 SLIST_INIT(&lstate->immed_notifies); 9139 ahd_lock(ahd, &s); 9140 ahd_pause(ahd); 9141 if (target != CAM_TARGET_WILDCARD) { 9142 tstate->enabled_luns[lun] = lstate; 9143 ahd->enabled_luns++; 9144 9145 if ((ahd->features & AHD_MULTI_TID) != 0) { 9146 u_int targid_mask; 9147 9148 targid_mask = ahd_inb(ahd, TARGID) 9149 | (ahd_inb(ahd, TARGID + 1) << 8); 9150 9151 targid_mask |= target_mask; 9152 ahd_outb(ahd, TARGID, targid_mask); 9153 ahd_outb(ahd, TARGID+1, (targid_mask >> 8)); 9154 9155 ahd_update_scsiid(ahd, targid_mask); 9156 } else { 9157 u_int our_id; 9158 char channel; 9159 9160 channel = SIM_CHANNEL(ahd, sim); 9161 our_id = SIM_SCSI_ID(ahd, sim); 9162 9163 /* 9164 * This can only happen if selections 9165 * are not enabled 9166 */ 9167 if (target != our_id) { 9168 u_int sblkctl; 9169 char cur_channel; 9170 int swap; 9171 9172 sblkctl = ahd_inb(ahd, SBLKCTL); 9173 cur_channel = (sblkctl & SELBUSB) 9174 ? 'B' : 'A'; 9175 if ((ahd->features & AHD_TWIN) == 0) 9176 cur_channel = 'A'; 9177 swap = cur_channel != channel; 9178 ahd->our_id = target; 9179 9180 if (swap) 9181 ahd_outb(ahd, SBLKCTL, 9182 sblkctl ^ SELBUSB); 9183 9184 ahd_outb(ahd, SCSIID, target); 9185 9186 if (swap) 9187 ahd_outb(ahd, SBLKCTL, sblkctl); 9188 } 9189 } 9190 } else 9191 ahd->black_hole = lstate; 9192 /* Allow select-in operations */ 9193 if (ahd->black_hole != NULL && ahd->enabled_luns > 0) { 9194 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 9195 scsiseq1 |= ENSELI; 9196 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); 9197 scsiseq1 = ahd_inb(ahd, SCSISEQ1); 9198 scsiseq1 |= ENSELI; 9199 ahd_outb(ahd, SCSISEQ1, scsiseq1); 9200 } 9201 ahd_unpause(ahd); 9202 ahd_unlock(ahd, &s); 9203 ccb->ccb_h.status = CAM_REQ_CMP; 9204 xpt_print_path(ccb->ccb_h.path); 9205 printf("Lun now enabled for target mode\n"); 9206 } else { 9207 struct scb *scb; 9208 int i, empty; 9209 9210 if (lstate == NULL) { 9211 ccb->ccb_h.status = CAM_LUN_INVALID; 9212 return; 9213 } 9214 9215 ahd_lock(ahd, &s); 9216 9217 ccb->ccb_h.status = CAM_REQ_CMP; 9218 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 9219 struct ccb_hdr *ccbh; 9220 9221 ccbh = &scb->io_ctx->ccb_h; 9222 if (ccbh->func_code == XPT_CONT_TARGET_IO 9223 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 9224 printf("CTIO pending\n"); 9225 ccb->ccb_h.status = CAM_REQ_INVALID; 9226 ahd_unlock(ahd, &s); 9227 return; 9228 } 9229 } 9230 9231 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 9232 printf("ATIOs pending\n"); 9233 ccb->ccb_h.status = CAM_REQ_INVALID; 9234 } 9235 9236 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 9237 printf("INOTs pending\n"); 9238 ccb->ccb_h.status = CAM_REQ_INVALID; 9239 } 9240 9241 if (ccb->ccb_h.status != CAM_REQ_CMP) { 9242 ahd_unlock(ahd, &s); 9243 return; 9244 } 9245 9246 xpt_print_path(ccb->ccb_h.path); 9247 printf("Target mode disabled\n"); 9248 xpt_free_path(lstate->path); 9249 free(lstate, M_DEVBUF); 9250 9251 ahd_pause(ahd); 9252 /* Can we clean up the target too? */ 9253 if (target != CAM_TARGET_WILDCARD) { 9254 tstate->enabled_luns[lun] = NULL; 9255 ahd->enabled_luns--; 9256 for (empty = 1, i = 0; i < 8; i++) 9257 if (tstate->enabled_luns[i] != NULL) { 9258 empty = 0; 9259 break; 9260 } 9261 9262 if (empty) { 9263 ahd_free_tstate(ahd, target, channel, 9264 /*force*/FALSE); 9265 if (ahd->features & AHD_MULTI_TID) { 9266 u_int targid_mask; 9267 9268 targid_mask = ahd_inb(ahd, TARGID) 9269 | (ahd_inb(ahd, TARGID + 1) 9270 << 8); 9271 9272 targid_mask &= ~target_mask; 9273 ahd_outb(ahd, TARGID, targid_mask); 9274 ahd_outb(ahd, TARGID+1, 9275 (targid_mask >> 8)); 9276 ahd_update_scsiid(ahd, targid_mask); 9277 } 9278 } 9279 } else { 9280 9281 ahd->black_hole = NULL; 9282 9283 /* 9284 * We can't allow selections without 9285 * our black hole device. 9286 */ 9287 empty = TRUE; 9288 } 9289 if (ahd->enabled_luns == 0) { 9290 /* Disallow select-in */ 9291 u_int scsiseq1; 9292 9293 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 9294 scsiseq1 &= ~ENSELI; 9295 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); 9296 scsiseq1 = ahd_inb(ahd, SCSISEQ1); 9297 scsiseq1 &= ~ENSELI; 9298 ahd_outb(ahd, SCSISEQ1, scsiseq1); 9299 9300 if ((ahd->features & AHD_MULTIROLE) == 0) { 9301 printf("Configuring Initiator Mode\n"); 9302 ahd->flags &= ~AHD_TARGETROLE; 9303 ahd->flags |= AHD_INITIATORROLE; 9304 ahd_pause(ahd); 9305 ahd_loadseq(ahd); 9306 } 9307 } 9308 ahd_unpause(ahd); 9309 ahd_unlock(ahd, &s); 9310 } 9311 #endif 9312 } 9313 9314 static void 9315 ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask) 9316 { 9317 #if NOT_YET 9318 u_int scsiid_mask; 9319 u_int scsiid; 9320 9321 if ((ahd->features & AHD_MULTI_TID) == 0) 9322 panic("ahd_update_scsiid called on non-multitid unit\n"); 9323 9324 /* 9325 * Since we will rely on the TARGID mask 9326 * for selection enables, ensure that OID 9327 * in SCSIID is not set to some other ID 9328 * that we don't want to allow selections on. 9329 */ 9330 if ((ahd->features & AHD_ULTRA2) != 0) 9331 scsiid = ahd_inb(ahd, SCSIID_ULTRA2); 9332 else 9333 scsiid = ahd_inb(ahd, SCSIID); 9334 scsiid_mask = 0x1 << (scsiid & OID); 9335 if ((targid_mask & scsiid_mask) == 0) { 9336 u_int our_id; 9337 9338 /* ffs counts from 1 */ 9339 our_id = ffs(targid_mask); 9340 if (our_id == 0) 9341 our_id = ahd->our_id; 9342 else 9343 our_id--; 9344 scsiid &= TID; 9345 scsiid |= our_id; 9346 } 9347 if ((ahd->features & AHD_ULTRA2) != 0) 9348 ahd_outb(ahd, SCSIID_ULTRA2, scsiid); 9349 else 9350 ahd_outb(ahd, SCSIID, scsiid); 9351 #endif 9352 } 9353 9354 void 9355 ahd_run_tqinfifo(struct ahd_softc *ahd, int paused) 9356 { 9357 struct target_cmd *cmd; 9358 9359 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_POSTREAD); 9360 while ((cmd = &ahd->targetcmds[ahd->tqinfifonext])->cmd_valid != 0) { 9361 9362 /* 9363 * Only advance through the queue if we 9364 * have the resources to process the command. 9365 */ 9366 if (ahd_handle_target_cmd(ahd, cmd) != 0) 9367 break; 9368 9369 cmd->cmd_valid = 0; 9370 ahd_dmamap_sync(ahd, ahd->shared_data_dmat, 9371 ahd->shared_data_dmamap, 9372 ahd_targetcmd_offset(ahd, ahd->tqinfifonext), 9373 sizeof(struct target_cmd), 9374 BUS_DMASYNC_PREREAD); 9375 ahd->tqinfifonext++; 9376 9377 /* 9378 * Lazily update our position in the target mode incoming 9379 * command queue as seen by the sequencer. 9380 */ 9381 if ((ahd->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 9382 u_int hs_mailbox; 9383 9384 hs_mailbox = ahd_inb(ahd, HS_MAILBOX); 9385 hs_mailbox &= ~HOST_TQINPOS; 9386 hs_mailbox |= ahd->tqinfifonext & HOST_TQINPOS; 9387 ahd_outb(ahd, HS_MAILBOX, hs_mailbox); 9388 } 9389 } 9390 } 9391 9392 static int 9393 ahd_handle_target_cmd(struct ahd_softc *ahd, struct target_cmd *cmd) 9394 { 9395 struct ahd_tmode_tstate *tstate; 9396 struct ahd_tmode_lstate *lstate; 9397 struct ccb_accept_tio *atio; 9398 uint8_t *byte; 9399 int initiator; 9400 int target; 9401 int lun; 9402 9403 initiator = SCSIID_TARGET(ahd, cmd->scsiid); 9404 target = SCSIID_OUR_ID(cmd->scsiid); 9405 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 9406 9407 byte = cmd->bytes; 9408 tstate = ahd->enabled_targets[target]; 9409 lstate = NULL; 9410 if (tstate != NULL) 9411 lstate = tstate->enabled_luns[lun]; 9412 9413 /* 9414 * Commands for disabled luns go to the black hole driver. 9415 */ 9416 if (lstate == NULL) 9417 lstate = ahd->black_hole; 9418 9419 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 9420 if (atio == NULL) { 9421 ahd->flags |= AHD_TQINFIFO_BLOCKED; 9422 /* 9423 * Wait for more ATIOs from the peripheral driver for this lun. 9424 */ 9425 return (1); 9426 } else 9427 ahd->flags &= ~AHD_TQINFIFO_BLOCKED; 9428 #ifdef AHD_DEBUG 9429 if ((ahd_debug & AHD_SHOW_TQIN) != 0) 9430 printf("Incoming command from %d for %d:%d%s\n", 9431 initiator, target, lun, 9432 lstate == ahd->black_hole ? "(Black Holed)" : ""); 9433 #endif 9434 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 9435 9436 if (lstate == ahd->black_hole) { 9437 /* Fill in the wildcards */ 9438 atio->ccb_h.target_id = target; 9439 atio->ccb_h.target_lun = lun; 9440 } 9441 9442 /* 9443 * Package it up and send it off to 9444 * whomever has this lun enabled. 9445 */ 9446 atio->sense_len = 0; 9447 atio->init_id = initiator; 9448 if (byte[0] != 0xFF) { 9449 /* Tag was included */ 9450 atio->tag_action = *byte++; 9451 atio->tag_id = *byte++; 9452 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 9453 } else { 9454 atio->ccb_h.flags = 0; 9455 } 9456 byte++; 9457 9458 /* Okay. Now determine the cdb size based on the command code */ 9459 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 9460 case 0: 9461 atio->cdb_len = 6; 9462 break; 9463 case 1: 9464 case 2: 9465 atio->cdb_len = 10; 9466 break; 9467 case 4: 9468 atio->cdb_len = 16; 9469 break; 9470 case 5: 9471 atio->cdb_len = 12; 9472 break; 9473 case 3: 9474 default: 9475 /* Only copy the opcode. */ 9476 atio->cdb_len = 1; 9477 printf("Reserved or VU command code type encountered\n"); 9478 break; 9479 } 9480 9481 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 9482 9483 atio->ccb_h.status |= CAM_CDB_RECVD; 9484 9485 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 9486 /* 9487 * We weren't allowed to disconnect. 9488 * We're hanging on the bus until a 9489 * continue target I/O comes in response 9490 * to this accept tio. 9491 */ 9492 #ifdef AHD_DEBUG 9493 if ((ahd_debug & AHD_SHOW_TQIN) != 0) 9494 printf("Received Immediate Command %d:%d:%d - %p\n", 9495 initiator, target, lun, ahd->pending_device); 9496 #endif 9497 ahd->pending_device = lstate; 9498 ahd_freeze_ccb((union ccb *)atio); 9499 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 9500 } 9501 xpt_done((union ccb*)atio); 9502 return (0); 9503 } 9504 9505 #endif 9506