1 /* 2 * Core routines and tables shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2002 Justin T. Gibbs. 5 * Copyright (c) 2000-2003 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.c#246 $ 41 */ 42 43 #ifdef __linux__ 44 #include "aic79xx_osm.h" 45 #include "aic79xx_inline.h" 46 #include "aicasm/aicasm_insformat.h" 47 #else 48 #include <sys/cdefs.h> 49 __FBSDID("$FreeBSD$"); 50 #include <dev/aic7xxx/aic79xx_osm.h> 51 #include <dev/aic7xxx/aic79xx_inline.h> 52 #include <dev/aic7xxx/aicasm/aicasm_insformat.h> 53 #endif 54 55 /******************************** Globals *************************************/ 56 struct ahd_softc_tailq ahd_tailq = TAILQ_HEAD_INITIALIZER(ahd_tailq); 57 uint32_t ahd_attach_to_HostRAID_controllers = 1; 58 59 /***************************** Lookup Tables **********************************/ 60 char *ahd_chip_names[] = 61 { 62 "NONE", 63 "aic7901", 64 "aic7902", 65 "aic7901A" 66 }; 67 static const u_int num_chip_names = NUM_ELEMENTS(ahd_chip_names); 68 69 /* 70 * Hardware error codes. 71 */ 72 struct ahd_hard_error_entry { 73 uint8_t errno; 74 char *errmesg; 75 }; 76 77 static struct ahd_hard_error_entry ahd_hard_errors[] = { 78 { DSCTMOUT, "Discard Timer has timed out" }, 79 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 80 { SQPARERR, "Sequencer Parity Error" }, 81 { DPARERR, "Data-path Parity Error" }, 82 { MPARERR, "Scratch or SCB Memory Parity Error" }, 83 { CIOPARERR, "CIOBUS Parity Error" }, 84 }; 85 static const u_int num_errors = NUM_ELEMENTS(ahd_hard_errors); 86 87 static struct ahd_phase_table_entry ahd_phase_table[] = 88 { 89 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 90 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 91 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 92 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 93 { P_COMMAND, MSG_NOOP, "in Command phase" }, 94 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 95 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 96 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 97 { P_BUSFREE, MSG_NOOP, "while idle" }, 98 { 0, MSG_NOOP, "in unknown phase" } 99 }; 100 101 /* 102 * In most cases we only wish to itterate over real phases, so 103 * exclude the last element from the count. 104 */ 105 static const u_int num_phases = NUM_ELEMENTS(ahd_phase_table) - 1; 106 107 /* Our Sequencer Program */ 108 #include "aic79xx_seq.h" 109 110 /**************************** Function Declarations ***************************/ 111 static void ahd_handle_transmission_error(struct ahd_softc *ahd); 112 static void ahd_handle_lqiphase_error(struct ahd_softc *ahd, 113 u_int lqistat1); 114 static int ahd_handle_pkt_busfree(struct ahd_softc *ahd, 115 u_int busfreetime); 116 static int ahd_handle_nonpkt_busfree(struct ahd_softc *ahd); 117 static void ahd_handle_proto_violation(struct ahd_softc *ahd); 118 static void ahd_force_renegotiation(struct ahd_softc *ahd, 119 struct ahd_devinfo *devinfo); 120 121 static struct ahd_tmode_tstate* 122 ahd_alloc_tstate(struct ahd_softc *ahd, 123 u_int scsi_id, char channel); 124 #ifdef AHD_TARGET_MODE 125 static void ahd_free_tstate(struct ahd_softc *ahd, 126 u_int scsi_id, char channel, int force); 127 #endif 128 static void ahd_devlimited_syncrate(struct ahd_softc *ahd, 129 struct ahd_initiator_tinfo *, 130 u_int *period, 131 u_int *ppr_options, 132 role_t role); 133 static void ahd_update_neg_table(struct ahd_softc *ahd, 134 struct ahd_devinfo *devinfo, 135 struct ahd_transinfo *tinfo); 136 static void ahd_update_pending_scbs(struct ahd_softc *ahd); 137 static void ahd_fetch_devinfo(struct ahd_softc *ahd, 138 struct ahd_devinfo *devinfo); 139 static void ahd_scb_devinfo(struct ahd_softc *ahd, 140 struct ahd_devinfo *devinfo, 141 struct scb *scb); 142 static void ahd_setup_initiator_msgout(struct ahd_softc *ahd, 143 struct ahd_devinfo *devinfo, 144 struct scb *scb); 145 static void ahd_build_transfer_msg(struct ahd_softc *ahd, 146 struct ahd_devinfo *devinfo); 147 static void ahd_construct_sdtr(struct ahd_softc *ahd, 148 struct ahd_devinfo *devinfo, 149 u_int period, u_int offset); 150 static void ahd_construct_wdtr(struct ahd_softc *ahd, 151 struct ahd_devinfo *devinfo, 152 u_int bus_width); 153 static void ahd_construct_ppr(struct ahd_softc *ahd, 154 struct ahd_devinfo *devinfo, 155 u_int period, u_int offset, 156 u_int bus_width, u_int ppr_options); 157 static void ahd_clear_msg_state(struct ahd_softc *ahd); 158 static void ahd_handle_message_phase(struct ahd_softc *ahd); 159 typedef enum { 160 AHDMSG_1B, 161 AHDMSG_2B, 162 AHDMSG_EXT 163 } ahd_msgtype; 164 static int ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, 165 u_int msgval, int full); 166 static int ahd_parse_msg(struct ahd_softc *ahd, 167 struct ahd_devinfo *devinfo); 168 static int ahd_handle_msg_reject(struct ahd_softc *ahd, 169 struct ahd_devinfo *devinfo); 170 static void ahd_handle_ign_wide_residue(struct ahd_softc *ahd, 171 struct ahd_devinfo *devinfo); 172 static void ahd_reinitialize_dataptrs(struct ahd_softc *ahd); 173 static void ahd_handle_devreset(struct ahd_softc *ahd, 174 struct ahd_devinfo *devinfo, 175 u_int lun, cam_status status, 176 char *message, int verbose_level); 177 #if AHD_TARGET_MODE 178 static void ahd_setup_target_msgin(struct ahd_softc *ahd, 179 struct ahd_devinfo *devinfo, 180 struct scb *scb); 181 #endif 182 183 static u_int ahd_sglist_size(struct ahd_softc *ahd); 184 static u_int ahd_sglist_allocsize(struct ahd_softc *ahd); 185 static bus_dmamap_callback_t 186 ahd_dmamap_cb; 187 static void ahd_initialize_hscbs(struct ahd_softc *ahd); 188 static int ahd_init_scbdata(struct ahd_softc *ahd); 189 static void ahd_fini_scbdata(struct ahd_softc *ahd); 190 static void ahd_setup_iocell_workaround(struct ahd_softc *ahd); 191 static void ahd_iocell_first_selection(struct ahd_softc *ahd); 192 static void ahd_add_col_list(struct ahd_softc *ahd, 193 struct scb *scb, u_int col_idx); 194 static void ahd_rem_col_list(struct ahd_softc *ahd, 195 struct scb *scb); 196 static void ahd_chip_init(struct ahd_softc *ahd); 197 static void ahd_qinfifo_requeue(struct ahd_softc *ahd, 198 struct scb *prev_scb, 199 struct scb *scb); 200 static int ahd_qinfifo_count(struct ahd_softc *ahd); 201 static int ahd_search_scb_list(struct ahd_softc *ahd, int target, 202 char channel, int lun, u_int tag, 203 role_t role, uint32_t status, 204 ahd_search_action action, 205 u_int *list_head, u_int tid); 206 static void ahd_stitch_tid_list(struct ahd_softc *ahd, 207 u_int tid_prev, u_int tid_cur, 208 u_int tid_next); 209 static void ahd_add_scb_to_free_list(struct ahd_softc *ahd, 210 u_int scbid); 211 static u_int ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, 212 u_int prev, u_int next, u_int tid); 213 static void ahd_reset_current_bus(struct ahd_softc *ahd); 214 static ahd_callback_t ahd_reset_poll; 215 static ahd_callback_t ahd_stat_timer; 216 #ifdef AHD_DUMP_SEQ 217 static void ahd_dumpseq(struct ahd_softc *ahd); 218 #endif 219 static void ahd_loadseq(struct ahd_softc *ahd); 220 static int ahd_check_patch(struct ahd_softc *ahd, 221 struct patch **start_patch, 222 u_int start_instr, u_int *skip_addr); 223 static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd, 224 u_int address); 225 static void ahd_download_instr(struct ahd_softc *ahd, 226 u_int instrptr, uint8_t *dconsts); 227 static int ahd_probe_stack_size(struct ahd_softc *ahd); 228 static int ahd_other_scb_timeout(struct ahd_softc *ahd, 229 struct scb *scb, 230 struct scb *other_scb); 231 static int ahd_scb_active_in_fifo(struct ahd_softc *ahd, 232 struct scb *scb); 233 static void ahd_run_data_fifo(struct ahd_softc *ahd, 234 struct scb *scb); 235 236 #ifdef AHD_TARGET_MODE 237 static void ahd_queue_lstate_event(struct ahd_softc *ahd, 238 struct ahd_tmode_lstate *lstate, 239 u_int initiator_id, 240 u_int event_type, 241 u_int event_arg); 242 static void ahd_update_scsiid(struct ahd_softc *ahd, 243 u_int targid_mask); 244 static int ahd_handle_target_cmd(struct ahd_softc *ahd, 245 struct target_cmd *cmd); 246 #endif 247 248 /******************************** Private Inlines *****************************/ 249 static __inline void ahd_assert_atn(struct ahd_softc *ahd); 250 static __inline int ahd_currently_packetized(struct ahd_softc *ahd); 251 static __inline int ahd_set_active_fifo(struct ahd_softc *ahd); 252 253 static __inline void 254 ahd_assert_atn(struct ahd_softc *ahd) 255 { 256 ahd_outb(ahd, SCSISIGO, ATNO); 257 } 258 259 /* 260 * Determine if the current connection has a packetized 261 * agreement. This does not necessarily mean that we 262 * are currently in a packetized transfer. We could 263 * just as easily be sending or receiving a message. 264 */ 265 static __inline int 266 ahd_currently_packetized(struct ahd_softc *ahd) 267 { 268 ahd_mode_state saved_modes; 269 int packetized; 270 271 saved_modes = ahd_save_modes(ahd); 272 if ((ahd->bugs & AHD_PKTIZED_STATUS_BUG) != 0) { 273 /* 274 * The packetized bit refers to the last 275 * connection, not the current one. Check 276 * for non-zero LQISTATE instead. 277 */ 278 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 279 packetized = ahd_inb(ahd, LQISTATE) != 0; 280 } else { 281 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 282 packetized = ahd_inb(ahd, LQISTAT2) & PACKETIZED; 283 } 284 ahd_restore_modes(ahd, saved_modes); 285 return (packetized); 286 } 287 288 static __inline int 289 ahd_set_active_fifo(struct ahd_softc *ahd) 290 { 291 u_int active_fifo; 292 293 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 294 active_fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; 295 switch (active_fifo) { 296 case 0: 297 case 1: 298 ahd_set_modes(ahd, active_fifo, active_fifo); 299 return (1); 300 default: 301 return (0); 302 } 303 } 304 305 /************************* Sequencer Execution Control ************************/ 306 /* 307 * Restart the sequencer program from address zero 308 */ 309 void 310 ahd_restart(struct ahd_softc *ahd) 311 { 312 313 ahd_pause(ahd); 314 315 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 316 317 /* No more pending messages */ 318 ahd_clear_msg_state(ahd); 319 ahd_outb(ahd, SCSISIGO, 0); /* De-assert BSY */ 320 ahd_outb(ahd, MSG_OUT, MSG_NOOP); /* No message to send */ 321 ahd_outb(ahd, SXFRCTL1, ahd_inb(ahd, SXFRCTL1) & ~BITBUCKET); 322 ahd_outb(ahd, SEQINTCTL, 0); 323 ahd_outb(ahd, LASTPHASE, P_BUSFREE); 324 ahd_outb(ahd, SEQ_FLAGS, 0); 325 ahd_outb(ahd, SAVED_SCSIID, 0xFF); 326 ahd_outb(ahd, SAVED_LUN, 0xFF); 327 328 /* 329 * Ensure that the sequencer's idea of TQINPOS 330 * matches our own. The sequencer increments TQINPOS 331 * only after it sees a DMA complete and a reset could 332 * occur before the increment leaving the kernel to believe 333 * the command arrived but the sequencer to not. 334 */ 335 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); 336 337 /* Always allow reselection */ 338 ahd_outb(ahd, SCSISEQ1, 339 ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 340 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 341 342 /* 343 * Clear any pending sequencer interrupt. It is no 344 * longer relevant since we're resetting the Program 345 * Counter. 346 */ 347 ahd_outb(ahd, CLRINT, CLRSEQINT); 348 349 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); 350 ahd_unpause(ahd); 351 } 352 353 void 354 ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo) 355 { 356 ahd_mode_state saved_modes; 357 358 #ifdef AHD_DEBUG 359 if ((ahd_debug & AHD_SHOW_FIFOS) != 0) 360 printf("%s: Clearing FIFO %d\n", ahd_name(ahd), fifo); 361 #endif 362 saved_modes = ahd_save_modes(ahd); 363 ahd_set_modes(ahd, fifo, fifo); 364 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); 365 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) 366 ahd_outb(ahd, CCSGCTL, CCSGRESET); 367 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 368 ahd_outb(ahd, SG_STATE, 0); 369 ahd_restore_modes(ahd, saved_modes); 370 } 371 372 /************************* Input/Output Queues ********************************/ 373 /* 374 * Flush and completed commands that are sitting in the command 375 * complete queues down on the chip but have yet to be dma'ed back up. 376 */ 377 void 378 ahd_flush_qoutfifo(struct ahd_softc *ahd) 379 { 380 struct scb *scb; 381 ahd_mode_state saved_modes; 382 u_int saved_scbptr; 383 u_int ccscbctl; 384 u_int scbid; 385 u_int next_scbid; 386 387 saved_modes = ahd_save_modes(ahd); 388 389 /* 390 * Flush the good status FIFO for completed packetized commands. 391 */ 392 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 393 saved_scbptr = ahd_get_scbptr(ahd); 394 while ((ahd_inb(ahd, LQISTAT2) & LQIGSAVAIL) != 0) { 395 u_int fifo_mode; 396 u_int i; 397 398 scbid = ahd_inw(ahd, GSFIFO); 399 scb = ahd_lookup_scb(ahd, scbid); 400 if (scb == NULL) { 401 printf("%s: Warning - GSFIFO SCB %d invalid\n", 402 ahd_name(ahd), scbid); 403 continue; 404 } 405 /* 406 * Determine if this transaction is still active in 407 * any FIFO. If it is, we must flush that FIFO to 408 * the host before completing the command. 409 */ 410 fifo_mode = 0; 411 rescan_fifos: 412 for (i = 0; i < 2; i++) { 413 /* Toggle to the other mode. */ 414 fifo_mode ^= 1; 415 ahd_set_modes(ahd, fifo_mode, fifo_mode); 416 417 if (ahd_scb_active_in_fifo(ahd, scb) == 0) 418 continue; 419 420 ahd_run_data_fifo(ahd, scb); 421 422 /* 423 * Running this FIFO may cause a CFG4DATA for 424 * this same transaction to assert in the other 425 * FIFO or a new snapshot SAVEPTRS interrupt 426 * in this FIFO. Even running a FIFO may not 427 * clear the transaction if we are still waiting 428 * for data to drain to the host. We must loop 429 * until the transaction is not active in either 430 * FIFO just to be sure. Reset our loop counter 431 * so we will visit both FIFOs again before 432 * declaring this transaction finished. We 433 * also delay a bit so that status has a chance 434 * to change before we look at this FIFO again. 435 */ 436 aic_delay(200); 437 goto rescan_fifos; 438 } 439 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 440 ahd_set_scbptr(ahd, scbid); 441 if ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_LIST_NULL) == 0 442 && ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_FULL_RESID) != 0 443 || (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR) 444 & SG_LIST_NULL) != 0)) { 445 u_int comp_head; 446 447 /* 448 * The transfer completed with a residual. 449 * Place this SCB on the complete DMA list 450 * so that we update our in-core copy of the 451 * SCB before completing the command. 452 */ 453 ahd_outb(ahd, SCB_SCSI_STATUS, 0); 454 ahd_outb(ahd, SCB_SGPTR, 455 ahd_inb_scbram(ahd, SCB_SGPTR) 456 | SG_STATUS_VALID); 457 ahd_outw(ahd, SCB_TAG, scbid); 458 ahd_outw(ahd, SCB_NEXT_COMPLETE, SCB_LIST_NULL); 459 comp_head = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 460 if (SCBID_IS_NULL(comp_head)) { 461 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, scbid); 462 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid); 463 } else { 464 u_int tail; 465 466 tail = ahd_inw(ahd, COMPLETE_DMA_SCB_TAIL); 467 ahd_set_scbptr(ahd, tail); 468 ahd_outw(ahd, SCB_NEXT_COMPLETE, scbid); 469 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid); 470 ahd_set_scbptr(ahd, scbid); 471 } 472 } else 473 ahd_complete_scb(ahd, scb); 474 } 475 ahd_set_scbptr(ahd, saved_scbptr); 476 477 /* 478 * Setup for command channel portion of flush. 479 */ 480 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 481 482 /* 483 * Wait for any inprogress DMA to complete and clear DMA state 484 * if this if for an SCB in the qinfifo. 485 */ 486 while (((ccscbctl = ahd_inb(ahd, CCSCBCTL)) & (CCARREN|CCSCBEN)) != 0) { 487 488 if ((ccscbctl & (CCSCBDIR|CCARREN)) == (CCSCBDIR|CCARREN)) { 489 if ((ccscbctl & ARRDONE) != 0) 490 break; 491 } else if ((ccscbctl & CCSCBDONE) != 0) 492 break; 493 aic_delay(200); 494 } 495 /* 496 * We leave the sequencer to cleanup in the case of DMA's to 497 * update the qoutfifo. In all other cases (DMA's to the 498 * chip or a push of an SCB from the COMPLETE_DMA_SCB list), 499 * we disable the DMA engine so that the sequencer will not 500 * attempt to handle the DMA completion. 501 */ 502 if ((ccscbctl & CCSCBDIR) != 0 || (ccscbctl & ARRDONE) != 0) 503 ahd_outb(ahd, CCSCBCTL, ccscbctl & ~(CCARREN|CCSCBEN)); 504 505 /* 506 * Complete any SCBs that just finished 507 * being DMA'ed into the qoutfifo. 508 */ 509 ahd_run_qoutfifo(ahd); 510 511 saved_scbptr = ahd_get_scbptr(ahd); 512 /* 513 * Manually update/complete any completed SCBs that are waiting to be 514 * DMA'ed back up to the host. 515 */ 516 scbid = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 517 while (!SCBID_IS_NULL(scbid)) { 518 uint8_t *hscb_ptr; 519 u_int i; 520 521 ahd_set_scbptr(ahd, scbid); 522 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 523 scb = ahd_lookup_scb(ahd, scbid); 524 if (scb == NULL) { 525 printf("%s: Warning - DMA-up and complete " 526 "SCB %d invalid\n", ahd_name(ahd), scbid); 527 continue; 528 } 529 hscb_ptr = (uint8_t *)scb->hscb; 530 for (i = 0; i < sizeof(struct hardware_scb); i++) 531 *hscb_ptr++ = ahd_inb_scbram(ahd, SCB_BASE + i); 532 533 ahd_complete_scb(ahd, scb); 534 scbid = next_scbid; 535 } 536 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); 537 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL); 538 539 scbid = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD); 540 while (!SCBID_IS_NULL(scbid)) { 541 542 ahd_set_scbptr(ahd, scbid); 543 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 544 scb = ahd_lookup_scb(ahd, scbid); 545 if (scb == NULL) { 546 printf("%s: Warning - Complete Qfrz SCB %d invalid\n", 547 ahd_name(ahd), scbid); 548 continue; 549 } 550 551 ahd_complete_scb(ahd, scb); 552 scbid = next_scbid; 553 } 554 ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL); 555 556 scbid = ahd_inw(ahd, COMPLETE_SCB_HEAD); 557 while (!SCBID_IS_NULL(scbid)) { 558 559 ahd_set_scbptr(ahd, scbid); 560 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 561 scb = ahd_lookup_scb(ahd, scbid); 562 if (scb == NULL) { 563 printf("%s: Warning - Complete SCB %d invalid\n", 564 ahd_name(ahd), scbid); 565 continue; 566 } 567 568 ahd_complete_scb(ahd, scb); 569 scbid = next_scbid; 570 } 571 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); 572 573 /* 574 * Restore state. 575 */ 576 ahd_set_scbptr(ahd, saved_scbptr); 577 ahd_restore_modes(ahd, saved_modes); 578 ahd->flags |= AHD_UPDATE_PEND_CMDS; 579 } 580 581 /* 582 * Determine if an SCB for a packetized transaction 583 * is active in a FIFO. 584 */ 585 static int 586 ahd_scb_active_in_fifo(struct ahd_softc *ahd, struct scb *scb) 587 { 588 589 /* 590 * The FIFO is only active for our transaction if 591 * the SCBPTR matches the SCB's ID and the firmware 592 * has installed a handler for the FIFO or we have 593 * a pending SAVEPTRS or CFG4DATA interrupt. 594 */ 595 if (ahd_get_scbptr(ahd) != SCB_GET_TAG(scb) 596 || ((ahd_inb(ahd, LONGJMP_ADDR+1) & INVALID_ADDR) != 0 597 && (ahd_inb(ahd, SEQINTSRC) & (CFG4DATA|SAVEPTRS)) == 0)) 598 return (0); 599 600 return (1); 601 } 602 603 /* 604 * Run a data fifo to completion for a transaction we know 605 * has completed across the SCSI bus (good status has been 606 * received). We are already set to the correct FIFO mode 607 * on entry to this routine. 608 * 609 * This function attempts to operate exactly as the firmware 610 * would when running this FIFO. Care must be taken to update 611 * this routine any time the firmware's FIFO algorithm is 612 * changed. 613 */ 614 static void 615 ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb) 616 { 617 u_int seqintsrc; 618 619 seqintsrc = ahd_inb(ahd, SEQINTSRC); 620 if ((seqintsrc & CFG4DATA) != 0) { 621 uint32_t datacnt; 622 uint32_t sgptr; 623 624 /* 625 * Clear full residual flag. 626 */ 627 sgptr = ahd_inl_scbram(ahd, SCB_SGPTR) & ~SG_FULL_RESID; 628 ahd_outb(ahd, SCB_SGPTR, sgptr); 629 630 /* 631 * Load datacnt and address. 632 */ 633 datacnt = ahd_inl_scbram(ahd, SCB_DATACNT); 634 if ((datacnt & AHD_DMA_LAST_SEG) != 0) { 635 sgptr |= LAST_SEG; 636 ahd_outb(ahd, SG_STATE, 0); 637 } else 638 ahd_outb(ahd, SG_STATE, LOADING_NEEDED); 639 ahd_outq(ahd, HADDR, ahd_inq_scbram(ahd, SCB_DATAPTR)); 640 ahd_outl(ahd, HCNT, datacnt & AHD_SG_LEN_MASK); 641 ahd_outb(ahd, SG_CACHE_PRE, sgptr); 642 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN); 643 644 /* 645 * Initialize Residual Fields. 646 */ 647 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, datacnt >> 24); 648 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr & SG_PTR_MASK); 649 650 /* 651 * Mark the SCB as having a FIFO in use. 652 */ 653 ahd_outb(ahd, SCB_FIFO_USE_COUNT, 654 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) + 1); 655 656 /* 657 * Install a "fake" handler for this FIFO. 658 */ 659 ahd_outw(ahd, LONGJMP_ADDR, 0); 660 661 /* 662 * Notify the hardware that we have satisfied 663 * this sequencer interrupt. 664 */ 665 ahd_outb(ahd, CLRSEQINTSRC, CLRCFG4DATA); 666 } else if ((seqintsrc & SAVEPTRS) != 0) { 667 uint32_t sgptr; 668 uint32_t resid; 669 670 if ((ahd_inb(ahd, LONGJMP_ADDR+1)&INVALID_ADDR) != 0) { 671 /* 672 * Snapshot Save Pointers. All that 673 * is necessary to clear the snapshot 674 * is a CLRCHN. 675 */ 676 goto clrchn; 677 } 678 679 /* 680 * Disable S/G fetch so the DMA engine 681 * is available to future users. 682 */ 683 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) 684 ahd_outb(ahd, CCSGCTL, 0); 685 ahd_outb(ahd, SG_STATE, 0); 686 687 /* 688 * Flush the data FIFO. Strickly only 689 * necessary for Rev A parts. 690 */ 691 ahd_outb(ahd, DFCNTRL, ahd_inb(ahd, DFCNTRL) | FIFOFLUSH); 692 693 /* 694 * Calculate residual. 695 */ 696 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 697 resid = ahd_inl(ahd, SHCNT); 698 resid |= ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+3) << 24; 699 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, resid); 700 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG) == 0) { 701 /* 702 * Must back up to the correct S/G element. 703 * Typically this just means resetting our 704 * low byte to the offset in the SG_CACHE, 705 * but if we wrapped, we have to correct 706 * the other bytes of the sgptr too. 707 */ 708 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & 0x80) != 0 709 && (sgptr & 0x80) == 0) 710 sgptr -= 0x100; 711 sgptr &= ~0xFF; 712 sgptr |= ahd_inb(ahd, SG_CACHE_SHADOW) 713 & SG_ADDR_MASK; 714 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr); 715 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 3, 0); 716 } else if ((resid & AHD_SG_LEN_MASK) == 0) { 717 ahd_outb(ahd, SCB_RESIDUAL_SGPTR, 718 sgptr | SG_LIST_NULL); 719 } 720 /* 721 * Save Pointers. 722 */ 723 ahd_outq(ahd, SCB_DATAPTR, ahd_inq(ahd, SHADDR)); 724 ahd_outl(ahd, SCB_DATACNT, resid); 725 ahd_outl(ahd, SCB_SGPTR, sgptr); 726 ahd_outb(ahd, CLRSEQINTSRC, CLRSAVEPTRS); 727 ahd_outb(ahd, SEQIMODE, 728 ahd_inb(ahd, SEQIMODE) | ENSAVEPTRS); 729 /* 730 * If the data is to the SCSI bus, we are 731 * done, otherwise wait for FIFOEMP. 732 */ 733 if ((ahd_inb(ahd, DFCNTRL) & DIRECTION) != 0) 734 goto clrchn; 735 } else if ((ahd_inb(ahd, SG_STATE) & LOADING_NEEDED) != 0) { 736 uint32_t sgptr; 737 uint64_t data_addr; 738 uint32_t data_len; 739 u_int dfcntrl; 740 741 /* 742 * Disable S/G fetch so the DMA engine 743 * is available to future users. We won't 744 * be using the DMA engine to load segments. 745 */ 746 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) { 747 ahd_outb(ahd, CCSGCTL, 0); 748 ahd_outb(ahd, SG_STATE, LOADING_NEEDED); 749 } 750 751 /* 752 * Wait for the DMA engine to notice that the 753 * host transfer is enabled and that there is 754 * space in the S/G FIFO for new segments before 755 * loading more segments. 756 */ 757 if ((ahd_inb(ahd, DFSTATUS) & PRELOAD_AVAIL) != 0 758 && (ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) { 759 760 /* 761 * Determine the offset of the next S/G 762 * element to load. 763 */ 764 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 765 sgptr &= SG_PTR_MASK; 766 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 767 struct ahd_dma64_seg *sg; 768 769 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 770 data_addr = sg->addr; 771 data_len = sg->len; 772 sgptr += sizeof(*sg); 773 } else { 774 struct ahd_dma_seg *sg; 775 776 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 777 data_addr = sg->len & AHD_SG_HIGH_ADDR_MASK; 778 data_addr <<= 8; 779 data_addr |= sg->addr; 780 data_len = sg->len; 781 sgptr += sizeof(*sg); 782 } 783 784 /* 785 * Update residual information. 786 */ 787 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, data_len >> 24); 788 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr); 789 790 /* 791 * Load the S/G. 792 */ 793 if (data_len & AHD_DMA_LAST_SEG) { 794 sgptr |= LAST_SEG; 795 ahd_outb(ahd, SG_STATE, 0); 796 } 797 ahd_outq(ahd, HADDR, data_addr); 798 ahd_outl(ahd, HCNT, data_len & AHD_SG_LEN_MASK); 799 ahd_outb(ahd, SG_CACHE_PRE, sgptr & 0xFF); 800 801 /* 802 * Advertise the segment to the hardware. 803 */ 804 dfcntrl = ahd_inb(ahd, DFCNTRL)|PRELOADEN|HDMAEN; 805 if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) != 0) { 806 /* 807 * Use SCSIENWRDIS so that SCSIEN 808 * is never modified by this 809 * operation. 810 */ 811 dfcntrl |= SCSIENWRDIS; 812 } 813 ahd_outb(ahd, DFCNTRL, dfcntrl); 814 } 815 } else if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG_DONE) != 0) { 816 817 /* 818 * Transfer completed to the end of SG list 819 * and has flushed to the host. 820 */ 821 ahd_outb(ahd, SCB_SGPTR, 822 ahd_inb_scbram(ahd, SCB_SGPTR) | SG_LIST_NULL); 823 goto clrchn; 824 } else if ((ahd_inb(ahd, DFSTATUS) & FIFOEMP) != 0) { 825 clrchn: 826 /* 827 * Clear any handler for this FIFO, decrement 828 * the FIFO use count for the SCB, and release 829 * the FIFO. 830 */ 831 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 832 ahd_outb(ahd, SCB_FIFO_USE_COUNT, 833 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) - 1); 834 ahd_outb(ahd, DFFSXFRCTL, CLRCHN); 835 } 836 } 837 838 /* 839 * Look for entries in the QoutFIFO that have completed. 840 * The valid_tag completion field indicates the validity 841 * of the entry - the valid value toggles each time through 842 * the queue. We use the sg_status field in the completion 843 * entry to avoid referencing the hscb if the completion 844 * occurred with no errors and no residual. sg_status is 845 * a copy of the first byte (little endian) of the sgptr 846 * hscb field. 847 */ 848 void 849 ahd_run_qoutfifo(struct ahd_softc *ahd) 850 { 851 struct ahd_completion *completion; 852 struct scb *scb; 853 u_int scb_index; 854 855 if ((ahd->flags & AHD_RUNNING_QOUTFIFO) != 0) 856 panic("ahd_run_qoutfifo recursion"); 857 ahd->flags |= AHD_RUNNING_QOUTFIFO; 858 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD); 859 for (;;) { 860 completion = &ahd->qoutfifo[ahd->qoutfifonext]; 861 862 if (completion->valid_tag != ahd->qoutfifonext_valid_tag) 863 break; 864 865 scb_index = aic_le16toh(completion->tag); 866 scb = ahd_lookup_scb(ahd, scb_index); 867 if (scb == NULL) { 868 printf("%s: WARNING no command for scb %d " 869 "(cmdcmplt)\nQOUTPOS = %d\n", 870 ahd_name(ahd), scb_index, 871 ahd->qoutfifonext); 872 ahd_dump_card_state(ahd); 873 } else if ((completion->sg_status & SG_STATUS_VALID) != 0) { 874 ahd_handle_scb_status(ahd, scb); 875 } else { 876 ahd_done(ahd, scb); 877 } 878 879 ahd->qoutfifonext = (ahd->qoutfifonext+1) & (AHD_QOUT_SIZE-1); 880 if (ahd->qoutfifonext == 0) 881 ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID; 882 } 883 ahd->flags &= ~AHD_RUNNING_QOUTFIFO; 884 } 885 886 /************************* Interrupt Handling *********************************/ 887 void 888 ahd_handle_hwerrint(struct ahd_softc *ahd) 889 { 890 /* 891 * Some catastrophic hardware error has occurred. 892 * Print it for the user and disable the controller. 893 */ 894 int i; 895 int error; 896 897 error = ahd_inb(ahd, ERROR); 898 for (i = 0; i < num_errors; i++) { 899 if ((error & ahd_hard_errors[i].errno) != 0) 900 printf("%s: hwerrint, %s\n", 901 ahd_name(ahd), ahd_hard_errors[i].errmesg); 902 } 903 904 ahd_dump_card_state(ahd); 905 panic("BRKADRINT"); 906 907 /* Tell everyone that this HBA is no longer available */ 908 ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, 909 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 910 CAM_NO_HBA); 911 912 /* Tell the system that this controller has gone away. */ 913 ahd_free(ahd); 914 } 915 916 void 917 ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat) 918 { 919 u_int seqintcode; 920 921 /* 922 * Save the sequencer interrupt code and clear the SEQINT 923 * bit. We will unpause the sequencer, if appropriate, 924 * after servicing the request. 925 */ 926 seqintcode = ahd_inb(ahd, SEQINTCODE); 927 ahd_outb(ahd, CLRINT, CLRSEQINT); 928 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { 929 /* 930 * Unpause the sequencer and let it clear 931 * SEQINT by writing NO_SEQINT to it. This 932 * will cause the sequencer to be paused again, 933 * which is the expected state of this routine. 934 */ 935 ahd_unpause(ahd); 936 while (!ahd_is_paused(ahd)) 937 ; 938 ahd_outb(ahd, CLRINT, CLRSEQINT); 939 } 940 ahd_update_modes(ahd); 941 #ifdef AHD_DEBUG 942 if ((ahd_debug & AHD_SHOW_MISC) != 0) 943 printf("%s: Handle Seqint Called for code %d\n", 944 ahd_name(ahd), seqintcode); 945 #endif 946 switch (seqintcode) { 947 case ENTERING_NONPACK: 948 { 949 struct scb *scb; 950 u_int scbid; 951 952 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 953 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 954 scbid = ahd_get_scbptr(ahd); 955 scb = ahd_lookup_scb(ahd, scbid); 956 if (scb == NULL) { 957 /* 958 * Somehow need to know if this 959 * is from a selection or reselection. 960 * From that, we can determine target 961 * ID so we at least have an I_T nexus. 962 */ 963 } else { 964 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); 965 ahd_outb(ahd, SAVED_LUN, scb->hscb->lun); 966 ahd_outb(ahd, SEQ_FLAGS, 0x0); 967 } 968 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0 969 && (ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { 970 /* 971 * Phase change after read stream with 972 * CRC error with P0 asserted on last 973 * packet. 974 */ 975 #ifdef AHD_DEBUG 976 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 977 printf("%s: Assuming LQIPHASE_NLQ with " 978 "P0 assertion\n", ahd_name(ahd)); 979 #endif 980 } 981 #ifdef AHD_DEBUG 982 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 983 printf("%s: Entering NONPACK\n", ahd_name(ahd)); 984 #endif 985 break; 986 } 987 case INVALID_SEQINT: 988 printf("%s: Invalid Sequencer interrupt occurred.\n", 989 ahd_name(ahd)); 990 ahd_dump_card_state(ahd); 991 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 992 break; 993 case STATUS_OVERRUN: 994 { 995 struct scb *scb; 996 u_int scbid; 997 998 scbid = ahd_get_scbptr(ahd); 999 scb = ahd_lookup_scb(ahd, scbid); 1000 if (scb != NULL) 1001 ahd_print_path(ahd, scb); 1002 else 1003 printf("%s: ", ahd_name(ahd)); 1004 printf("SCB %d Packetized Status Overrun", scbid); 1005 ahd_dump_card_state(ahd); 1006 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1007 break; 1008 } 1009 case CFG4ISTAT_INTR: 1010 { 1011 struct scb *scb; 1012 u_int scbid; 1013 1014 scbid = ahd_get_scbptr(ahd); 1015 scb = ahd_lookup_scb(ahd, scbid); 1016 if (scb == NULL) { 1017 ahd_dump_card_state(ahd); 1018 printf("CFG4ISTAT: Free SCB %d referenced", scbid); 1019 panic("For safety"); 1020 } 1021 ahd_outq(ahd, HADDR, scb->sense_busaddr); 1022 ahd_outw(ahd, HCNT, AHD_SENSE_BUFSIZE); 1023 ahd_outb(ahd, HCNT + 2, 0); 1024 ahd_outb(ahd, SG_CACHE_PRE, SG_LAST_SEG); 1025 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN); 1026 break; 1027 } 1028 case ILLEGAL_PHASE: 1029 { 1030 u_int bus_phase; 1031 1032 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1033 printf("%s: ILLEGAL_PHASE 0x%x\n", 1034 ahd_name(ahd), bus_phase); 1035 1036 switch (bus_phase) { 1037 case P_DATAOUT: 1038 case P_DATAIN: 1039 case P_DATAOUT_DT: 1040 case P_DATAIN_DT: 1041 case P_MESGOUT: 1042 case P_STATUS: 1043 case P_MESGIN: 1044 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1045 printf("%s: Issued Bus Reset.\n", ahd_name(ahd)); 1046 break; 1047 case P_COMMAND: 1048 { 1049 struct ahd_devinfo devinfo; 1050 struct scb *scb; 1051 struct ahd_initiator_tinfo *targ_info; 1052 struct ahd_tmode_tstate *tstate; 1053 struct ahd_transinfo *tinfo; 1054 u_int scbid; 1055 1056 /* 1057 * If a target takes us into the command phase 1058 * assume that it has been externally reset and 1059 * has thus lost our previous packetized negotiation 1060 * agreement. Since we have not sent an identify 1061 * message and may not have fully qualified the 1062 * connection, we change our command to TUR, assert 1063 * ATN and ABORT the task when we go to message in 1064 * phase. The OSM will see the REQUEUE_REQUEST 1065 * status and retry the command. 1066 */ 1067 scbid = ahd_get_scbptr(ahd); 1068 scb = ahd_lookup_scb(ahd, scbid); 1069 if (scb == NULL) { 1070 printf("Invalid phase with no valid SCB. " 1071 "Resetting bus.\n"); 1072 ahd_reset_channel(ahd, 'A', 1073 /*Initiate Reset*/TRUE); 1074 break; 1075 } 1076 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), 1077 SCB_GET_TARGET(ahd, scb), 1078 SCB_GET_LUN(scb), 1079 SCB_GET_CHANNEL(ahd, scb), 1080 ROLE_INITIATOR); 1081 targ_info = ahd_fetch_transinfo(ahd, 1082 devinfo.channel, 1083 devinfo.our_scsiid, 1084 devinfo.target, 1085 &tstate); 1086 tinfo = &targ_info->curr; 1087 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 1088 AHD_TRANS_ACTIVE, /*paused*/TRUE); 1089 ahd_set_syncrate(ahd, &devinfo, /*period*/0, 1090 /*offset*/0, /*ppr_options*/0, 1091 AHD_TRANS_ACTIVE, /*paused*/TRUE); 1092 ahd_outb(ahd, SCB_CDB_STORE, 0); 1093 ahd_outb(ahd, SCB_CDB_STORE+1, 0); 1094 ahd_outb(ahd, SCB_CDB_STORE+2, 0); 1095 ahd_outb(ahd, SCB_CDB_STORE+3, 0); 1096 ahd_outb(ahd, SCB_CDB_STORE+4, 0); 1097 ahd_outb(ahd, SCB_CDB_STORE+5, 0); 1098 ahd_outb(ahd, SCB_CDB_LEN, 6); 1099 scb->hscb->control &= ~(TAG_ENB|SCB_TAG_TYPE); 1100 scb->hscb->control |= MK_MESSAGE; 1101 ahd_outb(ahd, SCB_CONTROL, scb->hscb->control); 1102 ahd_outb(ahd, MSG_OUT, HOST_MSG); 1103 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); 1104 /* 1105 * The lun is 0, regardless of the SCB's lun 1106 * as we have not sent an identify message. 1107 */ 1108 ahd_outb(ahd, SAVED_LUN, 0); 1109 ahd_outb(ahd, SEQ_FLAGS, 0); 1110 ahd_assert_atn(ahd); 1111 scb->flags &= ~SCB_PACKETIZED; 1112 scb->flags |= SCB_ABORT|SCB_CMDPHASE_ABORT; 1113 ahd_freeze_devq(ahd, scb); 1114 aic_set_transaction_status(scb, CAM_REQUEUE_REQ); 1115 aic_freeze_scb(scb); 1116 1117 /* 1118 * Allow the sequencer to continue with 1119 * non-pack processing. 1120 */ 1121 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1122 ahd_outb(ahd, CLRLQOINT1, CLRLQOPHACHGINPKT); 1123 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 1124 ahd_outb(ahd, CLRLQOINT1, 0); 1125 } 1126 #ifdef AHD_DEBUG 1127 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1128 ahd_print_path(ahd, scb); 1129 printf("Unexpected command phase from " 1130 "packetized target\n"); 1131 } 1132 #endif 1133 break; 1134 } 1135 } 1136 break; 1137 } 1138 case CFG4OVERRUN: 1139 { 1140 struct scb *scb; 1141 u_int scb_index; 1142 1143 #ifdef AHD_DEBUG 1144 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1145 printf("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd), 1146 ahd_inb(ahd, MODE_PTR)); 1147 } 1148 #endif 1149 scb_index = ahd_get_scbptr(ahd); 1150 scb = ahd_lookup_scb(ahd, scb_index); 1151 if (scb == NULL) { 1152 /* 1153 * Attempt to transfer to an SCB that is 1154 * not outstanding. 1155 */ 1156 ahd_assert_atn(ahd); 1157 ahd_outb(ahd, MSG_OUT, HOST_MSG); 1158 ahd->msgout_buf[0] = MSG_ABORT_TASK; 1159 ahd->msgout_len = 1; 1160 ahd->msgout_index = 0; 1161 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1162 /* 1163 * Clear status received flag to prevent any 1164 * attempt to complete this bogus SCB. 1165 */ 1166 ahd_outb(ahd, SCB_CONTROL, 1167 ahd_inb_scbram(ahd, SCB_CONTROL) 1168 & ~STATUS_RCVD); 1169 } 1170 break; 1171 } 1172 case DUMP_CARD_STATE: 1173 { 1174 ahd_dump_card_state(ahd); 1175 break; 1176 } 1177 case PDATA_REINIT: 1178 { 1179 #ifdef AHD_DEBUG 1180 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1181 printf("%s: PDATA_REINIT - DFCNTRL = 0x%x " 1182 "SG_CACHE_SHADOW = 0x%x\n", 1183 ahd_name(ahd), ahd_inb(ahd, DFCNTRL), 1184 ahd_inb(ahd, SG_CACHE_SHADOW)); 1185 } 1186 #endif 1187 ahd_reinitialize_dataptrs(ahd); 1188 break; 1189 } 1190 case HOST_MSG_LOOP: 1191 { 1192 struct ahd_devinfo devinfo; 1193 1194 /* 1195 * The sequencer has encountered a message phase 1196 * that requires host assistance for completion. 1197 * While handling the message phase(s), we will be 1198 * notified by the sequencer after each byte is 1199 * transfered so we can track bus phase changes. 1200 * 1201 * If this is the first time we've seen a HOST_MSG_LOOP 1202 * interrupt, initialize the state of the host message 1203 * loop. 1204 */ 1205 ahd_fetch_devinfo(ahd, &devinfo); 1206 if (ahd->msg_type == MSG_TYPE_NONE) { 1207 struct scb *scb; 1208 u_int scb_index; 1209 u_int bus_phase; 1210 1211 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1212 if (bus_phase != P_MESGIN 1213 && bus_phase != P_MESGOUT) { 1214 printf("ahd_intr: HOST_MSG_LOOP bad " 1215 "phase 0x%x\n", bus_phase); 1216 /* 1217 * Probably transitioned to bus free before 1218 * we got here. Just punt the message. 1219 */ 1220 ahd_dump_card_state(ahd); 1221 ahd_clear_intstat(ahd); 1222 ahd_restart(ahd); 1223 return; 1224 } 1225 1226 scb_index = ahd_get_scbptr(ahd); 1227 scb = ahd_lookup_scb(ahd, scb_index); 1228 if (devinfo.role == ROLE_INITIATOR) { 1229 if (bus_phase == P_MESGOUT) 1230 ahd_setup_initiator_msgout(ahd, 1231 &devinfo, 1232 scb); 1233 else { 1234 ahd->msg_type = 1235 MSG_TYPE_INITIATOR_MSGIN; 1236 ahd->msgin_index = 0; 1237 } 1238 } 1239 #if AHD_TARGET_MODE 1240 else { 1241 if (bus_phase == P_MESGOUT) { 1242 ahd->msg_type = 1243 MSG_TYPE_TARGET_MSGOUT; 1244 ahd->msgin_index = 0; 1245 } 1246 else 1247 ahd_setup_target_msgin(ahd, 1248 &devinfo, 1249 scb); 1250 } 1251 #endif 1252 } 1253 1254 ahd_handle_message_phase(ahd); 1255 break; 1256 } 1257 case NO_MATCH: 1258 { 1259 /* Ensure we don't leave the selection hardware on */ 1260 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 1261 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 1262 1263 printf("%s:%c:%d: no active SCB for reconnecting " 1264 "target - issuing BUS DEVICE RESET\n", 1265 ahd_name(ahd), 'A', ahd_inb(ahd, SELID) >> 4); 1266 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 1267 "REG0 == 0x%x ACCUM = 0x%x\n", 1268 ahd_inb(ahd, SAVED_SCSIID), ahd_inb(ahd, SAVED_LUN), 1269 ahd_inw(ahd, REG0), ahd_inb(ahd, ACCUM)); 1270 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 1271 "SINDEX == 0x%x\n", 1272 ahd_inb(ahd, SEQ_FLAGS), ahd_get_scbptr(ahd), 1273 ahd_find_busy_tcl(ahd, 1274 BUILD_TCL(ahd_inb(ahd, SAVED_SCSIID), 1275 ahd_inb(ahd, SAVED_LUN))), 1276 ahd_inw(ahd, SINDEX)); 1277 printf("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 1278 "SCB_CONTROL == 0x%x\n", 1279 ahd_inb(ahd, SELID), ahd_inb_scbram(ahd, SCB_SCSIID), 1280 ahd_inb_scbram(ahd, SCB_LUN), 1281 ahd_inb_scbram(ahd, SCB_CONTROL)); 1282 printf("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n", 1283 ahd_inb(ahd, SCSIBUS), ahd_inb(ahd, SCSISIGI)); 1284 printf("SXFRCTL0 == 0x%x\n", ahd_inb(ahd, SXFRCTL0)); 1285 printf("SEQCTL0 == 0x%x\n", ahd_inb(ahd, SEQCTL0)); 1286 ahd_dump_card_state(ahd); 1287 ahd->msgout_buf[0] = MSG_BUS_DEV_RESET; 1288 ahd->msgout_len = 1; 1289 ahd->msgout_index = 0; 1290 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1291 ahd_outb(ahd, MSG_OUT, HOST_MSG); 1292 ahd_assert_atn(ahd); 1293 break; 1294 } 1295 case PROTO_VIOLATION: 1296 { 1297 ahd_handle_proto_violation(ahd); 1298 break; 1299 } 1300 case IGN_WIDE_RES: 1301 { 1302 struct ahd_devinfo devinfo; 1303 1304 ahd_fetch_devinfo(ahd, &devinfo); 1305 ahd_handle_ign_wide_residue(ahd, &devinfo); 1306 break; 1307 } 1308 case BAD_PHASE: 1309 { 1310 u_int lastphase; 1311 1312 lastphase = ahd_inb(ahd, LASTPHASE); 1313 printf("%s:%c:%d: unknown scsi bus phase %x, " 1314 "lastphase = 0x%x. Attempting to continue\n", 1315 ahd_name(ahd), 'A', 1316 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), 1317 lastphase, ahd_inb(ahd, SCSISIGI)); 1318 break; 1319 } 1320 case MISSED_BUSFREE: 1321 { 1322 u_int lastphase; 1323 1324 lastphase = ahd_inb(ahd, LASTPHASE); 1325 printf("%s:%c:%d: Missed busfree. " 1326 "Lastphase = 0x%x, Curphase = 0x%x\n", 1327 ahd_name(ahd), 'A', 1328 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), 1329 lastphase, ahd_inb(ahd, SCSISIGI)); 1330 ahd_restart(ahd); 1331 return; 1332 } 1333 case DATA_OVERRUN: 1334 { 1335 /* 1336 * When the sequencer detects an overrun, it 1337 * places the controller in "BITBUCKET" mode 1338 * and allows the target to complete its transfer. 1339 * Unfortunately, none of the counters get updated 1340 * when the controller is in this mode, so we have 1341 * no way of knowing how large the overrun was. 1342 */ 1343 struct scb *scb; 1344 u_int scbindex; 1345 #ifdef AHD_DEBUG 1346 u_int lastphase; 1347 #endif 1348 1349 scbindex = ahd_get_scbptr(ahd); 1350 scb = ahd_lookup_scb(ahd, scbindex); 1351 #ifdef AHD_DEBUG 1352 lastphase = ahd_inb(ahd, LASTPHASE); 1353 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1354 ahd_print_path(ahd, scb); 1355 printf("data overrun detected %s. Tag == 0x%x.\n", 1356 ahd_lookup_phase_entry(lastphase)->phasemsg, 1357 SCB_GET_TAG(scb)); 1358 ahd_print_path(ahd, scb); 1359 printf("%s seen Data Phase. Length = %ld. " 1360 "NumSGs = %d.\n", 1361 ahd_inb(ahd, SEQ_FLAGS) & DPHASE 1362 ? "Have" : "Haven't", 1363 aic_get_transfer_length(scb), scb->sg_count); 1364 ahd_dump_sglist(scb); 1365 } 1366 #endif 1367 1368 /* 1369 * Set this and it will take effect when the 1370 * target does a command complete. 1371 */ 1372 ahd_freeze_devq(ahd, scb); 1373 aic_set_transaction_status(scb, CAM_DATA_RUN_ERR); 1374 aic_freeze_scb(scb); 1375 break; 1376 } 1377 case MKMSG_FAILED: 1378 { 1379 struct ahd_devinfo devinfo; 1380 struct scb *scb; 1381 u_int scbid; 1382 1383 ahd_fetch_devinfo(ahd, &devinfo); 1384 printf("%s:%c:%d:%d: Attempt to issue message failed\n", 1385 ahd_name(ahd), devinfo.channel, devinfo.target, 1386 devinfo.lun); 1387 scbid = ahd_get_scbptr(ahd); 1388 scb = ahd_lookup_scb(ahd, scbid); 1389 if (scb != NULL 1390 && (scb->flags & SCB_RECOVERY_SCB) != 0) 1391 /* 1392 * Ensure that we didn't put a second instance of this 1393 * SCB into the QINFIFO. 1394 */ 1395 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 1396 SCB_GET_CHANNEL(ahd, scb), 1397 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1398 ROLE_INITIATOR, /*status*/0, 1399 SEARCH_REMOVE); 1400 ahd_outb(ahd, SCB_CONTROL, 1401 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE); 1402 break; 1403 } 1404 case TASKMGMT_FUNC_COMPLETE: 1405 { 1406 u_int scbid; 1407 struct scb *scb; 1408 1409 scbid = ahd_get_scbptr(ahd); 1410 scb = ahd_lookup_scb(ahd, scbid); 1411 if (scb != NULL) { 1412 u_int lun; 1413 u_int tag; 1414 cam_status error; 1415 1416 ahd_print_path(ahd, scb); 1417 printf("Task Management Func 0x%x Complete\n", 1418 scb->hscb->task_management); 1419 lun = CAM_LUN_WILDCARD; 1420 tag = SCB_LIST_NULL; 1421 1422 switch (scb->hscb->task_management) { 1423 case SIU_TASKMGMT_ABORT_TASK: 1424 tag = SCB_GET_TAG(scb); 1425 case SIU_TASKMGMT_ABORT_TASK_SET: 1426 case SIU_TASKMGMT_CLEAR_TASK_SET: 1427 lun = scb->hscb->lun; 1428 error = CAM_REQ_ABORTED; 1429 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 1430 'A', lun, tag, ROLE_INITIATOR, 1431 error); 1432 break; 1433 case SIU_TASKMGMT_LUN_RESET: 1434 lun = scb->hscb->lun; 1435 case SIU_TASKMGMT_TARGET_RESET: 1436 { 1437 struct ahd_devinfo devinfo; 1438 1439 ahd_scb_devinfo(ahd, &devinfo, scb); 1440 error = CAM_BDR_SENT; 1441 ahd_handle_devreset(ahd, &devinfo, lun, 1442 CAM_BDR_SENT, 1443 lun != CAM_LUN_WILDCARD 1444 ? "Lun Reset" 1445 : "Target Reset", 1446 /*verbose_level*/0); 1447 break; 1448 } 1449 default: 1450 panic("Unexpected TaskMgmt Func\n"); 1451 break; 1452 } 1453 } 1454 break; 1455 } 1456 case TASKMGMT_CMD_CMPLT_OKAY: 1457 { 1458 u_int scbid; 1459 struct scb *scb; 1460 1461 /* 1462 * An ABORT TASK TMF failed to be delivered before 1463 * the targeted command completed normally. 1464 */ 1465 scbid = ahd_get_scbptr(ahd); 1466 scb = ahd_lookup_scb(ahd, scbid); 1467 if (scb != NULL) { 1468 /* 1469 * Remove the second instance of this SCB from 1470 * the QINFIFO if it is still there. 1471 */ 1472 ahd_print_path(ahd, scb); 1473 printf("SCB completes before TMF\n"); 1474 /* 1475 * Handle losing the race. Wait until any 1476 * current selection completes. We will then 1477 * set the TMF back to zero in this SCB so that 1478 * the sequencer doesn't bother to issue another 1479 * sequencer interrupt for its completion. 1480 */ 1481 while ((ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0 1482 && (ahd_inb(ahd, SSTAT0) & SELDO) == 0 1483 && (ahd_inb(ahd, SSTAT1) & SELTO) == 0) 1484 ; 1485 ahd_outb(ahd, SCB_TASK_MANAGEMENT, 0); 1486 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 1487 SCB_GET_CHANNEL(ahd, scb), 1488 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1489 ROLE_INITIATOR, /*status*/0, 1490 SEARCH_REMOVE); 1491 } 1492 break; 1493 } 1494 case TRACEPOINT0: 1495 case TRACEPOINT1: 1496 case TRACEPOINT2: 1497 case TRACEPOINT3: 1498 printf("%s: Tracepoint %d\n", ahd_name(ahd), 1499 seqintcode - TRACEPOINT0); 1500 break; 1501 case NO_SEQINT: 1502 break; 1503 case SAW_HWERR: 1504 ahd_handle_hwerrint(ahd); 1505 break; 1506 default: 1507 printf("%s: Unexpected SEQINTCODE %d\n", ahd_name(ahd), 1508 seqintcode); 1509 break; 1510 } 1511 /* 1512 * The sequencer is paused immediately on 1513 * a SEQINT, so we should restart it when 1514 * we're done. 1515 */ 1516 ahd_unpause(ahd); 1517 } 1518 1519 void 1520 ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat) 1521 { 1522 struct scb *scb; 1523 u_int status0; 1524 u_int status3; 1525 u_int status; 1526 u_int lqistat1; 1527 u_int lqostat0; 1528 u_int scbid; 1529 u_int busfreetime; 1530 1531 ahd_update_modes(ahd); 1532 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1533 1534 status3 = ahd_inb(ahd, SSTAT3) & (NTRAMPERR|OSRAMPERR); 1535 status0 = ahd_inb(ahd, SSTAT0) & (IOERR|OVERRUN|SELDI|SELDO); 1536 status = ahd_inb(ahd, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 1537 lqistat1 = ahd_inb(ahd, LQISTAT1); 1538 lqostat0 = ahd_inb(ahd, LQOSTAT0); 1539 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; 1540 if ((status0 & (SELDI|SELDO)) != 0) { 1541 u_int simode0; 1542 1543 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 1544 simode0 = ahd_inb(ahd, SIMODE0); 1545 status0 &= simode0 & (IOERR|OVERRUN|SELDI|SELDO); 1546 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1547 } 1548 scbid = ahd_get_scbptr(ahd); 1549 scb = ahd_lookup_scb(ahd, scbid); 1550 if (scb != NULL 1551 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1552 scb = NULL; 1553 1554 if ((status0 & IOERR) != 0) { 1555 u_int now_lvd; 1556 1557 now_lvd = ahd_inb(ahd, SBLKCTL) & ENAB40; 1558 printf("%s: Transceiver State Has Changed to %s mode\n", 1559 ahd_name(ahd), now_lvd ? "LVD" : "SE"); 1560 ahd_outb(ahd, CLRSINT0, CLRIOERR); 1561 /* 1562 * A change in I/O mode is equivalent to a bus reset. 1563 */ 1564 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1565 ahd_pause(ahd); 1566 ahd_setup_iocell_workaround(ahd); 1567 ahd_unpause(ahd); 1568 } else if ((status0 & OVERRUN) != 0) { 1569 1570 printf("%s: SCSI offset overrun detected. Resetting bus.\n", 1571 ahd_name(ahd)); 1572 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1573 } else if ((status & SCSIRSTI) != 0) { 1574 1575 printf("%s: Someone reset channel A\n", ahd_name(ahd)); 1576 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE); 1577 } else if ((status & SCSIPERR) != 0) { 1578 1579 /* Make sure the sequencer is in a safe location. */ 1580 ahd_clear_critical_section(ahd); 1581 1582 ahd_handle_transmission_error(ahd); 1583 } else if (lqostat0 != 0) { 1584 1585 printf("%s: lqostat0 == 0x%x!\n", ahd_name(ahd), lqostat0); 1586 ahd_outb(ahd, CLRLQOINT0, lqostat0); 1587 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) 1588 ahd_outb(ahd, CLRLQOINT1, 0); 1589 } else if ((status & SELTO) != 0) { 1590 u_int scbid; 1591 1592 /* Stop the selection */ 1593 ahd_outb(ahd, SCSISEQ0, 0); 1594 1595 /* Make sure the sequencer is in a safe location. */ 1596 ahd_clear_critical_section(ahd); 1597 1598 /* No more pending messages */ 1599 ahd_clear_msg_state(ahd); 1600 1601 /* Clear interrupt state */ 1602 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1603 1604 /* 1605 * Although the driver does not care about the 1606 * 'Selection in Progress' status bit, the busy 1607 * LED does. SELINGO is only cleared by a sucessfull 1608 * selection, so we must manually clear it to insure 1609 * the LED turns off just incase no future successful 1610 * selections occur (e.g. no devices on the bus). 1611 */ 1612 ahd_outb(ahd, CLRSINT0, CLRSELINGO); 1613 1614 scbid = ahd_inw(ahd, WAITING_TID_HEAD); 1615 scb = ahd_lookup_scb(ahd, scbid); 1616 if (scb == NULL) { 1617 printf("%s: ahd_intr - referenced scb not " 1618 "valid during SELTO scb(0x%x)\n", 1619 ahd_name(ahd), scbid); 1620 ahd_dump_card_state(ahd); 1621 } else { 1622 struct ahd_devinfo devinfo; 1623 #ifdef AHD_DEBUG 1624 if ((ahd_debug & AHD_SHOW_SELTO) != 0) { 1625 ahd_print_path(ahd, scb); 1626 printf("Saw Selection Timeout for SCB 0x%x\n", 1627 scbid); 1628 } 1629 #endif 1630 ahd_scb_devinfo(ahd, &devinfo, scb); 1631 aic_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1632 ahd_freeze_devq(ahd, scb); 1633 1634 /* 1635 * Cancel any pending transactions on the device 1636 * now that it seems to be missing. This will 1637 * also revert us to async/narrow transfers until 1638 * we can renegotiate with the device. 1639 */ 1640 ahd_handle_devreset(ahd, &devinfo, 1641 CAM_LUN_WILDCARD, 1642 CAM_SEL_TIMEOUT, 1643 "Selection Timeout", 1644 /*verbose_level*/1); 1645 } 1646 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1647 ahd_iocell_first_selection(ahd); 1648 ahd_unpause(ahd); 1649 } else if ((status0 & (SELDI|SELDO)) != 0) { 1650 1651 ahd_iocell_first_selection(ahd); 1652 ahd_unpause(ahd); 1653 } else if (status3 != 0) { 1654 printf("%s: SCSI Cell parity error SSTAT3 == 0x%x\n", 1655 ahd_name(ahd), status3); 1656 ahd_outb(ahd, CLRSINT3, status3); 1657 } else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) { 1658 1659 /* Make sure the sequencer is in a safe location. */ 1660 ahd_clear_critical_section(ahd); 1661 1662 ahd_handle_lqiphase_error(ahd, lqistat1); 1663 } else if ((lqistat1 & LQICRCI_NLQ) != 0) { 1664 /* 1665 * This status can be delayed during some 1666 * streaming operations. The SCSIPHASE 1667 * handler has already dealt with this case 1668 * so just clear the error. 1669 */ 1670 ahd_outb(ahd, CLRLQIINT1, CLRLQICRCI_NLQ); 1671 } else if ((status & BUSFREE) != 0) { 1672 u_int lqostat1; 1673 int restart; 1674 int clear_fifo; 1675 int packetized; 1676 u_int mode; 1677 1678 /* 1679 * Clear our selection hardware as soon as possible. 1680 * We may have an entry in the waiting Q for this target, 1681 * that is affected by this busfree and we don't want to 1682 * go about selecting the target while we handle the event. 1683 */ 1684 ahd_outb(ahd, SCSISEQ0, 0); 1685 1686 /* Make sure the sequencer is in a safe location. */ 1687 ahd_clear_critical_section(ahd); 1688 1689 /* 1690 * Determine what we were up to at the time of 1691 * the busfree. 1692 */ 1693 mode = AHD_MODE_SCSI; 1694 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; 1695 lqostat1 = ahd_inb(ahd, LQOSTAT1); 1696 switch (busfreetime) { 1697 case BUSFREE_DFF0: 1698 case BUSFREE_DFF1: 1699 { 1700 u_int scbid; 1701 struct scb *scb; 1702 1703 mode = busfreetime == BUSFREE_DFF0 1704 ? AHD_MODE_DFF0 : AHD_MODE_DFF1; 1705 ahd_set_modes(ahd, mode, mode); 1706 scbid = ahd_get_scbptr(ahd); 1707 scb = ahd_lookup_scb(ahd, scbid); 1708 if (scb == NULL) { 1709 printf("%s: Invalid SCB %d in DFF%d " 1710 "during unexpected busfree\n", 1711 ahd_name(ahd), scbid, mode); 1712 packetized = 0; 1713 } else 1714 packetized = (scb->flags & SCB_PACKETIZED) != 0; 1715 clear_fifo = 1; 1716 break; 1717 } 1718 case BUSFREE_LQO: 1719 clear_fifo = 0; 1720 packetized = 1; 1721 break; 1722 default: 1723 clear_fifo = 0; 1724 packetized = (lqostat1 & LQOBUSFREE) != 0; 1725 if (!packetized 1726 && ahd_inb(ahd, LASTPHASE) == P_BUSFREE 1727 && (ahd_inb(ahd, SSTAT0) & SELDI) == 0 1728 && ((ahd_inb(ahd, SSTAT0) & SELDO) == 0 1729 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) == 0)) 1730 /* 1731 * Assume packetized if we are not 1732 * on the bus in a non-packetized 1733 * capacity and any pending selection 1734 * was a packetized selection. 1735 */ 1736 packetized = 1; 1737 break; 1738 } 1739 1740 #ifdef AHD_DEBUG 1741 if ((ahd_debug & AHD_SHOW_MISC) != 0) 1742 printf("Saw Busfree. Busfreetime = 0x%x.\n", 1743 busfreetime); 1744 #endif 1745 /* 1746 * Busfrees that occur in non-packetized phases are 1747 * handled by the nonpkt_busfree handler. 1748 */ 1749 if (packetized && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) { 1750 restart = ahd_handle_pkt_busfree(ahd, busfreetime); 1751 } else { 1752 packetized = 0; 1753 restart = ahd_handle_nonpkt_busfree(ahd); 1754 } 1755 /* 1756 * Clear the busfree interrupt status. The setting of 1757 * the interrupt is a pulse, so in a perfect world, we 1758 * would not need to muck with the ENBUSFREE logic. This 1759 * would ensure that if the bus moves on to another 1760 * connection, busfree protection is still in force. If 1761 * BUSFREEREV is broken, however, we must manually clear 1762 * the ENBUSFREE if the busfree occurred during a non-pack 1763 * connection so that we don't get false positives during 1764 * future, packetized, connections. 1765 */ 1766 ahd_outb(ahd, CLRSINT1, CLRBUSFREE); 1767 if (packetized == 0 1768 && (ahd->bugs & AHD_BUSFREEREV_BUG) != 0) 1769 ahd_outb(ahd, SIMODE1, 1770 ahd_inb(ahd, SIMODE1) & ~ENBUSFREE); 1771 1772 if (clear_fifo) 1773 ahd_clear_fifo(ahd, mode); 1774 1775 ahd_clear_msg_state(ahd); 1776 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1777 if (restart) { 1778 ahd_restart(ahd); 1779 } else { 1780 ahd_unpause(ahd); 1781 } 1782 } else { 1783 printf("%s: Missing case in ahd_handle_scsiint. status = %x\n", 1784 ahd_name(ahd), status); 1785 ahd_dump_card_state(ahd); 1786 ahd_clear_intstat(ahd); 1787 ahd_unpause(ahd); 1788 } 1789 } 1790 1791 static void 1792 ahd_handle_transmission_error(struct ahd_softc *ahd) 1793 { 1794 struct scb *scb; 1795 u_int scbid; 1796 u_int lqistat1; 1797 u_int lqistat2; 1798 u_int msg_out; 1799 u_int curphase; 1800 u_int lastphase; 1801 u_int perrdiag; 1802 u_int cur_col; 1803 int silent; 1804 1805 scb = NULL; 1806 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1807 lqistat1 = ahd_inb(ahd, LQISTAT1) & ~(LQIPHASE_LQ|LQIPHASE_NLQ); 1808 lqistat2 = ahd_inb(ahd, LQISTAT2); 1809 if ((lqistat1 & (LQICRCI_NLQ|LQICRCI_LQ)) == 0 1810 && (ahd->bugs & AHD_NLQICRC_DELAYED_BUG) != 0) { 1811 u_int lqistate; 1812 1813 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 1814 lqistate = ahd_inb(ahd, LQISTATE); 1815 if ((lqistate >= 0x1E && lqistate <= 0x24) 1816 || (lqistate == 0x29)) { 1817 #ifdef AHD_DEBUG 1818 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1819 printf("%s: NLQCRC found via LQISTATE\n", 1820 ahd_name(ahd)); 1821 } 1822 #endif 1823 lqistat1 |= LQICRCI_NLQ; 1824 } 1825 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1826 } 1827 1828 ahd_outb(ahd, CLRLQIINT1, lqistat1); 1829 lastphase = ahd_inb(ahd, LASTPHASE); 1830 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1831 perrdiag = ahd_inb(ahd, PERRDIAG); 1832 msg_out = MSG_INITIATOR_DET_ERR; 1833 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR); 1834 1835 /* 1836 * Try to find the SCB associated with this error. 1837 */ 1838 silent = FALSE; 1839 if (lqistat1 == 0 1840 || (lqistat1 & LQICRCI_NLQ) != 0) { 1841 if ((lqistat1 & (LQICRCI_NLQ|LQIOVERI_NLQ)) != 0) 1842 ahd_set_active_fifo(ahd); 1843 scbid = ahd_get_scbptr(ahd); 1844 scb = ahd_lookup_scb(ahd, scbid); 1845 if (scb != NULL && SCB_IS_SILENT(scb)) 1846 silent = TRUE; 1847 } 1848 1849 cur_col = 0; 1850 if (silent == FALSE) { 1851 printf("%s: Transmission error detected\n", ahd_name(ahd)); 1852 ahd_lqistat1_print(lqistat1, &cur_col, 50); 1853 ahd_lastphase_print(lastphase, &cur_col, 50); 1854 ahd_scsisigi_print(curphase, &cur_col, 50); 1855 ahd_perrdiag_print(perrdiag, &cur_col, 50); 1856 printf("\n"); 1857 ahd_dump_card_state(ahd); 1858 } 1859 1860 if ((lqistat1 & (LQIOVERI_LQ|LQIOVERI_NLQ)) != 0) { 1861 if (silent == FALSE) { 1862 printf("%s: Gross protocol error during incoming " 1863 "packet. lqistat1 == 0x%x. Resetting bus.\n", 1864 ahd_name(ahd), lqistat1); 1865 } 1866 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1867 return; 1868 } else if ((lqistat1 & LQICRCI_LQ) != 0) { 1869 /* 1870 * A CRC error has been detected on an incoming LQ. 1871 * The bus is currently hung on the last ACK. 1872 * Hit LQIRETRY to release the last ack, and 1873 * wait for the sequencer to determine that ATNO 1874 * is asserted while in message out to take us 1875 * to our host message loop. No NONPACKREQ or 1876 * LQIPHASE type errors will occur in this 1877 * scenario. After this first LQIRETRY, the LQI 1878 * manager will be in ISELO where it will 1879 * happily sit until another packet phase begins. 1880 * Unexpected bus free detection is enabled 1881 * through any phases that occur after we release 1882 * this last ack until the LQI manager sees a 1883 * packet phase. This implies we may have to 1884 * ignore a perfectly valid "unexected busfree" 1885 * after our "initiator detected error" message is 1886 * sent. A busfree is the expected response after 1887 * we tell the target that it's L_Q was corrupted. 1888 * (SPI4R09 10.7.3.3.3) 1889 */ 1890 ahd_outb(ahd, LQCTL2, LQIRETRY); 1891 printf("LQIRetry for LQICRCI_LQ to release ACK\n"); 1892 } else if ((lqistat1 & LQICRCI_NLQ) != 0) { 1893 /* 1894 * We detected a CRC error in a NON-LQ packet. 1895 * The hardware has varying behavior in this situation 1896 * depending on whether this packet was part of a 1897 * stream or not. 1898 * 1899 * PKT by PKT mode: 1900 * The hardware has already acked the complete packet. 1901 * If the target honors our outstanding ATN condition, 1902 * we should be (or soon will be) in MSGOUT phase. 1903 * This will trigger the LQIPHASE_LQ status bit as the 1904 * hardware was expecting another LQ. Unexpected 1905 * busfree detection is enabled. Once LQIPHASE_LQ is 1906 * true (first entry into host message loop is much 1907 * the same), we must clear LQIPHASE_LQ and hit 1908 * LQIRETRY so the hardware is ready to handle 1909 * a future LQ. NONPACKREQ will not be asserted again 1910 * once we hit LQIRETRY until another packet is 1911 * processed. The target may either go busfree 1912 * or start another packet in response to our message. 1913 * 1914 * Read Streaming P0 asserted: 1915 * If we raise ATN and the target completes the entire 1916 * stream (P0 asserted during the last packet), the 1917 * hardware will ack all data and return to the ISTART 1918 * state. When the target reponds to our ATN condition, 1919 * LQIPHASE_LQ will be asserted. We should respond to 1920 * this with an LQIRETRY to prepare for any future 1921 * packets. NONPACKREQ will not be asserted again 1922 * once we hit LQIRETRY until another packet is 1923 * processed. The target may either go busfree or 1924 * start another packet in response to our message. 1925 * Busfree detection is enabled. 1926 * 1927 * Read Streaming P0 not asserted: 1928 * If we raise ATN and the target transitions to 1929 * MSGOUT in or after a packet where P0 is not 1930 * asserted, the hardware will assert LQIPHASE_NLQ. 1931 * We should respond to the LQIPHASE_NLQ with an 1932 * LQIRETRY. Should the target stay in a non-pkt 1933 * phase after we send our message, the hardware 1934 * will assert LQIPHASE_LQ. Recovery is then just as 1935 * listed above for the read streaming with P0 asserted. 1936 * Busfree detection is enabled. 1937 */ 1938 if (silent == FALSE) 1939 printf("LQICRC_NLQ\n"); 1940 if (scb == NULL) { 1941 printf("%s: No SCB valid for LQICRC_NLQ. " 1942 "Resetting bus\n", ahd_name(ahd)); 1943 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1944 return; 1945 } 1946 } else if ((lqistat1 & LQIBADLQI) != 0) { 1947 printf("Need to handle BADLQI!\n"); 1948 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1949 return; 1950 } else if ((perrdiag & (PARITYERR|PREVPHASE)) == PARITYERR) { 1951 if ((curphase & ~P_DATAIN_DT) != 0) { 1952 /* Ack the byte. So we can continue. */ 1953 if (silent == FALSE) 1954 printf("Acking %s to clear perror\n", 1955 ahd_lookup_phase_entry(curphase)->phasemsg); 1956 ahd_inb(ahd, SCSIDAT); 1957 } 1958 1959 if (curphase == P_MESGIN) 1960 msg_out = MSG_PARITY_ERROR; 1961 } 1962 1963 /* 1964 * We've set the hardware to assert ATN if we 1965 * get a parity error on "in" phases, so all we 1966 * need to do is stuff the message buffer with 1967 * the appropriate message. "In" phases have set 1968 * mesg_out to something other than MSG_NOP. 1969 */ 1970 ahd->send_msg_perror = msg_out; 1971 if (scb != NULL && msg_out == MSG_INITIATOR_DET_ERR) 1972 scb->flags |= SCB_TRANSMISSION_ERROR; 1973 ahd_outb(ahd, MSG_OUT, HOST_MSG); 1974 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1975 ahd_unpause(ahd); 1976 } 1977 1978 static void 1979 ahd_handle_lqiphase_error(struct ahd_softc *ahd, u_int lqistat1) 1980 { 1981 /* 1982 * Clear the sources of the interrupts. 1983 */ 1984 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1985 ahd_outb(ahd, CLRLQIINT1, lqistat1); 1986 1987 /* 1988 * If the "illegal" phase changes were in response 1989 * to our ATN to flag a CRC error, AND we ended up 1990 * on packet boundaries, clear the error, restart the 1991 * LQI manager as appropriate, and go on our merry 1992 * way toward sending the message. Otherwise, reset 1993 * the bus to clear the error. 1994 */ 1995 ahd_set_active_fifo(ahd); 1996 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0 1997 && (ahd_inb(ahd, MDFFSTAT) & DLZERO) != 0) { 1998 if ((lqistat1 & LQIPHASE_LQ) != 0) { 1999 printf("LQIRETRY for LQIPHASE_LQ\n"); 2000 ahd_outb(ahd, LQCTL2, LQIRETRY); 2001 } else if ((lqistat1 & LQIPHASE_NLQ) != 0) { 2002 printf("LQIRETRY for LQIPHASE_NLQ\n"); 2003 ahd_outb(ahd, LQCTL2, LQIRETRY); 2004 } else 2005 panic("ahd_handle_lqiphase_error: No phase errors\n"); 2006 ahd_dump_card_state(ahd); 2007 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2008 ahd_unpause(ahd); 2009 } else { 2010 printf("Reseting Channel for LQI Phase error\n"); 2011 ahd_dump_card_state(ahd); 2012 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 2013 } 2014 } 2015 2016 /* 2017 * Packetized unexpected or expected busfree. 2018 * Entered in mode based on busfreetime. 2019 */ 2020 static int 2021 ahd_handle_pkt_busfree(struct ahd_softc *ahd, u_int busfreetime) 2022 { 2023 u_int lqostat1; 2024 2025 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 2026 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 2027 lqostat1 = ahd_inb(ahd, LQOSTAT1); 2028 if ((lqostat1 & LQOBUSFREE) != 0) { 2029 struct scb *scb; 2030 u_int scbid; 2031 u_int saved_scbptr; 2032 u_int waiting_h; 2033 u_int waiting_t; 2034 u_int next; 2035 2036 if ((busfreetime & BUSFREE_LQO) == 0) 2037 printf("%s: Warning, BUSFREE time is 0x%x. " 2038 "Expected BUSFREE_LQO.\n", 2039 ahd_name(ahd), busfreetime); 2040 /* 2041 * The LQO manager detected an unexpected busfree 2042 * either: 2043 * 2044 * 1) During an outgoing LQ. 2045 * 2) After an outgoing LQ but before the first 2046 * REQ of the command packet. 2047 * 3) During an outgoing command packet. 2048 * 2049 * In all cases, CURRSCB is pointing to the 2050 * SCB that encountered the failure. Clean 2051 * up the queue, clear SELDO and LQOBUSFREE, 2052 * and allow the sequencer to restart the select 2053 * out at its lesure. 2054 */ 2055 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2056 scbid = ahd_inw(ahd, CURRSCB); 2057 scb = ahd_lookup_scb(ahd, scbid); 2058 if (scb == NULL) 2059 panic("SCB not valid during LQOBUSFREE"); 2060 /* 2061 * Clear the status. 2062 */ 2063 ahd_outb(ahd, CLRLQOINT1, CLRLQOBUSFREE); 2064 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) 2065 ahd_outb(ahd, CLRLQOINT1, 0); 2066 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 2067 ahd_flush_device_writes(ahd); 2068 ahd_outb(ahd, CLRSINT0, CLRSELDO); 2069 2070 /* 2071 * Return the LQO manager to its idle loop. It will 2072 * not do this automatically if the busfree occurs 2073 * after the first REQ of either the LQ or command 2074 * packet or between the LQ and command packet. 2075 */ 2076 ahd_outb(ahd, LQCTL2, ahd_inb(ahd, LQCTL2) | LQOTOIDLE); 2077 2078 /* 2079 * Update the waiting for selection queue so 2080 * we restart on the correct SCB. 2081 */ 2082 waiting_h = ahd_inw(ahd, WAITING_TID_HEAD); 2083 saved_scbptr = ahd_get_scbptr(ahd); 2084 if (waiting_h != scbid) { 2085 2086 ahd_outw(ahd, WAITING_TID_HEAD, scbid); 2087 waiting_t = ahd_inw(ahd, WAITING_TID_TAIL); 2088 if (waiting_t == waiting_h) { 2089 ahd_outw(ahd, WAITING_TID_TAIL, scbid); 2090 next = SCB_LIST_NULL; 2091 } else { 2092 ahd_set_scbptr(ahd, waiting_h); 2093 next = ahd_inw_scbram(ahd, SCB_NEXT2); 2094 } 2095 ahd_set_scbptr(ahd, scbid); 2096 ahd_outw(ahd, SCB_NEXT2, next); 2097 } 2098 ahd_set_scbptr(ahd, saved_scbptr); 2099 if (scb->crc_retry_count < AHD_MAX_LQ_CRC_ERRORS) { 2100 if (SCB_IS_SILENT(scb) == FALSE) { 2101 ahd_print_path(ahd, scb); 2102 printf("Probable outgoing LQ CRC error. " 2103 "Retrying command\n"); 2104 } 2105 scb->crc_retry_count++; 2106 } else { 2107 aic_set_transaction_status(scb, CAM_UNCOR_PARITY); 2108 aic_freeze_scb(scb); 2109 ahd_freeze_devq(ahd, scb); 2110 } 2111 /* Return unpausing the sequencer. */ 2112 return (0); 2113 } else if ((ahd_inb(ahd, PERRDIAG) & PARITYERR) != 0) { 2114 /* 2115 * Ignore what are really parity errors that 2116 * occur on the last REQ of a free running 2117 * clock prior to going busfree. Some drives 2118 * do not properly active negate just before 2119 * going busfree resulting in a parity glitch. 2120 */ 2121 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR|CLRBUSFREE); 2122 #ifdef AHD_DEBUG 2123 if ((ahd_debug & AHD_SHOW_MASKED_ERRORS) != 0) 2124 printf("%s: Parity on last REQ detected " 2125 "during busfree phase.\n", 2126 ahd_name(ahd)); 2127 #endif 2128 /* Return unpausing the sequencer. */ 2129 return (0); 2130 } 2131 if (ahd->src_mode != AHD_MODE_SCSI) { 2132 u_int scbid; 2133 struct scb *scb; 2134 2135 scbid = ahd_get_scbptr(ahd); 2136 scb = ahd_lookup_scb(ahd, scbid); 2137 ahd_print_path(ahd, scb); 2138 printf("Unexpected PKT busfree condition\n"); 2139 ahd_dump_card_state(ahd); 2140 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 'A', 2141 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 2142 ROLE_INITIATOR, CAM_UNEXP_BUSFREE); 2143 2144 /* Return restarting the sequencer. */ 2145 return (1); 2146 } 2147 printf("%s: Unexpected PKT busfree condition\n", ahd_name(ahd)); 2148 ahd_dump_card_state(ahd); 2149 /* Restart the sequencer. */ 2150 return (1); 2151 } 2152 2153 /* 2154 * Non-packetized unexpected or expected busfree. 2155 */ 2156 static int 2157 ahd_handle_nonpkt_busfree(struct ahd_softc *ahd) 2158 { 2159 struct ahd_devinfo devinfo; 2160 struct scb *scb; 2161 u_int lastphase; 2162 u_int saved_scsiid; 2163 u_int saved_lun; 2164 u_int target; 2165 u_int initiator_role_id; 2166 u_int scbid; 2167 u_int ppr_busfree; 2168 int printerror; 2169 2170 /* 2171 * Look at what phase we were last in. If its message out, 2172 * chances are pretty good that the busfree was in response 2173 * to one of our abort requests. 2174 */ 2175 lastphase = ahd_inb(ahd, LASTPHASE); 2176 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); 2177 saved_lun = ahd_inb(ahd, SAVED_LUN); 2178 target = SCSIID_TARGET(ahd, saved_scsiid); 2179 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 2180 ahd_compile_devinfo(&devinfo, initiator_role_id, 2181 target, saved_lun, 'A', ROLE_INITIATOR); 2182 printerror = 1; 2183 2184 scbid = ahd_get_scbptr(ahd); 2185 scb = ahd_lookup_scb(ahd, scbid); 2186 if (scb != NULL 2187 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 2188 scb = NULL; 2189 2190 ppr_busfree = (ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0; 2191 if (lastphase == P_MESGOUT) { 2192 u_int tag; 2193 2194 tag = SCB_LIST_NULL; 2195 if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT_TAG, TRUE) 2196 || ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT, TRUE)) { 2197 int found; 2198 int sent_msg; 2199 2200 if (scb == NULL) { 2201 ahd_print_devinfo(ahd, &devinfo); 2202 printf("Abort for unidentified " 2203 "connection completed.\n"); 2204 /* restart the sequencer. */ 2205 return (1); 2206 } 2207 sent_msg = ahd->msgout_buf[ahd->msgout_index - 1]; 2208 ahd_print_path(ahd, scb); 2209 printf("SCB %d - Abort%s Completed.\n", 2210 SCB_GET_TAG(scb), 2211 sent_msg == MSG_ABORT_TAG ? "" : " Tag"); 2212 2213 if (sent_msg == MSG_ABORT_TAG) 2214 tag = SCB_GET_TAG(scb); 2215 2216 if ((scb->flags & SCB_CMDPHASE_ABORT) != 0) { 2217 /* 2218 * This abort is in response to an 2219 * unexpected switch to command phase 2220 * for a packetized connection. Since 2221 * the identify message was never sent, 2222 * "saved lun" is 0. We really want to 2223 * abort only the SCB that encountered 2224 * this error, which could have a different 2225 * lun. The SCB will be retried so the OS 2226 * will see the UA after renegotiating to 2227 * packetized. 2228 */ 2229 tag = SCB_GET_TAG(scb); 2230 saved_lun = scb->hscb->lun; 2231 } 2232 found = ahd_abort_scbs(ahd, target, 'A', saved_lun, 2233 tag, ROLE_INITIATOR, 2234 CAM_REQ_ABORTED); 2235 printf("found == 0x%x\n", found); 2236 printerror = 0; 2237 } else if (ahd_sent_msg(ahd, AHDMSG_1B, 2238 MSG_BUS_DEV_RESET, TRUE)) { 2239 #ifdef __FreeBSD__ 2240 /* 2241 * Don't mark the user's request for this BDR 2242 * as completing with CAM_BDR_SENT. CAM3 2243 * specifies CAM_REQ_CMP. 2244 */ 2245 if (scb != NULL 2246 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 2247 && ahd_match_scb(ahd, scb, target, 'A', 2248 CAM_LUN_WILDCARD, SCB_LIST_NULL, 2249 ROLE_INITIATOR)) 2250 aic_set_transaction_status(scb, CAM_REQ_CMP); 2251 #endif 2252 ahd_handle_devreset(ahd, &devinfo, CAM_LUN_WILDCARD, 2253 CAM_BDR_SENT, "Bus Device Reset", 2254 /*verbose_level*/0); 2255 printerror = 0; 2256 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, FALSE) 2257 && ppr_busfree == 0) { 2258 struct ahd_initiator_tinfo *tinfo; 2259 struct ahd_tmode_tstate *tstate; 2260 2261 /* 2262 * PPR Rejected. Try non-ppr negotiation 2263 * and retry command. 2264 */ 2265 #ifdef AHD_DEBUG 2266 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2267 printf("PPR negotiation rejected busfree.\n"); 2268 #endif 2269 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel, 2270 devinfo.our_scsiid, 2271 devinfo.target, &tstate); 2272 tinfo->curr.transport_version = 2; 2273 tinfo->goal.transport_version = 2; 2274 tinfo->goal.ppr_options = 0; 2275 ahd_qinfifo_requeue_tail(ahd, scb); 2276 printerror = 0; 2277 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, FALSE) 2278 && ppr_busfree == 0) { 2279 /* 2280 * Negotiation Rejected. Go-narrow and 2281 * retry command. 2282 */ 2283 #ifdef AHD_DEBUG 2284 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2285 printf("WDTR negotiation rejected busfree.\n"); 2286 #endif 2287 ahd_set_width(ahd, &devinfo, 2288 MSG_EXT_WDTR_BUS_8_BIT, 2289 AHD_TRANS_CUR|AHD_TRANS_GOAL, 2290 /*paused*/TRUE); 2291 ahd_qinfifo_requeue_tail(ahd, scb); 2292 printerror = 0; 2293 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, FALSE) 2294 && ppr_busfree == 0) { 2295 /* 2296 * Negotiation Rejected. Go-async and 2297 * retry command. 2298 */ 2299 #ifdef AHD_DEBUG 2300 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2301 printf("SDTR negotiation rejected busfree.\n"); 2302 #endif 2303 ahd_set_syncrate(ahd, &devinfo, 2304 /*period*/0, /*offset*/0, 2305 /*ppr_options*/0, 2306 AHD_TRANS_CUR|AHD_TRANS_GOAL, 2307 /*paused*/TRUE); 2308 ahd_qinfifo_requeue_tail(ahd, scb); 2309 printerror = 0; 2310 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_IDE_BUSFREE) != 0 2311 && ahd_sent_msg(ahd, AHDMSG_1B, 2312 MSG_INITIATOR_DET_ERR, TRUE)) { 2313 2314 #ifdef AHD_DEBUG 2315 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2316 printf("Expected IDE Busfree\n"); 2317 #endif 2318 printerror = 0; 2319 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_QASREJ_BUSFREE) 2320 && ahd_sent_msg(ahd, AHDMSG_1B, 2321 MSG_MESSAGE_REJECT, TRUE)) { 2322 2323 #ifdef AHD_DEBUG 2324 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2325 printf("Expected QAS Reject Busfree\n"); 2326 #endif 2327 printerror = 0; 2328 } 2329 } 2330 2331 /* 2332 * The busfree required flag is honored at the end of 2333 * the message phases. We check it last in case we 2334 * had to send some other message that caused a busfree. 2335 */ 2336 if (printerror != 0 2337 && (lastphase == P_MESGIN || lastphase == P_MESGOUT) 2338 && ((ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0)) { 2339 2340 ahd_freeze_devq(ahd, scb); 2341 aic_set_transaction_status(scb, CAM_REQUEUE_REQ); 2342 aic_freeze_scb(scb); 2343 if ((ahd->msg_flags & MSG_FLAG_IU_REQ_CHANGED) != 0) { 2344 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 2345 SCB_GET_CHANNEL(ahd, scb), 2346 SCB_GET_LUN(scb), SCB_LIST_NULL, 2347 ROLE_INITIATOR, CAM_REQ_ABORTED); 2348 } else { 2349 #ifdef AHD_DEBUG 2350 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2351 printf("PPR Negotiation Busfree.\n"); 2352 #endif 2353 ahd_done(ahd, scb); 2354 } 2355 printerror = 0; 2356 } 2357 if (printerror != 0) { 2358 int aborted; 2359 2360 aborted = 0; 2361 if (scb != NULL) { 2362 u_int tag; 2363 2364 if ((scb->hscb->control & TAG_ENB) != 0) 2365 tag = SCB_GET_TAG(scb); 2366 else 2367 tag = SCB_LIST_NULL; 2368 ahd_print_path(ahd, scb); 2369 aborted = ahd_abort_scbs(ahd, target, 'A', 2370 SCB_GET_LUN(scb), tag, 2371 ROLE_INITIATOR, 2372 CAM_UNEXP_BUSFREE); 2373 } else { 2374 /* 2375 * We had not fully identified this connection, 2376 * so we cannot abort anything. 2377 */ 2378 printf("%s: ", ahd_name(ahd)); 2379 } 2380 if (lastphase != P_BUSFREE) 2381 ahd_force_renegotiation(ahd, &devinfo); 2382 printf("Unexpected busfree %s, %d SCBs aborted, " 2383 "PRGMCNT == 0x%x\n", 2384 ahd_lookup_phase_entry(lastphase)->phasemsg, 2385 aborted, 2386 ahd_inw(ahd, PRGMCNT)); 2387 ahd_dump_card_state(ahd); 2388 } 2389 /* Always restart the sequencer. */ 2390 return (1); 2391 } 2392 2393 static void 2394 ahd_handle_proto_violation(struct ahd_softc *ahd) 2395 { 2396 struct ahd_devinfo devinfo; 2397 struct scb *scb; 2398 u_int scbid; 2399 u_int seq_flags; 2400 u_int curphase; 2401 u_int lastphase; 2402 int found; 2403 2404 ahd_fetch_devinfo(ahd, &devinfo); 2405 scbid = ahd_get_scbptr(ahd); 2406 scb = ahd_lookup_scb(ahd, scbid); 2407 seq_flags = ahd_inb(ahd, SEQ_FLAGS); 2408 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 2409 lastphase = ahd_inb(ahd, LASTPHASE); 2410 if ((seq_flags & NOT_IDENTIFIED) != 0) { 2411 2412 /* 2413 * The reconnecting target either did not send an 2414 * identify message, or did, but we didn't find an SCB 2415 * to match. 2416 */ 2417 ahd_print_devinfo(ahd, &devinfo); 2418 printf("Target did not send an IDENTIFY message. " 2419 "LASTPHASE = 0x%x.\n", lastphase); 2420 scb = NULL; 2421 } else if (scb == NULL) { 2422 /* 2423 * We don't seem to have an SCB active for this 2424 * transaction. Print an error and reset the bus. 2425 */ 2426 ahd_print_devinfo(ahd, &devinfo); 2427 printf("No SCB found during protocol violation\n"); 2428 goto proto_violation_reset; 2429 } else { 2430 aic_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 2431 if ((seq_flags & NO_CDB_SENT) != 0) { 2432 ahd_print_path(ahd, scb); 2433 printf("No or incomplete CDB sent to device.\n"); 2434 } else if ((ahd_inb_scbram(ahd, SCB_CONTROL) 2435 & STATUS_RCVD) == 0) { 2436 /* 2437 * The target never bothered to provide status to 2438 * us prior to completing the command. Since we don't 2439 * know the disposition of this command, we must attempt 2440 * to abort it. Assert ATN and prepare to send an abort 2441 * message. 2442 */ 2443 ahd_print_path(ahd, scb); 2444 printf("Completed command without status.\n"); 2445 } else { 2446 ahd_print_path(ahd, scb); 2447 printf("Unknown protocol violation.\n"); 2448 ahd_dump_card_state(ahd); 2449 } 2450 } 2451 if ((lastphase & ~P_DATAIN_DT) == 0 2452 || lastphase == P_COMMAND) { 2453 proto_violation_reset: 2454 /* 2455 * Target either went directly to data 2456 * phase or didn't respond to our ATN. 2457 * The only safe thing to do is to blow 2458 * it away with a bus reset. 2459 */ 2460 found = ahd_reset_channel(ahd, 'A', TRUE); 2461 printf("%s: Issued Channel %c Bus Reset. " 2462 "%d SCBs aborted\n", ahd_name(ahd), 'A', found); 2463 } else { 2464 /* 2465 * Leave the selection hardware off in case 2466 * this abort attempt will affect yet to 2467 * be sent commands. 2468 */ 2469 ahd_outb(ahd, SCSISEQ0, 2470 ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 2471 ahd_assert_atn(ahd); 2472 ahd_outb(ahd, MSG_OUT, HOST_MSG); 2473 if (scb == NULL) { 2474 ahd_print_devinfo(ahd, &devinfo); 2475 ahd->msgout_buf[0] = MSG_ABORT_TASK; 2476 ahd->msgout_len = 1; 2477 ahd->msgout_index = 0; 2478 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2479 } else { 2480 ahd_print_path(ahd, scb); 2481 scb->flags |= SCB_ABORT; 2482 } 2483 printf("Protocol violation %s. Attempting to abort.\n", 2484 ahd_lookup_phase_entry(curphase)->phasemsg); 2485 } 2486 } 2487 2488 /* 2489 * Force renegotiation to occur the next time we initiate 2490 * a command to the current device. 2491 */ 2492 static void 2493 ahd_force_renegotiation(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 2494 { 2495 struct ahd_initiator_tinfo *targ_info; 2496 struct ahd_tmode_tstate *tstate; 2497 2498 #ifdef AHD_DEBUG 2499 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 2500 ahd_print_devinfo(ahd, devinfo); 2501 printf("Forcing renegotiation\n"); 2502 } 2503 #endif 2504 targ_info = ahd_fetch_transinfo(ahd, 2505 devinfo->channel, 2506 devinfo->our_scsiid, 2507 devinfo->target, 2508 &tstate); 2509 ahd_update_neg_request(ahd, devinfo, tstate, 2510 targ_info, AHD_NEG_IF_NON_ASYNC); 2511 } 2512 2513 #define AHD_MAX_STEPS 2000 2514 void 2515 ahd_clear_critical_section(struct ahd_softc *ahd) 2516 { 2517 ahd_mode_state saved_modes; 2518 int stepping; 2519 int steps; 2520 int first_instr; 2521 u_int simode0; 2522 u_int simode1; 2523 u_int simode3; 2524 u_int lqimode0; 2525 u_int lqimode1; 2526 u_int lqomode0; 2527 u_int lqomode1; 2528 2529 if (ahd->num_critical_sections == 0) 2530 return; 2531 2532 stepping = FALSE; 2533 steps = 0; 2534 first_instr = 0; 2535 simode0 = 0; 2536 simode1 = 0; 2537 simode3 = 0; 2538 lqimode0 = 0; 2539 lqimode1 = 0; 2540 lqomode0 = 0; 2541 lqomode1 = 0; 2542 saved_modes = ahd_save_modes(ahd); 2543 for (;;) { 2544 struct cs *cs; 2545 u_int seqaddr; 2546 u_int i; 2547 2548 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2549 seqaddr = ahd_inw(ahd, CURADDR); 2550 2551 cs = ahd->critical_sections; 2552 for (i = 0; i < ahd->num_critical_sections; i++, cs++) { 2553 2554 if (cs->begin < seqaddr && cs->end >= seqaddr) 2555 break; 2556 } 2557 2558 if (i == ahd->num_critical_sections) 2559 break; 2560 2561 if (steps > AHD_MAX_STEPS) { 2562 printf("%s: Infinite loop in critical section\n" 2563 "%s: First Instruction 0x%x now 0x%x\n", 2564 ahd_name(ahd), ahd_name(ahd), first_instr, 2565 seqaddr); 2566 ahd_dump_card_state(ahd); 2567 panic("critical section loop"); 2568 } 2569 2570 steps++; 2571 #ifdef AHD_DEBUG 2572 if ((ahd_debug & AHD_SHOW_MISC) != 0) 2573 printf("%s: Single stepping at 0x%x\n", ahd_name(ahd), 2574 seqaddr); 2575 #endif 2576 if (stepping == FALSE) { 2577 2578 first_instr = seqaddr; 2579 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 2580 simode0 = ahd_inb(ahd, SIMODE0); 2581 simode3 = ahd_inb(ahd, SIMODE3); 2582 lqimode0 = ahd_inb(ahd, LQIMODE0); 2583 lqimode1 = ahd_inb(ahd, LQIMODE1); 2584 lqomode0 = ahd_inb(ahd, LQOMODE0); 2585 lqomode1 = ahd_inb(ahd, LQOMODE1); 2586 ahd_outb(ahd, SIMODE0, 0); 2587 ahd_outb(ahd, SIMODE3, 0); 2588 ahd_outb(ahd, LQIMODE0, 0); 2589 ahd_outb(ahd, LQIMODE1, 0); 2590 ahd_outb(ahd, LQOMODE0, 0); 2591 ahd_outb(ahd, LQOMODE1, 0); 2592 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2593 simode1 = ahd_inb(ahd, SIMODE1); 2594 /* 2595 * We don't clear ENBUSFREE. Unfortunately 2596 * we cannot re-enable busfree detection within 2597 * the current connection, so we must leave it 2598 * on while single stepping. 2599 */ 2600 ahd_outb(ahd, SIMODE1, simode1 & ENBUSFREE); 2601 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) | STEP); 2602 stepping = TRUE; 2603 } 2604 ahd_outb(ahd, CLRSINT1, CLRBUSFREE); 2605 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2606 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 2607 ahd_outb(ahd, HCNTRL, ahd->unpause); 2608 while (!ahd_is_paused(ahd)) 2609 aic_delay(200); 2610 ahd_update_modes(ahd); 2611 } 2612 if (stepping) { 2613 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 2614 ahd_outb(ahd, SIMODE0, simode0); 2615 ahd_outb(ahd, SIMODE3, simode3); 2616 ahd_outb(ahd, LQIMODE0, lqimode0); 2617 ahd_outb(ahd, LQIMODE1, lqimode1); 2618 ahd_outb(ahd, LQOMODE0, lqomode0); 2619 ahd_outb(ahd, LQOMODE1, lqomode1); 2620 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2621 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP); 2622 ahd_outb(ahd, SIMODE1, simode1); 2623 /* 2624 * SCSIINT seems to glitch occassionally when 2625 * the interrupt masks are restored. Clear SCSIINT 2626 * one more time so that only persistent errors 2627 * are seen as a real interrupt. 2628 */ 2629 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2630 } 2631 ahd_restore_modes(ahd, saved_modes); 2632 } 2633 2634 /* 2635 * Clear any pending interrupt status. 2636 */ 2637 void 2638 ahd_clear_intstat(struct ahd_softc *ahd) 2639 { 2640 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 2641 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 2642 /* Clear any interrupt conditions this may have caused */ 2643 ahd_outb(ahd, CLRLQIINT0, CLRLQIATNQAS|CLRLQICRCT1|CLRLQICRCT2 2644 |CLRLQIBADLQT|CLRLQIATNLQ|CLRLQIATNCMD); 2645 ahd_outb(ahd, CLRLQIINT1, CLRLQIPHASE_LQ|CLRLQIPHASE_NLQ|CLRLIQABORT 2646 |CLRLQICRCI_LQ|CLRLQICRCI_NLQ|CLRLQIBADLQI 2647 |CLRLQIOVERI_LQ|CLRLQIOVERI_NLQ|CLRNONPACKREQ); 2648 ahd_outb(ahd, CLRLQOINT0, CLRLQOTARGSCBPERR|CLRLQOSTOPT2|CLRLQOATNLQ 2649 |CLRLQOATNPKT|CLRLQOTCRC); 2650 ahd_outb(ahd, CLRLQOINT1, CLRLQOINITSCBPERR|CLRLQOSTOPI2|CLRLQOBADQAS 2651 |CLRLQOBUSFREE|CLRLQOPHACHGINPKT); 2652 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 2653 ahd_outb(ahd, CLRLQOINT0, 0); 2654 ahd_outb(ahd, CLRLQOINT1, 0); 2655 } 2656 ahd_outb(ahd, CLRSINT3, CLRNTRAMPERR|CLROSRAMPERR); 2657 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 2658 |CLRBUSFREE|CLRSCSIPERR|CLRREQINIT); 2659 ahd_outb(ahd, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO 2660 |CLRIOERR|CLROVERRUN); 2661 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2662 } 2663 2664 /**************************** Debugging Routines ******************************/ 2665 #ifdef AHD_DEBUG 2666 uint32_t ahd_debug = AHD_DEBUG_OPTS; 2667 #endif 2668 void 2669 ahd_print_scb(struct scb *scb) 2670 { 2671 struct hardware_scb *hscb; 2672 int i; 2673 2674 hscb = scb->hscb; 2675 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 2676 (void *)scb, 2677 hscb->control, 2678 hscb->scsiid, 2679 hscb->lun, 2680 hscb->cdb_len); 2681 printf("Shared Data: "); 2682 for (i = 0; i < sizeof(hscb->shared_data.idata.cdb); i++) 2683 printf("%#02x", hscb->shared_data.idata.cdb[i]); 2684 printf(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n", 2685 (uint32_t)((aic_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF), 2686 (uint32_t)(aic_le64toh(hscb->dataptr) & 0xFFFFFFFF), 2687 aic_le32toh(hscb->datacnt), 2688 aic_le32toh(hscb->sgptr), 2689 SCB_GET_TAG(scb)); 2690 ahd_dump_sglist(scb); 2691 } 2692 2693 void 2694 ahd_dump_sglist(struct scb *scb) 2695 { 2696 int i; 2697 2698 if (scb->sg_count > 0) { 2699 if ((scb->ahd_softc->flags & AHD_64BIT_ADDRESSING) != 0) { 2700 struct ahd_dma64_seg *sg_list; 2701 2702 sg_list = (struct ahd_dma64_seg*)scb->sg_list; 2703 for (i = 0; i < scb->sg_count; i++) { 2704 uint64_t addr; 2705 uint32_t len; 2706 2707 addr = aic_le64toh(sg_list[i].addr); 2708 len = aic_le32toh(sg_list[i].len); 2709 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n", 2710 i, 2711 (uint32_t)((addr >> 32) & 0xFFFFFFFF), 2712 (uint32_t)(addr & 0xFFFFFFFF), 2713 sg_list[i].len & AHD_SG_LEN_MASK, 2714 (sg_list[i].len & AHD_DMA_LAST_SEG) 2715 ? " Last" : ""); 2716 } 2717 } else { 2718 struct ahd_dma_seg *sg_list; 2719 2720 sg_list = (struct ahd_dma_seg*)scb->sg_list; 2721 for (i = 0; i < scb->sg_count; i++) { 2722 uint32_t len; 2723 2724 len = aic_le32toh(sg_list[i].len); 2725 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n", 2726 i, 2727 (len & AHD_SG_HIGH_ADDR_MASK) >> 24, 2728 aic_le32toh(sg_list[i].addr), 2729 len & AHD_SG_LEN_MASK, 2730 len & AHD_DMA_LAST_SEG ? " Last" : ""); 2731 } 2732 } 2733 } 2734 } 2735 2736 /************************* Transfer Negotiation *******************************/ 2737 /* 2738 * Allocate per target mode instance (ID we respond to as a target) 2739 * transfer negotiation data structures. 2740 */ 2741 static struct ahd_tmode_tstate * 2742 ahd_alloc_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel) 2743 { 2744 struct ahd_tmode_tstate *master_tstate; 2745 struct ahd_tmode_tstate *tstate; 2746 int i; 2747 2748 master_tstate = ahd->enabled_targets[ahd->our_id]; 2749 if (ahd->enabled_targets[scsi_id] != NULL 2750 && ahd->enabled_targets[scsi_id] != master_tstate) 2751 panic("%s: ahd_alloc_tstate - Target already allocated", 2752 ahd_name(ahd)); 2753 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); 2754 if (tstate == NULL) 2755 return (NULL); 2756 2757 /* 2758 * If we have allocated a master tstate, copy user settings from 2759 * the master tstate (taken from SRAM or the EEPROM) for this 2760 * channel, but reset our current and goal settings to async/narrow 2761 * until an initiator talks to us. 2762 */ 2763 if (master_tstate != NULL) { 2764 memcpy(tstate, master_tstate, sizeof(*tstate)); 2765 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 2766 for (i = 0; i < 16; i++) { 2767 memset(&tstate->transinfo[i].curr, 0, 2768 sizeof(tstate->transinfo[i].curr)); 2769 memset(&tstate->transinfo[i].goal, 0, 2770 sizeof(tstate->transinfo[i].goal)); 2771 } 2772 } else 2773 memset(tstate, 0, sizeof(*tstate)); 2774 ahd->enabled_targets[scsi_id] = tstate; 2775 return (tstate); 2776 } 2777 2778 #ifdef AHD_TARGET_MODE 2779 /* 2780 * Free per target mode instance (ID we respond to as a target) 2781 * transfer negotiation data structures. 2782 */ 2783 static void 2784 ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force) 2785 { 2786 struct ahd_tmode_tstate *tstate; 2787 2788 /* 2789 * Don't clean up our "master" tstate. 2790 * It has our default user settings. 2791 */ 2792 if (scsi_id == ahd->our_id 2793 && force == FALSE) 2794 return; 2795 2796 tstate = ahd->enabled_targets[scsi_id]; 2797 if (tstate != NULL) 2798 free(tstate, M_DEVBUF); 2799 ahd->enabled_targets[scsi_id] = NULL; 2800 } 2801 #endif 2802 2803 /* 2804 * Called when we have an active connection to a target on the bus, 2805 * this function finds the nearest period to the input period limited 2806 * by the capabilities of the bus connectivity of and sync settings for 2807 * the target. 2808 */ 2809 void 2810 ahd_devlimited_syncrate(struct ahd_softc *ahd, 2811 struct ahd_initiator_tinfo *tinfo, 2812 u_int *period, u_int *ppr_options, role_t role) 2813 { 2814 struct ahd_transinfo *transinfo; 2815 u_int maxsync; 2816 2817 if ((ahd_inb(ahd, SBLKCTL) & ENAB40) != 0 2818 && (ahd_inb(ahd, SSTAT2) & EXP_ACTIVE) == 0) { 2819 maxsync = AHD_SYNCRATE_PACED; 2820 } else { 2821 maxsync = AHD_SYNCRATE_ULTRA; 2822 /* Can't do DT related options on an SE bus */ 2823 *ppr_options &= MSG_EXT_PPR_QAS_REQ; 2824 } 2825 /* 2826 * Never allow a value higher than our current goal 2827 * period otherwise we may allow a target initiated 2828 * negotiation to go above the limit as set by the 2829 * user. In the case of an initiator initiated 2830 * sync negotiation, we limit based on the user 2831 * setting. This allows the system to still accept 2832 * incoming negotiations even if target initiated 2833 * negotiation is not performed. 2834 */ 2835 if (role == ROLE_TARGET) 2836 transinfo = &tinfo->user; 2837 else 2838 transinfo = &tinfo->goal; 2839 *ppr_options &= (transinfo->ppr_options|MSG_EXT_PPR_PCOMP_EN); 2840 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 2841 maxsync = MAX(maxsync, AHD_SYNCRATE_ULTRA2); 2842 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2843 } 2844 if (transinfo->period == 0) { 2845 *period = 0; 2846 *ppr_options = 0; 2847 } else { 2848 *period = MAX(*period, transinfo->period); 2849 ahd_find_syncrate(ahd, period, ppr_options, maxsync); 2850 } 2851 } 2852 2853 /* 2854 * Look up the valid period to SCSIRATE conversion in our table. 2855 * Return the period and offset that should be sent to the target 2856 * if this was the beginning of an SDTR. 2857 */ 2858 void 2859 ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 2860 u_int *ppr_options, u_int maxsync) 2861 { 2862 if (*period < maxsync) 2863 *period = maxsync; 2864 2865 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) != 0 2866 && *period > AHD_SYNCRATE_MIN_DT) 2867 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2868 2869 if (*period > AHD_SYNCRATE_MIN) 2870 *period = 0; 2871 2872 /* Honor PPR option conformance rules. */ 2873 if (*period > AHD_SYNCRATE_PACED) 2874 *ppr_options &= ~MSG_EXT_PPR_RTI; 2875 2876 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0) 2877 *ppr_options &= (MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_QAS_REQ); 2878 2879 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0) 2880 *ppr_options &= MSG_EXT_PPR_QAS_REQ; 2881 2882 /* Skip all PACED only entries if IU is not available */ 2883 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0 2884 && *period < AHD_SYNCRATE_DT) 2885 *period = AHD_SYNCRATE_DT; 2886 2887 /* Skip all DT only entries if DT is not available */ 2888 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 2889 && *period < AHD_SYNCRATE_ULTRA2) 2890 *period = AHD_SYNCRATE_ULTRA2; 2891 } 2892 2893 /* 2894 * Truncate the given synchronous offset to a value the 2895 * current adapter type and syncrate are capable of. 2896 */ 2897 void 2898 ahd_validate_offset(struct ahd_softc *ahd, 2899 struct ahd_initiator_tinfo *tinfo, 2900 u_int period, u_int *offset, int wide, 2901 role_t role) 2902 { 2903 u_int maxoffset; 2904 2905 /* Limit offset to what we can do */ 2906 if (period == 0) 2907 maxoffset = 0; 2908 else if (period <= AHD_SYNCRATE_PACED) { 2909 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) 2910 maxoffset = MAX_OFFSET_PACED_BUG; 2911 else 2912 maxoffset = MAX_OFFSET_PACED; 2913 } else 2914 maxoffset = MAX_OFFSET_NON_PACED; 2915 *offset = MIN(*offset, maxoffset); 2916 if (tinfo != NULL) { 2917 if (role == ROLE_TARGET) 2918 *offset = MIN(*offset, tinfo->user.offset); 2919 else 2920 *offset = MIN(*offset, tinfo->goal.offset); 2921 } 2922 } 2923 2924 /* 2925 * Truncate the given transfer width parameter to a value the 2926 * current adapter type is capable of. 2927 */ 2928 void 2929 ahd_validate_width(struct ahd_softc *ahd, struct ahd_initiator_tinfo *tinfo, 2930 u_int *bus_width, role_t role) 2931 { 2932 switch (*bus_width) { 2933 default: 2934 if (ahd->features & AHD_WIDE) { 2935 /* Respond Wide */ 2936 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 2937 break; 2938 } 2939 /* FALLTHROUGH */ 2940 case MSG_EXT_WDTR_BUS_8_BIT: 2941 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 2942 break; 2943 } 2944 if (tinfo != NULL) { 2945 if (role == ROLE_TARGET) 2946 *bus_width = MIN(tinfo->user.width, *bus_width); 2947 else 2948 *bus_width = MIN(tinfo->goal.width, *bus_width); 2949 } 2950 } 2951 2952 /* 2953 * Update the bitmask of targets for which the controller should 2954 * negotiate with at the next convenient oportunity. This currently 2955 * means the next time we send the initial identify messages for 2956 * a new transaction. 2957 */ 2958 int 2959 ahd_update_neg_request(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 2960 struct ahd_tmode_tstate *tstate, 2961 struct ahd_initiator_tinfo *tinfo, ahd_neg_type neg_type) 2962 { 2963 u_int auto_negotiate_orig; 2964 2965 auto_negotiate_orig = tstate->auto_negotiate; 2966 if (neg_type == AHD_NEG_ALWAYS) { 2967 /* 2968 * Force our "current" settings to be 2969 * unknown so that unless a bus reset 2970 * occurs the need to renegotiate is 2971 * recorded persistently. 2972 */ 2973 if ((ahd->features & AHD_WIDE) != 0) 2974 tinfo->curr.width = AHD_WIDTH_UNKNOWN; 2975 tinfo->curr.period = AHD_PERIOD_UNKNOWN; 2976 tinfo->curr.offset = AHD_OFFSET_UNKNOWN; 2977 } 2978 if (tinfo->curr.period != tinfo->goal.period 2979 || tinfo->curr.width != tinfo->goal.width 2980 || tinfo->curr.offset != tinfo->goal.offset 2981 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 2982 || (neg_type == AHD_NEG_IF_NON_ASYNC 2983 && (tinfo->goal.offset != 0 2984 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 2985 || tinfo->goal.ppr_options != 0))) 2986 tstate->auto_negotiate |= devinfo->target_mask; 2987 else 2988 tstate->auto_negotiate &= ~devinfo->target_mask; 2989 2990 return (auto_negotiate_orig != tstate->auto_negotiate); 2991 } 2992 2993 /* 2994 * Update the user/goal/curr tables of synchronous negotiation 2995 * parameters as well as, in the case of a current or active update, 2996 * any data structures on the host controller. In the case of an 2997 * active update, the specified target is currently talking to us on 2998 * the bus, so the transfer parameter update must take effect 2999 * immediately. 3000 */ 3001 void 3002 ahd_set_syncrate(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3003 u_int period, u_int offset, u_int ppr_options, 3004 u_int type, int paused) 3005 { 3006 struct ahd_initiator_tinfo *tinfo; 3007 struct ahd_tmode_tstate *tstate; 3008 u_int old_period; 3009 u_int old_offset; 3010 u_int old_ppr; 3011 int active; 3012 int update_needed; 3013 3014 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; 3015 update_needed = 0; 3016 3017 if (period == 0 || offset == 0) { 3018 period = 0; 3019 offset = 0; 3020 } 3021 3022 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3023 devinfo->target, &tstate); 3024 3025 if ((type & AHD_TRANS_USER) != 0) { 3026 tinfo->user.period = period; 3027 tinfo->user.offset = offset; 3028 tinfo->user.ppr_options = ppr_options; 3029 } 3030 3031 if ((type & AHD_TRANS_GOAL) != 0) { 3032 tinfo->goal.period = period; 3033 tinfo->goal.offset = offset; 3034 tinfo->goal.ppr_options = ppr_options; 3035 } 3036 3037 old_period = tinfo->curr.period; 3038 old_offset = tinfo->curr.offset; 3039 old_ppr = tinfo->curr.ppr_options; 3040 3041 if ((type & AHD_TRANS_CUR) != 0 3042 && (old_period != period 3043 || old_offset != offset 3044 || old_ppr != ppr_options)) { 3045 3046 update_needed++; 3047 3048 tinfo->curr.period = period; 3049 tinfo->curr.offset = offset; 3050 tinfo->curr.ppr_options = ppr_options; 3051 3052 ahd_send_async(ahd, devinfo->channel, devinfo->target, 3053 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 3054 if (bootverbose) { 3055 if (offset != 0) { 3056 int options; 3057 3058 printf("%s: target %d synchronous with " 3059 "period = 0x%x, offset = 0x%x", 3060 ahd_name(ahd), devinfo->target, 3061 period, offset); 3062 options = 0; 3063 if ((ppr_options & MSG_EXT_PPR_RD_STRM) != 0) { 3064 printf("(RDSTRM"); 3065 options++; 3066 } 3067 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) { 3068 printf("%s", options ? "|DT" : "(DT"); 3069 options++; 3070 } 3071 if ((ppr_options & MSG_EXT_PPR_IU_REQ) != 0) { 3072 printf("%s", options ? "|IU" : "(IU"); 3073 options++; 3074 } 3075 if ((ppr_options & MSG_EXT_PPR_RTI) != 0) { 3076 printf("%s", options ? "|RTI" : "(RTI"); 3077 options++; 3078 } 3079 if ((ppr_options & MSG_EXT_PPR_QAS_REQ) != 0) { 3080 printf("%s", options ? "|QAS" : "(QAS"); 3081 options++; 3082 } 3083 if (options != 0) 3084 printf(")\n"); 3085 else 3086 printf("\n"); 3087 } else { 3088 printf("%s: target %d using " 3089 "asynchronous transfers%s\n", 3090 ahd_name(ahd), devinfo->target, 3091 (ppr_options & MSG_EXT_PPR_QAS_REQ) != 0 3092 ? "(QAS)" : ""); 3093 } 3094 } 3095 } 3096 /* 3097 * Always refresh the neg-table to handle the case of the 3098 * sequencer setting the ENATNO bit for a MK_MESSAGE request. 3099 * We will always renegotiate in that case if this is a 3100 * packetized request. Also manage the busfree expected flag 3101 * from this common routine so that we catch changes due to 3102 * WDTR or SDTR messages. 3103 */ 3104 if ((type & AHD_TRANS_CUR) != 0) { 3105 if (!paused) 3106 ahd_pause(ahd); 3107 ahd_update_neg_table(ahd, devinfo, &tinfo->curr); 3108 if (!paused) 3109 ahd_unpause(ahd); 3110 if (ahd->msg_type != MSG_TYPE_NONE) { 3111 if ((old_ppr & MSG_EXT_PPR_IU_REQ) 3112 != (ppr_options & MSG_EXT_PPR_IU_REQ)) { 3113 #ifdef AHD_DEBUG 3114 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3115 ahd_print_devinfo(ahd, devinfo); 3116 printf("Expecting IU Change busfree\n"); 3117 } 3118 #endif 3119 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE 3120 | MSG_FLAG_IU_REQ_CHANGED; 3121 } 3122 if ((old_ppr & MSG_EXT_PPR_IU_REQ) != 0) { 3123 #ifdef AHD_DEBUG 3124 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3125 printf("PPR with IU_REQ outstanding\n"); 3126 #endif 3127 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE; 3128 } 3129 } 3130 } 3131 3132 update_needed += ahd_update_neg_request(ahd, devinfo, tstate, 3133 tinfo, AHD_NEG_TO_GOAL); 3134 3135 if (update_needed && active) 3136 ahd_update_pending_scbs(ahd); 3137 } 3138 3139 /* 3140 * Update the user/goal/curr tables of wide negotiation 3141 * parameters as well as, in the case of a current or active update, 3142 * any data structures on the host controller. In the case of an 3143 * active update, the specified target is currently talking to us on 3144 * the bus, so the transfer parameter update must take effect 3145 * immediately. 3146 */ 3147 void 3148 ahd_set_width(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3149 u_int width, u_int type, int paused) 3150 { 3151 struct ahd_initiator_tinfo *tinfo; 3152 struct ahd_tmode_tstate *tstate; 3153 u_int oldwidth; 3154 int active; 3155 int update_needed; 3156 3157 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; 3158 update_needed = 0; 3159 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3160 devinfo->target, &tstate); 3161 3162 if ((type & AHD_TRANS_USER) != 0) 3163 tinfo->user.width = width; 3164 3165 if ((type & AHD_TRANS_GOAL) != 0) 3166 tinfo->goal.width = width; 3167 3168 oldwidth = tinfo->curr.width; 3169 if ((type & AHD_TRANS_CUR) != 0 && oldwidth != width) { 3170 3171 update_needed++; 3172 3173 tinfo->curr.width = width; 3174 ahd_send_async(ahd, devinfo->channel, devinfo->target, 3175 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 3176 if (bootverbose) { 3177 printf("%s: target %d using %dbit transfers\n", 3178 ahd_name(ahd), devinfo->target, 3179 8 * (0x01 << width)); 3180 } 3181 } 3182 3183 if ((type & AHD_TRANS_CUR) != 0) { 3184 if (!paused) 3185 ahd_pause(ahd); 3186 ahd_update_neg_table(ahd, devinfo, &tinfo->curr); 3187 if (!paused) 3188 ahd_unpause(ahd); 3189 } 3190 3191 update_needed += ahd_update_neg_request(ahd, devinfo, tstate, 3192 tinfo, AHD_NEG_TO_GOAL); 3193 if (update_needed && active) 3194 ahd_update_pending_scbs(ahd); 3195 3196 } 3197 3198 /* 3199 * Update the current state of tagged queuing for a given target. 3200 */ 3201 void 3202 ahd_set_tags(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3203 ahd_queue_alg alg) 3204 { 3205 ahd_platform_set_tags(ahd, devinfo, alg); 3206 ahd_send_async(ahd, devinfo->channel, devinfo->target, 3207 devinfo->lun, AC_TRANSFER_NEG, &alg); 3208 } 3209 3210 static void 3211 ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3212 struct ahd_transinfo *tinfo) 3213 { 3214 ahd_mode_state saved_modes; 3215 u_int period; 3216 u_int ppr_opts; 3217 u_int con_opts; 3218 u_int offset; 3219 u_int saved_negoaddr; 3220 uint8_t iocell_opts[sizeof(ahd->iocell_opts)]; 3221 3222 saved_modes = ahd_save_modes(ahd); 3223 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3224 3225 saved_negoaddr = ahd_inb(ahd, NEGOADDR); 3226 ahd_outb(ahd, NEGOADDR, devinfo->target); 3227 period = tinfo->period; 3228 offset = tinfo->offset; 3229 memcpy(iocell_opts, ahd->iocell_opts, sizeof(ahd->iocell_opts)); 3230 ppr_opts = tinfo->ppr_options & (MSG_EXT_PPR_QAS_REQ|MSG_EXT_PPR_DT_REQ 3231 |MSG_EXT_PPR_IU_REQ|MSG_EXT_PPR_RTI); 3232 con_opts = 0; 3233 if (period == 0) 3234 period = AHD_SYNCRATE_ASYNC; 3235 if (period == AHD_SYNCRATE_160) { 3236 3237 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) { 3238 /* 3239 * When the SPI4 spec was finalized, PACE transfers 3240 * was not made a configurable option in the PPR 3241 * message. Instead it is assumed to be enabled for 3242 * any syncrate faster than 80MHz. Nevertheless, 3243 * Harpoon2A4 allows this to be configurable. 3244 * 3245 * Harpoon2A4 also assumes at most 2 data bytes per 3246 * negotiated REQ/ACK offset. Paced transfers take 3247 * 4, so we must adjust our offset. 3248 */ 3249 ppr_opts |= PPROPT_PACE; 3250 offset *= 2; 3251 3252 /* 3253 * Harpoon2A assumed that there would be a 3254 * fallback rate between 160MHz and 80Mhz, 3255 * so 7 is used as the period factor rather 3256 * than 8 for 160MHz. 3257 */ 3258 period = AHD_SYNCRATE_REVA_160; 3259 } 3260 if ((tinfo->ppr_options & MSG_EXT_PPR_PCOMP_EN) == 0) 3261 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= 3262 ~AHD_PRECOMP_MASK; 3263 } else { 3264 /* 3265 * Precomp should be disabled for non-paced transfers. 3266 */ 3267 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; 3268 3269 if ((ahd->features & AHD_NEW_IOCELL_OPTS) != 0 3270 && (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0 3271 && (ppr_opts & MSG_EXT_PPR_IU_REQ) == 0) { 3272 /* 3273 * Slow down our CRC interval to be 3274 * compatible with non-packetized 3275 * U160 devices that can't handle a 3276 * CRC at full speed. 3277 */ 3278 con_opts |= ENSLOWCRC; 3279 } 3280 3281 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) { 3282 /* 3283 * On H2A4, revert to a slower slewrate 3284 * on non-paced transfers. 3285 */ 3286 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= 3287 ~AHD_SLEWRATE_MASK; 3288 } 3289 } 3290 3291 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP_SLEW); 3292 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_PRECOMP_SLEW_INDEX]); 3293 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_AMPLITUDE); 3294 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_AMPLITUDE_INDEX]); 3295 3296 ahd_outb(ahd, NEGPERIOD, period); 3297 ahd_outb(ahd, NEGPPROPTS, ppr_opts); 3298 ahd_outb(ahd, NEGOFFSET, offset); 3299 3300 if (tinfo->width == MSG_EXT_WDTR_BUS_16_BIT) 3301 con_opts |= WIDEXFER; 3302 3303 /* 3304 * During packetized transfers, the target will 3305 * give us the oportunity to send command packets 3306 * without us asserting attention. 3307 */ 3308 if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0) 3309 con_opts |= ENAUTOATNO; 3310 ahd_outb(ahd, NEGCONOPTS, con_opts); 3311 ahd_outb(ahd, NEGOADDR, saved_negoaddr); 3312 ahd_restore_modes(ahd, saved_modes); 3313 } 3314 3315 /* 3316 * When the transfer settings for a connection change, setup for 3317 * negotiation in pending SCBs to effect the change as quickly as 3318 * possible. We also cancel any negotiations that are scheduled 3319 * for inflight SCBs that have not been started yet. 3320 */ 3321 static void 3322 ahd_update_pending_scbs(struct ahd_softc *ahd) 3323 { 3324 struct scb *pending_scb; 3325 int pending_scb_count; 3326 u_int scb_tag; 3327 int paused; 3328 u_int saved_scbptr; 3329 ahd_mode_state saved_modes; 3330 3331 /* 3332 * Traverse the pending SCB list and ensure that all of the 3333 * SCBs there have the proper settings. We can only safely 3334 * clear the negotiation required flag (setting requires the 3335 * execution queue to be modified) and this is only possible 3336 * if we are not already attempting to select out for this 3337 * SCB. For this reason, all callers only call this routine 3338 * if we are changing the negotiation settings for the currently 3339 * active transaction on the bus. 3340 */ 3341 pending_scb_count = 0; 3342 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) { 3343 struct ahd_devinfo devinfo; 3344 struct hardware_scb *pending_hscb; 3345 struct ahd_initiator_tinfo *tinfo; 3346 struct ahd_tmode_tstate *tstate; 3347 3348 ahd_scb_devinfo(ahd, &devinfo, pending_scb); 3349 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel, 3350 devinfo.our_scsiid, 3351 devinfo.target, &tstate); 3352 pending_hscb = pending_scb->hscb; 3353 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 3354 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 3355 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 3356 pending_hscb->control &= ~MK_MESSAGE; 3357 } 3358 ahd_sync_scb(ahd, pending_scb, 3359 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3360 pending_scb_count++; 3361 } 3362 3363 if (pending_scb_count == 0) 3364 return; 3365 3366 if (ahd_is_paused(ahd)) { 3367 paused = 1; 3368 } else { 3369 paused = 0; 3370 ahd_pause(ahd); 3371 } 3372 3373 /* 3374 * Force the sequencer to reinitialize the selection for 3375 * the command at the head of the execution queue if it 3376 * has already been setup. The negotiation changes may 3377 * effect whether we select-out with ATN. It is only 3378 * safe to clear ENSELO when the bus is not free and no 3379 * selection is in progres or completed. 3380 */ 3381 saved_modes = ahd_save_modes(ahd); 3382 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3383 if ((ahd_inb(ahd, SCSISIGI) & BSYI) != 0 3384 && (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0) 3385 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 3386 saved_scbptr = ahd_get_scbptr(ahd); 3387 /* Ensure that the hscbs down on the card match the new information */ 3388 for (scb_tag = 0; scb_tag < ahd->scb_data.maxhscbs; scb_tag++) { 3389 struct hardware_scb *pending_hscb; 3390 u_int control; 3391 3392 pending_scb = ahd_lookup_scb(ahd, scb_tag); 3393 if (pending_scb == NULL) 3394 continue; 3395 ahd_set_scbptr(ahd, scb_tag); 3396 pending_hscb = pending_scb->hscb; 3397 control = ahd_inb_scbram(ahd, SCB_CONTROL); 3398 control &= ~MK_MESSAGE; 3399 control |= pending_hscb->control & MK_MESSAGE; 3400 ahd_outb(ahd, SCB_CONTROL, control); 3401 } 3402 ahd_set_scbptr(ahd, saved_scbptr); 3403 ahd_restore_modes(ahd, saved_modes); 3404 3405 if (paused == 0) 3406 ahd_unpause(ahd); 3407 } 3408 3409 /**************************** Pathing Information *****************************/ 3410 static void 3411 ahd_fetch_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3412 { 3413 ahd_mode_state saved_modes; 3414 u_int saved_scsiid; 3415 role_t role; 3416 int our_id; 3417 3418 saved_modes = ahd_save_modes(ahd); 3419 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3420 3421 if (ahd_inb(ahd, SSTAT0) & TARGET) 3422 role = ROLE_TARGET; 3423 else 3424 role = ROLE_INITIATOR; 3425 3426 if (role == ROLE_TARGET 3427 && (ahd_inb(ahd, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 3428 /* We were selected, so pull our id from TARGIDIN */ 3429 our_id = ahd_inb(ahd, TARGIDIN) & OID; 3430 } else if (role == ROLE_TARGET) 3431 our_id = ahd_inb(ahd, TOWNID); 3432 else 3433 our_id = ahd_inb(ahd, IOWNID); 3434 3435 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); 3436 ahd_compile_devinfo(devinfo, 3437 our_id, 3438 SCSIID_TARGET(ahd, saved_scsiid), 3439 ahd_inb(ahd, SAVED_LUN), 3440 SCSIID_CHANNEL(ahd, saved_scsiid), 3441 role); 3442 ahd_restore_modes(ahd, saved_modes); 3443 } 3444 3445 void 3446 ahd_print_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3447 { 3448 printf("%s:%c:%d:%d: ", ahd_name(ahd), 'A', 3449 devinfo->target, devinfo->lun); 3450 } 3451 3452 struct ahd_phase_table_entry* 3453 ahd_lookup_phase_entry(int phase) 3454 { 3455 struct ahd_phase_table_entry *entry; 3456 struct ahd_phase_table_entry *last_entry; 3457 3458 /* 3459 * num_phases doesn't include the default entry which 3460 * will be returned if the phase doesn't match. 3461 */ 3462 last_entry = &ahd_phase_table[num_phases]; 3463 for (entry = ahd_phase_table; entry < last_entry; entry++) { 3464 if (phase == entry->phase) 3465 break; 3466 } 3467 return (entry); 3468 } 3469 3470 void 3471 ahd_compile_devinfo(struct ahd_devinfo *devinfo, u_int our_id, u_int target, 3472 u_int lun, char channel, role_t role) 3473 { 3474 devinfo->our_scsiid = our_id; 3475 devinfo->target = target; 3476 devinfo->lun = lun; 3477 devinfo->target_offset = target; 3478 devinfo->channel = channel; 3479 devinfo->role = role; 3480 if (channel == 'B') 3481 devinfo->target_offset += 8; 3482 devinfo->target_mask = (0x01 << devinfo->target_offset); 3483 } 3484 3485 static void 3486 ahd_scb_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3487 struct scb *scb) 3488 { 3489 role_t role; 3490 int our_id; 3491 3492 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 3493 role = ROLE_INITIATOR; 3494 if ((scb->hscb->control & TARGET_SCB) != 0) 3495 role = ROLE_TARGET; 3496 ahd_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahd, scb), 3497 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahd, scb), role); 3498 } 3499 3500 3501 /************************ Message Phase Processing ****************************/ 3502 /* 3503 * When an initiator transaction with the MK_MESSAGE flag either reconnects 3504 * or enters the initial message out phase, we are interrupted. Fill our 3505 * outgoing message buffer with the appropriate message and beging handing 3506 * the message phase(s) manually. 3507 */ 3508 static void 3509 ahd_setup_initiator_msgout(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3510 struct scb *scb) 3511 { 3512 /* 3513 * To facilitate adding multiple messages together, 3514 * each routine should increment the index and len 3515 * variables instead of setting them explicitly. 3516 */ 3517 ahd->msgout_index = 0; 3518 ahd->msgout_len = 0; 3519 3520 if (ahd_currently_packetized(ahd)) 3521 ahd->msg_flags |= MSG_FLAG_PACKETIZED; 3522 3523 if (ahd->send_msg_perror 3524 && ahd_inb(ahd, MSG_OUT) == HOST_MSG) { 3525 ahd->msgout_buf[ahd->msgout_index++] = ahd->send_msg_perror; 3526 ahd->msgout_len++; 3527 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3528 #ifdef AHD_DEBUG 3529 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3530 printf("Setting up for Parity Error delivery\n"); 3531 #endif 3532 return; 3533 } else if (scb == NULL) { 3534 printf("%s: WARNING. No pending message for " 3535 "I_T msgin. Issuing NO-OP\n", ahd_name(ahd)); 3536 ahd->msgout_buf[ahd->msgout_index++] = MSG_NOOP; 3537 ahd->msgout_len++; 3538 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3539 return; 3540 } 3541 3542 if ((scb->flags & SCB_DEVICE_RESET) == 0 3543 && (scb->flags & SCB_PACKETIZED) == 0 3544 && ahd_inb(ahd, MSG_OUT) == MSG_IDENTIFYFLAG) { 3545 u_int identify_msg; 3546 3547 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 3548 if ((scb->hscb->control & DISCENB) != 0) 3549 identify_msg |= MSG_IDENTIFY_DISCFLAG; 3550 ahd->msgout_buf[ahd->msgout_index++] = identify_msg; 3551 ahd->msgout_len++; 3552 3553 if ((scb->hscb->control & TAG_ENB) != 0) { 3554 ahd->msgout_buf[ahd->msgout_index++] = 3555 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 3556 ahd->msgout_buf[ahd->msgout_index++] = SCB_GET_TAG(scb); 3557 ahd->msgout_len += 2; 3558 } 3559 } 3560 3561 if (scb->flags & SCB_DEVICE_RESET) { 3562 ahd->msgout_buf[ahd->msgout_index++] = MSG_BUS_DEV_RESET; 3563 ahd->msgout_len++; 3564 ahd_print_path(ahd, scb); 3565 printf("Bus Device Reset Message Sent\n"); 3566 /* 3567 * Clear our selection hardware in advance of 3568 * the busfree. We may have an entry in the waiting 3569 * Q for this target, and we don't want to go about 3570 * selecting while we handle the busfree and blow it 3571 * away. 3572 */ 3573 ahd_outb(ahd, SCSISEQ0, 0); 3574 } else if ((scb->flags & SCB_ABORT) != 0) { 3575 3576 if ((scb->hscb->control & TAG_ENB) != 0) { 3577 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT_TAG; 3578 } else { 3579 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT; 3580 } 3581 ahd->msgout_len++; 3582 ahd_print_path(ahd, scb); 3583 printf("Abort%s Message Sent\n", 3584 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 3585 /* 3586 * Clear our selection hardware in advance of 3587 * the busfree. We may have an entry in the waiting 3588 * Q for this target, and we don't want to go about 3589 * selecting while we handle the busfree and blow it 3590 * away. 3591 */ 3592 ahd_outb(ahd, SCSISEQ0, 0); 3593 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 3594 ahd_build_transfer_msg(ahd, devinfo); 3595 /* 3596 * Clear our selection hardware in advance of potential 3597 * PPR IU status change busfree. We may have an entry in 3598 * the waiting Q for this target, and we don't want to go 3599 * about selecting while we handle the busfree and blow 3600 * it away. 3601 */ 3602 ahd_outb(ahd, SCSISEQ0, 0); 3603 } else { 3604 printf("ahd_intr: AWAITING_MSG for an SCB that " 3605 "does not have a waiting message\n"); 3606 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 3607 devinfo->target_mask); 3608 panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x " 3609 "SCB flags = %x", SCB_GET_TAG(scb), scb->hscb->control, 3610 ahd_inb_scbram(ahd, SCB_CONTROL), ahd_inb(ahd, MSG_OUT), 3611 scb->flags); 3612 } 3613 3614 /* 3615 * Clear the MK_MESSAGE flag from the SCB so we aren't 3616 * asked to send this message again. 3617 */ 3618 ahd_outb(ahd, SCB_CONTROL, 3619 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE); 3620 scb->hscb->control &= ~MK_MESSAGE; 3621 ahd->msgout_index = 0; 3622 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3623 } 3624 3625 /* 3626 * Build an appropriate transfer negotiation message for the 3627 * currently active target. 3628 */ 3629 static void 3630 ahd_build_transfer_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3631 { 3632 /* 3633 * We need to initiate transfer negotiations. 3634 * If our current and goal settings are identical, 3635 * we want to renegotiate due to a check condition. 3636 */ 3637 struct ahd_initiator_tinfo *tinfo; 3638 struct ahd_tmode_tstate *tstate; 3639 int dowide; 3640 int dosync; 3641 int doppr; 3642 u_int period; 3643 u_int ppr_options; 3644 u_int offset; 3645 3646 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3647 devinfo->target, &tstate); 3648 /* 3649 * Filter our period based on the current connection. 3650 * If we can't perform DT transfers on this segment (not in LVD 3651 * mode for instance), then our decision to issue a PPR message 3652 * may change. 3653 */ 3654 period = tinfo->goal.period; 3655 offset = tinfo->goal.offset; 3656 ppr_options = tinfo->goal.ppr_options; 3657 /* Target initiated PPR is not allowed in the SCSI spec */ 3658 if (devinfo->role == ROLE_TARGET) 3659 ppr_options = 0; 3660 ahd_devlimited_syncrate(ahd, tinfo, &period, 3661 &ppr_options, devinfo->role); 3662 dowide = tinfo->curr.width != tinfo->goal.width; 3663 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period; 3664 /* 3665 * Only use PPR if we have options that need it, even if the device 3666 * claims to support it. There might be an expander in the way 3667 * that doesn't. 3668 */ 3669 doppr = ppr_options != 0; 3670 3671 if (!dowide && !dosync && !doppr) { 3672 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 3673 dosync = tinfo->goal.offset != 0; 3674 } 3675 3676 if (!dowide && !dosync && !doppr) { 3677 /* 3678 * Force async with a WDTR message if we have a wide bus, 3679 * or just issue an SDTR with a 0 offset. 3680 */ 3681 if ((ahd->features & AHD_WIDE) != 0) 3682 dowide = 1; 3683 else 3684 dosync = 1; 3685 3686 if (bootverbose) { 3687 ahd_print_devinfo(ahd, devinfo); 3688 printf("Ensuring async\n"); 3689 } 3690 } 3691 /* Target initiated PPR is not allowed in the SCSI spec */ 3692 if (devinfo->role == ROLE_TARGET) 3693 doppr = 0; 3694 3695 /* 3696 * Both the PPR message and SDTR message require the 3697 * goal syncrate to be limited to what the target device 3698 * is capable of handling (based on whether an LVD->SE 3699 * expander is on the bus), so combine these two cases. 3700 * Regardless, guarantee that if we are using WDTR and SDTR 3701 * messages that WDTR comes first. 3702 */ 3703 if (doppr || (dosync && !dowide)) { 3704 3705 offset = tinfo->goal.offset; 3706 ahd_validate_offset(ahd, tinfo, period, &offset, 3707 doppr ? tinfo->goal.width 3708 : tinfo->curr.width, 3709 devinfo->role); 3710 if (doppr) { 3711 ahd_construct_ppr(ahd, devinfo, period, offset, 3712 tinfo->goal.width, ppr_options); 3713 } else { 3714 ahd_construct_sdtr(ahd, devinfo, period, offset); 3715 } 3716 } else { 3717 ahd_construct_wdtr(ahd, devinfo, tinfo->goal.width); 3718 } 3719 } 3720 3721 /* 3722 * Build a synchronous negotiation message in our message 3723 * buffer based on the input parameters. 3724 */ 3725 static void 3726 ahd_construct_sdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3727 u_int period, u_int offset) 3728 { 3729 if (offset == 0) 3730 period = AHD_ASYNC_XFER_PERIOD; 3731 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3732 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR_LEN; 3733 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR; 3734 ahd->msgout_buf[ahd->msgout_index++] = period; 3735 ahd->msgout_buf[ahd->msgout_index++] = offset; 3736 ahd->msgout_len += 5; 3737 if (bootverbose) { 3738 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 3739 ahd_name(ahd), devinfo->channel, devinfo->target, 3740 devinfo->lun, period, offset); 3741 } 3742 } 3743 3744 /* 3745 * Build a wide negotiateion message in our message 3746 * buffer based on the input parameters. 3747 */ 3748 static void 3749 ahd_construct_wdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3750 u_int bus_width) 3751 { 3752 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3753 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR_LEN; 3754 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR; 3755 ahd->msgout_buf[ahd->msgout_index++] = bus_width; 3756 ahd->msgout_len += 4; 3757 if (bootverbose) { 3758 printf("(%s:%c:%d:%d): Sending WDTR %x\n", 3759 ahd_name(ahd), devinfo->channel, devinfo->target, 3760 devinfo->lun, bus_width); 3761 } 3762 } 3763 3764 /* 3765 * Build a parallel protocol request message in our message 3766 * buffer based on the input parameters. 3767 */ 3768 static void 3769 ahd_construct_ppr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3770 u_int period, u_int offset, u_int bus_width, 3771 u_int ppr_options) 3772 { 3773 /* 3774 * Always request precompensation from 3775 * the other target if we are running 3776 * at paced syncrates. 3777 */ 3778 if (period <= AHD_SYNCRATE_PACED) 3779 ppr_options |= MSG_EXT_PPR_PCOMP_EN; 3780 if (offset == 0) 3781 period = AHD_ASYNC_XFER_PERIOD; 3782 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3783 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR_LEN; 3784 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR; 3785 ahd->msgout_buf[ahd->msgout_index++] = period; 3786 ahd->msgout_buf[ahd->msgout_index++] = 0; 3787 ahd->msgout_buf[ahd->msgout_index++] = offset; 3788 ahd->msgout_buf[ahd->msgout_index++] = bus_width; 3789 ahd->msgout_buf[ahd->msgout_index++] = ppr_options; 3790 ahd->msgout_len += 8; 3791 if (bootverbose) { 3792 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, " 3793 "offset %x, ppr_options %x\n", ahd_name(ahd), 3794 devinfo->channel, devinfo->target, devinfo->lun, 3795 bus_width, period, offset, ppr_options); 3796 } 3797 } 3798 3799 /* 3800 * Clear any active message state. 3801 */ 3802 static void 3803 ahd_clear_msg_state(struct ahd_softc *ahd) 3804 { 3805 ahd_mode_state saved_modes; 3806 3807 saved_modes = ahd_save_modes(ahd); 3808 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3809 ahd->send_msg_perror = 0; 3810 ahd->msg_flags = MSG_FLAG_NONE; 3811 ahd->msgout_len = 0; 3812 ahd->msgin_index = 0; 3813 ahd->msg_type = MSG_TYPE_NONE; 3814 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { 3815 /* 3816 * The target didn't care to respond to our 3817 * message request, so clear ATN. 3818 */ 3819 ahd_outb(ahd, CLRSINT1, CLRATNO); 3820 } 3821 ahd_outb(ahd, MSG_OUT, MSG_NOOP); 3822 ahd_outb(ahd, SEQ_FLAGS2, 3823 ahd_inb(ahd, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 3824 ahd_restore_modes(ahd, saved_modes); 3825 } 3826 3827 /* 3828 * Manual message loop handler. 3829 */ 3830 static void 3831 ahd_handle_message_phase(struct ahd_softc *ahd) 3832 { 3833 struct ahd_devinfo devinfo; 3834 u_int bus_phase; 3835 int end_session; 3836 3837 ahd_fetch_devinfo(ahd, &devinfo); 3838 end_session = FALSE; 3839 bus_phase = ahd_inb(ahd, LASTPHASE); 3840 3841 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0) { 3842 printf("LQIRETRY for LQIPHASE_OUTPKT\n"); 3843 ahd_outb(ahd, LQCTL2, LQIRETRY); 3844 } 3845 reswitch: 3846 switch (ahd->msg_type) { 3847 case MSG_TYPE_INITIATOR_MSGOUT: 3848 { 3849 int lastbyte; 3850 int phasemis; 3851 int msgdone; 3852 3853 if (ahd->msgout_len == 0 && ahd->send_msg_perror == 0) 3854 panic("HOST_MSG_LOOP interrupt with no active message"); 3855 3856 #ifdef AHD_DEBUG 3857 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3858 ahd_print_devinfo(ahd, &devinfo); 3859 printf("INITIATOR_MSG_OUT"); 3860 } 3861 #endif 3862 phasemis = bus_phase != P_MESGOUT; 3863 if (phasemis) { 3864 #ifdef AHD_DEBUG 3865 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3866 printf(" PHASEMIS %s\n", 3867 ahd_lookup_phase_entry(bus_phase) 3868 ->phasemsg); 3869 } 3870 #endif 3871 if (bus_phase == P_MESGIN) { 3872 /* 3873 * Change gears and see if 3874 * this messages is of interest to 3875 * us or should be passed back to 3876 * the sequencer. 3877 */ 3878 ahd_outb(ahd, CLRSINT1, CLRATNO); 3879 ahd->send_msg_perror = 0; 3880 ahd->msg_type = MSG_TYPE_INITIATOR_MSGIN; 3881 ahd->msgin_index = 0; 3882 goto reswitch; 3883 } 3884 end_session = TRUE; 3885 break; 3886 } 3887 3888 if (ahd->send_msg_perror) { 3889 ahd_outb(ahd, CLRSINT1, CLRATNO); 3890 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3891 #ifdef AHD_DEBUG 3892 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3893 printf(" byte 0x%x\n", ahd->send_msg_perror); 3894 #endif 3895 /* 3896 * If we are notifying the target of a CRC error 3897 * during packetized operations, the target is 3898 * within its rights to acknowledge our message 3899 * with a busfree. 3900 */ 3901 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0 3902 && ahd->send_msg_perror == MSG_INITIATOR_DET_ERR) 3903 ahd->msg_flags |= MSG_FLAG_EXPECT_IDE_BUSFREE; 3904 3905 ahd_outb(ahd, RETURN_2, ahd->send_msg_perror); 3906 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); 3907 break; 3908 } 3909 3910 msgdone = ahd->msgout_index == ahd->msgout_len; 3911 if (msgdone) { 3912 /* 3913 * The target has requested a retry. 3914 * Re-assert ATN, reset our message index to 3915 * 0, and try again. 3916 */ 3917 ahd->msgout_index = 0; 3918 ahd_assert_atn(ahd); 3919 } 3920 3921 lastbyte = ahd->msgout_index == (ahd->msgout_len - 1); 3922 if (lastbyte) { 3923 /* Last byte is signified by dropping ATN */ 3924 ahd_outb(ahd, CLRSINT1, CLRATNO); 3925 } 3926 3927 /* 3928 * Clear our interrupt status and present 3929 * the next byte on the bus. 3930 */ 3931 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3932 #ifdef AHD_DEBUG 3933 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3934 printf(" byte 0x%x\n", 3935 ahd->msgout_buf[ahd->msgout_index]); 3936 #endif 3937 ahd_outb(ahd, RETURN_2, ahd->msgout_buf[ahd->msgout_index++]); 3938 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); 3939 break; 3940 } 3941 case MSG_TYPE_INITIATOR_MSGIN: 3942 { 3943 int phasemis; 3944 int message_done; 3945 3946 #ifdef AHD_DEBUG 3947 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3948 ahd_print_devinfo(ahd, &devinfo); 3949 printf("INITIATOR_MSG_IN"); 3950 } 3951 #endif 3952 phasemis = bus_phase != P_MESGIN; 3953 if (phasemis) { 3954 #ifdef AHD_DEBUG 3955 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3956 printf(" PHASEMIS %s\n", 3957 ahd_lookup_phase_entry(bus_phase) 3958 ->phasemsg); 3959 } 3960 #endif 3961 ahd->msgin_index = 0; 3962 if (bus_phase == P_MESGOUT 3963 && (ahd->send_msg_perror != 0 3964 || (ahd->msgout_len != 0 3965 && ahd->msgout_index == 0))) { 3966 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3967 goto reswitch; 3968 } 3969 end_session = TRUE; 3970 break; 3971 } 3972 3973 /* Pull the byte in without acking it */ 3974 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIBUS); 3975 #ifdef AHD_DEBUG 3976 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3977 printf(" byte 0x%x\n", 3978 ahd->msgin_buf[ahd->msgin_index]); 3979 #endif 3980 3981 message_done = ahd_parse_msg(ahd, &devinfo); 3982 3983 if (message_done) { 3984 /* 3985 * Clear our incoming message buffer in case there 3986 * is another message following this one. 3987 */ 3988 ahd->msgin_index = 0; 3989 3990 /* 3991 * If this message illicited a response, 3992 * assert ATN so the target takes us to the 3993 * message out phase. 3994 */ 3995 if (ahd->msgout_len != 0) { 3996 #ifdef AHD_DEBUG 3997 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3998 ahd_print_devinfo(ahd, &devinfo); 3999 printf("Asserting ATN for response\n"); 4000 } 4001 #endif 4002 ahd_assert_atn(ahd); 4003 } 4004 } else 4005 ahd->msgin_index++; 4006 4007 if (message_done == MSGLOOP_TERMINATED) { 4008 end_session = TRUE; 4009 } else { 4010 /* Ack the byte */ 4011 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 4012 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_READ); 4013 } 4014 break; 4015 } 4016 case MSG_TYPE_TARGET_MSGIN: 4017 { 4018 int msgdone; 4019 int msgout_request; 4020 4021 /* 4022 * By default, the message loop will continue. 4023 */ 4024 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); 4025 4026 if (ahd->msgout_len == 0) 4027 panic("Target MSGIN with no active message"); 4028 4029 /* 4030 * If we interrupted a mesgout session, the initiator 4031 * will not know this until our first REQ. So, we 4032 * only honor mesgout requests after we've sent our 4033 * first byte. 4034 */ 4035 if ((ahd_inb(ahd, SCSISIGI) & ATNI) != 0 4036 && ahd->msgout_index > 0) 4037 msgout_request = TRUE; 4038 else 4039 msgout_request = FALSE; 4040 4041 if (msgout_request) { 4042 4043 /* 4044 * Change gears and see if 4045 * this messages is of interest to 4046 * us or should be passed back to 4047 * the sequencer. 4048 */ 4049 ahd->msg_type = MSG_TYPE_TARGET_MSGOUT; 4050 ahd_outb(ahd, SCSISIGO, P_MESGOUT | BSYO); 4051 ahd->msgin_index = 0; 4052 /* Dummy read to REQ for first byte */ 4053 ahd_inb(ahd, SCSIDAT); 4054 ahd_outb(ahd, SXFRCTL0, 4055 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 4056 break; 4057 } 4058 4059 msgdone = ahd->msgout_index == ahd->msgout_len; 4060 if (msgdone) { 4061 ahd_outb(ahd, SXFRCTL0, 4062 ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); 4063 end_session = TRUE; 4064 break; 4065 } 4066 4067 /* 4068 * Present the next byte on the bus. 4069 */ 4070 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) | SPIOEN); 4071 ahd_outb(ahd, SCSIDAT, ahd->msgout_buf[ahd->msgout_index++]); 4072 break; 4073 } 4074 case MSG_TYPE_TARGET_MSGOUT: 4075 { 4076 int lastbyte; 4077 int msgdone; 4078 4079 /* 4080 * By default, the message loop will continue. 4081 */ 4082 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); 4083 4084 /* 4085 * The initiator signals that this is 4086 * the last byte by dropping ATN. 4087 */ 4088 lastbyte = (ahd_inb(ahd, SCSISIGI) & ATNI) == 0; 4089 4090 /* 4091 * Read the latched byte, but turn off SPIOEN first 4092 * so that we don't inadvertently cause a REQ for the 4093 * next byte. 4094 */ 4095 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); 4096 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIDAT); 4097 msgdone = ahd_parse_msg(ahd, &devinfo); 4098 if (msgdone == MSGLOOP_TERMINATED) { 4099 /* 4100 * The message is *really* done in that it caused 4101 * us to go to bus free. The sequencer has already 4102 * been reset at this point, so pull the ejection 4103 * handle. 4104 */ 4105 return; 4106 } 4107 4108 ahd->msgin_index++; 4109 4110 /* 4111 * XXX Read spec about initiator dropping ATN too soon 4112 * and use msgdone to detect it. 4113 */ 4114 if (msgdone == MSGLOOP_MSGCOMPLETE) { 4115 ahd->msgin_index = 0; 4116 4117 /* 4118 * If this message illicited a response, transition 4119 * to the Message in phase and send it. 4120 */ 4121 if (ahd->msgout_len != 0) { 4122 ahd_outb(ahd, SCSISIGO, P_MESGIN | BSYO); 4123 ahd_outb(ahd, SXFRCTL0, 4124 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 4125 ahd->msg_type = MSG_TYPE_TARGET_MSGIN; 4126 ahd->msgin_index = 0; 4127 break; 4128 } 4129 } 4130 4131 if (lastbyte) 4132 end_session = TRUE; 4133 else { 4134 /* Ask for the next byte. */ 4135 ahd_outb(ahd, SXFRCTL0, 4136 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 4137 } 4138 4139 break; 4140 } 4141 default: 4142 panic("Unknown REQINIT message type"); 4143 } 4144 4145 if (end_session) { 4146 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0) { 4147 printf("%s: Returning to Idle Loop\n", 4148 ahd_name(ahd)); 4149 ahd_clear_msg_state(ahd); 4150 4151 /* 4152 * Perform the equivalent of a clear_target_state. 4153 */ 4154 ahd_outb(ahd, LASTPHASE, P_BUSFREE); 4155 ahd_outb(ahd, SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT); 4156 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); 4157 } else { 4158 ahd_clear_msg_state(ahd); 4159 ahd_outb(ahd, RETURN_1, EXIT_MSG_LOOP); 4160 } 4161 } 4162 } 4163 4164 /* 4165 * See if we sent a particular extended message to the target. 4166 * If "full" is true, return true only if the target saw the full 4167 * message. If "full" is false, return true if the target saw at 4168 * least the first byte of the message. 4169 */ 4170 static int 4171 ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, u_int msgval, int full) 4172 { 4173 int found; 4174 u_int index; 4175 4176 found = FALSE; 4177 index = 0; 4178 4179 while (index < ahd->msgout_len) { 4180 if (ahd->msgout_buf[index] == MSG_EXTENDED) { 4181 u_int end_index; 4182 4183 end_index = index + 1 + ahd->msgout_buf[index + 1]; 4184 if (ahd->msgout_buf[index+2] == msgval 4185 && type == AHDMSG_EXT) { 4186 4187 if (full) { 4188 if (ahd->msgout_index > end_index) 4189 found = TRUE; 4190 } else if (ahd->msgout_index > index) 4191 found = TRUE; 4192 } 4193 index = end_index; 4194 } else if (ahd->msgout_buf[index] >= MSG_SIMPLE_TASK 4195 && ahd->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 4196 4197 /* Skip tag type and tag id or residue param*/ 4198 index += 2; 4199 } else { 4200 /* Single byte message */ 4201 if (type == AHDMSG_1B 4202 && ahd->msgout_index > index 4203 && (ahd->msgout_buf[index] == msgval 4204 || ((ahd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0 4205 && msgval == MSG_IDENTIFYFLAG))) 4206 found = TRUE; 4207 index++; 4208 } 4209 4210 if (found) 4211 break; 4212 } 4213 return (found); 4214 } 4215 4216 /* 4217 * Wait for a complete incoming message, parse it, and respond accordingly. 4218 */ 4219 static int 4220 ahd_parse_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4221 { 4222 struct ahd_initiator_tinfo *tinfo; 4223 struct ahd_tmode_tstate *tstate; 4224 int reject; 4225 int done; 4226 int response; 4227 4228 done = MSGLOOP_IN_PROG; 4229 response = FALSE; 4230 reject = FALSE; 4231 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 4232 devinfo->target, &tstate); 4233 4234 /* 4235 * Parse as much of the message as is available, 4236 * rejecting it if we don't support it. When 4237 * the entire message is available and has been 4238 * handled, return MSGLOOP_MSGCOMPLETE, indicating 4239 * that we have parsed an entire message. 4240 * 4241 * In the case of extended messages, we accept the length 4242 * byte outright and perform more checking once we know the 4243 * extended message type. 4244 */ 4245 switch (ahd->msgin_buf[0]) { 4246 case MSG_DISCONNECT: 4247 case MSG_SAVEDATAPOINTER: 4248 case MSG_CMDCOMPLETE: 4249 case MSG_RESTOREPOINTERS: 4250 case MSG_IGN_WIDE_RESIDUE: 4251 /* 4252 * End our message loop as these are messages 4253 * the sequencer handles on its own. 4254 */ 4255 done = MSGLOOP_TERMINATED; 4256 break; 4257 case MSG_MESSAGE_REJECT: 4258 response = ahd_handle_msg_reject(ahd, devinfo); 4259 /* FALLTHROUGH */ 4260 case MSG_NOOP: 4261 done = MSGLOOP_MSGCOMPLETE; 4262 break; 4263 case MSG_EXTENDED: 4264 { 4265 /* Wait for enough of the message to begin validation */ 4266 if (ahd->msgin_index < 2) 4267 break; 4268 switch (ahd->msgin_buf[2]) { 4269 case MSG_EXT_SDTR: 4270 { 4271 u_int period; 4272 u_int ppr_options; 4273 u_int offset; 4274 u_int saved_offset; 4275 4276 if (ahd->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 4277 reject = TRUE; 4278 break; 4279 } 4280 4281 /* 4282 * Wait until we have both args before validating 4283 * and acting on this message. 4284 * 4285 * Add one to MSG_EXT_SDTR_LEN to account for 4286 * the extended message preamble. 4287 */ 4288 if (ahd->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 4289 break; 4290 4291 period = ahd->msgin_buf[3]; 4292 ppr_options = 0; 4293 saved_offset = offset = ahd->msgin_buf[4]; 4294 ahd_devlimited_syncrate(ahd, tinfo, &period, 4295 &ppr_options, devinfo->role); 4296 ahd_validate_offset(ahd, tinfo, period, &offset, 4297 tinfo->curr.width, devinfo->role); 4298 if (bootverbose) { 4299 printf("(%s:%c:%d:%d): Received " 4300 "SDTR period %x, offset %x\n\t" 4301 "Filtered to period %x, offset %x\n", 4302 ahd_name(ahd), devinfo->channel, 4303 devinfo->target, devinfo->lun, 4304 ahd->msgin_buf[3], saved_offset, 4305 period, offset); 4306 } 4307 ahd_set_syncrate(ahd, devinfo, period, 4308 offset, ppr_options, 4309 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4310 /*paused*/TRUE); 4311 4312 /* 4313 * See if we initiated Sync Negotiation 4314 * and didn't have to fall down to async 4315 * transfers. 4316 */ 4317 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, TRUE)) { 4318 /* We started it */ 4319 if (saved_offset != offset) { 4320 /* Went too low - force async */ 4321 reject = TRUE; 4322 } 4323 } else { 4324 /* 4325 * Send our own SDTR in reply 4326 */ 4327 if (bootverbose 4328 && devinfo->role == ROLE_INITIATOR) { 4329 printf("(%s:%c:%d:%d): Target " 4330 "Initiated SDTR\n", 4331 ahd_name(ahd), devinfo->channel, 4332 devinfo->target, devinfo->lun); 4333 } 4334 ahd->msgout_index = 0; 4335 ahd->msgout_len = 0; 4336 ahd_construct_sdtr(ahd, devinfo, 4337 period, offset); 4338 ahd->msgout_index = 0; 4339 response = TRUE; 4340 } 4341 done = MSGLOOP_MSGCOMPLETE; 4342 break; 4343 } 4344 case MSG_EXT_WDTR: 4345 { 4346 u_int bus_width; 4347 u_int saved_width; 4348 u_int sending_reply; 4349 4350 sending_reply = FALSE; 4351 if (ahd->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 4352 reject = TRUE; 4353 break; 4354 } 4355 4356 /* 4357 * Wait until we have our arg before validating 4358 * and acting on this message. 4359 * 4360 * Add one to MSG_EXT_WDTR_LEN to account for 4361 * the extended message preamble. 4362 */ 4363 if (ahd->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 4364 break; 4365 4366 bus_width = ahd->msgin_buf[3]; 4367 saved_width = bus_width; 4368 ahd_validate_width(ahd, tinfo, &bus_width, 4369 devinfo->role); 4370 if (bootverbose) { 4371 printf("(%s:%c:%d:%d): Received WDTR " 4372 "%x filtered to %x\n", 4373 ahd_name(ahd), devinfo->channel, 4374 devinfo->target, devinfo->lun, 4375 saved_width, bus_width); 4376 } 4377 4378 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, TRUE)) { 4379 /* 4380 * Don't send a WDTR back to the 4381 * target, since we asked first. 4382 * If the width went higher than our 4383 * request, reject it. 4384 */ 4385 if (saved_width > bus_width) { 4386 reject = TRUE; 4387 printf("(%s:%c:%d:%d): requested %dBit " 4388 "transfers. Rejecting...\n", 4389 ahd_name(ahd), devinfo->channel, 4390 devinfo->target, devinfo->lun, 4391 8 * (0x01 << bus_width)); 4392 bus_width = 0; 4393 } 4394 } else { 4395 /* 4396 * Send our own WDTR in reply 4397 */ 4398 if (bootverbose 4399 && devinfo->role == ROLE_INITIATOR) { 4400 printf("(%s:%c:%d:%d): Target " 4401 "Initiated WDTR\n", 4402 ahd_name(ahd), devinfo->channel, 4403 devinfo->target, devinfo->lun); 4404 } 4405 ahd->msgout_index = 0; 4406 ahd->msgout_len = 0; 4407 ahd_construct_wdtr(ahd, devinfo, bus_width); 4408 ahd->msgout_index = 0; 4409 response = TRUE; 4410 sending_reply = TRUE; 4411 } 4412 /* 4413 * After a wide message, we are async, but 4414 * some devices don't seem to honor this portion 4415 * of the spec. Force a renegotiation of the 4416 * sync component of our transfer agreement even 4417 * if our goal is async. By updating our width 4418 * after forcing the negotiation, we avoid 4419 * renegotiating for width. 4420 */ 4421 ahd_update_neg_request(ahd, devinfo, tstate, 4422 tinfo, AHD_NEG_ALWAYS); 4423 ahd_set_width(ahd, devinfo, bus_width, 4424 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4425 /*paused*/TRUE); 4426 if (sending_reply == FALSE && reject == FALSE) { 4427 4428 /* 4429 * We will always have an SDTR to send. 4430 */ 4431 ahd->msgout_index = 0; 4432 ahd->msgout_len = 0; 4433 ahd_build_transfer_msg(ahd, devinfo); 4434 ahd->msgout_index = 0; 4435 response = TRUE; 4436 } 4437 done = MSGLOOP_MSGCOMPLETE; 4438 break; 4439 } 4440 case MSG_EXT_PPR: 4441 { 4442 u_int period; 4443 u_int offset; 4444 u_int bus_width; 4445 u_int ppr_options; 4446 u_int saved_width; 4447 u_int saved_offset; 4448 u_int saved_ppr_options; 4449 4450 if (ahd->msgin_buf[1] != MSG_EXT_PPR_LEN) { 4451 reject = TRUE; 4452 break; 4453 } 4454 4455 /* 4456 * Wait until we have all args before validating 4457 * and acting on this message. 4458 * 4459 * Add one to MSG_EXT_PPR_LEN to account for 4460 * the extended message preamble. 4461 */ 4462 if (ahd->msgin_index < (MSG_EXT_PPR_LEN + 1)) 4463 break; 4464 4465 period = ahd->msgin_buf[3]; 4466 offset = ahd->msgin_buf[5]; 4467 bus_width = ahd->msgin_buf[6]; 4468 saved_width = bus_width; 4469 ppr_options = ahd->msgin_buf[7]; 4470 /* 4471 * According to the spec, a DT only 4472 * period factor with no DT option 4473 * set implies async. 4474 */ 4475 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 4476 && period <= 9) 4477 offset = 0; 4478 saved_ppr_options = ppr_options; 4479 saved_offset = offset; 4480 4481 /* 4482 * Transfer options are only available if we 4483 * are negotiating wide. 4484 */ 4485 if (bus_width == 0) 4486 ppr_options &= MSG_EXT_PPR_QAS_REQ; 4487 4488 ahd_validate_width(ahd, tinfo, &bus_width, 4489 devinfo->role); 4490 ahd_devlimited_syncrate(ahd, tinfo, &period, 4491 &ppr_options, devinfo->role); 4492 ahd_validate_offset(ahd, tinfo, period, &offset, 4493 bus_width, devinfo->role); 4494 4495 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, TRUE)) { 4496 /* 4497 * If we are unable to do any of the 4498 * requested options (we went too low), 4499 * then we'll have to reject the message. 4500 */ 4501 if (saved_width > bus_width 4502 || saved_offset != offset 4503 || saved_ppr_options != ppr_options) { 4504 reject = TRUE; 4505 period = 0; 4506 offset = 0; 4507 bus_width = 0; 4508 ppr_options = 0; 4509 } 4510 } else { 4511 if (devinfo->role != ROLE_TARGET) 4512 printf("(%s:%c:%d:%d): Target " 4513 "Initiated PPR\n", 4514 ahd_name(ahd), devinfo->channel, 4515 devinfo->target, devinfo->lun); 4516 else 4517 printf("(%s:%c:%d:%d): Initiator " 4518 "Initiated PPR\n", 4519 ahd_name(ahd), devinfo->channel, 4520 devinfo->target, devinfo->lun); 4521 ahd->msgout_index = 0; 4522 ahd->msgout_len = 0; 4523 ahd_construct_ppr(ahd, devinfo, period, offset, 4524 bus_width, ppr_options); 4525 ahd->msgout_index = 0; 4526 response = TRUE; 4527 } 4528 if (bootverbose) { 4529 printf("(%s:%c:%d:%d): Received PPR width %x, " 4530 "period %x, offset %x,options %x\n" 4531 "\tFiltered to width %x, period %x, " 4532 "offset %x, options %x\n", 4533 ahd_name(ahd), devinfo->channel, 4534 devinfo->target, devinfo->lun, 4535 saved_width, ahd->msgin_buf[3], 4536 saved_offset, saved_ppr_options, 4537 bus_width, period, offset, ppr_options); 4538 } 4539 ahd_set_width(ahd, devinfo, bus_width, 4540 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4541 /*paused*/TRUE); 4542 ahd_set_syncrate(ahd, devinfo, period, 4543 offset, ppr_options, 4544 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4545 /*paused*/TRUE); 4546 4547 done = MSGLOOP_MSGCOMPLETE; 4548 break; 4549 } 4550 default: 4551 /* Unknown extended message. Reject it. */ 4552 reject = TRUE; 4553 break; 4554 } 4555 break; 4556 } 4557 #ifdef AHD_TARGET_MODE 4558 case MSG_BUS_DEV_RESET: 4559 ahd_handle_devreset(ahd, devinfo, CAM_LUN_WILDCARD, 4560 CAM_BDR_SENT, 4561 "Bus Device Reset Received", 4562 /*verbose_level*/0); 4563 ahd_restart(ahd); 4564 done = MSGLOOP_TERMINATED; 4565 break; 4566 case MSG_ABORT_TAG: 4567 case MSG_ABORT: 4568 case MSG_CLEAR_QUEUE: 4569 { 4570 int tag; 4571 4572 /* Target mode messages */ 4573 if (devinfo->role != ROLE_TARGET) { 4574 reject = TRUE; 4575 break; 4576 } 4577 tag = SCB_LIST_NULL; 4578 if (ahd->msgin_buf[0] == MSG_ABORT_TAG) 4579 tag = ahd_inb(ahd, INITIATOR_TAG); 4580 ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, 4581 devinfo->lun, tag, ROLE_TARGET, 4582 CAM_REQ_ABORTED); 4583 4584 tstate = ahd->enabled_targets[devinfo->our_scsiid]; 4585 if (tstate != NULL) { 4586 struct ahd_tmode_lstate* lstate; 4587 4588 lstate = tstate->enabled_luns[devinfo->lun]; 4589 if (lstate != NULL) { 4590 ahd_queue_lstate_event(ahd, lstate, 4591 devinfo->our_scsiid, 4592 ahd->msgin_buf[0], 4593 /*arg*/tag); 4594 ahd_send_lstate_events(ahd, lstate); 4595 } 4596 } 4597 ahd_restart(ahd); 4598 done = MSGLOOP_TERMINATED; 4599 break; 4600 } 4601 #endif 4602 case MSG_QAS_REQUEST: 4603 #ifdef AHD_DEBUG 4604 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 4605 printf("%s: QAS request. SCSISIGI == 0x%x\n", 4606 ahd_name(ahd), ahd_inb(ahd, SCSISIGI)); 4607 #endif 4608 ahd->msg_flags |= MSG_FLAG_EXPECT_QASREJ_BUSFREE; 4609 /* FALLTHROUGH */ 4610 case MSG_TERM_IO_PROC: 4611 default: 4612 reject = TRUE; 4613 break; 4614 } 4615 4616 if (reject) { 4617 /* 4618 * Setup to reject the message. 4619 */ 4620 ahd->msgout_index = 0; 4621 ahd->msgout_len = 1; 4622 ahd->msgout_buf[0] = MSG_MESSAGE_REJECT; 4623 done = MSGLOOP_MSGCOMPLETE; 4624 response = TRUE; 4625 } 4626 4627 if (done != MSGLOOP_IN_PROG && !response) 4628 /* Clear the outgoing message buffer */ 4629 ahd->msgout_len = 0; 4630 4631 return (done); 4632 } 4633 4634 /* 4635 * Process a message reject message. 4636 */ 4637 static int 4638 ahd_handle_msg_reject(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4639 { 4640 /* 4641 * What we care about here is if we had an 4642 * outstanding SDTR or WDTR message for this 4643 * target. If we did, this is a signal that 4644 * the target is refusing negotiation. 4645 */ 4646 struct scb *scb; 4647 struct ahd_initiator_tinfo *tinfo; 4648 struct ahd_tmode_tstate *tstate; 4649 u_int scb_index; 4650 u_int last_msg; 4651 int response = 0; 4652 4653 scb_index = ahd_get_scbptr(ahd); 4654 scb = ahd_lookup_scb(ahd, scb_index); 4655 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, 4656 devinfo->our_scsiid, 4657 devinfo->target, &tstate); 4658 /* Might be necessary */ 4659 last_msg = ahd_inb(ahd, LAST_MSG); 4660 4661 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 4662 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/TRUE) 4663 && tinfo->goal.period <= AHD_SYNCRATE_PACED) { 4664 /* 4665 * Target may not like our SPI-4 PPR Options. 4666 * Attempt to negotiate 80MHz which will turn 4667 * off these options. 4668 */ 4669 if (bootverbose) { 4670 printf("(%s:%c:%d:%d): PPR Rejected. " 4671 "Trying simple U160 PPR\n", 4672 ahd_name(ahd), devinfo->channel, 4673 devinfo->target, devinfo->lun); 4674 } 4675 tinfo->goal.period = AHD_SYNCRATE_DT; 4676 tinfo->goal.ppr_options &= MSG_EXT_PPR_IU_REQ 4677 | MSG_EXT_PPR_QAS_REQ 4678 | MSG_EXT_PPR_DT_REQ; 4679 } else { 4680 /* 4681 * Target does not support the PPR message. 4682 * Attempt to negotiate SPI-2 style. 4683 */ 4684 if (bootverbose) { 4685 printf("(%s:%c:%d:%d): PPR Rejected. " 4686 "Trying WDTR/SDTR\n", 4687 ahd_name(ahd), devinfo->channel, 4688 devinfo->target, devinfo->lun); 4689 } 4690 tinfo->goal.ppr_options = 0; 4691 tinfo->curr.transport_version = 2; 4692 tinfo->goal.transport_version = 2; 4693 } 4694 ahd->msgout_index = 0; 4695 ahd->msgout_len = 0; 4696 ahd_build_transfer_msg(ahd, devinfo); 4697 ahd->msgout_index = 0; 4698 response = 1; 4699 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 4700 4701 /* note 8bit xfers */ 4702 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 4703 "8bit transfers\n", ahd_name(ahd), 4704 devinfo->channel, devinfo->target, devinfo->lun); 4705 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 4706 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4707 /*paused*/TRUE); 4708 /* 4709 * No need to clear the sync rate. If the target 4710 * did not accept the command, our syncrate is 4711 * unaffected. If the target started the negotiation, 4712 * but rejected our response, we already cleared the 4713 * sync rate before sending our WDTR. 4714 */ 4715 if (tinfo->goal.offset != tinfo->curr.offset) { 4716 4717 /* Start the sync negotiation */ 4718 ahd->msgout_index = 0; 4719 ahd->msgout_len = 0; 4720 ahd_build_transfer_msg(ahd, devinfo); 4721 ahd->msgout_index = 0; 4722 response = 1; 4723 } 4724 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 4725 /* note asynch xfers and clear flag */ 4726 ahd_set_syncrate(ahd, devinfo, /*period*/0, 4727 /*offset*/0, /*ppr_options*/0, 4728 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4729 /*paused*/TRUE); 4730 printf("(%s:%c:%d:%d): refuses synchronous negotiation. " 4731 "Using asynchronous transfers\n", 4732 ahd_name(ahd), devinfo->channel, 4733 devinfo->target, devinfo->lun); 4734 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 4735 int tag_type; 4736 int mask; 4737 4738 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 4739 4740 if (tag_type == MSG_SIMPLE_TASK) { 4741 printf("(%s:%c:%d:%d): refuses tagged commands. " 4742 "Performing non-tagged I/O\n", ahd_name(ahd), 4743 devinfo->channel, devinfo->target, devinfo->lun); 4744 ahd_set_tags(ahd, devinfo, AHD_QUEUE_NONE); 4745 mask = ~0x23; 4746 } else { 4747 printf("(%s:%c:%d:%d): refuses %s tagged commands. " 4748 "Performing simple queue tagged I/O only\n", 4749 ahd_name(ahd), devinfo->channel, devinfo->target, 4750 devinfo->lun, tag_type == MSG_ORDERED_TASK 4751 ? "ordered" : "head of queue"); 4752 ahd_set_tags(ahd, devinfo, AHD_QUEUE_BASIC); 4753 mask = ~0x03; 4754 } 4755 4756 /* 4757 * Resend the identify for this CCB as the target 4758 * may believe that the selection is invalid otherwise. 4759 */ 4760 ahd_outb(ahd, SCB_CONTROL, 4761 ahd_inb_scbram(ahd, SCB_CONTROL) & mask); 4762 scb->hscb->control &= mask; 4763 aic_set_transaction_tag(scb, /*enabled*/FALSE, 4764 /*type*/MSG_SIMPLE_TASK); 4765 ahd_outb(ahd, MSG_OUT, MSG_IDENTIFYFLAG); 4766 ahd_assert_atn(ahd); 4767 ahd_busy_tcl(ahd, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 4768 SCB_GET_TAG(scb)); 4769 4770 /* 4771 * Requeue all tagged commands for this target 4772 * currently in our posession so they can be 4773 * converted to untagged commands. 4774 */ 4775 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 4776 SCB_GET_CHANNEL(ahd, scb), 4777 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 4778 ROLE_INITIATOR, CAM_REQUEUE_REQ, 4779 SEARCH_COMPLETE); 4780 } else if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_IDENTIFYFLAG, TRUE)) { 4781 /* 4782 * Most likely the device believes that we had 4783 * previously negotiated packetized. 4784 */ 4785 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE 4786 | MSG_FLAG_IU_REQ_CHANGED; 4787 4788 ahd_force_renegotiation(ahd, devinfo); 4789 ahd->msgout_index = 0; 4790 ahd->msgout_len = 0; 4791 ahd_build_transfer_msg(ahd, devinfo); 4792 ahd->msgout_index = 0; 4793 response = 1; 4794 } else { 4795 /* 4796 * Otherwise, we ignore it. 4797 */ 4798 printf("%s:%c:%d: Message reject for %x -- ignored\n", 4799 ahd_name(ahd), devinfo->channel, devinfo->target, 4800 last_msg); 4801 } 4802 return (response); 4803 } 4804 4805 /* 4806 * Process an ingnore wide residue message. 4807 */ 4808 static void 4809 ahd_handle_ign_wide_residue(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4810 { 4811 u_int scb_index; 4812 struct scb *scb; 4813 4814 scb_index = ahd_get_scbptr(ahd); 4815 scb = ahd_lookup_scb(ahd, scb_index); 4816 /* 4817 * XXX Actually check data direction in the sequencer? 4818 * Perhaps add datadir to some spare bits in the hscb? 4819 */ 4820 if ((ahd_inb(ahd, SEQ_FLAGS) & DPHASE) == 0 4821 || aic_get_transfer_dir(scb) != CAM_DIR_IN) { 4822 /* 4823 * Ignore the message if we haven't 4824 * seen an appropriate data phase yet. 4825 */ 4826 } else { 4827 /* 4828 * If the residual occurred on the last 4829 * transfer and the transfer request was 4830 * expected to end on an odd count, do 4831 * nothing. Otherwise, subtract a byte 4832 * and update the residual count accordingly. 4833 */ 4834 uint32_t sgptr; 4835 4836 sgptr = ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR); 4837 if ((sgptr & SG_LIST_NULL) != 0 4838 && (ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE) 4839 & SCB_XFERLEN_ODD) != 0) { 4840 /* 4841 * If the residual occurred on the last 4842 * transfer and the transfer request was 4843 * expected to end on an odd count, do 4844 * nothing. 4845 */ 4846 } else { 4847 uint32_t data_cnt; 4848 uint64_t data_addr; 4849 uint32_t sglen; 4850 4851 /* Pull in the rest of the sgptr */ 4852 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 4853 data_cnt = ahd_inl_scbram(ahd, SCB_RESIDUAL_DATACNT); 4854 if ((sgptr & SG_LIST_NULL) != 0) { 4855 /* 4856 * The residual data count is not updated 4857 * for the command run to completion case. 4858 * Explicitly zero the count. 4859 */ 4860 data_cnt &= ~AHD_SG_LEN_MASK; 4861 } 4862 data_addr = ahd_inq(ahd, SHADDR); 4863 data_cnt += 1; 4864 data_addr -= 1; 4865 sgptr &= SG_PTR_MASK; 4866 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 4867 struct ahd_dma64_seg *sg; 4868 4869 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4870 4871 /* 4872 * The residual sg ptr points to the next S/G 4873 * to load so we must go back one. 4874 */ 4875 sg--; 4876 sglen = aic_le32toh(sg->len) & AHD_SG_LEN_MASK; 4877 if (sg != scb->sg_list 4878 && sglen < (data_cnt & AHD_SG_LEN_MASK)) { 4879 4880 sg--; 4881 sglen = aic_le32toh(sg->len); 4882 /* 4883 * Preserve High Address and SG_LIST 4884 * bits while setting the count to 1. 4885 */ 4886 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); 4887 data_addr = aic_le64toh(sg->addr) 4888 + (sglen & AHD_SG_LEN_MASK) 4889 - 1; 4890 4891 /* 4892 * Increment sg so it points to the 4893 * "next" sg. 4894 */ 4895 sg++; 4896 sgptr = ahd_sg_virt_to_bus(ahd, scb, 4897 sg); 4898 } 4899 } else { 4900 struct ahd_dma_seg *sg; 4901 4902 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4903 4904 /* 4905 * The residual sg ptr points to the next S/G 4906 * to load so we must go back one. 4907 */ 4908 sg--; 4909 sglen = aic_le32toh(sg->len) & AHD_SG_LEN_MASK; 4910 if (sg != scb->sg_list 4911 && sglen < (data_cnt & AHD_SG_LEN_MASK)) { 4912 4913 sg--; 4914 sglen = aic_le32toh(sg->len); 4915 /* 4916 * Preserve High Address and SG_LIST 4917 * bits while setting the count to 1. 4918 */ 4919 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); 4920 data_addr = aic_le32toh(sg->addr) 4921 + (sglen & AHD_SG_LEN_MASK) 4922 - 1; 4923 4924 /* 4925 * Increment sg so it points to the 4926 * "next" sg. 4927 */ 4928 sg++; 4929 sgptr = ahd_sg_virt_to_bus(ahd, scb, 4930 sg); 4931 } 4932 } 4933 /* 4934 * Toggle the "oddness" of the transfer length 4935 * to handle this mid-transfer ignore wide 4936 * residue. This ensures that the oddness is 4937 * correct for subsequent data transfers. 4938 */ 4939 ahd_outb(ahd, SCB_TASK_ATTRIBUTE, 4940 ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE) 4941 ^ SCB_XFERLEN_ODD); 4942 4943 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr); 4944 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, data_cnt); 4945 /* 4946 * The FIFO's pointers will be updated if/when the 4947 * sequencer re-enters a data phase. 4948 */ 4949 } 4950 } 4951 } 4952 4953 4954 /* 4955 * Reinitialize the data pointers for the active transfer 4956 * based on its current residual. 4957 */ 4958 static void 4959 ahd_reinitialize_dataptrs(struct ahd_softc *ahd) 4960 { 4961 struct scb *scb; 4962 ahd_mode_state saved_modes; 4963 u_int scb_index; 4964 u_int wait; 4965 uint32_t sgptr; 4966 uint32_t resid; 4967 uint64_t dataptr; 4968 4969 AHD_ASSERT_MODES(ahd, AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK, 4970 AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK); 4971 4972 scb_index = ahd_get_scbptr(ahd); 4973 scb = ahd_lookup_scb(ahd, scb_index); 4974 4975 /* 4976 * Release and reacquire the FIFO so we 4977 * have a clean slate. 4978 */ 4979 ahd_outb(ahd, DFFSXFRCTL, CLRCHN); 4980 wait = 1000; 4981 while (--wait && !(ahd_inb(ahd, MDFFSTAT) & FIFOFREE)) 4982 aic_delay(100); 4983 if (wait == 0) { 4984 ahd_print_path(ahd, scb); 4985 printf("ahd_reinitialize_dataptrs: Forcing FIFO free.\n"); 4986 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); 4987 } 4988 saved_modes = ahd_save_modes(ahd); 4989 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 4990 ahd_outb(ahd, DFFSTAT, 4991 ahd_inb(ahd, DFFSTAT) 4992 | (saved_modes == 0x11 ? CURRFIFO_1 : CURRFIFO_0)); 4993 4994 /* 4995 * Determine initial values for data_addr and data_cnt 4996 * for resuming the data phase. 4997 */ 4998 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 4999 sgptr &= SG_PTR_MASK; 5000 5001 resid = (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 2) << 16) 5002 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 1) << 8) 5003 | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT); 5004 5005 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 5006 struct ahd_dma64_seg *sg; 5007 5008 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 5009 5010 /* The residual sg_ptr always points to the next sg */ 5011 sg--; 5012 5013 dataptr = aic_le64toh(sg->addr) 5014 + (aic_le32toh(sg->len) & AHD_SG_LEN_MASK) 5015 - resid; 5016 ahd_outl(ahd, HADDR + 4, dataptr >> 32); 5017 } else { 5018 struct ahd_dma_seg *sg; 5019 5020 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 5021 5022 /* The residual sg_ptr always points to the next sg */ 5023 sg--; 5024 5025 dataptr = aic_le32toh(sg->addr) 5026 + (aic_le32toh(sg->len) & AHD_SG_LEN_MASK) 5027 - resid; 5028 ahd_outb(ahd, HADDR + 4, 5029 (aic_le32toh(sg->len) & ~AHD_SG_LEN_MASK) >> 24); 5030 } 5031 ahd_outl(ahd, HADDR, dataptr); 5032 ahd_outb(ahd, HCNT + 2, resid >> 16); 5033 ahd_outb(ahd, HCNT + 1, resid >> 8); 5034 ahd_outb(ahd, HCNT, resid); 5035 } 5036 5037 /* 5038 * Handle the effects of issuing a bus device reset message. 5039 */ 5040 static void 5041 ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 5042 u_int lun, cam_status status, char *message, 5043 int verbose_level) 5044 { 5045 #ifdef AHD_TARGET_MODE 5046 struct ahd_tmode_tstate* tstate; 5047 #endif 5048 int found; 5049 5050 found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, 5051 lun, SCB_LIST_NULL, devinfo->role, 5052 status); 5053 5054 #ifdef AHD_TARGET_MODE 5055 /* 5056 * Send an immediate notify ccb to all target mord peripheral 5057 * drivers affected by this action. 5058 */ 5059 tstate = ahd->enabled_targets[devinfo->our_scsiid]; 5060 if (tstate != NULL) { 5061 u_int cur_lun; 5062 u_int max_lun; 5063 5064 if (lun != CAM_LUN_WILDCARD) { 5065 cur_lun = 0; 5066 max_lun = AHD_NUM_LUNS - 1; 5067 } else { 5068 cur_lun = lun; 5069 max_lun = lun; 5070 } 5071 for (cur_lun <= max_lun; cur_lun++) { 5072 struct ahd_tmode_lstate* lstate; 5073 5074 lstate = tstate->enabled_luns[cur_lun]; 5075 if (lstate == NULL) 5076 continue; 5077 5078 ahd_queue_lstate_event(ahd, lstate, devinfo->our_scsiid, 5079 MSG_BUS_DEV_RESET, /*arg*/0); 5080 ahd_send_lstate_events(ahd, lstate); 5081 } 5082 } 5083 #endif 5084 5085 /* 5086 * Go back to async/narrow transfers and renegotiate. 5087 */ 5088 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 5089 AHD_TRANS_CUR, /*paused*/TRUE); 5090 ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0, 5091 /*ppr_options*/0, AHD_TRANS_CUR, 5092 /*paused*/TRUE); 5093 5094 if (status != CAM_SEL_TIMEOUT) 5095 ahd_send_async(ahd, devinfo->channel, devinfo->target, 5096 lun, AC_SENT_BDR, NULL); 5097 5098 if (message != NULL 5099 && (verbose_level <= bootverbose)) 5100 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd), 5101 message, devinfo->channel, devinfo->target, found); 5102 } 5103 5104 #ifdef AHD_TARGET_MODE 5105 static void 5106 ahd_setup_target_msgin(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 5107 struct scb *scb) 5108 { 5109 5110 /* 5111 * To facilitate adding multiple messages together, 5112 * each routine should increment the index and len 5113 * variables instead of setting them explicitly. 5114 */ 5115 ahd->msgout_index = 0; 5116 ahd->msgout_len = 0; 5117 5118 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 5119 ahd_build_transfer_msg(ahd, devinfo); 5120 else 5121 panic("ahd_intr: AWAITING target message with no message"); 5122 5123 ahd->msgout_index = 0; 5124 ahd->msg_type = MSG_TYPE_TARGET_MSGIN; 5125 } 5126 #endif 5127 /**************************** Initialization **********************************/ 5128 static u_int 5129 ahd_sglist_size(struct ahd_softc *ahd) 5130 { 5131 bus_size_t list_size; 5132 5133 list_size = sizeof(struct ahd_dma_seg) * AHD_NSEG; 5134 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 5135 list_size = sizeof(struct ahd_dma64_seg) * AHD_NSEG; 5136 return (list_size); 5137 } 5138 5139 /* 5140 * Calculate the optimum S/G List allocation size. S/G elements used 5141 * for a given transaction must be physically contiguous. Assume the 5142 * OS will allocate full pages to us, so it doesn't make sense to request 5143 * less than a page. 5144 */ 5145 static u_int 5146 ahd_sglist_allocsize(struct ahd_softc *ahd) 5147 { 5148 bus_size_t sg_list_increment; 5149 bus_size_t sg_list_size; 5150 bus_size_t max_list_size; 5151 bus_size_t best_list_size; 5152 5153 /* Start out with the minimum required for AHD_NSEG. */ 5154 sg_list_increment = ahd_sglist_size(ahd); 5155 sg_list_size = sg_list_increment; 5156 5157 /* Get us as close as possible to a page in size. */ 5158 while ((sg_list_size + sg_list_increment) <= PAGE_SIZE) 5159 sg_list_size += sg_list_increment; 5160 5161 /* 5162 * Try to reduce the amount of wastage by allocating 5163 * multiple pages. 5164 */ 5165 best_list_size = sg_list_size; 5166 max_list_size = roundup(sg_list_increment, PAGE_SIZE); 5167 if (max_list_size < 4 * PAGE_SIZE) 5168 max_list_size = 4 * PAGE_SIZE; 5169 if (max_list_size > (AHD_SCB_MAX_ALLOC * sg_list_increment)) 5170 max_list_size = (AHD_SCB_MAX_ALLOC * sg_list_increment); 5171 while ((sg_list_size + sg_list_increment) <= max_list_size 5172 && (sg_list_size % PAGE_SIZE) != 0) { 5173 bus_size_t new_mod; 5174 bus_size_t best_mod; 5175 5176 sg_list_size += sg_list_increment; 5177 new_mod = sg_list_size % PAGE_SIZE; 5178 best_mod = best_list_size % PAGE_SIZE; 5179 if (new_mod > best_mod || new_mod == 0) { 5180 best_list_size = sg_list_size; 5181 } 5182 } 5183 return (best_list_size); 5184 } 5185 5186 /* 5187 * Allocate a controller structure for a new device 5188 * and perform initial initializion. 5189 */ 5190 struct ahd_softc * 5191 ahd_alloc(void *platform_arg, char *name) 5192 { 5193 struct ahd_softc *ahd; 5194 5195 #ifndef __FreeBSD__ 5196 ahd = malloc(sizeof(*ahd), M_DEVBUF, M_NOWAIT); 5197 if (!ahd) { 5198 printf("aic7xxx: cannot malloc softc!\n"); 5199 free(name, M_DEVBUF); 5200 return NULL; 5201 } 5202 #else 5203 ahd = device_get_softc((device_t)platform_arg); 5204 #endif 5205 memset(ahd, 0, sizeof(*ahd)); 5206 ahd->seep_config = malloc(sizeof(*ahd->seep_config), 5207 M_DEVBUF, M_NOWAIT); 5208 if (ahd->seep_config == NULL) { 5209 #ifndef __FreeBSD__ 5210 free(ahd, M_DEVBUF); 5211 #endif 5212 free(name, M_DEVBUF); 5213 return (NULL); 5214 } 5215 LIST_INIT(&ahd->pending_scbs); 5216 /* We don't know our unit number until the OSM sets it */ 5217 ahd->name = name; 5218 ahd->unit = -1; 5219 ahd->description = NULL; 5220 ahd->bus_description = NULL; 5221 ahd->channel = 'A'; 5222 ahd->chip = AHD_NONE; 5223 ahd->features = AHD_FENONE; 5224 ahd->bugs = AHD_BUGNONE; 5225 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A 5226 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A; 5227 aic_timer_init(&ahd->reset_timer); 5228 aic_timer_init(&ahd->stat_timer); 5229 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT; 5230 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT; 5231 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT; 5232 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT; 5233 ahd->int_coalescing_stop_threshold = 5234 AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT; 5235 5236 if (ahd_platform_alloc(ahd, platform_arg) != 0) { 5237 ahd_free(ahd); 5238 ahd = NULL; 5239 } 5240 #ifdef AHD_DEBUG 5241 if ((ahd_debug & AHD_SHOW_MEMORY) != 0) { 5242 printf("%s: scb size = 0x%x, hscb size = 0x%x\n", 5243 ahd_name(ahd), (u_int)sizeof(struct scb), 5244 (u_int)sizeof(struct hardware_scb)); 5245 } 5246 #endif 5247 return (ahd); 5248 } 5249 5250 int 5251 ahd_softc_init(struct ahd_softc *ahd) 5252 { 5253 5254 ahd->unpause = 0; 5255 ahd->pause = PAUSE; 5256 return (0); 5257 } 5258 5259 void 5260 ahd_softc_insert(struct ahd_softc *ahd) 5261 { 5262 struct ahd_softc *list_ahd; 5263 5264 #if AIC_PCI_CONFIG > 0 5265 /* 5266 * Second Function PCI devices need to inherit some 5267 * settings from function 0. 5268 */ 5269 if ((ahd->features & AHD_MULTI_FUNC) != 0) { 5270 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) { 5271 aic_dev_softc_t list_pci; 5272 aic_dev_softc_t pci; 5273 5274 list_pci = list_ahd->dev_softc; 5275 pci = ahd->dev_softc; 5276 if (aic_get_pci_slot(list_pci) == aic_get_pci_slot(pci) 5277 && aic_get_pci_bus(list_pci) == aic_get_pci_bus(pci)) { 5278 struct ahd_softc *master; 5279 struct ahd_softc *slave; 5280 5281 if (aic_get_pci_function(list_pci) == 0) { 5282 master = list_ahd; 5283 slave = ahd; 5284 } else { 5285 master = ahd; 5286 slave = list_ahd; 5287 } 5288 slave->flags &= ~AHD_BIOS_ENABLED; 5289 slave->flags |= 5290 master->flags & AHD_BIOS_ENABLED; 5291 break; 5292 } 5293 } 5294 } 5295 #endif 5296 5297 /* 5298 * Insertion sort into our list of softcs. 5299 */ 5300 list_ahd = TAILQ_FIRST(&ahd_tailq); 5301 while (list_ahd != NULL 5302 && ahd_softc_comp(ahd, list_ahd) <= 0) 5303 list_ahd = TAILQ_NEXT(list_ahd, links); 5304 if (list_ahd != NULL) 5305 TAILQ_INSERT_BEFORE(list_ahd, ahd, links); 5306 else 5307 TAILQ_INSERT_TAIL(&ahd_tailq, ahd, links); 5308 ahd->init_level++; 5309 } 5310 5311 /* 5312 * Verify that the passed in softc pointer is for a 5313 * controller that is still configured. 5314 */ 5315 struct ahd_softc * 5316 ahd_find_softc(struct ahd_softc *ahd) 5317 { 5318 struct ahd_softc *list_ahd; 5319 5320 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) { 5321 if (list_ahd == ahd) 5322 return (ahd); 5323 } 5324 return (NULL); 5325 } 5326 5327 void 5328 ahd_set_unit(struct ahd_softc *ahd, int unit) 5329 { 5330 ahd->unit = unit; 5331 } 5332 5333 void 5334 ahd_set_name(struct ahd_softc *ahd, char *name) 5335 { 5336 if (ahd->name != NULL) 5337 free(ahd->name, M_DEVBUF); 5338 ahd->name = name; 5339 } 5340 5341 void 5342 ahd_free(struct ahd_softc *ahd) 5343 { 5344 int i; 5345 5346 ahd_terminate_recovery_thread(ahd); 5347 switch (ahd->init_level) { 5348 default: 5349 case 5: 5350 ahd_shutdown(ahd); 5351 /* FALLTHROUGH */ 5352 case 4: 5353 aic_dmamap_unload(ahd, ahd->shared_data_dmat, 5354 ahd->shared_data_map.dmamap); 5355 /* FALLTHROUGH */ 5356 case 3: 5357 aic_dmamem_free(ahd, ahd->shared_data_dmat, ahd->qoutfifo, 5358 ahd->shared_data_map.dmamap); 5359 aic_dmamap_destroy(ahd, ahd->shared_data_dmat, 5360 ahd->shared_data_map.dmamap); 5361 /* FALLTHROUGH */ 5362 case 2: 5363 aic_dma_tag_destroy(ahd, ahd->shared_data_dmat); 5364 case 1: 5365 #ifndef __linux__ 5366 aic_dma_tag_destroy(ahd, ahd->buffer_dmat); 5367 #endif 5368 break; 5369 case 0: 5370 break; 5371 } 5372 5373 #ifndef __linux__ 5374 aic_dma_tag_destroy(ahd, ahd->parent_dmat); 5375 #endif 5376 ahd_platform_free(ahd); 5377 ahd_fini_scbdata(ahd); 5378 for (i = 0; i < AHD_NUM_TARGETS; i++) { 5379 struct ahd_tmode_tstate *tstate; 5380 5381 tstate = ahd->enabled_targets[i]; 5382 if (tstate != NULL) { 5383 #if AHD_TARGET_MODE 5384 int j; 5385 5386 for (j = 0; j < AHD_NUM_LUNS; j++) { 5387 struct ahd_tmode_lstate *lstate; 5388 5389 lstate = tstate->enabled_luns[j]; 5390 if (lstate != NULL) { 5391 xpt_free_path(lstate->path); 5392 free(lstate, M_DEVBUF); 5393 } 5394 } 5395 #endif 5396 free(tstate, M_DEVBUF); 5397 } 5398 } 5399 #if AHD_TARGET_MODE 5400 if (ahd->black_hole != NULL) { 5401 xpt_free_path(ahd->black_hole->path); 5402 free(ahd->black_hole, M_DEVBUF); 5403 } 5404 #endif 5405 if (ahd->name != NULL) 5406 free(ahd->name, M_DEVBUF); 5407 if (ahd->seep_config != NULL) 5408 free(ahd->seep_config, M_DEVBUF); 5409 if (ahd->saved_stack != NULL) 5410 free(ahd->saved_stack, M_DEVBUF); 5411 #ifndef __FreeBSD__ 5412 free(ahd, M_DEVBUF); 5413 #endif 5414 return; 5415 } 5416 5417 void 5418 ahd_shutdown(void *arg) 5419 { 5420 struct ahd_softc *ahd; 5421 5422 ahd = (struct ahd_softc *)arg; 5423 5424 /* 5425 * Stop periodic timer callbacks. 5426 */ 5427 aic_timer_stop(&ahd->reset_timer); 5428 aic_timer_stop(&ahd->stat_timer); 5429 5430 /* This will reset most registers to 0, but not all */ 5431 ahd_reset(ahd, /*reinit*/FALSE); 5432 } 5433 5434 /* 5435 * Reset the controller and record some information about it 5436 * that is only available just after a reset. If "reinit" is 5437 * non-zero, this reset occured after initial configuration 5438 * and the caller requests that the chip be fully reinitialized 5439 * to a runable state. Chip interrupts are *not* enabled after 5440 * a reinitialization. The caller must enable interrupts via 5441 * ahd_intr_enable(). 5442 */ 5443 int 5444 ahd_reset(struct ahd_softc *ahd, int reinit) 5445 { 5446 u_int sxfrctl1; 5447 int wait; 5448 uint32_t cmd; 5449 5450 /* 5451 * Preserve the value of the SXFRCTL1 register for all channels. 5452 * It contains settings that affect termination and we don't want 5453 * to disturb the integrity of the bus. 5454 */ 5455 ahd_pause(ahd); 5456 ahd_update_modes(ahd); 5457 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5458 sxfrctl1 = ahd_inb(ahd, SXFRCTL1); 5459 5460 cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 5461 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { 5462 uint32_t mod_cmd; 5463 5464 /* 5465 * A4 Razor #632 5466 * During the assertion of CHIPRST, the chip 5467 * does not disable its parity logic prior to 5468 * the start of the reset. This may cause a 5469 * parity error to be detected and thus a 5470 * spurious SERR or PERR assertion. Disble 5471 * PERR and SERR responses during the CHIPRST. 5472 */ 5473 mod_cmd = cmd & ~(PCIM_CMD_PERRESPEN|PCIM_CMD_SERRESPEN); 5474 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 5475 mod_cmd, /*bytes*/2); 5476 } 5477 ahd_outb(ahd, HCNTRL, CHIPRST | ahd->pause); 5478 5479 /* 5480 * Ensure that the reset has finished. We delay 1000us 5481 * prior to reading the register to make sure the chip 5482 * has sufficiently completed its reset to handle register 5483 * accesses. 5484 */ 5485 wait = 1000; 5486 do { 5487 aic_delay(1000); 5488 } while (--wait && !(ahd_inb(ahd, HCNTRL) & CHIPRSTACK)); 5489 5490 if (wait == 0) { 5491 printf("%s: WARNING - Failed chip reset! " 5492 "Trying to initialize anyway.\n", ahd_name(ahd)); 5493 } 5494 ahd_outb(ahd, HCNTRL, ahd->pause); 5495 5496 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { 5497 /* 5498 * Clear any latched PCI error status and restore 5499 * previous SERR and PERR response enables. 5500 */ 5501 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 5502 0xFF, /*bytes*/1); 5503 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 5504 cmd, /*bytes*/2); 5505 } 5506 5507 /* 5508 * Mode should be SCSI after a chip reset, but lets 5509 * set it just to be safe. We touch the MODE_PTR 5510 * register directly so as to bypass the lazy update 5511 * code in ahd_set_modes(). 5512 */ 5513 ahd_known_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5514 ahd_outb(ahd, MODE_PTR, 5515 ahd_build_mode_state(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI)); 5516 5517 /* 5518 * Restore SXFRCTL1. 5519 * 5520 * We must always initialize STPWEN to 1 before we 5521 * restore the saved values. STPWEN is initialized 5522 * to a tri-state condition which can only be cleared 5523 * by turning it on. 5524 */ 5525 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 5526 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 5527 5528 /* Determine chip configuration */ 5529 ahd->features &= ~AHD_WIDE; 5530 if ((ahd_inb(ahd, SBLKCTL) & SELWIDE) != 0) 5531 ahd->features |= AHD_WIDE; 5532 5533 /* 5534 * If a recovery action has forced a chip reset, 5535 * re-initialize the chip to our liking. 5536 */ 5537 if (reinit != 0) 5538 ahd_chip_init(ahd); 5539 5540 return (0); 5541 } 5542 5543 /* 5544 * Determine the number of SCBs available on the controller 5545 */ 5546 int 5547 ahd_probe_scbs(struct ahd_softc *ahd) { 5548 int i; 5549 5550 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 5551 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 5552 for (i = 0; i < AHD_SCB_MAX; i++) { 5553 int j; 5554 5555 ahd_set_scbptr(ahd, i); 5556 ahd_outw(ahd, SCB_BASE, i); 5557 for (j = 2; j < 64; j++) 5558 ahd_outb(ahd, SCB_BASE+j, 0); 5559 /* Start out life as unallocated (needing an abort) */ 5560 ahd_outb(ahd, SCB_CONTROL, MK_MESSAGE); 5561 if (ahd_inw_scbram(ahd, SCB_BASE) != i) 5562 break; 5563 ahd_set_scbptr(ahd, 0); 5564 if (ahd_inw_scbram(ahd, SCB_BASE) != 0) 5565 break; 5566 } 5567 return (i); 5568 } 5569 5570 static void 5571 ahd_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 5572 { 5573 bus_addr_t *baddr; 5574 5575 baddr = (bus_addr_t *)arg; 5576 *baddr = segs->ds_addr; 5577 } 5578 5579 static void 5580 ahd_initialize_hscbs(struct ahd_softc *ahd) 5581 { 5582 int i; 5583 5584 for (i = 0; i < ahd->scb_data.maxhscbs; i++) { 5585 ahd_set_scbptr(ahd, i); 5586 5587 /* Clear the control byte. */ 5588 ahd_outb(ahd, SCB_CONTROL, 0); 5589 5590 /* Set the next pointer */ 5591 ahd_outw(ahd, SCB_NEXT, SCB_LIST_NULL); 5592 } 5593 } 5594 5595 static int 5596 ahd_init_scbdata(struct ahd_softc *ahd) 5597 { 5598 struct scb_data *scb_data; 5599 int i; 5600 5601 scb_data = &ahd->scb_data; 5602 TAILQ_INIT(&scb_data->free_scbs); 5603 for (i = 0; i < AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT; i++) 5604 LIST_INIT(&scb_data->free_scb_lists[i]); 5605 LIST_INIT(&scb_data->any_dev_free_scb_list); 5606 SLIST_INIT(&scb_data->hscb_maps); 5607 SLIST_INIT(&scb_data->sg_maps); 5608 SLIST_INIT(&scb_data->sense_maps); 5609 5610 /* Determine the number of hardware SCBs and initialize them */ 5611 scb_data->maxhscbs = ahd_probe_scbs(ahd); 5612 if (scb_data->maxhscbs == 0) { 5613 printf("%s: No SCB space found\n", ahd_name(ahd)); 5614 return (ENXIO); 5615 } 5616 5617 ahd_initialize_hscbs(ahd); 5618 5619 /* 5620 * Create our DMA tags. These tags define the kinds of device 5621 * accessible memory allocations and memory mappings we will 5622 * need to perform during normal operation. 5623 * 5624 * Unless we need to further restrict the allocation, we rely 5625 * on the restrictions of the parent dmat, hence the common 5626 * use of MAXADDR and MAXSIZE. 5627 */ 5628 5629 /* DMA tag for our hardware scb structures */ 5630 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1, 5631 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 5632 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 5633 /*highaddr*/BUS_SPACE_MAXADDR, 5634 /*filter*/NULL, /*filterarg*/NULL, 5635 PAGE_SIZE, /*nsegments*/1, 5636 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 5637 /*flags*/0, &scb_data->hscb_dmat) != 0) { 5638 goto error_exit; 5639 } 5640 5641 scb_data->init_level++; 5642 5643 /* DMA tag for our S/G structures. */ 5644 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/8, 5645 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 5646 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 5647 /*highaddr*/BUS_SPACE_MAXADDR, 5648 /*filter*/NULL, /*filterarg*/NULL, 5649 ahd_sglist_allocsize(ahd), /*nsegments*/1, 5650 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 5651 /*flags*/0, &scb_data->sg_dmat) != 0) { 5652 goto error_exit; 5653 } 5654 #ifdef AHD_DEBUG 5655 if ((ahd_debug & AHD_SHOW_MEMORY) != 0) 5656 printf("%s: ahd_sglist_allocsize = 0x%x\n", ahd_name(ahd), 5657 ahd_sglist_allocsize(ahd)); 5658 #endif 5659 5660 scb_data->init_level++; 5661 5662 /* DMA tag for our sense buffers. We allocate in page sized chunks */ 5663 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1, 5664 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 5665 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 5666 /*highaddr*/BUS_SPACE_MAXADDR, 5667 /*filter*/NULL, /*filterarg*/NULL, 5668 PAGE_SIZE, /*nsegments*/1, 5669 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 5670 /*flags*/0, &scb_data->sense_dmat) != 0) { 5671 goto error_exit; 5672 } 5673 5674 scb_data->init_level++; 5675 5676 /* Perform initial CCB allocation */ 5677 ahd_alloc_scbs(ahd); 5678 5679 if (scb_data->numscbs == 0) { 5680 printf("%s: ahd_init_scbdata - " 5681 "Unable to allocate initial scbs\n", 5682 ahd_name(ahd)); 5683 goto error_exit; 5684 } 5685 5686 /* 5687 * Note that we were successfull 5688 */ 5689 return (0); 5690 5691 error_exit: 5692 5693 return (ENOMEM); 5694 } 5695 5696 static struct scb * 5697 ahd_find_scb_by_tag(struct ahd_softc *ahd, u_int tag) 5698 { 5699 struct scb *scb; 5700 5701 /* 5702 * Look on the pending list. 5703 */ 5704 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 5705 if (SCB_GET_TAG(scb) == tag) 5706 return (scb); 5707 } 5708 5709 /* 5710 * Then on all of the collision free lists. 5711 */ 5712 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 5713 struct scb *list_scb; 5714 5715 list_scb = scb; 5716 do { 5717 if (SCB_GET_TAG(list_scb) == tag) 5718 return (list_scb); 5719 list_scb = LIST_NEXT(list_scb, collision_links); 5720 } while (list_scb); 5721 } 5722 5723 /* 5724 * And finally on the generic free list. 5725 */ 5726 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { 5727 if (SCB_GET_TAG(scb) == tag) 5728 return (scb); 5729 } 5730 5731 return (NULL); 5732 } 5733 5734 static void 5735 ahd_fini_scbdata(struct ahd_softc *ahd) 5736 { 5737 struct scb_data *scb_data; 5738 5739 scb_data = &ahd->scb_data; 5740 if (scb_data == NULL) 5741 return; 5742 5743 switch (scb_data->init_level) { 5744 default: 5745 case 7: 5746 { 5747 struct map_node *sns_map; 5748 5749 while ((sns_map = SLIST_FIRST(&scb_data->sense_maps)) != NULL) { 5750 SLIST_REMOVE_HEAD(&scb_data->sense_maps, links); 5751 aic_dmamap_unload(ahd, scb_data->sense_dmat, 5752 sns_map->dmamap); 5753 aic_dmamem_free(ahd, scb_data->sense_dmat, 5754 sns_map->vaddr, sns_map->dmamap); 5755 free(sns_map, M_DEVBUF); 5756 } 5757 aic_dma_tag_destroy(ahd, scb_data->sense_dmat); 5758 /* FALLTHROUGH */ 5759 } 5760 case 6: 5761 { 5762 struct map_node *sg_map; 5763 5764 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)) != NULL) { 5765 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 5766 aic_dmamap_unload(ahd, scb_data->sg_dmat, 5767 sg_map->dmamap); 5768 aic_dmamem_free(ahd, scb_data->sg_dmat, 5769 sg_map->vaddr, sg_map->dmamap); 5770 free(sg_map, M_DEVBUF); 5771 } 5772 aic_dma_tag_destroy(ahd, scb_data->sg_dmat); 5773 /* FALLTHROUGH */ 5774 } 5775 case 5: 5776 { 5777 struct map_node *hscb_map; 5778 5779 while ((hscb_map = SLIST_FIRST(&scb_data->hscb_maps)) != NULL) { 5780 SLIST_REMOVE_HEAD(&scb_data->hscb_maps, links); 5781 aic_dmamap_unload(ahd, scb_data->hscb_dmat, 5782 hscb_map->dmamap); 5783 aic_dmamem_free(ahd, scb_data->hscb_dmat, 5784 hscb_map->vaddr, hscb_map->dmamap); 5785 free(hscb_map, M_DEVBUF); 5786 } 5787 aic_dma_tag_destroy(ahd, scb_data->hscb_dmat); 5788 /* FALLTHROUGH */ 5789 } 5790 case 4: 5791 case 3: 5792 case 2: 5793 case 1: 5794 case 0: 5795 break; 5796 } 5797 } 5798 5799 /* 5800 * DSP filter Bypass must be enabled until the first selection 5801 * after a change in bus mode (Razor #491 and #493). 5802 */ 5803 static void 5804 ahd_setup_iocell_workaround(struct ahd_softc *ahd) 5805 { 5806 ahd_mode_state saved_modes; 5807 5808 saved_modes = ahd_save_modes(ahd); 5809 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5810 ahd_outb(ahd, DSPDATACTL, ahd_inb(ahd, DSPDATACTL) 5811 | BYPASSENAB | RCVROFFSTDIS | XMITOFFSTDIS); 5812 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) | (ENSELDO|ENSELDI)); 5813 #ifdef AHD_DEBUG 5814 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5815 printf("%s: Setting up iocell workaround\n", ahd_name(ahd)); 5816 #endif 5817 ahd_restore_modes(ahd, saved_modes); 5818 ahd->flags &= ~AHD_HAD_FIRST_SEL; 5819 } 5820 5821 static void 5822 ahd_iocell_first_selection(struct ahd_softc *ahd) 5823 { 5824 ahd_mode_state saved_modes; 5825 u_int sblkctl; 5826 5827 if ((ahd->flags & AHD_HAD_FIRST_SEL) != 0) 5828 return; 5829 saved_modes = ahd_save_modes(ahd); 5830 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5831 sblkctl = ahd_inb(ahd, SBLKCTL); 5832 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5833 #ifdef AHD_DEBUG 5834 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5835 printf("%s: iocell first selection\n", ahd_name(ahd)); 5836 #endif 5837 if ((sblkctl & ENAB40) != 0) { 5838 ahd_outb(ahd, DSPDATACTL, 5839 ahd_inb(ahd, DSPDATACTL) & ~BYPASSENAB); 5840 #ifdef AHD_DEBUG 5841 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5842 printf("%s: BYPASS now disabled\n", ahd_name(ahd)); 5843 #endif 5844 } 5845 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) & ~(ENSELDO|ENSELDI)); 5846 ahd_outb(ahd, CLRINT, CLRSCSIINT); 5847 ahd_restore_modes(ahd, saved_modes); 5848 ahd->flags |= AHD_HAD_FIRST_SEL; 5849 } 5850 5851 /*************************** SCB Management ***********************************/ 5852 static void 5853 ahd_add_col_list(struct ahd_softc *ahd, struct scb *scb, u_int col_idx) 5854 { 5855 struct scb_list *free_list; 5856 struct scb_tailq *free_tailq; 5857 struct scb *first_scb; 5858 5859 scb->flags |= SCB_ON_COL_LIST; 5860 AHD_SET_SCB_COL_IDX(scb, col_idx); 5861 free_list = &ahd->scb_data.free_scb_lists[col_idx]; 5862 free_tailq = &ahd->scb_data.free_scbs; 5863 first_scb = LIST_FIRST(free_list); 5864 if (first_scb != NULL) { 5865 LIST_INSERT_AFTER(first_scb, scb, collision_links); 5866 } else { 5867 LIST_INSERT_HEAD(free_list, scb, collision_links); 5868 TAILQ_INSERT_TAIL(free_tailq, scb, links.tqe); 5869 } 5870 } 5871 5872 static void 5873 ahd_rem_col_list(struct ahd_softc *ahd, struct scb *scb) 5874 { 5875 struct scb_list *free_list; 5876 struct scb_tailq *free_tailq; 5877 struct scb *first_scb; 5878 u_int col_idx; 5879 5880 scb->flags &= ~SCB_ON_COL_LIST; 5881 col_idx = AHD_GET_SCB_COL_IDX(ahd, scb); 5882 free_list = &ahd->scb_data.free_scb_lists[col_idx]; 5883 free_tailq = &ahd->scb_data.free_scbs; 5884 first_scb = LIST_FIRST(free_list); 5885 if (first_scb == scb) { 5886 struct scb *next_scb; 5887 5888 /* 5889 * Maintain order in the collision free 5890 * lists for fairness if this device has 5891 * other colliding tags active. 5892 */ 5893 next_scb = LIST_NEXT(scb, collision_links); 5894 if (next_scb != NULL) { 5895 TAILQ_INSERT_AFTER(free_tailq, scb, 5896 next_scb, links.tqe); 5897 } 5898 TAILQ_REMOVE(free_tailq, scb, links.tqe); 5899 } 5900 LIST_REMOVE(scb, collision_links); 5901 } 5902 5903 /* 5904 * Get a free scb. If there are none, see if we can allocate a new SCB. 5905 */ 5906 struct scb * 5907 ahd_get_scb(struct ahd_softc *ahd, u_int col_idx) 5908 { 5909 struct scb *scb; 5910 int tries; 5911 5912 tries = 0; 5913 look_again: 5914 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 5915 if (AHD_GET_SCB_COL_IDX(ahd, scb) != col_idx) { 5916 ahd_rem_col_list(ahd, scb); 5917 goto found; 5918 } 5919 } 5920 if ((scb = LIST_FIRST(&ahd->scb_data.any_dev_free_scb_list)) == NULL) { 5921 5922 if (tries++ != 0) 5923 return (NULL); 5924 ahd_alloc_scbs(ahd); 5925 goto look_again; 5926 } 5927 LIST_REMOVE(scb, links.le); 5928 if (col_idx != AHD_NEVER_COL_IDX 5929 && (scb->col_scb != NULL) 5930 && (scb->col_scb->flags & SCB_ACTIVE) == 0) { 5931 LIST_REMOVE(scb->col_scb, links.le); 5932 ahd_add_col_list(ahd, scb->col_scb, col_idx); 5933 } 5934 found: 5935 scb->flags |= SCB_ACTIVE; 5936 return (scb); 5937 } 5938 5939 /* 5940 * Return an SCB resource to the free list. 5941 */ 5942 void 5943 ahd_free_scb(struct ahd_softc *ahd, struct scb *scb) 5944 { 5945 5946 /* Clean up for the next user */ 5947 scb->flags = SCB_FLAG_NONE; 5948 scb->hscb->control = 0; 5949 ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = NULL; 5950 5951 if (scb->col_scb == NULL) { 5952 5953 /* 5954 * No collision possible. Just free normally. 5955 */ 5956 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5957 scb, links.le); 5958 } else if ((scb->col_scb->flags & SCB_ON_COL_LIST) != 0) { 5959 5960 /* 5961 * The SCB we might have collided with is on 5962 * a free collision list. Put both SCBs on 5963 * the generic list. 5964 */ 5965 ahd_rem_col_list(ahd, scb->col_scb); 5966 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5967 scb, links.le); 5968 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5969 scb->col_scb, links.le); 5970 } else if ((scb->col_scb->flags 5971 & (SCB_PACKETIZED|SCB_ACTIVE)) == SCB_ACTIVE 5972 && (scb->col_scb->hscb->control & TAG_ENB) != 0) { 5973 5974 /* 5975 * The SCB we might collide with on the next allocation 5976 * is still active in a non-packetized, tagged, context. 5977 * Put us on the SCB collision list. 5978 */ 5979 ahd_add_col_list(ahd, scb, 5980 AHD_GET_SCB_COL_IDX(ahd, scb->col_scb)); 5981 } else { 5982 /* 5983 * The SCB we might collide with on the next allocation 5984 * is either active in a packetized context, or free. 5985 * Since we can't collide, put this SCB on the generic 5986 * free list. 5987 */ 5988 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5989 scb, links.le); 5990 } 5991 5992 aic_platform_scb_free(ahd, scb); 5993 } 5994 5995 void 5996 ahd_alloc_scbs(struct ahd_softc *ahd) 5997 { 5998 struct scb_data *scb_data; 5999 struct scb *next_scb; 6000 struct hardware_scb *hscb; 6001 struct map_node *hscb_map; 6002 struct map_node *sg_map; 6003 struct map_node *sense_map; 6004 uint8_t *segs; 6005 uint8_t *sense_data; 6006 bus_addr_t hscb_busaddr; 6007 bus_addr_t sg_busaddr; 6008 bus_addr_t sense_busaddr; 6009 int newcount; 6010 int i; 6011 6012 scb_data = &ahd->scb_data; 6013 if (scb_data->numscbs >= AHD_SCB_MAX_ALLOC) 6014 /* Can't allocate any more */ 6015 return; 6016 6017 if (scb_data->scbs_left != 0) { 6018 int offset; 6019 6020 offset = (PAGE_SIZE / sizeof(*hscb)) - scb_data->scbs_left; 6021 hscb_map = SLIST_FIRST(&scb_data->hscb_maps); 6022 hscb = &((struct hardware_scb *)hscb_map->vaddr)[offset]; 6023 hscb_busaddr = hscb_map->busaddr + (offset * sizeof(*hscb)); 6024 } else { 6025 hscb_map = malloc(sizeof(*hscb_map), M_DEVBUF, M_NOWAIT); 6026 6027 if (hscb_map == NULL) 6028 return; 6029 6030 /* Allocate the next batch of hardware SCBs */ 6031 if (aic_dmamem_alloc(ahd, scb_data->hscb_dmat, 6032 (void **)&hscb_map->vaddr, 6033 BUS_DMA_NOWAIT, &hscb_map->dmamap) != 0) { 6034 free(hscb_map, M_DEVBUF); 6035 return; 6036 } 6037 6038 SLIST_INSERT_HEAD(&scb_data->hscb_maps, hscb_map, links); 6039 6040 aic_dmamap_load(ahd, scb_data->hscb_dmat, hscb_map->dmamap, 6041 hscb_map->vaddr, PAGE_SIZE, ahd_dmamap_cb, 6042 &hscb_map->busaddr, /*flags*/0); 6043 6044 hscb = (struct hardware_scb *)hscb_map->vaddr; 6045 hscb_busaddr = hscb_map->busaddr; 6046 scb_data->scbs_left = PAGE_SIZE / sizeof(*hscb); 6047 } 6048 6049 if (scb_data->sgs_left != 0) { 6050 int offset; 6051 6052 offset = ((ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd)) 6053 - scb_data->sgs_left) * ahd_sglist_size(ahd); 6054 sg_map = SLIST_FIRST(&scb_data->sg_maps); 6055 segs = sg_map->vaddr + offset; 6056 sg_busaddr = sg_map->busaddr + offset; 6057 } else { 6058 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 6059 6060 if (sg_map == NULL) 6061 return; 6062 6063 /* Allocate the next batch of S/G lists */ 6064 if (aic_dmamem_alloc(ahd, scb_data->sg_dmat, 6065 (void **)&sg_map->vaddr, 6066 BUS_DMA_NOWAIT, &sg_map->dmamap) != 0) { 6067 free(sg_map, M_DEVBUF); 6068 return; 6069 } 6070 6071 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 6072 6073 aic_dmamap_load(ahd, scb_data->sg_dmat, sg_map->dmamap, 6074 sg_map->vaddr, ahd_sglist_allocsize(ahd), 6075 ahd_dmamap_cb, &sg_map->busaddr, /*flags*/0); 6076 6077 segs = sg_map->vaddr; 6078 sg_busaddr = sg_map->busaddr; 6079 scb_data->sgs_left = 6080 ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd); 6081 #ifdef AHD_DEBUG 6082 if (ahd_debug & AHD_SHOW_MEMORY) 6083 printf("Mapped SG data\n"); 6084 #endif 6085 } 6086 6087 if (scb_data->sense_left != 0) { 6088 int offset; 6089 6090 offset = PAGE_SIZE - (AHD_SENSE_BUFSIZE * scb_data->sense_left); 6091 sense_map = SLIST_FIRST(&scb_data->sense_maps); 6092 sense_data = sense_map->vaddr + offset; 6093 sense_busaddr = sense_map->busaddr + offset; 6094 } else { 6095 sense_map = malloc(sizeof(*sense_map), M_DEVBUF, M_NOWAIT); 6096 6097 if (sense_map == NULL) 6098 return; 6099 6100 /* Allocate the next batch of sense buffers */ 6101 if (aic_dmamem_alloc(ahd, scb_data->sense_dmat, 6102 (void **)&sense_map->vaddr, 6103 BUS_DMA_NOWAIT, &sense_map->dmamap) != 0) { 6104 free(sense_map, M_DEVBUF); 6105 return; 6106 } 6107 6108 SLIST_INSERT_HEAD(&scb_data->sense_maps, sense_map, links); 6109 6110 aic_dmamap_load(ahd, scb_data->sense_dmat, sense_map->dmamap, 6111 sense_map->vaddr, PAGE_SIZE, ahd_dmamap_cb, 6112 &sense_map->busaddr, /*flags*/0); 6113 6114 sense_data = sense_map->vaddr; 6115 sense_busaddr = sense_map->busaddr; 6116 scb_data->sense_left = PAGE_SIZE / AHD_SENSE_BUFSIZE; 6117 #ifdef AHD_DEBUG 6118 if (ahd_debug & AHD_SHOW_MEMORY) 6119 printf("Mapped sense data\n"); 6120 #endif 6121 } 6122 6123 newcount = MIN(scb_data->sense_left, scb_data->scbs_left); 6124 newcount = MIN(newcount, scb_data->sgs_left); 6125 newcount = MIN(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs)); 6126 scb_data->sense_left -= newcount; 6127 scb_data->scbs_left -= newcount; 6128 scb_data->sgs_left -= newcount; 6129 for (i = 0; i < newcount; i++) { 6130 struct scb_platform_data *pdata; 6131 u_int col_tag; 6132 #ifndef __linux__ 6133 int error; 6134 #endif 6135 6136 next_scb = (struct scb *)malloc(sizeof(*next_scb), 6137 M_DEVBUF, M_NOWAIT); 6138 if (next_scb == NULL) 6139 break; 6140 6141 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), 6142 M_DEVBUF, M_NOWAIT); 6143 if (pdata == NULL) { 6144 free(next_scb, M_DEVBUF); 6145 break; 6146 } 6147 next_scb->platform_data = pdata; 6148 next_scb->hscb_map = hscb_map; 6149 next_scb->sg_map = sg_map; 6150 next_scb->sense_map = sense_map; 6151 next_scb->sg_list = segs; 6152 next_scb->sense_data = sense_data; 6153 next_scb->sense_busaddr = sense_busaddr; 6154 memset(hscb, 0, sizeof(*hscb)); 6155 next_scb->hscb = hscb; 6156 hscb->hscb_busaddr = aic_htole32(hscb_busaddr); 6157 6158 /* 6159 * The sequencer always starts with the second entry. 6160 * The first entry is embedded in the scb. 6161 */ 6162 next_scb->sg_list_busaddr = sg_busaddr; 6163 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 6164 next_scb->sg_list_busaddr 6165 += sizeof(struct ahd_dma64_seg); 6166 else 6167 next_scb->sg_list_busaddr += sizeof(struct ahd_dma_seg); 6168 next_scb->ahd_softc = ahd; 6169 next_scb->flags = SCB_FLAG_NONE; 6170 #ifndef __linux__ 6171 error = aic_dmamap_create(ahd, ahd->buffer_dmat, /*flags*/0, 6172 &next_scb->dmamap); 6173 if (error != 0) { 6174 free(next_scb, M_DEVBUF); 6175 free(pdata, M_DEVBUF); 6176 break; 6177 } 6178 #endif 6179 next_scb->hscb->tag = aic_htole16(scb_data->numscbs); 6180 col_tag = scb_data->numscbs ^ 0x100; 6181 next_scb->col_scb = ahd_find_scb_by_tag(ahd, col_tag); 6182 if (next_scb->col_scb != NULL) 6183 next_scb->col_scb->col_scb = next_scb; 6184 ahd_free_scb(ahd, next_scb); 6185 hscb++; 6186 hscb_busaddr += sizeof(*hscb); 6187 segs += ahd_sglist_size(ahd); 6188 sg_busaddr += ahd_sglist_size(ahd); 6189 sense_data += AHD_SENSE_BUFSIZE; 6190 sense_busaddr += AHD_SENSE_BUFSIZE; 6191 scb_data->numscbs++; 6192 } 6193 } 6194 6195 void 6196 ahd_controller_info(struct ahd_softc *ahd, char *buf) 6197 { 6198 const char *speed; 6199 const char *type; 6200 int len; 6201 6202 len = sprintf(buf, "%s: ", ahd_chip_names[ahd->chip & AHD_CHIPID_MASK]); 6203 buf += len; 6204 6205 speed = "Ultra320 "; 6206 if ((ahd->features & AHD_WIDE) != 0) { 6207 type = "Wide "; 6208 } else { 6209 type = "Single "; 6210 } 6211 len = sprintf(buf, "%s%sChannel %c, SCSI Id=%d, ", 6212 speed, type, ahd->channel, ahd->our_id); 6213 buf += len; 6214 6215 sprintf(buf, "%s, %d SCBs", ahd->bus_description, 6216 ahd->scb_data.maxhscbs); 6217 } 6218 6219 static const char *channel_strings[] = { 6220 "Primary Low", 6221 "Primary High", 6222 "Secondary Low", 6223 "Secondary High" 6224 }; 6225 6226 static const char *termstat_strings[] = { 6227 "Terminated Correctly", 6228 "Over Terminated", 6229 "Under Terminated", 6230 "Not Configured" 6231 }; 6232 6233 /* 6234 * Start the board, ready for normal operation 6235 */ 6236 int 6237 ahd_init(struct ahd_softc *ahd) 6238 { 6239 uint8_t *next_vaddr; 6240 bus_addr_t next_baddr; 6241 size_t driver_data_size; 6242 int i; 6243 int error; 6244 u_int warn_user; 6245 uint8_t current_sensing; 6246 uint8_t fstat; 6247 6248 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 6249 6250 ahd->stack_size = ahd_probe_stack_size(ahd); 6251 ahd->saved_stack = malloc(ahd->stack_size * sizeof(uint16_t), 6252 M_DEVBUF, M_NOWAIT); 6253 if (ahd->saved_stack == NULL) 6254 return (ENOMEM); 6255 6256 /* 6257 * Verify that the compiler hasn't over-agressively 6258 * padded important structures. 6259 */ 6260 if (sizeof(struct hardware_scb) != 64) 6261 panic("Hardware SCB size is incorrect"); 6262 6263 #ifdef AHD_DEBUG 6264 if ((ahd_debug & AHD_DEBUG_SEQUENCER) != 0) 6265 ahd->flags |= AHD_SEQUENCER_DEBUG; 6266 #endif 6267 6268 /* 6269 * Default to allowing initiator operations. 6270 */ 6271 ahd->flags |= AHD_INITIATORROLE; 6272 6273 /* 6274 * Only allow target mode features if this unit has them enabled. 6275 */ 6276 if ((AHD_TMODE_ENABLE & (0x1 << ahd->unit)) == 0) 6277 ahd->features &= ~AHD_TARGETMODE; 6278 6279 #ifndef __linux__ 6280 /* DMA tag for mapping buffers into device visible space. */ 6281 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1, 6282 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 6283 /*lowaddr*/ahd->flags & AHD_39BIT_ADDRESSING 6284 ? (bus_addr_t)0x7FFFFFFFFFULL 6285 : BUS_SPACE_MAXADDR_32BIT, 6286 /*highaddr*/BUS_SPACE_MAXADDR, 6287 /*filter*/NULL, /*filterarg*/NULL, 6288 /*maxsize*/(AHD_NSEG - 1) * PAGE_SIZE, 6289 /*nsegments*/AHD_NSEG, 6290 /*maxsegsz*/AHD_MAXTRANSFER_SIZE, 6291 /*flags*/BUS_DMA_ALLOCNOW, 6292 &ahd->buffer_dmat) != 0) { 6293 return (ENOMEM); 6294 } 6295 #endif 6296 6297 ahd->init_level++; 6298 6299 /* 6300 * DMA tag for our command fifos and other data in system memory 6301 * the card's sequencer must be able to access. For initiator 6302 * roles, we need to allocate space for the qoutfifo. When providing 6303 * for the target mode role, we must additionally provide space for 6304 * the incoming target command fifo. 6305 */ 6306 driver_data_size = AHD_SCB_MAX * sizeof(*ahd->qoutfifo) 6307 + sizeof(struct hardware_scb); 6308 if ((ahd->features & AHD_TARGETMODE) != 0) 6309 driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd); 6310 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) 6311 driver_data_size += PKT_OVERRUN_BUFSIZE; 6312 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1, 6313 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 6314 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 6315 /*highaddr*/BUS_SPACE_MAXADDR, 6316 /*filter*/NULL, /*filterarg*/NULL, 6317 driver_data_size, 6318 /*nsegments*/1, 6319 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 6320 /*flags*/0, &ahd->shared_data_dmat) != 0) { 6321 return (ENOMEM); 6322 } 6323 6324 ahd->init_level++; 6325 6326 /* Allocation of driver data */ 6327 if (aic_dmamem_alloc(ahd, ahd->shared_data_dmat, 6328 (void **)&ahd->shared_data_map.vaddr, 6329 BUS_DMA_NOWAIT, 6330 &ahd->shared_data_map.dmamap) != 0) { 6331 return (ENOMEM); 6332 } 6333 6334 ahd->init_level++; 6335 6336 /* And permanently map it in */ 6337 aic_dmamap_load(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap, 6338 ahd->shared_data_map.vaddr, driver_data_size, 6339 ahd_dmamap_cb, &ahd->shared_data_map.busaddr, 6340 /*flags*/0); 6341 ahd->qoutfifo = (struct ahd_completion *)ahd->shared_data_map.vaddr; 6342 next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE]; 6343 next_baddr = ahd->shared_data_map.busaddr 6344 + AHD_QOUT_SIZE*sizeof(struct ahd_completion); 6345 if ((ahd->features & AHD_TARGETMODE) != 0) { 6346 ahd->targetcmds = (struct target_cmd *)next_vaddr; 6347 next_vaddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); 6348 next_baddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); 6349 } 6350 6351 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) { 6352 ahd->overrun_buf = next_vaddr; 6353 next_vaddr += PKT_OVERRUN_BUFSIZE; 6354 next_baddr += PKT_OVERRUN_BUFSIZE; 6355 } 6356 6357 /* 6358 * We need one SCB to serve as the "next SCB". Since the 6359 * tag identifier in this SCB will never be used, there is 6360 * no point in using a valid HSCB tag from an SCB pulled from 6361 * the standard free pool. So, we allocate this "sentinel" 6362 * specially from the DMA safe memory chunk used for the QOUTFIFO. 6363 */ 6364 ahd->next_queued_hscb = (struct hardware_scb *)next_vaddr; 6365 ahd->next_queued_hscb_map = &ahd->shared_data_map; 6366 ahd->next_queued_hscb->hscb_busaddr = aic_htole32(next_baddr); 6367 6368 ahd->init_level++; 6369 6370 /* Allocate SCB data now that buffer_dmat is initialized */ 6371 if (ahd_init_scbdata(ahd) != 0) 6372 return (ENOMEM); 6373 6374 if ((ahd->flags & AHD_INITIATORROLE) == 0) 6375 ahd->flags &= ~AHD_RESET_BUS_A; 6376 6377 /* 6378 * Before committing these settings to the chip, give 6379 * the OSM one last chance to modify our configuration. 6380 */ 6381 ahd_platform_init(ahd); 6382 6383 /* Bring up the chip. */ 6384 ahd_chip_init(ahd); 6385 6386 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 6387 6388 if ((ahd->flags & AHD_CURRENT_SENSING) == 0) 6389 goto init_done; 6390 6391 /* 6392 * Verify termination based on current draw and 6393 * warn user if the bus is over/under terminated. 6394 */ 6395 error = ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 6396 CURSENSE_ENB); 6397 if (error != 0) { 6398 printf("%s: current sensing timeout 1\n", ahd_name(ahd)); 6399 goto init_done; 6400 } 6401 for (i = 20, fstat = FLX_FSTAT_BUSY; 6402 (fstat & FLX_FSTAT_BUSY) != 0 && i; i--) { 6403 error = ahd_read_flexport(ahd, FLXADDR_FLEXSTAT, &fstat); 6404 if (error != 0) { 6405 printf("%s: current sensing timeout 2\n", 6406 ahd_name(ahd)); 6407 goto init_done; 6408 } 6409 } 6410 if (i == 0) { 6411 printf("%s: Timedout during current-sensing test\n", 6412 ahd_name(ahd)); 6413 goto init_done; 6414 } 6415 6416 /* Latch Current Sensing status. */ 6417 error = ahd_read_flexport(ahd, FLXADDR_CURRENT_STAT, ¤t_sensing); 6418 if (error != 0) { 6419 printf("%s: current sensing timeout 3\n", ahd_name(ahd)); 6420 goto init_done; 6421 } 6422 6423 /* Diable current sensing. */ 6424 ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 6425 6426 #ifdef AHD_DEBUG 6427 if ((ahd_debug & AHD_SHOW_TERMCTL) != 0) { 6428 printf("%s: current_sensing == 0x%x\n", 6429 ahd_name(ahd), current_sensing); 6430 } 6431 #endif 6432 warn_user = 0; 6433 for (i = 0; i < 4; i++, current_sensing >>= FLX_CSTAT_SHIFT) { 6434 u_int term_stat; 6435 6436 term_stat = (current_sensing & FLX_CSTAT_MASK); 6437 switch (term_stat) { 6438 case FLX_CSTAT_OVER: 6439 case FLX_CSTAT_UNDER: 6440 warn_user++; 6441 case FLX_CSTAT_INVALID: 6442 case FLX_CSTAT_OKAY: 6443 if (warn_user == 0 && bootverbose == 0) 6444 break; 6445 printf("%s: %s Channel %s\n", ahd_name(ahd), 6446 channel_strings[i], termstat_strings[term_stat]); 6447 break; 6448 } 6449 } 6450 if (warn_user) { 6451 printf("%s: WARNING. Termination is not configured correctly.\n" 6452 "%s: WARNING. SCSI bus operations may FAIL.\n", 6453 ahd_name(ahd), ahd_name(ahd)); 6454 } 6455 init_done: 6456 ahd_restart(ahd); 6457 aic_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US, 6458 ahd_stat_timer, ahd); 6459 return (0); 6460 } 6461 6462 /* 6463 * (Re)initialize chip state after a chip reset. 6464 */ 6465 static void 6466 ahd_chip_init(struct ahd_softc *ahd) 6467 { 6468 uint32_t busaddr; 6469 u_int sxfrctl1; 6470 u_int scsiseq_template; 6471 u_int wait; 6472 u_int i; 6473 u_int target; 6474 6475 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6476 /* 6477 * Take the LED out of diagnostic mode 6478 */ 6479 ahd_outb(ahd, SBLKCTL, ahd_inb(ahd, SBLKCTL) & ~(DIAGLEDEN|DIAGLEDON)); 6480 6481 /* 6482 * Return HS_MAILBOX to its default value. 6483 */ 6484 ahd->hs_mailbox = 0; 6485 ahd_outb(ahd, HS_MAILBOX, 0); 6486 6487 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */ 6488 ahd_outb(ahd, IOWNID, ahd->our_id); 6489 ahd_outb(ahd, TOWNID, ahd->our_id); 6490 sxfrctl1 = (ahd->flags & AHD_TERM_ENB_A) != 0 ? STPWEN : 0; 6491 sxfrctl1 |= (ahd->flags & AHD_SPCHK_ENB_A) != 0 ? ENSPCHK : 0; 6492 if ((ahd->bugs & AHD_LONG_SETIMO_BUG) 6493 && (ahd->seltime != STIMESEL_MIN)) { 6494 /* 6495 * The selection timer duration is twice as long 6496 * as it should be. Halve it by adding "1" to 6497 * the user specified setting. 6498 */ 6499 sxfrctl1 |= ahd->seltime + STIMESEL_BUG_ADJ; 6500 } else { 6501 sxfrctl1 |= ahd->seltime; 6502 } 6503 6504 ahd_outb(ahd, SXFRCTL0, DFON); 6505 ahd_outb(ahd, SXFRCTL1, sxfrctl1|ahd->seltime|ENSTIMER|ACTNEGEN); 6506 ahd_outb(ahd, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 6507 6508 /* 6509 * Now that termination is set, wait for up 6510 * to 500ms for our transceivers to settle. If 6511 * the adapter does not have a cable attached, 6512 * the transceivers may never settle, so don't 6513 * complain if we fail here. 6514 */ 6515 for (wait = 10000; 6516 (ahd_inb(ahd, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 6517 wait--) 6518 aic_delay(100); 6519 6520 /* Clear any false bus resets due to the transceivers settling */ 6521 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); 6522 ahd_outb(ahd, CLRINT, CLRSCSIINT); 6523 6524 /* Initialize mode specific S/G state. */ 6525 for (i = 0; i < 2; i++) { 6526 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); 6527 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 6528 ahd_outb(ahd, SG_STATE, 0); 6529 ahd_outb(ahd, CLRSEQINTSRC, 0xFF); 6530 ahd_outb(ahd, SEQIMODE, 6531 ENSAVEPTRS|ENCFG4DATA|ENCFG4ISTAT 6532 |ENCFG4TSTAT|ENCFG4ICMD|ENCFG4TCMD); 6533 } 6534 6535 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 6536 ahd_outb(ahd, DSCOMMAND0, ahd_inb(ahd, DSCOMMAND0)|MPARCKEN|CACHETHEN); 6537 ahd_outb(ahd, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 6538 ahd_outb(ahd, SIMODE0, ENIOERR|ENOVERRUN); 6539 ahd_outb(ahd, SIMODE3, ENNTRAMPERR|ENOSRAMPERR); 6540 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) { 6541 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|AUTO_MSGOUT_DE); 6542 } else { 6543 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|BUSFREEREV|AUTO_MSGOUT_DE); 6544 } 6545 ahd_outb(ahd, SCSCHKN, CURRFIFODEF|WIDERESEN|SHVALIDSTDIS); 6546 if ((ahd->chip & AHD_BUS_MASK) == AHD_PCIX) 6547 /* 6548 * Do not issue a target abort when a split completion 6549 * error occurs. Let our PCIX interrupt handler deal 6550 * with it instead. H2A4 Razor #625 6551 */ 6552 ahd_outb(ahd, PCIXCTL, ahd_inb(ahd, PCIXCTL) | SPLTSTADIS); 6553 6554 if ((ahd->bugs & AHD_LQOOVERRUN_BUG) != 0) 6555 ahd_outb(ahd, LQOSCSCTL, LQONOCHKOVER); 6556 6557 /* 6558 * Tweak IOCELL settings. 6559 */ 6560 if ((ahd->flags & AHD_HP_BOARD) != 0) { 6561 for (i = 0; i < NUMDSPS; i++) { 6562 ahd_outb(ahd, DSPSELECT, i); 6563 ahd_outb(ahd, WRTBIASCTL, WRTBIASCTL_HP_DEFAULT); 6564 } 6565 #ifdef AHD_DEBUG 6566 if ((ahd_debug & AHD_SHOW_MISC) != 0) 6567 printf("%s: WRTBIASCTL now 0x%x\n", ahd_name(ahd), 6568 WRTBIASCTL_HP_DEFAULT); 6569 #endif 6570 } 6571 ahd_setup_iocell_workaround(ahd); 6572 6573 /* 6574 * Enable LQI Manager interrupts. 6575 */ 6576 ahd_outb(ahd, LQIMODE1, ENLQIPHASE_LQ|ENLQIPHASE_NLQ|ENLIQABORT 6577 | ENLQICRCI_LQ|ENLQICRCI_NLQ|ENLQIBADLQI 6578 | ENLQIOVERI_LQ|ENLQIOVERI_NLQ); 6579 ahd_outb(ahd, LQOMODE0, ENLQOATNLQ|ENLQOATNPKT|ENLQOTCRC); 6580 /* 6581 * An interrupt from LQOBUSFREE is made redundant by the 6582 * BUSFREE interrupt. We choose to have the sequencer catch 6583 * LQOPHCHGINPKT errors manually for the command phase at the 6584 * start of a packetized selection case. 6585 ahd_outb(ahd, LQOMODE1, ENLQOBUSFREE|ENLQOPHACHGINPKT); 6586 */ 6587 ahd_outb(ahd, LQOMODE1, 0); 6588 6589 /* 6590 * Setup sequencer interrupt handlers. 6591 */ 6592 ahd_outw(ahd, INTVEC1_ADDR, ahd_resolve_seqaddr(ahd, LABEL_seq_isr)); 6593 ahd_outw(ahd, INTVEC2_ADDR, ahd_resolve_seqaddr(ahd, LABEL_timer_isr)); 6594 6595 /* 6596 * Setup SCB Offset registers. 6597 */ 6598 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { 6599 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, 6600 pkt_long_lun)); 6601 } else { 6602 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, lun)); 6603 } 6604 ahd_outb(ahd, CMDLENPTR, offsetof(struct hardware_scb, cdb_len)); 6605 ahd_outb(ahd, ATTRPTR, offsetof(struct hardware_scb, task_attribute)); 6606 ahd_outb(ahd, FLAGPTR, offsetof(struct hardware_scb, task_management)); 6607 ahd_outb(ahd, CMDPTR, offsetof(struct hardware_scb, 6608 shared_data.idata.cdb)); 6609 ahd_outb(ahd, QNEXTPTR, 6610 offsetof(struct hardware_scb, next_hscb_busaddr)); 6611 ahd_outb(ahd, ABRTBITPTR, MK_MESSAGE_BIT_OFFSET); 6612 ahd_outb(ahd, ABRTBYTEPTR, offsetof(struct hardware_scb, control)); 6613 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { 6614 ahd_outb(ahd, LUNLEN, 6615 sizeof(ahd->next_queued_hscb->pkt_long_lun) - 1); 6616 } else { 6617 ahd_outb(ahd, LUNLEN, LUNLEN_SINGLE_LEVEL_LUN); 6618 } 6619 ahd_outb(ahd, CDBLIMIT, SCB_CDB_LEN_PTR - 1); 6620 ahd_outb(ahd, MAXCMD, 0xFF); 6621 ahd_outb(ahd, SCBAUTOPTR, 6622 AUSCBPTR_EN | offsetof(struct hardware_scb, tag)); 6623 6624 /* We haven't been enabled for target mode yet. */ 6625 ahd_outb(ahd, MULTARGID, 0); 6626 ahd_outb(ahd, MULTARGID + 1, 0); 6627 6628 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6629 /* Initialize the negotiation table. */ 6630 if ((ahd->features & AHD_NEW_IOCELL_OPTS) == 0) { 6631 /* 6632 * Clear the spare bytes in the neg table to avoid 6633 * spurious parity errors. 6634 */ 6635 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6636 ahd_outb(ahd, NEGOADDR, target); 6637 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PER_DEV0); 6638 for (i = 0; i < AHD_NUM_PER_DEV_ANNEXCOLS; i++) 6639 ahd_outb(ahd, ANNEXDAT, 0); 6640 } 6641 } 6642 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6643 struct ahd_devinfo devinfo; 6644 struct ahd_initiator_tinfo *tinfo; 6645 struct ahd_tmode_tstate *tstate; 6646 6647 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6648 target, &tstate); 6649 ahd_compile_devinfo(&devinfo, ahd->our_id, 6650 target, CAM_LUN_WILDCARD, 6651 'A', ROLE_INITIATOR); 6652 ahd_update_neg_table(ahd, &devinfo, &tinfo->curr); 6653 } 6654 6655 ahd_outb(ahd, CLRSINT3, NTRAMPERR|OSRAMPERR); 6656 ahd_outb(ahd, CLRINT, CLRSCSIINT); 6657 6658 #if NEEDS_MORE_TESTING 6659 /* 6660 * Always enable abort on incoming L_Qs if this feature is 6661 * supported. We use this to catch invalid SCB references. 6662 */ 6663 if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0) 6664 ahd_outb(ahd, LQCTL1, ABORTPENDING); 6665 else 6666 #endif 6667 ahd_outb(ahd, LQCTL1, 0); 6668 6669 /* All of our queues are empty */ 6670 ahd->qoutfifonext = 0; 6671 ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID; 6672 ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID); 6673 for (i = 0; i < AHD_QOUT_SIZE; i++) 6674 ahd->qoutfifo[i].valid_tag = 0; 6675 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD); 6676 6677 ahd->qinfifonext = 0; 6678 for (i = 0; i < AHD_QIN_SIZE; i++) 6679 ahd->qinfifo[i] = SCB_LIST_NULL; 6680 6681 if ((ahd->features & AHD_TARGETMODE) != 0) { 6682 /* All target command blocks start out invalid. */ 6683 for (i = 0; i < AHD_TMODE_CMDS; i++) 6684 ahd->targetcmds[i].cmd_valid = 0; 6685 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_PREREAD); 6686 ahd->tqinfifonext = 1; 6687 ahd_outb(ahd, KERNEL_TQINPOS, ahd->tqinfifonext - 1); 6688 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); 6689 } 6690 6691 /* Initialize Scratch Ram. */ 6692 ahd_outb(ahd, SEQ_FLAGS, 0); 6693 ahd_outb(ahd, SEQ_FLAGS2, 0); 6694 6695 /* We don't have any waiting selections */ 6696 ahd_outw(ahd, WAITING_TID_HEAD, SCB_LIST_NULL); 6697 ahd_outw(ahd, WAITING_TID_TAIL, SCB_LIST_NULL); 6698 for (i = 0; i < AHD_NUM_TARGETS; i++) 6699 ahd_outw(ahd, WAITING_SCB_TAILS + (2 * i), SCB_LIST_NULL); 6700 6701 /* 6702 * Nobody is waiting to be DMAed into the QOUTFIFO. 6703 */ 6704 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); 6705 ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL); 6706 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); 6707 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL); 6708 ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL); 6709 6710 /* 6711 * The Freeze Count is 0. 6712 */ 6713 ahd->qfreeze_cnt = 0; 6714 ahd_outw(ahd, QFREEZE_COUNT, 0); 6715 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, 0); 6716 6717 /* 6718 * Tell the sequencer where it can find our arrays in memory. 6719 */ 6720 busaddr = ahd->shared_data_map.busaddr; 6721 ahd_outl(ahd, SHARED_DATA_ADDR, busaddr); 6722 ahd_outl(ahd, QOUTFIFO_NEXT_ADDR, busaddr); 6723 6724 /* 6725 * Setup the allowed SCSI Sequences based on operational mode. 6726 * If we are a target, we'll enable select in operations once 6727 * we've had a lun enabled. 6728 */ 6729 scsiseq_template = ENAUTOATNP; 6730 if ((ahd->flags & AHD_INITIATORROLE) != 0) 6731 scsiseq_template |= ENRSELI; 6732 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq_template); 6733 6734 /* There are no busy SCBs yet. */ 6735 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6736 int lun; 6737 6738 for (lun = 0; lun < AHD_NUM_LUNS_NONPKT; lun++) 6739 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(target, 'A', lun)); 6740 } 6741 6742 /* 6743 * Initialize the group code to command length table. 6744 * Vendor Unique codes are set to 0 so we only capture 6745 * the first byte of the cdb. These can be overridden 6746 * when target mode is enabled. 6747 */ 6748 ahd_outb(ahd, CMDSIZE_TABLE, 5); 6749 ahd_outb(ahd, CMDSIZE_TABLE + 1, 9); 6750 ahd_outb(ahd, CMDSIZE_TABLE + 2, 9); 6751 ahd_outb(ahd, CMDSIZE_TABLE + 3, 0); 6752 ahd_outb(ahd, CMDSIZE_TABLE + 4, 15); 6753 ahd_outb(ahd, CMDSIZE_TABLE + 5, 11); 6754 ahd_outb(ahd, CMDSIZE_TABLE + 6, 0); 6755 ahd_outb(ahd, CMDSIZE_TABLE + 7, 0); 6756 6757 /* Tell the sequencer of our initial queue positions */ 6758 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6759 ahd_outb(ahd, QOFF_CTLSTA, SCB_QSIZE_512); 6760 ahd->qinfifonext = 0; 6761 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 6762 ahd_set_hescb_qoff(ahd, 0); 6763 ahd_set_snscb_qoff(ahd, 0); 6764 ahd_set_sescb_qoff(ahd, 0); 6765 ahd_set_sdscb_qoff(ahd, 0); 6766 6767 /* 6768 * Tell the sequencer which SCB will be the next one it receives. 6769 */ 6770 busaddr = aic_le32toh(ahd->next_queued_hscb->hscb_busaddr); 6771 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr); 6772 6773 /* 6774 * Default to coalescing disabled. 6775 */ 6776 ahd_outw(ahd, INT_COALESCING_CMDCOUNT, 0); 6777 ahd_outw(ahd, CMDS_PENDING, 0); 6778 ahd_update_coalescing_values(ahd, ahd->int_coalescing_timer, 6779 ahd->int_coalescing_maxcmds, 6780 ahd->int_coalescing_mincmds); 6781 ahd_enable_coalescing(ahd, FALSE); 6782 6783 ahd_loadseq(ahd); 6784 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6785 } 6786 6787 /* 6788 * Setup default device and controller settings. 6789 * This should only be called if our probe has 6790 * determined that no configuration data is available. 6791 */ 6792 int 6793 ahd_default_config(struct ahd_softc *ahd) 6794 { 6795 int targ; 6796 6797 ahd->our_id = 7; 6798 6799 /* 6800 * Allocate a tstate to house information for our 6801 * initiator presence on the bus as well as the user 6802 * data for any target mode initiator. 6803 */ 6804 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { 6805 printf("%s: unable to allocate ahd_tmode_tstate. " 6806 "Failing attach\n", ahd_name(ahd)); 6807 return (ENOMEM); 6808 } 6809 6810 for (targ = 0; targ < AHD_NUM_TARGETS; targ++) { 6811 struct ahd_devinfo devinfo; 6812 struct ahd_initiator_tinfo *tinfo; 6813 struct ahd_tmode_tstate *tstate; 6814 uint16_t target_mask; 6815 6816 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6817 targ, &tstate); 6818 /* 6819 * We support SPC2 and SPI4. 6820 */ 6821 tinfo->user.protocol_version = 4; 6822 tinfo->user.transport_version = 4; 6823 6824 target_mask = 0x01 << targ; 6825 ahd->user_discenable |= target_mask; 6826 tstate->discenable |= target_mask; 6827 ahd->user_tagenable |= target_mask; 6828 #ifdef AHD_FORCE_160 6829 tinfo->user.period = AHD_SYNCRATE_DT; 6830 #else 6831 tinfo->user.period = AHD_SYNCRATE_160; 6832 #endif 6833 tinfo->user.offset = MAX_OFFSET; 6834 tinfo->user.ppr_options = MSG_EXT_PPR_RD_STRM 6835 | MSG_EXT_PPR_WR_FLOW 6836 | MSG_EXT_PPR_HOLD_MCS 6837 | MSG_EXT_PPR_IU_REQ 6838 | MSG_EXT_PPR_QAS_REQ 6839 | MSG_EXT_PPR_DT_REQ; 6840 if ((ahd->features & AHD_RTI) != 0) 6841 tinfo->user.ppr_options |= MSG_EXT_PPR_RTI; 6842 6843 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 6844 6845 /* 6846 * Start out Async/Narrow/Untagged and with 6847 * conservative protocol support. 6848 */ 6849 tinfo->goal.protocol_version = 2; 6850 tinfo->goal.transport_version = 2; 6851 tinfo->curr.protocol_version = 2; 6852 tinfo->curr.transport_version = 2; 6853 ahd_compile_devinfo(&devinfo, ahd->our_id, 6854 targ, CAM_LUN_WILDCARD, 6855 'A', ROLE_INITIATOR); 6856 tstate->tagenable &= ~target_mask; 6857 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6858 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); 6859 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, 6860 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, 6861 /*paused*/TRUE); 6862 } 6863 return (0); 6864 } 6865 6866 /* 6867 * Parse device configuration information. 6868 */ 6869 int 6870 ahd_parse_cfgdata(struct ahd_softc *ahd, struct seeprom_config *sc) 6871 { 6872 int targ; 6873 int max_targ; 6874 6875 max_targ = sc->max_targets & CFMAXTARG; 6876 ahd->our_id = sc->brtime_id & CFSCSIID; 6877 6878 /* 6879 * Allocate a tstate to house information for our 6880 * initiator presence on the bus as well as the user 6881 * data for any target mode initiator. 6882 */ 6883 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { 6884 printf("%s: unable to allocate ahd_tmode_tstate. " 6885 "Failing attach\n", ahd_name(ahd)); 6886 return (ENOMEM); 6887 } 6888 6889 for (targ = 0; targ < max_targ; targ++) { 6890 struct ahd_devinfo devinfo; 6891 struct ahd_initiator_tinfo *tinfo; 6892 struct ahd_transinfo *user_tinfo; 6893 struct ahd_tmode_tstate *tstate; 6894 uint16_t target_mask; 6895 6896 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6897 targ, &tstate); 6898 user_tinfo = &tinfo->user; 6899 6900 /* 6901 * We support SPC2 and SPI4. 6902 */ 6903 tinfo->user.protocol_version = 4; 6904 tinfo->user.transport_version = 4; 6905 6906 target_mask = 0x01 << targ; 6907 ahd->user_discenable &= ~target_mask; 6908 tstate->discenable &= ~target_mask; 6909 ahd->user_tagenable &= ~target_mask; 6910 if (sc->device_flags[targ] & CFDISC) { 6911 tstate->discenable |= target_mask; 6912 ahd->user_discenable |= target_mask; 6913 ahd->user_tagenable |= target_mask; 6914 } else { 6915 /* 6916 * Cannot be packetized without disconnection. 6917 */ 6918 sc->device_flags[targ] &= ~CFPACKETIZED; 6919 } 6920 6921 user_tinfo->ppr_options = 0; 6922 user_tinfo->period = (sc->device_flags[targ] & CFXFER); 6923 if (user_tinfo->period < CFXFER_ASYNC) { 6924 if (user_tinfo->period <= AHD_PERIOD_10MHz) 6925 user_tinfo->ppr_options |= MSG_EXT_PPR_DT_REQ; 6926 user_tinfo->offset = MAX_OFFSET; 6927 } else { 6928 user_tinfo->offset = 0; 6929 user_tinfo->period = AHD_ASYNC_XFER_PERIOD; 6930 } 6931 #ifdef AHD_FORCE_160 6932 if (user_tinfo->period <= AHD_SYNCRATE_160) 6933 user_tinfo->period = AHD_SYNCRATE_DT; 6934 #endif 6935 6936 if ((sc->device_flags[targ] & CFPACKETIZED) != 0) { 6937 user_tinfo->ppr_options |= MSG_EXT_PPR_RD_STRM 6938 | MSG_EXT_PPR_WR_FLOW 6939 | MSG_EXT_PPR_HOLD_MCS 6940 | MSG_EXT_PPR_IU_REQ; 6941 if ((ahd->features & AHD_RTI) != 0) 6942 user_tinfo->ppr_options |= MSG_EXT_PPR_RTI; 6943 } 6944 6945 if ((sc->device_flags[targ] & CFQAS) != 0) 6946 user_tinfo->ppr_options |= MSG_EXT_PPR_QAS_REQ; 6947 6948 if ((sc->device_flags[targ] & CFWIDEB) != 0) 6949 user_tinfo->width = MSG_EXT_WDTR_BUS_16_BIT; 6950 else 6951 user_tinfo->width = MSG_EXT_WDTR_BUS_8_BIT; 6952 #ifdef AHD_DEBUG 6953 if ((ahd_debug & AHD_SHOW_MISC) != 0) 6954 printf("(%d): %x:%x:%x:%x\n", targ, user_tinfo->width, 6955 user_tinfo->period, user_tinfo->offset, 6956 user_tinfo->ppr_options); 6957 #endif 6958 /* 6959 * Start out Async/Narrow/Untagged and with 6960 * conservative protocol support. 6961 */ 6962 tstate->tagenable &= ~target_mask; 6963 tinfo->goal.protocol_version = 2; 6964 tinfo->goal.transport_version = 2; 6965 tinfo->curr.protocol_version = 2; 6966 tinfo->curr.transport_version = 2; 6967 ahd_compile_devinfo(&devinfo, ahd->our_id, 6968 targ, CAM_LUN_WILDCARD, 6969 'A', ROLE_INITIATOR); 6970 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6971 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); 6972 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, 6973 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, 6974 /*paused*/TRUE); 6975 } 6976 6977 ahd->flags &= ~AHD_SPCHK_ENB_A; 6978 if (sc->bios_control & CFSPARITY) 6979 ahd->flags |= AHD_SPCHK_ENB_A; 6980 6981 ahd->flags &= ~AHD_RESET_BUS_A; 6982 if (sc->bios_control & CFRESETB) 6983 ahd->flags |= AHD_RESET_BUS_A; 6984 6985 ahd->flags &= ~AHD_EXTENDED_TRANS_A; 6986 if (sc->bios_control & CFEXTEND) 6987 ahd->flags |= AHD_EXTENDED_TRANS_A; 6988 6989 ahd->flags &= ~AHD_BIOS_ENABLED; 6990 if ((sc->bios_control & CFBIOSSTATE) == CFBS_ENABLED) 6991 ahd->flags |= AHD_BIOS_ENABLED; 6992 6993 ahd->flags &= ~AHD_STPWLEVEL_A; 6994 if ((sc->adapter_control & CFSTPWLEVEL) != 0) 6995 ahd->flags |= AHD_STPWLEVEL_A; 6996 6997 return (0); 6998 } 6999 7000 /* 7001 * Parse device configuration information. 7002 */ 7003 int 7004 ahd_parse_vpddata(struct ahd_softc *ahd, struct vpd_config *vpd) 7005 { 7006 int error; 7007 7008 error = ahd_verify_vpd_cksum(vpd); 7009 if (error == 0) 7010 return (EINVAL); 7011 if ((vpd->bios_flags & VPDBOOTHOST) != 0) 7012 ahd->flags |= AHD_BOOT_CHANNEL; 7013 return (0); 7014 } 7015 7016 void 7017 ahd_intr_enable(struct ahd_softc *ahd, int enable) 7018 { 7019 u_int hcntrl; 7020 7021 hcntrl = ahd_inb(ahd, HCNTRL); 7022 hcntrl &= ~INTEN; 7023 ahd->pause &= ~INTEN; 7024 ahd->unpause &= ~INTEN; 7025 if (enable) { 7026 hcntrl |= INTEN; 7027 ahd->pause |= INTEN; 7028 ahd->unpause |= INTEN; 7029 } 7030 ahd_outb(ahd, HCNTRL, hcntrl); 7031 } 7032 7033 void 7034 ahd_update_coalescing_values(struct ahd_softc *ahd, u_int timer, u_int maxcmds, 7035 u_int mincmds) 7036 { 7037 if (timer > AHD_TIMER_MAX_US) 7038 timer = AHD_TIMER_MAX_US; 7039 ahd->int_coalescing_timer = timer; 7040 7041 if (maxcmds > AHD_INT_COALESCING_MAXCMDS_MAX) 7042 maxcmds = AHD_INT_COALESCING_MAXCMDS_MAX; 7043 if (mincmds > AHD_INT_COALESCING_MINCMDS_MAX) 7044 mincmds = AHD_INT_COALESCING_MINCMDS_MAX; 7045 ahd->int_coalescing_maxcmds = maxcmds; 7046 ahd_outw(ahd, INT_COALESCING_TIMER, timer / AHD_TIMER_US_PER_TICK); 7047 ahd_outb(ahd, INT_COALESCING_MAXCMDS, -maxcmds); 7048 ahd_outb(ahd, INT_COALESCING_MINCMDS, -mincmds); 7049 } 7050 7051 void 7052 ahd_enable_coalescing(struct ahd_softc *ahd, int enable) 7053 { 7054 7055 ahd->hs_mailbox &= ~ENINT_COALESCE; 7056 if (enable) 7057 ahd->hs_mailbox |= ENINT_COALESCE; 7058 ahd_outb(ahd, HS_MAILBOX, ahd->hs_mailbox); 7059 ahd_flush_device_writes(ahd); 7060 ahd_run_qoutfifo(ahd); 7061 } 7062 7063 /* 7064 * Ensure that the card is paused in a location 7065 * outside of all critical sections and that all 7066 * pending work is completed prior to returning. 7067 * This routine should only be called from outside 7068 * an interrupt context. 7069 */ 7070 void 7071 ahd_pause_and_flushwork(struct ahd_softc *ahd) 7072 { 7073 u_int intstat; 7074 u_int maxloops; 7075 7076 maxloops = 1000; 7077 ahd->flags |= AHD_ALL_INTERRUPTS; 7078 ahd_pause(ahd); 7079 /* 7080 * Freeze the outgoing selections. We do this only 7081 * until we are safely paused without further selections 7082 * pending. 7083 */ 7084 ahd->qfreeze_cnt--; 7085 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt); 7086 ahd_outb(ahd, SEQ_FLAGS2, ahd_inb(ahd, SEQ_FLAGS2) | SELECTOUT_QFROZEN); 7087 do { 7088 7089 ahd_unpause(ahd); 7090 /* 7091 * Give the sequencer some time to service 7092 * any active selections. 7093 */ 7094 aic_delay(500); 7095 7096 ahd_intr(ahd); 7097 ahd_pause(ahd); 7098 intstat = ahd_inb(ahd, INTSTAT); 7099 if ((intstat & INT_PEND) == 0) { 7100 ahd_clear_critical_section(ahd); 7101 intstat = ahd_inb(ahd, INTSTAT); 7102 } 7103 } while (--maxloops 7104 && (intstat != 0xFF || (ahd->features & AHD_REMOVABLE) == 0) 7105 && ((intstat & INT_PEND) != 0 7106 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0 7107 || (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0)); 7108 7109 if (maxloops == 0) { 7110 printf("Infinite interrupt loop, INTSTAT = %x", 7111 ahd_inb(ahd, INTSTAT)); 7112 } 7113 ahd->qfreeze_cnt++; 7114 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt); 7115 7116 ahd_flush_qoutfifo(ahd); 7117 7118 ahd_platform_flushwork(ahd); 7119 ahd->flags &= ~AHD_ALL_INTERRUPTS; 7120 } 7121 7122 int 7123 ahd_suspend(struct ahd_softc *ahd) 7124 { 7125 7126 ahd_pause_and_flushwork(ahd); 7127 7128 if (LIST_FIRST(&ahd->pending_scbs) != NULL) { 7129 ahd_unpause(ahd); 7130 return (EBUSY); 7131 } 7132 ahd_shutdown(ahd); 7133 return (0); 7134 } 7135 7136 int 7137 ahd_resume(struct ahd_softc *ahd) 7138 { 7139 7140 ahd_reset(ahd, /*reinit*/TRUE); 7141 ahd_intr_enable(ahd, TRUE); 7142 ahd_restart(ahd); 7143 return (0); 7144 } 7145 7146 /************************** Busy Target Table *********************************/ 7147 /* 7148 * Set SCBPTR to the SCB that contains the busy 7149 * table entry for TCL. Return the offset into 7150 * the SCB that contains the entry for TCL. 7151 * saved_scbid is dereferenced and set to the 7152 * scbid that should be restored once manipualtion 7153 * of the TCL entry is complete. 7154 */ 7155 static __inline u_int 7156 ahd_index_busy_tcl(struct ahd_softc *ahd, u_int *saved_scbid, u_int tcl) 7157 { 7158 /* 7159 * Index to the SCB that contains the busy entry. 7160 */ 7161 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7162 *saved_scbid = ahd_get_scbptr(ahd); 7163 ahd_set_scbptr(ahd, TCL_LUN(tcl) 7164 | ((TCL_TARGET_OFFSET(tcl) & 0xC) << 4)); 7165 7166 /* 7167 * And now calculate the SCB offset to the entry. 7168 * Each entry is 2 bytes wide, hence the 7169 * multiplication by 2. 7170 */ 7171 return (((TCL_TARGET_OFFSET(tcl) & 0x3) << 1) + SCB_DISCONNECTED_LISTS); 7172 } 7173 7174 /* 7175 * Return the untagged transaction id for a given target/channel lun. 7176 */ 7177 u_int 7178 ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl) 7179 { 7180 u_int scbid; 7181 u_int scb_offset; 7182 u_int saved_scbptr; 7183 7184 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); 7185 scbid = ahd_inw_scbram(ahd, scb_offset); 7186 ahd_set_scbptr(ahd, saved_scbptr); 7187 return (scbid); 7188 } 7189 7190 void 7191 ahd_busy_tcl(struct ahd_softc *ahd, u_int tcl, u_int scbid) 7192 { 7193 u_int scb_offset; 7194 u_int saved_scbptr; 7195 7196 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); 7197 ahd_outw(ahd, scb_offset, scbid); 7198 ahd_set_scbptr(ahd, saved_scbptr); 7199 } 7200 7201 /************************** SCB and SCB queue management **********************/ 7202 int 7203 ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, int target, 7204 char channel, int lun, u_int tag, role_t role) 7205 { 7206 int targ = SCB_GET_TARGET(ahd, scb); 7207 char chan = SCB_GET_CHANNEL(ahd, scb); 7208 int slun = SCB_GET_LUN(scb); 7209 int match; 7210 7211 match = ((chan == channel) || (channel == ALL_CHANNELS)); 7212 if (match != 0) 7213 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 7214 if (match != 0) 7215 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 7216 if (match != 0) { 7217 #if AHD_TARGET_MODE 7218 int group; 7219 7220 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 7221 if (role == ROLE_INITIATOR) { 7222 match = (group != XPT_FC_GROUP_TMODE) 7223 && ((tag == SCB_GET_TAG(scb)) 7224 || (tag == SCB_LIST_NULL)); 7225 } else if (role == ROLE_TARGET) { 7226 match = (group == XPT_FC_GROUP_TMODE) 7227 && ((tag == scb->io_ctx->csio.tag_id) 7228 || (tag == SCB_LIST_NULL)); 7229 } 7230 #else /* !AHD_TARGET_MODE */ 7231 match = ((tag == SCB_GET_TAG(scb)) || (tag == SCB_LIST_NULL)); 7232 #endif /* AHD_TARGET_MODE */ 7233 } 7234 7235 return match; 7236 } 7237 7238 void 7239 ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb) 7240 { 7241 int target; 7242 char channel; 7243 int lun; 7244 7245 target = SCB_GET_TARGET(ahd, scb); 7246 lun = SCB_GET_LUN(scb); 7247 channel = SCB_GET_CHANNEL(ahd, scb); 7248 7249 ahd_search_qinfifo(ahd, target, channel, lun, 7250 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 7251 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 7252 7253 ahd_platform_freeze_devq(ahd, scb); 7254 } 7255 7256 void 7257 ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, struct scb *scb) 7258 { 7259 struct scb *prev_scb; 7260 ahd_mode_state saved_modes; 7261 7262 saved_modes = ahd_save_modes(ahd); 7263 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 7264 prev_scb = NULL; 7265 if (ahd_qinfifo_count(ahd) != 0) { 7266 u_int prev_tag; 7267 u_int prev_pos; 7268 7269 prev_pos = AHD_QIN_WRAP(ahd->qinfifonext - 1); 7270 prev_tag = ahd->qinfifo[prev_pos]; 7271 prev_scb = ahd_lookup_scb(ahd, prev_tag); 7272 } 7273 ahd_qinfifo_requeue(ahd, prev_scb, scb); 7274 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 7275 ahd_restore_modes(ahd, saved_modes); 7276 } 7277 7278 static void 7279 ahd_qinfifo_requeue(struct ahd_softc *ahd, struct scb *prev_scb, 7280 struct scb *scb) 7281 { 7282 if (prev_scb == NULL) { 7283 uint32_t busaddr; 7284 7285 busaddr = aic_le32toh(scb->hscb->hscb_busaddr); 7286 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr); 7287 } else { 7288 prev_scb->hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr; 7289 ahd_sync_scb(ahd, prev_scb, 7290 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 7291 } 7292 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb); 7293 ahd->qinfifonext++; 7294 scb->hscb->next_hscb_busaddr = ahd->next_queued_hscb->hscb_busaddr; 7295 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 7296 } 7297 7298 static int 7299 ahd_qinfifo_count(struct ahd_softc *ahd) 7300 { 7301 u_int qinpos; 7302 u_int wrap_qinpos; 7303 u_int wrap_qinfifonext; 7304 7305 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7306 qinpos = ahd_get_snscb_qoff(ahd); 7307 wrap_qinpos = AHD_QIN_WRAP(qinpos); 7308 wrap_qinfifonext = AHD_QIN_WRAP(ahd->qinfifonext); 7309 if (wrap_qinfifonext >= wrap_qinpos) 7310 return (wrap_qinfifonext - wrap_qinpos); 7311 else 7312 return (wrap_qinfifonext 7313 + NUM_ELEMENTS(ahd->qinfifo) - wrap_qinpos); 7314 } 7315 7316 void 7317 ahd_reset_cmds_pending(struct ahd_softc *ahd) 7318 { 7319 struct scb *scb; 7320 ahd_mode_state saved_modes; 7321 u_int pending_cmds; 7322 7323 saved_modes = ahd_save_modes(ahd); 7324 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 7325 7326 /* 7327 * Don't count any commands as outstanding that the 7328 * sequencer has already marked for completion. 7329 */ 7330 ahd_flush_qoutfifo(ahd); 7331 7332 pending_cmds = 0; 7333 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 7334 pending_cmds++; 7335 } 7336 ahd_outw(ahd, CMDS_PENDING, pending_cmds - ahd_qinfifo_count(ahd)); 7337 ahd_restore_modes(ahd, saved_modes); 7338 ahd->flags &= ~AHD_UPDATE_PEND_CMDS; 7339 } 7340 7341 int 7342 ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel, 7343 int lun, u_int tag, role_t role, uint32_t status, 7344 ahd_search_action action) 7345 { 7346 struct scb *scb; 7347 struct scb *prev_scb; 7348 ahd_mode_state saved_modes; 7349 u_int qinstart; 7350 u_int qinpos; 7351 u_int qintail; 7352 u_int tid_next; 7353 u_int tid_prev; 7354 u_int scbid; 7355 u_int savedscbptr; 7356 uint32_t busaddr; 7357 int found; 7358 int targets; 7359 7360 /* Must be in CCHAN mode */ 7361 saved_modes = ahd_save_modes(ahd); 7362 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 7363 7364 /* 7365 * Halt any pending SCB DMA. The sequencer will reinitiate 7366 * this dma if the qinfifo is not empty once we unpause. 7367 */ 7368 if ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN|CCSCBDIR)) 7369 == (CCARREN|CCSCBEN|CCSCBDIR)) { 7370 ahd_outb(ahd, CCSCBCTL, 7371 ahd_inb(ahd, CCSCBCTL) & ~(CCARREN|CCSCBEN)); 7372 while ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0) 7373 ; 7374 } 7375 /* Determine sequencer's position in the qinfifo. */ 7376 qintail = AHD_QIN_WRAP(ahd->qinfifonext); 7377 qinstart = ahd_get_snscb_qoff(ahd); 7378 qinpos = AHD_QIN_WRAP(qinstart); 7379 found = 0; 7380 prev_scb = NULL; 7381 7382 if (action == SEARCH_PRINT) { 7383 printf("qinstart = %d qinfifonext = %d\nQINFIFO:", 7384 qinstart, ahd->qinfifonext); 7385 } 7386 7387 /* 7388 * Start with an empty queue. Entries that are not chosen 7389 * for removal will be re-added to the queue as we go. 7390 */ 7391 ahd->qinfifonext = qinstart; 7392 busaddr = aic_le32toh(ahd->next_queued_hscb->hscb_busaddr); 7393 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr); 7394 7395 while (qinpos != qintail) { 7396 scb = ahd_lookup_scb(ahd, ahd->qinfifo[qinpos]); 7397 if (scb == NULL) { 7398 printf("qinpos = %d, SCB index = %d\n", 7399 qinpos, ahd->qinfifo[qinpos]); 7400 panic("Loop 1\n"); 7401 } 7402 7403 if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) { 7404 /* 7405 * We found an scb that needs to be acted on. 7406 */ 7407 found++; 7408 switch (action) { 7409 case SEARCH_COMPLETE: 7410 { 7411 cam_status ostat; 7412 cam_status cstat; 7413 7414 ostat = aic_get_transaction_status(scb); 7415 if (ostat == CAM_REQ_INPROG) 7416 aic_set_transaction_status(scb, 7417 status); 7418 cstat = aic_get_transaction_status(scb); 7419 if (cstat != CAM_REQ_CMP) 7420 aic_freeze_scb(scb); 7421 if ((scb->flags & SCB_ACTIVE) == 0) 7422 printf("Inactive SCB in qinfifo\n"); 7423 ahd_done(ahd, scb); 7424 7425 /* FALLTHROUGH */ 7426 } 7427 case SEARCH_REMOVE: 7428 break; 7429 case SEARCH_PRINT: 7430 printf(" 0x%x", ahd->qinfifo[qinpos]); 7431 /* FALLTHROUGH */ 7432 case SEARCH_COUNT: 7433 ahd_qinfifo_requeue(ahd, prev_scb, scb); 7434 prev_scb = scb; 7435 break; 7436 } 7437 } else { 7438 ahd_qinfifo_requeue(ahd, prev_scb, scb); 7439 prev_scb = scb; 7440 } 7441 qinpos = AHD_QIN_WRAP(qinpos+1); 7442 } 7443 7444 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 7445 7446 if (action == SEARCH_PRINT) 7447 printf("\nWAITING_TID_QUEUES:\n"); 7448 7449 /* 7450 * Search waiting for selection lists. We traverse the 7451 * list of "their ids" waiting for selection and, if 7452 * appropriate, traverse the SCBs of each "their id" 7453 * looking for matches. 7454 */ 7455 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7456 savedscbptr = ahd_get_scbptr(ahd); 7457 tid_next = ahd_inw(ahd, WAITING_TID_HEAD); 7458 tid_prev = SCB_LIST_NULL; 7459 targets = 0; 7460 for (scbid = tid_next; !SCBID_IS_NULL(scbid); scbid = tid_next) { 7461 u_int tid_head; 7462 7463 /* 7464 * We limit based on the number of SCBs since 7465 * MK_MESSAGE SCBs are not in the per-tid lists. 7466 */ 7467 targets++; 7468 if (targets > AHD_SCB_MAX) { 7469 panic("TID LIST LOOP"); 7470 } 7471 if (scbid >= ahd->scb_data.numscbs) { 7472 printf("%s: Waiting TID List inconsistency. " 7473 "SCB index == 0x%x, yet numscbs == 0x%x.", 7474 ahd_name(ahd), scbid, ahd->scb_data.numscbs); 7475 ahd_dump_card_state(ahd); 7476 panic("for safety"); 7477 } 7478 scb = ahd_lookup_scb(ahd, scbid); 7479 if (scb == NULL) { 7480 printf("%s: SCB = 0x%x Not Active!\n", 7481 ahd_name(ahd), scbid); 7482 panic("Waiting TID List traversal\n"); 7483 } 7484 ahd_set_scbptr(ahd, scbid); 7485 tid_next = ahd_inw_scbram(ahd, SCB_NEXT2); 7486 if (ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD, 7487 SCB_LIST_NULL, ROLE_UNKNOWN) == 0) { 7488 tid_prev = scbid; 7489 continue; 7490 } 7491 7492 /* 7493 * We found a list of scbs that needs to be searched. 7494 */ 7495 if (action == SEARCH_PRINT) 7496 printf(" %d ( ", SCB_GET_TARGET(ahd, scb)); 7497 tid_head = scbid; 7498 found += ahd_search_scb_list(ahd, target, channel, 7499 lun, tag, role, status, 7500 action, &tid_head, 7501 SCB_GET_TARGET(ahd, scb)); 7502 if (tid_head != scbid) 7503 ahd_stitch_tid_list(ahd, tid_prev, tid_head, tid_next); 7504 if (!SCBID_IS_NULL(tid_head)) 7505 tid_prev = tid_head; 7506 if (action == SEARCH_PRINT) 7507 printf(")\n"); 7508 } 7509 ahd_set_scbptr(ahd, savedscbptr); 7510 ahd_restore_modes(ahd, saved_modes); 7511 return (found); 7512 } 7513 7514 static int 7515 ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel, 7516 int lun, u_int tag, role_t role, uint32_t status, 7517 ahd_search_action action, u_int *list_head, u_int tid) 7518 { 7519 struct scb *scb; 7520 u_int scbid; 7521 u_int next; 7522 u_int prev; 7523 int found; 7524 7525 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7526 found = 0; 7527 prev = SCB_LIST_NULL; 7528 next = *list_head; 7529 for (scbid = next; !SCBID_IS_NULL(scbid); scbid = next) { 7530 if (scbid >= ahd->scb_data.numscbs) { 7531 printf("%s:SCB List inconsistency. " 7532 "SCB == 0x%x, yet numscbs == 0x%x.", 7533 ahd_name(ahd), scbid, ahd->scb_data.numscbs); 7534 ahd_dump_card_state(ahd); 7535 panic("for safety"); 7536 } 7537 scb = ahd_lookup_scb(ahd, scbid); 7538 if (scb == NULL) { 7539 printf("%s: SCB = %d Not Active!\n", 7540 ahd_name(ahd), scbid); 7541 panic("Waiting List traversal\n"); 7542 } 7543 ahd_set_scbptr(ahd, scbid); 7544 next = ahd_inw_scbram(ahd, SCB_NEXT); 7545 if (ahd_match_scb(ahd, scb, target, channel, 7546 lun, SCB_LIST_NULL, role) == 0) { 7547 prev = scbid; 7548 continue; 7549 } 7550 found++; 7551 switch (action) { 7552 case SEARCH_COMPLETE: 7553 { 7554 cam_status ostat; 7555 cam_status cstat; 7556 7557 ostat = aic_get_transaction_status(scb); 7558 if (ostat == CAM_REQ_INPROG) 7559 aic_set_transaction_status(scb, status); 7560 cstat = aic_get_transaction_status(scb); 7561 if (cstat != CAM_REQ_CMP) 7562 aic_freeze_scb(scb); 7563 if ((scb->flags & SCB_ACTIVE) == 0) 7564 printf("Inactive SCB in Waiting List\n"); 7565 ahd_done(ahd, scb); 7566 /* FALLTHROUGH */ 7567 } 7568 case SEARCH_REMOVE: 7569 ahd_rem_wscb(ahd, scbid, prev, next, tid); 7570 if (prev == SCB_LIST_NULL) 7571 *list_head = next; 7572 break; 7573 case SEARCH_PRINT: 7574 printf("0x%x ", scbid); 7575 case SEARCH_COUNT: 7576 prev = scbid; 7577 break; 7578 } 7579 if (found > AHD_SCB_MAX) 7580 panic("SCB LIST LOOP"); 7581 } 7582 if (action == SEARCH_COMPLETE 7583 || action == SEARCH_REMOVE) 7584 ahd_outw(ahd, CMDS_PENDING, ahd_inw(ahd, CMDS_PENDING) - found); 7585 return (found); 7586 } 7587 7588 static void 7589 ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev, 7590 u_int tid_cur, u_int tid_next) 7591 { 7592 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7593 7594 if (SCBID_IS_NULL(tid_cur)) { 7595 7596 /* Bypass current TID list */ 7597 if (SCBID_IS_NULL(tid_prev)) { 7598 ahd_outw(ahd, WAITING_TID_HEAD, tid_next); 7599 } else { 7600 ahd_set_scbptr(ahd, tid_prev); 7601 ahd_outw(ahd, SCB_NEXT2, tid_next); 7602 } 7603 if (SCBID_IS_NULL(tid_next)) 7604 ahd_outw(ahd, WAITING_TID_TAIL, tid_prev); 7605 } else { 7606 7607 /* Stitch through tid_cur */ 7608 if (SCBID_IS_NULL(tid_prev)) { 7609 ahd_outw(ahd, WAITING_TID_HEAD, tid_cur); 7610 } else { 7611 ahd_set_scbptr(ahd, tid_prev); 7612 ahd_outw(ahd, SCB_NEXT2, tid_cur); 7613 } 7614 ahd_set_scbptr(ahd, tid_cur); 7615 ahd_outw(ahd, SCB_NEXT2, tid_next); 7616 7617 if (SCBID_IS_NULL(tid_next)) 7618 ahd_outw(ahd, WAITING_TID_TAIL, tid_cur); 7619 } 7620 } 7621 7622 /* 7623 * Manipulate the waiting for selection list and return the 7624 * scb that follows the one that we remove. 7625 */ 7626 static u_int 7627 ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, 7628 u_int prev, u_int next, u_int tid) 7629 { 7630 u_int tail_offset; 7631 7632 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7633 if (!SCBID_IS_NULL(prev)) { 7634 ahd_set_scbptr(ahd, prev); 7635 ahd_outw(ahd, SCB_NEXT, next); 7636 } 7637 7638 /* 7639 * SCBs that had MK_MESSAGE set in them will not 7640 * be queued to the per-target lists, so don't 7641 * blindly clear the tail pointer. 7642 */ 7643 tail_offset = WAITING_SCB_TAILS + (2 * tid); 7644 if (SCBID_IS_NULL(next) 7645 && ahd_inw(ahd, tail_offset) == scbid) 7646 ahd_outw(ahd, tail_offset, prev); 7647 ahd_add_scb_to_free_list(ahd, scbid); 7648 return (next); 7649 } 7650 7651 /* 7652 * Add the SCB as selected by SCBPTR onto the on chip list of 7653 * free hardware SCBs. This list is empty/unused if we are not 7654 * performing SCB paging. 7655 */ 7656 static void 7657 ahd_add_scb_to_free_list(struct ahd_softc *ahd, u_int scbid) 7658 { 7659 /* XXX Need some other mechanism to designate "free". */ 7660 /* 7661 * Invalidate the tag so that our abort 7662 * routines don't think it's active. 7663 ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL); 7664 */ 7665 } 7666 7667 /******************************** Error Handling ******************************/ 7668 /* 7669 * Abort all SCBs that match the given description (target/channel/lun/tag), 7670 * setting their status to the passed in status if the status has not already 7671 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 7672 * is paused before it is called. 7673 */ 7674 int 7675 ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel, 7676 int lun, u_int tag, role_t role, uint32_t status) 7677 { 7678 struct scb *scbp; 7679 struct scb *scbp_next; 7680 u_int i, j; 7681 u_int maxtarget; 7682 u_int minlun; 7683 u_int maxlun; 7684 int found; 7685 ahd_mode_state saved_modes; 7686 7687 /* restore this when we're done */ 7688 saved_modes = ahd_save_modes(ahd); 7689 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7690 7691 found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL, 7692 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 7693 7694 /* 7695 * Clean out the busy target table for any untagged commands. 7696 */ 7697 i = 0; 7698 maxtarget = 16; 7699 if (target != CAM_TARGET_WILDCARD) { 7700 i = target; 7701 if (channel == 'B') 7702 i += 8; 7703 maxtarget = i + 1; 7704 } 7705 7706 if (lun == CAM_LUN_WILDCARD) { 7707 minlun = 0; 7708 maxlun = AHD_NUM_LUNS_NONPKT; 7709 } else if (lun >= AHD_NUM_LUNS_NONPKT) { 7710 minlun = maxlun = 0; 7711 } else { 7712 minlun = lun; 7713 maxlun = lun + 1; 7714 } 7715 7716 if (role != ROLE_TARGET) { 7717 for (;i < maxtarget; i++) { 7718 for (j = minlun;j < maxlun; j++) { 7719 u_int scbid; 7720 u_int tcl; 7721 7722 tcl = BUILD_TCL_RAW(i, 'A', j); 7723 scbid = ahd_find_busy_tcl(ahd, tcl); 7724 scbp = ahd_lookup_scb(ahd, scbid); 7725 if (scbp == NULL 7726 || ahd_match_scb(ahd, scbp, target, channel, 7727 lun, tag, role) == 0) 7728 continue; 7729 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(i, 'A', j)); 7730 } 7731 } 7732 } 7733 7734 /* 7735 * Don't abort commands that have already completed, 7736 * but haven't quite made it up to the host yet. 7737 */ 7738 ahd_flush_qoutfifo(ahd); 7739 7740 /* 7741 * Go through the pending CCB list and look for 7742 * commands for this target that are still active. 7743 * These are other tagged commands that were 7744 * disconnected when the reset occurred. 7745 */ 7746 scbp_next = LIST_FIRST(&ahd->pending_scbs); 7747 while (scbp_next != NULL) { 7748 scbp = scbp_next; 7749 scbp_next = LIST_NEXT(scbp, pending_links); 7750 if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) { 7751 cam_status ostat; 7752 7753 ostat = aic_get_transaction_status(scbp); 7754 if (ostat == CAM_REQ_INPROG) 7755 aic_set_transaction_status(scbp, status); 7756 if (aic_get_transaction_status(scbp) != CAM_REQ_CMP) 7757 aic_freeze_scb(scbp); 7758 if ((scbp->flags & SCB_ACTIVE) == 0) 7759 printf("Inactive SCB on pending list\n"); 7760 ahd_done(ahd, scbp); 7761 found++; 7762 } 7763 } 7764 ahd_restore_modes(ahd, saved_modes); 7765 ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status); 7766 ahd->flags |= AHD_UPDATE_PEND_CMDS; 7767 return found; 7768 } 7769 7770 static void 7771 ahd_reset_current_bus(struct ahd_softc *ahd) 7772 { 7773 uint8_t scsiseq; 7774 7775 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7776 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENSCSIRST); 7777 scsiseq = ahd_inb(ahd, SCSISEQ0) & ~(ENSELO|ENARBO|SCSIRSTO); 7778 ahd_outb(ahd, SCSISEQ0, scsiseq | SCSIRSTO); 7779 ahd_flush_device_writes(ahd); 7780 aic_delay(AHD_BUSRESET_DELAY); 7781 /* Turn off the bus reset */ 7782 ahd_outb(ahd, SCSISEQ0, scsiseq); 7783 ahd_flush_device_writes(ahd); 7784 aic_delay(AHD_BUSRESET_DELAY); 7785 if ((ahd->bugs & AHD_SCSIRST_BUG) != 0) { 7786 /* 7787 * 2A Razor #474 7788 * Certain chip state is not cleared for 7789 * SCSI bus resets that we initiate, so 7790 * we must reset the chip. 7791 */ 7792 ahd_reset(ahd, /*reinit*/TRUE); 7793 ahd_intr_enable(ahd, /*enable*/TRUE); 7794 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7795 } 7796 7797 ahd_clear_intstat(ahd); 7798 } 7799 7800 int 7801 ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset) 7802 { 7803 struct ahd_devinfo devinfo; 7804 u_int initiator; 7805 u_int target; 7806 u_int max_scsiid; 7807 int found; 7808 u_int fifo; 7809 u_int next_fifo; 7810 7811 ahd->pending_device = NULL; 7812 7813 ahd_compile_devinfo(&devinfo, 7814 CAM_TARGET_WILDCARD, 7815 CAM_TARGET_WILDCARD, 7816 CAM_LUN_WILDCARD, 7817 channel, ROLE_UNKNOWN); 7818 ahd_pause(ahd); 7819 7820 /* Make sure the sequencer is in a safe location. */ 7821 ahd_clear_critical_section(ahd); 7822 7823 #if AHD_TARGET_MODE 7824 if ((ahd->flags & AHD_TARGETROLE) != 0) { 7825 ahd_run_tqinfifo(ahd, /*paused*/TRUE); 7826 } 7827 #endif 7828 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7829 7830 /* 7831 * Disable selections so no automatic hardware 7832 * functions will modify chip state. 7833 */ 7834 ahd_outb(ahd, SCSISEQ0, 0); 7835 ahd_outb(ahd, SCSISEQ1, 0); 7836 7837 /* 7838 * Safely shut down our DMA engines. Always start with 7839 * the FIFO that is not currently active (if any are 7840 * actively connected). 7841 */ 7842 next_fifo = fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; 7843 if (next_fifo > CURRFIFO_1) 7844 /* If disconneced, arbitrarily start with FIFO1. */ 7845 next_fifo = fifo = 0; 7846 do { 7847 next_fifo ^= CURRFIFO_1; 7848 ahd_set_modes(ahd, next_fifo, next_fifo); 7849 ahd_outb(ahd, DFCNTRL, 7850 ahd_inb(ahd, DFCNTRL) & ~(SCSIEN|HDMAEN)); 7851 while ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) 7852 aic_delay(10); 7853 /* 7854 * Set CURRFIFO to the now inactive channel. 7855 */ 7856 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7857 ahd_outb(ahd, DFFSTAT, next_fifo); 7858 } while (next_fifo != fifo); 7859 7860 /* 7861 * Reset the bus if we are initiating this reset 7862 */ 7863 ahd_clear_msg_state(ahd); 7864 ahd_outb(ahd, SIMODE1, 7865 ahd_inb(ahd, SIMODE1) & ~(ENBUSFREE|ENSCSIRST)); 7866 7867 if (initiate_reset) 7868 ahd_reset_current_bus(ahd); 7869 7870 ahd_clear_intstat(ahd); 7871 7872 /* 7873 * Clean up all the state information for the 7874 * pending transactions on this bus. 7875 */ 7876 found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel, 7877 CAM_LUN_WILDCARD, SCB_LIST_NULL, 7878 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 7879 7880 /* 7881 * Cleanup anything left in the FIFOs. 7882 */ 7883 ahd_clear_fifo(ahd, 0); 7884 ahd_clear_fifo(ahd, 1); 7885 7886 /* 7887 * Revert to async/narrow transfers until we renegotiate. 7888 */ 7889 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7; 7890 for (target = 0; target <= max_scsiid; target++) { 7891 7892 if (ahd->enabled_targets[target] == NULL) 7893 continue; 7894 for (initiator = 0; initiator <= max_scsiid; initiator++) { 7895 struct ahd_devinfo devinfo; 7896 7897 ahd_compile_devinfo(&devinfo, target, initiator, 7898 CAM_LUN_WILDCARD, 7899 'A', ROLE_UNKNOWN); 7900 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 7901 AHD_TRANS_CUR, /*paused*/TRUE); 7902 ahd_set_syncrate(ahd, &devinfo, /*period*/0, 7903 /*offset*/0, /*ppr_options*/0, 7904 AHD_TRANS_CUR, /*paused*/TRUE); 7905 } 7906 } 7907 7908 #ifdef AHD_TARGET_MODE 7909 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7; 7910 7911 /* 7912 * Send an immediate notify ccb to all target more peripheral 7913 * drivers affected by this action. 7914 */ 7915 for (target = 0; target <= max_scsiid; target++) { 7916 struct ahd_tmode_tstate* tstate; 7917 u_int lun; 7918 7919 tstate = ahd->enabled_targets[target]; 7920 if (tstate == NULL) 7921 continue; 7922 for (lun = 0; lun < AHD_NUM_LUNS; lun++) { 7923 struct ahd_tmode_lstate* lstate; 7924 7925 lstate = tstate->enabled_luns[lun]; 7926 if (lstate == NULL) 7927 continue; 7928 7929 ahd_queue_lstate_event(ahd, lstate, CAM_TARGET_WILDCARD, 7930 EVENT_TYPE_BUS_RESET, /*arg*/0); 7931 ahd_send_lstate_events(ahd, lstate); 7932 } 7933 } 7934 #endif 7935 /* Notify the XPT that a bus reset occurred */ 7936 ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD, 7937 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL); 7938 ahd_restart(ahd); 7939 /* 7940 * Freeze the SIMQ until our poller can determine that 7941 * the bus reset has really gone away. We set the initial 7942 * timer to 0 to have the check performed as soon as possible 7943 * from the timer context. 7944 */ 7945 if ((ahd->flags & AHD_RESET_POLL_ACTIVE) == 0) { 7946 ahd->flags |= AHD_RESET_POLL_ACTIVE; 7947 aic_freeze_simq(ahd); 7948 aic_timer_reset(&ahd->reset_timer, 0, ahd_reset_poll, ahd); 7949 } 7950 return (found); 7951 } 7952 7953 7954 #define AHD_RESET_POLL_US 1000 7955 static void 7956 ahd_reset_poll(void *arg) 7957 { 7958 struct ahd_softc *ahd; 7959 u_int scsiseq1; 7960 u_long l; 7961 u_long s; 7962 7963 ahd_list_lock(&l); 7964 ahd = ahd_find_softc((struct ahd_softc *)arg); 7965 if (ahd == NULL) { 7966 printf("ahd_reset_poll: Instance %p no longer exists\n", arg); 7967 ahd_list_unlock(&l); 7968 return; 7969 } 7970 ahd_lock(ahd, &s); 7971 ahd_pause(ahd); 7972 ahd_update_modes(ahd); 7973 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7974 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); 7975 if ((ahd_inb(ahd, SSTAT1) & SCSIRSTI) != 0) { 7976 aic_timer_reset(&ahd->reset_timer, AHD_RESET_POLL_US, 7977 ahd_reset_poll, ahd); 7978 ahd_unpause(ahd); 7979 ahd_unlock(ahd, &s); 7980 ahd_list_unlock(&l); 7981 return; 7982 } 7983 7984 /* Reset is now low. Complete chip reinitialization. */ 7985 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST); 7986 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 7987 ahd_outb(ahd, SCSISEQ1, scsiseq1 & (ENSELI|ENRSELI|ENAUTOATNP)); 7988 ahd_unpause(ahd); 7989 ahd->flags &= ~AHD_RESET_POLL_ACTIVE; 7990 ahd_unlock(ahd, &s); 7991 aic_release_simq(ahd); 7992 ahd_list_unlock(&l); 7993 } 7994 7995 /**************************** Statistics Processing ***************************/ 7996 static void 7997 ahd_stat_timer(void *arg) 7998 { 7999 struct ahd_softc *ahd; 8000 u_long l; 8001 u_long s; 8002 int enint_coal; 8003 8004 ahd_list_lock(&l); 8005 ahd = ahd_find_softc((struct ahd_softc *)arg); 8006 if (ahd == NULL) { 8007 printf("ahd_stat_timer: Instance %p no longer exists\n", arg); 8008 ahd_list_unlock(&l); 8009 return; 8010 } 8011 ahd_lock(ahd, &s); 8012 8013 enint_coal = ahd->hs_mailbox & ENINT_COALESCE; 8014 if (ahd->cmdcmplt_total > ahd->int_coalescing_threshold) 8015 enint_coal |= ENINT_COALESCE; 8016 else if (ahd->cmdcmplt_total < ahd->int_coalescing_stop_threshold) 8017 enint_coal &= ~ENINT_COALESCE; 8018 8019 if (enint_coal != (ahd->hs_mailbox & ENINT_COALESCE)) { 8020 ahd_enable_coalescing(ahd, enint_coal); 8021 #ifdef AHD_DEBUG 8022 if ((ahd_debug & AHD_SHOW_INT_COALESCING) != 0) 8023 printf("%s: Interrupt coalescing " 8024 "now %sabled. Cmds %d\n", 8025 ahd_name(ahd), 8026 (enint_coal & ENINT_COALESCE) ? "en" : "dis", 8027 ahd->cmdcmplt_total); 8028 #endif 8029 } 8030 8031 ahd->cmdcmplt_bucket = (ahd->cmdcmplt_bucket+1) & (AHD_STAT_BUCKETS-1); 8032 ahd->cmdcmplt_total -= ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket]; 8033 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket] = 0; 8034 aic_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US, 8035 ahd_stat_timer, ahd); 8036 ahd_unlock(ahd, &s); 8037 ahd_list_unlock(&l); 8038 } 8039 8040 /****************************** Status Processing *****************************/ 8041 void 8042 ahd_handle_scb_status(struct ahd_softc *ahd, struct scb *scb) 8043 { 8044 if (scb->hscb->shared_data.istatus.scsi_status != 0) { 8045 ahd_handle_scsi_status(ahd, scb); 8046 } else { 8047 ahd_calc_residual(ahd, scb); 8048 ahd_done(ahd, scb); 8049 } 8050 } 8051 8052 void 8053 ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb) 8054 { 8055 struct hardware_scb *hscb; 8056 int paused; 8057 8058 /* 8059 * The sequencer freezes its select-out queue 8060 * anytime a SCSI status error occurs. We must 8061 * handle the error and increment our qfreeze count 8062 * to allow the sequencer to continue. We don't 8063 * bother clearing critical sections here since all 8064 * operations are on data structures that the sequencer 8065 * is not touching once the queue is frozen. 8066 */ 8067 hscb = scb->hscb; 8068 8069 if (ahd_is_paused(ahd)) { 8070 paused = 1; 8071 } else { 8072 paused = 0; 8073 ahd_pause(ahd); 8074 } 8075 8076 /* Freeze the queue until the client sees the error. */ 8077 ahd_freeze_devq(ahd, scb); 8078 aic_freeze_scb(scb); 8079 ahd->qfreeze_cnt++; 8080 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt); 8081 8082 if (paused == 0) 8083 ahd_unpause(ahd); 8084 8085 /* Don't want to clobber the original sense code */ 8086 if ((scb->flags & SCB_SENSE) != 0) { 8087 /* 8088 * Clear the SCB_SENSE Flag and perform 8089 * a normal command completion. 8090 */ 8091 scb->flags &= ~SCB_SENSE; 8092 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 8093 ahd_done(ahd, scb); 8094 return; 8095 } 8096 aic_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR); 8097 aic_set_scsi_status(scb, hscb->shared_data.istatus.scsi_status); 8098 switch (hscb->shared_data.istatus.scsi_status) { 8099 case STATUS_PKT_SENSE: 8100 { 8101 struct scsi_status_iu_header *siu; 8102 8103 ahd_sync_sense(ahd, scb, BUS_DMASYNC_POSTREAD); 8104 siu = (struct scsi_status_iu_header *)scb->sense_data; 8105 aic_set_scsi_status(scb, siu->status); 8106 #ifdef AHD_DEBUG 8107 if ((ahd_debug & AHD_SHOW_SENSE) != 0) { 8108 ahd_print_path(ahd, scb); 8109 printf("SCB 0x%x Received PKT Status of 0x%x\n", 8110 SCB_GET_TAG(scb), siu->status); 8111 printf("\tflags = 0x%x, sense len = 0x%x, " 8112 "pktfail = 0x%x\n", 8113 siu->flags, scsi_4btoul(siu->sense_length), 8114 scsi_4btoul(siu->pkt_failures_length)); 8115 } 8116 #endif 8117 if ((siu->flags & SIU_RSPVALID) != 0) { 8118 ahd_print_path(ahd, scb); 8119 if (scsi_4btoul(siu->pkt_failures_length) < 4) { 8120 printf("Unable to parse pkt_failures\n"); 8121 } else { 8122 8123 switch (SIU_PKTFAIL_CODE(siu)) { 8124 case SIU_PFC_NONE: 8125 printf("No packet failure found\n"); 8126 break; 8127 case SIU_PFC_CIU_FIELDS_INVALID: 8128 printf("Invalid Command IU Field\n"); 8129 break; 8130 case SIU_PFC_TMF_NOT_SUPPORTED: 8131 printf("TMF not supportd\n"); 8132 break; 8133 case SIU_PFC_TMF_FAILED: 8134 printf("TMF failed\n"); 8135 break; 8136 case SIU_PFC_INVALID_TYPE_CODE: 8137 printf("Invalid L_Q Type code\n"); 8138 break; 8139 case SIU_PFC_ILLEGAL_REQUEST: 8140 printf("Illegal request\n"); 8141 default: 8142 break; 8143 } 8144 } 8145 if (siu->status == SCSI_STATUS_OK) 8146 aic_set_transaction_status(scb, 8147 CAM_REQ_CMP_ERR); 8148 } 8149 if ((siu->flags & SIU_SNSVALID) != 0) { 8150 scb->flags |= SCB_PKT_SENSE; 8151 #ifdef AHD_DEBUG 8152 if ((ahd_debug & AHD_SHOW_SENSE) != 0) 8153 printf("Sense data available\n"); 8154 #endif 8155 } 8156 ahd_done(ahd, scb); 8157 break; 8158 } 8159 case SCSI_STATUS_CMD_TERMINATED: 8160 case SCSI_STATUS_CHECK_COND: 8161 { 8162 struct ahd_devinfo devinfo; 8163 struct ahd_dma_seg *sg; 8164 struct scsi_sense *sc; 8165 struct ahd_initiator_tinfo *targ_info; 8166 struct ahd_tmode_tstate *tstate; 8167 struct ahd_transinfo *tinfo; 8168 #ifdef AHD_DEBUG 8169 if (ahd_debug & AHD_SHOW_SENSE) { 8170 ahd_print_path(ahd, scb); 8171 printf("SCB %d: requests Check Status\n", 8172 SCB_GET_TAG(scb)); 8173 } 8174 #endif 8175 8176 if (aic_perform_autosense(scb) == 0) 8177 break; 8178 8179 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), 8180 SCB_GET_TARGET(ahd, scb), 8181 SCB_GET_LUN(scb), 8182 SCB_GET_CHANNEL(ahd, scb), 8183 ROLE_INITIATOR); 8184 targ_info = ahd_fetch_transinfo(ahd, 8185 devinfo.channel, 8186 devinfo.our_scsiid, 8187 devinfo.target, 8188 &tstate); 8189 tinfo = &targ_info->curr; 8190 sg = scb->sg_list; 8191 sc = (struct scsi_sense *)hscb->shared_data.idata.cdb; 8192 /* 8193 * Save off the residual if there is one. 8194 */ 8195 ahd_update_residual(ahd, scb); 8196 #ifdef AHD_DEBUG 8197 if (ahd_debug & AHD_SHOW_SENSE) { 8198 ahd_print_path(ahd, scb); 8199 printf("Sending Sense\n"); 8200 } 8201 #endif 8202 scb->sg_count = 0; 8203 sg = ahd_sg_setup(ahd, scb, sg, ahd_get_sense_bufaddr(ahd, scb), 8204 aic_get_sense_bufsize(ahd, scb), 8205 /*last*/TRUE); 8206 sc->opcode = REQUEST_SENSE; 8207 sc->byte2 = 0; 8208 if (tinfo->protocol_version <= SCSI_REV_2 8209 && SCB_GET_LUN(scb) < 8) 8210 sc->byte2 = SCB_GET_LUN(scb) << 5; 8211 sc->unused[0] = 0; 8212 sc->unused[1] = 0; 8213 sc->length = aic_get_sense_bufsize(ahd, scb); 8214 sc->control = 0; 8215 8216 /* 8217 * We can't allow the target to disconnect. 8218 * This will be an untagged transaction and 8219 * having the target disconnect will make this 8220 * transaction indestinguishable from outstanding 8221 * tagged transactions. 8222 */ 8223 hscb->control = 0; 8224 8225 /* 8226 * This request sense could be because the 8227 * the device lost power or in some other 8228 * way has lost our transfer negotiations. 8229 * Renegotiate if appropriate. Unit attention 8230 * errors will be reported before any data 8231 * phases occur. 8232 */ 8233 if (aic_get_residual(scb) == aic_get_transfer_length(scb)) { 8234 ahd_update_neg_request(ahd, &devinfo, 8235 tstate, targ_info, 8236 AHD_NEG_IF_NON_ASYNC); 8237 } 8238 if (tstate->auto_negotiate & devinfo.target_mask) { 8239 hscb->control |= MK_MESSAGE; 8240 scb->flags &= 8241 ~(SCB_NEGOTIATE|SCB_ABORT|SCB_DEVICE_RESET); 8242 scb->flags |= SCB_AUTO_NEGOTIATE; 8243 } 8244 hscb->cdb_len = sizeof(*sc); 8245 ahd_setup_data_scb(ahd, scb); 8246 scb->flags |= SCB_SENSE; 8247 ahd_queue_scb(ahd, scb); 8248 /* 8249 * Ensure we have enough time to actually 8250 * retrieve the sense. 8251 */ 8252 aic_scb_timer_reset(scb, 5 * 1000000); 8253 break; 8254 } 8255 case SCSI_STATUS_OK: 8256 printf("%s: Interrupted for staus of 0???\n", 8257 ahd_name(ahd)); 8258 /* FALLTHROUGH */ 8259 default: 8260 ahd_done(ahd, scb); 8261 break; 8262 } 8263 } 8264 8265 /* 8266 * Calculate the residual for a just completed SCB. 8267 */ 8268 void 8269 ahd_calc_residual(struct ahd_softc *ahd, struct scb *scb) 8270 { 8271 struct hardware_scb *hscb; 8272 struct initiator_status *spkt; 8273 uint32_t sgptr; 8274 uint32_t resid_sgptr; 8275 uint32_t resid; 8276 8277 /* 8278 * 5 cases. 8279 * 1) No residual. 8280 * SG_STATUS_VALID clear in sgptr. 8281 * 2) Transferless command 8282 * 3) Never performed any transfers. 8283 * sgptr has SG_FULL_RESID set. 8284 * 4) No residual but target did not 8285 * save data pointers after the 8286 * last transfer, so sgptr was 8287 * never updated. 8288 * 5) We have a partial residual. 8289 * Use residual_sgptr to determine 8290 * where we are. 8291 */ 8292 8293 hscb = scb->hscb; 8294 sgptr = aic_le32toh(hscb->sgptr); 8295 if ((sgptr & SG_STATUS_VALID) == 0) 8296 /* Case 1 */ 8297 return; 8298 sgptr &= ~SG_STATUS_VALID; 8299 8300 if ((sgptr & SG_LIST_NULL) != 0) 8301 /* Case 2 */ 8302 return; 8303 8304 /* 8305 * Residual fields are the same in both 8306 * target and initiator status packets, 8307 * so we can always use the initiator fields 8308 * regardless of the role for this SCB. 8309 */ 8310 spkt = &hscb->shared_data.istatus; 8311 resid_sgptr = aic_le32toh(spkt->residual_sgptr); 8312 if ((sgptr & SG_FULL_RESID) != 0) { 8313 /* Case 3 */ 8314 resid = aic_get_transfer_length(scb); 8315 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 8316 /* Case 4 */ 8317 return; 8318 } else if ((resid_sgptr & SG_OVERRUN_RESID) != 0) { 8319 ahd_print_path(ahd, scb); 8320 printf("data overrun detected Tag == 0x%x.\n", 8321 SCB_GET_TAG(scb)); 8322 ahd_freeze_devq(ahd, scb); 8323 aic_set_transaction_status(scb, CAM_DATA_RUN_ERR); 8324 aic_freeze_scb(scb); 8325 return; 8326 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 8327 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 8328 /* NOTREACHED */ 8329 } else { 8330 struct ahd_dma_seg *sg; 8331 8332 /* 8333 * Remainder of the SG where the transfer 8334 * stopped. 8335 */ 8336 resid = aic_le32toh(spkt->residual_datacnt) & AHD_SG_LEN_MASK; 8337 sg = ahd_sg_bus_to_virt(ahd, scb, resid_sgptr & SG_PTR_MASK); 8338 8339 /* The residual sg_ptr always points to the next sg */ 8340 sg--; 8341 8342 /* 8343 * Add up the contents of all residual 8344 * SG segments that are after the SG where 8345 * the transfer stopped. 8346 */ 8347 while ((aic_le32toh(sg->len) & AHD_DMA_LAST_SEG) == 0) { 8348 sg++; 8349 resid += aic_le32toh(sg->len) & AHD_SG_LEN_MASK; 8350 } 8351 } 8352 if ((scb->flags & SCB_SENSE) == 0) 8353 aic_set_residual(scb, resid); 8354 else 8355 aic_set_sense_residual(scb, resid); 8356 8357 #ifdef AHD_DEBUG 8358 if ((ahd_debug & AHD_SHOW_MISC) != 0) { 8359 ahd_print_path(ahd, scb); 8360 printf("Handled %sResidual of %d bytes\n", 8361 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 8362 } 8363 #endif 8364 } 8365 8366 /******************************* Target Mode **********************************/ 8367 #ifdef AHD_TARGET_MODE 8368 /* 8369 * Add a target mode event to this lun's queue 8370 */ 8371 static void 8372 ahd_queue_lstate_event(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate, 8373 u_int initiator_id, u_int event_type, u_int event_arg) 8374 { 8375 struct ahd_tmode_event *event; 8376 int pending; 8377 8378 xpt_freeze_devq(lstate->path, /*count*/1); 8379 if (lstate->event_w_idx >= lstate->event_r_idx) 8380 pending = lstate->event_w_idx - lstate->event_r_idx; 8381 else 8382 pending = AHD_TMODE_EVENT_BUFFER_SIZE + 1 8383 - (lstate->event_r_idx - lstate->event_w_idx); 8384 8385 if (event_type == EVENT_TYPE_BUS_RESET 8386 || event_type == MSG_BUS_DEV_RESET) { 8387 /* 8388 * Any earlier events are irrelevant, so reset our buffer. 8389 * This has the effect of allowing us to deal with reset 8390 * floods (an external device holding down the reset line) 8391 * without losing the event that is really interesting. 8392 */ 8393 lstate->event_r_idx = 0; 8394 lstate->event_w_idx = 0; 8395 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 8396 } 8397 8398 if (pending == AHD_TMODE_EVENT_BUFFER_SIZE) { 8399 xpt_print_path(lstate->path); 8400 printf("immediate event %x:%x lost\n", 8401 lstate->event_buffer[lstate->event_r_idx].event_type, 8402 lstate->event_buffer[lstate->event_r_idx].event_arg); 8403 lstate->event_r_idx++; 8404 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 8405 lstate->event_r_idx = 0; 8406 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 8407 } 8408 8409 event = &lstate->event_buffer[lstate->event_w_idx]; 8410 event->initiator_id = initiator_id; 8411 event->event_type = event_type; 8412 event->event_arg = event_arg; 8413 lstate->event_w_idx++; 8414 if (lstate->event_w_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 8415 lstate->event_w_idx = 0; 8416 } 8417 8418 /* 8419 * Send any target mode events queued up waiting 8420 * for immediate notify resources. 8421 */ 8422 void 8423 ahd_send_lstate_events(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate) 8424 { 8425 struct ccb_hdr *ccbh; 8426 struct ccb_immed_notify *inot; 8427 8428 while (lstate->event_r_idx != lstate->event_w_idx 8429 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 8430 struct ahd_tmode_event *event; 8431 8432 event = &lstate->event_buffer[lstate->event_r_idx]; 8433 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 8434 inot = (struct ccb_immed_notify *)ccbh; 8435 switch (event->event_type) { 8436 case EVENT_TYPE_BUS_RESET: 8437 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 8438 break; 8439 default: 8440 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 8441 inot->message_args[0] = event->event_type; 8442 inot->message_args[1] = event->event_arg; 8443 break; 8444 } 8445 inot->initiator_id = event->initiator_id; 8446 inot->sense_len = 0; 8447 xpt_done((union ccb *)inot); 8448 lstate->event_r_idx++; 8449 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 8450 lstate->event_r_idx = 0; 8451 } 8452 } 8453 #endif 8454 8455 /******************** Sequencer Program Patching/Download *********************/ 8456 8457 #ifdef AHD_DUMP_SEQ 8458 void 8459 ahd_dumpseq(struct ahd_softc* ahd) 8460 { 8461 int i; 8462 int max_prog; 8463 8464 max_prog = 2048; 8465 8466 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 8467 ahd_outw(ahd, PRGMCNT, 0); 8468 for (i = 0; i < max_prog; i++) { 8469 uint8_t ins_bytes[4]; 8470 8471 ahd_insb(ahd, SEQRAM, ins_bytes, 4); 8472 printf("0x%08x\n", ins_bytes[0] << 24 8473 | ins_bytes[1] << 16 8474 | ins_bytes[2] << 8 8475 | ins_bytes[3]); 8476 } 8477 } 8478 #endif 8479 8480 static void 8481 ahd_loadseq(struct ahd_softc *ahd) 8482 { 8483 struct cs cs_table[num_critical_sections]; 8484 u_int begin_set[num_critical_sections]; 8485 u_int end_set[num_critical_sections]; 8486 struct patch *cur_patch; 8487 u_int cs_count; 8488 u_int cur_cs; 8489 u_int i; 8490 int downloaded; 8491 u_int skip_addr; 8492 u_int sg_prefetch_cnt; 8493 u_int sg_prefetch_cnt_limit; 8494 u_int sg_prefetch_align; 8495 u_int sg_size; 8496 u_int cacheline_mask; 8497 uint8_t download_consts[DOWNLOAD_CONST_COUNT]; 8498 8499 if (bootverbose) 8500 printf("%s: Downloading Sequencer Program...", 8501 ahd_name(ahd)); 8502 8503 #if DOWNLOAD_CONST_COUNT != 8 8504 #error "Download Const Mismatch" 8505 #endif 8506 /* 8507 * Start out with 0 critical sections 8508 * that apply to this firmware load. 8509 */ 8510 cs_count = 0; 8511 cur_cs = 0; 8512 memset(begin_set, 0, sizeof(begin_set)); 8513 memset(end_set, 0, sizeof(end_set)); 8514 8515 /* 8516 * Setup downloadable constant table. 8517 * 8518 * The computation for the S/G prefetch variables is 8519 * a bit complicated. We would like to always fetch 8520 * in terms of cachelined sized increments. However, 8521 * if the cacheline is not an even multiple of the 8522 * SG element size or is larger than our SG RAM, using 8523 * just the cache size might leave us with only a portion 8524 * of an SG element at the tail of a prefetch. If the 8525 * cacheline is larger than our S/G prefetch buffer less 8526 * the size of an SG element, we may round down to a cacheline 8527 * that doesn't contain any or all of the S/G of interest 8528 * within the bounds of our S/G ram. Provide variables to 8529 * the sequencer that will allow it to handle these edge 8530 * cases. 8531 */ 8532 /* Start by aligning to the nearest cacheline. */ 8533 sg_prefetch_align = ahd->pci_cachesize; 8534 if (sg_prefetch_align == 0) 8535 sg_prefetch_align = 8; 8536 /* Round down to the nearest power of 2. */ 8537 while (powerof2(sg_prefetch_align) == 0) 8538 sg_prefetch_align--; 8539 8540 cacheline_mask = sg_prefetch_align - 1; 8541 8542 /* 8543 * If the cacheline boundary is greater than half our prefetch RAM 8544 * we risk not being able to fetch even a single complete S/G 8545 * segment if we align to that boundary. 8546 */ 8547 if (sg_prefetch_align > CCSGADDR_MAX/2) 8548 sg_prefetch_align = CCSGADDR_MAX/2; 8549 /* Start by fetching a single cacheline. */ 8550 sg_prefetch_cnt = sg_prefetch_align; 8551 /* 8552 * Increment the prefetch count by cachelines until 8553 * at least one S/G element will fit. 8554 */ 8555 sg_size = sizeof(struct ahd_dma_seg); 8556 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 8557 sg_size = sizeof(struct ahd_dma64_seg); 8558 while (sg_prefetch_cnt < sg_size) 8559 sg_prefetch_cnt += sg_prefetch_align; 8560 /* 8561 * If the cacheline is not an even multiple of 8562 * the S/G size, we may only get a partial S/G when 8563 * we align. Add a cacheline if this is the case. 8564 */ 8565 if ((sg_prefetch_align % sg_size) != 0 8566 && (sg_prefetch_cnt < CCSGADDR_MAX)) 8567 sg_prefetch_cnt += sg_prefetch_align; 8568 /* 8569 * Lastly, compute a value that the sequencer can use 8570 * to determine if the remainder of the CCSGRAM buffer 8571 * has a full S/G element in it. 8572 */ 8573 sg_prefetch_cnt_limit = -(sg_prefetch_cnt - sg_size + 1); 8574 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 8575 download_consts[SG_PREFETCH_CNT_LIMIT] = sg_prefetch_cnt_limit; 8576 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_align - 1); 8577 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_align - 1); 8578 download_consts[SG_SIZEOF] = sg_size; 8579 download_consts[PKT_OVERRUN_BUFOFFSET] = 8580 (ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256; 8581 download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_1BYTE_LUN; 8582 download_consts[CACHELINE_MASK] = cacheline_mask; 8583 cur_patch = patches; 8584 downloaded = 0; 8585 skip_addr = 0; 8586 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 8587 ahd_outw(ahd, PRGMCNT, 0); 8588 8589 for (i = 0; i < sizeof(seqprog)/4; i++) { 8590 if (ahd_check_patch(ahd, &cur_patch, i, &skip_addr) == 0) { 8591 /* 8592 * Don't download this instruction as it 8593 * is in a patch that was removed. 8594 */ 8595 continue; 8596 } 8597 /* 8598 * Move through the CS table until we find a CS 8599 * that might apply to this instruction. 8600 */ 8601 for (; cur_cs < num_critical_sections; cur_cs++) { 8602 if (critical_sections[cur_cs].end <= i) { 8603 if (begin_set[cs_count] == TRUE 8604 && end_set[cs_count] == FALSE) { 8605 cs_table[cs_count].end = downloaded; 8606 end_set[cs_count] = TRUE; 8607 cs_count++; 8608 } 8609 continue; 8610 } 8611 if (critical_sections[cur_cs].begin <= i 8612 && begin_set[cs_count] == FALSE) { 8613 cs_table[cs_count].begin = downloaded; 8614 begin_set[cs_count] = TRUE; 8615 } 8616 break; 8617 } 8618 ahd_download_instr(ahd, i, download_consts); 8619 downloaded++; 8620 } 8621 8622 ahd->num_critical_sections = cs_count; 8623 if (cs_count != 0) { 8624 8625 cs_count *= sizeof(struct cs); 8626 ahd->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 8627 if (ahd->critical_sections == NULL) 8628 panic("ahd_loadseq: Could not malloc"); 8629 memcpy(ahd->critical_sections, cs_table, cs_count); 8630 } 8631 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE); 8632 8633 if (bootverbose) { 8634 printf(" %d instructions downloaded\n", downloaded); 8635 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 8636 ahd_name(ahd), ahd->features, ahd->bugs, ahd->flags); 8637 } 8638 } 8639 8640 static int 8641 ahd_check_patch(struct ahd_softc *ahd, struct patch **start_patch, 8642 u_int start_instr, u_int *skip_addr) 8643 { 8644 struct patch *cur_patch; 8645 struct patch *last_patch; 8646 u_int num_patches; 8647 8648 num_patches = sizeof(patches)/sizeof(struct patch); 8649 last_patch = &patches[num_patches]; 8650 cur_patch = *start_patch; 8651 8652 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 8653 8654 if (cur_patch->patch_func(ahd) == 0) { 8655 8656 /* Start rejecting code */ 8657 *skip_addr = start_instr + cur_patch->skip_instr; 8658 cur_patch += cur_patch->skip_patch; 8659 } else { 8660 /* Accepted this patch. Advance to the next 8661 * one and wait for our intruction pointer to 8662 * hit this point. 8663 */ 8664 cur_patch++; 8665 } 8666 } 8667 8668 *start_patch = cur_patch; 8669 if (start_instr < *skip_addr) 8670 /* Still skipping */ 8671 return (0); 8672 8673 return (1); 8674 } 8675 8676 static u_int 8677 ahd_resolve_seqaddr(struct ahd_softc *ahd, u_int address) 8678 { 8679 struct patch *cur_patch; 8680 int address_offset; 8681 u_int skip_addr; 8682 u_int i; 8683 8684 address_offset = 0; 8685 cur_patch = patches; 8686 skip_addr = 0; 8687 8688 for (i = 0; i < address;) { 8689 8690 ahd_check_patch(ahd, &cur_patch, i, &skip_addr); 8691 8692 if (skip_addr > i) { 8693 int end_addr; 8694 8695 end_addr = MIN(address, skip_addr); 8696 address_offset += end_addr - i; 8697 i = skip_addr; 8698 } else { 8699 i++; 8700 } 8701 } 8702 return (address - address_offset); 8703 } 8704 8705 static void 8706 ahd_download_instr(struct ahd_softc *ahd, u_int instrptr, uint8_t *dconsts) 8707 { 8708 union ins_formats instr; 8709 struct ins_format1 *fmt1_ins; 8710 struct ins_format3 *fmt3_ins; 8711 u_int opcode; 8712 8713 /* 8714 * The firmware is always compiled into a little endian format. 8715 */ 8716 instr.integer = aic_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 8717 8718 fmt1_ins = &instr.format1; 8719 fmt3_ins = NULL; 8720 8721 /* Pull the opcode */ 8722 opcode = instr.format1.opcode; 8723 switch (opcode) { 8724 case AIC_OP_JMP: 8725 case AIC_OP_JC: 8726 case AIC_OP_JNC: 8727 case AIC_OP_CALL: 8728 case AIC_OP_JNE: 8729 case AIC_OP_JNZ: 8730 case AIC_OP_JE: 8731 case AIC_OP_JZ: 8732 { 8733 fmt3_ins = &instr.format3; 8734 fmt3_ins->address = ahd_resolve_seqaddr(ahd, fmt3_ins->address); 8735 /* FALLTHROUGH */ 8736 } 8737 case AIC_OP_OR: 8738 case AIC_OP_AND: 8739 case AIC_OP_XOR: 8740 case AIC_OP_ADD: 8741 case AIC_OP_ADC: 8742 case AIC_OP_BMOV: 8743 if (fmt1_ins->parity != 0) { 8744 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 8745 } 8746 fmt1_ins->parity = 0; 8747 /* FALLTHROUGH */ 8748 case AIC_OP_ROL: 8749 { 8750 int i, count; 8751 8752 /* Calculate odd parity for the instruction */ 8753 for (i = 0, count = 0; i < 31; i++) { 8754 uint32_t mask; 8755 8756 mask = 0x01 << i; 8757 if ((instr.integer & mask) != 0) 8758 count++; 8759 } 8760 if ((count & 0x01) == 0) 8761 instr.format1.parity = 1; 8762 8763 /* The sequencer is a little endian cpu */ 8764 instr.integer = aic_htole32(instr.integer); 8765 ahd_outsb(ahd, SEQRAM, instr.bytes, 4); 8766 break; 8767 } 8768 default: 8769 panic("Unknown opcode encountered in seq program"); 8770 break; 8771 } 8772 } 8773 8774 static int 8775 ahd_probe_stack_size(struct ahd_softc *ahd) 8776 { 8777 int last_probe; 8778 8779 last_probe = 0; 8780 while (1) { 8781 int i; 8782 8783 /* 8784 * We avoid using 0 as a pattern to avoid 8785 * confusion if the stack implementation 8786 * "back-fills" with zeros when "poping' 8787 * entries. 8788 */ 8789 for (i = 1; i <= last_probe+1; i++) { 8790 ahd_outb(ahd, STACK, i & 0xFF); 8791 ahd_outb(ahd, STACK, (i >> 8) & 0xFF); 8792 } 8793 8794 /* Verify */ 8795 for (i = last_probe+1; i > 0; i--) { 8796 u_int stack_entry; 8797 8798 stack_entry = ahd_inb(ahd, STACK) 8799 |(ahd_inb(ahd, STACK) << 8); 8800 if (stack_entry != i) 8801 goto sized; 8802 } 8803 last_probe++; 8804 } 8805 sized: 8806 return (last_probe); 8807 } 8808 8809 void 8810 ahd_dump_all_cards_state(void) 8811 { 8812 struct ahd_softc *list_ahd; 8813 8814 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) { 8815 ahd_dump_card_state(list_ahd); 8816 } 8817 } 8818 8819 int 8820 ahd_print_register(ahd_reg_parse_entry_t *table, u_int num_entries, 8821 const char *name, u_int address, u_int value, 8822 u_int *cur_column, u_int wrap_point) 8823 { 8824 int printed; 8825 u_int printed_mask; 8826 8827 if (cur_column != NULL && *cur_column >= wrap_point) { 8828 printf("\n"); 8829 *cur_column = 0; 8830 } 8831 printed = printf("%s[0x%x]", name, value); 8832 if (table == NULL) { 8833 printed += printf(" "); 8834 *cur_column += printed; 8835 return (printed); 8836 } 8837 printed_mask = 0; 8838 while (printed_mask != 0xFF) { 8839 int entry; 8840 8841 for (entry = 0; entry < num_entries; entry++) { 8842 if (((value & table[entry].mask) 8843 != table[entry].value) 8844 || ((printed_mask & table[entry].mask) 8845 == table[entry].mask)) 8846 continue; 8847 8848 printed += printf("%s%s", 8849 printed_mask == 0 ? ":(" : "|", 8850 table[entry].name); 8851 printed_mask |= table[entry].mask; 8852 8853 break; 8854 } 8855 if (entry >= num_entries) 8856 break; 8857 } 8858 if (printed_mask != 0) 8859 printed += printf(") "); 8860 else 8861 printed += printf(" "); 8862 if (cur_column != NULL) 8863 *cur_column += printed; 8864 return (printed); 8865 } 8866 8867 void 8868 ahd_dump_card_state(struct ahd_softc *ahd) 8869 { 8870 struct scb *scb; 8871 ahd_mode_state saved_modes; 8872 u_int dffstat; 8873 int paused; 8874 u_int scb_index; 8875 u_int saved_scb_index; 8876 u_int cur_col; 8877 int i; 8878 8879 if (ahd_is_paused(ahd)) { 8880 paused = 1; 8881 } else { 8882 paused = 0; 8883 ahd_pause(ahd); 8884 } 8885 saved_modes = ahd_save_modes(ahd); 8886 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 8887 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 8888 "%s: Dumping Card State at program address 0x%x Mode 0x%x\n", 8889 ahd_name(ahd), 8890 ahd_inw(ahd, CURADDR), 8891 ahd_build_mode_state(ahd, ahd->saved_src_mode, 8892 ahd->saved_dst_mode)); 8893 if (paused) 8894 printf("Card was paused\n"); 8895 8896 if (ahd_check_cmdcmpltqueues(ahd)) 8897 printf("Completions are pending\n"); 8898 8899 /* 8900 * Mode independent registers. 8901 */ 8902 cur_col = 0; 8903 ahd_hs_mailbox_print(ahd_inb(ahd, LOCAL_HS_MAILBOX), &cur_col, 50); 8904 ahd_intctl_print(ahd_inb(ahd, INTCTL), &cur_col, 50); 8905 ahd_seqintstat_print(ahd_inb(ahd, SEQINTSTAT), &cur_col, 50); 8906 ahd_saved_mode_print(ahd_inb(ahd, SAVED_MODE), &cur_col, 50); 8907 ahd_dffstat_print(ahd_inb(ahd, DFFSTAT), &cur_col, 50); 8908 ahd_scsisigi_print(ahd_inb(ahd, SCSISIGI), &cur_col, 50); 8909 ahd_scsiphase_print(ahd_inb(ahd, SCSIPHASE), &cur_col, 50); 8910 ahd_scsibus_print(ahd_inb(ahd, SCSIBUS), &cur_col, 50); 8911 ahd_lastphase_print(ahd_inb(ahd, LASTPHASE), &cur_col, 50); 8912 ahd_scsiseq0_print(ahd_inb(ahd, SCSISEQ0), &cur_col, 50); 8913 ahd_scsiseq1_print(ahd_inb(ahd, SCSISEQ1), &cur_col, 50); 8914 ahd_seqctl0_print(ahd_inb(ahd, SEQCTL0), &cur_col, 50); 8915 ahd_seqintctl_print(ahd_inb(ahd, SEQINTCTL), &cur_col, 50); 8916 ahd_seq_flags_print(ahd_inb(ahd, SEQ_FLAGS), &cur_col, 50); 8917 ahd_seq_flags2_print(ahd_inb(ahd, SEQ_FLAGS2), &cur_col, 50); 8918 ahd_sstat0_print(ahd_inb(ahd, SSTAT0), &cur_col, 50); 8919 ahd_sstat1_print(ahd_inb(ahd, SSTAT1), &cur_col, 50); 8920 ahd_sstat2_print(ahd_inb(ahd, SSTAT2), &cur_col, 50); 8921 ahd_sstat3_print(ahd_inb(ahd, SSTAT3), &cur_col, 50); 8922 ahd_perrdiag_print(ahd_inb(ahd, PERRDIAG), &cur_col, 50); 8923 ahd_simode1_print(ahd_inb(ahd, SIMODE1), &cur_col, 50); 8924 ahd_lqistat0_print(ahd_inb(ahd, LQISTAT0), &cur_col, 50); 8925 ahd_lqistat1_print(ahd_inb(ahd, LQISTAT1), &cur_col, 50); 8926 ahd_lqistat2_print(ahd_inb(ahd, LQISTAT2), &cur_col, 50); 8927 ahd_lqostat0_print(ahd_inb(ahd, LQOSTAT0), &cur_col, 50); 8928 ahd_lqostat1_print(ahd_inb(ahd, LQOSTAT1), &cur_col, 50); 8929 ahd_lqostat2_print(ahd_inb(ahd, LQOSTAT2), &cur_col, 50); 8930 printf("\n"); 8931 printf("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x " 8932 "CURRSCB 0x%x NEXTSCB 0x%x\n", 8933 ahd->scb_data.numscbs, ahd_inw(ahd, CMDS_PENDING), 8934 ahd_inw(ahd, LASTSCB), ahd_inw(ahd, CURRSCB), 8935 ahd_inw(ahd, NEXTSCB)); 8936 cur_col = 0; 8937 /* QINFIFO */ 8938 ahd_search_qinfifo(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, 8939 CAM_LUN_WILDCARD, SCB_LIST_NULL, 8940 ROLE_UNKNOWN, /*status*/0, SEARCH_PRINT); 8941 saved_scb_index = ahd_get_scbptr(ahd); 8942 printf("Pending list:"); 8943 i = 0; 8944 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 8945 if (i++ > AHD_SCB_MAX) 8946 break; 8947 cur_col = printf("\n%3d FIFO_USE[0x%x] ", SCB_GET_TAG(scb), 8948 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT)); 8949 ahd_set_scbptr(ahd, SCB_GET_TAG(scb)); 8950 ahd_scb_control_print(ahd_inb_scbram(ahd, SCB_CONTROL), 8951 &cur_col, 60); 8952 ahd_scb_scsiid_print(ahd_inb_scbram(ahd, SCB_SCSIID), 8953 &cur_col, 60); 8954 } 8955 printf("\nTotal %d\n", i); 8956 8957 printf("Kernel Free SCB list: "); 8958 i = 0; 8959 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 8960 struct scb *list_scb; 8961 8962 list_scb = scb; 8963 do { 8964 printf("%d ", SCB_GET_TAG(list_scb)); 8965 list_scb = LIST_NEXT(list_scb, collision_links); 8966 } while (list_scb && i++ < AHD_SCB_MAX); 8967 } 8968 8969 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { 8970 if (i++ > AHD_SCB_MAX) 8971 break; 8972 printf("%d ", SCB_GET_TAG(scb)); 8973 } 8974 printf("\n"); 8975 8976 printf("Sequencer Complete DMA-inprog list: "); 8977 scb_index = ahd_inw(ahd, COMPLETE_SCB_DMAINPROG_HEAD); 8978 i = 0; 8979 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8980 ahd_set_scbptr(ahd, scb_index); 8981 printf("%d ", scb_index); 8982 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 8983 } 8984 printf("\n"); 8985 8986 printf("Sequencer Complete list: "); 8987 scb_index = ahd_inw(ahd, COMPLETE_SCB_HEAD); 8988 i = 0; 8989 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 8990 ahd_set_scbptr(ahd, scb_index); 8991 printf("%d ", scb_index); 8992 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 8993 } 8994 printf("\n"); 8995 8996 8997 printf("Sequencer DMA-Up and Complete list: "); 8998 scb_index = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 8999 i = 0; 9000 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 9001 ahd_set_scbptr(ahd, scb_index); 9002 printf("%d ", scb_index); 9003 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 9004 } 9005 printf("\n"); 9006 printf("Sequencer On QFreeze and Complete list: "); 9007 scb_index = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD); 9008 i = 0; 9009 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 9010 ahd_set_scbptr(ahd, scb_index); 9011 printf("%d ", scb_index); 9012 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 9013 } 9014 printf("\n"); 9015 ahd_set_scbptr(ahd, saved_scb_index); 9016 dffstat = ahd_inb(ahd, DFFSTAT); 9017 for (i = 0; i < 2; i++) { 9018 #ifdef AHD_DEBUG 9019 struct scb *fifo_scb; 9020 #endif 9021 u_int fifo_scbptr; 9022 9023 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); 9024 fifo_scbptr = ahd_get_scbptr(ahd); 9025 printf("\n%s: FIFO%d %s, LONGJMP == 0x%x, SCB 0x%x\n", 9026 ahd_name(ahd), i, 9027 (dffstat & (FIFO0FREE << i)) ? "Free" : "Active", 9028 ahd_inw(ahd, LONGJMP_ADDR), fifo_scbptr); 9029 cur_col = 0; 9030 ahd_seqimode_print(ahd_inb(ahd, SEQIMODE), &cur_col, 50); 9031 ahd_seqintsrc_print(ahd_inb(ahd, SEQINTSRC), &cur_col, 50); 9032 ahd_dfcntrl_print(ahd_inb(ahd, DFCNTRL), &cur_col, 50); 9033 ahd_dfstatus_print(ahd_inb(ahd, DFSTATUS), &cur_col, 50); 9034 ahd_sg_cache_shadow_print(ahd_inb(ahd, SG_CACHE_SHADOW), 9035 &cur_col, 50); 9036 ahd_sg_state_print(ahd_inb(ahd, SG_STATE), &cur_col, 50); 9037 ahd_dffsxfrctl_print(ahd_inb(ahd, DFFSXFRCTL), &cur_col, 50); 9038 ahd_soffcnt_print(ahd_inb(ahd, SOFFCNT), &cur_col, 50); 9039 ahd_mdffstat_print(ahd_inb(ahd, MDFFSTAT), &cur_col, 50); 9040 if (cur_col > 50) { 9041 printf("\n"); 9042 cur_col = 0; 9043 } 9044 cur_col += printf("SHADDR = 0x%x%x, SHCNT = 0x%x ", 9045 ahd_inl(ahd, SHADDR+4), 9046 ahd_inl(ahd, SHADDR), 9047 (ahd_inb(ahd, SHCNT) 9048 | (ahd_inb(ahd, SHCNT + 1) << 8) 9049 | (ahd_inb(ahd, SHCNT + 2) << 16))); 9050 if (cur_col > 50) { 9051 printf("\n"); 9052 cur_col = 0; 9053 } 9054 cur_col += printf("HADDR = 0x%x%x, HCNT = 0x%x ", 9055 ahd_inl(ahd, HADDR+4), 9056 ahd_inl(ahd, HADDR), 9057 (ahd_inb(ahd, HCNT) 9058 | (ahd_inb(ahd, HCNT + 1) << 8) 9059 | (ahd_inb(ahd, HCNT + 2) << 16))); 9060 ahd_ccsgctl_print(ahd_inb(ahd, CCSGCTL), &cur_col, 50); 9061 #ifdef AHD_DEBUG 9062 if ((ahd_debug & AHD_SHOW_SG) != 0) { 9063 fifo_scb = ahd_lookup_scb(ahd, fifo_scbptr); 9064 if (fifo_scb != NULL) 9065 ahd_dump_sglist(fifo_scb); 9066 } 9067 #endif 9068 } 9069 printf("\nLQIN: "); 9070 for (i = 0; i < 20; i++) 9071 printf("0x%x ", ahd_inb(ahd, LQIN + i)); 9072 printf("\n"); 9073 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 9074 printf("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n", 9075 ahd_name(ahd), ahd_inb(ahd, LQISTATE), ahd_inb(ahd, LQOSTATE), 9076 ahd_inb(ahd, OPTIONMODE)); 9077 printf("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n", 9078 ahd_name(ahd), ahd_inb(ahd, OS_SPACE_CNT), 9079 ahd_inb(ahd, MAXCMDCNT)); 9080 ahd_simode0_print(ahd_inb(ahd, SIMODE0), &cur_col, 50); 9081 printf("\n"); 9082 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 9083 cur_col = 0; 9084 ahd_ccscbctl_print(ahd_inb(ahd, CCSCBCTL), &cur_col, 50); 9085 printf("\n"); 9086 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 9087 printf("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n", 9088 ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX), 9089 ahd_inw(ahd, DINDEX)); 9090 printf("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n", 9091 ahd_name(ahd), ahd_get_scbptr(ahd), 9092 ahd_inw_scbram(ahd, SCB_NEXT), 9093 ahd_inw_scbram(ahd, SCB_NEXT2)); 9094 printf("CDB %x %x %x %x %x %x\n", 9095 ahd_inb_scbram(ahd, SCB_CDB_STORE), 9096 ahd_inb_scbram(ahd, SCB_CDB_STORE+1), 9097 ahd_inb_scbram(ahd, SCB_CDB_STORE+2), 9098 ahd_inb_scbram(ahd, SCB_CDB_STORE+3), 9099 ahd_inb_scbram(ahd, SCB_CDB_STORE+4), 9100 ahd_inb_scbram(ahd, SCB_CDB_STORE+5)); 9101 printf("STACK:"); 9102 for (i = 0; i < ahd->stack_size; i++) { 9103 ahd->saved_stack[i] = 9104 ahd_inb(ahd, STACK)|(ahd_inb(ahd, STACK) << 8); 9105 printf(" 0x%x", ahd->saved_stack[i]); 9106 } 9107 for (i = ahd->stack_size-1; i >= 0; i--) { 9108 ahd_outb(ahd, STACK, ahd->saved_stack[i] & 0xFF); 9109 ahd_outb(ahd, STACK, (ahd->saved_stack[i] >> 8) & 0xFF); 9110 } 9111 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 9112 ahd_platform_dump_card_state(ahd); 9113 ahd_restore_modes(ahd, saved_modes); 9114 if (paused == 0) 9115 ahd_unpause(ahd); 9116 } 9117 9118 void 9119 ahd_dump_scbs(struct ahd_softc *ahd) 9120 { 9121 ahd_mode_state saved_modes; 9122 u_int saved_scb_index; 9123 int i; 9124 9125 saved_modes = ahd_save_modes(ahd); 9126 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 9127 saved_scb_index = ahd_get_scbptr(ahd); 9128 for (i = 0; i < AHD_SCB_MAX; i++) { 9129 ahd_set_scbptr(ahd, i); 9130 printf("%3d", i); 9131 printf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n", 9132 ahd_inb_scbram(ahd, SCB_CONTROL), 9133 ahd_inb_scbram(ahd, SCB_SCSIID), 9134 ahd_inw_scbram(ahd, SCB_NEXT), 9135 ahd_inw_scbram(ahd, SCB_NEXT2), 9136 ahd_inl_scbram(ahd, SCB_SGPTR), 9137 ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR)); 9138 } 9139 printf("\n"); 9140 ahd_set_scbptr(ahd, saved_scb_index); 9141 ahd_restore_modes(ahd, saved_modes); 9142 } 9143 9144 9145 /*************************** Timeout Handling *********************************/ 9146 void 9147 ahd_timeout(struct scb *scb) 9148 { 9149 struct ahd_softc *ahd; 9150 9151 ahd = scb->ahd_softc; 9152 if ((scb->flags & SCB_ACTIVE) != 0) { 9153 if ((scb->flags & SCB_TIMEDOUT) == 0) { 9154 LIST_INSERT_HEAD(&ahd->timedout_scbs, scb, 9155 timedout_links); 9156 scb->flags |= SCB_TIMEDOUT; 9157 } 9158 ahd_wakeup_recovery_thread(ahd); 9159 } 9160 } 9161 9162 /* 9163 * ahd_recover_commands determines if any of the commands that have currently 9164 * timedout are the root cause for this timeout. Innocent commands are given 9165 * a new timeout while we wait for the command executing on the bus to timeout. 9166 * This routine is invoked from a thread context so we are allowed to sleep. 9167 * Our lock is not held on entry. 9168 */ 9169 void 9170 ahd_recover_commands(struct ahd_softc *ahd) 9171 { 9172 struct scb *scb; 9173 struct scb *active_scb; 9174 long s; 9175 int found; 9176 int was_paused; 9177 u_int active_scbptr; 9178 u_int last_phase; 9179 9180 ahd_lock(ahd, &s); 9181 9182 /* 9183 * Pause the controller and manually flush any 9184 * commands that have just completed but that our 9185 * interrupt handler has yet to see. 9186 */ 9187 was_paused = ahd_is_paused(ahd); 9188 ahd_pause_and_flushwork(ahd); 9189 9190 if (LIST_EMPTY(&ahd->timedout_scbs) != 0) { 9191 /* 9192 * The timedout commands have already 9193 * completed. This typically means 9194 * that either the timeout value was on 9195 * the hairy edge of what the device 9196 * requires or - more likely - interrupts 9197 * are not happening. 9198 */ 9199 printf("%s: Timedout SCBs already complete. " 9200 "Interrupts may not be functioning.\n", ahd_name(ahd)); 9201 ahd_unpause(ahd); 9202 ahd_unlock(ahd, &s); 9203 return; 9204 } 9205 9206 printf("%s: Recovery Initiated - Card was %spaused\n", ahd_name(ahd), 9207 was_paused ? "" : "not "); 9208 ahd_dump_card_state(ahd); 9209 9210 /* 9211 * Determine identity of SCB acting on the bus. 9212 * This test only catches non-packetized transactions. 9213 * Due to the fleeting nature of packetized operations, 9214 * we can't easily determine that a packetized operation 9215 * is on the bus. 9216 */ 9217 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 9218 last_phase = ahd_inb(ahd, LASTPHASE); 9219 active_scbptr = ahd_get_scbptr(ahd); 9220 active_scb = NULL; 9221 if (last_phase != P_BUSFREE 9222 || (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) == 0) 9223 active_scb = ahd_lookup_scb(ahd, active_scbptr); 9224 9225 while ((scb = LIST_FIRST(&ahd->timedout_scbs)) != NULL) { 9226 int target; 9227 int lun; 9228 char channel; 9229 9230 target = SCB_GET_TARGET(ahd, scb); 9231 channel = SCB_GET_CHANNEL(ahd, scb); 9232 lun = SCB_GET_LUN(scb); 9233 9234 ahd_print_path(ahd, scb); 9235 printf("SCB 0x%x - timed out\n", scb->hscb->tag); 9236 9237 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { 9238 /* 9239 * Been down this road before. 9240 * Do a full bus reset. 9241 */ 9242 aic_set_transaction_status(scb, CAM_CMD_TIMEOUT); 9243 bus_reset: 9244 found = ahd_reset_channel(ahd, channel, 9245 /*Initiate Reset*/TRUE); 9246 printf("%s: Issued Channel %c Bus Reset. " 9247 "%d SCBs aborted\n", ahd_name(ahd), channel, 9248 found); 9249 continue; 9250 } 9251 9252 /* 9253 * Remove the command from the timedout list in 9254 * preparation for requeing it. 9255 */ 9256 LIST_REMOVE(scb, timedout_links); 9257 scb->flags &= ~SCB_TIMEDOUT; 9258 9259 if (active_scb != NULL) { 9260 9261 if (active_scb != scb) { 9262 9263 /* 9264 * If the active SCB is not us, assume that 9265 * the active SCB has a longer timeout than 9266 * the timedout SCB, and wait for the active 9267 * SCB to timeout. As a safeguard, only 9268 * allow this deferral to continue if some 9269 * untimed-out command is outstanding. 9270 */ 9271 if (ahd_other_scb_timeout(ahd, scb, 9272 active_scb) != 0) 9273 goto bus_reset; 9274 continue; 9275 } 9276 9277 /* 9278 * We're active on the bus, so assert ATN 9279 * and hope that the target responds. 9280 */ 9281 ahd_set_recoveryscb(ahd, active_scb); 9282 active_scb->flags |= SCB_RECOVERY_SCB|SCB_DEVICE_RESET; 9283 ahd_outb(ahd, MSG_OUT, HOST_MSG); 9284 ahd_outb(ahd, SCSISIGO, last_phase|ATNO); 9285 ahd_print_path(ahd, active_scb); 9286 printf("BDR message in message buffer\n"); 9287 aic_scb_timer_reset(scb, 2 * 1000000); 9288 break; 9289 } else if (last_phase != P_BUSFREE 9290 && ahd_inb(ahd, SCSIPHASE) == 0) { 9291 /* 9292 * SCB is not identified, there 9293 * is no pending REQ, and the sequencer 9294 * has not seen a busfree. Looks like 9295 * a stuck connection waiting to 9296 * go busfree. Reset the bus. 9297 */ 9298 printf("%s: Connection stuck awaiting busfree or " 9299 "Identify Msg.\n", ahd_name(ahd)); 9300 goto bus_reset; 9301 } else if (ahd_search_qinfifo(ahd, target, channel, lun, 9302 scb->hscb->tag, ROLE_INITIATOR, 9303 /*status*/0, SEARCH_COUNT) > 0) { 9304 9305 /* 9306 * We haven't even gone out on the bus 9307 * yet, so the timeout must be due to 9308 * some other command. Reset the timer 9309 * and go on. 9310 */ 9311 if (ahd_other_scb_timeout(ahd, scb, NULL) != 0) 9312 goto bus_reset; 9313 } else { 9314 /* 9315 * This SCB is for a disconnected transaction 9316 * and we haven't found a better candidate on 9317 * the bus to explain this timeout. 9318 */ 9319 ahd_set_recoveryscb(ahd, scb); 9320 9321 /* 9322 * Actually re-queue this SCB in an attempt 9323 * to select the device before it reconnects. 9324 * In either case (selection or reselection), 9325 * we will now issue a target reset to the 9326 * timed-out device. 9327 * 9328 * Set the MK_MESSAGE control bit indicating 9329 * that we desire to send a message. We 9330 * also set the disconnected flag since 9331 * in the paging case there is no guarantee 9332 * that our SCB control byte matches the 9333 * version on the card. We don't want the 9334 * sequencer to abort the command thinking 9335 * an unsolicited reselection occurred. 9336 */ 9337 scb->flags |= SCB_DEVICE_RESET; 9338 scb->hscb->cdb_len = 0; 9339 scb->hscb->task_attribute = 0; 9340 scb->hscb->task_management = SIU_TASKMGMT_ABORT_TASK; 9341 9342 ahd_set_scbptr(ahd, SCB_GET_TAG(scb)); 9343 if ((scb->flags & SCB_PACKETIZED) != 0) { 9344 /* 9345 * Mark the SCB has having an outstanding 9346 * task management function. Should the command 9347 * complete normally before the task management 9348 * function can be sent, the host will be 9349 * notified to abort our requeued SCB. 9350 */ 9351 ahd_outb(ahd, SCB_TASK_MANAGEMENT, 9352 scb->hscb->task_management); 9353 } else { 9354 /* 9355 * If non-packetized, set the MK_MESSAGE control 9356 * bit indicating that we desire to send a 9357 * message. We also set the disconnected flag 9358 * since there is no guarantee that our SCB 9359 * control byte matches the version on the 9360 * card. We don't want the sequencer to abort 9361 * the command thinking an unsolicited 9362 * reselection occurred. 9363 */ 9364 scb->hscb->control |= MK_MESSAGE|DISCONNECTED; 9365 9366 /* 9367 * The sequencer will never re-reference the 9368 * in-core SCB. To make sure we are notified 9369 * during reslection, set the MK_MESSAGE flag in 9370 * the card's copy of the SCB. 9371 */ 9372 ahd_outb(ahd, SCB_CONTROL, 9373 ahd_inb(ahd, SCB_CONTROL)|MK_MESSAGE); 9374 } 9375 9376 /* 9377 * Clear out any entries in the QINFIFO first 9378 * so we are the next SCB for this target 9379 * to run. 9380 */ 9381 ahd_search_qinfifo(ahd, target, channel, lun, 9382 SCB_LIST_NULL, ROLE_INITIATOR, 9383 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 9384 ahd_qinfifo_requeue_tail(ahd, scb); 9385 ahd_set_scbptr(ahd, active_scbptr); 9386 ahd_print_path(ahd, scb); 9387 printf("Queuing a BDR SCB\n"); 9388 aic_scb_timer_reset(scb, 2 * 1000000); 9389 break; 9390 } 9391 } 9392 9393 /* 9394 * Any remaining SCBs were not the "culprit", so remove 9395 * them from the timeout list. The timer for these commands 9396 * will be reset once the recovery SCB completes. 9397 */ 9398 while ((scb = LIST_FIRST(&ahd->timedout_scbs)) != NULL) { 9399 9400 LIST_REMOVE(scb, timedout_links); 9401 scb->flags &= ~SCB_TIMEDOUT; 9402 } 9403 9404 ahd_unpause(ahd); 9405 ahd_unlock(ahd, &s); 9406 } 9407 9408 /* 9409 * Re-schedule a timeout for the passed in SCB if we determine that some 9410 * other SCB is in the process of recovery or an SCB with a longer 9411 * timeout is still pending. Limit our search to just "other_scb" 9412 * if it is non-NULL. 9413 */ 9414 static int 9415 ahd_other_scb_timeout(struct ahd_softc *ahd, struct scb *scb, 9416 struct scb *other_scb) 9417 { 9418 u_int newtimeout; 9419 int found; 9420 9421 ahd_print_path(ahd, scb); 9422 printf("Other SCB Timeout%s", 9423 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 9424 ? " again\n" : "\n"); 9425 9426 newtimeout = aic_get_timeout(scb); 9427 scb->flags |= SCB_OTHERTCL_TIMEOUT; 9428 found = 0; 9429 if (other_scb != NULL) { 9430 if ((other_scb->flags 9431 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0 9432 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) { 9433 found++; 9434 newtimeout = MAX(aic_get_timeout(other_scb), 9435 newtimeout); 9436 } 9437 } else { 9438 LIST_FOREACH(other_scb, &ahd->pending_scbs, pending_links) { 9439 if ((other_scb->flags 9440 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0 9441 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) { 9442 found++; 9443 newtimeout = MAX(aic_get_timeout(other_scb), 9444 newtimeout); 9445 } 9446 } 9447 } 9448 9449 if (found != 0) 9450 aic_scb_timer_reset(scb, newtimeout); 9451 else { 9452 ahd_print_path(ahd, scb); 9453 printf("No other SCB worth waiting for...\n"); 9454 } 9455 9456 return (found != 0); 9457 } 9458 9459 /**************************** Flexport Logic **********************************/ 9460 /* 9461 * Read count 16bit words from 16bit word address start_addr from the 9462 * SEEPROM attached to the controller, into buf, using the controller's 9463 * SEEPROM reading state machine. Optionally treat the data as a byte 9464 * stream in terms of byte order. 9465 */ 9466 int 9467 ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 9468 u_int start_addr, u_int count, int bytestream) 9469 { 9470 u_int cur_addr; 9471 u_int end_addr; 9472 int error; 9473 9474 /* 9475 * If we never make it through the loop even once, 9476 * we were passed invalid arguments. 9477 */ 9478 error = EINVAL; 9479 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 9480 end_addr = start_addr + count; 9481 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { 9482 9483 ahd_outb(ahd, SEEADR, cur_addr); 9484 ahd_outb(ahd, SEECTL, SEEOP_READ | SEESTART); 9485 9486 error = ahd_wait_seeprom(ahd); 9487 if (error) 9488 break; 9489 if (bytestream != 0) { 9490 uint8_t *bytestream_ptr; 9491 9492 bytestream_ptr = (uint8_t *)buf; 9493 *bytestream_ptr++ = ahd_inb(ahd, SEEDAT); 9494 *bytestream_ptr = ahd_inb(ahd, SEEDAT+1); 9495 } else { 9496 /* 9497 * ahd_inw() already handles machine byte order. 9498 */ 9499 *buf = ahd_inw(ahd, SEEDAT); 9500 } 9501 buf++; 9502 } 9503 return (error); 9504 } 9505 9506 /* 9507 * Write count 16bit words from buf, into SEEPROM attache to the 9508 * controller starting at 16bit word address start_addr, using the 9509 * controller's SEEPROM writing state machine. 9510 */ 9511 int 9512 ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 9513 u_int start_addr, u_int count) 9514 { 9515 u_int cur_addr; 9516 u_int end_addr; 9517 int error; 9518 int retval; 9519 9520 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 9521 error = ENOENT; 9522 9523 /* Place the chip into write-enable mode */ 9524 ahd_outb(ahd, SEEADR, SEEOP_EWEN_ADDR); 9525 ahd_outb(ahd, SEECTL, SEEOP_EWEN | SEESTART); 9526 error = ahd_wait_seeprom(ahd); 9527 if (error) 9528 return (error); 9529 9530 /* 9531 * Write the data. If we don't get throught the loop at 9532 * least once, the arguments were invalid. 9533 */ 9534 retval = EINVAL; 9535 end_addr = start_addr + count; 9536 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { 9537 ahd_outw(ahd, SEEDAT, *buf++); 9538 ahd_outb(ahd, SEEADR, cur_addr); 9539 ahd_outb(ahd, SEECTL, SEEOP_WRITE | SEESTART); 9540 9541 retval = ahd_wait_seeprom(ahd); 9542 if (retval) 9543 break; 9544 } 9545 9546 /* 9547 * Disable writes. 9548 */ 9549 ahd_outb(ahd, SEEADR, SEEOP_EWDS_ADDR); 9550 ahd_outb(ahd, SEECTL, SEEOP_EWDS | SEESTART); 9551 error = ahd_wait_seeprom(ahd); 9552 if (error) 9553 return (error); 9554 return (retval); 9555 } 9556 9557 /* 9558 * Wait ~100us for the serial eeprom to satisfy our request. 9559 */ 9560 int 9561 ahd_wait_seeprom(struct ahd_softc *ahd) 9562 { 9563 int cnt; 9564 9565 cnt = 5000; 9566 while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt) 9567 aic_delay(5); 9568 9569 if (cnt == 0) 9570 return (ETIMEDOUT); 9571 return (0); 9572 } 9573 9574 /* 9575 * Validate the two checksums in the per_channel 9576 * vital product data struct. 9577 */ 9578 int 9579 ahd_verify_vpd_cksum(struct vpd_config *vpd) 9580 { 9581 int i; 9582 int maxaddr; 9583 uint32_t checksum; 9584 uint8_t *vpdarray; 9585 9586 vpdarray = (uint8_t *)vpd; 9587 maxaddr = offsetof(struct vpd_config, vpd_checksum); 9588 checksum = 0; 9589 for (i = offsetof(struct vpd_config, resource_type); i < maxaddr; i++) 9590 checksum = checksum + vpdarray[i]; 9591 if (checksum == 0 9592 || (-checksum & 0xFF) != vpd->vpd_checksum) 9593 return (0); 9594 9595 checksum = 0; 9596 maxaddr = offsetof(struct vpd_config, checksum); 9597 for (i = offsetof(struct vpd_config, default_target_flags); 9598 i < maxaddr; i++) 9599 checksum = checksum + vpdarray[i]; 9600 if (checksum == 0 9601 || (-checksum & 0xFF) != vpd->checksum) 9602 return (0); 9603 return (1); 9604 } 9605 9606 int 9607 ahd_verify_cksum(struct seeprom_config *sc) 9608 { 9609 int i; 9610 int maxaddr; 9611 uint32_t checksum; 9612 uint16_t *scarray; 9613 9614 maxaddr = (sizeof(*sc)/2) - 1; 9615 checksum = 0; 9616 scarray = (uint16_t *)sc; 9617 9618 for (i = 0; i < maxaddr; i++) 9619 checksum = checksum + scarray[i]; 9620 if (checksum == 0 9621 || (checksum & 0xFFFF) != sc->checksum) { 9622 return (0); 9623 } else { 9624 return (1); 9625 } 9626 } 9627 9628 int 9629 ahd_acquire_seeprom(struct ahd_softc *ahd) 9630 { 9631 /* 9632 * We should be able to determine the SEEPROM type 9633 * from the flexport logic, but unfortunately not 9634 * all implementations have this logic and there is 9635 * no programatic method for determining if the logic 9636 * is present. 9637 */ 9638 return (1); 9639 #if 0 9640 uint8_t seetype; 9641 int error; 9642 9643 error = ahd_read_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, &seetype); 9644 if (error != 0 9645 || ((seetype & FLX_ROMSTAT_SEECFG) == FLX_ROMSTAT_SEE_NONE)) 9646 return (0); 9647 return (1); 9648 #endif 9649 } 9650 9651 void 9652 ahd_release_seeprom(struct ahd_softc *ahd) 9653 { 9654 /* Currently a no-op */ 9655 } 9656 9657 int 9658 ahd_write_flexport(struct ahd_softc *ahd, u_int addr, u_int value) 9659 { 9660 int error; 9661 9662 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 9663 if (addr > 7) 9664 panic("ahd_write_flexport: address out of range"); 9665 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); 9666 error = ahd_wait_flexport(ahd); 9667 if (error != 0) 9668 return (error); 9669 ahd_outb(ahd, BRDDAT, value); 9670 ahd_flush_device_writes(ahd); 9671 ahd_outb(ahd, BRDCTL, BRDSTB|BRDEN|(addr << 3)); 9672 ahd_flush_device_writes(ahd); 9673 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); 9674 ahd_flush_device_writes(ahd); 9675 ahd_outb(ahd, BRDCTL, 0); 9676 ahd_flush_device_writes(ahd); 9677 return (0); 9678 } 9679 9680 int 9681 ahd_read_flexport(struct ahd_softc *ahd, u_int addr, uint8_t *value) 9682 { 9683 int error; 9684 9685 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 9686 if (addr > 7) 9687 panic("ahd_read_flexport: address out of range"); 9688 ahd_outb(ahd, BRDCTL, BRDRW|BRDEN|(addr << 3)); 9689 error = ahd_wait_flexport(ahd); 9690 if (error != 0) 9691 return (error); 9692 *value = ahd_inb(ahd, BRDDAT); 9693 ahd_outb(ahd, BRDCTL, 0); 9694 ahd_flush_device_writes(ahd); 9695 return (0); 9696 } 9697 9698 /* 9699 * Wait at most 2 seconds for flexport arbitration to succeed. 9700 */ 9701 int 9702 ahd_wait_flexport(struct ahd_softc *ahd) 9703 { 9704 int cnt; 9705 9706 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 9707 cnt = 1000000 * 2 / 5; 9708 while ((ahd_inb(ahd, BRDCTL) & FLXARBACK) == 0 && --cnt) 9709 aic_delay(5); 9710 9711 if (cnt == 0) 9712 return (ETIMEDOUT); 9713 return (0); 9714 } 9715 9716 /************************* Target Mode ****************************************/ 9717 #ifdef AHD_TARGET_MODE 9718 cam_status 9719 ahd_find_tmode_devs(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb, 9720 struct ahd_tmode_tstate **tstate, 9721 struct ahd_tmode_lstate **lstate, 9722 int notfound_failure) 9723 { 9724 9725 if ((ahd->features & AHD_TARGETMODE) == 0) 9726 return (CAM_REQ_INVALID); 9727 9728 /* 9729 * Handle the 'black hole' device that sucks up 9730 * requests to unattached luns on enabled targets. 9731 */ 9732 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 9733 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 9734 *tstate = NULL; 9735 *lstate = ahd->black_hole; 9736 } else { 9737 u_int max_id; 9738 9739 max_id = (ahd->features & AHD_WIDE) ? 15 : 7; 9740 if (ccb->ccb_h.target_id > max_id) 9741 return (CAM_TID_INVALID); 9742 9743 if (ccb->ccb_h.target_lun >= AHD_NUM_LUNS) 9744 return (CAM_LUN_INVALID); 9745 9746 *tstate = ahd->enabled_targets[ccb->ccb_h.target_id]; 9747 *lstate = NULL; 9748 if (*tstate != NULL) 9749 *lstate = 9750 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 9751 } 9752 9753 if (notfound_failure != 0 && *lstate == NULL) 9754 return (CAM_PATH_INVALID); 9755 9756 return (CAM_REQ_CMP); 9757 } 9758 9759 void 9760 ahd_handle_en_lun(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb) 9761 { 9762 #if NOT_YET 9763 struct ahd_tmode_tstate *tstate; 9764 struct ahd_tmode_lstate *lstate; 9765 struct ccb_en_lun *cel; 9766 cam_status status; 9767 u_int target; 9768 u_int lun; 9769 u_int target_mask; 9770 u_long s; 9771 char channel; 9772 9773 status = ahd_find_tmode_devs(ahd, sim, ccb, &tstate, &lstate, 9774 /*notfound_failure*/FALSE); 9775 9776 if (status != CAM_REQ_CMP) { 9777 ccb->ccb_h.status = status; 9778 return; 9779 } 9780 9781 if ((ahd->features & AHD_MULTIROLE) != 0) { 9782 u_int our_id; 9783 9784 our_id = ahd->our_id; 9785 if (ccb->ccb_h.target_id != our_id) { 9786 if ((ahd->features & AHD_MULTI_TID) != 0 9787 && (ahd->flags & AHD_INITIATORROLE) != 0) { 9788 /* 9789 * Only allow additional targets if 9790 * the initiator role is disabled. 9791 * The hardware cannot handle a re-select-in 9792 * on the initiator id during a re-select-out 9793 * on a different target id. 9794 */ 9795 status = CAM_TID_INVALID; 9796 } else if ((ahd->flags & AHD_INITIATORROLE) != 0 9797 || ahd->enabled_luns > 0) { 9798 /* 9799 * Only allow our target id to change 9800 * if the initiator role is not configured 9801 * and there are no enabled luns which 9802 * are attached to the currently registered 9803 * scsi id. 9804 */ 9805 status = CAM_TID_INVALID; 9806 } 9807 } 9808 } 9809 9810 if (status != CAM_REQ_CMP) { 9811 ccb->ccb_h.status = status; 9812 return; 9813 } 9814 9815 /* 9816 * We now have an id that is valid. 9817 * If we aren't in target mode, switch modes. 9818 */ 9819 if ((ahd->flags & AHD_TARGETROLE) == 0 9820 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 9821 u_long s; 9822 9823 printf("Configuring Target Mode\n"); 9824 ahd_lock(ahd, &s); 9825 if (LIST_FIRST(&ahd->pending_scbs) != NULL) { 9826 ccb->ccb_h.status = CAM_BUSY; 9827 ahd_unlock(ahd, &s); 9828 return; 9829 } 9830 ahd->flags |= AHD_TARGETROLE; 9831 if ((ahd->features & AHD_MULTIROLE) == 0) 9832 ahd->flags &= ~AHD_INITIATORROLE; 9833 ahd_pause(ahd); 9834 ahd_loadseq(ahd); 9835 ahd_restart(ahd); 9836 ahd_unlock(ahd, &s); 9837 } 9838 cel = &ccb->cel; 9839 target = ccb->ccb_h.target_id; 9840 lun = ccb->ccb_h.target_lun; 9841 channel = SIM_CHANNEL(ahd, sim); 9842 target_mask = 0x01 << target; 9843 if (channel == 'B') 9844 target_mask <<= 8; 9845 9846 if (cel->enable != 0) { 9847 u_int scsiseq1; 9848 9849 /* Are we already enabled?? */ 9850 if (lstate != NULL) { 9851 xpt_print_path(ccb->ccb_h.path); 9852 printf("Lun already enabled\n"); 9853 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 9854 return; 9855 } 9856 9857 if (cel->grp6_len != 0 9858 || cel->grp7_len != 0) { 9859 /* 9860 * Don't (yet?) support vendor 9861 * specific commands. 9862 */ 9863 ccb->ccb_h.status = CAM_REQ_INVALID; 9864 printf("Non-zero Group Codes\n"); 9865 return; 9866 } 9867 9868 /* 9869 * Seems to be okay. 9870 * Setup our data structures. 9871 */ 9872 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 9873 tstate = ahd_alloc_tstate(ahd, target, channel); 9874 if (tstate == NULL) { 9875 xpt_print_path(ccb->ccb_h.path); 9876 printf("Couldn't allocate tstate\n"); 9877 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9878 return; 9879 } 9880 } 9881 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 9882 if (lstate == NULL) { 9883 xpt_print_path(ccb->ccb_h.path); 9884 printf("Couldn't allocate lstate\n"); 9885 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9886 return; 9887 } 9888 memset(lstate, 0, sizeof(*lstate)); 9889 status = xpt_create_path(&lstate->path, /*periph*/NULL, 9890 xpt_path_path_id(ccb->ccb_h.path), 9891 xpt_path_target_id(ccb->ccb_h.path), 9892 xpt_path_lun_id(ccb->ccb_h.path)); 9893 if (status != CAM_REQ_CMP) { 9894 free(lstate, M_DEVBUF); 9895 xpt_print_path(ccb->ccb_h.path); 9896 printf("Couldn't allocate path\n"); 9897 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9898 return; 9899 } 9900 SLIST_INIT(&lstate->accept_tios); 9901 SLIST_INIT(&lstate->immed_notifies); 9902 ahd_lock(ahd, &s); 9903 ahd_pause(ahd); 9904 if (target != CAM_TARGET_WILDCARD) { 9905 tstate->enabled_luns[lun] = lstate; 9906 ahd->enabled_luns++; 9907 9908 if ((ahd->features & AHD_MULTI_TID) != 0) { 9909 u_int targid_mask; 9910 9911 targid_mask = ahd_inw(ahd, TARGID); 9912 targid_mask |= target_mask; 9913 ahd_outw(ahd, TARGID, targid_mask); 9914 ahd_update_scsiid(ahd, targid_mask); 9915 } else { 9916 u_int our_id; 9917 char channel; 9918 9919 channel = SIM_CHANNEL(ahd, sim); 9920 our_id = SIM_SCSI_ID(ahd, sim); 9921 9922 /* 9923 * This can only happen if selections 9924 * are not enabled 9925 */ 9926 if (target != our_id) { 9927 u_int sblkctl; 9928 char cur_channel; 9929 int swap; 9930 9931 sblkctl = ahd_inb(ahd, SBLKCTL); 9932 cur_channel = (sblkctl & SELBUSB) 9933 ? 'B' : 'A'; 9934 if ((ahd->features & AHD_TWIN) == 0) 9935 cur_channel = 'A'; 9936 swap = cur_channel != channel; 9937 ahd->our_id = target; 9938 9939 if (swap) 9940 ahd_outb(ahd, SBLKCTL, 9941 sblkctl ^ SELBUSB); 9942 9943 ahd_outb(ahd, SCSIID, target); 9944 9945 if (swap) 9946 ahd_outb(ahd, SBLKCTL, sblkctl); 9947 } 9948 } 9949 } else 9950 ahd->black_hole = lstate; 9951 /* Allow select-in operations */ 9952 if (ahd->black_hole != NULL && ahd->enabled_luns > 0) { 9953 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 9954 scsiseq1 |= ENSELI; 9955 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); 9956 scsiseq1 = ahd_inb(ahd, SCSISEQ1); 9957 scsiseq1 |= ENSELI; 9958 ahd_outb(ahd, SCSISEQ1, scsiseq1); 9959 } 9960 ahd_unpause(ahd); 9961 ahd_unlock(ahd, &s); 9962 ccb->ccb_h.status = CAM_REQ_CMP; 9963 xpt_print_path(ccb->ccb_h.path); 9964 printf("Lun now enabled for target mode\n"); 9965 } else { 9966 struct scb *scb; 9967 int i, empty; 9968 9969 if (lstate == NULL) { 9970 ccb->ccb_h.status = CAM_LUN_INVALID; 9971 return; 9972 } 9973 9974 ahd_lock(ahd, &s); 9975 9976 ccb->ccb_h.status = CAM_REQ_CMP; 9977 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 9978 struct ccb_hdr *ccbh; 9979 9980 ccbh = &scb->io_ctx->ccb_h; 9981 if (ccbh->func_code == XPT_CONT_TARGET_IO 9982 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 9983 printf("CTIO pending\n"); 9984 ccb->ccb_h.status = CAM_REQ_INVALID; 9985 ahd_unlock(ahd, &s); 9986 return; 9987 } 9988 } 9989 9990 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 9991 printf("ATIOs pending\n"); 9992 ccb->ccb_h.status = CAM_REQ_INVALID; 9993 } 9994 9995 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 9996 printf("INOTs pending\n"); 9997 ccb->ccb_h.status = CAM_REQ_INVALID; 9998 } 9999 10000 if (ccb->ccb_h.status != CAM_REQ_CMP) { 10001 ahd_unlock(ahd, &s); 10002 return; 10003 } 10004 10005 xpt_print_path(ccb->ccb_h.path); 10006 printf("Target mode disabled\n"); 10007 xpt_free_path(lstate->path); 10008 free(lstate, M_DEVBUF); 10009 10010 ahd_pause(ahd); 10011 /* Can we clean up the target too? */ 10012 if (target != CAM_TARGET_WILDCARD) { 10013 tstate->enabled_luns[lun] = NULL; 10014 ahd->enabled_luns--; 10015 for (empty = 1, i = 0; i < 8; i++) 10016 if (tstate->enabled_luns[i] != NULL) { 10017 empty = 0; 10018 break; 10019 } 10020 10021 if (empty) { 10022 ahd_free_tstate(ahd, target, channel, 10023 /*force*/FALSE); 10024 if (ahd->features & AHD_MULTI_TID) { 10025 u_int targid_mask; 10026 10027 targid_mask = ahd_inw(ahd, TARGID); 10028 targid_mask &= ~target_mask; 10029 ahd_outw(ahd, TARGID, targid_mask); 10030 ahd_update_scsiid(ahd, targid_mask); 10031 } 10032 } 10033 } else { 10034 10035 ahd->black_hole = NULL; 10036 10037 /* 10038 * We can't allow selections without 10039 * our black hole device. 10040 */ 10041 empty = TRUE; 10042 } 10043 if (ahd->enabled_luns == 0) { 10044 /* Disallow select-in */ 10045 u_int scsiseq1; 10046 10047 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 10048 scsiseq1 &= ~ENSELI; 10049 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); 10050 scsiseq1 = ahd_inb(ahd, SCSISEQ1); 10051 scsiseq1 &= ~ENSELI; 10052 ahd_outb(ahd, SCSISEQ1, scsiseq1); 10053 10054 if ((ahd->features & AHD_MULTIROLE) == 0) { 10055 printf("Configuring Initiator Mode\n"); 10056 ahd->flags &= ~AHD_TARGETROLE; 10057 ahd->flags |= AHD_INITIATORROLE; 10058 ahd_pause(ahd); 10059 ahd_loadseq(ahd); 10060 ahd_restart(ahd); 10061 /* 10062 * Unpaused. The extra unpause 10063 * that follows is harmless. 10064 */ 10065 } 10066 } 10067 ahd_unpause(ahd); 10068 ahd_unlock(ahd, &s); 10069 } 10070 #endif 10071 } 10072 10073 static void 10074 ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask) 10075 { 10076 #if NOT_YET 10077 u_int scsiid_mask; 10078 u_int scsiid; 10079 10080 if ((ahd->features & AHD_MULTI_TID) == 0) 10081 panic("ahd_update_scsiid called on non-multitid unit\n"); 10082 10083 /* 10084 * Since we will rely on the TARGID mask 10085 * for selection enables, ensure that OID 10086 * in SCSIID is not set to some other ID 10087 * that we don't want to allow selections on. 10088 */ 10089 if ((ahd->features & AHD_ULTRA2) != 0) 10090 scsiid = ahd_inb(ahd, SCSIID_ULTRA2); 10091 else 10092 scsiid = ahd_inb(ahd, SCSIID); 10093 scsiid_mask = 0x1 << (scsiid & OID); 10094 if ((targid_mask & scsiid_mask) == 0) { 10095 u_int our_id; 10096 10097 /* ffs counts from 1 */ 10098 our_id = ffs(targid_mask); 10099 if (our_id == 0) 10100 our_id = ahd->our_id; 10101 else 10102 our_id--; 10103 scsiid &= TID; 10104 scsiid |= our_id; 10105 } 10106 if ((ahd->features & AHD_ULTRA2) != 0) 10107 ahd_outb(ahd, SCSIID_ULTRA2, scsiid); 10108 else 10109 ahd_outb(ahd, SCSIID, scsiid); 10110 #endif 10111 } 10112 10113 void 10114 ahd_run_tqinfifo(struct ahd_softc *ahd, int paused) 10115 { 10116 struct target_cmd *cmd; 10117 10118 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_POSTREAD); 10119 while ((cmd = &ahd->targetcmds[ahd->tqinfifonext])->cmd_valid != 0) { 10120 10121 /* 10122 * Only advance through the queue if we 10123 * have the resources to process the command. 10124 */ 10125 if (ahd_handle_target_cmd(ahd, cmd) != 0) 10126 break; 10127 10128 cmd->cmd_valid = 0; 10129 ahd_dmamap_sync(ahd, ahd->shared_data_dmat, 10130 ahd->shared_data_dmamap, 10131 ahd_targetcmd_offset(ahd, ahd->tqinfifonext), 10132 sizeof(struct target_cmd), 10133 BUS_DMASYNC_PREREAD); 10134 ahd->tqinfifonext++; 10135 10136 /* 10137 * Lazily update our position in the target mode incoming 10138 * command queue as seen by the sequencer. 10139 */ 10140 if ((ahd->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 10141 u_int hs_mailbox; 10142 10143 hs_mailbox = ahd_inb(ahd, HS_MAILBOX); 10144 hs_mailbox &= ~HOST_TQINPOS; 10145 hs_mailbox |= ahd->tqinfifonext & HOST_TQINPOS; 10146 ahd_outb(ahd, HS_MAILBOX, hs_mailbox); 10147 } 10148 } 10149 } 10150 10151 static int 10152 ahd_handle_target_cmd(struct ahd_softc *ahd, struct target_cmd *cmd) 10153 { 10154 struct ahd_tmode_tstate *tstate; 10155 struct ahd_tmode_lstate *lstate; 10156 struct ccb_accept_tio *atio; 10157 uint8_t *byte; 10158 int initiator; 10159 int target; 10160 int lun; 10161 10162 initiator = SCSIID_TARGET(ahd, cmd->scsiid); 10163 target = SCSIID_OUR_ID(cmd->scsiid); 10164 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 10165 10166 byte = cmd->bytes; 10167 tstate = ahd->enabled_targets[target]; 10168 lstate = NULL; 10169 if (tstate != NULL) 10170 lstate = tstate->enabled_luns[lun]; 10171 10172 /* 10173 * Commands for disabled luns go to the black hole driver. 10174 */ 10175 if (lstate == NULL) 10176 lstate = ahd->black_hole; 10177 10178 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 10179 if (atio == NULL) { 10180 ahd->flags |= AHD_TQINFIFO_BLOCKED; 10181 /* 10182 * Wait for more ATIOs from the peripheral driver for this lun. 10183 */ 10184 return (1); 10185 } else 10186 ahd->flags &= ~AHD_TQINFIFO_BLOCKED; 10187 #ifdef AHD_DEBUG 10188 if ((ahd_debug & AHD_SHOW_TQIN) != 0) 10189 printf("Incoming command from %d for %d:%d%s\n", 10190 initiator, target, lun, 10191 lstate == ahd->black_hole ? "(Black Holed)" : ""); 10192 #endif 10193 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 10194 10195 if (lstate == ahd->black_hole) { 10196 /* Fill in the wildcards */ 10197 atio->ccb_h.target_id = target; 10198 atio->ccb_h.target_lun = lun; 10199 } 10200 10201 /* 10202 * Package it up and send it off to 10203 * whomever has this lun enabled. 10204 */ 10205 atio->sense_len = 0; 10206 atio->init_id = initiator; 10207 if (byte[0] != 0xFF) { 10208 /* Tag was included */ 10209 atio->tag_action = *byte++; 10210 atio->tag_id = *byte++; 10211 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 10212 } else { 10213 atio->ccb_h.flags = 0; 10214 } 10215 byte++; 10216 10217 /* Okay. Now determine the cdb size based on the command code */ 10218 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 10219 case 0: 10220 atio->cdb_len = 6; 10221 break; 10222 case 1: 10223 case 2: 10224 atio->cdb_len = 10; 10225 break; 10226 case 4: 10227 atio->cdb_len = 16; 10228 break; 10229 case 5: 10230 atio->cdb_len = 12; 10231 break; 10232 case 3: 10233 default: 10234 /* Only copy the opcode. */ 10235 atio->cdb_len = 1; 10236 printf("Reserved or VU command code type encountered\n"); 10237 break; 10238 } 10239 10240 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 10241 10242 atio->ccb_h.status |= CAM_CDB_RECVD; 10243 10244 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 10245 /* 10246 * We weren't allowed to disconnect. 10247 * We're hanging on the bus until a 10248 * continue target I/O comes in response 10249 * to this accept tio. 10250 */ 10251 #ifdef AHD_DEBUG 10252 if ((ahd_debug & AHD_SHOW_TQIN) != 0) 10253 printf("Received Immediate Command %d:%d:%d - %p\n", 10254 initiator, target, lun, ahd->pending_device); 10255 #endif 10256 ahd->pending_device = lstate; 10257 ahd_freeze_ccb((union ccb *)atio); 10258 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 10259 } 10260 xpt_done((union ccb*)atio); 10261 return (0); 10262 } 10263 10264 #endif 10265