1 /*- 2 * Core routines and tables shareable across OS platforms. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * Copyright (c) 1994-2002, 2004 Justin T. Gibbs. 7 * Copyright (c) 2000-2003 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.c#246 $ 43 */ 44 45 #ifdef __linux__ 46 #include "aic79xx_osm.h" 47 #include "aic79xx_inline.h" 48 #include "aicasm/aicasm_insformat.h" 49 #else 50 #include <sys/cdefs.h> 51 #include <dev/aic7xxx/aic79xx_osm.h> 52 #include <dev/aic7xxx/aic79xx_inline.h> 53 #include <dev/aic7xxx/aicasm/aicasm_insformat.h> 54 #endif 55 56 /******************************** Globals *************************************/ 57 struct ahd_softc_tailq ahd_tailq = TAILQ_HEAD_INITIALIZER(ahd_tailq); 58 uint32_t ahd_attach_to_HostRAID_controllers = 1; 59 60 /***************************** Lookup Tables **********************************/ 61 char *ahd_chip_names[] = 62 { 63 "NONE", 64 "aic7901", 65 "aic7902", 66 "aic7901A" 67 }; 68 69 /* 70 * Hardware error codes. 71 */ 72 struct ahd_hard_error_entry { 73 uint8_t errno; 74 char *errmesg; 75 }; 76 77 static struct ahd_hard_error_entry ahd_hard_errors[] = { 78 { DSCTMOUT, "Discard Timer has timed out" }, 79 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 80 { SQPARERR, "Sequencer Parity Error" }, 81 { DPARERR, "Data-path Parity Error" }, 82 { MPARERR, "Scratch or SCB Memory Parity Error" }, 83 { CIOPARERR, "CIOBUS Parity Error" }, 84 }; 85 static const u_int num_errors = NUM_ELEMENTS(ahd_hard_errors); 86 87 static struct ahd_phase_table_entry ahd_phase_table[] = 88 { 89 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 90 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 91 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 92 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 93 { P_COMMAND, MSG_NOOP, "in Command phase" }, 94 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 95 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 96 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 97 { P_BUSFREE, MSG_NOOP, "while idle" }, 98 { 0, MSG_NOOP, "in unknown phase" } 99 }; 100 101 /* 102 * In most cases we only wish to itterate over real phases, so 103 * exclude the last element from the count. 104 */ 105 static const u_int num_phases = NUM_ELEMENTS(ahd_phase_table) - 1; 106 107 /* Our Sequencer Program */ 108 #include "aic79xx_seq.h" 109 110 /**************************** Function Declarations ***************************/ 111 static void ahd_handle_transmission_error(struct ahd_softc *ahd); 112 static void ahd_handle_lqiphase_error(struct ahd_softc *ahd, 113 u_int lqistat1); 114 static int ahd_handle_pkt_busfree(struct ahd_softc *ahd, 115 u_int busfreetime); 116 static int ahd_handle_nonpkt_busfree(struct ahd_softc *ahd); 117 static void ahd_handle_proto_violation(struct ahd_softc *ahd); 118 static void ahd_force_renegotiation(struct ahd_softc *ahd, 119 struct ahd_devinfo *devinfo); 120 121 static struct ahd_tmode_tstate* 122 ahd_alloc_tstate(struct ahd_softc *ahd, 123 u_int scsi_id, char channel); 124 #ifdef AHD_TARGET_MODE 125 static void ahd_free_tstate(struct ahd_softc *ahd, 126 u_int scsi_id, char channel, int force); 127 #endif 128 static void ahd_devlimited_syncrate(struct ahd_softc *ahd, 129 struct ahd_initiator_tinfo *, 130 u_int *period, 131 u_int *ppr_options, 132 role_t role); 133 static void ahd_update_neg_table(struct ahd_softc *ahd, 134 struct ahd_devinfo *devinfo, 135 struct ahd_transinfo *tinfo); 136 static void ahd_update_pending_scbs(struct ahd_softc *ahd); 137 static void ahd_fetch_devinfo(struct ahd_softc *ahd, 138 struct ahd_devinfo *devinfo); 139 static void ahd_scb_devinfo(struct ahd_softc *ahd, 140 struct ahd_devinfo *devinfo, 141 struct scb *scb); 142 static void ahd_setup_initiator_msgout(struct ahd_softc *ahd, 143 struct ahd_devinfo *devinfo, 144 struct scb *scb); 145 static void ahd_build_transfer_msg(struct ahd_softc *ahd, 146 struct ahd_devinfo *devinfo); 147 static void ahd_construct_sdtr(struct ahd_softc *ahd, 148 struct ahd_devinfo *devinfo, 149 u_int period, u_int offset); 150 static void ahd_construct_wdtr(struct ahd_softc *ahd, 151 struct ahd_devinfo *devinfo, 152 u_int bus_width); 153 static void ahd_construct_ppr(struct ahd_softc *ahd, 154 struct ahd_devinfo *devinfo, 155 u_int period, u_int offset, 156 u_int bus_width, u_int ppr_options); 157 static void ahd_clear_msg_state(struct ahd_softc *ahd); 158 static void ahd_handle_message_phase(struct ahd_softc *ahd); 159 typedef enum { 160 AHDMSG_1B, 161 AHDMSG_2B, 162 AHDMSG_EXT 163 } ahd_msgtype; 164 static int ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, 165 u_int msgval, int full); 166 static int ahd_parse_msg(struct ahd_softc *ahd, 167 struct ahd_devinfo *devinfo); 168 static int ahd_handle_msg_reject(struct ahd_softc *ahd, 169 struct ahd_devinfo *devinfo); 170 static void ahd_handle_ign_wide_residue(struct ahd_softc *ahd, 171 struct ahd_devinfo *devinfo); 172 static void ahd_reinitialize_dataptrs(struct ahd_softc *ahd); 173 static void ahd_handle_devreset(struct ahd_softc *ahd, 174 struct ahd_devinfo *devinfo, 175 u_int lun, cam_status status, 176 char *message, int verbose_level); 177 #ifdef AHD_TARGET_MODE 178 static void ahd_setup_target_msgin(struct ahd_softc *ahd, 179 struct ahd_devinfo *devinfo, 180 struct scb *scb); 181 #endif 182 183 static u_int ahd_sglist_size(struct ahd_softc *ahd); 184 static u_int ahd_sglist_allocsize(struct ahd_softc *ahd); 185 static bus_dmamap_callback_t 186 ahd_dmamap_cb; 187 static void ahd_initialize_hscbs(struct ahd_softc *ahd); 188 static int ahd_init_scbdata(struct ahd_softc *ahd); 189 static void ahd_fini_scbdata(struct ahd_softc *ahd); 190 static void ahd_setup_iocell_workaround(struct ahd_softc *ahd); 191 static void ahd_iocell_first_selection(struct ahd_softc *ahd); 192 static void ahd_add_col_list(struct ahd_softc *ahd, 193 struct scb *scb, u_int col_idx); 194 static void ahd_rem_col_list(struct ahd_softc *ahd, 195 struct scb *scb); 196 static void ahd_chip_init(struct ahd_softc *ahd); 197 static void ahd_qinfifo_requeue(struct ahd_softc *ahd, 198 struct scb *prev_scb, 199 struct scb *scb); 200 static int ahd_qinfifo_count(struct ahd_softc *ahd); 201 static int ahd_search_scb_list(struct ahd_softc *ahd, int target, 202 char channel, int lun, u_int tag, 203 role_t role, uint32_t status, 204 ahd_search_action action, 205 u_int *list_head, u_int *list_tail, 206 u_int tid); 207 static void ahd_stitch_tid_list(struct ahd_softc *ahd, 208 u_int tid_prev, u_int tid_cur, 209 u_int tid_next); 210 static void ahd_add_scb_to_free_list(struct ahd_softc *ahd, 211 u_int scbid); 212 static u_int ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, 213 u_int prev, u_int next, u_int tid); 214 static void ahd_reset_current_bus(struct ahd_softc *ahd); 215 static ahd_callback_t ahd_reset_poll; 216 static ahd_callback_t ahd_stat_timer; 217 #ifdef AHD_DUMP_SEQ 218 static void ahd_dumpseq(struct ahd_softc *ahd); 219 #endif 220 static void ahd_loadseq(struct ahd_softc *ahd); 221 static int ahd_check_patch(struct ahd_softc *ahd, 222 struct patch **start_patch, 223 u_int start_instr, u_int *skip_addr); 224 static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd, 225 u_int address); 226 static void ahd_download_instr(struct ahd_softc *ahd, 227 u_int instrptr, uint8_t *dconsts); 228 static int ahd_probe_stack_size(struct ahd_softc *ahd); 229 static int ahd_other_scb_timeout(struct ahd_softc *ahd, 230 struct scb *scb, 231 struct scb *other_scb); 232 static int ahd_scb_active_in_fifo(struct ahd_softc *ahd, 233 struct scb *scb); 234 static void ahd_run_data_fifo(struct ahd_softc *ahd, 235 struct scb *scb); 236 237 #ifdef AHD_TARGET_MODE 238 static void ahd_queue_lstate_event(struct ahd_softc *ahd, 239 struct ahd_tmode_lstate *lstate, 240 u_int initiator_id, 241 u_int event_type, 242 u_int event_arg); 243 static void ahd_update_scsiid(struct ahd_softc *ahd, 244 u_int targid_mask); 245 static int ahd_handle_target_cmd(struct ahd_softc *ahd, 246 struct target_cmd *cmd); 247 #endif 248 249 /******************************** Private Inlines *****************************/ 250 static __inline void ahd_assert_atn(struct ahd_softc *ahd); 251 static __inline int ahd_currently_packetized(struct ahd_softc *ahd); 252 static __inline int ahd_set_active_fifo(struct ahd_softc *ahd); 253 254 static __inline void 255 ahd_assert_atn(struct ahd_softc *ahd) 256 { 257 ahd_outb(ahd, SCSISIGO, ATNO); 258 } 259 260 /* 261 * Determine if the current connection has a packetized 262 * agreement. This does not necessarily mean that we 263 * are currently in a packetized transfer. We could 264 * just as easily be sending or receiving a message. 265 */ 266 static __inline int 267 ahd_currently_packetized(struct ahd_softc *ahd) 268 { 269 ahd_mode_state saved_modes; 270 int packetized; 271 272 saved_modes = ahd_save_modes(ahd); 273 if ((ahd->bugs & AHD_PKTIZED_STATUS_BUG) != 0) { 274 /* 275 * The packetized bit refers to the last 276 * connection, not the current one. Check 277 * for non-zero LQISTATE instead. 278 */ 279 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 280 packetized = ahd_inb(ahd, LQISTATE) != 0; 281 } else { 282 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 283 packetized = ahd_inb(ahd, LQISTAT2) & PACKETIZED; 284 } 285 ahd_restore_modes(ahd, saved_modes); 286 return (packetized); 287 } 288 289 static __inline int 290 ahd_set_active_fifo(struct ahd_softc *ahd) 291 { 292 u_int active_fifo; 293 294 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 295 active_fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; 296 switch (active_fifo) { 297 case 0: 298 case 1: 299 ahd_set_modes(ahd, active_fifo, active_fifo); 300 return (1); 301 default: 302 return (0); 303 } 304 } 305 306 /************************* Sequencer Execution Control ************************/ 307 /* 308 * Restart the sequencer program from address zero 309 */ 310 void 311 ahd_restart(struct ahd_softc *ahd) 312 { 313 314 ahd_pause(ahd); 315 316 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 317 318 /* No more pending messages */ 319 ahd_clear_msg_state(ahd); 320 ahd_outb(ahd, SCSISIGO, 0); /* De-assert BSY */ 321 ahd_outb(ahd, MSG_OUT, MSG_NOOP); /* No message to send */ 322 ahd_outb(ahd, SXFRCTL1, ahd_inb(ahd, SXFRCTL1) & ~BITBUCKET); 323 ahd_outb(ahd, SEQINTCTL, 0); 324 ahd_outb(ahd, LASTPHASE, P_BUSFREE); 325 ahd_outb(ahd, SEQ_FLAGS, 0); 326 ahd_outb(ahd, SAVED_SCSIID, 0xFF); 327 ahd_outb(ahd, SAVED_LUN, 0xFF); 328 329 /* 330 * Ensure that the sequencer's idea of TQINPOS 331 * matches our own. The sequencer increments TQINPOS 332 * only after it sees a DMA complete and a reset could 333 * occur before the increment leaving the kernel to believe 334 * the command arrived but the sequencer to not. 335 */ 336 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); 337 338 /* Always allow reselection */ 339 ahd_outb(ahd, SCSISEQ1, 340 ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 341 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 342 343 /* 344 * Clear any pending sequencer interrupt. It is no 345 * longer relevant since we're resetting the Program 346 * Counter. 347 */ 348 ahd_outb(ahd, CLRINT, CLRSEQINT); 349 350 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); 351 ahd_unpause(ahd); 352 } 353 354 void 355 ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo) 356 { 357 ahd_mode_state saved_modes; 358 359 #ifdef AHD_DEBUG 360 if ((ahd_debug & AHD_SHOW_FIFOS) != 0) 361 printf("%s: Clearing FIFO %d\n", ahd_name(ahd), fifo); 362 #endif 363 saved_modes = ahd_save_modes(ahd); 364 ahd_set_modes(ahd, fifo, fifo); 365 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); 366 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) 367 ahd_outb(ahd, CCSGCTL, CCSGRESET); 368 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 369 ahd_outb(ahd, SG_STATE, 0); 370 ahd_restore_modes(ahd, saved_modes); 371 } 372 373 /************************* Input/Output Queues ********************************/ 374 /* 375 * Flush and completed commands that are sitting in the command 376 * complete queues down on the chip but have yet to be dma'ed back up. 377 */ 378 void 379 ahd_flush_qoutfifo(struct ahd_softc *ahd) 380 { 381 struct scb *scb; 382 ahd_mode_state saved_modes; 383 u_int saved_scbptr; 384 u_int ccscbctl; 385 u_int scbid; 386 u_int next_scbid; 387 388 saved_modes = ahd_save_modes(ahd); 389 390 /* 391 * Flush the good status FIFO for completed packetized commands. 392 */ 393 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 394 saved_scbptr = ahd_get_scbptr(ahd); 395 while ((ahd_inb(ahd, LQISTAT2) & LQIGSAVAIL) != 0) { 396 u_int fifo_mode; 397 u_int i; 398 399 scbid = ahd_inw(ahd, GSFIFO); 400 scb = ahd_lookup_scb(ahd, scbid); 401 if (scb == NULL) { 402 printf("%s: Warning - GSFIFO SCB %d invalid\n", 403 ahd_name(ahd), scbid); 404 AHD_CORRECTABLE_ERROR(ahd); 405 continue; 406 } 407 /* 408 * Determine if this transaction is still active in 409 * any FIFO. If it is, we must flush that FIFO to 410 * the host before completing the command. 411 */ 412 fifo_mode = 0; 413 rescan_fifos: 414 for (i = 0; i < 2; i++) { 415 /* Toggle to the other mode. */ 416 fifo_mode ^= 1; 417 ahd_set_modes(ahd, fifo_mode, fifo_mode); 418 419 if (ahd_scb_active_in_fifo(ahd, scb) == 0) 420 continue; 421 422 ahd_run_data_fifo(ahd, scb); 423 424 /* 425 * Running this FIFO may cause a CFG4DATA for 426 * this same transaction to assert in the other 427 * FIFO or a new snapshot SAVEPTRS interrupt 428 * in this FIFO. Even running a FIFO may not 429 * clear the transaction if we are still waiting 430 * for data to drain to the host. We must loop 431 * until the transaction is not active in either 432 * FIFO just to be sure. Reset our loop counter 433 * so we will visit both FIFOs again before 434 * declaring this transaction finished. We 435 * also delay a bit so that status has a chance 436 * to change before we look at this FIFO again. 437 */ 438 aic_delay(200); 439 goto rescan_fifos; 440 } 441 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 442 ahd_set_scbptr(ahd, scbid); 443 if ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_LIST_NULL) == 0 444 && ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_FULL_RESID) != 0 445 || (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR) 446 & SG_LIST_NULL) != 0)) { 447 u_int comp_head; 448 449 /* 450 * The transfer completed with a residual. 451 * Place this SCB on the complete DMA list 452 * so that we update our in-core copy of the 453 * SCB before completing the command. 454 */ 455 ahd_outb(ahd, SCB_SCSI_STATUS, 0); 456 ahd_outb(ahd, SCB_SGPTR, 457 ahd_inb_scbram(ahd, SCB_SGPTR) 458 | SG_STATUS_VALID); 459 ahd_outw(ahd, SCB_TAG, scbid); 460 ahd_outw(ahd, SCB_NEXT_COMPLETE, SCB_LIST_NULL); 461 comp_head = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 462 if (SCBID_IS_NULL(comp_head)) { 463 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, scbid); 464 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid); 465 } else { 466 u_int tail; 467 468 tail = ahd_inw(ahd, COMPLETE_DMA_SCB_TAIL); 469 ahd_set_scbptr(ahd, tail); 470 ahd_outw(ahd, SCB_NEXT_COMPLETE, scbid); 471 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid); 472 ahd_set_scbptr(ahd, scbid); 473 } 474 } else 475 ahd_complete_scb(ahd, scb); 476 } 477 ahd_set_scbptr(ahd, saved_scbptr); 478 479 /* 480 * Setup for command channel portion of flush. 481 */ 482 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 483 484 /* 485 * Wait for any inprogress DMA to complete and clear DMA state 486 * if this if for an SCB in the qinfifo. 487 */ 488 while (((ccscbctl = ahd_inb(ahd, CCSCBCTL)) & (CCARREN|CCSCBEN)) != 0) { 489 if ((ccscbctl & (CCSCBDIR|CCARREN)) == (CCSCBDIR|CCARREN)) { 490 if ((ccscbctl & ARRDONE) != 0) 491 break; 492 } else if ((ccscbctl & CCSCBDONE) != 0) 493 break; 494 aic_delay(200); 495 } 496 /* 497 * We leave the sequencer to cleanup in the case of DMA's to 498 * update the qoutfifo. In all other cases (DMA's to the 499 * chip or a push of an SCB from the COMPLETE_DMA_SCB list), 500 * we disable the DMA engine so that the sequencer will not 501 * attempt to handle the DMA completion. 502 */ 503 if ((ccscbctl & CCSCBDIR) != 0 || (ccscbctl & ARRDONE) != 0) 504 ahd_outb(ahd, CCSCBCTL, ccscbctl & ~(CCARREN|CCSCBEN)); 505 506 /* 507 * Complete any SCBs that just finished 508 * being DMA'ed into the qoutfifo. 509 */ 510 ahd_run_qoutfifo(ahd); 511 512 saved_scbptr = ahd_get_scbptr(ahd); 513 /* 514 * Manually update/complete any completed SCBs that are waiting to be 515 * DMA'ed back up to the host. 516 */ 517 scbid = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 518 while (!SCBID_IS_NULL(scbid)) { 519 uint8_t *hscb_ptr; 520 u_int i; 521 522 ahd_set_scbptr(ahd, scbid); 523 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 524 scb = ahd_lookup_scb(ahd, scbid); 525 if (scb == NULL) { 526 printf("%s: Warning - DMA-up and complete " 527 "SCB %d invalid\n", ahd_name(ahd), scbid); 528 AHD_CORRECTABLE_ERROR(ahd); 529 continue; 530 } 531 hscb_ptr = (uint8_t *)scb->hscb; 532 for (i = 0; i < sizeof(struct hardware_scb); i++) 533 *hscb_ptr++ = ahd_inb_scbram(ahd, SCB_BASE + i); 534 535 ahd_complete_scb(ahd, scb); 536 scbid = next_scbid; 537 } 538 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); 539 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL); 540 541 scbid = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD); 542 while (!SCBID_IS_NULL(scbid)) { 543 ahd_set_scbptr(ahd, scbid); 544 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 545 scb = ahd_lookup_scb(ahd, scbid); 546 if (scb == NULL) { 547 printf("%s: Warning - Complete Qfrz SCB %d invalid\n", 548 ahd_name(ahd), scbid); 549 AHD_CORRECTABLE_ERROR(ahd); 550 continue; 551 } 552 553 ahd_complete_scb(ahd, scb); 554 scbid = next_scbid; 555 } 556 ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL); 557 558 scbid = ahd_inw(ahd, COMPLETE_SCB_HEAD); 559 while (!SCBID_IS_NULL(scbid)) { 560 ahd_set_scbptr(ahd, scbid); 561 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 562 scb = ahd_lookup_scb(ahd, scbid); 563 if (scb == NULL) { 564 printf("%s: Warning - Complete SCB %d invalid\n", 565 ahd_name(ahd), scbid); 566 AHD_CORRECTABLE_ERROR(ahd); 567 continue; 568 } 569 570 ahd_complete_scb(ahd, scb); 571 scbid = next_scbid; 572 } 573 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); 574 575 /* 576 * Restore state. 577 */ 578 ahd_set_scbptr(ahd, saved_scbptr); 579 ahd_restore_modes(ahd, saved_modes); 580 ahd->flags |= AHD_UPDATE_PEND_CMDS; 581 } 582 583 /* 584 * Determine if an SCB for a packetized transaction 585 * is active in a FIFO. 586 */ 587 static int 588 ahd_scb_active_in_fifo(struct ahd_softc *ahd, struct scb *scb) 589 { 590 591 /* 592 * The FIFO is only active for our transaction if 593 * the SCBPTR matches the SCB's ID and the firmware 594 * has installed a handler for the FIFO or we have 595 * a pending SAVEPTRS or CFG4DATA interrupt. 596 */ 597 if (ahd_get_scbptr(ahd) != SCB_GET_TAG(scb) 598 || ((ahd_inb(ahd, LONGJMP_ADDR+1) & INVALID_ADDR) != 0 599 && (ahd_inb(ahd, SEQINTSRC) & (CFG4DATA|SAVEPTRS)) == 0)) 600 return (0); 601 602 return (1); 603 } 604 605 /* 606 * Run a data fifo to completion for a transaction we know 607 * has completed across the SCSI bus (good status has been 608 * received). We are already set to the correct FIFO mode 609 * on entry to this routine. 610 * 611 * This function attempts to operate exactly as the firmware 612 * would when running this FIFO. Care must be taken to update 613 * this routine any time the firmware's FIFO algorithm is 614 * changed. 615 */ 616 static void 617 ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb) 618 { 619 u_int seqintsrc; 620 621 seqintsrc = ahd_inb(ahd, SEQINTSRC); 622 if ((seqintsrc & CFG4DATA) != 0) { 623 uint32_t datacnt; 624 uint32_t sgptr; 625 626 /* 627 * Clear full residual flag. 628 */ 629 sgptr = ahd_inl_scbram(ahd, SCB_SGPTR) & ~SG_FULL_RESID; 630 ahd_outb(ahd, SCB_SGPTR, sgptr); 631 632 /* 633 * Load datacnt and address. 634 */ 635 datacnt = ahd_inl_scbram(ahd, SCB_DATACNT); 636 if ((datacnt & AHD_DMA_LAST_SEG) != 0) { 637 sgptr |= LAST_SEG; 638 ahd_outb(ahd, SG_STATE, 0); 639 } else 640 ahd_outb(ahd, SG_STATE, LOADING_NEEDED); 641 ahd_outq(ahd, HADDR, ahd_inq_scbram(ahd, SCB_DATAPTR)); 642 ahd_outl(ahd, HCNT, datacnt & AHD_SG_LEN_MASK); 643 ahd_outb(ahd, SG_CACHE_PRE, sgptr); 644 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN); 645 646 /* 647 * Initialize Residual Fields. 648 */ 649 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, datacnt >> 24); 650 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr & SG_PTR_MASK); 651 652 /* 653 * Mark the SCB as having a FIFO in use. 654 */ 655 ahd_outb(ahd, SCB_FIFO_USE_COUNT, 656 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) + 1); 657 658 /* 659 * Install a "fake" handler for this FIFO. 660 */ 661 ahd_outw(ahd, LONGJMP_ADDR, 0); 662 663 /* 664 * Notify the hardware that we have satisfied 665 * this sequencer interrupt. 666 */ 667 ahd_outb(ahd, CLRSEQINTSRC, CLRCFG4DATA); 668 } else if ((seqintsrc & SAVEPTRS) != 0) { 669 uint32_t sgptr; 670 uint32_t resid; 671 672 if ((ahd_inb(ahd, LONGJMP_ADDR+1)&INVALID_ADDR) != 0) { 673 /* 674 * Snapshot Save Pointers. All that 675 * is necessary to clear the snapshot 676 * is a CLRCHN. 677 */ 678 goto clrchn; 679 } 680 681 /* 682 * Disable S/G fetch so the DMA engine 683 * is available to future users. 684 */ 685 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) 686 ahd_outb(ahd, CCSGCTL, 0); 687 ahd_outb(ahd, SG_STATE, 0); 688 689 /* 690 * Flush the data FIFO. Strickly only 691 * necessary for Rev A parts. 692 */ 693 ahd_outb(ahd, DFCNTRL, ahd_inb(ahd, DFCNTRL) | FIFOFLUSH); 694 695 /* 696 * Calculate residual. 697 */ 698 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 699 resid = ahd_inl(ahd, SHCNT); 700 resid |= ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+3) << 24; 701 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, resid); 702 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG) == 0) { 703 /* 704 * Must back up to the correct S/G element. 705 * Typically this just means resetting our 706 * low byte to the offset in the SG_CACHE, 707 * but if we wrapped, we have to correct 708 * the other bytes of the sgptr too. 709 */ 710 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & 0x80) != 0 711 && (sgptr & 0x80) == 0) 712 sgptr -= 0x100; 713 sgptr &= ~0xFF; 714 sgptr |= ahd_inb(ahd, SG_CACHE_SHADOW) 715 & SG_ADDR_MASK; 716 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr); 717 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 3, 0); 718 } else if ((resid & AHD_SG_LEN_MASK) == 0) { 719 ahd_outb(ahd, SCB_RESIDUAL_SGPTR, 720 sgptr | SG_LIST_NULL); 721 } 722 /* 723 * Save Pointers. 724 */ 725 ahd_outq(ahd, SCB_DATAPTR, ahd_inq(ahd, SHADDR)); 726 ahd_outl(ahd, SCB_DATACNT, resid); 727 ahd_outl(ahd, SCB_SGPTR, sgptr); 728 ahd_outb(ahd, CLRSEQINTSRC, CLRSAVEPTRS); 729 ahd_outb(ahd, SEQIMODE, 730 ahd_inb(ahd, SEQIMODE) | ENSAVEPTRS); 731 /* 732 * If the data is to the SCSI bus, we are 733 * done, otherwise wait for FIFOEMP. 734 */ 735 if ((ahd_inb(ahd, DFCNTRL) & DIRECTION) != 0) 736 goto clrchn; 737 } else if ((ahd_inb(ahd, SG_STATE) & LOADING_NEEDED) != 0) { 738 uint32_t sgptr; 739 uint64_t data_addr; 740 uint32_t data_len; 741 u_int dfcntrl; 742 743 /* 744 * Disable S/G fetch so the DMA engine 745 * is available to future users. We won't 746 * be using the DMA engine to load segments. 747 */ 748 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) { 749 ahd_outb(ahd, CCSGCTL, 0); 750 ahd_outb(ahd, SG_STATE, LOADING_NEEDED); 751 } 752 753 /* 754 * Wait for the DMA engine to notice that the 755 * host transfer is enabled and that there is 756 * space in the S/G FIFO for new segments before 757 * loading more segments. 758 */ 759 if ((ahd_inb(ahd, DFSTATUS) & PRELOAD_AVAIL) != 0 760 && (ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) { 761 /* 762 * Determine the offset of the next S/G 763 * element to load. 764 */ 765 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 766 sgptr &= SG_PTR_MASK; 767 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 768 struct ahd_dma64_seg *sg; 769 770 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 771 data_addr = sg->addr; 772 data_len = sg->len; 773 sgptr += sizeof(*sg); 774 } else { 775 struct ahd_dma_seg *sg; 776 777 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 778 data_addr = sg->len & AHD_SG_HIGH_ADDR_MASK; 779 data_addr <<= 8; 780 data_addr |= sg->addr; 781 data_len = sg->len; 782 sgptr += sizeof(*sg); 783 } 784 785 /* 786 * Update residual information. 787 */ 788 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, data_len >> 24); 789 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr); 790 791 /* 792 * Load the S/G. 793 */ 794 if (data_len & AHD_DMA_LAST_SEG) { 795 sgptr |= LAST_SEG; 796 ahd_outb(ahd, SG_STATE, 0); 797 } 798 ahd_outq(ahd, HADDR, data_addr); 799 ahd_outl(ahd, HCNT, data_len & AHD_SG_LEN_MASK); 800 ahd_outb(ahd, SG_CACHE_PRE, sgptr & 0xFF); 801 802 /* 803 * Advertise the segment to the hardware. 804 */ 805 dfcntrl = ahd_inb(ahd, DFCNTRL)|PRELOADEN|HDMAEN; 806 if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) != 0) { 807 /* 808 * Use SCSIENWRDIS so that SCSIEN 809 * is never modified by this 810 * operation. 811 */ 812 dfcntrl |= SCSIENWRDIS; 813 } 814 ahd_outb(ahd, DFCNTRL, dfcntrl); 815 } 816 } else if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG_DONE) != 0) { 817 /* 818 * Transfer completed to the end of SG list 819 * and has flushed to the host. 820 */ 821 ahd_outb(ahd, SCB_SGPTR, 822 ahd_inb_scbram(ahd, SCB_SGPTR) | SG_LIST_NULL); 823 goto clrchn; 824 } else if ((ahd_inb(ahd, DFSTATUS) & FIFOEMP) != 0) { 825 clrchn: 826 /* 827 * Clear any handler for this FIFO, decrement 828 * the FIFO use count for the SCB, and release 829 * the FIFO. 830 */ 831 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 832 ahd_outb(ahd, SCB_FIFO_USE_COUNT, 833 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) - 1); 834 ahd_outb(ahd, DFFSXFRCTL, CLRCHN); 835 } 836 } 837 838 /* 839 * Look for entries in the QoutFIFO that have completed. 840 * The valid_tag completion field indicates the validity 841 * of the entry - the valid value toggles each time through 842 * the queue. We use the sg_status field in the completion 843 * entry to avoid referencing the hscb if the completion 844 * occurred with no errors and no residual. sg_status is 845 * a copy of the first byte (little endian) of the sgptr 846 * hscb field. 847 */ 848 void 849 ahd_run_qoutfifo(struct ahd_softc *ahd) 850 { 851 struct ahd_completion *completion; 852 struct scb *scb; 853 u_int scb_index; 854 855 if ((ahd->flags & AHD_RUNNING_QOUTFIFO) != 0) 856 panic("ahd_run_qoutfifo recursion"); 857 ahd->flags |= AHD_RUNNING_QOUTFIFO; 858 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD); 859 for (;;) { 860 completion = &ahd->qoutfifo[ahd->qoutfifonext]; 861 862 if (completion->valid_tag != ahd->qoutfifonext_valid_tag) 863 break; 864 865 scb_index = aic_le16toh(completion->tag); 866 scb = ahd_lookup_scb(ahd, scb_index); 867 if (scb == NULL) { 868 printf("%s: WARNING no command for scb %d " 869 "(cmdcmplt)\nQOUTPOS = %d\n", 870 ahd_name(ahd), scb_index, 871 ahd->qoutfifonext); 872 AHD_CORRECTABLE_ERROR(ahd); 873 ahd_dump_card_state(ahd); 874 } else if ((completion->sg_status & SG_STATUS_VALID) != 0) { 875 ahd_handle_scb_status(ahd, scb); 876 } else { 877 ahd_done(ahd, scb); 878 } 879 880 ahd->qoutfifonext = (ahd->qoutfifonext+1) & (AHD_QOUT_SIZE-1); 881 if (ahd->qoutfifonext == 0) 882 ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID; 883 } 884 ahd->flags &= ~AHD_RUNNING_QOUTFIFO; 885 } 886 887 /************************* Interrupt Handling *********************************/ 888 void 889 ahd_handle_hwerrint(struct ahd_softc *ahd) 890 { 891 /* 892 * Some catastrophic hardware error has occurred. 893 * Print it for the user and disable the controller. 894 */ 895 int i; 896 int error; 897 898 error = ahd_inb(ahd, ERROR); 899 for (i = 0; i < num_errors; i++) { 900 if ((error & ahd_hard_errors[i].errno) != 0) { 901 printf("%s: hwerrint, %s\n", 902 ahd_name(ahd), ahd_hard_errors[i].errmesg); 903 AHD_UNCORRECTABLE_ERROR(ahd); 904 } 905 } 906 907 ahd_dump_card_state(ahd); 908 panic("BRKADRINT"); 909 910 /* Tell everyone that this HBA is no longer available */ 911 ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, 912 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 913 CAM_NO_HBA); 914 915 /* Tell the system that this controller has gone away. */ 916 ahd_free(ahd); 917 } 918 919 void 920 ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat) 921 { 922 u_int seqintcode; 923 924 /* 925 * Save the sequencer interrupt code and clear the SEQINT 926 * bit. We will unpause the sequencer, if appropriate, 927 * after servicing the request. 928 */ 929 seqintcode = ahd_inb(ahd, SEQINTCODE); 930 ahd_outb(ahd, CLRINT, CLRSEQINT); 931 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { 932 /* 933 * Unpause the sequencer and let it clear 934 * SEQINT by writing NO_SEQINT to it. This 935 * will cause the sequencer to be paused again, 936 * which is the expected state of this routine. 937 */ 938 ahd_unpause(ahd); 939 while (!ahd_is_paused(ahd)) 940 ; 941 ahd_outb(ahd, CLRINT, CLRSEQINT); 942 } 943 ahd_update_modes(ahd); 944 #ifdef AHD_DEBUG 945 if ((ahd_debug & AHD_SHOW_MISC) != 0) 946 printf("%s: Handle Seqint Called for code %d\n", 947 ahd_name(ahd), seqintcode); 948 #endif 949 switch (seqintcode) { 950 case ENTERING_NONPACK: 951 { 952 struct scb *scb; 953 u_int scbid; 954 955 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 956 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 957 scbid = ahd_get_scbptr(ahd); 958 scb = ahd_lookup_scb(ahd, scbid); 959 if (scb == NULL) { 960 /* 961 * Somehow need to know if this 962 * is from a selection or reselection. 963 * From that, we can determine target 964 * ID so we at least have an I_T nexus. 965 */ 966 } else { 967 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); 968 ahd_outb(ahd, SAVED_LUN, scb->hscb->lun); 969 ahd_outb(ahd, SEQ_FLAGS, 0x0); 970 } 971 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0 972 && (ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { 973 /* 974 * Phase change after read stream with 975 * CRC error with P0 asserted on last 976 * packet. 977 */ 978 #ifdef AHD_DEBUG 979 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 980 printf("%s: Assuming LQIPHASE_NLQ with " 981 "P0 assertion\n", ahd_name(ahd)); 982 #endif 983 } 984 #ifdef AHD_DEBUG 985 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) 986 printf("%s: Entering NONPACK\n", ahd_name(ahd)); 987 #endif 988 break; 989 } 990 case INVALID_SEQINT: 991 printf("%s: Invalid Sequencer interrupt occurred.\n", 992 ahd_name(ahd)); 993 ahd_dump_card_state(ahd); 994 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 995 AHD_UNCORRECTABLE_ERROR(ahd); 996 break; 997 case STATUS_OVERRUN: 998 { 999 struct scb *scb; 1000 u_int scbid; 1001 1002 scbid = ahd_get_scbptr(ahd); 1003 scb = ahd_lookup_scb(ahd, scbid); 1004 if (scb != NULL) 1005 ahd_print_path(ahd, scb); 1006 else 1007 printf("%s: ", ahd_name(ahd)); 1008 printf("SCB %d Packetized Status Overrun", scbid); 1009 ahd_dump_card_state(ahd); 1010 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1011 AHD_UNCORRECTABLE_ERROR(ahd); 1012 break; 1013 } 1014 case CFG4ISTAT_INTR: 1015 { 1016 struct scb *scb; 1017 u_int scbid; 1018 1019 scbid = ahd_get_scbptr(ahd); 1020 scb = ahd_lookup_scb(ahd, scbid); 1021 if (scb == NULL) { 1022 ahd_dump_card_state(ahd); 1023 printf("CFG4ISTAT: Free SCB %d referenced", scbid); 1024 AHD_FATAL_ERROR(ahd); 1025 panic("For safety"); 1026 } 1027 ahd_outq(ahd, HADDR, scb->sense_busaddr); 1028 ahd_outw(ahd, HCNT, AHD_SENSE_BUFSIZE); 1029 ahd_outb(ahd, HCNT + 2, 0); 1030 ahd_outb(ahd, SG_CACHE_PRE, SG_LAST_SEG); 1031 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN); 1032 break; 1033 } 1034 case ILLEGAL_PHASE: 1035 { 1036 u_int bus_phase; 1037 1038 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1039 printf("%s: ILLEGAL_PHASE 0x%x\n", 1040 ahd_name(ahd), bus_phase); 1041 1042 switch (bus_phase) { 1043 case P_DATAOUT: 1044 case P_DATAIN: 1045 case P_DATAOUT_DT: 1046 case P_DATAIN_DT: 1047 case P_MESGOUT: 1048 case P_STATUS: 1049 case P_MESGIN: 1050 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1051 printf("%s: Issued Bus Reset.\n", ahd_name(ahd)); 1052 AHD_UNCORRECTABLE_ERROR(ahd); 1053 break; 1054 case P_COMMAND: 1055 { 1056 struct ahd_devinfo devinfo; 1057 struct scb *scb; 1058 struct ahd_tmode_tstate *tstate; 1059 u_int scbid; 1060 1061 /* 1062 * If a target takes us into the command phase 1063 * assume that it has been externally reset and 1064 * has thus lost our previous packetized negotiation 1065 * agreement. Since we have not sent an identify 1066 * message and may not have fully qualified the 1067 * connection, we change our command to TUR, assert 1068 * ATN and ABORT the task when we go to message in 1069 * phase. The OSM will see the REQUEUE_REQUEST 1070 * status and retry the command. 1071 */ 1072 scbid = ahd_get_scbptr(ahd); 1073 scb = ahd_lookup_scb(ahd, scbid); 1074 if (scb == NULL) { 1075 AHD_CORRECTABLE_ERROR(ahd); 1076 printf("Invalid phase with no valid SCB. " 1077 "Resetting bus.\n"); 1078 ahd_reset_channel(ahd, 'A', 1079 /*Initiate Reset*/TRUE); 1080 break; 1081 } 1082 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), 1083 SCB_GET_TARGET(ahd, scb), 1084 SCB_GET_LUN(scb), 1085 SCB_GET_CHANNEL(ahd, scb), 1086 ROLE_INITIATOR); 1087 ahd_fetch_transinfo(ahd, 1088 devinfo.channel, 1089 devinfo.our_scsiid, 1090 devinfo.target, 1091 &tstate); 1092 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 1093 AHD_TRANS_ACTIVE, /*paused*/TRUE); 1094 ahd_set_syncrate(ahd, &devinfo, /*period*/0, 1095 /*offset*/0, /*ppr_options*/0, 1096 AHD_TRANS_ACTIVE, /*paused*/TRUE); 1097 ahd_outb(ahd, SCB_CDB_STORE, 0); 1098 ahd_outb(ahd, SCB_CDB_STORE+1, 0); 1099 ahd_outb(ahd, SCB_CDB_STORE+2, 0); 1100 ahd_outb(ahd, SCB_CDB_STORE+3, 0); 1101 ahd_outb(ahd, SCB_CDB_STORE+4, 0); 1102 ahd_outb(ahd, SCB_CDB_STORE+5, 0); 1103 ahd_outb(ahd, SCB_CDB_LEN, 6); 1104 scb->hscb->control &= ~(TAG_ENB|SCB_TAG_TYPE); 1105 scb->hscb->control |= MK_MESSAGE; 1106 ahd_outb(ahd, SCB_CONTROL, scb->hscb->control); 1107 ahd_outb(ahd, MSG_OUT, HOST_MSG); 1108 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid); 1109 /* 1110 * The lun is 0, regardless of the SCB's lun 1111 * as we have not sent an identify message. 1112 */ 1113 ahd_outb(ahd, SAVED_LUN, 0); 1114 ahd_outb(ahd, SEQ_FLAGS, 0); 1115 ahd_assert_atn(ahd); 1116 scb->flags &= ~SCB_PACKETIZED; 1117 scb->flags |= SCB_ABORT|SCB_CMDPHASE_ABORT; 1118 ahd_freeze_devq(ahd, scb); 1119 aic_set_transaction_status(scb, CAM_REQUEUE_REQ); 1120 aic_freeze_scb(scb); 1121 1122 /* 1123 * Allow the sequencer to continue with 1124 * non-pack processing. 1125 */ 1126 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1127 ahd_outb(ahd, CLRLQOINT1, CLRLQOPHACHGINPKT); 1128 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 1129 ahd_outb(ahd, CLRLQOINT1, 0); 1130 } 1131 #ifdef AHD_DEBUG 1132 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1133 ahd_print_path(ahd, scb); 1134 AHD_CORRECTABLE_ERROR(ahd); 1135 printf("Unexpected command phase from " 1136 "packetized target\n"); 1137 } 1138 #endif 1139 break; 1140 } 1141 } 1142 break; 1143 } 1144 case CFG4OVERRUN: 1145 { 1146 struct scb *scb; 1147 u_int scb_index; 1148 1149 #ifdef AHD_DEBUG 1150 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1151 printf("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd), 1152 ahd_inb(ahd, MODE_PTR)); 1153 } 1154 #endif 1155 scb_index = ahd_get_scbptr(ahd); 1156 scb = ahd_lookup_scb(ahd, scb_index); 1157 if (scb == NULL) { 1158 /* 1159 * Attempt to transfer to an SCB that is 1160 * not outstanding. 1161 */ 1162 ahd_assert_atn(ahd); 1163 ahd_outb(ahd, MSG_OUT, HOST_MSG); 1164 ahd->msgout_buf[0] = MSG_ABORT_TASK; 1165 ahd->msgout_len = 1; 1166 ahd->msgout_index = 0; 1167 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1168 /* 1169 * Clear status received flag to prevent any 1170 * attempt to complete this bogus SCB. 1171 */ 1172 ahd_outb(ahd, SCB_CONTROL, 1173 ahd_inb_scbram(ahd, SCB_CONTROL) 1174 & ~STATUS_RCVD); 1175 } 1176 break; 1177 } 1178 case DUMP_CARD_STATE: 1179 { 1180 ahd_dump_card_state(ahd); 1181 break; 1182 } 1183 case PDATA_REINIT: 1184 { 1185 #ifdef AHD_DEBUG 1186 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1187 printf("%s: PDATA_REINIT - DFCNTRL = 0x%x " 1188 "SG_CACHE_SHADOW = 0x%x\n", 1189 ahd_name(ahd), ahd_inb(ahd, DFCNTRL), 1190 ahd_inb(ahd, SG_CACHE_SHADOW)); 1191 } 1192 #endif 1193 ahd_reinitialize_dataptrs(ahd); 1194 break; 1195 } 1196 case HOST_MSG_LOOP: 1197 { 1198 struct ahd_devinfo devinfo; 1199 1200 /* 1201 * The sequencer has encountered a message phase 1202 * that requires host assistance for completion. 1203 * While handling the message phase(s), we will be 1204 * notified by the sequencer after each byte is 1205 * transferred so we can track bus phase changes. 1206 * 1207 * If this is the first time we've seen a HOST_MSG_LOOP 1208 * interrupt, initialize the state of the host message 1209 * loop. 1210 */ 1211 ahd_fetch_devinfo(ahd, &devinfo); 1212 if (ahd->msg_type == MSG_TYPE_NONE) { 1213 struct scb *scb; 1214 u_int scb_index; 1215 u_int bus_phase; 1216 1217 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1218 if (bus_phase != P_MESGIN 1219 && bus_phase != P_MESGOUT) { 1220 printf("ahd_intr: HOST_MSG_LOOP bad " 1221 "phase 0x%x\n", bus_phase); 1222 AHD_CORRECTABLE_ERROR(ahd); 1223 /* 1224 * Probably transitioned to bus free before 1225 * we got here. Just punt the message. 1226 */ 1227 ahd_dump_card_state(ahd); 1228 ahd_clear_intstat(ahd); 1229 ahd_restart(ahd); 1230 return; 1231 } 1232 1233 scb_index = ahd_get_scbptr(ahd); 1234 scb = ahd_lookup_scb(ahd, scb_index); 1235 if (devinfo.role == ROLE_INITIATOR) { 1236 if (bus_phase == P_MESGOUT) 1237 ahd_setup_initiator_msgout(ahd, 1238 &devinfo, 1239 scb); 1240 else { 1241 ahd->msg_type = 1242 MSG_TYPE_INITIATOR_MSGIN; 1243 ahd->msgin_index = 0; 1244 } 1245 } 1246 #ifdef AHD_TARGET_MODE 1247 else { 1248 if (bus_phase == P_MESGOUT) { 1249 ahd->msg_type = 1250 MSG_TYPE_TARGET_MSGOUT; 1251 ahd->msgin_index = 0; 1252 } 1253 else 1254 ahd_setup_target_msgin(ahd, 1255 &devinfo, 1256 scb); 1257 } 1258 #endif 1259 } 1260 1261 ahd_handle_message_phase(ahd); 1262 break; 1263 } 1264 case NO_MATCH: 1265 { 1266 /* Ensure we don't leave the selection hardware on */ 1267 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 1268 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 1269 1270 printf("%s:%c:%d: no active SCB for reconnecting " 1271 "target - issuing BUS DEVICE RESET\n", 1272 ahd_name(ahd), 'A', ahd_inb(ahd, SELID) >> 4); 1273 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 1274 "REG0 == 0x%x ACCUM = 0x%x\n", 1275 ahd_inb(ahd, SAVED_SCSIID), ahd_inb(ahd, SAVED_LUN), 1276 ahd_inw(ahd, REG0), ahd_inb(ahd, ACCUM)); 1277 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 1278 "SINDEX == 0x%x\n", 1279 ahd_inb(ahd, SEQ_FLAGS), ahd_get_scbptr(ahd), 1280 ahd_find_busy_tcl(ahd, 1281 BUILD_TCL(ahd_inb(ahd, SAVED_SCSIID), 1282 ahd_inb(ahd, SAVED_LUN))), 1283 ahd_inw(ahd, SINDEX)); 1284 printf("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 1285 "SCB_CONTROL == 0x%x\n", 1286 ahd_inb(ahd, SELID), ahd_inb_scbram(ahd, SCB_SCSIID), 1287 ahd_inb_scbram(ahd, SCB_LUN), 1288 ahd_inb_scbram(ahd, SCB_CONTROL)); 1289 printf("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n", 1290 ahd_inb(ahd, SCSIBUS), ahd_inb(ahd, SCSISIGI)); 1291 printf("SXFRCTL0 == 0x%x\n", ahd_inb(ahd, SXFRCTL0)); 1292 printf("SEQCTL0 == 0x%x\n", ahd_inb(ahd, SEQCTL0)); 1293 ahd_dump_card_state(ahd); 1294 ahd->msgout_buf[0] = MSG_BUS_DEV_RESET; 1295 ahd->msgout_len = 1; 1296 ahd->msgout_index = 0; 1297 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1298 ahd_outb(ahd, MSG_OUT, HOST_MSG); 1299 ahd_assert_atn(ahd); 1300 break; 1301 } 1302 case PROTO_VIOLATION: 1303 { 1304 ahd_handle_proto_violation(ahd); 1305 break; 1306 } 1307 case IGN_WIDE_RES: 1308 { 1309 struct ahd_devinfo devinfo; 1310 1311 ahd_fetch_devinfo(ahd, &devinfo); 1312 ahd_handle_ign_wide_residue(ahd, &devinfo); 1313 break; 1314 } 1315 case BAD_PHASE: 1316 { 1317 u_int lastphase; 1318 1319 lastphase = ahd_inb(ahd, LASTPHASE); 1320 printf("%s:%c:%d: unknown scsi bus phase %x, " 1321 "lastphase = 0x%x. Attempting to continue\n", 1322 ahd_name(ahd), 'A', 1323 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), 1324 lastphase, ahd_inb(ahd, SCSISIGI)); 1325 AHD_CORRECTABLE_ERROR(ahd); 1326 break; 1327 } 1328 case MISSED_BUSFREE: 1329 { 1330 u_int lastphase; 1331 1332 lastphase = ahd_inb(ahd, LASTPHASE); 1333 printf("%s:%c:%d: Missed busfree. " 1334 "Lastphase = 0x%x, Curphase = 0x%x\n", 1335 ahd_name(ahd), 'A', 1336 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)), 1337 lastphase, ahd_inb(ahd, SCSISIGI)); 1338 AHD_CORRECTABLE_ERROR(ahd); 1339 ahd_restart(ahd); 1340 return; 1341 } 1342 case DATA_OVERRUN: 1343 { 1344 /* 1345 * When the sequencer detects an overrun, it 1346 * places the controller in "BITBUCKET" mode 1347 * and allows the target to complete its transfer. 1348 * Unfortunately, none of the counters get updated 1349 * when the controller is in this mode, so we have 1350 * no way of knowing how large the overrun was. 1351 */ 1352 struct scb *scb; 1353 u_int scbindex; 1354 #ifdef AHD_DEBUG 1355 u_int lastphase; 1356 #endif 1357 1358 scbindex = ahd_get_scbptr(ahd); 1359 scb = ahd_lookup_scb(ahd, scbindex); 1360 #ifdef AHD_DEBUG 1361 lastphase = ahd_inb(ahd, LASTPHASE); 1362 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1363 ahd_print_path(ahd, scb); 1364 printf("data overrun detected %s. Tag == 0x%x.\n", 1365 ahd_lookup_phase_entry(lastphase)->phasemsg, 1366 SCB_GET_TAG(scb)); 1367 ahd_print_path(ahd, scb); 1368 printf("%s seen Data Phase. Length = %ld. " 1369 "NumSGs = %d.\n", 1370 ahd_inb(ahd, SEQ_FLAGS) & DPHASE 1371 ? "Have" : "Haven't", 1372 aic_get_transfer_length(scb), scb->sg_count); 1373 ahd_dump_sglist(scb); 1374 } 1375 #endif 1376 1377 /* 1378 * Set this and it will take effect when the 1379 * target does a command complete. 1380 */ 1381 ahd_freeze_devq(ahd, scb); 1382 aic_set_transaction_status(scb, CAM_DATA_RUN_ERR); 1383 aic_freeze_scb(scb); 1384 break; 1385 } 1386 case MKMSG_FAILED: 1387 { 1388 struct ahd_devinfo devinfo; 1389 struct scb *scb; 1390 u_int scbid; 1391 1392 ahd_fetch_devinfo(ahd, &devinfo); 1393 printf("%s:%c:%d:%d: Attempt to issue message failed\n", 1394 ahd_name(ahd), devinfo.channel, devinfo.target, 1395 devinfo.lun); 1396 scbid = ahd_get_scbptr(ahd); 1397 scb = ahd_lookup_scb(ahd, scbid); 1398 AHD_CORRECTABLE_ERROR(ahd); 1399 if (scb != NULL 1400 && (scb->flags & SCB_RECOVERY_SCB) != 0) 1401 /* 1402 * Ensure that we didn't put a second instance of this 1403 * SCB into the QINFIFO. 1404 */ 1405 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 1406 SCB_GET_CHANNEL(ahd, scb), 1407 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1408 ROLE_INITIATOR, /*status*/0, 1409 SEARCH_REMOVE); 1410 ahd_outb(ahd, SCB_CONTROL, 1411 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE); 1412 break; 1413 } 1414 case TASKMGMT_FUNC_COMPLETE: 1415 { 1416 u_int scbid; 1417 struct scb *scb; 1418 1419 scbid = ahd_get_scbptr(ahd); 1420 scb = ahd_lookup_scb(ahd, scbid); 1421 if (scb != NULL) { 1422 u_int lun; 1423 u_int tag; 1424 cam_status error; 1425 1426 ahd_print_path(ahd, scb); 1427 printf("Task Management Func 0x%x Complete\n", 1428 scb->hscb->task_management); 1429 lun = CAM_LUN_WILDCARD; 1430 tag = SCB_LIST_NULL; 1431 1432 switch (scb->hscb->task_management) { 1433 case SIU_TASKMGMT_ABORT_TASK: 1434 tag = SCB_GET_TAG(scb); 1435 case SIU_TASKMGMT_ABORT_TASK_SET: 1436 case SIU_TASKMGMT_CLEAR_TASK_SET: 1437 lun = scb->hscb->lun; 1438 error = CAM_REQ_ABORTED; 1439 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 1440 'A', lun, tag, ROLE_INITIATOR, 1441 error); 1442 break; 1443 case SIU_TASKMGMT_LUN_RESET: 1444 lun = scb->hscb->lun; 1445 case SIU_TASKMGMT_TARGET_RESET: 1446 { 1447 struct ahd_devinfo devinfo; 1448 1449 ahd_scb_devinfo(ahd, &devinfo, scb); 1450 error = CAM_BDR_SENT; 1451 ahd_handle_devreset(ahd, &devinfo, lun, 1452 CAM_BDR_SENT, 1453 lun != CAM_LUN_WILDCARD 1454 ? "Lun Reset" 1455 : "Target Reset", 1456 /*verbose_level*/0); 1457 break; 1458 } 1459 default: 1460 panic("Unexpected TaskMgmt Func\n"); 1461 break; 1462 } 1463 } 1464 break; 1465 } 1466 case TASKMGMT_CMD_CMPLT_OKAY: 1467 { 1468 u_int scbid; 1469 struct scb *scb; 1470 1471 /* 1472 * An ABORT TASK TMF failed to be delivered before 1473 * the targeted command completed normally. 1474 */ 1475 scbid = ahd_get_scbptr(ahd); 1476 scb = ahd_lookup_scb(ahd, scbid); 1477 if (scb != NULL) { 1478 /* 1479 * Remove the second instance of this SCB from 1480 * the QINFIFO if it is still there. 1481 */ 1482 ahd_print_path(ahd, scb); 1483 printf("SCB completes before TMF\n"); 1484 /* 1485 * Handle losing the race. Wait until any 1486 * current selection completes. We will then 1487 * set the TMF back to zero in this SCB so that 1488 * the sequencer doesn't bother to issue another 1489 * sequencer interrupt for its completion. 1490 */ 1491 while ((ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0 1492 && (ahd_inb(ahd, SSTAT0) & SELDO) == 0 1493 && (ahd_inb(ahd, SSTAT1) & SELTO) == 0) 1494 ; 1495 ahd_outb(ahd, SCB_TASK_MANAGEMENT, 0); 1496 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 1497 SCB_GET_CHANNEL(ahd, scb), 1498 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 1499 ROLE_INITIATOR, /*status*/0, 1500 SEARCH_REMOVE); 1501 } 1502 break; 1503 } 1504 case TRACEPOINT0: 1505 case TRACEPOINT1: 1506 case TRACEPOINT2: 1507 case TRACEPOINT3: 1508 printf("%s: Tracepoint %d\n", ahd_name(ahd), 1509 seqintcode - TRACEPOINT0); 1510 break; 1511 case NO_SEQINT: 1512 break; 1513 case SAW_HWERR: 1514 ahd_handle_hwerrint(ahd); 1515 break; 1516 default: 1517 printf("%s: Unexpected SEQINTCODE %d\n", ahd_name(ahd), 1518 seqintcode); 1519 break; 1520 } 1521 /* 1522 * The sequencer is paused immediately on 1523 * a SEQINT, so we should restart it when 1524 * we're done. 1525 */ 1526 ahd_unpause(ahd); 1527 } 1528 1529 void 1530 ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat) 1531 { 1532 struct scb *scb; 1533 u_int status0; 1534 u_int status3; 1535 u_int status; 1536 u_int lqistat1; 1537 u_int lqostat0; 1538 u_int scbid; 1539 u_int busfreetime; 1540 1541 ahd_update_modes(ahd); 1542 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1543 1544 status3 = ahd_inb(ahd, SSTAT3) & (NTRAMPERR|OSRAMPERR); 1545 status0 = ahd_inb(ahd, SSTAT0) & (IOERR|OVERRUN|SELDI|SELDO); 1546 status = ahd_inb(ahd, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 1547 lqistat1 = ahd_inb(ahd, LQISTAT1); 1548 lqostat0 = ahd_inb(ahd, LQOSTAT0); 1549 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; 1550 if ((status0 & (SELDI|SELDO)) != 0) { 1551 u_int simode0; 1552 1553 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 1554 simode0 = ahd_inb(ahd, SIMODE0); 1555 status0 &= simode0 & (IOERR|OVERRUN|SELDI|SELDO); 1556 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1557 } 1558 scbid = ahd_get_scbptr(ahd); 1559 scb = ahd_lookup_scb(ahd, scbid); 1560 if (scb != NULL 1561 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1562 scb = NULL; 1563 1564 if ((status0 & IOERR) != 0) { 1565 u_int now_lvd; 1566 1567 now_lvd = ahd_inb(ahd, SBLKCTL) & ENAB40; 1568 printf("%s: Transceiver State Has Changed to %s mode\n", 1569 ahd_name(ahd), now_lvd ? "LVD" : "SE"); 1570 ahd_outb(ahd, CLRSINT0, CLRIOERR); 1571 /* 1572 * A change in I/O mode is equivalent to a bus reset. 1573 */ 1574 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1575 ahd_pause(ahd); 1576 ahd_setup_iocell_workaround(ahd); 1577 ahd_unpause(ahd); 1578 } else if ((status0 & OVERRUN) != 0) { 1579 printf("%s: SCSI offset overrun detected. Resetting bus.\n", 1580 ahd_name(ahd)); 1581 AHD_CORRECTABLE_ERROR(ahd); 1582 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1583 } else if ((status & SCSIRSTI) != 0) { 1584 printf("%s: Someone reset channel A\n", ahd_name(ahd)); 1585 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE); 1586 AHD_UNCORRECTABLE_ERROR(ahd); 1587 } else if ((status & SCSIPERR) != 0) { 1588 /* Make sure the sequencer is in a safe location. */ 1589 ahd_clear_critical_section(ahd); 1590 1591 ahd_handle_transmission_error(ahd); 1592 } else if (lqostat0 != 0) { 1593 printf("%s: lqostat0 == 0x%x!\n", ahd_name(ahd), lqostat0); 1594 ahd_outb(ahd, CLRLQOINT0, lqostat0); 1595 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) 1596 ahd_outb(ahd, CLRLQOINT1, 0); 1597 } else if ((status & SELTO) != 0) { 1598 u_int scbid; 1599 1600 /* Stop the selection */ 1601 ahd_outb(ahd, SCSISEQ0, 0); 1602 1603 /* Make sure the sequencer is in a safe location. */ 1604 ahd_clear_critical_section(ahd); 1605 1606 /* No more pending messages */ 1607 ahd_clear_msg_state(ahd); 1608 1609 /* Clear interrupt state */ 1610 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1611 1612 /* 1613 * Although the driver does not care about the 1614 * 'Selection in Progress' status bit, the busy 1615 * LED does. SELINGO is only cleared by a successful 1616 * selection, so we must manually clear it to insure 1617 * the LED turns off just incase no future successful 1618 * selections occur (e.g. no devices on the bus). 1619 */ 1620 ahd_outb(ahd, CLRSINT0, CLRSELINGO); 1621 1622 scbid = ahd_inw(ahd, WAITING_TID_HEAD); 1623 scb = ahd_lookup_scb(ahd, scbid); 1624 if (scb == NULL) { 1625 printf("%s: ahd_intr - referenced scb not " 1626 "valid during SELTO scb(0x%x)\n", 1627 ahd_name(ahd), scbid); 1628 ahd_dump_card_state(ahd); 1629 AHD_UNCORRECTABLE_ERROR(ahd); 1630 } else { 1631 struct ahd_devinfo devinfo; 1632 #ifdef AHD_DEBUG 1633 if ((ahd_debug & AHD_SHOW_SELTO) != 0) { 1634 ahd_print_path(ahd, scb); 1635 printf("Saw Selection Timeout for SCB 0x%x\n", 1636 scbid); 1637 } 1638 #endif 1639 ahd_scb_devinfo(ahd, &devinfo, scb); 1640 aic_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1641 ahd_freeze_devq(ahd, scb); 1642 1643 /* 1644 * Cancel any pending transactions on the device 1645 * now that it seems to be missing. This will 1646 * also revert us to async/narrow transfers until 1647 * we can renegotiate with the device. 1648 */ 1649 ahd_handle_devreset(ahd, &devinfo, 1650 CAM_LUN_WILDCARD, 1651 CAM_SEL_TIMEOUT, 1652 "Selection Timeout", 1653 /*verbose_level*/1); 1654 } 1655 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1656 ahd_iocell_first_selection(ahd); 1657 ahd_unpause(ahd); 1658 } else if ((status0 & (SELDI|SELDO)) != 0) { 1659 ahd_iocell_first_selection(ahd); 1660 ahd_unpause(ahd); 1661 } else if (status3 != 0) { 1662 printf("%s: SCSI Cell parity error SSTAT3 == 0x%x\n", 1663 ahd_name(ahd), status3); 1664 AHD_CORRECTABLE_ERROR(ahd); 1665 ahd_outb(ahd, CLRSINT3, status3); 1666 } else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) { 1667 /* Make sure the sequencer is in a safe location. */ 1668 ahd_clear_critical_section(ahd); 1669 1670 ahd_handle_lqiphase_error(ahd, lqistat1); 1671 } else if ((lqistat1 & LQICRCI_NLQ) != 0) { 1672 /* 1673 * This status can be delayed during some 1674 * streaming operations. The SCSIPHASE 1675 * handler has already dealt with this case 1676 * so just clear the error. 1677 */ 1678 ahd_outb(ahd, CLRLQIINT1, CLRLQICRCI_NLQ); 1679 } else if ((status & BUSFREE) != 0 1680 || (lqistat1 & LQOBUSFREE) != 0) { 1681 u_int lqostat1; 1682 int restart; 1683 int clear_fifo; 1684 int packetized; 1685 u_int mode; 1686 1687 /* 1688 * Clear our selection hardware as soon as possible. 1689 * We may have an entry in the waiting Q for this target, 1690 * that is affected by this busfree and we don't want to 1691 * go about selecting the target while we handle the event. 1692 */ 1693 ahd_outb(ahd, SCSISEQ0, 0); 1694 1695 /* Make sure the sequencer is in a safe location. */ 1696 ahd_clear_critical_section(ahd); 1697 1698 /* 1699 * Determine what we were up to at the time of 1700 * the busfree. 1701 */ 1702 mode = AHD_MODE_SCSI; 1703 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME; 1704 lqostat1 = ahd_inb(ahd, LQOSTAT1); 1705 switch (busfreetime) { 1706 case BUSFREE_DFF0: 1707 case BUSFREE_DFF1: 1708 { 1709 u_int scbid; 1710 struct scb *scb; 1711 1712 mode = busfreetime == BUSFREE_DFF0 1713 ? AHD_MODE_DFF0 : AHD_MODE_DFF1; 1714 ahd_set_modes(ahd, mode, mode); 1715 scbid = ahd_get_scbptr(ahd); 1716 scb = ahd_lookup_scb(ahd, scbid); 1717 if (scb == NULL) { 1718 printf("%s: Invalid SCB %d in DFF%d " 1719 "during unexpected busfree\n", 1720 ahd_name(ahd), scbid, mode); 1721 packetized = 0; 1722 AHD_CORRECTABLE_ERROR(ahd); 1723 } else 1724 packetized = (scb->flags & SCB_PACKETIZED) != 0; 1725 clear_fifo = 1; 1726 break; 1727 } 1728 case BUSFREE_LQO: 1729 clear_fifo = 0; 1730 packetized = 1; 1731 break; 1732 default: 1733 clear_fifo = 0; 1734 packetized = (lqostat1 & LQOBUSFREE) != 0; 1735 if (!packetized 1736 && ahd_inb(ahd, LASTPHASE) == P_BUSFREE 1737 && (ahd_inb(ahd, SSTAT0) & SELDI) == 0 1738 && ((ahd_inb(ahd, SSTAT0) & SELDO) == 0 1739 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) == 0)) 1740 /* 1741 * Assume packetized if we are not 1742 * on the bus in a non-packetized 1743 * capacity and any pending selection 1744 * was a packetized selection. 1745 */ 1746 packetized = 1; 1747 break; 1748 } 1749 1750 #ifdef AHD_DEBUG 1751 if ((ahd_debug & AHD_SHOW_MISC) != 0) 1752 printf("Saw Busfree. Busfreetime = 0x%x.\n", 1753 busfreetime); 1754 #endif 1755 /* 1756 * Busfrees that occur in non-packetized phases are 1757 * handled by the nonpkt_busfree handler. 1758 */ 1759 if (packetized && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) { 1760 restart = ahd_handle_pkt_busfree(ahd, busfreetime); 1761 } else { 1762 packetized = 0; 1763 restart = ahd_handle_nonpkt_busfree(ahd); 1764 } 1765 /* 1766 * Clear the busfree interrupt status. The setting of 1767 * the interrupt is a pulse, so in a perfect world, we 1768 * would not need to muck with the ENBUSFREE logic. This 1769 * would ensure that if the bus moves on to another 1770 * connection, busfree protection is still in force. If 1771 * BUSFREEREV is broken, however, we must manually clear 1772 * the ENBUSFREE if the busfree occurred during a non-pack 1773 * connection so that we don't get false positives during 1774 * future, packetized, connections. 1775 */ 1776 ahd_outb(ahd, CLRSINT1, CLRBUSFREE); 1777 if (packetized == 0 1778 && (ahd->bugs & AHD_BUSFREEREV_BUG) != 0) 1779 ahd_outb(ahd, SIMODE1, 1780 ahd_inb(ahd, SIMODE1) & ~ENBUSFREE); 1781 1782 if (clear_fifo) 1783 ahd_clear_fifo(ahd, mode); 1784 1785 ahd_clear_msg_state(ahd); 1786 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1787 if (restart) { 1788 ahd_restart(ahd); 1789 } else { 1790 ahd_unpause(ahd); 1791 } 1792 } else { 1793 printf("%s: Missing case in ahd_handle_scsiint. status = %x\n", 1794 ahd_name(ahd), status); 1795 ahd_dump_card_state(ahd); 1796 ahd_clear_intstat(ahd); 1797 ahd_unpause(ahd); 1798 } 1799 } 1800 1801 static void 1802 ahd_handle_transmission_error(struct ahd_softc *ahd) 1803 { 1804 struct scb *scb; 1805 u_int scbid; 1806 u_int lqistat1; 1807 u_int msg_out; 1808 u_int curphase; 1809 u_int lastphase; 1810 u_int perrdiag; 1811 u_int cur_col; 1812 int silent; 1813 1814 scb = NULL; 1815 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1816 lqistat1 = ahd_inb(ahd, LQISTAT1) & ~(LQIPHASE_LQ|LQIPHASE_NLQ); 1817 ahd_inb(ahd, LQISTAT2); 1818 if ((lqistat1 & (LQICRCI_NLQ|LQICRCI_LQ)) == 0 1819 && (ahd->bugs & AHD_NLQICRC_DELAYED_BUG) != 0) { 1820 u_int lqistate; 1821 1822 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 1823 lqistate = ahd_inb(ahd, LQISTATE); 1824 if ((lqistate >= 0x1E && lqistate <= 0x24) 1825 || (lqistate == 0x29)) { 1826 #ifdef AHD_DEBUG 1827 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) { 1828 printf("%s: NLQCRC found via LQISTATE\n", 1829 ahd_name(ahd)); 1830 } 1831 #endif 1832 lqistat1 |= LQICRCI_NLQ; 1833 } 1834 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1835 } 1836 1837 ahd_outb(ahd, CLRLQIINT1, lqistat1); 1838 lastphase = ahd_inb(ahd, LASTPHASE); 1839 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 1840 perrdiag = ahd_inb(ahd, PERRDIAG); 1841 msg_out = MSG_INITIATOR_DET_ERR; 1842 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR); 1843 1844 /* 1845 * Try to find the SCB associated with this error. 1846 */ 1847 silent = FALSE; 1848 if (lqistat1 == 0 1849 || (lqistat1 & LQICRCI_NLQ) != 0) { 1850 if ((lqistat1 & (LQICRCI_NLQ|LQIOVERI_NLQ)) != 0) 1851 ahd_set_active_fifo(ahd); 1852 scbid = ahd_get_scbptr(ahd); 1853 scb = ahd_lookup_scb(ahd, scbid); 1854 if (scb != NULL && SCB_IS_SILENT(scb)) 1855 silent = TRUE; 1856 } 1857 1858 cur_col = 0; 1859 if (silent == FALSE) { 1860 printf("%s: Transmission error detected\n", ahd_name(ahd)); 1861 ahd_lqistat1_print(lqistat1, &cur_col, 50); 1862 ahd_lastphase_print(lastphase, &cur_col, 50); 1863 ahd_scsisigi_print(curphase, &cur_col, 50); 1864 ahd_perrdiag_print(perrdiag, &cur_col, 50); 1865 printf("\n"); 1866 AHD_CORRECTABLE_ERROR(ahd); 1867 ahd_dump_card_state(ahd); 1868 } 1869 1870 if ((lqistat1 & (LQIOVERI_LQ|LQIOVERI_NLQ)) != 0) { 1871 if (silent == FALSE) { 1872 printf("%s: Gross protocol error during incoming " 1873 "packet. lqistat1 == 0x%x. Resetting bus.\n", 1874 ahd_name(ahd), lqistat1); 1875 AHD_UNCORRECTABLE_ERROR(ahd); 1876 } 1877 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1878 return; 1879 } else if ((lqistat1 & LQICRCI_LQ) != 0) { 1880 /* 1881 * A CRC error has been detected on an incoming LQ. 1882 * The bus is currently hung on the last ACK. 1883 * Hit LQIRETRY to release the last ack, and 1884 * wait for the sequencer to determine that ATNO 1885 * is asserted while in message out to take us 1886 * to our host message loop. No NONPACKREQ or 1887 * LQIPHASE type errors will occur in this 1888 * scenario. After this first LQIRETRY, the LQI 1889 * manager will be in ISELO where it will 1890 * happily sit until another packet phase begins. 1891 * Unexpected bus free detection is enabled 1892 * through any phases that occur after we release 1893 * this last ack until the LQI manager sees a 1894 * packet phase. This implies we may have to 1895 * ignore a perfectly valid "unexected busfree" 1896 * after our "initiator detected error" message is 1897 * sent. A busfree is the expected response after 1898 * we tell the target that it's L_Q was corrupted. 1899 * (SPI4R09 10.7.3.3.3) 1900 */ 1901 ahd_outb(ahd, LQCTL2, LQIRETRY); 1902 printf("LQIRetry for LQICRCI_LQ to release ACK\n"); 1903 AHD_CORRECTABLE_ERROR(ahd); 1904 } else if ((lqistat1 & LQICRCI_NLQ) != 0) { 1905 /* 1906 * We detected a CRC error in a NON-LQ packet. 1907 * The hardware has varying behavior in this situation 1908 * depending on whether this packet was part of a 1909 * stream or not. 1910 * 1911 * PKT by PKT mode: 1912 * The hardware has already acked the complete packet. 1913 * If the target honors our outstanding ATN condition, 1914 * we should be (or soon will be) in MSGOUT phase. 1915 * This will trigger the LQIPHASE_LQ status bit as the 1916 * hardware was expecting another LQ. Unexpected 1917 * busfree detection is enabled. Once LQIPHASE_LQ is 1918 * true (first entry into host message loop is much 1919 * the same), we must clear LQIPHASE_LQ and hit 1920 * LQIRETRY so the hardware is ready to handle 1921 * a future LQ. NONPACKREQ will not be asserted again 1922 * once we hit LQIRETRY until another packet is 1923 * processed. The target may either go busfree 1924 * or start another packet in response to our message. 1925 * 1926 * Read Streaming P0 asserted: 1927 * If we raise ATN and the target completes the entire 1928 * stream (P0 asserted during the last packet), the 1929 * hardware will ack all data and return to the ISTART 1930 * state. When the target reponds to our ATN condition, 1931 * LQIPHASE_LQ will be asserted. We should respond to 1932 * this with an LQIRETRY to prepare for any future 1933 * packets. NONPACKREQ will not be asserted again 1934 * once we hit LQIRETRY until another packet is 1935 * processed. The target may either go busfree or 1936 * start another packet in response to our message. 1937 * Busfree detection is enabled. 1938 * 1939 * Read Streaming P0 not asserted: 1940 * If we raise ATN and the target transitions to 1941 * MSGOUT in or after a packet where P0 is not 1942 * asserted, the hardware will assert LQIPHASE_NLQ. 1943 * We should respond to the LQIPHASE_NLQ with an 1944 * LQIRETRY. Should the target stay in a non-pkt 1945 * phase after we send our message, the hardware 1946 * will assert LQIPHASE_LQ. Recovery is then just as 1947 * listed above for the read streaming with P0 asserted. 1948 * Busfree detection is enabled. 1949 */ 1950 if (silent == FALSE) 1951 printf("LQICRC_NLQ\n"); 1952 if (scb == NULL) { 1953 printf("%s: No SCB valid for LQICRC_NLQ. " 1954 "Resetting bus\n", ahd_name(ahd)); 1955 AHD_UNCORRECTABLE_ERROR(ahd); 1956 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1957 return; 1958 } 1959 } else if ((lqistat1 & LQIBADLQI) != 0) { 1960 printf("Need to handle BADLQI!\n"); 1961 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 1962 return; 1963 } else if ((perrdiag & (PARITYERR|PREVPHASE)) == PARITYERR) { 1964 if ((curphase & ~P_DATAIN_DT) != 0) { 1965 /* Ack the byte. So we can continue. */ 1966 if (silent == FALSE) 1967 printf("Acking %s to clear perror\n", 1968 ahd_lookup_phase_entry(curphase)->phasemsg); 1969 ahd_inb(ahd, SCSIDAT); 1970 } 1971 1972 if (curphase == P_MESGIN) 1973 msg_out = MSG_PARITY_ERROR; 1974 } 1975 1976 /* 1977 * We've set the hardware to assert ATN if we 1978 * get a parity error on "in" phases, so all we 1979 * need to do is stuff the message buffer with 1980 * the appropriate message. "In" phases have set 1981 * mesg_out to something other than MSG_NOP. 1982 */ 1983 ahd->send_msg_perror = msg_out; 1984 if (scb != NULL && msg_out == MSG_INITIATOR_DET_ERR) 1985 scb->flags |= SCB_TRANSMISSION_ERROR; 1986 ahd_outb(ahd, MSG_OUT, HOST_MSG); 1987 ahd_outb(ahd, CLRINT, CLRSCSIINT); 1988 ahd_unpause(ahd); 1989 } 1990 1991 static void 1992 ahd_handle_lqiphase_error(struct ahd_softc *ahd, u_int lqistat1) 1993 { 1994 /* 1995 * Clear the sources of the interrupts. 1996 */ 1997 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 1998 ahd_outb(ahd, CLRLQIINT1, lqistat1); 1999 2000 /* 2001 * If the "illegal" phase changes were in response 2002 * to our ATN to flag a CRC error, AND we ended up 2003 * on packet boundaries, clear the error, restart the 2004 * LQI manager as appropriate, and go on our merry 2005 * way toward sending the message. Otherwise, reset 2006 * the bus to clear the error. 2007 */ 2008 ahd_set_active_fifo(ahd); 2009 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0 2010 && (ahd_inb(ahd, MDFFSTAT) & DLZERO) != 0) { 2011 if ((lqistat1 & LQIPHASE_LQ) != 0) { 2012 printf("LQIRETRY for LQIPHASE_LQ\n"); 2013 AHD_CORRECTABLE_ERROR(ahd); 2014 ahd_outb(ahd, LQCTL2, LQIRETRY); 2015 } else if ((lqistat1 & LQIPHASE_NLQ) != 0) { 2016 printf("LQIRETRY for LQIPHASE_NLQ\n"); 2017 AHD_CORRECTABLE_ERROR(ahd); 2018 ahd_outb(ahd, LQCTL2, LQIRETRY); 2019 } else 2020 panic("ahd_handle_lqiphase_error: No phase errors\n"); 2021 ahd_dump_card_state(ahd); 2022 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2023 ahd_unpause(ahd); 2024 } else { 2025 printf("Reseting Channel for LQI Phase error\n"); 2026 AHD_CORRECTABLE_ERROR(ahd); 2027 ahd_dump_card_state(ahd); 2028 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE); 2029 } 2030 } 2031 2032 /* 2033 * Packetized unexpected or expected busfree. 2034 * Entered in mode based on busfreetime. 2035 */ 2036 static int 2037 ahd_handle_pkt_busfree(struct ahd_softc *ahd, u_int busfreetime) 2038 { 2039 u_int lqostat1; 2040 2041 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 2042 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 2043 lqostat1 = ahd_inb(ahd, LQOSTAT1); 2044 if ((lqostat1 & LQOBUSFREE) != 0) { 2045 struct scb *scb; 2046 u_int scbid; 2047 u_int saved_scbptr; 2048 u_int waiting_h; 2049 u_int waiting_t; 2050 u_int next; 2051 2052 /* 2053 * The LQO manager detected an unexpected busfree 2054 * either: 2055 * 2056 * 1) During an outgoing LQ. 2057 * 2) After an outgoing LQ but before the first 2058 * REQ of the command packet. 2059 * 3) During an outgoing command packet. 2060 * 2061 * In all cases, CURRSCB is pointing to the 2062 * SCB that encountered the failure. Clean 2063 * up the queue, clear SELDO and LQOBUSFREE, 2064 * and allow the sequencer to restart the select 2065 * out at its lesure. 2066 */ 2067 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2068 scbid = ahd_inw(ahd, CURRSCB); 2069 scb = ahd_lookup_scb(ahd, scbid); 2070 if (scb == NULL) 2071 panic("SCB not valid during LQOBUSFREE"); 2072 /* 2073 * Clear the status. 2074 */ 2075 ahd_outb(ahd, CLRLQOINT1, CLRLQOBUSFREE); 2076 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) 2077 ahd_outb(ahd, CLRLQOINT1, 0); 2078 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 2079 ahd_flush_device_writes(ahd); 2080 ahd_outb(ahd, CLRSINT0, CLRSELDO); 2081 2082 /* 2083 * Return the LQO manager to its idle loop. It will 2084 * not do this automatically if the busfree occurs 2085 * after the first REQ of either the LQ or command 2086 * packet or between the LQ and command packet. 2087 */ 2088 ahd_outb(ahd, LQCTL2, ahd_inb(ahd, LQCTL2) | LQOTOIDLE); 2089 2090 /* 2091 * Update the waiting for selection queue so 2092 * we restart on the correct SCB. 2093 */ 2094 waiting_h = ahd_inw(ahd, WAITING_TID_HEAD); 2095 saved_scbptr = ahd_get_scbptr(ahd); 2096 if (waiting_h != scbid) { 2097 ahd_outw(ahd, WAITING_TID_HEAD, scbid); 2098 waiting_t = ahd_inw(ahd, WAITING_TID_TAIL); 2099 if (waiting_t == waiting_h) { 2100 ahd_outw(ahd, WAITING_TID_TAIL, scbid); 2101 next = SCB_LIST_NULL; 2102 } else { 2103 ahd_set_scbptr(ahd, waiting_h); 2104 next = ahd_inw_scbram(ahd, SCB_NEXT2); 2105 } 2106 ahd_set_scbptr(ahd, scbid); 2107 ahd_outw(ahd, SCB_NEXT2, next); 2108 } 2109 ahd_set_scbptr(ahd, saved_scbptr); 2110 if (scb->crc_retry_count < AHD_MAX_LQ_CRC_ERRORS) { 2111 if (SCB_IS_SILENT(scb) == FALSE) { 2112 ahd_print_path(ahd, scb); 2113 printf("Probable outgoing LQ CRC error. " 2114 "Retrying command\n"); 2115 AHD_CORRECTABLE_ERROR(ahd); 2116 } 2117 scb->crc_retry_count++; 2118 } else { 2119 aic_set_transaction_status(scb, CAM_UNCOR_PARITY); 2120 aic_freeze_scb(scb); 2121 ahd_freeze_devq(ahd, scb); 2122 } 2123 /* Return unpausing the sequencer. */ 2124 return (0); 2125 } else if ((ahd_inb(ahd, PERRDIAG) & PARITYERR) != 0) { 2126 /* 2127 * Ignore what are really parity errors that 2128 * occur on the last REQ of a free running 2129 * clock prior to going busfree. Some drives 2130 * do not properly active negate just before 2131 * going busfree resulting in a parity glitch. 2132 */ 2133 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR|CLRBUSFREE); 2134 #ifdef AHD_DEBUG 2135 if ((ahd_debug & AHD_SHOW_MASKED_ERRORS) != 0) 2136 printf("%s: Parity on last REQ detected " 2137 "during busfree phase.\n", 2138 ahd_name(ahd)); 2139 #endif 2140 /* Return unpausing the sequencer. */ 2141 return (0); 2142 } 2143 if (ahd->src_mode != AHD_MODE_SCSI) { 2144 u_int scbid; 2145 struct scb *scb; 2146 2147 scbid = ahd_get_scbptr(ahd); 2148 scb = ahd_lookup_scb(ahd, scbid); 2149 ahd_print_path(ahd, scb); 2150 printf("Unexpected PKT busfree condition\n"); 2151 AHD_UNCORRECTABLE_ERROR(ahd); 2152 ahd_dump_card_state(ahd); 2153 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 'A', 2154 SCB_GET_LUN(scb), SCB_GET_TAG(scb), 2155 ROLE_INITIATOR, CAM_UNEXP_BUSFREE); 2156 2157 /* Return restarting the sequencer. */ 2158 return (1); 2159 } 2160 printf("%s: Unexpected PKT busfree condition\n", ahd_name(ahd)); 2161 AHD_UNCORRECTABLE_ERROR(ahd); 2162 ahd_dump_card_state(ahd); 2163 /* Restart the sequencer. */ 2164 return (1); 2165 } 2166 2167 /* 2168 * Non-packetized unexpected or expected busfree. 2169 */ 2170 static int 2171 ahd_handle_nonpkt_busfree(struct ahd_softc *ahd) 2172 { 2173 struct ahd_devinfo devinfo; 2174 struct scb *scb; 2175 u_int lastphase; 2176 u_int saved_scsiid; 2177 u_int saved_lun; 2178 u_int target; 2179 u_int initiator_role_id; 2180 u_int scbid; 2181 u_int ppr_busfree; 2182 int printerror; 2183 2184 /* 2185 * Look at what phase we were last in. If its message out, 2186 * chances are pretty good that the busfree was in response 2187 * to one of our abort requests. 2188 */ 2189 lastphase = ahd_inb(ahd, LASTPHASE); 2190 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); 2191 saved_lun = ahd_inb(ahd, SAVED_LUN); 2192 target = SCSIID_TARGET(ahd, saved_scsiid); 2193 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 2194 ahd_compile_devinfo(&devinfo, initiator_role_id, 2195 target, saved_lun, 'A', ROLE_INITIATOR); 2196 printerror = 1; 2197 2198 scbid = ahd_get_scbptr(ahd); 2199 scb = ahd_lookup_scb(ahd, scbid); 2200 if (scb != NULL 2201 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 2202 scb = NULL; 2203 2204 ppr_busfree = (ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0; 2205 if (lastphase == P_MESGOUT) { 2206 u_int tag; 2207 2208 tag = SCB_LIST_NULL; 2209 if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT_TAG, TRUE) 2210 || ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT, TRUE)) { 2211 int found; 2212 int sent_msg; 2213 2214 if (scb == NULL) { 2215 ahd_print_devinfo(ahd, &devinfo); 2216 printf("Abort for unidentified " 2217 "connection completed.\n"); 2218 /* restart the sequencer. */ 2219 return (1); 2220 } 2221 sent_msg = ahd->msgout_buf[ahd->msgout_index - 1]; 2222 ahd_print_path(ahd, scb); 2223 printf("SCB %d - Abort%s Completed.\n", 2224 SCB_GET_TAG(scb), 2225 sent_msg == MSG_ABORT_TAG ? "" : " Tag"); 2226 2227 if (sent_msg == MSG_ABORT_TAG) 2228 tag = SCB_GET_TAG(scb); 2229 2230 if ((scb->flags & SCB_CMDPHASE_ABORT) != 0) { 2231 /* 2232 * This abort is in response to an 2233 * unexpected switch to command phase 2234 * for a packetized connection. Since 2235 * the identify message was never sent, 2236 * "saved lun" is 0. We really want to 2237 * abort only the SCB that encountered 2238 * this error, which could have a different 2239 * lun. The SCB will be retried so the OS 2240 * will see the UA after renegotiating to 2241 * packetized. 2242 */ 2243 tag = SCB_GET_TAG(scb); 2244 saved_lun = scb->hscb->lun; 2245 } 2246 found = ahd_abort_scbs(ahd, target, 'A', saved_lun, 2247 tag, ROLE_INITIATOR, 2248 CAM_REQ_ABORTED); 2249 printf("found == 0x%x\n", found); 2250 printerror = 0; 2251 } else if (ahd_sent_msg(ahd, AHDMSG_1B, 2252 MSG_BUS_DEV_RESET, TRUE)) { 2253 #ifdef __FreeBSD__ 2254 /* 2255 * Don't mark the user's request for this BDR 2256 * as completing with CAM_BDR_SENT. CAM3 2257 * specifies CAM_REQ_CMP. 2258 */ 2259 if (scb != NULL 2260 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 2261 && ahd_match_scb(ahd, scb, target, 'A', 2262 CAM_LUN_WILDCARD, SCB_LIST_NULL, 2263 ROLE_INITIATOR)) 2264 aic_set_transaction_status(scb, CAM_REQ_CMP); 2265 #endif 2266 ahd_handle_devreset(ahd, &devinfo, CAM_LUN_WILDCARD, 2267 CAM_BDR_SENT, "Bus Device Reset", 2268 /*verbose_level*/0); 2269 printerror = 0; 2270 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, FALSE) 2271 && ppr_busfree == 0) { 2272 struct ahd_initiator_tinfo *tinfo; 2273 struct ahd_tmode_tstate *tstate; 2274 2275 /* 2276 * PPR Rejected. 2277 * 2278 * If the previous negotiation was packetized, 2279 * this could be because the device has been 2280 * reset without our knowledge. Force our 2281 * current negotiation to async and retry the 2282 * negotiation. Otherwise retry the command 2283 * with non-ppr negotiation. 2284 */ 2285 #ifdef AHD_DEBUG 2286 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2287 printf("PPR negotiation rejected busfree.\n"); 2288 #endif 2289 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel, 2290 devinfo.our_scsiid, 2291 devinfo.target, &tstate); 2292 if ((tinfo->curr.ppr_options & MSG_EXT_PPR_IU_REQ)!=0) { 2293 ahd_set_width(ahd, &devinfo, 2294 MSG_EXT_WDTR_BUS_8_BIT, 2295 AHD_TRANS_CUR, 2296 /*paused*/TRUE); 2297 ahd_set_syncrate(ahd, &devinfo, 2298 /*period*/0, /*offset*/0, 2299 /*ppr_options*/0, 2300 AHD_TRANS_CUR, 2301 /*paused*/TRUE); 2302 /* 2303 * The expect PPR busfree handler below 2304 * will effect the retry and necessary 2305 * abort. 2306 */ 2307 } else { 2308 tinfo->curr.transport_version = 2; 2309 tinfo->goal.transport_version = 2; 2310 tinfo->goal.ppr_options = 0; 2311 /* 2312 * Remove any SCBs in the waiting for selection 2313 * queue that may also be for this target so 2314 * that command ordering is preserved. 2315 */ 2316 ahd_freeze_devq(ahd, scb); 2317 ahd_qinfifo_requeue_tail(ahd, scb); 2318 printerror = 0; 2319 } 2320 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, FALSE) 2321 && ppr_busfree == 0) { 2322 /* 2323 * Negotiation Rejected. Go-narrow and 2324 * retry command. 2325 */ 2326 #ifdef AHD_DEBUG 2327 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2328 printf("WDTR negotiation rejected busfree.\n"); 2329 #endif 2330 ahd_set_width(ahd, &devinfo, 2331 MSG_EXT_WDTR_BUS_8_BIT, 2332 AHD_TRANS_CUR|AHD_TRANS_GOAL, 2333 /*paused*/TRUE); 2334 /* 2335 * Remove any SCBs in the waiting for selection 2336 * queue that may also be for this target so that 2337 * command ordering is preserved. 2338 */ 2339 ahd_freeze_devq(ahd, scb); 2340 ahd_qinfifo_requeue_tail(ahd, scb); 2341 printerror = 0; 2342 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, FALSE) 2343 && ppr_busfree == 0) { 2344 /* 2345 * Negotiation Rejected. Go-async and 2346 * retry command. 2347 */ 2348 #ifdef AHD_DEBUG 2349 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2350 printf("SDTR negotiation rejected busfree.\n"); 2351 #endif 2352 ahd_set_syncrate(ahd, &devinfo, 2353 /*period*/0, /*offset*/0, 2354 /*ppr_options*/0, 2355 AHD_TRANS_CUR|AHD_TRANS_GOAL, 2356 /*paused*/TRUE); 2357 /* 2358 * Remove any SCBs in the waiting for selection 2359 * queue that may also be for this target so that 2360 * command ordering is preserved. 2361 */ 2362 ahd_freeze_devq(ahd, scb); 2363 ahd_qinfifo_requeue_tail(ahd, scb); 2364 printerror = 0; 2365 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_IDE_BUSFREE) != 0 2366 && ahd_sent_msg(ahd, AHDMSG_1B, 2367 MSG_INITIATOR_DET_ERR, TRUE)) { 2368 #ifdef AHD_DEBUG 2369 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2370 printf("Expected IDE Busfree\n"); 2371 #endif 2372 printerror = 0; 2373 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_QASREJ_BUSFREE) 2374 && ahd_sent_msg(ahd, AHDMSG_1B, 2375 MSG_MESSAGE_REJECT, TRUE)) { 2376 #ifdef AHD_DEBUG 2377 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2378 printf("Expected QAS Reject Busfree\n"); 2379 #endif 2380 printerror = 0; 2381 } 2382 } 2383 2384 /* 2385 * The busfree required flag is honored at the end of 2386 * the message phases. We check it last in case we 2387 * had to send some other message that caused a busfree. 2388 */ 2389 if (printerror != 0 2390 && (lastphase == P_MESGIN || lastphase == P_MESGOUT) 2391 && ((ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0)) { 2392 ahd_freeze_devq(ahd, scb); 2393 aic_set_transaction_status(scb, CAM_REQUEUE_REQ); 2394 aic_freeze_scb(scb); 2395 if ((ahd->msg_flags & MSG_FLAG_IU_REQ_CHANGED) != 0) { 2396 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 2397 SCB_GET_CHANNEL(ahd, scb), 2398 SCB_GET_LUN(scb), SCB_LIST_NULL, 2399 ROLE_INITIATOR, CAM_REQ_ABORTED); 2400 } else { 2401 #ifdef AHD_DEBUG 2402 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 2403 printf("PPR Negotiation Busfree.\n"); 2404 #endif 2405 ahd_done(ahd, scb); 2406 } 2407 printerror = 0; 2408 } 2409 if (printerror != 0) { 2410 int aborted; 2411 2412 aborted = 0; 2413 if (scb != NULL) { 2414 u_int tag; 2415 2416 if ((scb->hscb->control & TAG_ENB) != 0) 2417 tag = SCB_GET_TAG(scb); 2418 else 2419 tag = SCB_LIST_NULL; 2420 ahd_print_path(ahd, scb); 2421 aborted = ahd_abort_scbs(ahd, target, 'A', 2422 SCB_GET_LUN(scb), tag, 2423 ROLE_INITIATOR, 2424 CAM_UNEXP_BUSFREE); 2425 } else { 2426 /* 2427 * We had not fully identified this connection, 2428 * so we cannot abort anything. 2429 */ 2430 printf("%s: ", ahd_name(ahd)); 2431 } 2432 printf("Unexpected busfree %s, %d SCBs aborted, " 2433 "PRGMCNT == 0x%x\n", 2434 ahd_lookup_phase_entry(lastphase)->phasemsg, 2435 aborted, 2436 ahd_inw(ahd, PRGMCNT)); 2437 AHD_UNCORRECTABLE_ERROR(ahd); 2438 ahd_dump_card_state(ahd); 2439 if (lastphase != P_BUSFREE) 2440 ahd_force_renegotiation(ahd, &devinfo); 2441 } 2442 /* Always restart the sequencer. */ 2443 return (1); 2444 } 2445 2446 static void 2447 ahd_handle_proto_violation(struct ahd_softc *ahd) 2448 { 2449 struct ahd_devinfo devinfo; 2450 struct scb *scb; 2451 u_int scbid; 2452 u_int seq_flags; 2453 u_int curphase; 2454 u_int lastphase; 2455 int found; 2456 2457 ahd_fetch_devinfo(ahd, &devinfo); 2458 scbid = ahd_get_scbptr(ahd); 2459 scb = ahd_lookup_scb(ahd, scbid); 2460 seq_flags = ahd_inb(ahd, SEQ_FLAGS); 2461 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK; 2462 lastphase = ahd_inb(ahd, LASTPHASE); 2463 if ((seq_flags & NOT_IDENTIFIED) != 0) { 2464 /* 2465 * The reconnecting target either did not send an 2466 * identify message, or did, but we didn't find an SCB 2467 * to match. 2468 */ 2469 ahd_print_devinfo(ahd, &devinfo); 2470 printf("Target did not send an IDENTIFY message. " 2471 "LASTPHASE = 0x%x.\n", lastphase); 2472 AHD_UNCORRECTABLE_ERROR(ahd); 2473 scb = NULL; 2474 } else if (scb == NULL) { 2475 /* 2476 * We don't seem to have an SCB active for this 2477 * transaction. Print an error and reset the bus. 2478 */ 2479 ahd_print_devinfo(ahd, &devinfo); 2480 printf("No SCB found during protocol violation\n"); 2481 AHD_UNCORRECTABLE_ERROR(ahd); 2482 goto proto_violation_reset; 2483 } else { 2484 aic_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 2485 if ((seq_flags & NO_CDB_SENT) != 0) { 2486 ahd_print_path(ahd, scb); 2487 printf("No or incomplete CDB sent to device.\n"); 2488 AHD_UNCORRECTABLE_ERROR(ahd); 2489 } else if ((ahd_inb_scbram(ahd, SCB_CONTROL) 2490 & STATUS_RCVD) == 0) { 2491 /* 2492 * The target never bothered to provide status to 2493 * us prior to completing the command. Since we don't 2494 * know the disposition of this command, we must attempt 2495 * to abort it. Assert ATN and prepare to send an abort 2496 * message. 2497 */ 2498 ahd_print_path(ahd, scb); 2499 printf("Completed command without status.\n"); 2500 } else { 2501 ahd_print_path(ahd, scb); 2502 printf("Unknown protocol violation.\n"); 2503 AHD_UNCORRECTABLE_ERROR(ahd); 2504 ahd_dump_card_state(ahd); 2505 } 2506 } 2507 if ((lastphase & ~P_DATAIN_DT) == 0 2508 || lastphase == P_COMMAND) { 2509 proto_violation_reset: 2510 /* 2511 * Target either went directly to data 2512 * phase or didn't respond to our ATN. 2513 * The only safe thing to do is to blow 2514 * it away with a bus reset. 2515 */ 2516 found = ahd_reset_channel(ahd, 'A', TRUE); 2517 printf("%s: Issued Channel %c Bus Reset. " 2518 "%d SCBs aborted\n", ahd_name(ahd), 'A', found); 2519 AHD_UNCORRECTABLE_ERROR(ahd); 2520 } else { 2521 /* 2522 * Leave the selection hardware off in case 2523 * this abort attempt will affect yet to 2524 * be sent commands. 2525 */ 2526 ahd_outb(ahd, SCSISEQ0, 2527 ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 2528 ahd_assert_atn(ahd); 2529 ahd_outb(ahd, MSG_OUT, HOST_MSG); 2530 if (scb == NULL) { 2531 ahd_print_devinfo(ahd, &devinfo); 2532 ahd->msgout_buf[0] = MSG_ABORT_TASK; 2533 ahd->msgout_len = 1; 2534 ahd->msgout_index = 0; 2535 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2536 } else { 2537 ahd_print_path(ahd, scb); 2538 scb->flags |= SCB_ABORT; 2539 } 2540 printf("Protocol violation %s. Attempting to abort.\n", 2541 ahd_lookup_phase_entry(curphase)->phasemsg); 2542 AHD_UNCORRECTABLE_ERROR(ahd); 2543 } 2544 } 2545 2546 /* 2547 * Force renegotiation to occur the next time we initiate 2548 * a command to the current device. 2549 */ 2550 static void 2551 ahd_force_renegotiation(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 2552 { 2553 struct ahd_initiator_tinfo *targ_info; 2554 struct ahd_tmode_tstate *tstate; 2555 2556 #ifdef AHD_DEBUG 2557 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 2558 ahd_print_devinfo(ahd, devinfo); 2559 printf("Forcing renegotiation\n"); 2560 } 2561 #endif 2562 targ_info = ahd_fetch_transinfo(ahd, 2563 devinfo->channel, 2564 devinfo->our_scsiid, 2565 devinfo->target, 2566 &tstate); 2567 ahd_update_neg_request(ahd, devinfo, tstate, 2568 targ_info, AHD_NEG_IF_NON_ASYNC); 2569 } 2570 2571 #define AHD_MAX_STEPS 2000 2572 void 2573 ahd_clear_critical_section(struct ahd_softc *ahd) 2574 { 2575 ahd_mode_state saved_modes; 2576 int stepping; 2577 int steps; 2578 int first_instr; 2579 u_int simode0; 2580 u_int simode1; 2581 u_int simode3; 2582 u_int lqimode0; 2583 u_int lqimode1; 2584 u_int lqomode0; 2585 u_int lqomode1; 2586 2587 if (ahd->num_critical_sections == 0) 2588 return; 2589 2590 stepping = FALSE; 2591 steps = 0; 2592 first_instr = 0; 2593 simode0 = 0; 2594 simode1 = 0; 2595 simode3 = 0; 2596 lqimode0 = 0; 2597 lqimode1 = 0; 2598 lqomode0 = 0; 2599 lqomode1 = 0; 2600 saved_modes = ahd_save_modes(ahd); 2601 for (;;) { 2602 struct cs *cs; 2603 u_int seqaddr; 2604 u_int i; 2605 2606 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2607 seqaddr = ahd_inw(ahd, CURADDR); 2608 2609 cs = ahd->critical_sections; 2610 for (i = 0; i < ahd->num_critical_sections; i++, cs++) { 2611 2612 if (cs->begin < seqaddr && cs->end >= seqaddr) 2613 break; 2614 } 2615 2616 if (i == ahd->num_critical_sections) 2617 break; 2618 2619 if (steps > AHD_MAX_STEPS) { 2620 printf("%s: Infinite loop in critical section\n" 2621 "%s: First Instruction 0x%x now 0x%x\n", 2622 ahd_name(ahd), ahd_name(ahd), first_instr, 2623 seqaddr); 2624 AHD_FATAL_ERROR(ahd); 2625 ahd_dump_card_state(ahd); 2626 panic("critical section loop"); 2627 } 2628 2629 steps++; 2630 #ifdef AHD_DEBUG 2631 if ((ahd_debug & AHD_SHOW_MISC) != 0) 2632 printf("%s: Single stepping at 0x%x\n", ahd_name(ahd), 2633 seqaddr); 2634 #endif 2635 if (stepping == FALSE) { 2636 first_instr = seqaddr; 2637 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 2638 simode0 = ahd_inb(ahd, SIMODE0); 2639 simode3 = ahd_inb(ahd, SIMODE3); 2640 lqimode0 = ahd_inb(ahd, LQIMODE0); 2641 lqimode1 = ahd_inb(ahd, LQIMODE1); 2642 lqomode0 = ahd_inb(ahd, LQOMODE0); 2643 lqomode1 = ahd_inb(ahd, LQOMODE1); 2644 ahd_outb(ahd, SIMODE0, 0); 2645 ahd_outb(ahd, SIMODE3, 0); 2646 ahd_outb(ahd, LQIMODE0, 0); 2647 ahd_outb(ahd, LQIMODE1, 0); 2648 ahd_outb(ahd, LQOMODE0, 0); 2649 ahd_outb(ahd, LQOMODE1, 0); 2650 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2651 simode1 = ahd_inb(ahd, SIMODE1); 2652 /* 2653 * We don't clear ENBUSFREE. Unfortunately 2654 * we cannot re-enable busfree detection within 2655 * the current connection, so we must leave it 2656 * on while single stepping. 2657 */ 2658 ahd_outb(ahd, SIMODE1, simode1 & ENBUSFREE); 2659 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) | STEP); 2660 stepping = TRUE; 2661 } 2662 ahd_outb(ahd, CLRSINT1, CLRBUSFREE); 2663 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2664 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 2665 ahd_outb(ahd, HCNTRL, ahd->unpause); 2666 while (!ahd_is_paused(ahd)) 2667 aic_delay(200); 2668 ahd_update_modes(ahd); 2669 } 2670 if (stepping) { 2671 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 2672 ahd_outb(ahd, SIMODE0, simode0); 2673 ahd_outb(ahd, SIMODE3, simode3); 2674 ahd_outb(ahd, LQIMODE0, lqimode0); 2675 ahd_outb(ahd, LQIMODE1, lqimode1); 2676 ahd_outb(ahd, LQOMODE0, lqomode0); 2677 ahd_outb(ahd, LQOMODE1, lqomode1); 2678 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 2679 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP); 2680 ahd_outb(ahd, SIMODE1, simode1); 2681 /* 2682 * SCSIINT seems to glitch occasionally when 2683 * the interrupt masks are restored. Clear SCSIINT 2684 * one more time so that only persistent errors 2685 * are seen as a real interrupt. 2686 */ 2687 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2688 } 2689 ahd_restore_modes(ahd, saved_modes); 2690 } 2691 2692 /* 2693 * Clear any pending interrupt status. 2694 */ 2695 void 2696 ahd_clear_intstat(struct ahd_softc *ahd) 2697 { 2698 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 2699 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 2700 /* Clear any interrupt conditions this may have caused */ 2701 ahd_outb(ahd, CLRLQIINT0, CLRLQIATNQAS|CLRLQICRCT1|CLRLQICRCT2 2702 |CLRLQIBADLQT|CLRLQIATNLQ|CLRLQIATNCMD); 2703 ahd_outb(ahd, CLRLQIINT1, CLRLQIPHASE_LQ|CLRLQIPHASE_NLQ|CLRLIQABORT 2704 |CLRLQICRCI_LQ|CLRLQICRCI_NLQ|CLRLQIBADLQI 2705 |CLRLQIOVERI_LQ|CLRLQIOVERI_NLQ|CLRNONPACKREQ); 2706 ahd_outb(ahd, CLRLQOINT0, CLRLQOTARGSCBPERR|CLRLQOSTOPT2|CLRLQOATNLQ 2707 |CLRLQOATNPKT|CLRLQOTCRC); 2708 ahd_outb(ahd, CLRLQOINT1, CLRLQOINITSCBPERR|CLRLQOSTOPI2|CLRLQOBADQAS 2709 |CLRLQOBUSFREE|CLRLQOPHACHGINPKT); 2710 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) { 2711 ahd_outb(ahd, CLRLQOINT0, 0); 2712 ahd_outb(ahd, CLRLQOINT1, 0); 2713 } 2714 ahd_outb(ahd, CLRSINT3, CLRNTRAMPERR|CLROSRAMPERR); 2715 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 2716 |CLRBUSFREE|CLRSCSIPERR|CLRREQINIT); 2717 ahd_outb(ahd, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO 2718 |CLRIOERR|CLROVERRUN); 2719 ahd_outb(ahd, CLRINT, CLRSCSIINT); 2720 } 2721 2722 /**************************** Debugging Routines ******************************/ 2723 #ifdef AHD_DEBUG 2724 uint32_t ahd_debug = AHD_DEBUG_OPTS; 2725 #endif 2726 void 2727 ahd_print_scb(struct scb *scb) 2728 { 2729 struct hardware_scb *hscb; 2730 int i; 2731 2732 hscb = scb->hscb; 2733 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 2734 (void *)scb, 2735 hscb->control, 2736 hscb->scsiid, 2737 hscb->lun, 2738 hscb->cdb_len); 2739 printf("Shared Data: "); 2740 for (i = 0; i < sizeof(hscb->shared_data.idata.cdb); i++) 2741 printf("%#02x", hscb->shared_data.idata.cdb[i]); 2742 printf(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n", 2743 (uint32_t)((aic_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF), 2744 (uint32_t)(aic_le64toh(hscb->dataptr) & 0xFFFFFFFF), 2745 aic_le32toh(hscb->datacnt), 2746 aic_le32toh(hscb->sgptr), 2747 SCB_GET_TAG(scb)); 2748 ahd_dump_sglist(scb); 2749 } 2750 2751 void 2752 ahd_dump_sglist(struct scb *scb) 2753 { 2754 int i; 2755 2756 if (scb->sg_count > 0) { 2757 if ((scb->ahd_softc->flags & AHD_64BIT_ADDRESSING) != 0) { 2758 struct ahd_dma64_seg *sg_list; 2759 2760 sg_list = (struct ahd_dma64_seg*)scb->sg_list; 2761 for (i = 0; i < scb->sg_count; i++) { 2762 uint64_t addr; 2763 2764 addr = aic_le64toh(sg_list[i].addr); 2765 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n", 2766 i, 2767 (uint32_t)((addr >> 32) & 0xFFFFFFFF), 2768 (uint32_t)(addr & 0xFFFFFFFF), 2769 sg_list[i].len & AHD_SG_LEN_MASK, 2770 (sg_list[i].len & AHD_DMA_LAST_SEG) 2771 ? " Last" : ""); 2772 } 2773 } else { 2774 struct ahd_dma_seg *sg_list; 2775 2776 sg_list = (struct ahd_dma_seg*)scb->sg_list; 2777 for (i = 0; i < scb->sg_count; i++) { 2778 uint32_t len; 2779 2780 len = aic_le32toh(sg_list[i].len); 2781 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n", 2782 i, 2783 (len & AHD_SG_HIGH_ADDR_MASK) >> 24, 2784 aic_le32toh(sg_list[i].addr), 2785 len & AHD_SG_LEN_MASK, 2786 len & AHD_DMA_LAST_SEG ? " Last" : ""); 2787 } 2788 } 2789 } 2790 } 2791 2792 /************************* Transfer Negotiation *******************************/ 2793 /* 2794 * Allocate per target mode instance (ID we respond to as a target) 2795 * transfer negotiation data structures. 2796 */ 2797 static struct ahd_tmode_tstate * 2798 ahd_alloc_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel) 2799 { 2800 struct ahd_tmode_tstate *master_tstate; 2801 struct ahd_tmode_tstate *tstate; 2802 int i; 2803 2804 master_tstate = ahd->enabled_targets[ahd->our_id]; 2805 if (ahd->enabled_targets[scsi_id] != NULL 2806 && ahd->enabled_targets[scsi_id] != master_tstate) 2807 panic("%s: ahd_alloc_tstate - Target already allocated", 2808 ahd_name(ahd)); 2809 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT); 2810 if (tstate == NULL) 2811 return (NULL); 2812 2813 /* 2814 * If we have allocated a master tstate, copy user settings from 2815 * the master tstate (taken from SRAM or the EEPROM) for this 2816 * channel, but reset our current and goal settings to async/narrow 2817 * until an initiator talks to us. 2818 */ 2819 if (master_tstate != NULL) { 2820 memcpy(tstate, master_tstate, sizeof(*tstate)); 2821 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 2822 for (i = 0; i < 16; i++) { 2823 memset(&tstate->transinfo[i].curr, 0, 2824 sizeof(tstate->transinfo[i].curr)); 2825 memset(&tstate->transinfo[i].goal, 0, 2826 sizeof(tstate->transinfo[i].goal)); 2827 } 2828 } else 2829 memset(tstate, 0, sizeof(*tstate)); 2830 ahd->enabled_targets[scsi_id] = tstate; 2831 return (tstate); 2832 } 2833 2834 #ifdef AHD_TARGET_MODE 2835 /* 2836 * Free per target mode instance (ID we respond to as a target) 2837 * transfer negotiation data structures. 2838 */ 2839 static void 2840 ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force) 2841 { 2842 struct ahd_tmode_tstate *tstate; 2843 2844 /* 2845 * Don't clean up our "master" tstate. 2846 * It has our default user settings. 2847 */ 2848 if (scsi_id == ahd->our_id 2849 && force == FALSE) 2850 return; 2851 2852 tstate = ahd->enabled_targets[scsi_id]; 2853 if (tstate != NULL) 2854 free(tstate, M_DEVBUF); 2855 ahd->enabled_targets[scsi_id] = NULL; 2856 } 2857 #endif 2858 2859 /* 2860 * Called when we have an active connection to a target on the bus, 2861 * this function finds the nearest period to the input period limited 2862 * by the capabilities of the bus connectivity of and sync settings for 2863 * the target. 2864 */ 2865 void 2866 ahd_devlimited_syncrate(struct ahd_softc *ahd, 2867 struct ahd_initiator_tinfo *tinfo, 2868 u_int *period, u_int *ppr_options, role_t role) 2869 { 2870 struct ahd_transinfo *transinfo; 2871 u_int maxsync; 2872 2873 if ((ahd_inb(ahd, SBLKCTL) & ENAB40) != 0 2874 && (ahd_inb(ahd, SSTAT2) & EXP_ACTIVE) == 0) { 2875 maxsync = AHD_SYNCRATE_PACED; 2876 } else { 2877 maxsync = AHD_SYNCRATE_ULTRA; 2878 /* Can't do DT related options on an SE bus */ 2879 *ppr_options &= MSG_EXT_PPR_QAS_REQ; 2880 } 2881 /* 2882 * Never allow a value higher than our current goal 2883 * period otherwise we may allow a target initiated 2884 * negotiation to go above the limit as set by the 2885 * user. In the case of an initiator initiated 2886 * sync negotiation, we limit based on the user 2887 * setting. This allows the system to still accept 2888 * incoming negotiations even if target initiated 2889 * negotiation is not performed. 2890 */ 2891 if (role == ROLE_TARGET) 2892 transinfo = &tinfo->user; 2893 else 2894 transinfo = &tinfo->goal; 2895 *ppr_options &= (transinfo->ppr_options|MSG_EXT_PPR_PCOMP_EN); 2896 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 2897 maxsync = MAX(maxsync, AHD_SYNCRATE_ULTRA2); 2898 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2899 } 2900 if (transinfo->period == 0) { 2901 *period = 0; 2902 *ppr_options = 0; 2903 } else { 2904 *period = MAX(*period, transinfo->period); 2905 ahd_find_syncrate(ahd, period, ppr_options, maxsync); 2906 } 2907 } 2908 2909 /* 2910 * Look up the valid period to SCSIRATE conversion in our table. 2911 * Return the period and offset that should be sent to the target 2912 * if this was the beginning of an SDTR. 2913 */ 2914 void 2915 ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 2916 u_int *ppr_options, u_int maxsync) 2917 { 2918 if (*period < maxsync) 2919 *period = maxsync; 2920 2921 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) != 0 2922 && *period > AHD_SYNCRATE_MIN_DT) 2923 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2924 2925 if (*period > AHD_SYNCRATE_MIN) 2926 *period = 0; 2927 2928 /* Honor PPR option conformance rules. */ 2929 if (*period > AHD_SYNCRATE_PACED) 2930 *ppr_options &= ~MSG_EXT_PPR_RTI; 2931 2932 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0) 2933 *ppr_options &= (MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_QAS_REQ); 2934 2935 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0) 2936 *ppr_options &= MSG_EXT_PPR_QAS_REQ; 2937 2938 /* Skip all PACED only entries if IU is not available */ 2939 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0 2940 && *period < AHD_SYNCRATE_DT) 2941 *period = AHD_SYNCRATE_DT; 2942 2943 /* Skip all DT only entries if DT is not available */ 2944 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 2945 && *period < AHD_SYNCRATE_ULTRA2) 2946 *period = AHD_SYNCRATE_ULTRA2; 2947 } 2948 2949 /* 2950 * Truncate the given synchronous offset to a value the 2951 * current adapter type and syncrate are capable of. 2952 */ 2953 void 2954 ahd_validate_offset(struct ahd_softc *ahd, 2955 struct ahd_initiator_tinfo *tinfo, 2956 u_int period, u_int *offset, int wide, 2957 role_t role) 2958 { 2959 u_int maxoffset; 2960 2961 /* Limit offset to what we can do */ 2962 if (period == 0) 2963 maxoffset = 0; 2964 else if (period <= AHD_SYNCRATE_PACED) { 2965 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) 2966 maxoffset = MAX_OFFSET_PACED_BUG; 2967 else 2968 maxoffset = MAX_OFFSET_PACED; 2969 } else 2970 maxoffset = MAX_OFFSET_NON_PACED; 2971 *offset = MIN(*offset, maxoffset); 2972 if (tinfo != NULL) { 2973 if (role == ROLE_TARGET) 2974 *offset = MIN(*offset, tinfo->user.offset); 2975 else 2976 *offset = MIN(*offset, tinfo->goal.offset); 2977 } 2978 } 2979 2980 /* 2981 * Truncate the given transfer width parameter to a value the 2982 * current adapter type is capable of. 2983 */ 2984 void 2985 ahd_validate_width(struct ahd_softc *ahd, struct ahd_initiator_tinfo *tinfo, 2986 u_int *bus_width, role_t role) 2987 { 2988 switch (*bus_width) { 2989 default: 2990 if (ahd->features & AHD_WIDE) { 2991 /* Respond Wide */ 2992 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 2993 break; 2994 } 2995 /* FALLTHROUGH */ 2996 case MSG_EXT_WDTR_BUS_8_BIT: 2997 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 2998 break; 2999 } 3000 if (tinfo != NULL) { 3001 if (role == ROLE_TARGET) 3002 *bus_width = MIN(tinfo->user.width, *bus_width); 3003 else 3004 *bus_width = MIN(tinfo->goal.width, *bus_width); 3005 } 3006 } 3007 3008 /* 3009 * Update the bitmask of targets for which the controller should 3010 * negotiate with at the next convenient opportunity. This currently 3011 * means the next time we send the initial identify messages for 3012 * a new transaction. 3013 */ 3014 int 3015 ahd_update_neg_request(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3016 struct ahd_tmode_tstate *tstate, 3017 struct ahd_initiator_tinfo *tinfo, ahd_neg_type neg_type) 3018 { 3019 u_int auto_negotiate_orig; 3020 3021 auto_negotiate_orig = tstate->auto_negotiate; 3022 if (neg_type == AHD_NEG_ALWAYS) { 3023 /* 3024 * Force our "current" settings to be 3025 * unknown so that unless a bus reset 3026 * occurs the need to renegotiate is 3027 * recorded persistently. 3028 */ 3029 if ((ahd->features & AHD_WIDE) != 0) 3030 tinfo->curr.width = AHD_WIDTH_UNKNOWN; 3031 tinfo->curr.period = AHD_PERIOD_UNKNOWN; 3032 tinfo->curr.offset = AHD_OFFSET_UNKNOWN; 3033 } 3034 if (tinfo->curr.period != tinfo->goal.period 3035 || tinfo->curr.width != tinfo->goal.width 3036 || tinfo->curr.offset != tinfo->goal.offset 3037 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 3038 || (neg_type == AHD_NEG_IF_NON_ASYNC 3039 && (tinfo->goal.offset != 0 3040 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 3041 || tinfo->goal.ppr_options != 0))) 3042 tstate->auto_negotiate |= devinfo->target_mask; 3043 else 3044 tstate->auto_negotiate &= ~devinfo->target_mask; 3045 3046 return (auto_negotiate_orig != tstate->auto_negotiate); 3047 } 3048 3049 /* 3050 * Update the user/goal/curr tables of synchronous negotiation 3051 * parameters as well as, in the case of a current or active update, 3052 * any data structures on the host controller. In the case of an 3053 * active update, the specified target is currently talking to us on 3054 * the bus, so the transfer parameter update must take effect 3055 * immediately. 3056 */ 3057 void 3058 ahd_set_syncrate(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3059 u_int period, u_int offset, u_int ppr_options, 3060 u_int type, int paused) 3061 { 3062 struct ahd_initiator_tinfo *tinfo; 3063 struct ahd_tmode_tstate *tstate; 3064 u_int old_period; 3065 u_int old_offset; 3066 u_int old_ppr; 3067 int active; 3068 int update_needed; 3069 3070 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; 3071 update_needed = 0; 3072 3073 if (period == 0 || offset == 0) { 3074 period = 0; 3075 offset = 0; 3076 } 3077 3078 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3079 devinfo->target, &tstate); 3080 3081 if ((type & AHD_TRANS_USER) != 0) { 3082 tinfo->user.period = period; 3083 tinfo->user.offset = offset; 3084 tinfo->user.ppr_options = ppr_options; 3085 } 3086 3087 if ((type & AHD_TRANS_GOAL) != 0) { 3088 tinfo->goal.period = period; 3089 tinfo->goal.offset = offset; 3090 tinfo->goal.ppr_options = ppr_options; 3091 } 3092 3093 old_period = tinfo->curr.period; 3094 old_offset = tinfo->curr.offset; 3095 old_ppr = tinfo->curr.ppr_options; 3096 3097 if ((type & AHD_TRANS_CUR) != 0 3098 && (old_period != period 3099 || old_offset != offset 3100 || old_ppr != ppr_options)) { 3101 update_needed++; 3102 3103 tinfo->curr.period = period; 3104 tinfo->curr.offset = offset; 3105 tinfo->curr.ppr_options = ppr_options; 3106 3107 ahd_send_async(ahd, devinfo->channel, devinfo->target, 3108 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 3109 if (bootverbose) { 3110 if (offset != 0) { 3111 int options; 3112 3113 printf("%s: target %d synchronous with " 3114 "period = 0x%x, offset = 0x%x", 3115 ahd_name(ahd), devinfo->target, 3116 period, offset); 3117 options = 0; 3118 if ((ppr_options & MSG_EXT_PPR_RD_STRM) != 0) { 3119 printf("(RDSTRM"); 3120 options++; 3121 } 3122 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) { 3123 printf("%s", options ? "|DT" : "(DT"); 3124 options++; 3125 } 3126 if ((ppr_options & MSG_EXT_PPR_IU_REQ) != 0) { 3127 printf("%s", options ? "|IU" : "(IU"); 3128 options++; 3129 } 3130 if ((ppr_options & MSG_EXT_PPR_RTI) != 0) { 3131 printf("%s", options ? "|RTI" : "(RTI"); 3132 options++; 3133 } 3134 if ((ppr_options & MSG_EXT_PPR_QAS_REQ) != 0) { 3135 printf("%s", options ? "|QAS" : "(QAS"); 3136 options++; 3137 } 3138 if (options != 0) 3139 printf(")\n"); 3140 else 3141 printf("\n"); 3142 } else { 3143 printf("%s: target %d using " 3144 "asynchronous transfers%s\n", 3145 ahd_name(ahd), devinfo->target, 3146 (ppr_options & MSG_EXT_PPR_QAS_REQ) != 0 3147 ? "(QAS)" : ""); 3148 } 3149 } 3150 } 3151 /* 3152 * Always refresh the neg-table to handle the case of the 3153 * sequencer setting the ENATNO bit for a MK_MESSAGE request. 3154 * We will always renegotiate in that case if this is a 3155 * packetized request. Also manage the busfree expected flag 3156 * from this common routine so that we catch changes due to 3157 * WDTR or SDTR messages. 3158 */ 3159 if ((type & AHD_TRANS_CUR) != 0) { 3160 if (!paused) 3161 ahd_pause(ahd); 3162 ahd_update_neg_table(ahd, devinfo, &tinfo->curr); 3163 if (!paused) 3164 ahd_unpause(ahd); 3165 if (ahd->msg_type != MSG_TYPE_NONE) { 3166 if ((old_ppr & MSG_EXT_PPR_IU_REQ) 3167 != (ppr_options & MSG_EXT_PPR_IU_REQ)) { 3168 #ifdef AHD_DEBUG 3169 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3170 ahd_print_devinfo(ahd, devinfo); 3171 printf("Expecting IU Change busfree\n"); 3172 } 3173 #endif 3174 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE 3175 | MSG_FLAG_IU_REQ_CHANGED; 3176 } 3177 if ((old_ppr & MSG_EXT_PPR_IU_REQ) != 0) { 3178 #ifdef AHD_DEBUG 3179 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3180 printf("PPR with IU_REQ outstanding\n"); 3181 #endif 3182 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE; 3183 } 3184 } 3185 } 3186 3187 update_needed += ahd_update_neg_request(ahd, devinfo, tstate, 3188 tinfo, AHD_NEG_TO_GOAL); 3189 3190 if (update_needed && active) 3191 ahd_update_pending_scbs(ahd); 3192 } 3193 3194 /* 3195 * Update the user/goal/curr tables of wide negotiation 3196 * parameters as well as, in the case of a current or active update, 3197 * any data structures on the host controller. In the case of an 3198 * active update, the specified target is currently talking to us on 3199 * the bus, so the transfer parameter update must take effect 3200 * immediately. 3201 */ 3202 void 3203 ahd_set_width(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3204 u_int width, u_int type, int paused) 3205 { 3206 struct ahd_initiator_tinfo *tinfo; 3207 struct ahd_tmode_tstate *tstate; 3208 u_int oldwidth; 3209 int active; 3210 int update_needed; 3211 3212 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE; 3213 update_needed = 0; 3214 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3215 devinfo->target, &tstate); 3216 3217 if ((type & AHD_TRANS_USER) != 0) 3218 tinfo->user.width = width; 3219 3220 if ((type & AHD_TRANS_GOAL) != 0) 3221 tinfo->goal.width = width; 3222 3223 oldwidth = tinfo->curr.width; 3224 if ((type & AHD_TRANS_CUR) != 0 && oldwidth != width) { 3225 update_needed++; 3226 3227 tinfo->curr.width = width; 3228 ahd_send_async(ahd, devinfo->channel, devinfo->target, 3229 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL); 3230 if (bootverbose) { 3231 printf("%s: target %d using %dbit transfers\n", 3232 ahd_name(ahd), devinfo->target, 3233 8 * (0x01 << width)); 3234 } 3235 } 3236 3237 if ((type & AHD_TRANS_CUR) != 0) { 3238 if (!paused) 3239 ahd_pause(ahd); 3240 ahd_update_neg_table(ahd, devinfo, &tinfo->curr); 3241 if (!paused) 3242 ahd_unpause(ahd); 3243 } 3244 3245 update_needed += ahd_update_neg_request(ahd, devinfo, tstate, 3246 tinfo, AHD_NEG_TO_GOAL); 3247 if (update_needed && active) 3248 ahd_update_pending_scbs(ahd); 3249 3250 } 3251 3252 /* 3253 * Update the current state of tagged queuing for a given target. 3254 */ 3255 void 3256 ahd_set_tags(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3257 ahd_queue_alg alg) 3258 { 3259 ahd_platform_set_tags(ahd, devinfo, alg); 3260 ahd_send_async(ahd, devinfo->channel, devinfo->target, 3261 devinfo->lun, AC_TRANSFER_NEG, &alg); 3262 } 3263 3264 static void 3265 ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3266 struct ahd_transinfo *tinfo) 3267 { 3268 ahd_mode_state saved_modes; 3269 u_int period; 3270 u_int ppr_opts; 3271 u_int con_opts; 3272 u_int offset; 3273 u_int saved_negoaddr; 3274 uint8_t iocell_opts[sizeof(ahd->iocell_opts)]; 3275 3276 saved_modes = ahd_save_modes(ahd); 3277 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3278 3279 saved_negoaddr = ahd_inb(ahd, NEGOADDR); 3280 ahd_outb(ahd, NEGOADDR, devinfo->target); 3281 period = tinfo->period; 3282 offset = tinfo->offset; 3283 memcpy(iocell_opts, ahd->iocell_opts, sizeof(ahd->iocell_opts)); 3284 ppr_opts = tinfo->ppr_options & (MSG_EXT_PPR_QAS_REQ|MSG_EXT_PPR_DT_REQ 3285 |MSG_EXT_PPR_IU_REQ|MSG_EXT_PPR_RTI); 3286 con_opts = 0; 3287 if (period == 0) 3288 period = AHD_SYNCRATE_ASYNC; 3289 if (period == AHD_SYNCRATE_160) { 3290 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) { 3291 /* 3292 * When the SPI4 spec was finalized, PACE transfers 3293 * was not made a configurable option in the PPR 3294 * message. Instead it is assumed to be enabled for 3295 * any syncrate faster than 80MHz. Nevertheless, 3296 * Harpoon2A4 allows this to be configurable. 3297 * 3298 * Harpoon2A4 also assumes at most 2 data bytes per 3299 * negotiated REQ/ACK offset. Paced transfers take 3300 * 4, so we must adjust our offset. 3301 */ 3302 ppr_opts |= PPROPT_PACE; 3303 offset *= 2; 3304 3305 /* 3306 * Harpoon2A assumed that there would be a 3307 * fallback rate between 160MHz and 80Mhz, 3308 * so 7 is used as the period factor rather 3309 * than 8 for 160MHz. 3310 */ 3311 period = AHD_SYNCRATE_REVA_160; 3312 } 3313 if ((tinfo->ppr_options & MSG_EXT_PPR_PCOMP_EN) == 0) 3314 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= 3315 ~AHD_PRECOMP_MASK; 3316 } else { 3317 /* 3318 * Precomp should be disabled for non-paced transfers. 3319 */ 3320 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; 3321 3322 if ((ahd->features & AHD_NEW_IOCELL_OPTS) != 0 3323 && (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0 3324 && (ppr_opts & MSG_EXT_PPR_IU_REQ) == 0) { 3325 /* 3326 * Slow down our CRC interval to be 3327 * compatible with non-packetized 3328 * U160 devices that can't handle a 3329 * CRC at full speed. 3330 */ 3331 con_opts |= ENSLOWCRC; 3332 } 3333 3334 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) { 3335 /* 3336 * On H2A4, revert to a slower slewrate 3337 * on non-paced transfers. 3338 */ 3339 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= 3340 ~AHD_SLEWRATE_MASK; 3341 } 3342 } 3343 3344 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP_SLEW); 3345 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_PRECOMP_SLEW_INDEX]); 3346 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_AMPLITUDE); 3347 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_AMPLITUDE_INDEX]); 3348 3349 ahd_outb(ahd, NEGPERIOD, period); 3350 ahd_outb(ahd, NEGPPROPTS, ppr_opts); 3351 ahd_outb(ahd, NEGOFFSET, offset); 3352 3353 if (tinfo->width == MSG_EXT_WDTR_BUS_16_BIT) 3354 con_opts |= WIDEXFER; 3355 3356 /* 3357 * During packetized transfers, the target will 3358 * give us the opportunity to send command packets 3359 * without us asserting attention. 3360 */ 3361 if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0) 3362 con_opts |= ENAUTOATNO; 3363 ahd_outb(ahd, NEGCONOPTS, con_opts); 3364 ahd_outb(ahd, NEGOADDR, saved_negoaddr); 3365 ahd_restore_modes(ahd, saved_modes); 3366 } 3367 3368 /* 3369 * When the transfer settings for a connection change, setup for 3370 * negotiation in pending SCBs to effect the change as quickly as 3371 * possible. We also cancel any negotiations that are scheduled 3372 * for inflight SCBs that have not been started yet. 3373 */ 3374 static void 3375 ahd_update_pending_scbs(struct ahd_softc *ahd) 3376 { 3377 struct scb *pending_scb; 3378 int pending_scb_count; 3379 int paused; 3380 u_int saved_scbptr; 3381 ahd_mode_state saved_modes; 3382 3383 /* 3384 * Traverse the pending SCB list and ensure that all of the 3385 * SCBs there have the proper settings. We can only safely 3386 * clear the negotiation required flag (setting requires the 3387 * execution queue to be modified) and this is only possible 3388 * if we are not already attempting to select out for this 3389 * SCB. For this reason, all callers only call this routine 3390 * if we are changing the negotiation settings for the currently 3391 * active transaction on the bus. 3392 */ 3393 pending_scb_count = 0; 3394 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) { 3395 struct ahd_devinfo devinfo; 3396 struct ahd_tmode_tstate *tstate; 3397 3398 ahd_scb_devinfo(ahd, &devinfo, pending_scb); 3399 ahd_fetch_transinfo(ahd, devinfo.channel, 3400 devinfo.our_scsiid, 3401 devinfo.target, &tstate); 3402 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 3403 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 3404 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 3405 pending_scb->hscb->control &= ~MK_MESSAGE; 3406 } 3407 ahd_sync_scb(ahd, pending_scb, 3408 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3409 pending_scb_count++; 3410 } 3411 3412 if (pending_scb_count == 0) 3413 return; 3414 3415 if (ahd_is_paused(ahd)) { 3416 paused = 1; 3417 } else { 3418 paused = 0; 3419 ahd_pause(ahd); 3420 } 3421 3422 /* 3423 * Force the sequencer to reinitialize the selection for 3424 * the command at the head of the execution queue if it 3425 * has already been setup. The negotiation changes may 3426 * effect whether we select-out with ATN. It is only 3427 * safe to clear ENSELO when the bus is not free and no 3428 * selection is in progres or completed. 3429 */ 3430 saved_modes = ahd_save_modes(ahd); 3431 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3432 if ((ahd_inb(ahd, SCSISIGI) & BSYI) != 0 3433 && (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0) 3434 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO); 3435 saved_scbptr = ahd_get_scbptr(ahd); 3436 /* Ensure that the hscbs down on the card match the new information */ 3437 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) { 3438 u_int scb_tag; 3439 u_int control; 3440 3441 scb_tag = SCB_GET_TAG(pending_scb); 3442 ahd_set_scbptr(ahd, scb_tag); 3443 control = ahd_inb_scbram(ahd, SCB_CONTROL); 3444 control &= ~MK_MESSAGE; 3445 control |= pending_scb->hscb->control & MK_MESSAGE; 3446 ahd_outb(ahd, SCB_CONTROL, control); 3447 } 3448 ahd_set_scbptr(ahd, saved_scbptr); 3449 ahd_restore_modes(ahd, saved_modes); 3450 3451 if (paused == 0) 3452 ahd_unpause(ahd); 3453 } 3454 3455 /**************************** Pathing Information *****************************/ 3456 static void 3457 ahd_fetch_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3458 { 3459 ahd_mode_state saved_modes; 3460 u_int saved_scsiid; 3461 role_t role; 3462 int our_id; 3463 3464 saved_modes = ahd_save_modes(ahd); 3465 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3466 3467 if (ahd_inb(ahd, SSTAT0) & TARGET) 3468 role = ROLE_TARGET; 3469 else 3470 role = ROLE_INITIATOR; 3471 3472 if (role == ROLE_TARGET 3473 && (ahd_inb(ahd, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) { 3474 /* We were selected, so pull our id from TARGIDIN */ 3475 our_id = ahd_inb(ahd, TARGIDIN) & OID; 3476 } else if (role == ROLE_TARGET) 3477 our_id = ahd_inb(ahd, TOWNID); 3478 else 3479 our_id = ahd_inb(ahd, IOWNID); 3480 3481 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID); 3482 ahd_compile_devinfo(devinfo, 3483 our_id, 3484 SCSIID_TARGET(ahd, saved_scsiid), 3485 ahd_inb(ahd, SAVED_LUN), 3486 SCSIID_CHANNEL(ahd, saved_scsiid), 3487 role); 3488 ahd_restore_modes(ahd, saved_modes); 3489 } 3490 3491 void 3492 ahd_print_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3493 { 3494 printf("%s:%c:%d:%d: ", ahd_name(ahd), 'A', 3495 devinfo->target, devinfo->lun); 3496 } 3497 3498 struct ahd_phase_table_entry* 3499 ahd_lookup_phase_entry(int phase) 3500 { 3501 struct ahd_phase_table_entry *entry; 3502 struct ahd_phase_table_entry *last_entry; 3503 3504 /* 3505 * num_phases doesn't include the default entry which 3506 * will be returned if the phase doesn't match. 3507 */ 3508 last_entry = &ahd_phase_table[num_phases]; 3509 for (entry = ahd_phase_table; entry < last_entry; entry++) { 3510 if (phase == entry->phase) 3511 break; 3512 } 3513 return (entry); 3514 } 3515 3516 void 3517 ahd_compile_devinfo(struct ahd_devinfo *devinfo, u_int our_id, u_int target, 3518 u_int lun, char channel, role_t role) 3519 { 3520 devinfo->our_scsiid = our_id; 3521 devinfo->target = target; 3522 devinfo->lun = lun; 3523 devinfo->target_offset = target; 3524 devinfo->channel = channel; 3525 devinfo->role = role; 3526 if (channel == 'B') 3527 devinfo->target_offset += 8; 3528 devinfo->target_mask = (0x01 << devinfo->target_offset); 3529 } 3530 3531 static void 3532 ahd_scb_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3533 struct scb *scb) 3534 { 3535 role_t role; 3536 int our_id; 3537 3538 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 3539 role = ROLE_INITIATOR; 3540 if ((scb->hscb->control & TARGET_SCB) != 0) 3541 role = ROLE_TARGET; 3542 ahd_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahd, scb), 3543 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahd, scb), role); 3544 } 3545 3546 /************************ Message Phase Processing ****************************/ 3547 /* 3548 * When an initiator transaction with the MK_MESSAGE flag either reconnects 3549 * or enters the initial message out phase, we are interrupted. Fill our 3550 * outgoing message buffer with the appropriate message and beging handing 3551 * the message phase(s) manually. 3552 */ 3553 static void 3554 ahd_setup_initiator_msgout(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3555 struct scb *scb) 3556 { 3557 /* 3558 * To facilitate adding multiple messages together, 3559 * each routine should increment the index and len 3560 * variables instead of setting them explicitly. 3561 */ 3562 ahd->msgout_index = 0; 3563 ahd->msgout_len = 0; 3564 3565 if (ahd_currently_packetized(ahd)) 3566 ahd->msg_flags |= MSG_FLAG_PACKETIZED; 3567 3568 if (ahd->send_msg_perror 3569 && ahd_inb(ahd, MSG_OUT) == HOST_MSG) { 3570 ahd->msgout_buf[ahd->msgout_index++] = ahd->send_msg_perror; 3571 ahd->msgout_len++; 3572 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3573 #ifdef AHD_DEBUG 3574 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3575 printf("Setting up for Parity Error delivery\n"); 3576 #endif 3577 return; 3578 } else if (scb == NULL) { 3579 printf("%s: WARNING. No pending message for " 3580 "I_T msgin. Issuing NO-OP\n", ahd_name(ahd)); 3581 AHD_CORRECTABLE_ERROR(ahd); 3582 ahd->msgout_buf[ahd->msgout_index++] = MSG_NOOP; 3583 ahd->msgout_len++; 3584 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3585 return; 3586 } 3587 3588 if ((scb->flags & SCB_DEVICE_RESET) == 0 3589 && (scb->flags & SCB_PACKETIZED) == 0 3590 && ahd_inb(ahd, MSG_OUT) == MSG_IDENTIFYFLAG) { 3591 u_int identify_msg; 3592 3593 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 3594 if ((scb->hscb->control & DISCENB) != 0) 3595 identify_msg |= MSG_IDENTIFY_DISCFLAG; 3596 ahd->msgout_buf[ahd->msgout_index++] = identify_msg; 3597 ahd->msgout_len++; 3598 3599 if ((scb->hscb->control & TAG_ENB) != 0) { 3600 ahd->msgout_buf[ahd->msgout_index++] = 3601 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 3602 ahd->msgout_buf[ahd->msgout_index++] = SCB_GET_TAG(scb); 3603 ahd->msgout_len += 2; 3604 } 3605 } 3606 3607 if (scb->flags & SCB_DEVICE_RESET) { 3608 ahd->msgout_buf[ahd->msgout_index++] = MSG_BUS_DEV_RESET; 3609 ahd->msgout_len++; 3610 ahd_print_path(ahd, scb); 3611 printf("Bus Device Reset Message Sent\n"); 3612 AHD_CORRECTABLE_ERROR(ahd); 3613 /* 3614 * Clear our selection hardware in advance of 3615 * the busfree. We may have an entry in the waiting 3616 * Q for this target, and we don't want to go about 3617 * selecting while we handle the busfree and blow it 3618 * away. 3619 */ 3620 ahd_outb(ahd, SCSISEQ0, 0); 3621 } else if ((scb->flags & SCB_ABORT) != 0) { 3622 if ((scb->hscb->control & TAG_ENB) != 0) { 3623 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT_TAG; 3624 } else { 3625 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT; 3626 } 3627 ahd->msgout_len++; 3628 ahd_print_path(ahd, scb); 3629 printf("Abort%s Message Sent\n", 3630 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 3631 AHD_CORRECTABLE_ERROR(ahd); 3632 /* 3633 * Clear our selection hardware in advance of 3634 * the busfree. We may have an entry in the waiting 3635 * Q for this target, and we don't want to go about 3636 * selecting while we handle the busfree and blow it 3637 * away. 3638 */ 3639 ahd_outb(ahd, SCSISEQ0, 0); 3640 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 3641 ahd_build_transfer_msg(ahd, devinfo); 3642 /* 3643 * Clear our selection hardware in advance of potential 3644 * PPR IU status change busfree. We may have an entry in 3645 * the waiting Q for this target, and we don't want to go 3646 * about selecting while we handle the busfree and blow 3647 * it away. 3648 */ 3649 ahd_outb(ahd, SCSISEQ0, 0); 3650 } else { 3651 printf("ahd_intr: AWAITING_MSG for an SCB that " 3652 "does not have a waiting message\n"); 3653 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 3654 devinfo->target_mask); 3655 AHD_FATAL_ERROR(ahd); 3656 panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x " 3657 "SCB flags = %x", SCB_GET_TAG(scb), scb->hscb->control, 3658 ahd_inb_scbram(ahd, SCB_CONTROL), ahd_inb(ahd, MSG_OUT), 3659 scb->flags); 3660 } 3661 3662 /* 3663 * Clear the MK_MESSAGE flag from the SCB so we aren't 3664 * asked to send this message again. 3665 */ 3666 ahd_outb(ahd, SCB_CONTROL, 3667 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE); 3668 scb->hscb->control &= ~MK_MESSAGE; 3669 ahd->msgout_index = 0; 3670 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3671 } 3672 3673 /* 3674 * Build an appropriate transfer negotiation message for the 3675 * currently active target. 3676 */ 3677 static void 3678 ahd_build_transfer_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 3679 { 3680 /* 3681 * We need to initiate transfer negotiations. 3682 * If our current and goal settings are identical, 3683 * we want to renegotiate due to a check condition. 3684 */ 3685 struct ahd_initiator_tinfo *tinfo; 3686 struct ahd_tmode_tstate *tstate; 3687 int dowide; 3688 int dosync; 3689 int doppr; 3690 u_int period; 3691 u_int ppr_options; 3692 u_int offset; 3693 3694 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 3695 devinfo->target, &tstate); 3696 /* 3697 * Filter our period based on the current connection. 3698 * If we can't perform DT transfers on this segment (not in LVD 3699 * mode for instance), then our decision to issue a PPR message 3700 * may change. 3701 */ 3702 period = tinfo->goal.period; 3703 offset = tinfo->goal.offset; 3704 ppr_options = tinfo->goal.ppr_options; 3705 /* Target initiated PPR is not allowed in the SCSI spec */ 3706 if (devinfo->role == ROLE_TARGET) 3707 ppr_options = 0; 3708 ahd_devlimited_syncrate(ahd, tinfo, &period, 3709 &ppr_options, devinfo->role); 3710 dowide = tinfo->curr.width != tinfo->goal.width; 3711 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period; 3712 /* 3713 * Only use PPR if we have options that need it, even if the device 3714 * claims to support it. There might be an expander in the way 3715 * that doesn't. 3716 */ 3717 doppr = ppr_options != 0; 3718 3719 if (!dowide && !dosync && !doppr) { 3720 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 3721 dosync = tinfo->goal.offset != 0; 3722 } 3723 3724 if (!dowide && !dosync && !doppr) { 3725 /* 3726 * Force async with a WDTR message if we have a wide bus, 3727 * or just issue an SDTR with a 0 offset. 3728 */ 3729 if ((ahd->features & AHD_WIDE) != 0) 3730 dowide = 1; 3731 else 3732 dosync = 1; 3733 3734 if (bootverbose) { 3735 ahd_print_devinfo(ahd, devinfo); 3736 printf("Ensuring async\n"); 3737 } 3738 } 3739 /* Target initiated PPR is not allowed in the SCSI spec */ 3740 if (devinfo->role == ROLE_TARGET) 3741 doppr = 0; 3742 3743 /* 3744 * Both the PPR message and SDTR message require the 3745 * goal syncrate to be limited to what the target device 3746 * is capable of handling (based on whether an LVD->SE 3747 * expander is on the bus), so combine these two cases. 3748 * Regardless, guarantee that if we are using WDTR and SDTR 3749 * messages that WDTR comes first. 3750 */ 3751 if (doppr || (dosync && !dowide)) { 3752 offset = tinfo->goal.offset; 3753 ahd_validate_offset(ahd, tinfo, period, &offset, 3754 doppr ? tinfo->goal.width 3755 : tinfo->curr.width, 3756 devinfo->role); 3757 if (doppr) { 3758 ahd_construct_ppr(ahd, devinfo, period, offset, 3759 tinfo->goal.width, ppr_options); 3760 } else { 3761 ahd_construct_sdtr(ahd, devinfo, period, offset); 3762 } 3763 } else { 3764 ahd_construct_wdtr(ahd, devinfo, tinfo->goal.width); 3765 } 3766 } 3767 3768 /* 3769 * Build a synchronous negotiation message in our message 3770 * buffer based on the input parameters. 3771 */ 3772 static void 3773 ahd_construct_sdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3774 u_int period, u_int offset) 3775 { 3776 if (offset == 0) 3777 period = AHD_ASYNC_XFER_PERIOD; 3778 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3779 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR_LEN; 3780 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR; 3781 ahd->msgout_buf[ahd->msgout_index++] = period; 3782 ahd->msgout_buf[ahd->msgout_index++] = offset; 3783 ahd->msgout_len += 5; 3784 if (bootverbose) { 3785 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 3786 ahd_name(ahd), devinfo->channel, devinfo->target, 3787 devinfo->lun, period, offset); 3788 } 3789 } 3790 3791 /* 3792 * Build a wide negotiateion message in our message 3793 * buffer based on the input parameters. 3794 */ 3795 static void 3796 ahd_construct_wdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3797 u_int bus_width) 3798 { 3799 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3800 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR_LEN; 3801 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR; 3802 ahd->msgout_buf[ahd->msgout_index++] = bus_width; 3803 ahd->msgout_len += 4; 3804 if (bootverbose) { 3805 printf("(%s:%c:%d:%d): Sending WDTR %x\n", 3806 ahd_name(ahd), devinfo->channel, devinfo->target, 3807 devinfo->lun, bus_width); 3808 } 3809 } 3810 3811 /* 3812 * Build a parallel protocol request message in our message 3813 * buffer based on the input parameters. 3814 */ 3815 static void 3816 ahd_construct_ppr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 3817 u_int period, u_int offset, u_int bus_width, 3818 u_int ppr_options) 3819 { 3820 /* 3821 * Always request precompensation from 3822 * the other target if we are running 3823 * at paced syncrates. 3824 */ 3825 if (period <= AHD_SYNCRATE_PACED) 3826 ppr_options |= MSG_EXT_PPR_PCOMP_EN; 3827 if (offset == 0) 3828 period = AHD_ASYNC_XFER_PERIOD; 3829 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED; 3830 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR_LEN; 3831 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR; 3832 ahd->msgout_buf[ahd->msgout_index++] = period; 3833 ahd->msgout_buf[ahd->msgout_index++] = 0; 3834 ahd->msgout_buf[ahd->msgout_index++] = offset; 3835 ahd->msgout_buf[ahd->msgout_index++] = bus_width; 3836 ahd->msgout_buf[ahd->msgout_index++] = ppr_options; 3837 ahd->msgout_len += 8; 3838 if (bootverbose) { 3839 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, " 3840 "offset %x, ppr_options %x\n", ahd_name(ahd), 3841 devinfo->channel, devinfo->target, devinfo->lun, 3842 bus_width, period, offset, ppr_options); 3843 } 3844 } 3845 3846 /* 3847 * Clear any active message state. 3848 */ 3849 static void 3850 ahd_clear_msg_state(struct ahd_softc *ahd) 3851 { 3852 ahd_mode_state saved_modes; 3853 3854 saved_modes = ahd_save_modes(ahd); 3855 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 3856 ahd->send_msg_perror = 0; 3857 ahd->msg_flags = MSG_FLAG_NONE; 3858 ahd->msgout_len = 0; 3859 ahd->msgin_index = 0; 3860 ahd->msg_type = MSG_TYPE_NONE; 3861 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0) { 3862 /* 3863 * The target didn't care to respond to our 3864 * message request, so clear ATN. 3865 */ 3866 ahd_outb(ahd, CLRSINT1, CLRATNO); 3867 } 3868 ahd_outb(ahd, MSG_OUT, MSG_NOOP); 3869 ahd_outb(ahd, SEQ_FLAGS2, 3870 ahd_inb(ahd, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 3871 ahd_restore_modes(ahd, saved_modes); 3872 } 3873 3874 /* 3875 * Manual message loop handler. 3876 */ 3877 static void 3878 ahd_handle_message_phase(struct ahd_softc *ahd) 3879 { 3880 struct ahd_devinfo devinfo; 3881 u_int bus_phase; 3882 int end_session; 3883 3884 ahd_fetch_devinfo(ahd, &devinfo); 3885 end_session = FALSE; 3886 bus_phase = ahd_inb(ahd, LASTPHASE); 3887 3888 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0) { 3889 printf("LQIRETRY for LQIPHASE_OUTPKT\n"); 3890 ahd_outb(ahd, LQCTL2, LQIRETRY); 3891 } 3892 reswitch: 3893 switch (ahd->msg_type) { 3894 case MSG_TYPE_INITIATOR_MSGOUT: 3895 { 3896 int lastbyte; 3897 int phasemis; 3898 int msgdone; 3899 3900 if (ahd->msgout_len == 0 && ahd->send_msg_perror == 0) 3901 panic("HOST_MSG_LOOP interrupt with no active message"); 3902 3903 #ifdef AHD_DEBUG 3904 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3905 ahd_print_devinfo(ahd, &devinfo); 3906 printf("INITIATOR_MSG_OUT"); 3907 } 3908 #endif 3909 phasemis = bus_phase != P_MESGOUT; 3910 if (phasemis) { 3911 #ifdef AHD_DEBUG 3912 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3913 printf(" PHASEMIS %s\n", 3914 ahd_lookup_phase_entry(bus_phase) 3915 ->phasemsg); 3916 } 3917 #endif 3918 if (bus_phase == P_MESGIN) { 3919 /* 3920 * Change gears and see if 3921 * this messages is of interest to 3922 * us or should be passed back to 3923 * the sequencer. 3924 */ 3925 ahd_outb(ahd, CLRSINT1, CLRATNO); 3926 ahd->send_msg_perror = 0; 3927 ahd->msg_type = MSG_TYPE_INITIATOR_MSGIN; 3928 ahd->msgin_index = 0; 3929 goto reswitch; 3930 } 3931 end_session = TRUE; 3932 break; 3933 } 3934 3935 if (ahd->send_msg_perror) { 3936 ahd_outb(ahd, CLRSINT1, CLRATNO); 3937 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3938 #ifdef AHD_DEBUG 3939 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3940 printf(" byte 0x%x\n", ahd->send_msg_perror); 3941 #endif 3942 /* 3943 * If we are notifying the target of a CRC error 3944 * during packetized operations, the target is 3945 * within its rights to acknowledge our message 3946 * with a busfree. 3947 */ 3948 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0 3949 && ahd->send_msg_perror == MSG_INITIATOR_DET_ERR) 3950 ahd->msg_flags |= MSG_FLAG_EXPECT_IDE_BUSFREE; 3951 3952 ahd_outb(ahd, RETURN_2, ahd->send_msg_perror); 3953 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); 3954 break; 3955 } 3956 3957 msgdone = ahd->msgout_index == ahd->msgout_len; 3958 if (msgdone) { 3959 /* 3960 * The target has requested a retry. 3961 * Re-assert ATN, reset our message index to 3962 * 0, and try again. 3963 */ 3964 ahd->msgout_index = 0; 3965 ahd_assert_atn(ahd); 3966 } 3967 3968 lastbyte = ahd->msgout_index == (ahd->msgout_len - 1); 3969 if (lastbyte) { 3970 /* Last byte is signified by dropping ATN */ 3971 ahd_outb(ahd, CLRSINT1, CLRATNO); 3972 } 3973 3974 /* 3975 * Clear our interrupt status and present 3976 * the next byte on the bus. 3977 */ 3978 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 3979 #ifdef AHD_DEBUG 3980 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 3981 printf(" byte 0x%x\n", 3982 ahd->msgout_buf[ahd->msgout_index]); 3983 #endif 3984 ahd_outb(ahd, RETURN_2, ahd->msgout_buf[ahd->msgout_index++]); 3985 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE); 3986 break; 3987 } 3988 case MSG_TYPE_INITIATOR_MSGIN: 3989 { 3990 int phasemis; 3991 int message_done; 3992 3993 #ifdef AHD_DEBUG 3994 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 3995 ahd_print_devinfo(ahd, &devinfo); 3996 printf("INITIATOR_MSG_IN"); 3997 } 3998 #endif 3999 phasemis = bus_phase != P_MESGIN; 4000 if (phasemis) { 4001 #ifdef AHD_DEBUG 4002 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 4003 printf(" PHASEMIS %s\n", 4004 ahd_lookup_phase_entry(bus_phase) 4005 ->phasemsg); 4006 } 4007 #endif 4008 ahd->msgin_index = 0; 4009 if (bus_phase == P_MESGOUT 4010 && (ahd->send_msg_perror != 0 4011 || (ahd->msgout_len != 0 4012 && ahd->msgout_index == 0))) { 4013 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 4014 goto reswitch; 4015 } 4016 end_session = TRUE; 4017 break; 4018 } 4019 4020 /* Pull the byte in without acking it */ 4021 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIBUS); 4022 #ifdef AHD_DEBUG 4023 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 4024 printf(" byte 0x%x\n", 4025 ahd->msgin_buf[ahd->msgin_index]); 4026 #endif 4027 4028 message_done = ahd_parse_msg(ahd, &devinfo); 4029 4030 if (message_done) { 4031 /* 4032 * Clear our incoming message buffer in case there 4033 * is another message following this one. 4034 */ 4035 ahd->msgin_index = 0; 4036 4037 /* 4038 * If this message illicited a response, 4039 * assert ATN so the target takes us to the 4040 * message out phase. 4041 */ 4042 if (ahd->msgout_len != 0) { 4043 #ifdef AHD_DEBUG 4044 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) { 4045 ahd_print_devinfo(ahd, &devinfo); 4046 printf("Asserting ATN for response\n"); 4047 } 4048 #endif 4049 ahd_assert_atn(ahd); 4050 } 4051 } else 4052 ahd->msgin_index++; 4053 4054 if (message_done == MSGLOOP_TERMINATED) { 4055 end_session = TRUE; 4056 } else { 4057 /* Ack the byte */ 4058 ahd_outb(ahd, CLRSINT1, CLRREQINIT); 4059 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_READ); 4060 } 4061 break; 4062 } 4063 case MSG_TYPE_TARGET_MSGIN: 4064 { 4065 int msgdone; 4066 int msgout_request; 4067 4068 /* 4069 * By default, the message loop will continue. 4070 */ 4071 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); 4072 4073 if (ahd->msgout_len == 0) 4074 panic("Target MSGIN with no active message"); 4075 4076 /* 4077 * If we interrupted a mesgout session, the initiator 4078 * will not know this until our first REQ. So, we 4079 * only honor mesgout requests after we've sent our 4080 * first byte. 4081 */ 4082 if ((ahd_inb(ahd, SCSISIGI) & ATNI) != 0 4083 && ahd->msgout_index > 0) 4084 msgout_request = TRUE; 4085 else 4086 msgout_request = FALSE; 4087 4088 if (msgout_request) { 4089 /* 4090 * Change gears and see if 4091 * this messages is of interest to 4092 * us or should be passed back to 4093 * the sequencer. 4094 */ 4095 ahd->msg_type = MSG_TYPE_TARGET_MSGOUT; 4096 ahd_outb(ahd, SCSISIGO, P_MESGOUT | BSYO); 4097 ahd->msgin_index = 0; 4098 /* Dummy read to REQ for first byte */ 4099 ahd_inb(ahd, SCSIDAT); 4100 ahd_outb(ahd, SXFRCTL0, 4101 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 4102 break; 4103 } 4104 4105 msgdone = ahd->msgout_index == ahd->msgout_len; 4106 if (msgdone) { 4107 ahd_outb(ahd, SXFRCTL0, 4108 ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); 4109 end_session = TRUE; 4110 break; 4111 } 4112 4113 /* 4114 * Present the next byte on the bus. 4115 */ 4116 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) | SPIOEN); 4117 ahd_outb(ahd, SCSIDAT, ahd->msgout_buf[ahd->msgout_index++]); 4118 break; 4119 } 4120 case MSG_TYPE_TARGET_MSGOUT: 4121 { 4122 int lastbyte; 4123 int msgdone; 4124 4125 /* 4126 * By default, the message loop will continue. 4127 */ 4128 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG); 4129 4130 /* 4131 * The initiator signals that this is 4132 * the last byte by dropping ATN. 4133 */ 4134 lastbyte = (ahd_inb(ahd, SCSISIGI) & ATNI) == 0; 4135 4136 /* 4137 * Read the latched byte, but turn off SPIOEN first 4138 * so that we don't inadvertently cause a REQ for the 4139 * next byte. 4140 */ 4141 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) & ~SPIOEN); 4142 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIDAT); 4143 msgdone = ahd_parse_msg(ahd, &devinfo); 4144 if (msgdone == MSGLOOP_TERMINATED) { 4145 /* 4146 * The message is *really* done in that it caused 4147 * us to go to bus free. The sequencer has already 4148 * been reset at this point, so pull the ejection 4149 * handle. 4150 */ 4151 return; 4152 } 4153 4154 ahd->msgin_index++; 4155 4156 /* 4157 * XXX Read spec about initiator dropping ATN too soon 4158 * and use msgdone to detect it. 4159 */ 4160 if (msgdone == MSGLOOP_MSGCOMPLETE) { 4161 ahd->msgin_index = 0; 4162 4163 /* 4164 * If this message illicited a response, transition 4165 * to the Message in phase and send it. 4166 */ 4167 if (ahd->msgout_len != 0) { 4168 ahd_outb(ahd, SCSISIGO, P_MESGIN | BSYO); 4169 ahd_outb(ahd, SXFRCTL0, 4170 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 4171 ahd->msg_type = MSG_TYPE_TARGET_MSGIN; 4172 ahd->msgin_index = 0; 4173 break; 4174 } 4175 } 4176 4177 if (lastbyte) 4178 end_session = TRUE; 4179 else { 4180 /* Ask for the next byte. */ 4181 ahd_outb(ahd, SXFRCTL0, 4182 ahd_inb(ahd, SXFRCTL0) | SPIOEN); 4183 } 4184 4185 break; 4186 } 4187 default: 4188 panic("Unknown REQINIT message type"); 4189 } 4190 4191 if (end_session) { 4192 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0) { 4193 printf("%s: Returning to Idle Loop\n", 4194 ahd_name(ahd)); 4195 ahd_clear_msg_state(ahd); 4196 4197 /* 4198 * Perform the equivalent of a clear_target_state. 4199 */ 4200 ahd_outb(ahd, LASTPHASE, P_BUSFREE); 4201 ahd_outb(ahd, SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT); 4202 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET); 4203 } else { 4204 ahd_clear_msg_state(ahd); 4205 ahd_outb(ahd, RETURN_1, EXIT_MSG_LOOP); 4206 } 4207 } 4208 } 4209 4210 /* 4211 * See if we sent a particular extended message to the target. 4212 * If "full" is true, return true only if the target saw the full 4213 * message. If "full" is false, return true if the target saw at 4214 * least the first byte of the message. 4215 */ 4216 static int 4217 ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, u_int msgval, int full) 4218 { 4219 int found; 4220 u_int index; 4221 4222 found = FALSE; 4223 index = 0; 4224 4225 while (index < ahd->msgout_len) { 4226 if (ahd->msgout_buf[index] == MSG_EXTENDED) { 4227 u_int end_index; 4228 4229 end_index = index + 1 + ahd->msgout_buf[index + 1]; 4230 if (ahd->msgout_buf[index+2] == msgval 4231 && type == AHDMSG_EXT) { 4232 if (full) { 4233 if (ahd->msgout_index > end_index) 4234 found = TRUE; 4235 } else if (ahd->msgout_index > index) 4236 found = TRUE; 4237 } 4238 index = end_index; 4239 } else if (ahd->msgout_buf[index] >= MSG_SIMPLE_TASK 4240 && ahd->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 4241 /* Skip tag type and tag id or residue param*/ 4242 index += 2; 4243 } else { 4244 /* Single byte message */ 4245 if (type == AHDMSG_1B 4246 && ahd->msgout_index > index 4247 && (ahd->msgout_buf[index] == msgval 4248 || ((ahd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0 4249 && msgval == MSG_IDENTIFYFLAG))) 4250 found = TRUE; 4251 index++; 4252 } 4253 4254 if (found) 4255 break; 4256 } 4257 return (found); 4258 } 4259 4260 /* 4261 * Wait for a complete incoming message, parse it, and respond accordingly. 4262 */ 4263 static int 4264 ahd_parse_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4265 { 4266 struct ahd_initiator_tinfo *tinfo; 4267 struct ahd_tmode_tstate *tstate; 4268 int reject; 4269 int done; 4270 int response; 4271 4272 done = MSGLOOP_IN_PROG; 4273 response = FALSE; 4274 reject = FALSE; 4275 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid, 4276 devinfo->target, &tstate); 4277 4278 /* 4279 * Parse as much of the message as is available, 4280 * rejecting it if we don't support it. When 4281 * the entire message is available and has been 4282 * handled, return MSGLOOP_MSGCOMPLETE, indicating 4283 * that we have parsed an entire message. 4284 * 4285 * In the case of extended messages, we accept the length 4286 * byte outright and perform more checking once we know the 4287 * extended message type. 4288 */ 4289 switch (ahd->msgin_buf[0]) { 4290 case MSG_DISCONNECT: 4291 case MSG_SAVEDATAPOINTER: 4292 case MSG_CMDCOMPLETE: 4293 case MSG_RESTOREPOINTERS: 4294 case MSG_IGN_WIDE_RESIDUE: 4295 /* 4296 * End our message loop as these are messages 4297 * the sequencer handles on its own. 4298 */ 4299 done = MSGLOOP_TERMINATED; 4300 break; 4301 case MSG_MESSAGE_REJECT: 4302 response = ahd_handle_msg_reject(ahd, devinfo); 4303 /* FALLTHROUGH */ 4304 case MSG_NOOP: 4305 done = MSGLOOP_MSGCOMPLETE; 4306 break; 4307 case MSG_EXTENDED: 4308 { 4309 /* Wait for enough of the message to begin validation */ 4310 if (ahd->msgin_index < 2) 4311 break; 4312 switch (ahd->msgin_buf[2]) { 4313 case MSG_EXT_SDTR: 4314 { 4315 u_int period; 4316 u_int ppr_options; 4317 u_int offset; 4318 u_int saved_offset; 4319 4320 if (ahd->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 4321 reject = TRUE; 4322 break; 4323 } 4324 4325 /* 4326 * Wait until we have both args before validating 4327 * and acting on this message. 4328 * 4329 * Add one to MSG_EXT_SDTR_LEN to account for 4330 * the extended message preamble. 4331 */ 4332 if (ahd->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 4333 break; 4334 4335 period = ahd->msgin_buf[3]; 4336 ppr_options = 0; 4337 saved_offset = offset = ahd->msgin_buf[4]; 4338 ahd_devlimited_syncrate(ahd, tinfo, &period, 4339 &ppr_options, devinfo->role); 4340 ahd_validate_offset(ahd, tinfo, period, &offset, 4341 tinfo->curr.width, devinfo->role); 4342 if (bootverbose) { 4343 printf("(%s:%c:%d:%d): Received " 4344 "SDTR period %x, offset %x\n\t" 4345 "Filtered to period %x, offset %x\n", 4346 ahd_name(ahd), devinfo->channel, 4347 devinfo->target, devinfo->lun, 4348 ahd->msgin_buf[3], saved_offset, 4349 period, offset); 4350 } 4351 ahd_set_syncrate(ahd, devinfo, period, 4352 offset, ppr_options, 4353 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4354 /*paused*/TRUE); 4355 4356 /* 4357 * See if we initiated Sync Negotiation 4358 * and didn't have to fall down to async 4359 * transfers. 4360 */ 4361 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, TRUE)) { 4362 /* We started it */ 4363 if (saved_offset != offset) { 4364 /* Went too low - force async */ 4365 reject = TRUE; 4366 } 4367 } else { 4368 /* 4369 * Send our own SDTR in reply 4370 */ 4371 if (bootverbose 4372 && devinfo->role == ROLE_INITIATOR) { 4373 printf("(%s:%c:%d:%d): Target " 4374 "Initiated SDTR\n", 4375 ahd_name(ahd), devinfo->channel, 4376 devinfo->target, devinfo->lun); 4377 } 4378 ahd->msgout_index = 0; 4379 ahd->msgout_len = 0; 4380 ahd_construct_sdtr(ahd, devinfo, 4381 period, offset); 4382 ahd->msgout_index = 0; 4383 response = TRUE; 4384 } 4385 done = MSGLOOP_MSGCOMPLETE; 4386 break; 4387 } 4388 case MSG_EXT_WDTR: 4389 { 4390 u_int bus_width; 4391 u_int saved_width; 4392 u_int sending_reply; 4393 4394 sending_reply = FALSE; 4395 if (ahd->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 4396 reject = TRUE; 4397 break; 4398 } 4399 4400 /* 4401 * Wait until we have our arg before validating 4402 * and acting on this message. 4403 * 4404 * Add one to MSG_EXT_WDTR_LEN to account for 4405 * the extended message preamble. 4406 */ 4407 if (ahd->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 4408 break; 4409 4410 bus_width = ahd->msgin_buf[3]; 4411 saved_width = bus_width; 4412 ahd_validate_width(ahd, tinfo, &bus_width, 4413 devinfo->role); 4414 if (bootverbose) { 4415 printf("(%s:%c:%d:%d): Received WDTR " 4416 "%x filtered to %x\n", 4417 ahd_name(ahd), devinfo->channel, 4418 devinfo->target, devinfo->lun, 4419 saved_width, bus_width); 4420 } 4421 4422 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, TRUE)) { 4423 /* 4424 * Don't send a WDTR back to the 4425 * target, since we asked first. 4426 * If the width went higher than our 4427 * request, reject it. 4428 */ 4429 if (saved_width > bus_width) { 4430 reject = TRUE; 4431 printf("(%s:%c:%d:%d): requested %dBit " 4432 "transfers. Rejecting...\n", 4433 ahd_name(ahd), devinfo->channel, 4434 devinfo->target, devinfo->lun, 4435 8 * (0x01 << bus_width)); 4436 bus_width = 0; 4437 } 4438 } else { 4439 /* 4440 * Send our own WDTR in reply 4441 */ 4442 if (bootverbose 4443 && devinfo->role == ROLE_INITIATOR) { 4444 printf("(%s:%c:%d:%d): Target " 4445 "Initiated WDTR\n", 4446 ahd_name(ahd), devinfo->channel, 4447 devinfo->target, devinfo->lun); 4448 } 4449 ahd->msgout_index = 0; 4450 ahd->msgout_len = 0; 4451 ahd_construct_wdtr(ahd, devinfo, bus_width); 4452 ahd->msgout_index = 0; 4453 response = TRUE; 4454 sending_reply = TRUE; 4455 } 4456 /* 4457 * After a wide message, we are async, but 4458 * some devices don't seem to honor this portion 4459 * of the spec. Force a renegotiation of the 4460 * sync component of our transfer agreement even 4461 * if our goal is async. By updating our width 4462 * after forcing the negotiation, we avoid 4463 * renegotiating for width. 4464 */ 4465 ahd_update_neg_request(ahd, devinfo, tstate, 4466 tinfo, AHD_NEG_ALWAYS); 4467 ahd_set_width(ahd, devinfo, bus_width, 4468 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4469 /*paused*/TRUE); 4470 if (sending_reply == FALSE && reject == FALSE) { 4471 /* 4472 * We will always have an SDTR to send. 4473 */ 4474 ahd->msgout_index = 0; 4475 ahd->msgout_len = 0; 4476 ahd_build_transfer_msg(ahd, devinfo); 4477 ahd->msgout_index = 0; 4478 response = TRUE; 4479 } 4480 done = MSGLOOP_MSGCOMPLETE; 4481 break; 4482 } 4483 case MSG_EXT_PPR: 4484 { 4485 u_int period; 4486 u_int offset; 4487 u_int bus_width; 4488 u_int ppr_options; 4489 u_int saved_width; 4490 u_int saved_offset; 4491 u_int saved_ppr_options; 4492 4493 if (ahd->msgin_buf[1] != MSG_EXT_PPR_LEN) { 4494 reject = TRUE; 4495 break; 4496 } 4497 4498 /* 4499 * Wait until we have all args before validating 4500 * and acting on this message. 4501 * 4502 * Add one to MSG_EXT_PPR_LEN to account for 4503 * the extended message preamble. 4504 */ 4505 if (ahd->msgin_index < (MSG_EXT_PPR_LEN + 1)) 4506 break; 4507 4508 period = ahd->msgin_buf[3]; 4509 offset = ahd->msgin_buf[5]; 4510 bus_width = ahd->msgin_buf[6]; 4511 saved_width = bus_width; 4512 ppr_options = ahd->msgin_buf[7]; 4513 /* 4514 * According to the spec, a DT only 4515 * period factor with no DT option 4516 * set implies async. 4517 */ 4518 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 4519 && period <= 9) 4520 offset = 0; 4521 saved_ppr_options = ppr_options; 4522 saved_offset = offset; 4523 4524 /* 4525 * Transfer options are only available if we 4526 * are negotiating wide. 4527 */ 4528 if (bus_width == 0) 4529 ppr_options &= MSG_EXT_PPR_QAS_REQ; 4530 4531 ahd_validate_width(ahd, tinfo, &bus_width, 4532 devinfo->role); 4533 ahd_devlimited_syncrate(ahd, tinfo, &period, 4534 &ppr_options, devinfo->role); 4535 ahd_validate_offset(ahd, tinfo, period, &offset, 4536 bus_width, devinfo->role); 4537 4538 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, TRUE)) { 4539 /* 4540 * If we are unable to do any of the 4541 * requested options (we went too low), 4542 * then we'll have to reject the message. 4543 */ 4544 if (saved_width > bus_width 4545 || saved_offset != offset 4546 || saved_ppr_options != ppr_options) { 4547 reject = TRUE; 4548 period = 0; 4549 offset = 0; 4550 bus_width = 0; 4551 ppr_options = 0; 4552 } 4553 } else { 4554 if (devinfo->role != ROLE_TARGET) 4555 printf("(%s:%c:%d:%d): Target " 4556 "Initiated PPR\n", 4557 ahd_name(ahd), devinfo->channel, 4558 devinfo->target, devinfo->lun); 4559 else 4560 printf("(%s:%c:%d:%d): Initiator " 4561 "Initiated PPR\n", 4562 ahd_name(ahd), devinfo->channel, 4563 devinfo->target, devinfo->lun); 4564 ahd->msgout_index = 0; 4565 ahd->msgout_len = 0; 4566 ahd_construct_ppr(ahd, devinfo, period, offset, 4567 bus_width, ppr_options); 4568 ahd->msgout_index = 0; 4569 response = TRUE; 4570 } 4571 if (bootverbose) { 4572 printf("(%s:%c:%d:%d): Received PPR width %x, " 4573 "period %x, offset %x,options %x\n" 4574 "\tFiltered to width %x, period %x, " 4575 "offset %x, options %x\n", 4576 ahd_name(ahd), devinfo->channel, 4577 devinfo->target, devinfo->lun, 4578 saved_width, ahd->msgin_buf[3], 4579 saved_offset, saved_ppr_options, 4580 bus_width, period, offset, ppr_options); 4581 } 4582 ahd_set_width(ahd, devinfo, bus_width, 4583 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4584 /*paused*/TRUE); 4585 ahd_set_syncrate(ahd, devinfo, period, 4586 offset, ppr_options, 4587 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4588 /*paused*/TRUE); 4589 4590 done = MSGLOOP_MSGCOMPLETE; 4591 break; 4592 } 4593 default: 4594 /* Unknown extended message. Reject it. */ 4595 reject = TRUE; 4596 break; 4597 } 4598 break; 4599 } 4600 #ifdef AHD_TARGET_MODE 4601 case MSG_BUS_DEV_RESET: 4602 ahd_handle_devreset(ahd, devinfo, CAM_LUN_WILDCARD, 4603 CAM_BDR_SENT, 4604 "Bus Device Reset Received", 4605 /*verbose_level*/0); 4606 ahd_restart(ahd); 4607 done = MSGLOOP_TERMINATED; 4608 break; 4609 case MSG_ABORT_TAG: 4610 case MSG_ABORT: 4611 case MSG_CLEAR_QUEUE: 4612 { 4613 int tag; 4614 4615 /* Target mode messages */ 4616 if (devinfo->role != ROLE_TARGET) { 4617 reject = TRUE; 4618 break; 4619 } 4620 tag = SCB_LIST_NULL; 4621 if (ahd->msgin_buf[0] == MSG_ABORT_TAG) 4622 tag = ahd_inb(ahd, INITIATOR_TAG); 4623 ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, 4624 devinfo->lun, tag, ROLE_TARGET, 4625 CAM_REQ_ABORTED); 4626 4627 tstate = ahd->enabled_targets[devinfo->our_scsiid]; 4628 if (tstate != NULL) { 4629 struct ahd_tmode_lstate* lstate; 4630 4631 lstate = tstate->enabled_luns[devinfo->lun]; 4632 if (lstate != NULL) { 4633 ahd_queue_lstate_event(ahd, lstate, 4634 devinfo->our_scsiid, 4635 ahd->msgin_buf[0], 4636 /*arg*/tag); 4637 ahd_send_lstate_events(ahd, lstate); 4638 } 4639 } 4640 ahd_restart(ahd); 4641 done = MSGLOOP_TERMINATED; 4642 break; 4643 } 4644 #endif 4645 case MSG_QAS_REQUEST: 4646 #ifdef AHD_DEBUG 4647 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) 4648 printf("%s: QAS request. SCSISIGI == 0x%x\n", 4649 ahd_name(ahd), ahd_inb(ahd, SCSISIGI)); 4650 #endif 4651 ahd->msg_flags |= MSG_FLAG_EXPECT_QASREJ_BUSFREE; 4652 /* FALLTHROUGH */ 4653 case MSG_TERM_IO_PROC: 4654 default: 4655 reject = TRUE; 4656 break; 4657 } 4658 4659 if (reject) { 4660 /* 4661 * Setup to reject the message. 4662 */ 4663 ahd->msgout_index = 0; 4664 ahd->msgout_len = 1; 4665 ahd->msgout_buf[0] = MSG_MESSAGE_REJECT; 4666 done = MSGLOOP_MSGCOMPLETE; 4667 response = TRUE; 4668 } 4669 4670 if (done != MSGLOOP_IN_PROG && !response) 4671 /* Clear the outgoing message buffer */ 4672 ahd->msgout_len = 0; 4673 4674 return (done); 4675 } 4676 4677 /* 4678 * Process a message reject message. 4679 */ 4680 static int 4681 ahd_handle_msg_reject(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4682 { 4683 /* 4684 * What we care about here is if we had an 4685 * outstanding SDTR or WDTR message for this 4686 * target. If we did, this is a signal that 4687 * the target is refusing negotiation. 4688 */ 4689 struct scb *scb; 4690 struct ahd_initiator_tinfo *tinfo; 4691 struct ahd_tmode_tstate *tstate; 4692 u_int scb_index; 4693 u_int last_msg; 4694 int response = 0; 4695 4696 scb_index = ahd_get_scbptr(ahd); 4697 scb = ahd_lookup_scb(ahd, scb_index); 4698 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, 4699 devinfo->our_scsiid, 4700 devinfo->target, &tstate); 4701 /* Might be necessary */ 4702 last_msg = ahd_inb(ahd, LAST_MSG); 4703 4704 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 4705 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/TRUE) 4706 && tinfo->goal.period <= AHD_SYNCRATE_PACED) { 4707 /* 4708 * Target may not like our SPI-4 PPR Options. 4709 * Attempt to negotiate 80MHz which will turn 4710 * off these options. 4711 */ 4712 if (bootverbose) { 4713 printf("(%s:%c:%d:%d): PPR Rejected. " 4714 "Trying simple U160 PPR\n", 4715 ahd_name(ahd), devinfo->channel, 4716 devinfo->target, devinfo->lun); 4717 } 4718 tinfo->goal.period = AHD_SYNCRATE_DT; 4719 tinfo->goal.ppr_options &= MSG_EXT_PPR_IU_REQ 4720 | MSG_EXT_PPR_QAS_REQ 4721 | MSG_EXT_PPR_DT_REQ; 4722 } else { 4723 /* 4724 * Target does not support the PPR message. 4725 * Attempt to negotiate SPI-2 style. 4726 */ 4727 if (bootverbose) { 4728 printf("(%s:%c:%d:%d): PPR Rejected. " 4729 "Trying WDTR/SDTR\n", 4730 ahd_name(ahd), devinfo->channel, 4731 devinfo->target, devinfo->lun); 4732 } 4733 tinfo->goal.ppr_options = 0; 4734 tinfo->curr.transport_version = 2; 4735 tinfo->goal.transport_version = 2; 4736 } 4737 ahd->msgout_index = 0; 4738 ahd->msgout_len = 0; 4739 ahd_build_transfer_msg(ahd, devinfo); 4740 ahd->msgout_index = 0; 4741 response = 1; 4742 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 4743 /* note 8bit xfers */ 4744 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 4745 "8bit transfers\n", ahd_name(ahd), 4746 devinfo->channel, devinfo->target, devinfo->lun); 4747 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 4748 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4749 /*paused*/TRUE); 4750 /* 4751 * No need to clear the sync rate. If the target 4752 * did not accept the command, our syncrate is 4753 * unaffected. If the target started the negotiation, 4754 * but rejected our response, we already cleared the 4755 * sync rate before sending our WDTR. 4756 */ 4757 if (tinfo->goal.offset != tinfo->curr.offset) { 4758 /* Start the sync negotiation */ 4759 ahd->msgout_index = 0; 4760 ahd->msgout_len = 0; 4761 ahd_build_transfer_msg(ahd, devinfo); 4762 ahd->msgout_index = 0; 4763 response = 1; 4764 } 4765 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 4766 /* note asynch xfers and clear flag */ 4767 ahd_set_syncrate(ahd, devinfo, /*period*/0, 4768 /*offset*/0, /*ppr_options*/0, 4769 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL, 4770 /*paused*/TRUE); 4771 printf("(%s:%c:%d:%d): refuses synchronous negotiation. " 4772 "Using asynchronous transfers\n", 4773 ahd_name(ahd), devinfo->channel, 4774 devinfo->target, devinfo->lun); 4775 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 4776 int tag_type; 4777 int mask; 4778 4779 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 4780 4781 if (tag_type == MSG_SIMPLE_TASK) { 4782 printf("(%s:%c:%d:%d): refuses tagged commands. " 4783 "Performing non-tagged I/O\n", ahd_name(ahd), 4784 devinfo->channel, devinfo->target, devinfo->lun); 4785 ahd_set_tags(ahd, devinfo, AHD_QUEUE_NONE); 4786 mask = ~0x23; 4787 } else { 4788 printf("(%s:%c:%d:%d): refuses %s tagged commands. " 4789 "Performing simple queue tagged I/O only\n", 4790 ahd_name(ahd), devinfo->channel, devinfo->target, 4791 devinfo->lun, tag_type == MSG_ORDERED_TASK 4792 ? "ordered" : "head of queue"); 4793 ahd_set_tags(ahd, devinfo, AHD_QUEUE_BASIC); 4794 mask = ~0x03; 4795 } 4796 4797 /* 4798 * Resend the identify for this CCB as the target 4799 * may believe that the selection is invalid otherwise. 4800 */ 4801 ahd_outb(ahd, SCB_CONTROL, 4802 ahd_inb_scbram(ahd, SCB_CONTROL) & mask); 4803 scb->hscb->control &= mask; 4804 aic_set_transaction_tag(scb, /*enabled*/FALSE, 4805 /*type*/MSG_SIMPLE_TASK); 4806 ahd_outb(ahd, MSG_OUT, MSG_IDENTIFYFLAG); 4807 ahd_assert_atn(ahd); 4808 ahd_busy_tcl(ahd, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 4809 SCB_GET_TAG(scb)); 4810 4811 /* 4812 * Requeue all tagged commands for this target 4813 * currently in our possession so they can be 4814 * converted to untagged commands. 4815 */ 4816 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb), 4817 SCB_GET_CHANNEL(ahd, scb), 4818 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 4819 ROLE_INITIATOR, CAM_REQUEUE_REQ, 4820 SEARCH_COMPLETE); 4821 } else if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_IDENTIFYFLAG, TRUE)) { 4822 /* 4823 * Most likely the device believes that we had 4824 * previously negotiated packetized. 4825 */ 4826 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE 4827 | MSG_FLAG_IU_REQ_CHANGED; 4828 4829 ahd_force_renegotiation(ahd, devinfo); 4830 ahd->msgout_index = 0; 4831 ahd->msgout_len = 0; 4832 ahd_build_transfer_msg(ahd, devinfo); 4833 ahd->msgout_index = 0; 4834 response = 1; 4835 } else { 4836 /* 4837 * Otherwise, we ignore it. 4838 */ 4839 printf("%s:%c:%d: Message reject for %x -- ignored\n", 4840 ahd_name(ahd), devinfo->channel, devinfo->target, 4841 last_msg); 4842 } 4843 return (response); 4844 } 4845 4846 /* 4847 * Process an ignore wide residue message. 4848 */ 4849 static void 4850 ahd_handle_ign_wide_residue(struct ahd_softc *ahd, struct ahd_devinfo *devinfo) 4851 { 4852 u_int scb_index; 4853 struct scb *scb; 4854 4855 scb_index = ahd_get_scbptr(ahd); 4856 scb = ahd_lookup_scb(ahd, scb_index); 4857 /* 4858 * XXX Actually check data direction in the sequencer? 4859 * Perhaps add datadir to some spare bits in the hscb? 4860 */ 4861 if ((ahd_inb(ahd, SEQ_FLAGS) & DPHASE) == 0 4862 || aic_get_transfer_dir(scb) != CAM_DIR_IN) { 4863 /* 4864 * Ignore the message if we haven't 4865 * seen an appropriate data phase yet. 4866 */ 4867 } else { 4868 /* 4869 * If the residual occurred on the last 4870 * transfer and the transfer request was 4871 * expected to end on an odd count, do 4872 * nothing. Otherwise, subtract a byte 4873 * and update the residual count accordingly. 4874 */ 4875 uint32_t sgptr; 4876 4877 sgptr = ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR); 4878 if ((sgptr & SG_LIST_NULL) != 0 4879 && (ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE) 4880 & SCB_XFERLEN_ODD) != 0) { 4881 /* 4882 * If the residual occurred on the last 4883 * transfer and the transfer request was 4884 * expected to end on an odd count, do 4885 * nothing. 4886 */ 4887 } else { 4888 uint32_t data_cnt; 4889 uint32_t sglen; 4890 4891 /* Pull in the rest of the sgptr */ 4892 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 4893 data_cnt = ahd_inl_scbram(ahd, SCB_RESIDUAL_DATACNT); 4894 if ((sgptr & SG_LIST_NULL) != 0) { 4895 /* 4896 * The residual data count is not updated 4897 * for the command run to completion case. 4898 * Explicitly zero the count. 4899 */ 4900 data_cnt &= ~AHD_SG_LEN_MASK; 4901 } 4902 data_cnt += 1; 4903 sgptr &= SG_PTR_MASK; 4904 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 4905 struct ahd_dma64_seg *sg; 4906 4907 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4908 4909 /* 4910 * The residual sg ptr points to the next S/G 4911 * to load so we must go back one. 4912 */ 4913 sg--; 4914 sglen = aic_le32toh(sg->len) & AHD_SG_LEN_MASK; 4915 if (sg != scb->sg_list 4916 && sglen < (data_cnt & AHD_SG_LEN_MASK)) { 4917 sg--; 4918 sglen = aic_le32toh(sg->len); 4919 /* 4920 * Preserve High Address and SG_LIST 4921 * bits while setting the count to 1. 4922 */ 4923 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); 4924 4925 /* 4926 * Increment sg so it points to the 4927 * "next" sg. 4928 */ 4929 sg++; 4930 sgptr = ahd_sg_virt_to_bus(ahd, scb, 4931 sg); 4932 } 4933 } else { 4934 struct ahd_dma_seg *sg; 4935 4936 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 4937 4938 /* 4939 * The residual sg ptr points to the next S/G 4940 * to load so we must go back one. 4941 */ 4942 sg--; 4943 sglen = aic_le32toh(sg->len) & AHD_SG_LEN_MASK; 4944 if (sg != scb->sg_list 4945 && sglen < (data_cnt & AHD_SG_LEN_MASK)) { 4946 sg--; 4947 sglen = aic_le32toh(sg->len); 4948 /* 4949 * Preserve High Address and SG_LIST 4950 * bits while setting the count to 1. 4951 */ 4952 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK)); 4953 4954 /* 4955 * Increment sg so it points to the 4956 * "next" sg. 4957 */ 4958 sg++; 4959 sgptr = ahd_sg_virt_to_bus(ahd, scb, 4960 sg); 4961 } 4962 } 4963 /* 4964 * Toggle the "oddness" of the transfer length 4965 * to handle this mid-transfer ignore wide 4966 * residue. This ensures that the oddness is 4967 * correct for subsequent data transfers. 4968 */ 4969 ahd_outb(ahd, SCB_TASK_ATTRIBUTE, 4970 ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE) 4971 ^ SCB_XFERLEN_ODD); 4972 4973 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr); 4974 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, data_cnt); 4975 /* 4976 * The FIFO's pointers will be updated if/when the 4977 * sequencer re-enters a data phase. 4978 */ 4979 } 4980 } 4981 } 4982 4983 /* 4984 * Reinitialize the data pointers for the active transfer 4985 * based on its current residual. 4986 */ 4987 static void 4988 ahd_reinitialize_dataptrs(struct ahd_softc *ahd) 4989 { 4990 struct scb *scb; 4991 ahd_mode_state saved_modes; 4992 u_int scb_index; 4993 u_int wait; 4994 uint32_t sgptr; 4995 uint32_t resid; 4996 uint64_t dataptr; 4997 4998 AHD_ASSERT_MODES(ahd, AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK, 4999 AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK); 5000 5001 scb_index = ahd_get_scbptr(ahd); 5002 scb = ahd_lookup_scb(ahd, scb_index); 5003 5004 /* 5005 * Release and reacquire the FIFO so we 5006 * have a clean slate. 5007 */ 5008 ahd_outb(ahd, DFFSXFRCTL, CLRCHN); 5009 wait = 1000; 5010 while (--wait && !(ahd_inb(ahd, MDFFSTAT) & FIFOFREE)) 5011 aic_delay(100); 5012 if (wait == 0) { 5013 ahd_print_path(ahd, scb); 5014 printf("ahd_reinitialize_dataptrs: Forcing FIFO free.\n"); 5015 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT); 5016 } 5017 saved_modes = ahd_save_modes(ahd); 5018 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5019 ahd_outb(ahd, DFFSTAT, 5020 ahd_inb(ahd, DFFSTAT) 5021 | (saved_modes == 0x11 ? CURRFIFO_1 : CURRFIFO_0)); 5022 5023 /* 5024 * Determine initial values for data_addr and data_cnt 5025 * for resuming the data phase. 5026 */ 5027 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR); 5028 sgptr &= SG_PTR_MASK; 5029 5030 resid = (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 2) << 16) 5031 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 1) << 8) 5032 | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT); 5033 5034 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) { 5035 struct ahd_dma64_seg *sg; 5036 5037 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 5038 5039 /* The residual sg_ptr always points to the next sg */ 5040 sg--; 5041 5042 dataptr = aic_le64toh(sg->addr) 5043 + (aic_le32toh(sg->len) & AHD_SG_LEN_MASK) 5044 - resid; 5045 ahd_outl(ahd, HADDR + 4, dataptr >> 32); 5046 } else { 5047 struct ahd_dma_seg *sg; 5048 5049 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr); 5050 5051 /* The residual sg_ptr always points to the next sg */ 5052 sg--; 5053 5054 dataptr = aic_le32toh(sg->addr) 5055 + (aic_le32toh(sg->len) & AHD_SG_LEN_MASK) 5056 - resid; 5057 ahd_outb(ahd, HADDR + 4, 5058 (aic_le32toh(sg->len) & ~AHD_SG_LEN_MASK) >> 24); 5059 } 5060 ahd_outl(ahd, HADDR, dataptr); 5061 ahd_outb(ahd, HCNT + 2, resid >> 16); 5062 ahd_outb(ahd, HCNT + 1, resid >> 8); 5063 ahd_outb(ahd, HCNT, resid); 5064 } 5065 5066 /* 5067 * Handle the effects of issuing a bus device reset message. 5068 */ 5069 static void 5070 ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 5071 u_int lun, cam_status status, char *message, 5072 int verbose_level) 5073 { 5074 #ifdef AHD_TARGET_MODE 5075 struct ahd_tmode_tstate* tstate; 5076 #endif 5077 int found; 5078 5079 found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel, 5080 lun, SCB_LIST_NULL, devinfo->role, 5081 status); 5082 5083 #ifdef AHD_TARGET_MODE 5084 /* 5085 * Send an immediate notify ccb to all target mord peripheral 5086 * drivers affected by this action. 5087 */ 5088 tstate = ahd->enabled_targets[devinfo->our_scsiid]; 5089 if (tstate != NULL) { 5090 u_int cur_lun; 5091 u_int max_lun; 5092 5093 if (lun != CAM_LUN_WILDCARD) { 5094 cur_lun = 0; 5095 max_lun = AHD_NUM_LUNS - 1; 5096 } else { 5097 cur_lun = lun; 5098 max_lun = lun; 5099 } 5100 for (cur_lun <= max_lun; cur_lun++) { 5101 struct ahd_tmode_lstate* lstate; 5102 5103 lstate = tstate->enabled_luns[cur_lun]; 5104 if (lstate == NULL) 5105 continue; 5106 5107 ahd_queue_lstate_event(ahd, lstate, devinfo->our_scsiid, 5108 MSG_BUS_DEV_RESET, /*arg*/0); 5109 ahd_send_lstate_events(ahd, lstate); 5110 } 5111 } 5112 #endif 5113 5114 /* 5115 * Go back to async/narrow transfers and renegotiate. 5116 */ 5117 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 5118 AHD_TRANS_CUR, /*paused*/TRUE); 5119 ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0, 5120 /*ppr_options*/0, AHD_TRANS_CUR, 5121 /*paused*/TRUE); 5122 5123 if (status != CAM_SEL_TIMEOUT) 5124 ahd_send_async(ahd, devinfo->channel, devinfo->target, 5125 lun, AC_SENT_BDR, NULL); 5126 5127 if (message != NULL 5128 && (verbose_level <= bootverbose)) { 5129 AHD_CORRECTABLE_ERROR(ahd); 5130 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd), 5131 message, devinfo->channel, devinfo->target, found); 5132 } 5133 } 5134 5135 #ifdef AHD_TARGET_MODE 5136 static void 5137 ahd_setup_target_msgin(struct ahd_softc *ahd, struct ahd_devinfo *devinfo, 5138 struct scb *scb) 5139 { 5140 5141 /* 5142 * To facilitate adding multiple messages together, 5143 * each routine should increment the index and len 5144 * variables instead of setting them explicitly. 5145 */ 5146 ahd->msgout_index = 0; 5147 ahd->msgout_len = 0; 5148 5149 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 5150 ahd_build_transfer_msg(ahd, devinfo); 5151 else 5152 panic("ahd_intr: AWAITING target message with no message"); 5153 5154 ahd->msgout_index = 0; 5155 ahd->msg_type = MSG_TYPE_TARGET_MSGIN; 5156 } 5157 #endif 5158 /**************************** Initialization **********************************/ 5159 static u_int 5160 ahd_sglist_size(struct ahd_softc *ahd) 5161 { 5162 bus_size_t list_size; 5163 5164 list_size = sizeof(struct ahd_dma_seg) * AHD_NSEG; 5165 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 5166 list_size = sizeof(struct ahd_dma64_seg) * AHD_NSEG; 5167 return (list_size); 5168 } 5169 5170 /* 5171 * Calculate the optimum S/G List allocation size. S/G elements used 5172 * for a given transaction must be physically contiguous. Assume the 5173 * OS will allocate full pages to us, so it doesn't make sense to request 5174 * less than a page. 5175 */ 5176 static u_int 5177 ahd_sglist_allocsize(struct ahd_softc *ahd) 5178 { 5179 bus_size_t sg_list_increment; 5180 bus_size_t sg_list_size; 5181 bus_size_t max_list_size; 5182 bus_size_t best_list_size; 5183 5184 /* Start out with the minimum required for AHD_NSEG. */ 5185 sg_list_increment = ahd_sglist_size(ahd); 5186 sg_list_size = sg_list_increment; 5187 5188 /* Get us as close as possible to a page in size. */ 5189 while ((sg_list_size + sg_list_increment) <= PAGE_SIZE) 5190 sg_list_size += sg_list_increment; 5191 5192 /* 5193 * Try to reduce the amount of wastage by allocating 5194 * multiple pages. 5195 */ 5196 best_list_size = sg_list_size; 5197 max_list_size = roundup(sg_list_increment, PAGE_SIZE); 5198 if (max_list_size < 4 * PAGE_SIZE) 5199 max_list_size = 4 * PAGE_SIZE; 5200 if (max_list_size > (AHD_SCB_MAX_ALLOC * sg_list_increment)) 5201 max_list_size = (AHD_SCB_MAX_ALLOC * sg_list_increment); 5202 while ((sg_list_size + sg_list_increment) <= max_list_size 5203 && (sg_list_size % PAGE_SIZE) != 0) { 5204 bus_size_t new_mod; 5205 bus_size_t best_mod; 5206 5207 sg_list_size += sg_list_increment; 5208 new_mod = sg_list_size % PAGE_SIZE; 5209 best_mod = best_list_size % PAGE_SIZE; 5210 if (new_mod > best_mod || new_mod == 0) { 5211 best_list_size = sg_list_size; 5212 } 5213 } 5214 return (best_list_size); 5215 } 5216 5217 /* 5218 * Allocate a controller structure for a new device 5219 * and perform initial initializion. 5220 */ 5221 struct ahd_softc * 5222 ahd_alloc(void *platform_arg, char *name) 5223 { 5224 struct ahd_softc *ahd; 5225 5226 #ifndef __FreeBSD__ 5227 ahd = malloc(sizeof(*ahd), M_DEVBUF, M_NOWAIT); 5228 if (!ahd) { 5229 printf("aic7xxx: cannot malloc softc!\n"); 5230 free(name, M_DEVBUF); 5231 return NULL; 5232 } 5233 #else 5234 ahd = device_get_softc((device_t)platform_arg); 5235 #endif 5236 memset(ahd, 0, sizeof(*ahd)); 5237 ahd->seep_config = malloc(sizeof(*ahd->seep_config), 5238 M_DEVBUF, M_NOWAIT); 5239 if (ahd->seep_config == NULL) { 5240 #ifndef __FreeBSD__ 5241 free(ahd, M_DEVBUF); 5242 #endif 5243 free(name, M_DEVBUF); 5244 return (NULL); 5245 } 5246 LIST_INIT(&ahd->pending_scbs); 5247 LIST_INIT(&ahd->timedout_scbs); 5248 /* We don't know our unit number until the OSM sets it */ 5249 ahd->name = name; 5250 ahd->unit = -1; 5251 ahd->description = NULL; 5252 ahd->bus_description = NULL; 5253 ahd->channel = 'A'; 5254 ahd->chip = AHD_NONE; 5255 ahd->features = AHD_FENONE; 5256 ahd->bugs = AHD_BUGNONE; 5257 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A 5258 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A; 5259 aic_timer_init(&ahd->reset_timer); 5260 aic_timer_init(&ahd->stat_timer); 5261 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT; 5262 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT; 5263 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT; 5264 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT; 5265 ahd->int_coalescing_stop_threshold = 5266 AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT; 5267 5268 if (ahd_platform_alloc(ahd, platform_arg) != 0) { 5269 ahd_free(ahd); 5270 ahd = NULL; 5271 } 5272 ahd_lockinit(ahd); 5273 #ifdef AHD_DEBUG 5274 if ((ahd_debug & AHD_SHOW_MEMORY) != 0) { 5275 printf("%s: scb size = 0x%x, hscb size = 0x%x\n", 5276 ahd_name(ahd), (u_int)sizeof(struct scb), 5277 (u_int)sizeof(struct hardware_scb)); 5278 } 5279 #endif 5280 return (ahd); 5281 } 5282 5283 int 5284 ahd_softc_init(struct ahd_softc *ahd) 5285 { 5286 5287 ahd->unpause = 0; 5288 ahd->pause = PAUSE; 5289 return (0); 5290 } 5291 5292 void 5293 ahd_softc_insert(struct ahd_softc *ahd) 5294 { 5295 struct ahd_softc *list_ahd; 5296 5297 #if AIC_PCI_CONFIG > 0 5298 /* 5299 * Second Function PCI devices need to inherit some 5300 * settings from function 0. 5301 */ 5302 if ((ahd->features & AHD_MULTI_FUNC) != 0) { 5303 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) { 5304 aic_dev_softc_t list_pci; 5305 aic_dev_softc_t pci; 5306 5307 list_pci = list_ahd->dev_softc; 5308 pci = ahd->dev_softc; 5309 if (aic_get_pci_slot(list_pci) == aic_get_pci_slot(pci) 5310 && aic_get_pci_bus(list_pci) == aic_get_pci_bus(pci)) { 5311 struct ahd_softc *master; 5312 struct ahd_softc *slave; 5313 5314 if (aic_get_pci_function(list_pci) == 0) { 5315 master = list_ahd; 5316 slave = ahd; 5317 } else { 5318 master = ahd; 5319 slave = list_ahd; 5320 } 5321 slave->flags &= ~AHD_BIOS_ENABLED; 5322 slave->flags |= 5323 master->flags & AHD_BIOS_ENABLED; 5324 break; 5325 } 5326 } 5327 } 5328 #endif 5329 5330 /* 5331 * Insertion sort into our list of softcs. 5332 */ 5333 list_ahd = TAILQ_FIRST(&ahd_tailq); 5334 while (list_ahd != NULL 5335 && ahd_softc_comp(ahd, list_ahd) <= 0) 5336 list_ahd = TAILQ_NEXT(list_ahd, links); 5337 if (list_ahd != NULL) 5338 TAILQ_INSERT_BEFORE(list_ahd, ahd, links); 5339 else 5340 TAILQ_INSERT_TAIL(&ahd_tailq, ahd, links); 5341 ahd->init_level++; 5342 } 5343 5344 void 5345 ahd_set_unit(struct ahd_softc *ahd, int unit) 5346 { 5347 ahd->unit = unit; 5348 } 5349 5350 void 5351 ahd_set_name(struct ahd_softc *ahd, char *name) 5352 { 5353 if (ahd->name != NULL) 5354 free(ahd->name, M_DEVBUF); 5355 ahd->name = name; 5356 } 5357 5358 void 5359 ahd_free(struct ahd_softc *ahd) 5360 { 5361 int i; 5362 5363 ahd_terminate_recovery_thread(ahd); 5364 switch (ahd->init_level) { 5365 default: 5366 case 5: 5367 ahd_shutdown(ahd); 5368 /* FALLTHROUGH */ 5369 case 4: 5370 aic_dmamap_unload(ahd, ahd->shared_data_dmat, 5371 ahd->shared_data_map.dmamap); 5372 /* FALLTHROUGH */ 5373 case 3: 5374 aic_dmamem_free(ahd, ahd->shared_data_dmat, ahd->qoutfifo, 5375 ahd->shared_data_map.dmamap); 5376 /* FALLTHROUGH */ 5377 case 2: 5378 aic_dma_tag_destroy(ahd, ahd->shared_data_dmat); 5379 case 1: 5380 #ifndef __linux__ 5381 aic_dma_tag_destroy(ahd, ahd->buffer_dmat); 5382 #endif 5383 break; 5384 case 0: 5385 break; 5386 } 5387 5388 #ifndef __linux__ 5389 aic_dma_tag_destroy(ahd, ahd->parent_dmat); 5390 #endif 5391 ahd_platform_free(ahd); 5392 ahd_fini_scbdata(ahd); 5393 for (i = 0; i < AHD_NUM_TARGETS; i++) { 5394 struct ahd_tmode_tstate *tstate; 5395 5396 tstate = ahd->enabled_targets[i]; 5397 if (tstate != NULL) { 5398 #ifdef AHD_TARGET_MODE 5399 int j; 5400 5401 for (j = 0; j < AHD_NUM_LUNS; j++) { 5402 struct ahd_tmode_lstate *lstate; 5403 5404 lstate = tstate->enabled_luns[j]; 5405 if (lstate != NULL) { 5406 xpt_free_path(lstate->path); 5407 free(lstate, M_DEVBUF); 5408 } 5409 } 5410 #endif 5411 free(tstate, M_DEVBUF); 5412 } 5413 } 5414 #ifdef AHD_TARGET_MODE 5415 if (ahd->black_hole != NULL) { 5416 xpt_free_path(ahd->black_hole->path); 5417 free(ahd->black_hole, M_DEVBUF); 5418 } 5419 #endif 5420 if (ahd->name != NULL) 5421 free(ahd->name, M_DEVBUF); 5422 if (ahd->seep_config != NULL) 5423 free(ahd->seep_config, M_DEVBUF); 5424 if (ahd->saved_stack != NULL) 5425 free(ahd->saved_stack, M_DEVBUF); 5426 #ifndef __FreeBSD__ 5427 free(ahd, M_DEVBUF); 5428 #endif 5429 return; 5430 } 5431 5432 void 5433 ahd_shutdown(void *arg) 5434 { 5435 struct ahd_softc *ahd; 5436 5437 ahd = (struct ahd_softc *)arg; 5438 5439 /* 5440 * Stop periodic timer callbacks. 5441 */ 5442 aic_timer_stop(&ahd->reset_timer); 5443 aic_timer_stop(&ahd->stat_timer); 5444 5445 /* This will reset most registers to 0, but not all */ 5446 ahd_reset(ahd, /*reinit*/FALSE); 5447 } 5448 5449 /* 5450 * Reset the controller and record some information about it 5451 * that is only available just after a reset. If "reinit" is 5452 * non-zero, this reset occurred after initial configuration 5453 * and the caller requests that the chip be fully reinitialized 5454 * to a runable state. Chip interrupts are *not* enabled after 5455 * a reinitialization. The caller must enable interrupts via 5456 * ahd_intr_enable(). 5457 */ 5458 int 5459 ahd_reset(struct ahd_softc *ahd, int reinit) 5460 { 5461 u_int sxfrctl1; 5462 int wait; 5463 uint32_t cmd; 5464 5465 /* 5466 * Preserve the value of the SXFRCTL1 register for all channels. 5467 * It contains settings that affect termination and we don't want 5468 * to disturb the integrity of the bus. 5469 */ 5470 ahd_pause(ahd); 5471 ahd_update_modes(ahd); 5472 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5473 sxfrctl1 = ahd_inb(ahd, SXFRCTL1); 5474 5475 cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); 5476 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { 5477 uint32_t mod_cmd; 5478 5479 /* 5480 * A4 Razor #632 5481 * During the assertion of CHIPRST, the chip 5482 * does not disable its parity logic prior to 5483 * the start of the reset. This may cause a 5484 * parity error to be detected and thus a 5485 * spurious SERR or PERR assertion. Disable 5486 * PERR and SERR responses during the CHIPRST. 5487 */ 5488 mod_cmd = cmd & ~(PCIM_CMD_PERRESPEN|PCIM_CMD_SERRESPEN); 5489 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 5490 mod_cmd, /*bytes*/2); 5491 } 5492 ahd_outb(ahd, HCNTRL, CHIPRST | ahd->pause); 5493 5494 /* 5495 * Ensure that the reset has finished. We delay 1000us 5496 * prior to reading the register to make sure the chip 5497 * has sufficiently completed its reset to handle register 5498 * accesses. 5499 */ 5500 wait = 1000; 5501 do { 5502 aic_delay(1000); 5503 } while (--wait && !(ahd_inb(ahd, HCNTRL) & CHIPRSTACK)); 5504 5505 if (wait == 0) { 5506 printf("%s: WARNING - Failed chip reset! " 5507 "Trying to initialize anyway.\n", ahd_name(ahd)); 5508 AHD_FATAL_ERROR(ahd); 5509 } 5510 ahd_outb(ahd, HCNTRL, ahd->pause); 5511 5512 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) { 5513 /* 5514 * Clear any latched PCI error status and restore 5515 * previous SERR and PERR response enables. 5516 */ 5517 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, 5518 0xFF, /*bytes*/1); 5519 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 5520 cmd, /*bytes*/2); 5521 } 5522 5523 /* 5524 * Mode should be SCSI after a chip reset, but lets 5525 * set it just to be safe. We touch the MODE_PTR 5526 * register directly so as to bypass the lazy update 5527 * code in ahd_set_modes(). 5528 */ 5529 ahd_known_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5530 ahd_outb(ahd, MODE_PTR, 5531 ahd_build_mode_state(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI)); 5532 5533 /* 5534 * Restore SXFRCTL1. 5535 * 5536 * We must always initialize STPWEN to 1 before we 5537 * restore the saved values. STPWEN is initialized 5538 * to a tri-state condition which can only be cleared 5539 * by turning it on. 5540 */ 5541 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); 5542 ahd_outb(ahd, SXFRCTL1, sxfrctl1); 5543 5544 /* Determine chip configuration */ 5545 ahd->features &= ~AHD_WIDE; 5546 if ((ahd_inb(ahd, SBLKCTL) & SELWIDE) != 0) 5547 ahd->features |= AHD_WIDE; 5548 5549 /* 5550 * If a recovery action has forced a chip reset, 5551 * re-initialize the chip to our liking. 5552 */ 5553 if (reinit != 0) 5554 ahd_chip_init(ahd); 5555 5556 return (0); 5557 } 5558 5559 /* 5560 * Determine the number of SCBs available on the controller 5561 */ 5562 int 5563 ahd_probe_scbs(struct ahd_softc *ahd) { 5564 int i; 5565 5566 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK), 5567 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK)); 5568 for (i = 0; i < AHD_SCB_MAX; i++) { 5569 int j; 5570 5571 ahd_set_scbptr(ahd, i); 5572 ahd_outw(ahd, SCB_BASE, i); 5573 for (j = 2; j < 64; j++) 5574 ahd_outb(ahd, SCB_BASE+j, 0); 5575 /* Start out life as unallocated (needing an abort) */ 5576 ahd_outb(ahd, SCB_CONTROL, MK_MESSAGE); 5577 if (ahd_inw_scbram(ahd, SCB_BASE) != i) 5578 break; 5579 ahd_set_scbptr(ahd, 0); 5580 if (ahd_inw_scbram(ahd, SCB_BASE) != 0) 5581 break; 5582 } 5583 return (i); 5584 } 5585 5586 static void 5587 ahd_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 5588 { 5589 bus_addr_t *baddr; 5590 5591 baddr = (bus_addr_t *)arg; 5592 *baddr = segs->ds_addr; 5593 } 5594 5595 static void 5596 ahd_initialize_hscbs(struct ahd_softc *ahd) 5597 { 5598 int i; 5599 5600 for (i = 0; i < ahd->scb_data.maxhscbs; i++) { 5601 ahd_set_scbptr(ahd, i); 5602 5603 /* Clear the control byte. */ 5604 ahd_outb(ahd, SCB_CONTROL, 0); 5605 5606 /* Set the next pointer */ 5607 ahd_outw(ahd, SCB_NEXT, SCB_LIST_NULL); 5608 } 5609 } 5610 5611 static int 5612 ahd_init_scbdata(struct ahd_softc *ahd) 5613 { 5614 struct scb_data *scb_data; 5615 int i; 5616 5617 scb_data = &ahd->scb_data; 5618 TAILQ_INIT(&scb_data->free_scbs); 5619 for (i = 0; i < AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT; i++) 5620 LIST_INIT(&scb_data->free_scb_lists[i]); 5621 LIST_INIT(&scb_data->any_dev_free_scb_list); 5622 SLIST_INIT(&scb_data->hscb_maps); 5623 SLIST_INIT(&scb_data->sg_maps); 5624 SLIST_INIT(&scb_data->sense_maps); 5625 5626 /* Determine the number of hardware SCBs and initialize them */ 5627 scb_data->maxhscbs = ahd_probe_scbs(ahd); 5628 if (scb_data->maxhscbs == 0) { 5629 printf("%s: No SCB space found\n", ahd_name(ahd)); 5630 AHD_FATAL_ERROR(ahd); 5631 return (ENXIO); 5632 } 5633 5634 ahd_initialize_hscbs(ahd); 5635 5636 /* 5637 * Create our DMA tags. These tags define the kinds of device 5638 * accessible memory allocations and memory mappings we will 5639 * need to perform during normal operation. 5640 * 5641 * Unless we need to further restrict the allocation, we rely 5642 * on the restrictions of the parent dmat, hence the common 5643 * use of MAXADDR and MAXSIZE. 5644 */ 5645 5646 /* DMA tag for our hardware scb structures */ 5647 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1, 5648 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 5649 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 5650 /*highaddr*/BUS_SPACE_MAXADDR, 5651 /*filter*/NULL, /*filterarg*/NULL, 5652 PAGE_SIZE, /*nsegments*/1, 5653 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 5654 /*flags*/0, &scb_data->hscb_dmat) != 0) { 5655 goto error_exit; 5656 } 5657 5658 scb_data->init_level++; 5659 5660 /* DMA tag for our S/G structures. */ 5661 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/8, 5662 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 5663 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 5664 /*highaddr*/BUS_SPACE_MAXADDR, 5665 /*filter*/NULL, /*filterarg*/NULL, 5666 ahd_sglist_allocsize(ahd), /*nsegments*/1, 5667 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 5668 /*flags*/0, &scb_data->sg_dmat) != 0) { 5669 goto error_exit; 5670 } 5671 #ifdef AHD_DEBUG 5672 if ((ahd_debug & AHD_SHOW_MEMORY) != 0) 5673 printf("%s: ahd_sglist_allocsize = 0x%x\n", ahd_name(ahd), 5674 ahd_sglist_allocsize(ahd)); 5675 #endif 5676 5677 scb_data->init_level++; 5678 5679 /* DMA tag for our sense buffers. We allocate in page sized chunks */ 5680 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1, 5681 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 5682 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 5683 /*highaddr*/BUS_SPACE_MAXADDR, 5684 /*filter*/NULL, /*filterarg*/NULL, 5685 PAGE_SIZE, /*nsegments*/1, 5686 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 5687 /*flags*/0, &scb_data->sense_dmat) != 0) { 5688 goto error_exit; 5689 } 5690 5691 scb_data->init_level++; 5692 5693 /* Perform initial CCB allocation */ 5694 while (ahd_alloc_scbs(ahd) != 0) 5695 ; 5696 5697 if (scb_data->numscbs == 0) { 5698 printf("%s: ahd_init_scbdata - " 5699 "Unable to allocate initial scbs\n", 5700 ahd_name(ahd)); 5701 goto error_exit; 5702 } 5703 5704 /* 5705 * Note that we were successful 5706 */ 5707 return (0); 5708 5709 error_exit: 5710 5711 return (ENOMEM); 5712 } 5713 5714 static struct scb * 5715 ahd_find_scb_by_tag(struct ahd_softc *ahd, u_int tag) 5716 { 5717 struct scb *scb; 5718 5719 /* 5720 * Look on the pending list. 5721 */ 5722 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 5723 if (SCB_GET_TAG(scb) == tag) 5724 return (scb); 5725 } 5726 5727 /* 5728 * Then on all of the collision free lists. 5729 */ 5730 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 5731 struct scb *list_scb; 5732 5733 list_scb = scb; 5734 do { 5735 if (SCB_GET_TAG(list_scb) == tag) 5736 return (list_scb); 5737 list_scb = LIST_NEXT(list_scb, collision_links); 5738 } while (list_scb); 5739 } 5740 5741 /* 5742 * And finally on the generic free list. 5743 */ 5744 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { 5745 if (SCB_GET_TAG(scb) == tag) 5746 return (scb); 5747 } 5748 5749 return (NULL); 5750 } 5751 5752 static void 5753 ahd_fini_scbdata(struct ahd_softc *ahd) 5754 { 5755 struct scb_data *scb_data; 5756 5757 scb_data = &ahd->scb_data; 5758 if (scb_data == NULL) 5759 return; 5760 5761 switch (scb_data->init_level) { 5762 default: 5763 case 7: 5764 { 5765 struct map_node *sns_map; 5766 5767 while ((sns_map = SLIST_FIRST(&scb_data->sense_maps)) != NULL) { 5768 SLIST_REMOVE_HEAD(&scb_data->sense_maps, links); 5769 aic_dmamap_unload(ahd, scb_data->sense_dmat, 5770 sns_map->dmamap); 5771 aic_dmamem_free(ahd, scb_data->sense_dmat, 5772 sns_map->vaddr, sns_map->dmamap); 5773 free(sns_map, M_DEVBUF); 5774 } 5775 aic_dma_tag_destroy(ahd, scb_data->sense_dmat); 5776 /* FALLTHROUGH */ 5777 } 5778 case 6: 5779 { 5780 struct map_node *sg_map; 5781 5782 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)) != NULL) { 5783 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 5784 aic_dmamap_unload(ahd, scb_data->sg_dmat, 5785 sg_map->dmamap); 5786 aic_dmamem_free(ahd, scb_data->sg_dmat, 5787 sg_map->vaddr, sg_map->dmamap); 5788 free(sg_map, M_DEVBUF); 5789 } 5790 aic_dma_tag_destroy(ahd, scb_data->sg_dmat); 5791 /* FALLTHROUGH */ 5792 } 5793 case 5: 5794 { 5795 struct map_node *hscb_map; 5796 5797 while ((hscb_map = SLIST_FIRST(&scb_data->hscb_maps)) != NULL) { 5798 SLIST_REMOVE_HEAD(&scb_data->hscb_maps, links); 5799 aic_dmamap_unload(ahd, scb_data->hscb_dmat, 5800 hscb_map->dmamap); 5801 aic_dmamem_free(ahd, scb_data->hscb_dmat, 5802 hscb_map->vaddr, hscb_map->dmamap); 5803 free(hscb_map, M_DEVBUF); 5804 } 5805 aic_dma_tag_destroy(ahd, scb_data->hscb_dmat); 5806 /* FALLTHROUGH */ 5807 } 5808 case 4: 5809 case 3: 5810 case 2: 5811 case 1: 5812 case 0: 5813 break; 5814 } 5815 } 5816 5817 /* 5818 * DSP filter Bypass must be enabled until the first selection 5819 * after a change in bus mode (Razor #491 and #493). 5820 */ 5821 static void 5822 ahd_setup_iocell_workaround(struct ahd_softc *ahd) 5823 { 5824 ahd_mode_state saved_modes; 5825 5826 saved_modes = ahd_save_modes(ahd); 5827 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5828 ahd_outb(ahd, DSPDATACTL, ahd_inb(ahd, DSPDATACTL) 5829 | BYPASSENAB | RCVROFFSTDIS | XMITOFFSTDIS); 5830 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) | (ENSELDO|ENSELDI)); 5831 #ifdef AHD_DEBUG 5832 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5833 printf("%s: Setting up iocell workaround\n", ahd_name(ahd)); 5834 #endif 5835 ahd_restore_modes(ahd, saved_modes); 5836 ahd->flags &= ~AHD_HAD_FIRST_SEL; 5837 } 5838 5839 static void 5840 ahd_iocell_first_selection(struct ahd_softc *ahd) 5841 { 5842 ahd_mode_state saved_modes; 5843 u_int sblkctl; 5844 5845 if ((ahd->flags & AHD_HAD_FIRST_SEL) != 0) 5846 return; 5847 saved_modes = ahd_save_modes(ahd); 5848 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 5849 sblkctl = ahd_inb(ahd, SBLKCTL); 5850 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 5851 #ifdef AHD_DEBUG 5852 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5853 printf("%s: iocell first selection\n", ahd_name(ahd)); 5854 #endif 5855 if ((sblkctl & ENAB40) != 0) { 5856 ahd_outb(ahd, DSPDATACTL, 5857 ahd_inb(ahd, DSPDATACTL) & ~BYPASSENAB); 5858 #ifdef AHD_DEBUG 5859 if ((ahd_debug & AHD_SHOW_MISC) != 0) 5860 printf("%s: BYPASS now disabled\n", ahd_name(ahd)); 5861 #endif 5862 } 5863 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) & ~(ENSELDO|ENSELDI)); 5864 ahd_outb(ahd, CLRINT, CLRSCSIINT); 5865 ahd_restore_modes(ahd, saved_modes); 5866 ahd->flags |= AHD_HAD_FIRST_SEL; 5867 } 5868 5869 /*************************** SCB Management ***********************************/ 5870 static void 5871 ahd_add_col_list(struct ahd_softc *ahd, struct scb *scb, u_int col_idx) 5872 { 5873 struct scb_list *free_list; 5874 struct scb_tailq *free_tailq; 5875 struct scb *first_scb; 5876 5877 scb->flags |= SCB_ON_COL_LIST; 5878 AHD_SET_SCB_COL_IDX(scb, col_idx); 5879 free_list = &ahd->scb_data.free_scb_lists[col_idx]; 5880 free_tailq = &ahd->scb_data.free_scbs; 5881 first_scb = LIST_FIRST(free_list); 5882 if (first_scb != NULL) { 5883 LIST_INSERT_AFTER(first_scb, scb, collision_links); 5884 } else { 5885 LIST_INSERT_HEAD(free_list, scb, collision_links); 5886 TAILQ_INSERT_TAIL(free_tailq, scb, links.tqe); 5887 } 5888 } 5889 5890 static void 5891 ahd_rem_col_list(struct ahd_softc *ahd, struct scb *scb) 5892 { 5893 struct scb_list *free_list; 5894 struct scb_tailq *free_tailq; 5895 struct scb *first_scb; 5896 u_int col_idx; 5897 5898 scb->flags &= ~SCB_ON_COL_LIST; 5899 col_idx = AHD_GET_SCB_COL_IDX(ahd, scb); 5900 free_list = &ahd->scb_data.free_scb_lists[col_idx]; 5901 free_tailq = &ahd->scb_data.free_scbs; 5902 first_scb = LIST_FIRST(free_list); 5903 if (first_scb == scb) { 5904 struct scb *next_scb; 5905 5906 /* 5907 * Maintain order in the collision free 5908 * lists for fairness if this device has 5909 * other colliding tags active. 5910 */ 5911 next_scb = LIST_NEXT(scb, collision_links); 5912 if (next_scb != NULL) { 5913 TAILQ_INSERT_AFTER(free_tailq, scb, 5914 next_scb, links.tqe); 5915 } 5916 TAILQ_REMOVE(free_tailq, scb, links.tqe); 5917 } 5918 LIST_REMOVE(scb, collision_links); 5919 } 5920 5921 /* 5922 * Get a free scb. If there are none, see if we can allocate a new SCB. 5923 */ 5924 struct scb * 5925 ahd_get_scb(struct ahd_softc *ahd, u_int col_idx) 5926 { 5927 struct scb *scb; 5928 int tries; 5929 5930 tries = 0; 5931 look_again: 5932 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 5933 if (AHD_GET_SCB_COL_IDX(ahd, scb) != col_idx) { 5934 ahd_rem_col_list(ahd, scb); 5935 goto found; 5936 } 5937 } 5938 if ((scb = LIST_FIRST(&ahd->scb_data.any_dev_free_scb_list)) == NULL) { 5939 if (tries++ != 0) 5940 return (NULL); 5941 if (ahd_alloc_scbs(ahd) == 0) 5942 return (NULL); 5943 goto look_again; 5944 } 5945 LIST_REMOVE(scb, links.le); 5946 if (col_idx != AHD_NEVER_COL_IDX 5947 && (scb->col_scb != NULL) 5948 && (scb->col_scb->flags & SCB_ACTIVE) == 0) { 5949 LIST_REMOVE(scb->col_scb, links.le); 5950 ahd_add_col_list(ahd, scb->col_scb, col_idx); 5951 } 5952 found: 5953 scb->flags |= SCB_ACTIVE; 5954 return (scb); 5955 } 5956 5957 /* 5958 * Return an SCB resource to the free list. 5959 */ 5960 void 5961 ahd_free_scb(struct ahd_softc *ahd, struct scb *scb) 5962 { 5963 5964 /* Clean up for the next user */ 5965 scb->flags = SCB_FLAG_NONE; 5966 scb->hscb->control = 0; 5967 ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = NULL; 5968 5969 if (scb->col_scb == NULL) { 5970 /* 5971 * No collision possible. Just free normally. 5972 */ 5973 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5974 scb, links.le); 5975 } else if ((scb->col_scb->flags & SCB_ON_COL_LIST) != 0) { 5976 /* 5977 * The SCB we might have collided with is on 5978 * a free collision list. Put both SCBs on 5979 * the generic list. 5980 */ 5981 ahd_rem_col_list(ahd, scb->col_scb); 5982 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5983 scb, links.le); 5984 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 5985 scb->col_scb, links.le); 5986 } else if ((scb->col_scb->flags 5987 & (SCB_PACKETIZED|SCB_ACTIVE)) == SCB_ACTIVE 5988 && (scb->col_scb->hscb->control & TAG_ENB) != 0) { 5989 /* 5990 * The SCB we might collide with on the next allocation 5991 * is still active in a non-packetized, tagged, context. 5992 * Put us on the SCB collision list. 5993 */ 5994 ahd_add_col_list(ahd, scb, 5995 AHD_GET_SCB_COL_IDX(ahd, scb->col_scb)); 5996 } else { 5997 /* 5998 * The SCB we might collide with on the next allocation 5999 * is either active in a packetized context, or free. 6000 * Since we can't collide, put this SCB on the generic 6001 * free list. 6002 */ 6003 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list, 6004 scb, links.le); 6005 } 6006 6007 aic_platform_scb_free(ahd, scb); 6008 } 6009 6010 int 6011 ahd_alloc_scbs(struct ahd_softc *ahd) 6012 { 6013 struct scb_data *scb_data; 6014 struct scb *next_scb; 6015 struct hardware_scb *hscb; 6016 struct map_node *hscb_map; 6017 struct map_node *sg_map; 6018 struct map_node *sense_map; 6019 uint8_t *segs; 6020 uint8_t *sense_data; 6021 bus_addr_t hscb_busaddr; 6022 bus_addr_t sg_busaddr; 6023 bus_addr_t sense_busaddr; 6024 int newcount; 6025 int i; 6026 6027 scb_data = &ahd->scb_data; 6028 if (scb_data->numscbs >= AHD_SCB_MAX_ALLOC) 6029 /* Can't allocate any more */ 6030 return (0); 6031 6032 if (scb_data->scbs_left != 0) { 6033 int offset; 6034 6035 offset = (PAGE_SIZE / sizeof(*hscb)) - scb_data->scbs_left; 6036 hscb_map = SLIST_FIRST(&scb_data->hscb_maps); 6037 hscb = &((struct hardware_scb *)hscb_map->vaddr)[offset]; 6038 hscb_busaddr = hscb_map->busaddr + (offset * sizeof(*hscb)); 6039 } else { 6040 hscb_map = malloc(sizeof(*hscb_map), M_DEVBUF, M_NOWAIT); 6041 6042 if (hscb_map == NULL) 6043 return (0); 6044 6045 /* Allocate the next batch of hardware SCBs */ 6046 if (aic_dmamem_alloc(ahd, scb_data->hscb_dmat, 6047 (void **)&hscb_map->vaddr, 6048 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 6049 &hscb_map->dmamap) != 0) { 6050 free(hscb_map, M_DEVBUF); 6051 return (0); 6052 } 6053 6054 SLIST_INSERT_HEAD(&scb_data->hscb_maps, hscb_map, links); 6055 6056 aic_dmamap_load(ahd, scb_data->hscb_dmat, hscb_map->dmamap, 6057 hscb_map->vaddr, PAGE_SIZE, ahd_dmamap_cb, 6058 &hscb_map->busaddr, /*flags*/0); 6059 6060 hscb = (struct hardware_scb *)hscb_map->vaddr; 6061 hscb_busaddr = hscb_map->busaddr; 6062 scb_data->scbs_left = PAGE_SIZE / sizeof(*hscb); 6063 } 6064 6065 if (scb_data->sgs_left != 0) { 6066 int offset; 6067 6068 offset = ((ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd)) 6069 - scb_data->sgs_left) * ahd_sglist_size(ahd); 6070 sg_map = SLIST_FIRST(&scb_data->sg_maps); 6071 segs = sg_map->vaddr + offset; 6072 sg_busaddr = sg_map->busaddr + offset; 6073 } else { 6074 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 6075 6076 if (sg_map == NULL) 6077 return (0); 6078 6079 /* Allocate the next batch of S/G lists */ 6080 if (aic_dmamem_alloc(ahd, scb_data->sg_dmat, 6081 (void **)&sg_map->vaddr, 6082 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 6083 &sg_map->dmamap) != 0) { 6084 free(sg_map, M_DEVBUF); 6085 return (0); 6086 } 6087 6088 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 6089 6090 aic_dmamap_load(ahd, scb_data->sg_dmat, sg_map->dmamap, 6091 sg_map->vaddr, ahd_sglist_allocsize(ahd), 6092 ahd_dmamap_cb, &sg_map->busaddr, /*flags*/0); 6093 6094 segs = sg_map->vaddr; 6095 sg_busaddr = sg_map->busaddr; 6096 scb_data->sgs_left = 6097 ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd); 6098 #ifdef AHD_DEBUG 6099 if (ahd_debug & AHD_SHOW_MEMORY) 6100 printf("Mapped SG data\n"); 6101 #endif 6102 } 6103 6104 if (scb_data->sense_left != 0) { 6105 int offset; 6106 6107 offset = PAGE_SIZE - (AHD_SENSE_BUFSIZE * scb_data->sense_left); 6108 sense_map = SLIST_FIRST(&scb_data->sense_maps); 6109 sense_data = sense_map->vaddr + offset; 6110 sense_busaddr = sense_map->busaddr + offset; 6111 } else { 6112 sense_map = malloc(sizeof(*sense_map), M_DEVBUF, M_NOWAIT); 6113 6114 if (sense_map == NULL) 6115 return (0); 6116 6117 /* Allocate the next batch of sense buffers */ 6118 if (aic_dmamem_alloc(ahd, scb_data->sense_dmat, 6119 (void **)&sense_map->vaddr, 6120 BUS_DMA_NOWAIT, &sense_map->dmamap) != 0) { 6121 free(sense_map, M_DEVBUF); 6122 return (0); 6123 } 6124 6125 SLIST_INSERT_HEAD(&scb_data->sense_maps, sense_map, links); 6126 6127 aic_dmamap_load(ahd, scb_data->sense_dmat, sense_map->dmamap, 6128 sense_map->vaddr, PAGE_SIZE, ahd_dmamap_cb, 6129 &sense_map->busaddr, /*flags*/0); 6130 6131 sense_data = sense_map->vaddr; 6132 sense_busaddr = sense_map->busaddr; 6133 scb_data->sense_left = PAGE_SIZE / AHD_SENSE_BUFSIZE; 6134 #ifdef AHD_DEBUG 6135 if (ahd_debug & AHD_SHOW_MEMORY) 6136 printf("Mapped sense data\n"); 6137 #endif 6138 } 6139 6140 newcount = MIN(scb_data->sense_left, scb_data->scbs_left); 6141 newcount = MIN(newcount, scb_data->sgs_left); 6142 newcount = MIN(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs)); 6143 scb_data->sense_left -= newcount; 6144 scb_data->scbs_left -= newcount; 6145 scb_data->sgs_left -= newcount; 6146 for (i = 0; i < newcount; i++) { 6147 struct scb_platform_data *pdata; 6148 u_int col_tag; 6149 #ifndef __linux__ 6150 int error; 6151 #endif 6152 6153 next_scb = (struct scb *)malloc(sizeof(*next_scb), 6154 M_DEVBUF, M_NOWAIT); 6155 if (next_scb == NULL) 6156 break; 6157 6158 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), 6159 M_DEVBUF, M_NOWAIT); 6160 if (pdata == NULL) { 6161 free(next_scb, M_DEVBUF); 6162 break; 6163 } 6164 next_scb->platform_data = pdata; 6165 next_scb->hscb_map = hscb_map; 6166 next_scb->sg_map = sg_map; 6167 next_scb->sense_map = sense_map; 6168 next_scb->sg_list = segs; 6169 next_scb->sense_data = sense_data; 6170 next_scb->sense_busaddr = sense_busaddr; 6171 memset(hscb, 0, sizeof(*hscb)); 6172 next_scb->hscb = hscb; 6173 hscb->hscb_busaddr = aic_htole32(hscb_busaddr); 6174 6175 /* 6176 * The sequencer always starts with the second entry. 6177 * The first entry is embedded in the scb. 6178 */ 6179 next_scb->sg_list_busaddr = sg_busaddr; 6180 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 6181 next_scb->sg_list_busaddr 6182 += sizeof(struct ahd_dma64_seg); 6183 else 6184 next_scb->sg_list_busaddr += sizeof(struct ahd_dma_seg); 6185 next_scb->ahd_softc = ahd; 6186 next_scb->flags = SCB_FLAG_NONE; 6187 #ifndef __linux__ 6188 error = aic_dmamap_create(ahd, ahd->buffer_dmat, /*flags*/0, 6189 &next_scb->dmamap); 6190 if (error != 0) { 6191 free(next_scb, M_DEVBUF); 6192 free(pdata, M_DEVBUF); 6193 break; 6194 } 6195 #endif 6196 next_scb->hscb->tag = aic_htole16(scb_data->numscbs); 6197 col_tag = scb_data->numscbs ^ 0x100; 6198 next_scb->col_scb = ahd_find_scb_by_tag(ahd, col_tag); 6199 if (next_scb->col_scb != NULL) 6200 next_scb->col_scb->col_scb = next_scb; 6201 aic_timer_init(&next_scb->io_timer); 6202 ahd_free_scb(ahd, next_scb); 6203 hscb++; 6204 hscb_busaddr += sizeof(*hscb); 6205 segs += ahd_sglist_size(ahd); 6206 sg_busaddr += ahd_sglist_size(ahd); 6207 sense_data += AHD_SENSE_BUFSIZE; 6208 sense_busaddr += AHD_SENSE_BUFSIZE; 6209 scb_data->numscbs++; 6210 } 6211 return (i); 6212 } 6213 6214 void 6215 ahd_controller_info(struct ahd_softc *ahd, char *buf) 6216 { 6217 const char *speed; 6218 const char *type; 6219 int len; 6220 6221 len = sprintf(buf, "%s: ", ahd_chip_names[ahd->chip & AHD_CHIPID_MASK]); 6222 buf += len; 6223 6224 speed = "Ultra320 "; 6225 if ((ahd->features & AHD_WIDE) != 0) { 6226 type = "Wide "; 6227 } else { 6228 type = "Single "; 6229 } 6230 len = sprintf(buf, "%s%sChannel %c, SCSI Id=%d, ", 6231 speed, type, ahd->channel, ahd->our_id); 6232 buf += len; 6233 6234 sprintf(buf, "%s, %d SCBs", ahd->bus_description, 6235 ahd->scb_data.maxhscbs); 6236 } 6237 6238 static const char *channel_strings[] = { 6239 "Primary Low", 6240 "Primary High", 6241 "Secondary Low", 6242 "Secondary High" 6243 }; 6244 6245 static const char *termstat_strings[] = { 6246 "Terminated Correctly", 6247 "Over Terminated", 6248 "Under Terminated", 6249 "Not Configured" 6250 }; 6251 6252 /* 6253 * Start the board, ready for normal operation 6254 */ 6255 int 6256 ahd_init(struct ahd_softc *ahd) 6257 { 6258 uint8_t *next_vaddr; 6259 bus_addr_t next_baddr; 6260 size_t driver_data_size; 6261 int i; 6262 int error; 6263 u_int warn_user; 6264 uint8_t current_sensing; 6265 uint8_t fstat; 6266 6267 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 6268 6269 ahd->stack_size = ahd_probe_stack_size(ahd); 6270 ahd->saved_stack = malloc(ahd->stack_size * sizeof(uint16_t), 6271 M_DEVBUF, M_NOWAIT); 6272 if (ahd->saved_stack == NULL) 6273 return (ENOMEM); 6274 6275 /* 6276 * Verify that the compiler hasn't over-agressively 6277 * padded important structures. 6278 */ 6279 if (sizeof(struct hardware_scb) != 64) 6280 panic("Hardware SCB size is incorrect"); 6281 6282 #ifdef AHD_DEBUG 6283 if ((ahd_debug & AHD_DEBUG_SEQUENCER) != 0) 6284 ahd->flags |= AHD_SEQUENCER_DEBUG; 6285 #endif 6286 6287 /* 6288 * Default to allowing initiator operations. 6289 */ 6290 ahd->flags |= AHD_INITIATORROLE; 6291 6292 /* 6293 * Only allow target mode features if this unit has them enabled. 6294 */ 6295 if ((AHD_TMODE_ENABLE & (0x1 << ahd->unit)) == 0) 6296 ahd->features &= ~AHD_TARGETMODE; 6297 6298 #ifndef __linux__ 6299 /* DMA tag for mapping buffers into device visible space. */ 6300 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1, 6301 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 6302 /*lowaddr*/ahd->flags & AHD_39BIT_ADDRESSING 6303 ? (bus_addr_t)0x7FFFFFFFFFULL 6304 : BUS_SPACE_MAXADDR_32BIT, 6305 /*highaddr*/BUS_SPACE_MAXADDR, 6306 /*filter*/NULL, /*filterarg*/NULL, 6307 /*maxsize*/(AHD_NSEG - 1) * PAGE_SIZE, 6308 /*nsegments*/AHD_NSEG, 6309 /*maxsegsz*/AHD_MAXTRANSFER_SIZE, 6310 /*flags*/BUS_DMA_ALLOCNOW, 6311 &ahd->buffer_dmat) != 0) { 6312 return (ENOMEM); 6313 } 6314 #endif 6315 6316 ahd->init_level++; 6317 6318 /* 6319 * DMA tag for our command fifos and other data in system memory 6320 * the card's sequencer must be able to access. For initiator 6321 * roles, we need to allocate space for the qoutfifo. When providing 6322 * for the target mode role, we must additionally provide space for 6323 * the incoming target command fifo. 6324 */ 6325 driver_data_size = AHD_SCB_MAX * sizeof(*ahd->qoutfifo) 6326 + sizeof(struct hardware_scb); 6327 if ((ahd->features & AHD_TARGETMODE) != 0) 6328 driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd); 6329 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) 6330 driver_data_size += PKT_OVERRUN_BUFSIZE; 6331 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1, 6332 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 6333 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 6334 /*highaddr*/BUS_SPACE_MAXADDR, 6335 /*filter*/NULL, /*filterarg*/NULL, 6336 driver_data_size, 6337 /*nsegments*/1, 6338 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 6339 /*flags*/0, &ahd->shared_data_dmat) != 0) { 6340 return (ENOMEM); 6341 } 6342 6343 ahd->init_level++; 6344 6345 /* Allocation of driver data */ 6346 if (aic_dmamem_alloc(ahd, ahd->shared_data_dmat, 6347 (void **)&ahd->shared_data_map.vaddr, 6348 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, 6349 &ahd->shared_data_map.dmamap) != 0) { 6350 return (ENOMEM); 6351 } 6352 6353 ahd->init_level++; 6354 6355 /* And permanently map it in */ 6356 aic_dmamap_load(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap, 6357 ahd->shared_data_map.vaddr, driver_data_size, 6358 ahd_dmamap_cb, &ahd->shared_data_map.busaddr, 6359 /*flags*/0); 6360 ahd->qoutfifo = (struct ahd_completion *)ahd->shared_data_map.vaddr; 6361 next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE]; 6362 next_baddr = ahd->shared_data_map.busaddr 6363 + AHD_QOUT_SIZE*sizeof(struct ahd_completion); 6364 if ((ahd->features & AHD_TARGETMODE) != 0) { 6365 ahd->targetcmds = (struct target_cmd *)next_vaddr; 6366 next_vaddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); 6367 next_baddr += AHD_TMODE_CMDS * sizeof(struct target_cmd); 6368 } 6369 6370 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) { 6371 ahd->overrun_buf = next_vaddr; 6372 next_vaddr += PKT_OVERRUN_BUFSIZE; 6373 next_baddr += PKT_OVERRUN_BUFSIZE; 6374 } 6375 6376 /* 6377 * We need one SCB to serve as the "next SCB". Since the 6378 * tag identifier in this SCB will never be used, there is 6379 * no point in using a valid HSCB tag from an SCB pulled from 6380 * the standard free pool. So, we allocate this "sentinel" 6381 * specially from the DMA safe memory chunk used for the QOUTFIFO. 6382 */ 6383 ahd->next_queued_hscb = (struct hardware_scb *)next_vaddr; 6384 ahd->next_queued_hscb_map = &ahd->shared_data_map; 6385 ahd->next_queued_hscb->hscb_busaddr = aic_htole32(next_baddr); 6386 6387 ahd->init_level++; 6388 6389 /* Allocate SCB data now that buffer_dmat is initialized */ 6390 if (ahd_init_scbdata(ahd) != 0) 6391 return (ENOMEM); 6392 6393 if ((ahd->flags & AHD_INITIATORROLE) == 0) 6394 ahd->flags &= ~AHD_RESET_BUS_A; 6395 6396 /* 6397 * Before committing these settings to the chip, give 6398 * the OSM one last chance to modify our configuration. 6399 */ 6400 ahd_platform_init(ahd); 6401 6402 /* Bring up the chip. */ 6403 ahd_chip_init(ahd); 6404 6405 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 6406 6407 if ((ahd->flags & AHD_CURRENT_SENSING) == 0) 6408 goto init_done; 6409 6410 /* 6411 * Verify termination based on current draw and 6412 * warn user if the bus is over/under terminated. 6413 */ 6414 error = ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 6415 CURSENSE_ENB); 6416 if (error != 0) { 6417 printf("%s: current sensing timeout 1\n", ahd_name(ahd)); 6418 goto init_done; 6419 } 6420 for (i = 20, fstat = FLX_FSTAT_BUSY; 6421 (fstat & FLX_FSTAT_BUSY) != 0 && i; i--) { 6422 error = ahd_read_flexport(ahd, FLXADDR_FLEXSTAT, &fstat); 6423 if (error != 0) { 6424 printf("%s: current sensing timeout 2\n", 6425 ahd_name(ahd)); 6426 goto init_done; 6427 } 6428 } 6429 if (i == 0) { 6430 printf("%s: Timedout during current-sensing test\n", 6431 ahd_name(ahd)); 6432 goto init_done; 6433 } 6434 6435 /* Latch Current Sensing status. */ 6436 error = ahd_read_flexport(ahd, FLXADDR_CURRENT_STAT, ¤t_sensing); 6437 if (error != 0) { 6438 printf("%s: current sensing timeout 3\n", ahd_name(ahd)); 6439 goto init_done; 6440 } 6441 6442 /* Diable current sensing. */ 6443 ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); 6444 6445 #ifdef AHD_DEBUG 6446 if ((ahd_debug & AHD_SHOW_TERMCTL) != 0) { 6447 printf("%s: current_sensing == 0x%x\n", 6448 ahd_name(ahd), current_sensing); 6449 } 6450 #endif 6451 warn_user = 0; 6452 for (i = 0; i < 4; i++, current_sensing >>= FLX_CSTAT_SHIFT) { 6453 u_int term_stat; 6454 6455 term_stat = (current_sensing & FLX_CSTAT_MASK); 6456 switch (term_stat) { 6457 case FLX_CSTAT_OVER: 6458 case FLX_CSTAT_UNDER: 6459 warn_user++; 6460 case FLX_CSTAT_INVALID: 6461 case FLX_CSTAT_OKAY: 6462 if (warn_user == 0 && bootverbose == 0) 6463 break; 6464 printf("%s: %s Channel %s\n", ahd_name(ahd), 6465 channel_strings[i], termstat_strings[term_stat]); 6466 break; 6467 } 6468 } 6469 if (warn_user) { 6470 printf("%s: WARNING. Termination is not configured correctly.\n" 6471 "%s: WARNING. SCSI bus operations may FAIL.\n", 6472 ahd_name(ahd), ahd_name(ahd)); 6473 AHD_CORRECTABLE_ERROR(ahd); 6474 } 6475 init_done: 6476 ahd_restart(ahd); 6477 aic_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_MS, 6478 ahd_stat_timer, ahd); 6479 return (0); 6480 } 6481 6482 /* 6483 * (Re)initialize chip state after a chip reset. 6484 */ 6485 static void 6486 ahd_chip_init(struct ahd_softc *ahd) 6487 { 6488 uint32_t busaddr; 6489 u_int sxfrctl1; 6490 u_int scsiseq_template; 6491 u_int wait; 6492 u_int i; 6493 u_int target; 6494 6495 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6496 /* 6497 * Take the LED out of diagnostic mode 6498 */ 6499 ahd_outb(ahd, SBLKCTL, ahd_inb(ahd, SBLKCTL) & ~(DIAGLEDEN|DIAGLEDON)); 6500 6501 /* 6502 * Return HS_MAILBOX to its default value. 6503 */ 6504 ahd->hs_mailbox = 0; 6505 ahd_outb(ahd, HS_MAILBOX, 0); 6506 6507 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */ 6508 ahd_outb(ahd, IOWNID, ahd->our_id); 6509 ahd_outb(ahd, TOWNID, ahd->our_id); 6510 sxfrctl1 = (ahd->flags & AHD_TERM_ENB_A) != 0 ? STPWEN : 0; 6511 sxfrctl1 |= (ahd->flags & AHD_SPCHK_ENB_A) != 0 ? ENSPCHK : 0; 6512 if ((ahd->bugs & AHD_LONG_SETIMO_BUG) 6513 && (ahd->seltime != STIMESEL_MIN)) { 6514 /* 6515 * The selection timer duration is twice as long 6516 * as it should be. Halve it by adding "1" to 6517 * the user specified setting. 6518 */ 6519 sxfrctl1 |= ahd->seltime + STIMESEL_BUG_ADJ; 6520 } else { 6521 sxfrctl1 |= ahd->seltime; 6522 } 6523 6524 ahd_outb(ahd, SXFRCTL0, DFON); 6525 ahd_outb(ahd, SXFRCTL1, sxfrctl1|ahd->seltime|ENSTIMER|ACTNEGEN); 6526 ahd_outb(ahd, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 6527 6528 /* 6529 * Now that termination is set, wait for up 6530 * to 500ms for our transceivers to settle. If 6531 * the adapter does not have a cable attached, 6532 * the transceivers may never settle, so don't 6533 * complain if we fail here. 6534 */ 6535 for (wait = 10000; 6536 (ahd_inb(ahd, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 6537 wait--) 6538 aic_delay(100); 6539 6540 /* Clear any false bus resets due to the transceivers settling */ 6541 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); 6542 ahd_outb(ahd, CLRINT, CLRSCSIINT); 6543 6544 /* Initialize mode specific S/G state. */ 6545 for (i = 0; i < 2; i++) { 6546 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); 6547 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR); 6548 ahd_outb(ahd, SG_STATE, 0); 6549 ahd_outb(ahd, CLRSEQINTSRC, 0xFF); 6550 ahd_outb(ahd, SEQIMODE, 6551 ENSAVEPTRS|ENCFG4DATA|ENCFG4ISTAT 6552 |ENCFG4TSTAT|ENCFG4ICMD|ENCFG4TCMD); 6553 } 6554 6555 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 6556 ahd_outb(ahd, DSCOMMAND0, ahd_inb(ahd, DSCOMMAND0)|MPARCKEN|CACHETHEN); 6557 ahd_outb(ahd, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 6558 ahd_outb(ahd, SIMODE0, ENIOERR|ENOVERRUN); 6559 ahd_outb(ahd, SIMODE3, ENNTRAMPERR|ENOSRAMPERR); 6560 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) { 6561 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|AUTO_MSGOUT_DE); 6562 } else { 6563 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|BUSFREEREV|AUTO_MSGOUT_DE); 6564 } 6565 ahd_outb(ahd, SCSCHKN, CURRFIFODEF|WIDERESEN|SHVALIDSTDIS); 6566 if ((ahd->chip & AHD_BUS_MASK) == AHD_PCIX) 6567 /* 6568 * Do not issue a target abort when a split completion 6569 * error occurs. Let our PCIX interrupt handler deal 6570 * with it instead. H2A4 Razor #625 6571 */ 6572 ahd_outb(ahd, PCIXCTL, ahd_inb(ahd, PCIXCTL) | SPLTSTADIS); 6573 6574 if ((ahd->bugs & AHD_LQOOVERRUN_BUG) != 0) 6575 ahd_outb(ahd, LQOSCSCTL, LQONOCHKOVER); 6576 6577 /* 6578 * Tweak IOCELL settings. 6579 */ 6580 if ((ahd->flags & AHD_HP_BOARD) != 0) { 6581 for (i = 0; i < NUMDSPS; i++) { 6582 ahd_outb(ahd, DSPSELECT, i); 6583 ahd_outb(ahd, WRTBIASCTL, WRTBIASCTL_HP_DEFAULT); 6584 } 6585 #ifdef AHD_DEBUG 6586 if ((ahd_debug & AHD_SHOW_MISC) != 0) 6587 printf("%s: WRTBIASCTL now 0x%x\n", ahd_name(ahd), 6588 WRTBIASCTL_HP_DEFAULT); 6589 #endif 6590 } 6591 ahd_setup_iocell_workaround(ahd); 6592 6593 /* 6594 * Enable LQI Manager interrupts. 6595 */ 6596 ahd_outb(ahd, LQIMODE1, ENLQIPHASE_LQ|ENLQIPHASE_NLQ|ENLIQABORT 6597 | ENLQICRCI_LQ|ENLQICRCI_NLQ|ENLQIBADLQI 6598 | ENLQIOVERI_LQ|ENLQIOVERI_NLQ); 6599 ahd_outb(ahd, LQOMODE0, ENLQOATNLQ|ENLQOATNPKT|ENLQOTCRC); 6600 /* 6601 * We choose to have the sequencer catch LQOPHCHGINPKT errors 6602 * manually for the command phase at the start of a packetized 6603 * selection case. ENLQOBUSFREE should be made redundant by 6604 * the BUSFREE interrupt, but it seems that some LQOBUSFREE 6605 * events fail to assert the BUSFREE interrupt so we must 6606 * also enable LQOBUSFREE interrupts. 6607 */ 6608 ahd_outb(ahd, LQOMODE1, ENLQOBUSFREE); 6609 6610 /* 6611 * Setup sequencer interrupt handlers. 6612 */ 6613 ahd_outw(ahd, INTVEC1_ADDR, ahd_resolve_seqaddr(ahd, LABEL_seq_isr)); 6614 ahd_outw(ahd, INTVEC2_ADDR, ahd_resolve_seqaddr(ahd, LABEL_timer_isr)); 6615 6616 /* 6617 * Setup SCB Offset registers. 6618 */ 6619 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { 6620 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, 6621 pkt_long_lun)); 6622 } else { 6623 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, lun)); 6624 } 6625 ahd_outb(ahd, CMDLENPTR, offsetof(struct hardware_scb, cdb_len)); 6626 ahd_outb(ahd, ATTRPTR, offsetof(struct hardware_scb, task_attribute)); 6627 ahd_outb(ahd, FLAGPTR, offsetof(struct hardware_scb, task_management)); 6628 ahd_outb(ahd, CMDPTR, offsetof(struct hardware_scb, 6629 shared_data.idata.cdb)); 6630 ahd_outb(ahd, QNEXTPTR, 6631 offsetof(struct hardware_scb, next_hscb_busaddr)); 6632 ahd_outb(ahd, ABRTBITPTR, MK_MESSAGE_BIT_OFFSET); 6633 ahd_outb(ahd, ABRTBYTEPTR, offsetof(struct hardware_scb, control)); 6634 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) { 6635 ahd_outb(ahd, LUNLEN, 6636 sizeof(ahd->next_queued_hscb->pkt_long_lun) - 1); 6637 } else { 6638 ahd_outb(ahd, LUNLEN, LUNLEN_SINGLE_LEVEL_LUN); 6639 } 6640 ahd_outb(ahd, CDBLIMIT, SCB_CDB_LEN_PTR - 1); 6641 ahd_outb(ahd, MAXCMD, 0xFF); 6642 ahd_outb(ahd, SCBAUTOPTR, 6643 AUSCBPTR_EN | offsetof(struct hardware_scb, tag)); 6644 6645 /* We haven't been enabled for target mode yet. */ 6646 ahd_outb(ahd, MULTARGID, 0); 6647 ahd_outb(ahd, MULTARGID + 1, 0); 6648 6649 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6650 /* Initialize the negotiation table. */ 6651 if ((ahd->features & AHD_NEW_IOCELL_OPTS) == 0) { 6652 /* 6653 * Clear the spare bytes in the neg table to avoid 6654 * spurious parity errors. 6655 */ 6656 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6657 ahd_outb(ahd, NEGOADDR, target); 6658 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PER_DEV0); 6659 for (i = 0; i < AHD_NUM_PER_DEV_ANNEXCOLS; i++) 6660 ahd_outb(ahd, ANNEXDAT, 0); 6661 } 6662 } 6663 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6664 struct ahd_devinfo devinfo; 6665 struct ahd_initiator_tinfo *tinfo; 6666 struct ahd_tmode_tstate *tstate; 6667 6668 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6669 target, &tstate); 6670 ahd_compile_devinfo(&devinfo, ahd->our_id, 6671 target, CAM_LUN_WILDCARD, 6672 'A', ROLE_INITIATOR); 6673 ahd_update_neg_table(ahd, &devinfo, &tinfo->curr); 6674 } 6675 6676 ahd_outb(ahd, CLRSINT3, NTRAMPERR|OSRAMPERR); 6677 ahd_outb(ahd, CLRINT, CLRSCSIINT); 6678 6679 #ifdef NEEDS_MORE_TESTING 6680 /* 6681 * Always enable abort on incoming L_Qs if this feature is 6682 * supported. We use this to catch invalid SCB references. 6683 */ 6684 if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0) 6685 ahd_outb(ahd, LQCTL1, ABORTPENDING); 6686 else 6687 #endif 6688 ahd_outb(ahd, LQCTL1, 0); 6689 6690 /* All of our queues are empty */ 6691 ahd->qoutfifonext = 0; 6692 ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID; 6693 ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID); 6694 for (i = 0; i < AHD_QOUT_SIZE; i++) 6695 ahd->qoutfifo[i].valid_tag = 0; 6696 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD); 6697 6698 ahd->qinfifonext = 0; 6699 for (i = 0; i < AHD_QIN_SIZE; i++) 6700 ahd->qinfifo[i] = SCB_LIST_NULL; 6701 6702 if ((ahd->features & AHD_TARGETMODE) != 0) { 6703 /* All target command blocks start out invalid. */ 6704 for (i = 0; i < AHD_TMODE_CMDS; i++) 6705 ahd->targetcmds[i].cmd_valid = 0; 6706 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_PREREAD); 6707 ahd->tqinfifonext = 1; 6708 ahd_outb(ahd, KERNEL_TQINPOS, ahd->tqinfifonext - 1); 6709 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext); 6710 } 6711 6712 /* Initialize Scratch Ram. */ 6713 ahd_outb(ahd, SEQ_FLAGS, 0); 6714 ahd_outb(ahd, SEQ_FLAGS2, 0); 6715 6716 /* We don't have any waiting selections */ 6717 ahd_outw(ahd, WAITING_TID_HEAD, SCB_LIST_NULL); 6718 ahd_outw(ahd, WAITING_TID_TAIL, SCB_LIST_NULL); 6719 ahd_outw(ahd, MK_MESSAGE_SCB, SCB_LIST_NULL); 6720 ahd_outw(ahd, MK_MESSAGE_SCSIID, 0xFF); 6721 for (i = 0; i < AHD_NUM_TARGETS; i++) 6722 ahd_outw(ahd, WAITING_SCB_TAILS + (2 * i), SCB_LIST_NULL); 6723 6724 /* 6725 * Nobody is waiting to be DMAed into the QOUTFIFO. 6726 */ 6727 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL); 6728 ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL); 6729 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL); 6730 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL); 6731 ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL); 6732 6733 /* 6734 * The Freeze Count is 0. 6735 */ 6736 ahd->qfreeze_cnt = 0; 6737 ahd_outw(ahd, QFREEZE_COUNT, 0); 6738 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, 0); 6739 6740 /* 6741 * Tell the sequencer where it can find our arrays in memory. 6742 */ 6743 busaddr = ahd->shared_data_map.busaddr; 6744 ahd_outl(ahd, SHARED_DATA_ADDR, busaddr); 6745 ahd_outl(ahd, QOUTFIFO_NEXT_ADDR, busaddr); 6746 6747 /* 6748 * Setup the allowed SCSI Sequences based on operational mode. 6749 * If we are a target, we'll enable select in operations once 6750 * we've had a lun enabled. 6751 */ 6752 scsiseq_template = ENAUTOATNP; 6753 if ((ahd->flags & AHD_INITIATORROLE) != 0) 6754 scsiseq_template |= ENRSELI; 6755 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq_template); 6756 6757 /* There are no busy SCBs yet. */ 6758 for (target = 0; target < AHD_NUM_TARGETS; target++) { 6759 int lun; 6760 6761 for (lun = 0; lun < AHD_NUM_LUNS_NONPKT; lun++) 6762 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(target, 'A', lun)); 6763 } 6764 6765 /* 6766 * Initialize the group code to command length table. 6767 * Vendor Unique codes are set to 0 so we only capture 6768 * the first byte of the cdb. These can be overridden 6769 * when target mode is enabled. 6770 */ 6771 ahd_outb(ahd, CMDSIZE_TABLE, 5); 6772 ahd_outb(ahd, CMDSIZE_TABLE + 1, 9); 6773 ahd_outb(ahd, CMDSIZE_TABLE + 2, 9); 6774 ahd_outb(ahd, CMDSIZE_TABLE + 3, 0); 6775 ahd_outb(ahd, CMDSIZE_TABLE + 4, 15); 6776 ahd_outb(ahd, CMDSIZE_TABLE + 5, 11); 6777 ahd_outb(ahd, CMDSIZE_TABLE + 6, 0); 6778 ahd_outb(ahd, CMDSIZE_TABLE + 7, 0); 6779 6780 /* Tell the sequencer of our initial queue positions */ 6781 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 6782 ahd_outb(ahd, QOFF_CTLSTA, SCB_QSIZE_512); 6783 ahd->qinfifonext = 0; 6784 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 6785 ahd_set_hescb_qoff(ahd, 0); 6786 ahd_set_snscb_qoff(ahd, 0); 6787 ahd_set_sescb_qoff(ahd, 0); 6788 ahd_set_sdscb_qoff(ahd, 0); 6789 6790 /* 6791 * Tell the sequencer which SCB will be the next one it receives. 6792 */ 6793 busaddr = aic_le32toh(ahd->next_queued_hscb->hscb_busaddr); 6794 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr); 6795 6796 /* 6797 * Default to coalescing disabled. 6798 */ 6799 ahd_outw(ahd, INT_COALESCING_CMDCOUNT, 0); 6800 ahd_outw(ahd, CMDS_PENDING, 0); 6801 ahd_update_coalescing_values(ahd, ahd->int_coalescing_timer, 6802 ahd->int_coalescing_maxcmds, 6803 ahd->int_coalescing_mincmds); 6804 ahd_enable_coalescing(ahd, FALSE); 6805 6806 ahd_loadseq(ahd); 6807 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 6808 } 6809 6810 /* 6811 * Setup default device and controller settings. 6812 * This should only be called if our probe has 6813 * determined that no configuration data is available. 6814 */ 6815 int 6816 ahd_default_config(struct ahd_softc *ahd) 6817 { 6818 int targ; 6819 6820 ahd->our_id = 7; 6821 6822 /* 6823 * Allocate a tstate to house information for our 6824 * initiator presence on the bus as well as the user 6825 * data for any target mode initiator. 6826 */ 6827 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { 6828 printf("%s: unable to allocate ahd_tmode_tstate. " 6829 "Failing attach\n", ahd_name(ahd)); 6830 AHD_FATAL_ERROR(ahd); 6831 return (ENOMEM); 6832 } 6833 6834 for (targ = 0; targ < AHD_NUM_TARGETS; targ++) { 6835 struct ahd_devinfo devinfo; 6836 struct ahd_initiator_tinfo *tinfo; 6837 struct ahd_tmode_tstate *tstate; 6838 uint16_t target_mask; 6839 6840 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6841 targ, &tstate); 6842 /* 6843 * We support SPC2 and SPI4. 6844 */ 6845 tinfo->user.protocol_version = 4; 6846 tinfo->user.transport_version = 4; 6847 6848 target_mask = 0x01 << targ; 6849 ahd->user_discenable |= target_mask; 6850 tstate->discenable |= target_mask; 6851 ahd->user_tagenable |= target_mask; 6852 #ifdef AHD_FORCE_160 6853 tinfo->user.period = AHD_SYNCRATE_DT; 6854 #else 6855 tinfo->user.period = AHD_SYNCRATE_160; 6856 #endif 6857 tinfo->user.offset = MAX_OFFSET; 6858 tinfo->user.ppr_options = MSG_EXT_PPR_RD_STRM 6859 | MSG_EXT_PPR_WR_FLOW 6860 | MSG_EXT_PPR_HOLD_MCS 6861 | MSG_EXT_PPR_IU_REQ 6862 | MSG_EXT_PPR_QAS_REQ 6863 | MSG_EXT_PPR_DT_REQ; 6864 if ((ahd->features & AHD_RTI) != 0) 6865 tinfo->user.ppr_options |= MSG_EXT_PPR_RTI; 6866 6867 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 6868 6869 /* 6870 * Start out Async/Narrow/Untagged and with 6871 * conservative protocol support. 6872 */ 6873 tinfo->goal.protocol_version = 2; 6874 tinfo->goal.transport_version = 2; 6875 tinfo->curr.protocol_version = 2; 6876 tinfo->curr.transport_version = 2; 6877 ahd_compile_devinfo(&devinfo, ahd->our_id, 6878 targ, CAM_LUN_WILDCARD, 6879 'A', ROLE_INITIATOR); 6880 tstate->tagenable &= ~target_mask; 6881 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6882 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); 6883 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, 6884 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, 6885 /*paused*/TRUE); 6886 } 6887 return (0); 6888 } 6889 6890 /* 6891 * Parse device configuration information. 6892 */ 6893 int 6894 ahd_parse_cfgdata(struct ahd_softc *ahd, struct seeprom_config *sc) 6895 { 6896 int targ; 6897 int max_targ; 6898 6899 max_targ = sc->max_targets & CFMAXTARG; 6900 ahd->our_id = sc->brtime_id & CFSCSIID; 6901 6902 /* 6903 * Allocate a tstate to house information for our 6904 * initiator presence on the bus as well as the user 6905 * data for any target mode initiator. 6906 */ 6907 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) { 6908 printf("%s: unable to allocate ahd_tmode_tstate. " 6909 "Failing attach\n", ahd_name(ahd)); 6910 AHD_FATAL_ERROR(ahd); 6911 return (ENOMEM); 6912 } 6913 6914 for (targ = 0; targ < max_targ; targ++) { 6915 struct ahd_devinfo devinfo; 6916 struct ahd_initiator_tinfo *tinfo; 6917 struct ahd_transinfo *user_tinfo; 6918 struct ahd_tmode_tstate *tstate; 6919 uint16_t target_mask; 6920 6921 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id, 6922 targ, &tstate); 6923 user_tinfo = &tinfo->user; 6924 6925 /* 6926 * We support SPC2 and SPI4. 6927 */ 6928 tinfo->user.protocol_version = 4; 6929 tinfo->user.transport_version = 4; 6930 6931 target_mask = 0x01 << targ; 6932 ahd->user_discenable &= ~target_mask; 6933 tstate->discenable &= ~target_mask; 6934 ahd->user_tagenable &= ~target_mask; 6935 if (sc->device_flags[targ] & CFDISC) { 6936 tstate->discenable |= target_mask; 6937 ahd->user_discenable |= target_mask; 6938 ahd->user_tagenable |= target_mask; 6939 } else { 6940 /* 6941 * Cannot be packetized without disconnection. 6942 */ 6943 sc->device_flags[targ] &= ~CFPACKETIZED; 6944 } 6945 6946 user_tinfo->ppr_options = 0; 6947 user_tinfo->period = (sc->device_flags[targ] & CFXFER); 6948 if (user_tinfo->period < CFXFER_ASYNC) { 6949 if (user_tinfo->period <= AHD_PERIOD_10MHz) 6950 user_tinfo->ppr_options |= MSG_EXT_PPR_DT_REQ; 6951 user_tinfo->offset = MAX_OFFSET; 6952 } else { 6953 user_tinfo->offset = 0; 6954 user_tinfo->period = AHD_ASYNC_XFER_PERIOD; 6955 } 6956 #ifdef AHD_FORCE_160 6957 if (user_tinfo->period <= AHD_SYNCRATE_160) 6958 user_tinfo->period = AHD_SYNCRATE_DT; 6959 #endif 6960 6961 if ((sc->device_flags[targ] & CFPACKETIZED) != 0) { 6962 user_tinfo->ppr_options |= MSG_EXT_PPR_RD_STRM 6963 | MSG_EXT_PPR_WR_FLOW 6964 | MSG_EXT_PPR_HOLD_MCS 6965 | MSG_EXT_PPR_IU_REQ; 6966 if ((ahd->features & AHD_RTI) != 0) 6967 user_tinfo->ppr_options |= MSG_EXT_PPR_RTI; 6968 } 6969 6970 if ((sc->device_flags[targ] & CFQAS) != 0) 6971 user_tinfo->ppr_options |= MSG_EXT_PPR_QAS_REQ; 6972 6973 if ((sc->device_flags[targ] & CFWIDEB) != 0) 6974 user_tinfo->width = MSG_EXT_WDTR_BUS_16_BIT; 6975 else 6976 user_tinfo->width = MSG_EXT_WDTR_BUS_8_BIT; 6977 #ifdef AHD_DEBUG 6978 if ((ahd_debug & AHD_SHOW_MISC) != 0) 6979 printf("(%d): %x:%x:%x:%x\n", targ, user_tinfo->width, 6980 user_tinfo->period, user_tinfo->offset, 6981 user_tinfo->ppr_options); 6982 #endif 6983 /* 6984 * Start out Async/Narrow/Untagged and with 6985 * conservative protocol support. 6986 */ 6987 tstate->tagenable &= ~target_mask; 6988 tinfo->goal.protocol_version = 2; 6989 tinfo->goal.transport_version = 2; 6990 tinfo->curr.protocol_version = 2; 6991 tinfo->curr.transport_version = 2; 6992 ahd_compile_devinfo(&devinfo, ahd->our_id, 6993 targ, CAM_LUN_WILDCARD, 6994 'A', ROLE_INITIATOR); 6995 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6996 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE); 6997 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0, 6998 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL, 6999 /*paused*/TRUE); 7000 } 7001 7002 ahd->flags &= ~AHD_SPCHK_ENB_A; 7003 if (sc->bios_control & CFSPARITY) 7004 ahd->flags |= AHD_SPCHK_ENB_A; 7005 7006 ahd->flags &= ~AHD_RESET_BUS_A; 7007 if (sc->bios_control & CFRESETB) 7008 ahd->flags |= AHD_RESET_BUS_A; 7009 7010 ahd->flags &= ~AHD_EXTENDED_TRANS_A; 7011 if (sc->bios_control & CFEXTEND) 7012 ahd->flags |= AHD_EXTENDED_TRANS_A; 7013 7014 ahd->flags &= ~AHD_BIOS_ENABLED; 7015 if ((sc->bios_control & CFBIOSSTATE) == CFBS_ENABLED) 7016 ahd->flags |= AHD_BIOS_ENABLED; 7017 7018 ahd->flags &= ~AHD_STPWLEVEL_A; 7019 if ((sc->adapter_control & CFSTPWLEVEL) != 0) 7020 ahd->flags |= AHD_STPWLEVEL_A; 7021 7022 return (0); 7023 } 7024 7025 /* 7026 * Parse device configuration information. 7027 */ 7028 int 7029 ahd_parse_vpddata(struct ahd_softc *ahd, struct vpd_config *vpd) 7030 { 7031 int error; 7032 7033 error = ahd_verify_vpd_cksum(vpd); 7034 if (error == 0) 7035 return (EINVAL); 7036 if ((vpd->bios_flags & VPDBOOTHOST) != 0) 7037 ahd->flags |= AHD_BOOT_CHANNEL; 7038 return (0); 7039 } 7040 7041 void 7042 ahd_intr_enable(struct ahd_softc *ahd, int enable) 7043 { 7044 u_int hcntrl; 7045 7046 hcntrl = ahd_inb(ahd, HCNTRL); 7047 hcntrl &= ~INTEN; 7048 ahd->pause &= ~INTEN; 7049 ahd->unpause &= ~INTEN; 7050 if (enable) { 7051 hcntrl |= INTEN; 7052 ahd->pause |= INTEN; 7053 ahd->unpause |= INTEN; 7054 } 7055 ahd_outb(ahd, HCNTRL, hcntrl); 7056 } 7057 7058 void 7059 ahd_update_coalescing_values(struct ahd_softc *ahd, u_int timer, u_int maxcmds, 7060 u_int mincmds) 7061 { 7062 if (timer > AHD_TIMER_MAX_US) 7063 timer = AHD_TIMER_MAX_US; 7064 ahd->int_coalescing_timer = timer; 7065 7066 if (maxcmds > AHD_INT_COALESCING_MAXCMDS_MAX) 7067 maxcmds = AHD_INT_COALESCING_MAXCMDS_MAX; 7068 if (mincmds > AHD_INT_COALESCING_MINCMDS_MAX) 7069 mincmds = AHD_INT_COALESCING_MINCMDS_MAX; 7070 ahd->int_coalescing_maxcmds = maxcmds; 7071 ahd_outw(ahd, INT_COALESCING_TIMER, timer / AHD_TIMER_US_PER_TICK); 7072 ahd_outb(ahd, INT_COALESCING_MAXCMDS, -maxcmds); 7073 ahd_outb(ahd, INT_COALESCING_MINCMDS, -mincmds); 7074 } 7075 7076 void 7077 ahd_enable_coalescing(struct ahd_softc *ahd, int enable) 7078 { 7079 7080 ahd->hs_mailbox &= ~ENINT_COALESCE; 7081 if (enable) 7082 ahd->hs_mailbox |= ENINT_COALESCE; 7083 ahd_outb(ahd, HS_MAILBOX, ahd->hs_mailbox); 7084 ahd_flush_device_writes(ahd); 7085 ahd_run_qoutfifo(ahd); 7086 } 7087 7088 /* 7089 * Ensure that the card is paused in a location 7090 * outside of all critical sections and that all 7091 * pending work is completed prior to returning. 7092 * This routine should only be called from outside 7093 * an interrupt context. 7094 */ 7095 void 7096 ahd_pause_and_flushwork(struct ahd_softc *ahd) 7097 { 7098 u_int intstat; 7099 u_int maxloops; 7100 7101 maxloops = 1000; 7102 ahd->flags |= AHD_ALL_INTERRUPTS; 7103 ahd_pause(ahd); 7104 /* 7105 * Freeze the outgoing selections. We do this only 7106 * until we are safely paused without further selections 7107 * pending. 7108 */ 7109 ahd->qfreeze_cnt--; 7110 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt); 7111 ahd_outb(ahd, SEQ_FLAGS2, ahd_inb(ahd, SEQ_FLAGS2) | SELECTOUT_QFROZEN); 7112 do { 7113 ahd_unpause(ahd); 7114 /* 7115 * Give the sequencer some time to service 7116 * any active selections. 7117 */ 7118 aic_delay(500); 7119 7120 ahd_intr(ahd); 7121 ahd_pause(ahd); 7122 intstat = ahd_inb(ahd, INTSTAT); 7123 if ((intstat & INT_PEND) == 0) { 7124 ahd_clear_critical_section(ahd); 7125 intstat = ahd_inb(ahd, INTSTAT); 7126 } 7127 } while (--maxloops 7128 && (intstat != 0xFF || (ahd->features & AHD_REMOVABLE) == 0) 7129 && ((intstat & INT_PEND) != 0 7130 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0 7131 || (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0)); 7132 7133 if (maxloops == 0) { 7134 printf("Infinite interrupt loop, INTSTAT = %x", 7135 ahd_inb(ahd, INTSTAT)); 7136 AHD_FATAL_ERROR(ahd); 7137 } 7138 ahd->qfreeze_cnt++; 7139 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt); 7140 7141 ahd_flush_qoutfifo(ahd); 7142 7143 ahd_platform_flushwork(ahd); 7144 ahd->flags &= ~AHD_ALL_INTERRUPTS; 7145 } 7146 7147 int 7148 ahd_suspend(struct ahd_softc *ahd) 7149 { 7150 7151 ahd_pause_and_flushwork(ahd); 7152 7153 if (LIST_FIRST(&ahd->pending_scbs) != NULL) { 7154 ahd_unpause(ahd); 7155 return (EBUSY); 7156 } 7157 ahd_shutdown(ahd); 7158 return (0); 7159 } 7160 7161 int 7162 ahd_resume(struct ahd_softc *ahd) 7163 { 7164 7165 ahd_reset(ahd, /*reinit*/TRUE); 7166 ahd_intr_enable(ahd, TRUE); 7167 ahd_restart(ahd); 7168 return (0); 7169 } 7170 7171 /************************** Busy Target Table *********************************/ 7172 /* 7173 * Set SCBPTR to the SCB that contains the busy 7174 * table entry for TCL. Return the offset into 7175 * the SCB that contains the entry for TCL. 7176 * saved_scbid is dereferenced and set to the 7177 * scbid that should be restored once manipualtion 7178 * of the TCL entry is complete. 7179 */ 7180 static __inline u_int 7181 ahd_index_busy_tcl(struct ahd_softc *ahd, u_int *saved_scbid, u_int tcl) 7182 { 7183 /* 7184 * Index to the SCB that contains the busy entry. 7185 */ 7186 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7187 *saved_scbid = ahd_get_scbptr(ahd); 7188 ahd_set_scbptr(ahd, TCL_LUN(tcl) 7189 | ((TCL_TARGET_OFFSET(tcl) & 0xC) << 4)); 7190 7191 /* 7192 * And now calculate the SCB offset to the entry. 7193 * Each entry is 2 bytes wide, hence the 7194 * multiplication by 2. 7195 */ 7196 return (((TCL_TARGET_OFFSET(tcl) & 0x3) << 1) + SCB_DISCONNECTED_LISTS); 7197 } 7198 7199 /* 7200 * Return the untagged transaction id for a given target/channel lun. 7201 */ 7202 u_int 7203 ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl) 7204 { 7205 u_int scbid; 7206 u_int scb_offset; 7207 u_int saved_scbptr; 7208 7209 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); 7210 scbid = ahd_inw_scbram(ahd, scb_offset); 7211 ahd_set_scbptr(ahd, saved_scbptr); 7212 return (scbid); 7213 } 7214 7215 void 7216 ahd_busy_tcl(struct ahd_softc *ahd, u_int tcl, u_int scbid) 7217 { 7218 u_int scb_offset; 7219 u_int saved_scbptr; 7220 7221 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl); 7222 ahd_outw(ahd, scb_offset, scbid); 7223 ahd_set_scbptr(ahd, saved_scbptr); 7224 } 7225 7226 /************************** SCB and SCB queue management **********************/ 7227 int 7228 ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, int target, 7229 char channel, int lun, u_int tag, role_t role) 7230 { 7231 int targ = SCB_GET_TARGET(ahd, scb); 7232 char chan = SCB_GET_CHANNEL(ahd, scb); 7233 int slun = SCB_GET_LUN(scb); 7234 int match; 7235 7236 match = ((chan == channel) || (channel == ALL_CHANNELS)); 7237 if (match != 0) 7238 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 7239 if (match != 0) 7240 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 7241 if (match != 0) { 7242 #ifdef AHD_TARGET_MODE 7243 int group; 7244 7245 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 7246 if (role == ROLE_INITIATOR) { 7247 match = (group != XPT_FC_GROUP_TMODE) 7248 && ((tag == SCB_GET_TAG(scb)) 7249 || (tag == SCB_LIST_NULL)); 7250 } else if (role == ROLE_TARGET) { 7251 match = (group == XPT_FC_GROUP_TMODE) 7252 && ((tag == scb->io_ctx->csio.tag_id) 7253 || (tag == SCB_LIST_NULL)); 7254 } 7255 #else /* !AHD_TARGET_MODE */ 7256 match = ((tag == SCB_GET_TAG(scb)) || (tag == SCB_LIST_NULL)); 7257 #endif /* AHD_TARGET_MODE */ 7258 } 7259 7260 return match; 7261 } 7262 7263 void 7264 ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb) 7265 { 7266 int target; 7267 char channel; 7268 int lun; 7269 7270 target = SCB_GET_TARGET(ahd, scb); 7271 lun = SCB_GET_LUN(scb); 7272 channel = SCB_GET_CHANNEL(ahd, scb); 7273 7274 ahd_search_qinfifo(ahd, target, channel, lun, 7275 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 7276 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 7277 7278 ahd_platform_freeze_devq(ahd, scb); 7279 } 7280 7281 void 7282 ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, struct scb *scb) 7283 { 7284 struct scb *prev_scb; 7285 ahd_mode_state saved_modes; 7286 7287 saved_modes = ahd_save_modes(ahd); 7288 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 7289 prev_scb = NULL; 7290 if (ahd_qinfifo_count(ahd) != 0) { 7291 u_int prev_tag; 7292 u_int prev_pos; 7293 7294 prev_pos = AHD_QIN_WRAP(ahd->qinfifonext - 1); 7295 prev_tag = ahd->qinfifo[prev_pos]; 7296 prev_scb = ahd_lookup_scb(ahd, prev_tag); 7297 } 7298 ahd_qinfifo_requeue(ahd, prev_scb, scb); 7299 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 7300 ahd_restore_modes(ahd, saved_modes); 7301 } 7302 7303 static void 7304 ahd_qinfifo_requeue(struct ahd_softc *ahd, struct scb *prev_scb, 7305 struct scb *scb) 7306 { 7307 if (prev_scb == NULL) { 7308 uint32_t busaddr; 7309 7310 busaddr = aic_le32toh(scb->hscb->hscb_busaddr); 7311 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr); 7312 } else { 7313 prev_scb->hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr; 7314 ahd_sync_scb(ahd, prev_scb, 7315 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 7316 } 7317 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb); 7318 ahd->qinfifonext++; 7319 scb->hscb->next_hscb_busaddr = ahd->next_queued_hscb->hscb_busaddr; 7320 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 7321 } 7322 7323 static int 7324 ahd_qinfifo_count(struct ahd_softc *ahd) 7325 { 7326 u_int qinpos; 7327 u_int wrap_qinpos; 7328 u_int wrap_qinfifonext; 7329 7330 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK); 7331 qinpos = ahd_get_snscb_qoff(ahd); 7332 wrap_qinpos = AHD_QIN_WRAP(qinpos); 7333 wrap_qinfifonext = AHD_QIN_WRAP(ahd->qinfifonext); 7334 if (wrap_qinfifonext >= wrap_qinpos) 7335 return (wrap_qinfifonext - wrap_qinpos); 7336 else 7337 return (wrap_qinfifonext 7338 + NUM_ELEMENTS(ahd->qinfifo) - wrap_qinpos); 7339 } 7340 7341 void 7342 ahd_reset_cmds_pending(struct ahd_softc *ahd) 7343 { 7344 struct scb *scb; 7345 ahd_mode_state saved_modes; 7346 u_int pending_cmds; 7347 7348 saved_modes = ahd_save_modes(ahd); 7349 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 7350 7351 /* 7352 * Don't count any commands as outstanding that the 7353 * sequencer has already marked for completion. 7354 */ 7355 ahd_flush_qoutfifo(ahd); 7356 7357 pending_cmds = 0; 7358 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 7359 pending_cmds++; 7360 } 7361 ahd_outw(ahd, CMDS_PENDING, pending_cmds - ahd_qinfifo_count(ahd)); 7362 ahd_restore_modes(ahd, saved_modes); 7363 ahd->flags &= ~AHD_UPDATE_PEND_CMDS; 7364 } 7365 7366 void 7367 ahd_done_with_status(struct ahd_softc *ahd, struct scb *scb, uint32_t status) 7368 { 7369 cam_status ostat; 7370 cam_status cstat; 7371 7372 ostat = aic_get_transaction_status(scb); 7373 if (ostat == CAM_REQ_INPROG) 7374 aic_set_transaction_status(scb, status); 7375 cstat = aic_get_transaction_status(scb); 7376 if (cstat != CAM_REQ_CMP) 7377 aic_freeze_scb(scb); 7378 ahd_done(ahd, scb); 7379 } 7380 7381 int 7382 ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel, 7383 int lun, u_int tag, role_t role, uint32_t status, 7384 ahd_search_action action) 7385 { 7386 struct scb *scb; 7387 struct scb *mk_msg_scb; 7388 struct scb *prev_scb; 7389 ahd_mode_state saved_modes; 7390 u_int qinstart; 7391 u_int qinpos; 7392 u_int qintail; 7393 u_int tid_next; 7394 u_int tid_prev; 7395 u_int scbid; 7396 u_int seq_flags2; 7397 u_int savedscbptr; 7398 uint32_t busaddr; 7399 int found; 7400 int targets; 7401 7402 /* Must be in CCHAN mode */ 7403 saved_modes = ahd_save_modes(ahd); 7404 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 7405 7406 /* 7407 * Halt any pending SCB DMA. The sequencer will reinitiate 7408 * this dma if the qinfifo is not empty once we unpause. 7409 */ 7410 if ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN|CCSCBDIR)) 7411 == (CCARREN|CCSCBEN|CCSCBDIR)) { 7412 ahd_outb(ahd, CCSCBCTL, 7413 ahd_inb(ahd, CCSCBCTL) & ~(CCARREN|CCSCBEN)); 7414 while ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0) 7415 ; 7416 } 7417 /* Determine sequencer's position in the qinfifo. */ 7418 qintail = AHD_QIN_WRAP(ahd->qinfifonext); 7419 qinstart = ahd_get_snscb_qoff(ahd); 7420 qinpos = AHD_QIN_WRAP(qinstart); 7421 found = 0; 7422 prev_scb = NULL; 7423 7424 if (action == SEARCH_PRINT) { 7425 printf("qinstart = %d qinfifonext = %d\nQINFIFO:", 7426 qinstart, ahd->qinfifonext); 7427 } 7428 7429 /* 7430 * Start with an empty queue. Entries that are not chosen 7431 * for removal will be re-added to the queue as we go. 7432 */ 7433 ahd->qinfifonext = qinstart; 7434 busaddr = aic_le32toh(ahd->next_queued_hscb->hscb_busaddr); 7435 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr); 7436 7437 while (qinpos != qintail) { 7438 scb = ahd_lookup_scb(ahd, ahd->qinfifo[qinpos]); 7439 if (scb == NULL) { 7440 printf("qinpos = %d, SCB index = %d\n", 7441 qinpos, ahd->qinfifo[qinpos]); 7442 AHD_FATAL_ERROR(ahd); 7443 panic("Loop 1\n"); 7444 } 7445 7446 if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) { 7447 /* 7448 * We found an scb that needs to be acted on. 7449 */ 7450 found++; 7451 switch (action) { 7452 case SEARCH_COMPLETE: 7453 if ((scb->flags & SCB_ACTIVE) == 0) 7454 printf("Inactive SCB in qinfifo\n"); 7455 ahd_done_with_status(ahd, scb, status); 7456 /* FALLTHROUGH */ 7457 case SEARCH_REMOVE: 7458 break; 7459 case SEARCH_PRINT: 7460 printf(" 0x%x", ahd->qinfifo[qinpos]); 7461 /* FALLTHROUGH */ 7462 case SEARCH_COUNT: 7463 ahd_qinfifo_requeue(ahd, prev_scb, scb); 7464 prev_scb = scb; 7465 break; 7466 } 7467 } else { 7468 ahd_qinfifo_requeue(ahd, prev_scb, scb); 7469 prev_scb = scb; 7470 } 7471 qinpos = AHD_QIN_WRAP(qinpos+1); 7472 } 7473 7474 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext); 7475 7476 if (action == SEARCH_PRINT) 7477 printf("\nWAITING_TID_QUEUES:\n"); 7478 7479 /* 7480 * Search waiting for selection lists. We traverse the 7481 * list of "their ids" waiting for selection and, if 7482 * appropriate, traverse the SCBs of each "their id" 7483 * looking for matches. 7484 */ 7485 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7486 seq_flags2 = ahd_inb(ahd, SEQ_FLAGS2); 7487 if ((seq_flags2 & PENDING_MK_MESSAGE) != 0) { 7488 scbid = ahd_inw(ahd, MK_MESSAGE_SCB); 7489 mk_msg_scb = ahd_lookup_scb(ahd, scbid); 7490 } else 7491 mk_msg_scb = NULL; 7492 savedscbptr = ahd_get_scbptr(ahd); 7493 tid_next = ahd_inw(ahd, WAITING_TID_HEAD); 7494 tid_prev = SCB_LIST_NULL; 7495 targets = 0; 7496 for (scbid = tid_next; !SCBID_IS_NULL(scbid); scbid = tid_next) { 7497 u_int tid_head; 7498 u_int tid_tail; 7499 7500 targets++; 7501 if (targets > AHD_NUM_TARGETS) 7502 panic("TID LIST LOOP"); 7503 7504 if (scbid >= ahd->scb_data.numscbs) { 7505 printf("%s: Waiting TID List inconsistency. " 7506 "SCB index == 0x%x, yet numscbs == 0x%x.", 7507 ahd_name(ahd), scbid, ahd->scb_data.numscbs); 7508 ahd_dump_card_state(ahd); 7509 panic("for safety"); 7510 } 7511 scb = ahd_lookup_scb(ahd, scbid); 7512 if (scb == NULL) { 7513 printf("%s: SCB = 0x%x Not Active!\n", 7514 ahd_name(ahd), scbid); 7515 panic("Waiting TID List traversal\n"); 7516 } 7517 ahd_set_scbptr(ahd, scbid); 7518 tid_next = ahd_inw_scbram(ahd, SCB_NEXT2); 7519 if (ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD, 7520 SCB_LIST_NULL, ROLE_UNKNOWN) == 0) { 7521 tid_prev = scbid; 7522 continue; 7523 } 7524 7525 /* 7526 * We found a list of scbs that needs to be searched. 7527 */ 7528 if (action == SEARCH_PRINT) 7529 printf(" %d ( ", SCB_GET_TARGET(ahd, scb)); 7530 tid_head = scbid; 7531 found += ahd_search_scb_list(ahd, target, channel, 7532 lun, tag, role, status, 7533 action, &tid_head, &tid_tail, 7534 SCB_GET_TARGET(ahd, scb)); 7535 /* 7536 * Check any MK_MESSAGE SCB that is still waiting to 7537 * enter this target's waiting for selection queue. 7538 */ 7539 if (mk_msg_scb != NULL 7540 && ahd_match_scb(ahd, mk_msg_scb, target, channel, 7541 lun, tag, role)) { 7542 /* 7543 * We found an scb that needs to be acted on. 7544 */ 7545 found++; 7546 switch (action) { 7547 case SEARCH_COMPLETE: 7548 if ((mk_msg_scb->flags & SCB_ACTIVE) == 0) 7549 printf("Inactive SCB pending MK_MSG\n"); 7550 ahd_done_with_status(ahd, mk_msg_scb, status); 7551 /* FALLTHROUGH */ 7552 case SEARCH_REMOVE: 7553 { 7554 u_int tail_offset; 7555 7556 printf("Removing MK_MSG scb\n"); 7557 7558 /* 7559 * Reset our tail to the tail of the 7560 * main per-target list. 7561 */ 7562 tail_offset = WAITING_SCB_TAILS 7563 + (2 * SCB_GET_TARGET(ahd, mk_msg_scb)); 7564 ahd_outw(ahd, tail_offset, tid_tail); 7565 7566 seq_flags2 &= ~PENDING_MK_MESSAGE; 7567 ahd_outb(ahd, SEQ_FLAGS2, seq_flags2); 7568 ahd_outw(ahd, CMDS_PENDING, 7569 ahd_inw(ahd, CMDS_PENDING)-1); 7570 mk_msg_scb = NULL; 7571 break; 7572 } 7573 case SEARCH_PRINT: 7574 printf(" 0x%x", SCB_GET_TAG(scb)); 7575 /* FALLTHROUGH */ 7576 case SEARCH_COUNT: 7577 break; 7578 } 7579 } 7580 7581 if (mk_msg_scb != NULL 7582 && SCBID_IS_NULL(tid_head) 7583 && ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD, 7584 SCB_LIST_NULL, ROLE_UNKNOWN)) { 7585 /* 7586 * When removing the last SCB for a target 7587 * queue with a pending MK_MESSAGE scb, we 7588 * must queue the MK_MESSAGE scb. 7589 */ 7590 printf("Queueing mk_msg_scb\n"); 7591 tid_head = ahd_inw(ahd, MK_MESSAGE_SCB); 7592 seq_flags2 &= ~PENDING_MK_MESSAGE; 7593 ahd_outb(ahd, SEQ_FLAGS2, seq_flags2); 7594 mk_msg_scb = NULL; 7595 } 7596 if (tid_head != scbid) 7597 ahd_stitch_tid_list(ahd, tid_prev, tid_head, tid_next); 7598 if (!SCBID_IS_NULL(tid_head)) 7599 tid_prev = tid_head; 7600 if (action == SEARCH_PRINT) 7601 printf(")\n"); 7602 } 7603 7604 /* Restore saved state. */ 7605 ahd_set_scbptr(ahd, savedscbptr); 7606 ahd_restore_modes(ahd, saved_modes); 7607 return (found); 7608 } 7609 7610 static int 7611 ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel, 7612 int lun, u_int tag, role_t role, uint32_t status, 7613 ahd_search_action action, u_int *list_head, 7614 u_int *list_tail, u_int tid) 7615 { 7616 struct scb *scb; 7617 u_int scbid; 7618 u_int next; 7619 u_int prev; 7620 int found; 7621 7622 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7623 found = 0; 7624 prev = SCB_LIST_NULL; 7625 next = *list_head; 7626 *list_tail = SCB_LIST_NULL; 7627 for (scbid = next; !SCBID_IS_NULL(scbid); scbid = next) { 7628 if (scbid >= ahd->scb_data.numscbs) { 7629 printf("%s:SCB List inconsistency. " 7630 "SCB == 0x%x, yet numscbs == 0x%x.", 7631 ahd_name(ahd), scbid, ahd->scb_data.numscbs); 7632 ahd_dump_card_state(ahd); 7633 panic("for safety"); 7634 } 7635 scb = ahd_lookup_scb(ahd, scbid); 7636 if (scb == NULL) { 7637 printf("%s: SCB = %d Not Active!\n", 7638 ahd_name(ahd), scbid); 7639 panic("Waiting List traversal\n"); 7640 } 7641 ahd_set_scbptr(ahd, scbid); 7642 *list_tail = scbid; 7643 next = ahd_inw_scbram(ahd, SCB_NEXT); 7644 if (ahd_match_scb(ahd, scb, target, channel, 7645 lun, SCB_LIST_NULL, role) == 0) { 7646 prev = scbid; 7647 continue; 7648 } 7649 found++; 7650 switch (action) { 7651 case SEARCH_COMPLETE: 7652 if ((scb->flags & SCB_ACTIVE) == 0) 7653 printf("Inactive SCB in Waiting List\n"); 7654 ahd_done_with_status(ahd, scb, status); 7655 /* FALLTHROUGH */ 7656 case SEARCH_REMOVE: 7657 ahd_rem_wscb(ahd, scbid, prev, next, tid); 7658 *list_tail = prev; 7659 if (SCBID_IS_NULL(prev)) 7660 *list_head = next; 7661 break; 7662 case SEARCH_PRINT: 7663 printf("0x%x ", scbid); 7664 case SEARCH_COUNT: 7665 prev = scbid; 7666 break; 7667 } 7668 if (found > AHD_SCB_MAX) 7669 panic("SCB LIST LOOP"); 7670 } 7671 if (action == SEARCH_COMPLETE 7672 || action == SEARCH_REMOVE) 7673 ahd_outw(ahd, CMDS_PENDING, ahd_inw(ahd, CMDS_PENDING) - found); 7674 return (found); 7675 } 7676 7677 static void 7678 ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev, 7679 u_int tid_cur, u_int tid_next) 7680 { 7681 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7682 7683 if (SCBID_IS_NULL(tid_cur)) { 7684 /* Bypass current TID list */ 7685 if (SCBID_IS_NULL(tid_prev)) { 7686 ahd_outw(ahd, WAITING_TID_HEAD, tid_next); 7687 } else { 7688 ahd_set_scbptr(ahd, tid_prev); 7689 ahd_outw(ahd, SCB_NEXT2, tid_next); 7690 } 7691 if (SCBID_IS_NULL(tid_next)) 7692 ahd_outw(ahd, WAITING_TID_TAIL, tid_prev); 7693 } else { 7694 /* Stitch through tid_cur */ 7695 if (SCBID_IS_NULL(tid_prev)) { 7696 ahd_outw(ahd, WAITING_TID_HEAD, tid_cur); 7697 } else { 7698 ahd_set_scbptr(ahd, tid_prev); 7699 ahd_outw(ahd, SCB_NEXT2, tid_cur); 7700 } 7701 ahd_set_scbptr(ahd, tid_cur); 7702 ahd_outw(ahd, SCB_NEXT2, tid_next); 7703 7704 if (SCBID_IS_NULL(tid_next)) 7705 ahd_outw(ahd, WAITING_TID_TAIL, tid_cur); 7706 } 7707 } 7708 7709 /* 7710 * Manipulate the waiting for selection list and return the 7711 * scb that follows the one that we remove. 7712 */ 7713 static u_int 7714 ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid, 7715 u_int prev, u_int next, u_int tid) 7716 { 7717 u_int tail_offset; 7718 7719 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7720 if (!SCBID_IS_NULL(prev)) { 7721 ahd_set_scbptr(ahd, prev); 7722 ahd_outw(ahd, SCB_NEXT, next); 7723 } 7724 7725 /* 7726 * SCBs that have MK_MESSAGE set in them may 7727 * cause the tail pointer to be updated without 7728 * setting the next pointer of the previous tail. 7729 * Only clear the tail if the removed SCB was 7730 * the tail. 7731 */ 7732 tail_offset = WAITING_SCB_TAILS + (2 * tid); 7733 if (SCBID_IS_NULL(next) 7734 && ahd_inw(ahd, tail_offset) == scbid) 7735 ahd_outw(ahd, tail_offset, prev); 7736 7737 ahd_add_scb_to_free_list(ahd, scbid); 7738 return (next); 7739 } 7740 7741 /* 7742 * Add the SCB as selected by SCBPTR onto the on chip list of 7743 * free hardware SCBs. This list is empty/unused if we are not 7744 * performing SCB paging. 7745 */ 7746 static void 7747 ahd_add_scb_to_free_list(struct ahd_softc *ahd, u_int scbid) 7748 { 7749 /* XXX Need some other mechanism to designate "free". */ 7750 /* 7751 * Invalidate the tag so that our abort 7752 * routines don't think it's active. 7753 ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL); 7754 */ 7755 } 7756 7757 /******************************** Error Handling ******************************/ 7758 /* 7759 * Abort all SCBs that match the given description (target/channel/lun/tag), 7760 * setting their status to the passed in status if the status has not already 7761 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 7762 * is paused before it is called. 7763 */ 7764 int 7765 ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel, 7766 int lun, u_int tag, role_t role, uint32_t status) 7767 { 7768 struct scb *scbp; 7769 struct scb *scbp_next; 7770 u_int i, j; 7771 u_int maxtarget; 7772 u_int minlun; 7773 u_int maxlun; 7774 int found; 7775 ahd_mode_state saved_modes; 7776 7777 /* restore this when we're done */ 7778 saved_modes = ahd_save_modes(ahd); 7779 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7780 7781 found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL, 7782 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 7783 7784 /* 7785 * Clean out the busy target table for any untagged commands. 7786 */ 7787 i = 0; 7788 maxtarget = 16; 7789 if (target != CAM_TARGET_WILDCARD) { 7790 i = target; 7791 if (channel == 'B') 7792 i += 8; 7793 maxtarget = i + 1; 7794 } 7795 7796 if (lun == CAM_LUN_WILDCARD) { 7797 minlun = 0; 7798 maxlun = AHD_NUM_LUNS_NONPKT; 7799 } else if (lun >= AHD_NUM_LUNS_NONPKT) { 7800 minlun = maxlun = 0; 7801 } else { 7802 minlun = lun; 7803 maxlun = lun + 1; 7804 } 7805 7806 if (role != ROLE_TARGET) { 7807 for (;i < maxtarget; i++) { 7808 for (j = minlun;j < maxlun; j++) { 7809 u_int scbid; 7810 u_int tcl; 7811 7812 tcl = BUILD_TCL_RAW(i, 'A', j); 7813 scbid = ahd_find_busy_tcl(ahd, tcl); 7814 scbp = ahd_lookup_scb(ahd, scbid); 7815 if (scbp == NULL 7816 || ahd_match_scb(ahd, scbp, target, channel, 7817 lun, tag, role) == 0) 7818 continue; 7819 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(i, 'A', j)); 7820 } 7821 } 7822 } 7823 7824 /* 7825 * Don't abort commands that have already completed, 7826 * but haven't quite made it up to the host yet. 7827 */ 7828 ahd_flush_qoutfifo(ahd); 7829 7830 /* 7831 * Go through the pending CCB list and look for 7832 * commands for this target that are still active. 7833 * These are other tagged commands that were 7834 * disconnected when the reset occurred. 7835 */ 7836 scbp_next = LIST_FIRST(&ahd->pending_scbs); 7837 while (scbp_next != NULL) { 7838 scbp = scbp_next; 7839 scbp_next = LIST_NEXT(scbp, pending_links); 7840 if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) { 7841 cam_status ostat; 7842 7843 ostat = aic_get_transaction_status(scbp); 7844 if (ostat == CAM_REQ_INPROG) 7845 aic_set_transaction_status(scbp, status); 7846 if (aic_get_transaction_status(scbp) != CAM_REQ_CMP) 7847 aic_freeze_scb(scbp); 7848 if ((scbp->flags & SCB_ACTIVE) == 0) 7849 printf("Inactive SCB on pending list\n"); 7850 ahd_done(ahd, scbp); 7851 found++; 7852 } 7853 } 7854 ahd_restore_modes(ahd, saved_modes); 7855 ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status); 7856 ahd->flags |= AHD_UPDATE_PEND_CMDS; 7857 return found; 7858 } 7859 7860 static void 7861 ahd_reset_current_bus(struct ahd_softc *ahd) 7862 { 7863 uint8_t scsiseq; 7864 7865 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7866 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENSCSIRST); 7867 scsiseq = ahd_inb(ahd, SCSISEQ0) & ~(ENSELO|ENARBO|SCSIRSTO); 7868 ahd_outb(ahd, SCSISEQ0, scsiseq | SCSIRSTO); 7869 ahd_flush_device_writes(ahd); 7870 aic_delay(AHD_BUSRESET_DELAY); 7871 /* Turn off the bus reset */ 7872 ahd_outb(ahd, SCSISEQ0, scsiseq); 7873 ahd_flush_device_writes(ahd); 7874 aic_delay(AHD_BUSRESET_DELAY); 7875 if ((ahd->bugs & AHD_SCSIRST_BUG) != 0) { 7876 /* 7877 * 2A Razor #474 7878 * Certain chip state is not cleared for 7879 * SCSI bus resets that we initiate, so 7880 * we must reset the chip. 7881 */ 7882 ahd_reset(ahd, /*reinit*/TRUE); 7883 ahd_intr_enable(ahd, /*enable*/TRUE); 7884 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 7885 } 7886 7887 ahd_clear_intstat(ahd); 7888 } 7889 7890 int 7891 ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset) 7892 { 7893 struct ahd_devinfo devinfo; 7894 u_int initiator; 7895 u_int target; 7896 u_int max_scsiid; 7897 int found; 7898 u_int fifo; 7899 u_int next_fifo; 7900 7901 ahd->pending_device = NULL; 7902 7903 ahd_compile_devinfo(&devinfo, 7904 CAM_TARGET_WILDCARD, 7905 CAM_TARGET_WILDCARD, 7906 CAM_LUN_WILDCARD, 7907 channel, ROLE_UNKNOWN); 7908 ahd_pause(ahd); 7909 7910 /* Make sure the sequencer is in a safe location. */ 7911 ahd_clear_critical_section(ahd); 7912 7913 #ifdef AHD_TARGET_MODE 7914 if ((ahd->flags & AHD_TARGETROLE) != 0) { 7915 ahd_run_tqinfifo(ahd, /*paused*/TRUE); 7916 } 7917 #endif 7918 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7919 7920 /* 7921 * Disable selections so no automatic hardware 7922 * functions will modify chip state. 7923 */ 7924 ahd_outb(ahd, SCSISEQ0, 0); 7925 ahd_outb(ahd, SCSISEQ1, 0); 7926 7927 /* 7928 * Safely shut down our DMA engines. Always start with 7929 * the FIFO that is not currently active (if any are 7930 * actively connected). 7931 */ 7932 next_fifo = fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO; 7933 if (next_fifo > CURRFIFO_1) 7934 /* If disconneced, arbitrarily start with FIFO1. */ 7935 next_fifo = fifo = 0; 7936 do { 7937 next_fifo ^= CURRFIFO_1; 7938 ahd_set_modes(ahd, next_fifo, next_fifo); 7939 ahd_outb(ahd, DFCNTRL, 7940 ahd_inb(ahd, DFCNTRL) & ~(SCSIEN|HDMAEN)); 7941 while ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) 7942 aic_delay(10); 7943 /* 7944 * Set CURRFIFO to the now inactive channel. 7945 */ 7946 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 7947 ahd_outb(ahd, DFFSTAT, next_fifo); 7948 } while (next_fifo != fifo); 7949 7950 /* 7951 * Reset the bus if we are initiating this reset 7952 */ 7953 ahd_clear_msg_state(ahd); 7954 ahd_outb(ahd, SIMODE1, 7955 ahd_inb(ahd, SIMODE1) & ~(ENBUSFREE|ENSCSIRST)); 7956 7957 if (initiate_reset) 7958 ahd_reset_current_bus(ahd); 7959 7960 ahd_clear_intstat(ahd); 7961 7962 /* 7963 * Clean up all the state information for the 7964 * pending transactions on this bus. 7965 */ 7966 found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel, 7967 CAM_LUN_WILDCARD, SCB_LIST_NULL, 7968 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 7969 7970 /* 7971 * Cleanup anything left in the FIFOs. 7972 */ 7973 ahd_clear_fifo(ahd, 0); 7974 ahd_clear_fifo(ahd, 1); 7975 7976 /* 7977 * Revert to async/narrow transfers until we renegotiate. 7978 */ 7979 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7; 7980 for (target = 0; target <= max_scsiid; target++) { 7981 if (ahd->enabled_targets[target] == NULL) 7982 continue; 7983 for (initiator = 0; initiator <= max_scsiid; initiator++) { 7984 struct ahd_devinfo devinfo; 7985 7986 ahd_compile_devinfo(&devinfo, target, initiator, 7987 CAM_LUN_WILDCARD, 7988 'A', ROLE_UNKNOWN); 7989 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 7990 AHD_TRANS_CUR, /*paused*/TRUE); 7991 ahd_set_syncrate(ahd, &devinfo, /*period*/0, 7992 /*offset*/0, /*ppr_options*/0, 7993 AHD_TRANS_CUR, /*paused*/TRUE); 7994 } 7995 } 7996 7997 #ifdef AHD_TARGET_MODE 7998 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7; 7999 8000 /* 8001 * Send an immediate notify ccb to all target more peripheral 8002 * drivers affected by this action. 8003 */ 8004 for (target = 0; target <= max_scsiid; target++) { 8005 struct ahd_tmode_tstate* tstate; 8006 u_int lun; 8007 8008 tstate = ahd->enabled_targets[target]; 8009 if (tstate == NULL) 8010 continue; 8011 for (lun = 0; lun < AHD_NUM_LUNS; lun++) { 8012 struct ahd_tmode_lstate* lstate; 8013 8014 lstate = tstate->enabled_luns[lun]; 8015 if (lstate == NULL) 8016 continue; 8017 8018 ahd_queue_lstate_event(ahd, lstate, CAM_TARGET_WILDCARD, 8019 EVENT_TYPE_BUS_RESET, /*arg*/0); 8020 ahd_send_lstate_events(ahd, lstate); 8021 } 8022 } 8023 #endif 8024 /* Notify the XPT that a bus reset occurred */ 8025 ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD, 8026 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL); 8027 ahd_restart(ahd); 8028 /* 8029 * Freeze the SIMQ until our poller can determine that 8030 * the bus reset has really gone away. We set the initial 8031 * timer to 0 to have the check performed as soon as possible 8032 * from the timer context. 8033 */ 8034 if ((ahd->flags & AHD_RESET_POLL_ACTIVE) == 0) { 8035 ahd->flags |= AHD_RESET_POLL_ACTIVE; 8036 aic_freeze_simq(ahd); 8037 aic_timer_reset(&ahd->reset_timer, 0, ahd_reset_poll, ahd); 8038 } 8039 return (found); 8040 } 8041 8042 #define AHD_RESET_POLL_MS 1 8043 static void 8044 ahd_reset_poll(void *arg) 8045 { 8046 struct ahd_softc *ahd = (struct ahd_softc *)arg; 8047 u_int scsiseq1; 8048 8049 ahd_lock(ahd); 8050 ahd_pause(ahd); 8051 ahd_update_modes(ahd); 8052 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 8053 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI); 8054 if ((ahd_inb(ahd, SSTAT1) & SCSIRSTI) != 0) { 8055 aic_timer_reset(&ahd->reset_timer, AHD_RESET_POLL_MS, 8056 ahd_reset_poll, ahd); 8057 ahd_unpause(ahd); 8058 ahd_unlock(ahd); 8059 return; 8060 } 8061 8062 /* Reset is now low. Complete chip reinitialization. */ 8063 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST); 8064 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 8065 ahd_outb(ahd, SCSISEQ1, scsiseq1 & (ENSELI|ENRSELI|ENAUTOATNP)); 8066 ahd_unpause(ahd); 8067 ahd->flags &= ~AHD_RESET_POLL_ACTIVE; 8068 aic_release_simq(ahd); 8069 ahd_unlock(ahd); 8070 } 8071 8072 /**************************** Statistics Processing ***************************/ 8073 static void 8074 ahd_stat_timer(void *arg) 8075 { 8076 struct ahd_softc *ahd = (struct ahd_softc *)arg; 8077 int enint_coal; 8078 8079 ahd_lock(ahd); 8080 enint_coal = ahd->hs_mailbox & ENINT_COALESCE; 8081 if (ahd->cmdcmplt_total > ahd->int_coalescing_threshold) 8082 enint_coal |= ENINT_COALESCE; 8083 else if (ahd->cmdcmplt_total < ahd->int_coalescing_stop_threshold) 8084 enint_coal &= ~ENINT_COALESCE; 8085 8086 if (enint_coal != (ahd->hs_mailbox & ENINT_COALESCE)) { 8087 ahd_enable_coalescing(ahd, enint_coal); 8088 #ifdef AHD_DEBUG 8089 if ((ahd_debug & AHD_SHOW_INT_COALESCING) != 0) 8090 printf("%s: Interrupt coalescing " 8091 "now %sabled. Cmds %d\n", 8092 ahd_name(ahd), 8093 (enint_coal & ENINT_COALESCE) ? "en" : "dis", 8094 ahd->cmdcmplt_total); 8095 #endif 8096 } 8097 8098 ahd->cmdcmplt_bucket = (ahd->cmdcmplt_bucket+1) & (AHD_STAT_BUCKETS-1); 8099 ahd->cmdcmplt_total -= ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket]; 8100 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket] = 0; 8101 aic_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_MS, 8102 ahd_stat_timer, ahd); 8103 ahd_unlock(ahd); 8104 } 8105 8106 /****************************** Status Processing *****************************/ 8107 void 8108 ahd_handle_scb_status(struct ahd_softc *ahd, struct scb *scb) 8109 { 8110 if (scb->hscb->shared_data.istatus.scsi_status != 0) { 8111 ahd_handle_scsi_status(ahd, scb); 8112 } else { 8113 ahd_calc_residual(ahd, scb); 8114 ahd_done(ahd, scb); 8115 } 8116 } 8117 8118 void 8119 ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb) 8120 { 8121 struct hardware_scb *hscb; 8122 int paused; 8123 8124 /* 8125 * The sequencer freezes its select-out queue 8126 * anytime a SCSI status error occurs. We must 8127 * handle the error and increment our qfreeze count 8128 * to allow the sequencer to continue. We don't 8129 * bother clearing critical sections here since all 8130 * operations are on data structures that the sequencer 8131 * is not touching once the queue is frozen. 8132 */ 8133 hscb = scb->hscb; 8134 8135 if (ahd_is_paused(ahd)) { 8136 paused = 1; 8137 } else { 8138 paused = 0; 8139 ahd_pause(ahd); 8140 } 8141 8142 /* Freeze the queue until the client sees the error. */ 8143 ahd_freeze_devq(ahd, scb); 8144 aic_freeze_scb(scb); 8145 ahd->qfreeze_cnt++; 8146 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt); 8147 8148 if (paused == 0) 8149 ahd_unpause(ahd); 8150 8151 /* Don't want to clobber the original sense code */ 8152 if ((scb->flags & SCB_SENSE) != 0) { 8153 /* 8154 * Clear the SCB_SENSE Flag and perform 8155 * a normal command completion. 8156 */ 8157 scb->flags &= ~SCB_SENSE; 8158 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 8159 ahd_done(ahd, scb); 8160 return; 8161 } 8162 aic_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR); 8163 aic_set_scsi_status(scb, hscb->shared_data.istatus.scsi_status); 8164 switch (hscb->shared_data.istatus.scsi_status) { 8165 case STATUS_PKT_SENSE: 8166 { 8167 struct scsi_status_iu_header *siu; 8168 8169 ahd_sync_sense(ahd, scb, BUS_DMASYNC_POSTREAD); 8170 siu = (struct scsi_status_iu_header *)scb->sense_data; 8171 aic_set_scsi_status(scb, siu->status); 8172 #ifdef AHD_DEBUG 8173 if ((ahd_debug & AHD_SHOW_SENSE) != 0) { 8174 ahd_print_path(ahd, scb); 8175 printf("SCB 0x%x Received PKT Status of 0x%x\n", 8176 SCB_GET_TAG(scb), siu->status); 8177 printf("\tflags = 0x%x, sense len = 0x%x, " 8178 "pktfail = 0x%x\n", 8179 siu->flags, scsi_4btoul(siu->sense_length), 8180 scsi_4btoul(siu->pkt_failures_length)); 8181 } 8182 #endif 8183 if ((siu->flags & SIU_RSPVALID) != 0) { 8184 ahd_print_path(ahd, scb); 8185 if (scsi_4btoul(siu->pkt_failures_length) < 4) { 8186 printf("Unable to parse pkt_failures\n"); 8187 } else { 8188 switch (SIU_PKTFAIL_CODE(siu)) { 8189 case SIU_PFC_NONE: 8190 printf("No packet failure found\n"); 8191 AHD_UNCORRECTABLE_ERROR(ahd); 8192 break; 8193 case SIU_PFC_CIU_FIELDS_INVALID: 8194 printf("Invalid Command IU Field\n"); 8195 AHD_UNCORRECTABLE_ERROR(ahd); 8196 break; 8197 case SIU_PFC_TMF_NOT_SUPPORTED: 8198 printf("TMF not supportd\n"); 8199 AHD_UNCORRECTABLE_ERROR(ahd); 8200 break; 8201 case SIU_PFC_TMF_FAILED: 8202 printf("TMF failed\n"); 8203 AHD_UNCORRECTABLE_ERROR(ahd); 8204 break; 8205 case SIU_PFC_INVALID_TYPE_CODE: 8206 printf("Invalid L_Q Type code\n"); 8207 AHD_UNCORRECTABLE_ERROR(ahd); 8208 break; 8209 case SIU_PFC_ILLEGAL_REQUEST: 8210 AHD_UNCORRECTABLE_ERROR(ahd); 8211 printf("Illegal request\n"); 8212 default: 8213 break; 8214 } 8215 } 8216 if (siu->status == SCSI_STATUS_OK) 8217 aic_set_transaction_status(scb, 8218 CAM_REQ_CMP_ERR); 8219 } 8220 if ((siu->flags & SIU_SNSVALID) != 0) { 8221 scb->flags |= SCB_PKT_SENSE; 8222 #ifdef AHD_DEBUG 8223 if ((ahd_debug & AHD_SHOW_SENSE) != 0) 8224 printf("Sense data available\n"); 8225 #endif 8226 } 8227 ahd_done(ahd, scb); 8228 break; 8229 } 8230 case SCSI_STATUS_CMD_TERMINATED: 8231 case SCSI_STATUS_CHECK_COND: 8232 { 8233 struct ahd_devinfo devinfo; 8234 struct ahd_dma_seg *sg; 8235 struct scsi_sense *sc; 8236 struct ahd_initiator_tinfo *targ_info; 8237 struct ahd_tmode_tstate *tstate; 8238 struct ahd_transinfo *tinfo; 8239 #ifdef AHD_DEBUG 8240 if (ahd_debug & AHD_SHOW_SENSE) { 8241 ahd_print_path(ahd, scb); 8242 printf("SCB %d: requests Check Status\n", 8243 SCB_GET_TAG(scb)); 8244 } 8245 #endif 8246 8247 if (aic_perform_autosense(scb) == 0) 8248 break; 8249 8250 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb), 8251 SCB_GET_TARGET(ahd, scb), 8252 SCB_GET_LUN(scb), 8253 SCB_GET_CHANNEL(ahd, scb), 8254 ROLE_INITIATOR); 8255 targ_info = ahd_fetch_transinfo(ahd, 8256 devinfo.channel, 8257 devinfo.our_scsiid, 8258 devinfo.target, 8259 &tstate); 8260 tinfo = &targ_info->curr; 8261 sg = scb->sg_list; 8262 sc = (struct scsi_sense *)hscb->shared_data.idata.cdb; 8263 /* 8264 * Save off the residual if there is one. 8265 */ 8266 ahd_update_residual(ahd, scb); 8267 #ifdef AHD_DEBUG 8268 if (ahd_debug & AHD_SHOW_SENSE) { 8269 ahd_print_path(ahd, scb); 8270 printf("Sending Sense\n"); 8271 } 8272 #endif 8273 scb->sg_count = 0; 8274 sg = ahd_sg_setup(ahd, scb, sg, ahd_get_sense_bufaddr(ahd, scb), 8275 aic_get_sense_bufsize(ahd, scb), 8276 /*last*/TRUE); 8277 sc->opcode = REQUEST_SENSE; 8278 sc->byte2 = 0; 8279 if (tinfo->protocol_version <= SCSI_REV_2 8280 && SCB_GET_LUN(scb) < 8) 8281 sc->byte2 = SCB_GET_LUN(scb) << 5; 8282 sc->unused[0] = 0; 8283 sc->unused[1] = 0; 8284 sc->length = aic_get_sense_bufsize(ahd, scb); 8285 sc->control = 0; 8286 8287 /* 8288 * We can't allow the target to disconnect. 8289 * This will be an untagged transaction and 8290 * having the target disconnect will make this 8291 * transaction indestinguishable from outstanding 8292 * tagged transactions. 8293 */ 8294 hscb->control = 0; 8295 8296 /* 8297 * This request sense could be because the 8298 * the device lost power or in some other 8299 * way has lost our transfer negotiations. 8300 * Renegotiate if appropriate. Unit attention 8301 * errors will be reported before any data 8302 * phases occur. 8303 */ 8304 if (aic_get_residual(scb) == aic_get_transfer_length(scb)) { 8305 ahd_update_neg_request(ahd, &devinfo, 8306 tstate, targ_info, 8307 AHD_NEG_IF_NON_ASYNC); 8308 } 8309 if (tstate->auto_negotiate & devinfo.target_mask) { 8310 hscb->control |= MK_MESSAGE; 8311 scb->flags &= 8312 ~(SCB_NEGOTIATE|SCB_ABORT|SCB_DEVICE_RESET); 8313 scb->flags |= SCB_AUTO_NEGOTIATE; 8314 } 8315 hscb->cdb_len = sizeof(*sc); 8316 ahd_setup_data_scb(ahd, scb); 8317 scb->flags |= SCB_SENSE; 8318 ahd_queue_scb(ahd, scb); 8319 /* 8320 * Ensure we have enough time to actually 8321 * retrieve the sense, but only schedule 8322 * the timer if we are not in recovery or 8323 * this is a recovery SCB that is allowed 8324 * to have an active timer. 8325 */ 8326 if (ahd->scb_data.recovery_scbs == 0 8327 || (scb->flags & SCB_RECOVERY_SCB) != 0) 8328 aic_scb_timer_reset(scb, 5 * 1000); 8329 break; 8330 } 8331 case SCSI_STATUS_OK: 8332 printf("%s: Interrupted for staus of 0???\n", 8333 ahd_name(ahd)); 8334 /* FALLTHROUGH */ 8335 default: 8336 ahd_done(ahd, scb); 8337 break; 8338 } 8339 } 8340 8341 /* 8342 * Calculate the residual for a just completed SCB. 8343 */ 8344 void 8345 ahd_calc_residual(struct ahd_softc *ahd, struct scb *scb) 8346 { 8347 struct hardware_scb *hscb; 8348 struct initiator_status *spkt; 8349 uint32_t sgptr; 8350 uint32_t resid_sgptr; 8351 uint32_t resid; 8352 8353 /* 8354 * 5 cases. 8355 * 1) No residual. 8356 * SG_STATUS_VALID clear in sgptr. 8357 * 2) Transferless command 8358 * 3) Never performed any transfers. 8359 * sgptr has SG_FULL_RESID set. 8360 * 4) No residual but target did not 8361 * save data pointers after the 8362 * last transfer, so sgptr was 8363 * never updated. 8364 * 5) We have a partial residual. 8365 * Use residual_sgptr to determine 8366 * where we are. 8367 */ 8368 8369 hscb = scb->hscb; 8370 sgptr = aic_le32toh(hscb->sgptr); 8371 if ((sgptr & SG_STATUS_VALID) == 0) 8372 /* Case 1 */ 8373 return; 8374 sgptr &= ~SG_STATUS_VALID; 8375 8376 if ((sgptr & SG_LIST_NULL) != 0) 8377 /* Case 2 */ 8378 return; 8379 8380 /* 8381 * Residual fields are the same in both 8382 * target and initiator status packets, 8383 * so we can always use the initiator fields 8384 * regardless of the role for this SCB. 8385 */ 8386 spkt = &hscb->shared_data.istatus; 8387 resid_sgptr = aic_le32toh(spkt->residual_sgptr); 8388 if ((sgptr & SG_FULL_RESID) != 0) { 8389 /* Case 3 */ 8390 resid = aic_get_transfer_length(scb); 8391 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 8392 /* Case 4 */ 8393 return; 8394 } else if ((resid_sgptr & SG_OVERRUN_RESID) != 0) { 8395 ahd_print_path(ahd, scb); 8396 printf("data overrun detected Tag == 0x%x.\n", 8397 SCB_GET_TAG(scb)); 8398 ahd_freeze_devq(ahd, scb); 8399 aic_set_transaction_status(scb, CAM_DATA_RUN_ERR); 8400 aic_freeze_scb(scb); 8401 return; 8402 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 8403 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 8404 /* NOTREACHED */ 8405 } else { 8406 struct ahd_dma_seg *sg; 8407 8408 /* 8409 * Remainder of the SG where the transfer 8410 * stopped. 8411 */ 8412 resid = aic_le32toh(spkt->residual_datacnt) & AHD_SG_LEN_MASK; 8413 sg = ahd_sg_bus_to_virt(ahd, scb, resid_sgptr & SG_PTR_MASK); 8414 8415 /* The residual sg_ptr always points to the next sg */ 8416 sg--; 8417 8418 /* 8419 * Add up the contents of all residual 8420 * SG segments that are after the SG where 8421 * the transfer stopped. 8422 */ 8423 while ((aic_le32toh(sg->len) & AHD_DMA_LAST_SEG) == 0) { 8424 sg++; 8425 resid += aic_le32toh(sg->len) & AHD_SG_LEN_MASK; 8426 } 8427 } 8428 if ((scb->flags & SCB_SENSE) == 0) 8429 aic_set_residual(scb, resid); 8430 else 8431 aic_set_sense_residual(scb, resid); 8432 8433 #ifdef AHD_DEBUG 8434 if ((ahd_debug & AHD_SHOW_MISC) != 0) { 8435 ahd_print_path(ahd, scb); 8436 printf("Handled %sResidual of %d bytes\n", 8437 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 8438 } 8439 #endif 8440 } 8441 8442 /******************************* Target Mode **********************************/ 8443 #ifdef AHD_TARGET_MODE 8444 /* 8445 * Add a target mode event to this lun's queue 8446 */ 8447 static void 8448 ahd_queue_lstate_event(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate, 8449 u_int initiator_id, u_int event_type, u_int event_arg) 8450 { 8451 struct ahd_tmode_event *event; 8452 int pending; 8453 8454 xpt_freeze_devq(lstate->path, /*count*/1); 8455 if (lstate->event_w_idx >= lstate->event_r_idx) 8456 pending = lstate->event_w_idx - lstate->event_r_idx; 8457 else 8458 pending = AHD_TMODE_EVENT_BUFFER_SIZE + 1 8459 - (lstate->event_r_idx - lstate->event_w_idx); 8460 8461 if (event_type == EVENT_TYPE_BUS_RESET 8462 || event_type == MSG_BUS_DEV_RESET) { 8463 /* 8464 * Any earlier events are irrelevant, so reset our buffer. 8465 * This has the effect of allowing us to deal with reset 8466 * floods (an external device holding down the reset line) 8467 * without losing the event that is really interesting. 8468 */ 8469 lstate->event_r_idx = 0; 8470 lstate->event_w_idx = 0; 8471 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 8472 } 8473 8474 if (pending == AHD_TMODE_EVENT_BUFFER_SIZE) { 8475 xpt_print_path(lstate->path); 8476 printf("immediate event %x:%x lost\n", 8477 lstate->event_buffer[lstate->event_r_idx].event_type, 8478 lstate->event_buffer[lstate->event_r_idx].event_arg); 8479 lstate->event_r_idx++; 8480 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 8481 lstate->event_r_idx = 0; 8482 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 8483 } 8484 8485 event = &lstate->event_buffer[lstate->event_w_idx]; 8486 event->initiator_id = initiator_id; 8487 event->event_type = event_type; 8488 event->event_arg = event_arg; 8489 lstate->event_w_idx++; 8490 if (lstate->event_w_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 8491 lstate->event_w_idx = 0; 8492 } 8493 8494 /* 8495 * Send any target mode events queued up waiting 8496 * for immediate notify resources. 8497 */ 8498 void 8499 ahd_send_lstate_events(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate) 8500 { 8501 struct ccb_hdr *ccbh; 8502 struct ccb_immediate_notify *inot; 8503 8504 while (lstate->event_r_idx != lstate->event_w_idx 8505 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 8506 struct ahd_tmode_event *event; 8507 8508 event = &lstate->event_buffer[lstate->event_r_idx]; 8509 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 8510 inot = (struct ccb_immediate_notify *)ccbh; 8511 switch (event->event_type) { 8512 case EVENT_TYPE_BUS_RESET: 8513 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 8514 break; 8515 default: 8516 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 8517 inot->arg = event->event_type; 8518 inot->seq_id = event->event_arg; 8519 break; 8520 } 8521 inot->initiator_id = event->initiator_id; 8522 xpt_done((union ccb *)inot); 8523 lstate->event_r_idx++; 8524 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE) 8525 lstate->event_r_idx = 0; 8526 } 8527 } 8528 #endif 8529 8530 /******************** Sequencer Program Patching/Download *********************/ 8531 8532 #ifdef AHD_DUMP_SEQ 8533 void 8534 ahd_dumpseq(struct ahd_softc* ahd) 8535 { 8536 int i; 8537 int max_prog; 8538 8539 max_prog = 2048; 8540 8541 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 8542 ahd_outw(ahd, PRGMCNT, 0); 8543 for (i = 0; i < max_prog; i++) { 8544 uint8_t ins_bytes[4]; 8545 8546 ahd_insb(ahd, SEQRAM, ins_bytes, 4); 8547 printf("0x%08x\n", ins_bytes[0] << 24 8548 | ins_bytes[1] << 16 8549 | ins_bytes[2] << 8 8550 | ins_bytes[3]); 8551 } 8552 } 8553 #endif 8554 8555 static void 8556 ahd_loadseq(struct ahd_softc *ahd) 8557 { 8558 struct cs cs_table[num_critical_sections]; 8559 u_int begin_set[num_critical_sections]; 8560 u_int end_set[num_critical_sections]; 8561 struct patch *cur_patch; 8562 u_int cs_count; 8563 u_int cur_cs; 8564 u_int i; 8565 int downloaded; 8566 u_int skip_addr; 8567 u_int sg_prefetch_cnt; 8568 u_int sg_prefetch_cnt_limit; 8569 u_int sg_prefetch_align; 8570 u_int sg_size; 8571 u_int cacheline_mask; 8572 uint8_t download_consts[DOWNLOAD_CONST_COUNT]; 8573 8574 if (bootverbose) 8575 printf("%s: Downloading Sequencer Program...", 8576 ahd_name(ahd)); 8577 8578 #if DOWNLOAD_CONST_COUNT != 8 8579 #error "Download Const Mismatch" 8580 #endif 8581 /* 8582 * Start out with 0 critical sections 8583 * that apply to this firmware load. 8584 */ 8585 cs_count = 0; 8586 cur_cs = 0; 8587 memset(begin_set, 0, sizeof(begin_set)); 8588 memset(end_set, 0, sizeof(end_set)); 8589 8590 /* 8591 * Setup downloadable constant table. 8592 * 8593 * The computation for the S/G prefetch variables is 8594 * a bit complicated. We would like to always fetch 8595 * in terms of cachelined sized increments. However, 8596 * if the cacheline is not an even multiple of the 8597 * SG element size or is larger than our SG RAM, using 8598 * just the cache size might leave us with only a portion 8599 * of an SG element at the tail of a prefetch. If the 8600 * cacheline is larger than our S/G prefetch buffer less 8601 * the size of an SG element, we may round down to a cacheline 8602 * that doesn't contain any or all of the S/G of interest 8603 * within the bounds of our S/G ram. Provide variables to 8604 * the sequencer that will allow it to handle these edge 8605 * cases. 8606 */ 8607 /* Start by aligning to the nearest cacheline. */ 8608 sg_prefetch_align = ahd->pci_cachesize; 8609 if (sg_prefetch_align == 0) 8610 sg_prefetch_align = 8; 8611 /* Round down to the nearest power of 2. */ 8612 while (powerof2(sg_prefetch_align) == 0) 8613 sg_prefetch_align--; 8614 8615 cacheline_mask = sg_prefetch_align - 1; 8616 8617 /* 8618 * If the cacheline boundary is greater than half our prefetch RAM 8619 * we risk not being able to fetch even a single complete S/G 8620 * segment if we align to that boundary. 8621 */ 8622 if (sg_prefetch_align > CCSGADDR_MAX/2) 8623 sg_prefetch_align = CCSGADDR_MAX/2; 8624 /* Start by fetching a single cacheline. */ 8625 sg_prefetch_cnt = sg_prefetch_align; 8626 /* 8627 * Increment the prefetch count by cachelines until 8628 * at least one S/G element will fit. 8629 */ 8630 sg_size = sizeof(struct ahd_dma_seg); 8631 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) 8632 sg_size = sizeof(struct ahd_dma64_seg); 8633 while (sg_prefetch_cnt < sg_size) 8634 sg_prefetch_cnt += sg_prefetch_align; 8635 /* 8636 * If the cacheline is not an even multiple of 8637 * the S/G size, we may only get a partial S/G when 8638 * we align. Add a cacheline if this is the case. 8639 */ 8640 if ((sg_prefetch_align % sg_size) != 0 8641 && (sg_prefetch_cnt < CCSGADDR_MAX)) 8642 sg_prefetch_cnt += sg_prefetch_align; 8643 /* 8644 * Lastly, compute a value that the sequencer can use 8645 * to determine if the remainder of the CCSGRAM buffer 8646 * has a full S/G element in it. 8647 */ 8648 sg_prefetch_cnt_limit = -(sg_prefetch_cnt - sg_size + 1); 8649 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 8650 download_consts[SG_PREFETCH_CNT_LIMIT] = sg_prefetch_cnt_limit; 8651 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_align - 1); 8652 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_align - 1); 8653 download_consts[SG_SIZEOF] = sg_size; 8654 download_consts[PKT_OVERRUN_BUFOFFSET] = 8655 (ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256; 8656 download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_1BYTE_LUN; 8657 download_consts[CACHELINE_MASK] = cacheline_mask; 8658 cur_patch = patches; 8659 downloaded = 0; 8660 skip_addr = 0; 8661 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 8662 ahd_outw(ahd, PRGMCNT, 0); 8663 8664 for (i = 0; i < sizeof(seqprog)/4; i++) { 8665 if (ahd_check_patch(ahd, &cur_patch, i, &skip_addr) == 0) { 8666 /* 8667 * Don't download this instruction as it 8668 * is in a patch that was removed. 8669 */ 8670 continue; 8671 } 8672 /* 8673 * Move through the CS table until we find a CS 8674 * that might apply to this instruction. 8675 */ 8676 for (; cur_cs < num_critical_sections; cur_cs++) { 8677 if (critical_sections[cur_cs].end <= i) { 8678 if (begin_set[cs_count] == TRUE 8679 && end_set[cs_count] == FALSE) { 8680 cs_table[cs_count].end = downloaded; 8681 end_set[cs_count] = TRUE; 8682 cs_count++; 8683 } 8684 continue; 8685 } 8686 if (critical_sections[cur_cs].begin <= i 8687 && begin_set[cs_count] == FALSE) { 8688 cs_table[cs_count].begin = downloaded; 8689 begin_set[cs_count] = TRUE; 8690 } 8691 break; 8692 } 8693 ahd_download_instr(ahd, i, download_consts); 8694 downloaded++; 8695 } 8696 8697 ahd->num_critical_sections = cs_count; 8698 if (cs_count != 0) { 8699 cs_count *= sizeof(struct cs); 8700 ahd->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 8701 if (ahd->critical_sections == NULL) 8702 panic("ahd_loadseq: Could not malloc"); 8703 memcpy(ahd->critical_sections, cs_table, cs_count); 8704 } 8705 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE); 8706 8707 if (bootverbose) { 8708 printf(" %d instructions downloaded\n", downloaded); 8709 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 8710 ahd_name(ahd), ahd->features, ahd->bugs, ahd->flags); 8711 } 8712 } 8713 8714 static int 8715 ahd_check_patch(struct ahd_softc *ahd, struct patch **start_patch, 8716 u_int start_instr, u_int *skip_addr) 8717 { 8718 struct patch *cur_patch; 8719 struct patch *last_patch; 8720 u_int num_patches; 8721 8722 num_patches = sizeof(patches)/sizeof(struct patch); 8723 last_patch = &patches[num_patches]; 8724 cur_patch = *start_patch; 8725 8726 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 8727 if (cur_patch->patch_func(ahd) == 0) { 8728 /* Start rejecting code */ 8729 *skip_addr = start_instr + cur_patch->skip_instr; 8730 cur_patch += cur_patch->skip_patch; 8731 } else { 8732 /* Accepted this patch. Advance to the next 8733 * one and wait for our instruction pointer to 8734 * hit this point. 8735 */ 8736 cur_patch++; 8737 } 8738 } 8739 8740 *start_patch = cur_patch; 8741 if (start_instr < *skip_addr) 8742 /* Still skipping */ 8743 return (0); 8744 8745 return (1); 8746 } 8747 8748 static u_int 8749 ahd_resolve_seqaddr(struct ahd_softc *ahd, u_int address) 8750 { 8751 struct patch *cur_patch; 8752 int address_offset; 8753 u_int skip_addr; 8754 u_int i; 8755 8756 address_offset = 0; 8757 cur_patch = patches; 8758 skip_addr = 0; 8759 8760 for (i = 0; i < address;) { 8761 ahd_check_patch(ahd, &cur_patch, i, &skip_addr); 8762 8763 if (skip_addr > i) { 8764 int end_addr; 8765 8766 end_addr = MIN(address, skip_addr); 8767 address_offset += end_addr - i; 8768 i = skip_addr; 8769 } else { 8770 i++; 8771 } 8772 } 8773 return (address - address_offset); 8774 } 8775 8776 static void 8777 ahd_download_instr(struct ahd_softc *ahd, u_int instrptr, uint8_t *dconsts) 8778 { 8779 union ins_formats instr; 8780 struct ins_format1 *fmt1_ins; 8781 struct ins_format3 *fmt3_ins; 8782 u_int opcode; 8783 8784 /* 8785 * The firmware is always compiled into a little endian format. 8786 */ 8787 instr.integer = aic_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 8788 8789 fmt1_ins = &instr.format1; 8790 fmt3_ins = NULL; 8791 8792 /* Pull the opcode */ 8793 opcode = instr.format1.opcode; 8794 switch (opcode) { 8795 case AIC_OP_JMP: 8796 case AIC_OP_JC: 8797 case AIC_OP_JNC: 8798 case AIC_OP_CALL: 8799 case AIC_OP_JNE: 8800 case AIC_OP_JNZ: 8801 case AIC_OP_JE: 8802 case AIC_OP_JZ: 8803 { 8804 fmt3_ins = &instr.format3; 8805 fmt3_ins->address = ahd_resolve_seqaddr(ahd, fmt3_ins->address); 8806 /* FALLTHROUGH */ 8807 } 8808 case AIC_OP_OR: 8809 case AIC_OP_AND: 8810 case AIC_OP_XOR: 8811 case AIC_OP_ADD: 8812 case AIC_OP_ADC: 8813 case AIC_OP_BMOV: 8814 if (fmt1_ins->parity != 0) { 8815 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 8816 } 8817 fmt1_ins->parity = 0; 8818 /* FALLTHROUGH */ 8819 case AIC_OP_ROL: 8820 { 8821 int i, count; 8822 8823 /* Calculate odd parity for the instruction */ 8824 for (i = 0, count = 0; i < 31; i++) { 8825 uint32_t mask; 8826 8827 mask = 0x01 << i; 8828 if ((instr.integer & mask) != 0) 8829 count++; 8830 } 8831 if ((count & 0x01) == 0) 8832 instr.format1.parity = 1; 8833 8834 /* The sequencer is a little endian cpu */ 8835 instr.integer = aic_htole32(instr.integer); 8836 ahd_outsb(ahd, SEQRAM, instr.bytes, 4); 8837 break; 8838 } 8839 default: 8840 panic("Unknown opcode encountered in seq program"); 8841 break; 8842 } 8843 } 8844 8845 static int 8846 ahd_probe_stack_size(struct ahd_softc *ahd) 8847 { 8848 int last_probe; 8849 8850 last_probe = 0; 8851 while (1) { 8852 int i; 8853 8854 /* 8855 * We avoid using 0 as a pattern to avoid 8856 * confusion if the stack implementation 8857 * "back-fills" with zeros when "poping' 8858 * entries. 8859 */ 8860 for (i = 1; i <= last_probe+1; i++) { 8861 ahd_outb(ahd, STACK, i & 0xFF); 8862 ahd_outb(ahd, STACK, (i >> 8) & 0xFF); 8863 } 8864 8865 /* Verify */ 8866 for (i = last_probe+1; i > 0; i--) { 8867 u_int stack_entry; 8868 8869 stack_entry = ahd_inb(ahd, STACK) 8870 |(ahd_inb(ahd, STACK) << 8); 8871 if (stack_entry != i) 8872 goto sized; 8873 } 8874 last_probe++; 8875 } 8876 sized: 8877 return (last_probe); 8878 } 8879 8880 void 8881 ahd_dump_all_cards_state(void) 8882 { 8883 struct ahd_softc *list_ahd; 8884 8885 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) { 8886 ahd_dump_card_state(list_ahd); 8887 } 8888 } 8889 8890 int 8891 ahd_print_register(ahd_reg_parse_entry_t *table, u_int num_entries, 8892 const char *name, u_int address, u_int value, 8893 u_int *cur_column, u_int wrap_point) 8894 { 8895 int printed; 8896 u_int printed_mask; 8897 u_int dummy_column; 8898 8899 if (cur_column == NULL) { 8900 dummy_column = 0; 8901 cur_column = &dummy_column; 8902 } 8903 8904 if (cur_column != NULL && *cur_column >= wrap_point) { 8905 printf("\n"); 8906 *cur_column = 0; 8907 } 8908 printed = printf("%s[0x%x]", name, value); 8909 if (table == NULL) { 8910 printed += printf(" "); 8911 *cur_column += printed; 8912 return (printed); 8913 } 8914 printed_mask = 0; 8915 while (printed_mask != 0xFF) { 8916 int entry; 8917 8918 for (entry = 0; entry < num_entries; entry++) { 8919 if (((value & table[entry].mask) 8920 != table[entry].value) 8921 || ((printed_mask & table[entry].mask) 8922 == table[entry].mask)) 8923 continue; 8924 8925 printed += printf("%s%s", 8926 printed_mask == 0 ? ":(" : "|", 8927 table[entry].name); 8928 printed_mask |= table[entry].mask; 8929 8930 break; 8931 } 8932 if (entry >= num_entries) 8933 break; 8934 } 8935 if (printed_mask != 0) 8936 printed += printf(") "); 8937 else 8938 printed += printf(" "); 8939 *cur_column += printed; 8940 return (printed); 8941 } 8942 8943 void 8944 ahd_dump_card_state(struct ahd_softc *ahd) 8945 { 8946 struct scb *scb; 8947 ahd_mode_state saved_modes; 8948 u_int dffstat; 8949 int paused; 8950 u_int scb_index; 8951 u_int saved_scb_index; 8952 u_int cur_col; 8953 int i; 8954 8955 if (ahd_is_paused(ahd)) { 8956 paused = 1; 8957 } else { 8958 paused = 0; 8959 ahd_pause(ahd); 8960 } 8961 saved_modes = ahd_save_modes(ahd); 8962 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 8963 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 8964 "%s: Dumping Card State at program address 0x%x Mode 0x%x\n", 8965 ahd_name(ahd), 8966 ahd_inw(ahd, CURADDR), 8967 ahd_build_mode_state(ahd, ahd->saved_src_mode, 8968 ahd->saved_dst_mode)); 8969 if (paused) 8970 printf("Card was paused\n"); 8971 8972 if (ahd_check_cmdcmpltqueues(ahd)) 8973 printf("Completions are pending\n"); 8974 8975 /* 8976 * Mode independent registers. 8977 */ 8978 cur_col = 0; 8979 ahd_intstat_print(ahd_inb(ahd, INTSTAT), &cur_col, 50); 8980 ahd_seloid_print(ahd_inb(ahd, SELOID), &cur_col, 50); 8981 ahd_selid_print(ahd_inb(ahd, SELID), &cur_col, 50); 8982 ahd_hs_mailbox_print(ahd_inb(ahd, LOCAL_HS_MAILBOX), &cur_col, 50); 8983 ahd_intctl_print(ahd_inb(ahd, INTCTL), &cur_col, 50); 8984 ahd_seqintstat_print(ahd_inb(ahd, SEQINTSTAT), &cur_col, 50); 8985 ahd_saved_mode_print(ahd_inb(ahd, SAVED_MODE), &cur_col, 50); 8986 ahd_dffstat_print(ahd_inb(ahd, DFFSTAT), &cur_col, 50); 8987 ahd_scsisigi_print(ahd_inb(ahd, SCSISIGI), &cur_col, 50); 8988 ahd_scsiphase_print(ahd_inb(ahd, SCSIPHASE), &cur_col, 50); 8989 ahd_scsibus_print(ahd_inb(ahd, SCSIBUS), &cur_col, 50); 8990 ahd_lastphase_print(ahd_inb(ahd, LASTPHASE), &cur_col, 50); 8991 ahd_scsiseq0_print(ahd_inb(ahd, SCSISEQ0), &cur_col, 50); 8992 ahd_scsiseq1_print(ahd_inb(ahd, SCSISEQ1), &cur_col, 50); 8993 ahd_seqctl0_print(ahd_inb(ahd, SEQCTL0), &cur_col, 50); 8994 ahd_seqintctl_print(ahd_inb(ahd, SEQINTCTL), &cur_col, 50); 8995 ahd_seq_flags_print(ahd_inb(ahd, SEQ_FLAGS), &cur_col, 50); 8996 ahd_seq_flags2_print(ahd_inb(ahd, SEQ_FLAGS2), &cur_col, 50); 8997 ahd_qfreeze_count_print(ahd_inw(ahd, QFREEZE_COUNT), &cur_col, 50); 8998 ahd_kernel_qfreeze_count_print(ahd_inw(ahd, KERNEL_QFREEZE_COUNT), 8999 &cur_col, 50); 9000 ahd_mk_message_scb_print(ahd_inw(ahd, MK_MESSAGE_SCB), &cur_col, 50); 9001 ahd_mk_message_scsiid_print(ahd_inb(ahd, MK_MESSAGE_SCSIID), 9002 &cur_col, 50); 9003 ahd_sstat0_print(ahd_inb(ahd, SSTAT0), &cur_col, 50); 9004 ahd_sstat1_print(ahd_inb(ahd, SSTAT1), &cur_col, 50); 9005 ahd_sstat2_print(ahd_inb(ahd, SSTAT2), &cur_col, 50); 9006 ahd_sstat3_print(ahd_inb(ahd, SSTAT3), &cur_col, 50); 9007 ahd_perrdiag_print(ahd_inb(ahd, PERRDIAG), &cur_col, 50); 9008 ahd_simode1_print(ahd_inb(ahd, SIMODE1), &cur_col, 50); 9009 ahd_lqistat0_print(ahd_inb(ahd, LQISTAT0), &cur_col, 50); 9010 ahd_lqistat1_print(ahd_inb(ahd, LQISTAT1), &cur_col, 50); 9011 ahd_lqistat2_print(ahd_inb(ahd, LQISTAT2), &cur_col, 50); 9012 ahd_lqostat0_print(ahd_inb(ahd, LQOSTAT0), &cur_col, 50); 9013 ahd_lqostat1_print(ahd_inb(ahd, LQOSTAT1), &cur_col, 50); 9014 ahd_lqostat2_print(ahd_inb(ahd, LQOSTAT2), &cur_col, 50); 9015 printf("\n"); 9016 printf("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x " 9017 "CURRSCB 0x%x NEXTSCB 0x%x\n", 9018 ahd->scb_data.numscbs, ahd_inw(ahd, CMDS_PENDING), 9019 ahd_inw(ahd, LASTSCB), ahd_inw(ahd, CURRSCB), 9020 ahd_inw(ahd, NEXTSCB)); 9021 cur_col = 0; 9022 /* QINFIFO */ 9023 ahd_search_qinfifo(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS, 9024 CAM_LUN_WILDCARD, SCB_LIST_NULL, 9025 ROLE_UNKNOWN, /*status*/0, SEARCH_PRINT); 9026 saved_scb_index = ahd_get_scbptr(ahd); 9027 printf("Pending list:"); 9028 i = 0; 9029 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 9030 if (i++ > AHD_SCB_MAX) 9031 break; 9032 cur_col = printf("\n%3d FIFO_USE[0x%x] ", SCB_GET_TAG(scb), 9033 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT)); 9034 ahd_set_scbptr(ahd, SCB_GET_TAG(scb)); 9035 ahd_scb_control_print(ahd_inb_scbram(ahd, SCB_CONTROL), 9036 &cur_col, 60); 9037 ahd_scb_scsiid_print(ahd_inb_scbram(ahd, SCB_SCSIID), 9038 &cur_col, 60); 9039 } 9040 printf("\nTotal %d\n", i); 9041 9042 printf("Kernel Free SCB lists: "); 9043 i = 0; 9044 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) { 9045 struct scb *list_scb; 9046 9047 printf("\n COLIDX[%d]: ", AHD_GET_SCB_COL_IDX(ahd, scb)); 9048 list_scb = scb; 9049 do { 9050 printf("%d ", SCB_GET_TAG(list_scb)); 9051 list_scb = LIST_NEXT(list_scb, collision_links); 9052 } while (list_scb && i++ < AHD_SCB_MAX); 9053 } 9054 9055 printf("\n Any Device: "); 9056 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) { 9057 if (i++ > AHD_SCB_MAX) 9058 break; 9059 printf("%d ", SCB_GET_TAG(scb)); 9060 } 9061 printf("\n"); 9062 9063 printf("Sequencer Complete DMA-inprog list: "); 9064 scb_index = ahd_inw(ahd, COMPLETE_SCB_DMAINPROG_HEAD); 9065 i = 0; 9066 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 9067 ahd_set_scbptr(ahd, scb_index); 9068 printf("%d ", scb_index); 9069 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 9070 } 9071 printf("\n"); 9072 9073 printf("Sequencer Complete list: "); 9074 scb_index = ahd_inw(ahd, COMPLETE_SCB_HEAD); 9075 i = 0; 9076 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 9077 ahd_set_scbptr(ahd, scb_index); 9078 printf("%d ", scb_index); 9079 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 9080 } 9081 printf("\n"); 9082 9083 printf("Sequencer DMA-Up and Complete list: "); 9084 scb_index = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD); 9085 i = 0; 9086 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 9087 ahd_set_scbptr(ahd, scb_index); 9088 printf("%d ", scb_index); 9089 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 9090 } 9091 printf("\n"); 9092 printf("Sequencer On QFreeze and Complete list: "); 9093 scb_index = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD); 9094 i = 0; 9095 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) { 9096 ahd_set_scbptr(ahd, scb_index); 9097 printf("%d ", scb_index); 9098 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE); 9099 } 9100 printf("\n"); 9101 ahd_set_scbptr(ahd, saved_scb_index); 9102 dffstat = ahd_inb(ahd, DFFSTAT); 9103 for (i = 0; i < 2; i++) { 9104 #ifdef AHD_DEBUG 9105 struct scb *fifo_scb; 9106 #endif 9107 u_int fifo_scbptr; 9108 9109 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i); 9110 fifo_scbptr = ahd_get_scbptr(ahd); 9111 printf("\n\n%s: FIFO%d %s, LONGJMP == 0x%x, SCB 0x%x\n", 9112 ahd_name(ahd), i, 9113 (dffstat & (FIFO0FREE << i)) ? "Free" : "Active", 9114 ahd_inw(ahd, LONGJMP_ADDR), fifo_scbptr); 9115 cur_col = 0; 9116 ahd_seqimode_print(ahd_inb(ahd, SEQIMODE), &cur_col, 50); 9117 ahd_seqintsrc_print(ahd_inb(ahd, SEQINTSRC), &cur_col, 50); 9118 ahd_dfcntrl_print(ahd_inb(ahd, DFCNTRL), &cur_col, 50); 9119 ahd_dfstatus_print(ahd_inb(ahd, DFSTATUS), &cur_col, 50); 9120 ahd_sg_cache_shadow_print(ahd_inb(ahd, SG_CACHE_SHADOW), 9121 &cur_col, 50); 9122 ahd_sg_state_print(ahd_inb(ahd, SG_STATE), &cur_col, 50); 9123 ahd_dffsxfrctl_print(ahd_inb(ahd, DFFSXFRCTL), &cur_col, 50); 9124 ahd_soffcnt_print(ahd_inb(ahd, SOFFCNT), &cur_col, 50); 9125 ahd_mdffstat_print(ahd_inb(ahd, MDFFSTAT), &cur_col, 50); 9126 if (cur_col > 50) { 9127 printf("\n"); 9128 cur_col = 0; 9129 } 9130 cur_col += printf("SHADDR = 0x%x%x, SHCNT = 0x%x ", 9131 ahd_inl(ahd, SHADDR+4), 9132 ahd_inl(ahd, SHADDR), 9133 (ahd_inb(ahd, SHCNT) 9134 | (ahd_inb(ahd, SHCNT + 1) << 8) 9135 | (ahd_inb(ahd, SHCNT + 2) << 16))); 9136 if (cur_col > 50) { 9137 printf("\n"); 9138 cur_col = 0; 9139 } 9140 cur_col += printf("HADDR = 0x%x%x, HCNT = 0x%x ", 9141 ahd_inl(ahd, HADDR+4), 9142 ahd_inl(ahd, HADDR), 9143 (ahd_inb(ahd, HCNT) 9144 | (ahd_inb(ahd, HCNT + 1) << 8) 9145 | (ahd_inb(ahd, HCNT + 2) << 16))); 9146 ahd_ccsgctl_print(ahd_inb(ahd, CCSGCTL), &cur_col, 50); 9147 #ifdef AHD_DEBUG 9148 if ((ahd_debug & AHD_SHOW_SG) != 0) { 9149 fifo_scb = ahd_lookup_scb(ahd, fifo_scbptr); 9150 if (fifo_scb != NULL) 9151 ahd_dump_sglist(fifo_scb); 9152 } 9153 #endif 9154 } 9155 printf("\nLQIN: "); 9156 for (i = 0; i < 20; i++) 9157 printf("0x%x ", ahd_inb(ahd, LQIN + i)); 9158 printf("\n"); 9159 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); 9160 printf("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n", 9161 ahd_name(ahd), ahd_inb(ahd, LQISTATE), ahd_inb(ahd, LQOSTATE), 9162 ahd_inb(ahd, OPTIONMODE)); 9163 printf("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n", 9164 ahd_name(ahd), ahd_inb(ahd, OS_SPACE_CNT), 9165 ahd_inb(ahd, MAXCMDCNT)); 9166 printf("%s: SAVED_SCSIID = 0x%x SAVED_LUN = 0x%x\n", 9167 ahd_name(ahd), ahd_inb(ahd, SAVED_SCSIID), 9168 ahd_inb(ahd, SAVED_LUN)); 9169 ahd_simode0_print(ahd_inb(ahd, SIMODE0), &cur_col, 50); 9170 printf("\n"); 9171 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN); 9172 cur_col = 0; 9173 ahd_ccscbctl_print(ahd_inb(ahd, CCSCBCTL), &cur_col, 50); 9174 printf("\n"); 9175 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode); 9176 printf("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n", 9177 ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX), 9178 ahd_inw(ahd, DINDEX)); 9179 printf("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n", 9180 ahd_name(ahd), ahd_get_scbptr(ahd), 9181 ahd_inw_scbram(ahd, SCB_NEXT), 9182 ahd_inw_scbram(ahd, SCB_NEXT2)); 9183 printf("CDB %x %x %x %x %x %x\n", 9184 ahd_inb_scbram(ahd, SCB_CDB_STORE), 9185 ahd_inb_scbram(ahd, SCB_CDB_STORE+1), 9186 ahd_inb_scbram(ahd, SCB_CDB_STORE+2), 9187 ahd_inb_scbram(ahd, SCB_CDB_STORE+3), 9188 ahd_inb_scbram(ahd, SCB_CDB_STORE+4), 9189 ahd_inb_scbram(ahd, SCB_CDB_STORE+5)); 9190 printf("STACK:"); 9191 for (i = 0; i < ahd->stack_size; i++) { 9192 ahd->saved_stack[i] = 9193 ahd_inb(ahd, STACK)|(ahd_inb(ahd, STACK) << 8); 9194 printf(" 0x%x", ahd->saved_stack[i]); 9195 } 9196 for (i = ahd->stack_size-1; i >= 0; i--) { 9197 ahd_outb(ahd, STACK, ahd->saved_stack[i] & 0xFF); 9198 ahd_outb(ahd, STACK, (ahd->saved_stack[i] >> 8) & 0xFF); 9199 } 9200 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 9201 ahd_platform_dump_card_state(ahd); 9202 ahd_restore_modes(ahd, saved_modes); 9203 if (paused == 0) 9204 ahd_unpause(ahd); 9205 } 9206 9207 void 9208 ahd_dump_scbs(struct ahd_softc *ahd) 9209 { 9210 ahd_mode_state saved_modes; 9211 u_int saved_scb_index; 9212 int i; 9213 9214 saved_modes = ahd_save_modes(ahd); 9215 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 9216 saved_scb_index = ahd_get_scbptr(ahd); 9217 for (i = 0; i < AHD_SCB_MAX; i++) { 9218 ahd_set_scbptr(ahd, i); 9219 printf("%3d", i); 9220 printf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n", 9221 ahd_inb_scbram(ahd, SCB_CONTROL), 9222 ahd_inb_scbram(ahd, SCB_SCSIID), 9223 ahd_inw_scbram(ahd, SCB_NEXT), 9224 ahd_inw_scbram(ahd, SCB_NEXT2), 9225 ahd_inl_scbram(ahd, SCB_SGPTR), 9226 ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR)); 9227 } 9228 printf("\n"); 9229 ahd_set_scbptr(ahd, saved_scb_index); 9230 ahd_restore_modes(ahd, saved_modes); 9231 } 9232 9233 /*************************** Timeout Handling *********************************/ 9234 void 9235 ahd_timeout(struct scb *scb) 9236 { 9237 struct ahd_softc *ahd; 9238 9239 ahd = scb->ahd_softc; 9240 if ((scb->flags & SCB_ACTIVE) != 0) { 9241 if ((scb->flags & SCB_TIMEDOUT) == 0) { 9242 LIST_INSERT_HEAD(&ahd->timedout_scbs, scb, 9243 timedout_links); 9244 scb->flags |= SCB_TIMEDOUT; 9245 } 9246 ahd_wakeup_recovery_thread(ahd); 9247 } 9248 } 9249 9250 /* 9251 * ahd_recover_commands determines if any of the commands that have currently 9252 * timedout are the root cause for this timeout. Innocent commands are given 9253 * a new timeout while we wait for the command executing on the bus to timeout. 9254 * This routine is invoked from a thread context so we are allowed to sleep. 9255 * Our lock is not held on entry. 9256 */ 9257 void 9258 ahd_recover_commands(struct ahd_softc *ahd) 9259 { 9260 struct scb *scb; 9261 struct scb *active_scb; 9262 int found; 9263 int was_paused; 9264 u_int active_scbptr; 9265 u_int last_phase; 9266 9267 /* 9268 * Pause the controller and manually flush any 9269 * commands that have just completed but that our 9270 * interrupt handler has yet to see. 9271 */ 9272 was_paused = ahd_is_paused(ahd); 9273 9274 printf("%s: Recovery Initiated - Card was %spaused\n", ahd_name(ahd), 9275 was_paused ? "" : "not "); 9276 AHD_CORRECTABLE_ERROR(ahd); 9277 ahd_dump_card_state(ahd); 9278 9279 ahd_pause_and_flushwork(ahd); 9280 9281 if (LIST_EMPTY(&ahd->timedout_scbs) != 0) { 9282 /* 9283 * The timedout commands have already 9284 * completed. This typically means 9285 * that either the timeout value was on 9286 * the hairy edge of what the device 9287 * requires or - more likely - interrupts 9288 * are not happening. 9289 */ 9290 printf("%s: Timedout SCBs already complete. " 9291 "Interrupts may not be functioning.\n", ahd_name(ahd)); 9292 ahd_unpause(ahd); 9293 return; 9294 } 9295 9296 /* 9297 * Determine identity of SCB acting on the bus. 9298 * This test only catches non-packetized transactions. 9299 * Due to the fleeting nature of packetized operations, 9300 * we can't easily determine that a packetized operation 9301 * is on the bus. 9302 */ 9303 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); 9304 last_phase = ahd_inb(ahd, LASTPHASE); 9305 active_scbptr = ahd_get_scbptr(ahd); 9306 active_scb = NULL; 9307 if (last_phase != P_BUSFREE 9308 || (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) == 0) 9309 active_scb = ahd_lookup_scb(ahd, active_scbptr); 9310 9311 while ((scb = LIST_FIRST(&ahd->timedout_scbs)) != NULL) { 9312 int target; 9313 int lun; 9314 char channel; 9315 9316 target = SCB_GET_TARGET(ahd, scb); 9317 channel = SCB_GET_CHANNEL(ahd, scb); 9318 lun = SCB_GET_LUN(scb); 9319 9320 ahd_print_path(ahd, scb); 9321 printf("SCB %d - timed out\n", SCB_GET_TAG(scb)); 9322 9323 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) { 9324 /* 9325 * Been down this road before. 9326 * Do a full bus reset. 9327 */ 9328 aic_set_transaction_status(scb, CAM_CMD_TIMEOUT); 9329 bus_reset: 9330 found = ahd_reset_channel(ahd, channel, 9331 /*Initiate Reset*/TRUE); 9332 printf("%s: Issued Channel %c Bus Reset. " 9333 "%d SCBs aborted\n", ahd_name(ahd), channel, 9334 found); 9335 continue; 9336 } 9337 9338 /* 9339 * Remove the command from the timedout list in 9340 * preparation for requeing it. 9341 */ 9342 LIST_REMOVE(scb, timedout_links); 9343 scb->flags &= ~SCB_TIMEDOUT; 9344 9345 if (active_scb != NULL) { 9346 if (active_scb != scb) { 9347 /* 9348 * If the active SCB is not us, assume that 9349 * the active SCB has a longer timeout than 9350 * the timedout SCB, and wait for the active 9351 * SCB to timeout. As a safeguard, only 9352 * allow this deferral to continue if some 9353 * untimed-out command is outstanding. 9354 */ 9355 if (ahd_other_scb_timeout(ahd, scb, 9356 active_scb) == 0) 9357 goto bus_reset; 9358 continue; 9359 } 9360 9361 /* 9362 * We're active on the bus, so assert ATN 9363 * and hope that the target responds. 9364 */ 9365 ahd_set_recoveryscb(ahd, active_scb); 9366 active_scb->flags |= SCB_RECOVERY_SCB|SCB_DEVICE_RESET; 9367 ahd_outb(ahd, MSG_OUT, HOST_MSG); 9368 ahd_outb(ahd, SCSISIGO, last_phase|ATNO); 9369 ahd_print_path(ahd, active_scb); 9370 printf("BDR message in message buffer\n"); 9371 aic_scb_timer_reset(scb, 2 * 1000); 9372 break; 9373 } else if (last_phase != P_BUSFREE 9374 && ahd_inb(ahd, SCSIPHASE) == 0) { 9375 /* 9376 * SCB is not identified, there 9377 * is no pending REQ, and the sequencer 9378 * has not seen a busfree. Looks like 9379 * a stuck connection waiting to 9380 * go busfree. Reset the bus. 9381 */ 9382 printf("%s: Connection stuck awaiting busfree or " 9383 "Identify Msg.\n", ahd_name(ahd)); 9384 goto bus_reset; 9385 } else if (ahd_search_qinfifo(ahd, target, channel, lun, 9386 SCB_GET_TAG(scb), 9387 ROLE_INITIATOR, /*status*/0, 9388 SEARCH_COUNT) > 0) { 9389 /* 9390 * We haven't even gone out on the bus 9391 * yet, so the timeout must be due to 9392 * some other command. Reset the timer 9393 * and go on. 9394 */ 9395 if (ahd_other_scb_timeout(ahd, scb, NULL) == 0) 9396 goto bus_reset; 9397 } else { 9398 /* 9399 * This SCB is for a disconnected transaction 9400 * and we haven't found a better candidate on 9401 * the bus to explain this timeout. 9402 */ 9403 ahd_set_recoveryscb(ahd, scb); 9404 9405 /* 9406 * Actually re-queue this SCB in an attempt 9407 * to select the device before it reconnects. 9408 * In either case (selection or reselection), 9409 * we will now issue a target reset to the 9410 * timed-out device. 9411 */ 9412 scb->flags |= SCB_DEVICE_RESET; 9413 scb->hscb->cdb_len = 0; 9414 scb->hscb->task_attribute = 0; 9415 scb->hscb->task_management = SIU_TASKMGMT_ABORT_TASK; 9416 9417 ahd_set_scbptr(ahd, SCB_GET_TAG(scb)); 9418 if ((scb->flags & SCB_PACKETIZED) != 0) { 9419 /* 9420 * Mark the SCB has having an outstanding 9421 * task management function. Should the command 9422 * complete normally before the task management 9423 * function can be sent, the host will be 9424 * notified to abort our requeued SCB. 9425 */ 9426 ahd_outb(ahd, SCB_TASK_MANAGEMENT, 9427 scb->hscb->task_management); 9428 } else { 9429 /* 9430 * If non-packetized, set the MK_MESSAGE control 9431 * bit indicating that we desire to send a 9432 * message. We also set the disconnected flag 9433 * since there is no guarantee that our SCB 9434 * control byte matches the version on the 9435 * card. We don't want the sequencer to abort 9436 * the command thinking an unsolicited 9437 * reselection occurred. 9438 */ 9439 scb->hscb->control |= MK_MESSAGE|DISCONNECTED; 9440 9441 /* 9442 * The sequencer will never re-reference the 9443 * in-core SCB. To make sure we are notified 9444 * during reselection, set the MK_MESSAGE flag in 9445 * the card's copy of the SCB. 9446 */ 9447 ahd_outb(ahd, SCB_CONTROL, 9448 ahd_inb(ahd, SCB_CONTROL)|MK_MESSAGE); 9449 } 9450 9451 /* 9452 * Clear out any entries in the QINFIFO first 9453 * so we are the next SCB for this target 9454 * to run. 9455 */ 9456 ahd_search_qinfifo(ahd, target, channel, lun, 9457 SCB_LIST_NULL, ROLE_INITIATOR, 9458 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 9459 ahd_qinfifo_requeue_tail(ahd, scb); 9460 ahd_set_scbptr(ahd, active_scbptr); 9461 ahd_print_path(ahd, scb); 9462 printf("Queuing a BDR SCB\n"); 9463 aic_scb_timer_reset(scb, 2 * 1000); 9464 break; 9465 } 9466 } 9467 9468 /* 9469 * Any remaining SCBs were not the "culprit", so remove 9470 * them from the timeout list. The timer for these commands 9471 * will be reset once the recovery SCB completes. 9472 */ 9473 while ((scb = LIST_FIRST(&ahd->timedout_scbs)) != NULL) { 9474 LIST_REMOVE(scb, timedout_links); 9475 scb->flags &= ~SCB_TIMEDOUT; 9476 } 9477 9478 ahd_unpause(ahd); 9479 } 9480 9481 /* 9482 * Re-schedule a timeout for the passed in SCB if we determine that some 9483 * other SCB is in the process of recovery or an SCB with a longer 9484 * timeout is still pending. Limit our search to just "other_scb" 9485 * if it is non-NULL. 9486 */ 9487 static int 9488 ahd_other_scb_timeout(struct ahd_softc *ahd, struct scb *scb, 9489 struct scb *other_scb) 9490 { 9491 u_int newtimeout; 9492 int found; 9493 9494 ahd_print_path(ahd, scb); 9495 printf("Other SCB Timeout%s", 9496 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0 9497 ? " again\n" : "\n"); 9498 9499 AHD_UNCORRECTABLE_ERROR(ahd); 9500 newtimeout = aic_get_timeout(scb); 9501 scb->flags |= SCB_OTHERTCL_TIMEOUT; 9502 found = 0; 9503 if (other_scb != NULL) { 9504 if ((other_scb->flags 9505 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0 9506 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) { 9507 found++; 9508 newtimeout = MAX(aic_get_timeout(other_scb), 9509 newtimeout); 9510 } 9511 } else { 9512 LIST_FOREACH(other_scb, &ahd->pending_scbs, pending_links) { 9513 if ((other_scb->flags 9514 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0 9515 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) { 9516 found++; 9517 newtimeout = MAX(aic_get_timeout(other_scb), 9518 newtimeout); 9519 } 9520 } 9521 } 9522 9523 if (found != 0) 9524 aic_scb_timer_reset(scb, newtimeout); 9525 else { 9526 ahd_print_path(ahd, scb); 9527 printf("No other SCB worth waiting for...\n"); 9528 } 9529 9530 return (found != 0); 9531 } 9532 9533 /**************************** Flexport Logic **********************************/ 9534 /* 9535 * Read count 16bit words from 16bit word address start_addr from the 9536 * SEEPROM attached to the controller, into buf, using the controller's 9537 * SEEPROM reading state machine. Optionally treat the data as a byte 9538 * stream in terms of byte order. 9539 */ 9540 int 9541 ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 9542 u_int start_addr, u_int count, int bytestream) 9543 { 9544 u_int cur_addr; 9545 u_int end_addr; 9546 int error; 9547 9548 /* 9549 * If we never make it through the loop even once, 9550 * we were passed invalid arguments. 9551 */ 9552 error = EINVAL; 9553 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 9554 end_addr = start_addr + count; 9555 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { 9556 ahd_outb(ahd, SEEADR, cur_addr); 9557 ahd_outb(ahd, SEECTL, SEEOP_READ | SEESTART); 9558 9559 error = ahd_wait_seeprom(ahd); 9560 if (error) 9561 break; 9562 if (bytestream != 0) { 9563 uint8_t *bytestream_ptr; 9564 9565 bytestream_ptr = (uint8_t *)buf; 9566 *bytestream_ptr++ = ahd_inb(ahd, SEEDAT); 9567 *bytestream_ptr = ahd_inb(ahd, SEEDAT+1); 9568 } else { 9569 /* 9570 * ahd_inw() already handles machine byte order. 9571 */ 9572 *buf = ahd_inw(ahd, SEEDAT); 9573 } 9574 buf++; 9575 } 9576 return (error); 9577 } 9578 9579 /* 9580 * Write count 16bit words from buf, into SEEPROM attache to the 9581 * controller starting at 16bit word address start_addr, using the 9582 * controller's SEEPROM writing state machine. 9583 */ 9584 int 9585 ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 9586 u_int start_addr, u_int count) 9587 { 9588 u_int cur_addr; 9589 u_int end_addr; 9590 int error; 9591 int retval; 9592 9593 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 9594 error = ENOENT; 9595 9596 /* Place the chip into write-enable mode */ 9597 ahd_outb(ahd, SEEADR, SEEOP_EWEN_ADDR); 9598 ahd_outb(ahd, SEECTL, SEEOP_EWEN | SEESTART); 9599 error = ahd_wait_seeprom(ahd); 9600 if (error) 9601 return (error); 9602 9603 /* 9604 * Write the data. If we don't get through the loop at 9605 * least once, the arguments were invalid. 9606 */ 9607 retval = EINVAL; 9608 end_addr = start_addr + count; 9609 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) { 9610 ahd_outw(ahd, SEEDAT, *buf++); 9611 ahd_outb(ahd, SEEADR, cur_addr); 9612 ahd_outb(ahd, SEECTL, SEEOP_WRITE | SEESTART); 9613 9614 retval = ahd_wait_seeprom(ahd); 9615 if (retval) 9616 break; 9617 } 9618 9619 /* 9620 * Disable writes. 9621 */ 9622 ahd_outb(ahd, SEEADR, SEEOP_EWDS_ADDR); 9623 ahd_outb(ahd, SEECTL, SEEOP_EWDS | SEESTART); 9624 error = ahd_wait_seeprom(ahd); 9625 if (error) 9626 return (error); 9627 return (retval); 9628 } 9629 9630 /* 9631 * Wait ~100us for the serial eeprom to satisfy our request. 9632 */ 9633 int 9634 ahd_wait_seeprom(struct ahd_softc *ahd) 9635 { 9636 int cnt; 9637 9638 cnt = 5000; 9639 while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt) 9640 aic_delay(5); 9641 9642 if (cnt == 0) 9643 return (ETIMEDOUT); 9644 return (0); 9645 } 9646 9647 /* 9648 * Validate the two checksums in the per_channel 9649 * vital product data struct. 9650 */ 9651 int 9652 ahd_verify_vpd_cksum(struct vpd_config *vpd) 9653 { 9654 int i; 9655 int maxaddr; 9656 uint32_t checksum; 9657 uint8_t *vpdarray; 9658 9659 vpdarray = (uint8_t *)vpd; 9660 maxaddr = offsetof(struct vpd_config, vpd_checksum); 9661 checksum = 0; 9662 for (i = offsetof(struct vpd_config, resource_type); i < maxaddr; i++) 9663 checksum = checksum + vpdarray[i]; 9664 if (checksum == 0 9665 || (-checksum & 0xFF) != vpd->vpd_checksum) 9666 return (0); 9667 9668 checksum = 0; 9669 maxaddr = offsetof(struct vpd_config, checksum); 9670 for (i = offsetof(struct vpd_config, default_target_flags); 9671 i < maxaddr; i++) 9672 checksum = checksum + vpdarray[i]; 9673 if (checksum == 0 9674 || (-checksum & 0xFF) != vpd->checksum) 9675 return (0); 9676 return (1); 9677 } 9678 9679 int 9680 ahd_verify_cksum(struct seeprom_config *sc) 9681 { 9682 int i; 9683 int maxaddr; 9684 uint32_t checksum; 9685 uint16_t *scarray; 9686 9687 maxaddr = (sizeof(*sc)/2) - 1; 9688 checksum = 0; 9689 scarray = (uint16_t *)sc; 9690 9691 for (i = 0; i < maxaddr; i++) 9692 checksum = checksum + scarray[i]; 9693 if (checksum == 0 9694 || (checksum & 0xFFFF) != sc->checksum) { 9695 return (0); 9696 } else { 9697 return (1); 9698 } 9699 } 9700 9701 int 9702 ahd_acquire_seeprom(struct ahd_softc *ahd) 9703 { 9704 /* 9705 * We should be able to determine the SEEPROM type 9706 * from the flexport logic, but unfortunately not 9707 * all implementations have this logic and there is 9708 * no programatic method for determining if the logic 9709 * is present. 9710 */ 9711 return (1); 9712 #if 0 9713 uint8_t seetype; 9714 int error; 9715 9716 error = ahd_read_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, &seetype); 9717 if (error != 0 9718 || ((seetype & FLX_ROMSTAT_SEECFG) == FLX_ROMSTAT_SEE_NONE)) 9719 return (0); 9720 return (1); 9721 #endif 9722 } 9723 9724 void 9725 ahd_release_seeprom(struct ahd_softc *ahd) 9726 { 9727 /* Currently a no-op */ 9728 } 9729 9730 int 9731 ahd_write_flexport(struct ahd_softc *ahd, u_int addr, u_int value) 9732 { 9733 int error; 9734 9735 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 9736 if (addr > 7) 9737 panic("ahd_write_flexport: address out of range"); 9738 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); 9739 error = ahd_wait_flexport(ahd); 9740 if (error != 0) 9741 return (error); 9742 ahd_outb(ahd, BRDDAT, value); 9743 ahd_flush_device_writes(ahd); 9744 ahd_outb(ahd, BRDCTL, BRDSTB|BRDEN|(addr << 3)); 9745 ahd_flush_device_writes(ahd); 9746 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3)); 9747 ahd_flush_device_writes(ahd); 9748 ahd_outb(ahd, BRDCTL, 0); 9749 ahd_flush_device_writes(ahd); 9750 return (0); 9751 } 9752 9753 int 9754 ahd_read_flexport(struct ahd_softc *ahd, u_int addr, uint8_t *value) 9755 { 9756 int error; 9757 9758 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 9759 if (addr > 7) 9760 panic("ahd_read_flexport: address out of range"); 9761 ahd_outb(ahd, BRDCTL, BRDRW|BRDEN|(addr << 3)); 9762 error = ahd_wait_flexport(ahd); 9763 if (error != 0) 9764 return (error); 9765 *value = ahd_inb(ahd, BRDDAT); 9766 ahd_outb(ahd, BRDCTL, 0); 9767 ahd_flush_device_writes(ahd); 9768 return (0); 9769 } 9770 9771 /* 9772 * Wait at most 2 seconds for flexport arbitration to succeed. 9773 */ 9774 int 9775 ahd_wait_flexport(struct ahd_softc *ahd) 9776 { 9777 int cnt; 9778 9779 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK); 9780 cnt = 1000000 * 2 / 5; 9781 while ((ahd_inb(ahd, BRDCTL) & FLXARBACK) == 0 && --cnt) 9782 aic_delay(5); 9783 9784 if (cnt == 0) 9785 return (ETIMEDOUT); 9786 return (0); 9787 } 9788 9789 /************************* Target Mode ****************************************/ 9790 #ifdef AHD_TARGET_MODE 9791 cam_status 9792 ahd_find_tmode_devs(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb, 9793 struct ahd_tmode_tstate **tstate, 9794 struct ahd_tmode_lstate **lstate, 9795 int notfound_failure) 9796 { 9797 9798 if ((ahd->features & AHD_TARGETMODE) == 0) 9799 return (CAM_REQ_INVALID); 9800 9801 /* 9802 * Handle the 'black hole' device that sucks up 9803 * requests to unattached luns on enabled targets. 9804 */ 9805 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 9806 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 9807 *tstate = NULL; 9808 *lstate = ahd->black_hole; 9809 } else { 9810 u_int max_id; 9811 9812 max_id = (ahd->features & AHD_WIDE) ? 15 : 7; 9813 if (ccb->ccb_h.target_id > max_id) 9814 return (CAM_TID_INVALID); 9815 9816 if (ccb->ccb_h.target_lun >= AHD_NUM_LUNS) 9817 return (CAM_LUN_INVALID); 9818 9819 *tstate = ahd->enabled_targets[ccb->ccb_h.target_id]; 9820 *lstate = NULL; 9821 if (*tstate != NULL) 9822 *lstate = 9823 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 9824 } 9825 9826 if (notfound_failure != 0 && *lstate == NULL) 9827 return (CAM_PATH_INVALID); 9828 9829 return (CAM_REQ_CMP); 9830 } 9831 9832 void 9833 ahd_handle_en_lun(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb) 9834 { 9835 #if NOT_YET 9836 struct ahd_tmode_tstate *tstate; 9837 struct ahd_tmode_lstate *lstate; 9838 struct ccb_en_lun *cel; 9839 cam_status status; 9840 u_int target; 9841 u_int lun; 9842 u_int target_mask; 9843 u_long s; 9844 char channel; 9845 9846 status = ahd_find_tmode_devs(ahd, sim, ccb, &tstate, &lstate, 9847 /*notfound_failure*/FALSE); 9848 9849 if (status != CAM_REQ_CMP) { 9850 ccb->ccb_h.status = status; 9851 return; 9852 } 9853 9854 if ((ahd->features & AHD_MULTIROLE) != 0) { 9855 u_int our_id; 9856 9857 our_id = ahd->our_id; 9858 if (ccb->ccb_h.target_id != our_id 9859 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 9860 if ((ahd->features & AHD_MULTI_TID) != 0 9861 && (ahd->flags & AHD_INITIATORROLE) != 0) { 9862 /* 9863 * Only allow additional targets if 9864 * the initiator role is disabled. 9865 * The hardware cannot handle a re-select-in 9866 * on the initiator id during a re-select-out 9867 * on a different target id. 9868 */ 9869 status = CAM_TID_INVALID; 9870 } else if ((ahd->flags & AHD_INITIATORROLE) != 0 9871 || ahd->enabled_luns > 0) { 9872 /* 9873 * Only allow our target id to change 9874 * if the initiator role is not configured 9875 * and there are no enabled luns which 9876 * are attached to the currently registered 9877 * scsi id. 9878 */ 9879 status = CAM_TID_INVALID; 9880 } 9881 } 9882 } 9883 9884 if (status != CAM_REQ_CMP) { 9885 ccb->ccb_h.status = status; 9886 return; 9887 } 9888 9889 /* 9890 * We now have an id that is valid. 9891 * If we aren't in target mode, switch modes. 9892 */ 9893 if ((ahd->flags & AHD_TARGETROLE) == 0 9894 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 9895 printf("Configuring Target Mode\n"); 9896 if (LIST_FIRST(&ahd->pending_scbs) != NULL) { 9897 ccb->ccb_h.status = CAM_BUSY; 9898 return; 9899 } 9900 ahd->flags |= AHD_TARGETROLE; 9901 if ((ahd->features & AHD_MULTIROLE) == 0) 9902 ahd->flags &= ~AHD_INITIATORROLE; 9903 ahd_pause(ahd); 9904 ahd_loadseq(ahd); 9905 ahd_restart(ahd); 9906 } 9907 cel = &ccb->cel; 9908 target = ccb->ccb_h.target_id; 9909 lun = ccb->ccb_h.target_lun; 9910 channel = SIM_CHANNEL(ahd, sim); 9911 target_mask = 0x01 << target; 9912 if (channel == 'B') 9913 target_mask <<= 8; 9914 9915 if (cel->enable != 0) { 9916 u_int scsiseq1; 9917 9918 /* Are we already enabled?? */ 9919 if (lstate != NULL) { 9920 xpt_print_path(ccb->ccb_h.path); 9921 printf("Lun already enabled\n"); 9922 AHD_CORRECTABLE_ERROR(ahd); 9923 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 9924 return; 9925 } 9926 9927 if (cel->grp6_len != 0 9928 || cel->grp7_len != 0) { 9929 /* 9930 * Don't (yet?) support vendor 9931 * specific commands. 9932 */ 9933 ccb->ccb_h.status = CAM_REQ_INVALID; 9934 printf("Non-zero Group Codes\n"); 9935 return; 9936 } 9937 9938 /* 9939 * Seems to be okay. 9940 * Setup our data structures. 9941 */ 9942 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 9943 tstate = ahd_alloc_tstate(ahd, target, channel); 9944 if (tstate == NULL) { 9945 xpt_print_path(ccb->ccb_h.path); 9946 printf("Couldn't allocate tstate\n"); 9947 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9948 return; 9949 } 9950 } 9951 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 9952 if (lstate == NULL) { 9953 xpt_print_path(ccb->ccb_h.path); 9954 printf("Couldn't allocate lstate\n"); 9955 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9956 return; 9957 } 9958 memset(lstate, 0, sizeof(*lstate)); 9959 status = xpt_create_path(&lstate->path, /*periph*/NULL, 9960 xpt_path_path_id(ccb->ccb_h.path), 9961 xpt_path_target_id(ccb->ccb_h.path), 9962 xpt_path_lun_id(ccb->ccb_h.path)); 9963 if (status != CAM_REQ_CMP) { 9964 free(lstate, M_DEVBUF); 9965 xpt_print_path(ccb->ccb_h.path); 9966 printf("Couldn't allocate path\n"); 9967 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 9968 return; 9969 } 9970 SLIST_INIT(&lstate->accept_tios); 9971 SLIST_INIT(&lstate->immed_notifies); 9972 ahd_pause(ahd); 9973 if (target != CAM_TARGET_WILDCARD) { 9974 tstate->enabled_luns[lun] = lstate; 9975 ahd->enabled_luns++; 9976 9977 if ((ahd->features & AHD_MULTI_TID) != 0) { 9978 u_int targid_mask; 9979 9980 targid_mask = ahd_inw(ahd, TARGID); 9981 targid_mask |= target_mask; 9982 ahd_outw(ahd, TARGID, targid_mask); 9983 ahd_update_scsiid(ahd, targid_mask); 9984 } else { 9985 u_int our_id; 9986 char channel; 9987 9988 channel = SIM_CHANNEL(ahd, sim); 9989 our_id = SIM_SCSI_ID(ahd, sim); 9990 9991 /* 9992 * This can only happen if selections 9993 * are not enabled 9994 */ 9995 if (target != our_id) { 9996 u_int sblkctl; 9997 char cur_channel; 9998 int swap; 9999 10000 sblkctl = ahd_inb(ahd, SBLKCTL); 10001 cur_channel = (sblkctl & SELBUSB) 10002 ? 'B' : 'A'; 10003 if ((ahd->features & AHD_TWIN) == 0) 10004 cur_channel = 'A'; 10005 swap = cur_channel != channel; 10006 ahd->our_id = target; 10007 10008 if (swap) 10009 ahd_outb(ahd, SBLKCTL, 10010 sblkctl ^ SELBUSB); 10011 10012 ahd_outb(ahd, SCSIID, target); 10013 10014 if (swap) 10015 ahd_outb(ahd, SBLKCTL, sblkctl); 10016 } 10017 } 10018 } else 10019 ahd->black_hole = lstate; 10020 /* Allow select-in operations */ 10021 if (ahd->black_hole != NULL && ahd->enabled_luns > 0) { 10022 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 10023 scsiseq1 |= ENSELI; 10024 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); 10025 scsiseq1 = ahd_inb(ahd, SCSISEQ1); 10026 scsiseq1 |= ENSELI; 10027 ahd_outb(ahd, SCSISEQ1, scsiseq1); 10028 } 10029 ahd_unpause(ahd); 10030 ccb->ccb_h.status = CAM_REQ_CMP; 10031 xpt_print_path(ccb->ccb_h.path); 10032 printf("Lun now enabled for target mode\n"); 10033 } else { 10034 struct scb *scb; 10035 int i, empty; 10036 10037 if (lstate == NULL) { 10038 ccb->ccb_h.status = CAM_LUN_INVALID; 10039 return; 10040 } 10041 10042 ccb->ccb_h.status = CAM_REQ_CMP; 10043 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) { 10044 struct ccb_hdr *ccbh; 10045 10046 ccbh = &scb->io_ctx->ccb_h; 10047 if (ccbh->func_code == XPT_CONT_TARGET_IO 10048 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 10049 printf("CTIO pending\n"); 10050 ccb->ccb_h.status = CAM_REQ_INVALID; 10051 return; 10052 } 10053 } 10054 10055 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 10056 printf("ATIOs pending\n"); 10057 ccb->ccb_h.status = CAM_REQ_INVALID; 10058 } 10059 10060 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 10061 printf("INOTs pending\n"); 10062 ccb->ccb_h.status = CAM_REQ_INVALID; 10063 } 10064 10065 if (ccb->ccb_h.status != CAM_REQ_CMP) { 10066 return; 10067 } 10068 10069 xpt_print_path(ccb->ccb_h.path); 10070 printf("Target mode disabled\n"); 10071 xpt_free_path(lstate->path); 10072 free(lstate, M_DEVBUF); 10073 10074 ahd_pause(ahd); 10075 /* Can we clean up the target too? */ 10076 if (target != CAM_TARGET_WILDCARD) { 10077 tstate->enabled_luns[lun] = NULL; 10078 ahd->enabled_luns--; 10079 for (empty = 1, i = 0; i < 8; i++) 10080 if (tstate->enabled_luns[i] != NULL) { 10081 empty = 0; 10082 break; 10083 } 10084 10085 if (empty) { 10086 ahd_free_tstate(ahd, target, channel, 10087 /*force*/FALSE); 10088 if (ahd->features & AHD_MULTI_TID) { 10089 u_int targid_mask; 10090 10091 targid_mask = ahd_inw(ahd, TARGID); 10092 targid_mask &= ~target_mask; 10093 ahd_outw(ahd, TARGID, targid_mask); 10094 ahd_update_scsiid(ahd, targid_mask); 10095 } 10096 } 10097 } else { 10098 ahd->black_hole = NULL; 10099 10100 /* 10101 * We can't allow selections without 10102 * our black hole device. 10103 */ 10104 empty = TRUE; 10105 } 10106 if (ahd->enabled_luns == 0) { 10107 /* Disallow select-in */ 10108 u_int scsiseq1; 10109 10110 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE); 10111 scsiseq1 &= ~ENSELI; 10112 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1); 10113 scsiseq1 = ahd_inb(ahd, SCSISEQ1); 10114 scsiseq1 &= ~ENSELI; 10115 ahd_outb(ahd, SCSISEQ1, scsiseq1); 10116 10117 if ((ahd->features & AHD_MULTIROLE) == 0) { 10118 printf("Configuring Initiator Mode\n"); 10119 ahd->flags &= ~AHD_TARGETROLE; 10120 ahd->flags |= AHD_INITIATORROLE; 10121 ahd_pause(ahd); 10122 ahd_loadseq(ahd); 10123 ahd_restart(ahd); 10124 /* 10125 * Unpaused. The extra unpause 10126 * that follows is harmless. 10127 */ 10128 } 10129 } 10130 ahd_unpause(ahd); 10131 } 10132 #endif 10133 } 10134 10135 static void 10136 ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask) 10137 { 10138 #if NOT_YET 10139 u_int scsiid_mask; 10140 u_int scsiid; 10141 10142 if ((ahd->features & AHD_MULTI_TID) == 0) 10143 panic("ahd_update_scsiid called on non-multitid unit\n"); 10144 10145 /* 10146 * Since we will rely on the TARGID mask 10147 * for selection enables, ensure that OID 10148 * in SCSIID is not set to some other ID 10149 * that we don't want to allow selections on. 10150 */ 10151 if ((ahd->features & AHD_ULTRA2) != 0) 10152 scsiid = ahd_inb(ahd, SCSIID_ULTRA2); 10153 else 10154 scsiid = ahd_inb(ahd, SCSIID); 10155 scsiid_mask = 0x1 << (scsiid & OID); 10156 if ((targid_mask & scsiid_mask) == 0) { 10157 u_int our_id; 10158 10159 /* ffs counts from 1 */ 10160 our_id = ffs(targid_mask); 10161 if (our_id == 0) 10162 our_id = ahd->our_id; 10163 else 10164 our_id--; 10165 scsiid &= TID; 10166 scsiid |= our_id; 10167 } 10168 if ((ahd->features & AHD_ULTRA2) != 0) 10169 ahd_outb(ahd, SCSIID_ULTRA2, scsiid); 10170 else 10171 ahd_outb(ahd, SCSIID, scsiid); 10172 #endif 10173 } 10174 10175 void 10176 ahd_run_tqinfifo(struct ahd_softc *ahd, int paused) 10177 { 10178 struct target_cmd *cmd; 10179 10180 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_POSTREAD); 10181 while ((cmd = &ahd->targetcmds[ahd->tqinfifonext])->cmd_valid != 0) { 10182 /* 10183 * Only advance through the queue if we 10184 * have the resources to process the command. 10185 */ 10186 if (ahd_handle_target_cmd(ahd, cmd) != 0) 10187 break; 10188 10189 cmd->cmd_valid = 0; 10190 ahd_dmamap_sync(ahd, ahd->shared_data_dmat, 10191 ahd->shared_data_dmamap, 10192 ahd_targetcmd_offset(ahd, ahd->tqinfifonext), 10193 sizeof(struct target_cmd), 10194 BUS_DMASYNC_PREREAD); 10195 ahd->tqinfifonext++; 10196 10197 /* 10198 * Lazily update our position in the target mode incoming 10199 * command queue as seen by the sequencer. 10200 */ 10201 if ((ahd->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 10202 u_int hs_mailbox; 10203 10204 hs_mailbox = ahd_inb(ahd, HS_MAILBOX); 10205 hs_mailbox &= ~HOST_TQINPOS; 10206 hs_mailbox |= ahd->tqinfifonext & HOST_TQINPOS; 10207 ahd_outb(ahd, HS_MAILBOX, hs_mailbox); 10208 } 10209 } 10210 } 10211 10212 static int 10213 ahd_handle_target_cmd(struct ahd_softc *ahd, struct target_cmd *cmd) 10214 { 10215 struct ahd_tmode_tstate *tstate; 10216 struct ahd_tmode_lstate *lstate; 10217 struct ccb_accept_tio *atio; 10218 uint8_t *byte; 10219 int initiator; 10220 int target; 10221 int lun; 10222 10223 initiator = SCSIID_TARGET(ahd, cmd->scsiid); 10224 target = SCSIID_OUR_ID(cmd->scsiid); 10225 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 10226 10227 byte = cmd->bytes; 10228 tstate = ahd->enabled_targets[target]; 10229 lstate = NULL; 10230 if (tstate != NULL) 10231 lstate = tstate->enabled_luns[lun]; 10232 10233 /* 10234 * Commands for disabled luns go to the black hole driver. 10235 */ 10236 if (lstate == NULL) 10237 lstate = ahd->black_hole; 10238 10239 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 10240 if (atio == NULL) { 10241 ahd->flags |= AHD_TQINFIFO_BLOCKED; 10242 /* 10243 * Wait for more ATIOs from the peripheral driver for this lun. 10244 */ 10245 return (1); 10246 } else 10247 ahd->flags &= ~AHD_TQINFIFO_BLOCKED; 10248 #ifdef AHD_DEBUG 10249 if ((ahd_debug & AHD_SHOW_TQIN) != 0) 10250 printf("Incoming command from %d for %d:%d%s\n", 10251 initiator, target, lun, 10252 lstate == ahd->black_hole ? "(Black Holed)" : ""); 10253 #endif 10254 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 10255 10256 if (lstate == ahd->black_hole) { 10257 /* Fill in the wildcards */ 10258 atio->ccb_h.target_id = target; 10259 atio->ccb_h.target_lun = lun; 10260 } 10261 10262 /* 10263 * Package it up and send it off to 10264 * whomever has this lun enabled. 10265 */ 10266 atio->sense_len = 0; 10267 atio->init_id = initiator; 10268 if (byte[0] != 0xFF) { 10269 /* Tag was included */ 10270 atio->tag_action = *byte++; 10271 atio->tag_id = *byte++; 10272 atio->ccb_h.flags |= CAM_TAG_ACTION_VALID; 10273 } else { 10274 atio->ccb_h.flags &= ~CAM_TAG_ACTION_VALID; 10275 } 10276 byte++; 10277 10278 /* Okay. Now determine the cdb size based on the command code */ 10279 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 10280 case 0: 10281 atio->cdb_len = 6; 10282 break; 10283 case 1: 10284 case 2: 10285 atio->cdb_len = 10; 10286 break; 10287 case 4: 10288 atio->cdb_len = 16; 10289 break; 10290 case 5: 10291 atio->cdb_len = 12; 10292 break; 10293 case 3: 10294 default: 10295 /* Only copy the opcode. */ 10296 atio->cdb_len = 1; 10297 printf("Reserved or VU command code type encountered\n"); 10298 break; 10299 } 10300 10301 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 10302 10303 atio->ccb_h.status |= CAM_CDB_RECVD; 10304 10305 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 10306 /* 10307 * We weren't allowed to disconnect. 10308 * We're hanging on the bus until a 10309 * continue target I/O comes in response 10310 * to this accept tio. 10311 */ 10312 #ifdef AHD_DEBUG 10313 if ((ahd_debug & AHD_SHOW_TQIN) != 0) 10314 printf("Received Immediate Command %d:%d:%d - %p\n", 10315 initiator, target, lun, ahd->pending_device); 10316 #endif 10317 ahd->pending_device = lstate; 10318 ahd_freeze_ccb((union ccb *)atio); 10319 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 10320 } 10321 xpt_done((union ccb*)atio); 10322 return (0); 10323 } 10324 10325 #endif 10326