1 /* 2 * FreeBSD, PCI product support functions 3 * 4 * Copyright (c) 1995-2001 Justin T. Gibbs 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * Alternatively, this software may be distributed under the terms of the 17 * GNU Public License ("GPL"). 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $Id: ahd_pci.c,v 1.8 2003/05/03 23:27:57 gibbs Exp $ 32 * 33 * $FreeBSD$ 34 */ 35 36 #include <dev/aic7xxx/aic79xx_osm.h> 37 38 #define AHD_PCI_IOADDR0 PCIR_MAPS /* Primary I/O BAR */ 39 #define AHD_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 40 #define AHD_PCI_IOADDR1 (PCIR_MAPS + 12)/* Secondary I/O BAR */ 41 42 static int ahd_pci_probe(device_t dev); 43 static int ahd_pci_attach(device_t dev); 44 45 static device_method_t ahd_pci_device_methods[] = { 46 /* Device interface */ 47 DEVMETHOD(device_probe, ahd_pci_probe), 48 DEVMETHOD(device_attach, ahd_pci_attach), 49 DEVMETHOD(device_detach, ahd_detach), 50 { 0, 0 } 51 }; 52 53 static driver_t ahd_pci_driver = { 54 "ahd", 55 ahd_pci_device_methods, 56 sizeof(struct ahd_softc) 57 }; 58 59 static devclass_t ahd_devclass; 60 61 DRIVER_MODULE(ahd, pci, ahd_pci_driver, ahd_devclass, 0, 0); 62 DRIVER_MODULE(ahd, cardbus, ahd_pci_driver, ahd_devclass, 0, 0); 63 MODULE_DEPEND(ahd_pci, ahd, 1, 1, 1); 64 MODULE_VERSION(ahd_pci, 1); 65 66 static int 67 ahd_pci_probe(device_t dev) 68 { 69 struct ahd_pci_identity *entry; 70 71 entry = ahd_find_pci_device(dev); 72 if (entry != NULL) { 73 device_set_desc(dev, entry->name); 74 return (0); 75 } 76 return (ENXIO); 77 } 78 79 static int 80 ahd_pci_attach(device_t dev) 81 { 82 struct ahd_pci_identity *entry; 83 struct ahd_softc *ahd; 84 char *name; 85 int error; 86 87 entry = ahd_find_pci_device(dev); 88 if (entry == NULL) 89 return (ENXIO); 90 91 /* 92 * Allocate a softc for this card and 93 * set it up for attachment by our 94 * common detect routine. 95 */ 96 name = malloc(strlen(device_get_nameunit(dev)) + 1, M_DEVBUF, M_NOWAIT); 97 if (name == NULL) 98 return (ENOMEM); 99 strcpy(name, device_get_nameunit(dev)); 100 ahd = ahd_alloc(dev, name); 101 if (ahd == NULL) 102 return (ENOMEM); 103 104 ahd_set_unit(ahd, device_get_unit(dev)); 105 106 /* 107 * Should we bother disabling 39Bit addressing 108 * based on installed memory? 109 */ 110 if (sizeof(bus_addr_t) > 4) 111 ahd->flags |= AHD_39BIT_ADDRESSING; 112 113 /* Allocate a dmatag for our SCB DMA maps */ 114 /* XXX Should be a child of the PCI bus dma tag */ 115 error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1, 116 /*boundary*/0, 117 (ahd->flags & AHD_39BIT_ADDRESSING) 118 ? 0x7FFFFFFFFF 119 : BUS_SPACE_MAXADDR_32BIT, 120 /*highaddr*/BUS_SPACE_MAXADDR, 121 /*filter*/NULL, /*filterarg*/NULL, 122 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT, 123 /*nsegments*/AHD_NSEG, 124 /*maxsegsz*/AHD_MAXTRANSFER_SIZE, 125 /*flags*/0, 126 /*lockfunc*/busdma_lock_mutex, 127 /*lockarg*/&Giant, 128 &ahd->parent_dmat); 129 130 if (error != 0) { 131 printf("ahd_pci_attach: Could not allocate DMA tag " 132 "- error %d\n", error); 133 ahd_free(ahd); 134 return (ENOMEM); 135 } 136 ahd->dev_softc = dev; 137 error = ahd_pci_config(ahd, entry); 138 if (error != 0) { 139 ahd_free(ahd); 140 return (error); 141 } 142 143 ahd_attach(ahd); 144 return (0); 145 } 146 147 int 148 ahd_pci_map_registers(struct ahd_softc *ahd) 149 { 150 struct resource *regs; 151 struct resource *regs2; 152 u_int command; 153 int regs_type; 154 int regs_id; 155 int regs_id2; 156 int allow_memio; 157 158 command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/1); 159 regs = NULL; 160 regs2 = NULL; 161 regs_type = 0; 162 regs_id = 0; 163 164 /* Retrieve the per-device 'allow_memio' hint */ 165 if (resource_int_value(device_get_name(ahd->dev_softc), 166 device_get_unit(ahd->dev_softc), 167 "allow_memio", &allow_memio) != 0) { 168 if (bootverbose) 169 device_printf(ahd->dev_softc, 170 "Defaulting to MEMIO on\n"); 171 } 172 173 if ((command & PCIM_CMD_MEMEN) != 0 174 && (ahd->bugs & AHD_PCIX_MMAPIO_BUG) == 0 175 && allow_memio != 0) { 176 177 regs_type = SYS_RES_MEMORY; 178 regs_id = AHD_PCI_MEMADDR; 179 regs = bus_alloc_resource(ahd->dev_softc, regs_type, 180 ®s_id, 0, ~0, 1, RF_ACTIVE); 181 if (regs != NULL) { 182 int error; 183 184 ahd->tags[0] = rman_get_bustag(regs); 185 ahd->bshs[0] = rman_get_bushandle(regs); 186 ahd->tags[1] = ahd->tags[0]; 187 error = bus_space_subregion(ahd->tags[0], ahd->bshs[0], 188 /*offset*/0x100, 189 /*size*/0x100, 190 &ahd->bshs[1]); 191 /* 192 * Do a quick test to see if memory mapped 193 * I/O is functioning correctly. 194 */ 195 if (error != 0 196 || ahd_pci_test_register_access(ahd) != 0) { 197 device_printf(ahd->dev_softc, 198 "PCI Device %d:%d:%d failed memory " 199 "mapped test. Using PIO.\n", 200 ahd_get_pci_bus(ahd->dev_softc), 201 ahd_get_pci_slot(ahd->dev_softc), 202 ahd_get_pci_function(ahd->dev_softc)); 203 bus_release_resource(ahd->dev_softc, regs_type, 204 regs_id, regs); 205 regs = NULL; 206 } else { 207 command &= ~PCIM_CMD_PORTEN; 208 ahd_pci_write_config(ahd->dev_softc, 209 PCIR_COMMAND, 210 command, /*bytes*/1); 211 } 212 } 213 } 214 if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) { 215 regs_type = SYS_RES_IOPORT; 216 regs_id = AHD_PCI_IOADDR0; 217 regs = bus_alloc_resource(ahd->dev_softc, regs_type, 218 ®s_id, 0, ~0, 1, RF_ACTIVE); 219 if (regs == NULL) { 220 device_printf(ahd->dev_softc, 221 "can't allocate register resources\n"); 222 return (ENOMEM); 223 } 224 ahd->tags[0] = rman_get_bustag(regs); 225 ahd->bshs[0] = rman_get_bushandle(regs); 226 227 /* And now the second BAR */ 228 regs_id2 = AHD_PCI_IOADDR1; 229 regs2 = bus_alloc_resource(ahd->dev_softc, regs_type, 230 ®s_id2, 0, ~0, 1, RF_ACTIVE); 231 if (regs2 == NULL) { 232 device_printf(ahd->dev_softc, 233 "can't allocate register resources\n"); 234 return (ENOMEM); 235 } 236 ahd->tags[1] = rman_get_bustag(regs2); 237 ahd->bshs[1] = rman_get_bushandle(regs2); 238 command &= ~PCIM_CMD_MEMEN; 239 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, 240 command, /*bytes*/1); 241 ahd->platform_data->regs_res_type[1] = regs_type; 242 ahd->platform_data->regs_res_id[1] = regs_id2; 243 ahd->platform_data->regs[1] = regs2; 244 } 245 ahd->platform_data->regs_res_type[0] = regs_type; 246 ahd->platform_data->regs_res_id[0] = regs_id; 247 ahd->platform_data->regs[0] = regs; 248 return (0); 249 } 250 251 int 252 ahd_pci_map_int(struct ahd_softc *ahd) 253 { 254 int zero; 255 256 zero = 0; 257 ahd->platform_data->irq = 258 bus_alloc_resource(ahd->dev_softc, SYS_RES_IRQ, &zero, 259 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 260 if (ahd->platform_data->irq == NULL) 261 return (ENOMEM); 262 ahd->platform_data->irq_res_type = SYS_RES_IRQ; 263 return (ahd_map_int(ahd)); 264 } 265 266 void 267 ahd_power_state_change(struct ahd_softc *ahd, ahd_power_state new_state) 268 { 269 uint32_t cap; 270 u_int cap_offset; 271 272 /* 273 * Traverse the capability list looking for 274 * the power management capability. 275 */ 276 cap = 0; 277 cap_offset = ahd_pci_read_config(ahd->dev_softc, 278 PCIR_CAP_PTR, /*bytes*/1); 279 while (cap_offset != 0) { 280 281 cap = ahd_pci_read_config(ahd->dev_softc, 282 cap_offset, /*bytes*/4); 283 if ((cap & 0xFF) == 1 284 && ((cap >> 16) & 0x3) > 0) { 285 uint32_t pm_control; 286 287 pm_control = ahd_pci_read_config(ahd->dev_softc, 288 cap_offset + 4, 289 /*bytes*/2); 290 pm_control &= ~0x3; 291 pm_control |= new_state; 292 ahd_pci_write_config(ahd->dev_softc, 293 cap_offset + 4, 294 pm_control, /*bytes*/2); 295 break; 296 } 297 cap_offset = (cap >> 8) & 0xFF; 298 } 299 } 300