1 /* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Where this Software is combined with software released under the terms of 19 * the GNU Public License ("GPL") and the terms of the GPL would require the 20 * combined work to also be released under the terms of the GPL, the terms 21 * and conditions of this License will apply in addition to those of the 22 * GPL with the exception of any terms or conditions of this License that 23 * conflict with, or are expressly prohibited by, the GPL. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $FreeBSD$ 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/bus.h> 45 46 #include <pci/pcireg.h> 47 #include <pci/pcivar.h> 48 49 #include <machine/bus_memio.h> 50 #include <machine/bus_pio.h> 51 #include <machine/bus.h> 52 #include <machine/resource.h> 53 #include <machine/clock.h> 54 #include <sys/rman.h> 55 56 #include <cam/cam.h> 57 #include <cam/cam_ccb.h> 58 #include <cam/cam_sim.h> 59 #include <cam/cam_xpt_sim.h> 60 61 #include <cam/scsi/scsi_all.h> 62 63 #include <dev/aic7xxx/aic7xxx.h> 64 #include <dev/aic7xxx/93cx6.h> 65 66 #include <aic7xxx_reg.h> 67 68 #define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ 69 #define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 70 71 static __inline u_int64_t 72 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 73 { 74 u_int64_t id; 75 76 id = subvendor 77 | (subdevice << 16) 78 | ((u_int64_t)vendor << 32) 79 | ((u_int64_t)device << 48); 80 81 return (id); 82 } 83 84 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 85 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 86 #define ID_AIC7850 0x5078900400000000ull 87 #define ID_AHA_2910_15_20_30C 0x5078900478509004ull 88 #define ID_AIC7855 0x5578900400000000ull 89 #define ID_AIC7859 0x3860900400000000ull 90 #define ID_AHA_2930CU 0x3860900438699004ull 91 #define ID_AIC7860 0x6078900400000000ull 92 #define ID_AIC7860C 0x6078900478609004ull 93 #define ID_AHA_2940AU_0 0x6178900400000000ull 94 #define ID_AHA_2940AU_1 0x6178900478619004ull 95 #define ID_AHA_2940AU_CN 0x2178900478219004ull 96 #define ID_AHA_2930C_VAR 0x6038900438689004ull 97 98 #define ID_AIC7870 0x7078900400000000ull 99 #define ID_AHA_2940 0x7178900400000000ull 100 #define ID_AHA_3940 0x7278900400000000ull 101 #define ID_AHA_398X 0x7378900400000000ull 102 #define ID_AHA_2944 0x7478900400000000ull 103 #define ID_AHA_3944 0x7578900400000000ull 104 105 #define ID_AIC7880 0x8078900400000000ull 106 #define ID_AIC7880_B 0x8078900478809004ull 107 #define ID_AHA_2940U 0x8178900400000000ull 108 #define ID_AHA_3940U 0x8278900400000000ull 109 #define ID_AHA_2944U 0x8478900400000000ull 110 #define ID_AHA_3944U 0x8578900400000000ull 111 #define ID_AHA_398XU 0x8378900400000000ull 112 #define ID_AHA_4944U 0x8678900400000000ull 113 #define ID_AHA_2940UB 0x8178900478819004ull 114 #define ID_AHA_2930U 0x8878900478889004ull 115 #define ID_AHA_2940U_PRO 0x8778900478879004ull 116 #define ID_AHA_2940U_CN 0x0078900478009004ull 117 118 #define ID_AIC7895 0x7895900478959004ull 119 #define ID_AIC7895_RAID_PORT 0x7893900478939004ull 120 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 121 #define ID_AHA_3940AU 0x7895900478929004ull 122 #define ID_AHA_3944AU 0x7895900478949004ull 123 124 #define ID_AIC7890 0x001F9005000F9005ull 125 #define ID_AHA_2930U2 0x0011900501819005ull 126 #define ID_AHA_2940U2B 0x00109005A1009005ull 127 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 128 #define ID_AHA_2940U2 0x00109005A1809005ull 129 #define ID_AHA_2950U2B 0x00109005E1009005ull 130 131 #define ID_AIC7892 0x008F9005FFFF9005ull 132 #define ID_AHA_29160 0x00809005E2A09005ull 133 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull 134 #define ID_AHA_29160N 0x0080900562A09005ull 135 #define ID_AHA_29160B 0x00809005E2209005ull 136 #define ID_AHA_19160B 0x0081900562A19005ull 137 138 #define ID_AIC7896 0x005F9005FFFF9005ull 139 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 140 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 141 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 142 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 143 144 #define ID_AIC7899 0x00CF9005FFFF9005ull 145 #define ID_AHA_3960D 0x00C09005F6209005ull /* AKA AHA-39160 */ 146 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull 147 148 #define ID_AIC7810 0x1078900400000000ull 149 #define ID_AIC7815 0x1578900400000000ull 150 151 typedef int (ahc_device_setup_t)(device_t, char *, ahc_chip *, 152 ahc_feature *, ahc_flag *); 153 154 static ahc_device_setup_t ahc_aic7850_setup; 155 static ahc_device_setup_t ahc_aic7855_setup; 156 static ahc_device_setup_t ahc_aic7859_setup; 157 static ahc_device_setup_t ahc_aic7860_setup; 158 static ahc_device_setup_t ahc_aic7870_setup; 159 static ahc_device_setup_t ahc_aha394X_setup; 160 static ahc_device_setup_t ahc_aha398X_setup; 161 static ahc_device_setup_t ahc_aic7880_setup; 162 static ahc_device_setup_t ahc_2940Pro_setup; 163 static ahc_device_setup_t ahc_aha394XU_setup; 164 static ahc_device_setup_t ahc_aha398XU_setup; 165 static ahc_device_setup_t ahc_aic7890_setup; 166 static ahc_device_setup_t ahc_aic7892_setup; 167 static ahc_device_setup_t ahc_aic7895_setup; 168 static ahc_device_setup_t ahc_aic7896_setup; 169 static ahc_device_setup_t ahc_aic7899_setup; 170 static ahc_device_setup_t ahc_raid_setup; 171 static ahc_device_setup_t ahc_aha394XX_setup; 172 static ahc_device_setup_t ahc_aha398XX_setup; 173 174 struct ahc_pci_identity { 175 u_int64_t full_id; 176 u_int64_t id_mask; 177 char *name; 178 ahc_device_setup_t *setup; 179 }; 180 181 struct ahc_pci_identity ahc_pci_ident_table [] = 182 { 183 /* aic7850 based controllers */ 184 { 185 ID_AHA_2910_15_20_30C, 186 ID_ALL_MASK, 187 "Adaptec 2910/15/20/30C SCSI adapter", 188 ahc_aic7850_setup 189 }, 190 /* aic7859 based controllers */ 191 { 192 ID_AHA_2930CU, 193 ID_ALL_MASK, 194 "Adaptec 2930CU SCSI adapter", 195 ahc_aic7859_setup 196 }, 197 /* aic7860 based controllers */ 198 { 199 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 200 ID_DEV_VENDOR_MASK, 201 "Adaptec 2940A Ultra SCSI adapter", 202 ahc_aic7860_setup 203 }, 204 { 205 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 206 ID_DEV_VENDOR_MASK, 207 "Adaptec 2940A/CN Ultra SCSI adapter", 208 ahc_aic7860_setup 209 }, 210 { 211 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 212 ID_DEV_VENDOR_MASK, 213 "Adaptec 2930C SCSI adapter (VAR)", 214 ahc_aic7860_setup 215 }, 216 /* aic7870 based controllers */ 217 { 218 ID_AHA_2940, 219 ID_ALL_MASK, 220 "Adaptec 2940 SCSI adapter", 221 ahc_aic7870_setup 222 }, 223 { 224 ID_AHA_3940, 225 ID_ALL_MASK, 226 "Adaptec 3940 SCSI adapter", 227 ahc_aha394X_setup 228 }, 229 { 230 ID_AHA_398X, 231 ID_ALL_MASK, 232 "Adaptec 398X SCSI RAID adapter", 233 ahc_aha398X_setup 234 }, 235 { 236 ID_AHA_2944, 237 ID_ALL_MASK, 238 "Adaptec 2944 SCSI adapter", 239 ahc_aic7870_setup 240 }, 241 { 242 ID_AHA_3944, 243 ID_ALL_MASK, 244 "Adaptec 3944 SCSI adapter", 245 ahc_aha394X_setup 246 }, 247 /* aic7880 based controllers */ 248 { 249 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 250 ID_DEV_VENDOR_MASK, 251 "Adaptec 2940 Ultra SCSI adapter", 252 ahc_aic7880_setup 253 }, 254 { 255 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 256 ID_DEV_VENDOR_MASK, 257 "Adaptec 3940 Ultra SCSI adapter", 258 ahc_aha394XU_setup 259 }, 260 { 261 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 262 ID_DEV_VENDOR_MASK, 263 "Adaptec 2944 Ultra SCSI adapter", 264 ahc_aic7880_setup 265 }, 266 { 267 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 268 ID_DEV_VENDOR_MASK, 269 "Adaptec 3944 Ultra SCSI adapter", 270 ahc_aha394XU_setup 271 }, 272 { 273 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 274 ID_DEV_VENDOR_MASK, 275 "Adaptec 398X Ultra SCSI RAID adapter", 276 ahc_aha398XU_setup 277 }, 278 { 279 /* 280 * XXX Don't know the slot numbers 281 * so we can't identify channels 282 */ 283 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 284 ID_DEV_VENDOR_MASK, 285 "Adaptec 4944 Ultra SCSI adapter", 286 ahc_aic7880_setup 287 }, 288 { 289 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 290 ID_DEV_VENDOR_MASK, 291 "Adaptec 2930 Ultra SCSI adapter", 292 ahc_aic7880_setup 293 }, 294 { 295 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 296 ID_DEV_VENDOR_MASK, 297 "Adaptec 2940 Pro Ultra SCSI adapter", 298 ahc_2940Pro_setup 299 }, 300 { 301 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 302 ID_DEV_VENDOR_MASK, 303 "Adaptec 2940/CN Ultra SCSI adapter", 304 ahc_aic7880_setup 305 }, 306 /* aic7890 based controllers */ 307 { 308 ID_AHA_2930U2, 309 ID_ALL_MASK, 310 "Adaptec 2930 Ultra2 SCSI adapter", 311 ahc_aic7890_setup 312 }, 313 { 314 ID_AHA_2940U2B, 315 ID_ALL_MASK, 316 "Adaptec 2940B Ultra2 SCSI adapter", 317 ahc_aic7890_setup 318 }, 319 { 320 ID_AHA_2940U2_OEM, 321 ID_ALL_MASK, 322 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 323 ahc_aic7890_setup 324 }, 325 { 326 ID_AHA_2940U2, 327 ID_ALL_MASK, 328 "Adaptec 2940 Ultra2 SCSI adapter", 329 ahc_aic7890_setup 330 }, 331 { 332 ID_AHA_2950U2B, 333 ID_ALL_MASK, 334 "Adaptec 2950 Ultra2 SCSI adapter", 335 ahc_aic7890_setup 336 }, 337 /* aic7892 based controllers */ 338 { 339 ID_AHA_29160, 340 ID_ALL_MASK, 341 "Adaptec 29160 Ultra160 SCSI adapter", 342 ahc_aic7892_setup 343 }, 344 { 345 ID_AHA_29160_CPQ, 346 ID_ALL_MASK, 347 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 348 ahc_aic7892_setup 349 }, 350 { 351 ID_AHA_29160N, 352 ID_ALL_MASK, 353 "Adaptec 29160N Ultra160 SCSI adapter", 354 ahc_aic7892_setup 355 }, 356 { 357 ID_AHA_29160B, 358 ID_ALL_MASK, 359 "Adaptec 29160B Ultra160 SCSI adapter", 360 ahc_aic7892_setup 361 }, 362 { 363 ID_AHA_19160B, 364 ID_ALL_MASK, 365 "Adaptec 19160B Ultra160 SCSI adapter", 366 ahc_aic7892_setup 367 }, 368 /* aic7895 based controllers */ 369 { 370 ID_AHA_2940U_DUAL, 371 ID_ALL_MASK, 372 "Adaptec 2940/DUAL Ultra SCSI adapter", 373 ahc_aic7895_setup 374 }, 375 { 376 ID_AHA_3940AU, 377 ID_ALL_MASK, 378 "Adaptec 3940A Ultra SCSI adapter", 379 ahc_aic7895_setup 380 }, 381 { 382 ID_AHA_3944AU, 383 ID_ALL_MASK, 384 "Adaptec 3944A Ultra SCSI adapter", 385 ahc_aic7895_setup 386 }, 387 /* aic7896/97 based controllers */ 388 { 389 ID_AHA_3950U2B_0, 390 ID_ALL_MASK, 391 "Adaptec 3950B Ultra2 SCSI adapter", 392 ahc_aic7896_setup 393 }, 394 { 395 ID_AHA_3950U2B_1, 396 ID_ALL_MASK, 397 "Adaptec 3950B Ultra2 SCSI adapter", 398 ahc_aic7896_setup 399 }, 400 { 401 ID_AHA_3950U2D_0, 402 ID_ALL_MASK, 403 "Adaptec 3950D Ultra2 SCSI adapter", 404 ahc_aic7896_setup 405 }, 406 { 407 ID_AHA_3950U2D_1, 408 ID_ALL_MASK, 409 "Adaptec 3950D Ultra2 SCSI adapter", 410 ahc_aic7896_setup 411 }, 412 /* aic7899 based controllers */ 413 { 414 ID_AHA_3960D, 415 ID_ALL_MASK, 416 "Adaptec 3960D Ultra160 SCSI adapter", 417 ahc_aic7899_setup 418 }, 419 { 420 ID_AHA_3960D_CPQ, 421 ID_ALL_MASK, 422 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 423 ahc_aic7899_setup 424 }, 425 /* Generic chip probes for devices we don't know 'exactly' */ 426 { 427 ID_AIC7850 & ID_DEV_VENDOR_MASK, 428 ID_DEV_VENDOR_MASK, 429 "Adaptec aic7850 SCSI adapter", 430 ahc_aic7850_setup 431 }, 432 { 433 ID_AIC7855 & ID_DEV_VENDOR_MASK, 434 ID_DEV_VENDOR_MASK, 435 "Adaptec aic7855 SCSI adapter", 436 ahc_aic7855_setup 437 }, 438 { 439 ID_AIC7859 & ID_DEV_VENDOR_MASK, 440 ID_DEV_VENDOR_MASK, 441 "Adaptec aic7859 SCSI adapter", 442 ahc_aic7859_setup 443 }, 444 { 445 ID_AIC7860 & ID_DEV_VENDOR_MASK, 446 ID_DEV_VENDOR_MASK, 447 "Adaptec aic7860 SCSI adapter", 448 ahc_aic7860_setup 449 }, 450 { 451 ID_AIC7870 & ID_DEV_VENDOR_MASK, 452 ID_DEV_VENDOR_MASK, 453 "Adaptec aic7870 SCSI adapter", 454 ahc_aic7870_setup 455 }, 456 { 457 ID_AIC7880 & ID_DEV_VENDOR_MASK, 458 ID_DEV_VENDOR_MASK, 459 "Adaptec aic7880 Ultra SCSI adapter", 460 ahc_aic7880_setup 461 }, 462 { 463 ID_AIC7890 & ID_DEV_VENDOR_MASK, 464 ID_DEV_VENDOR_MASK, 465 "Adaptec aic7890/91 Ultra2 SCSI adapter", 466 ahc_aic7890_setup 467 }, 468 { 469 ID_AIC7892 & ID_DEV_VENDOR_MASK, 470 ID_DEV_VENDOR_MASK, 471 "Adaptec aic7892 Ultra160 SCSI adapter", 472 ahc_aic7892_setup 473 }, 474 { 475 ID_AIC7895 & ID_DEV_VENDOR_MASK, 476 ID_DEV_VENDOR_MASK, 477 "Adaptec aic7895 Ultra SCSI adapter", 478 ahc_aic7895_setup 479 }, 480 { 481 ID_AIC7895_RAID_PORT & ID_DEV_VENDOR_MASK, 482 ID_DEV_VENDOR_MASK, 483 "Adaptec aic7895 Ultra SCSI adapter (RAID PORT)", 484 ahc_aic7895_setup 485 }, 486 { 487 ID_AIC7896 & ID_DEV_VENDOR_MASK, 488 ID_DEV_VENDOR_MASK, 489 "Adaptec aic7896/97 Ultra2 SCSI adapter", 490 ahc_aic7896_setup 491 }, 492 { 493 ID_AIC7899 & ID_DEV_VENDOR_MASK, 494 ID_DEV_VENDOR_MASK, 495 "Adaptec aic7899 Ultra160 SCSI adapter", 496 ahc_aic7899_setup 497 }, 498 { 499 ID_AIC7810 & ID_DEV_VENDOR_MASK, 500 ID_DEV_VENDOR_MASK, 501 "Adaptec aic7810 RAID memory controller", 502 ahc_raid_setup 503 }, 504 { 505 ID_AIC7815 & ID_DEV_VENDOR_MASK, 506 ID_DEV_VENDOR_MASK, 507 "Adaptec aic7815 RAID memory controller", 508 ahc_raid_setup 509 } 510 }; 511 512 static const int ahc_num_pci_devs = 513 sizeof(ahc_pci_ident_table) / sizeof(*ahc_pci_ident_table); 514 515 #define AHC_394X_SLOT_CHANNEL_A 4 516 #define AHC_394X_SLOT_CHANNEL_B 5 517 518 #define AHC_398X_SLOT_CHANNEL_A 4 519 #define AHC_398X_SLOT_CHANNEL_B 8 520 #define AHC_398X_SLOT_CHANNEL_C 12 521 522 #define DEVCONFIG 0x40 523 #define SCBSIZE32 0x00010000ul /* aic789X only */ 524 #define MPORTMODE 0x00000400ul /* aic7870 only */ 525 #define RAMPSM 0x00000200ul /* aic7870 only */ 526 #define VOLSENSE 0x00000100ul 527 #define SCBRAMSEL 0x00000080ul 528 #define MRDCEN 0x00000040ul 529 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 530 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 531 #define BERREN 0x00000008ul 532 #define DACEN 0x00000004ul 533 #define STPWLEVEL 0x00000002ul 534 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 535 536 #define CSIZE_LATTIME 0x0c 537 #define CACHESIZE 0x0000003ful /* only 5 bits */ 538 #define LATTIME 0x0000ff00ul 539 540 static struct ahc_pci_identity *ahc_find_pci_device(device_t dev); 541 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 542 static void ahc_ext_scbram_config(struct ahc_softc *ahc, int enable, 543 int pcheck, int fast); 544 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 545 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 546 static void configure_termination(struct ahc_softc *ahc, 547 struct seeprom_descriptor *sd, 548 u_int adapter_control, 549 u_int *sxfrctl1); 550 551 static void ahc_new_term_detect(struct ahc_softc *ahc, 552 int *enableSEC_low, 553 int *enableSEC_high, 554 int *enablePRI_low, 555 int *enablePRI_high, 556 int *eeprom_present); 557 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 558 int *internal68_present, 559 int *externalcable_present, 560 int *eeprom_present); 561 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 562 int *externalcable_present, 563 int *eeprom_present); 564 static int acquire_seeprom(struct ahc_softc *ahc, 565 struct seeprom_descriptor *sd); 566 static void release_seeprom(struct seeprom_descriptor *sd); 567 static void write_brdctl(struct ahc_softc *ahc, u_int8_t value); 568 static u_int8_t read_brdctl(struct ahc_softc *ahc); 569 570 static struct ahc_softc *first_398X; 571 572 static int ahc_pci_probe(device_t dev); 573 static int ahc_pci_attach(device_t dev); 574 575 /* Exported for use in the ahc_intr routine */ 576 void ahc_pci_intr(struct ahc_softc *ahc); 577 578 static device_method_t ahc_pci_methods[] = { 579 /* Device interface */ 580 DEVMETHOD(device_probe, ahc_pci_probe), 581 DEVMETHOD(device_attach, ahc_pci_attach), 582 { 0, 0 } 583 }; 584 585 static driver_t ahc_pci_driver = { 586 "ahc", 587 ahc_pci_methods, 588 sizeof(struct ahc_softc) 589 }; 590 591 static devclass_t ahc_devclass; 592 593 DRIVER_MODULE(ahc, pci, ahc_pci_driver, ahc_devclass, 0, 0); 594 595 static struct ahc_pci_identity * 596 ahc_find_pci_device(device_t dev) 597 { 598 u_int64_t full_id; 599 struct ahc_pci_identity *entry; 600 u_int i; 601 602 full_id = ahc_compose_id(pci_get_device(dev), 603 pci_get_vendor(dev), 604 pci_get_subdevice(dev), 605 pci_get_subvendor(dev)); 606 607 for (i = 0; i < ahc_num_pci_devs; i++) { 608 entry = &ahc_pci_ident_table[i]; 609 if (entry->full_id == (full_id & entry->id_mask)) 610 return (entry); 611 } 612 return (NULL); 613 } 614 615 static int 616 ahc_pci_probe(device_t dev) 617 { 618 struct ahc_pci_identity *entry; 619 620 entry = ahc_find_pci_device(dev); 621 if (entry != NULL) { 622 device_set_desc(dev, entry->name); 623 return (0); 624 } 625 return (ENXIO); 626 } 627 628 static int 629 ahc_pci_attach(device_t dev) 630 { 631 bus_dma_tag_t parent_dmat; 632 struct ahc_pci_identity *entry; 633 struct resource *regs; 634 struct ahc_softc *ahc; 635 u_int command; 636 struct scb_data *shared_scb_data; 637 ahc_chip ahc_t = AHC_NONE; 638 ahc_feature ahc_fe = AHC_FENONE; 639 ahc_flag ahc_f = AHC_FNONE; 640 int regs_type; 641 int regs_id; 642 u_int our_id = 0; 643 u_int sxfrctl1; 644 u_int scsiseq; 645 int error; 646 int zero; 647 char channel; 648 649 shared_scb_data = NULL; 650 command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1); 651 entry = ahc_find_pci_device(dev); 652 if (entry == NULL) 653 return (ENXIO); 654 error = entry->setup(dev, &channel, &ahc_t, &ahc_fe, &ahc_f); 655 if (error != 0) 656 return (error); 657 658 regs = NULL; 659 regs_type = 0; 660 regs_id = 0; 661 #ifdef AHC_ALLOW_MEMIO 662 if ((command & PCIM_CMD_MEMEN) != 0) { 663 regs_type = SYS_RES_MEMORY; 664 regs_id = AHC_PCI_MEMADDR; 665 regs = bus_alloc_resource(dev, regs_type, 666 ®s_id, 0, ~0, 1, RF_ACTIVE); 667 } 668 #endif 669 if (regs == NULL && (command & PCI_COMMAND_IO_ENABLE) != 0) { 670 regs_type = SYS_RES_IOPORT; 671 regs_id = AHC_PCI_IOADDR; 672 regs = bus_alloc_resource(dev, regs_type, 673 ®s_id, 0, ~0, 1, RF_ACTIVE); 674 } 675 676 if (regs == NULL) { 677 device_printf(dev, "can't allocate register resources\n"); 678 return (ENOMEM); 679 } 680 681 /* Ensure busmastering is enabled */ 682 command |= PCIM_CMD_BUSMASTEREN; 683 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1); 684 685 /* Allocate a dmatag for our SCB DMA maps */ 686 /* XXX Should be a child of the PCI bus dma tag */ 687 error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1, 688 /*boundary*/0, 689 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 690 /*highaddr*/BUS_SPACE_MAXADDR, 691 /*filter*/NULL, /*filterarg*/NULL, 692 /*maxsize*/MAXBSIZE, /*nsegments*/AHC_NSEG, 693 /*maxsegsz*/AHC_MAXTRANSFER_SIZE, 694 /*flags*/BUS_DMA_ALLOCNOW, &parent_dmat); 695 696 if (error != 0) { 697 printf("ahc_pci_attach: Could not allocate DMA tag " 698 "- error %d\n", error); 699 return (ENOMEM); 700 } 701 702 /* On all PCI adapters, we allow SCB paging */ 703 ahc_f |= AHC_PAGESCBS; 704 if ((ahc = ahc_alloc(dev, regs, regs_type, regs_id, parent_dmat, 705 ahc_t|AHC_PCI, ahc_fe, ahc_f, 706 shared_scb_data)) == NULL) 707 return (ENOMEM); 708 709 ahc->channel = channel; 710 711 /* Store our PCI bus information for use in our PCI error handler */ 712 ahc->device = dev; 713 714 /* Remeber how the card was setup in case there is no SEEPROM */ 715 ahc_outb(ahc, HCNTRL, ahc->pause); 716 if ((ahc->features & AHC_ULTRA2) != 0) 717 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 718 else 719 our_id = ahc_inb(ahc, SCSIID) & OID; 720 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 721 scsiseq = ahc_inb(ahc, SCSISEQ); 722 723 if (ahc_reset(ahc) != 0) { 724 /* Failed */ 725 ahc_free(ahc); 726 return (ENXIO); 727 } 728 729 if ((ahc->features & AHC_DT) != 0) { 730 u_int sfunct; 731 732 /* Perform ALT-Mode Setup */ 733 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 734 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 735 ahc_outb(ahc, OPTIONMODE, OPTIONMODE_DEFAULTS); 736 /* Send CRC info in target mode every 4K */ 737 ahc_outb(ahc, TARGCRCCNT, 0); 738 ahc_outb(ahc, TARGCRCCNT + 1, 0x10); 739 ahc_outb(ahc, SFUNCT, sfunct); 740 741 /* Normal mode setup */ 742 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 743 |TARGCRCENDEN|TARGCRCCNTEN); 744 } 745 zero = 0; 746 ahc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &zero, 747 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 748 if (ahc->irq == NULL) { 749 ahc_free(ahc); 750 return (ENOMEM); 751 } 752 753 ahc->irq_res_type = SYS_RES_IRQ; 754 755 /* 756 * Do aic7880/aic7870/aic7860/aic7850 specific initialization 757 */ 758 { 759 u_int8_t sblkctl; 760 u_int dscommand0; 761 762 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 763 dscommand0 |= MPARCKEN; 764 if ((ahc->features & AHC_ULTRA2) != 0) { 765 766 /* 767 * DPARCKEN doesn't work correctly on 768 * some MBs so don't use it. 769 */ 770 dscommand0 &= ~(USCBSIZE32|DPARCKEN); 771 dscommand0 |= CACHETHEN; 772 } 773 774 ahc_outb(ahc, DSCOMMAND0, dscommand0); 775 776 /* See if we have an SEEPROM and perform auto-term */ 777 check_extport(ahc, &sxfrctl1); 778 779 /* 780 * Take the LED out of diagnostic mode 781 */ 782 sblkctl = ahc_inb(ahc, SBLKCTL); 783 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 784 785 /* 786 * I don't know where this is set in the SEEPROM or by the 787 * BIOS, so we default to 100% on Ultra or slower controllers 788 * and 75% on ULTRA2 controllers. 789 */ 790 if ((ahc->features & AHC_ULTRA2) != 0) { 791 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 792 } else { 793 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 794 } 795 796 if (ahc->flags & AHC_USEDEFAULTS) { 797 /* 798 * PCI Adapter default setup 799 * Should only be used if the adapter does not have 800 * an SEEPROM. 801 */ 802 /* See if someone else set us up already */ 803 if (scsiseq != 0) { 804 printf("%s: Using left over BIOS settings\n", 805 ahc_name(ahc)); 806 ahc->flags &= ~AHC_USEDEFAULTS; 807 } else { 808 /* 809 * Assume only one connector and always turn 810 * on termination. 811 */ 812 our_id = 0x07; 813 sxfrctl1 = STPWEN; 814 } 815 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 816 817 ahc->our_id = our_id; 818 } 819 } 820 821 /* 822 * Take a look to see if we have external SRAM. 823 * We currently do not attempt to use SRAM that is 824 * shared among multiple controllers. 825 */ 826 ahc_probe_ext_scbram(ahc); 827 828 829 printf("%s: %s ", ahc_name(ahc), 830 ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 831 832 /* 833 * Record our termination setting for the 834 * generic initialization routine. 835 */ 836 if ((sxfrctl1 & STPWEN) != 0) 837 ahc->flags |= AHC_TERM_ENB_A; 838 839 if (ahc_init(ahc)) { 840 ahc_free(ahc); 841 return (ENOMEM); 842 } 843 844 /* XXX Crude hack - fix sometime */ 845 if (ahc->flags & AHC_SHARED_SRAM) { 846 /* Only set this once we've successfully probed */ 847 if (shared_scb_data == NULL) 848 first_398X = ahc; 849 } 850 851 ahc_attach(ahc); 852 return (0); 853 } 854 855 /* 856 * Test for the presense of external sram in an 857 * "unshared" configuration. 858 */ 859 static int 860 ahc_ext_scbram_present(struct ahc_softc *ahc) 861 { 862 int ramps; 863 int single_user; 864 u_int32_t devconfig; 865 866 devconfig = pci_read_config(ahc->device, DEVCONFIG, /*bytes*/4); 867 single_user = (devconfig & MPORTMODE) != 0; 868 869 if ((ahc->features & AHC_ULTRA2) != 0) 870 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 871 else if ((ahc->chip & AHC_CHIPID_MASK) >= AHC_AIC7870) 872 ramps = (devconfig & RAMPSM) != 0; 873 else 874 ramps = 0; 875 876 if (ramps && single_user) 877 return (1); 878 return (0); 879 } 880 881 /* 882 * Enable external scbram. 883 */ 884 static void 885 ahc_ext_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, int fast) 886 { 887 u_int32_t devconfig; 888 889 if (ahc->features & AHC_MULTI_FUNC) { 890 /* 891 * Set the SCB Base addr (highest address bit) 892 * depending on which channel we are. 893 */ 894 ahc_outb(ahc, SCBBADDR, pci_get_function(ahc->device)); 895 } 896 897 devconfig = pci_read_config(ahc->device, DEVCONFIG, /*bytes*/4); 898 if ((ahc->features & AHC_ULTRA2) != 0) { 899 u_int dscommand0; 900 901 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 902 if (enable) 903 dscommand0 &= ~INTSCBRAMSEL; 904 else 905 dscommand0 |= INTSCBRAMSEL; 906 ahc_outb(ahc, DSCOMMAND0, dscommand0); 907 } else { 908 if (fast) 909 devconfig &= ~EXTSCBTIME; 910 else 911 devconfig |= EXTSCBTIME; 912 if (enable) 913 devconfig &= ~SCBRAMSEL; 914 else 915 devconfig |= SCBRAMSEL; 916 } 917 if (pcheck) 918 devconfig |= EXTSCBPEN; 919 else 920 devconfig &= ~EXTSCBPEN; 921 922 pci_write_config(ahc->device, DEVCONFIG, devconfig, /*bytes*/4); 923 } 924 925 /* 926 * Take a look to see if we have external SRAM. 927 * We currently do not attempt to use SRAM that is 928 * shared among multiple controllers. 929 */ 930 static void 931 ahc_probe_ext_scbram(struct ahc_softc *ahc) 932 { 933 int num_scbs; 934 int test_num_scbs; 935 int enable; 936 int pcheck; 937 int fast; 938 939 if (ahc_ext_scbram_present(ahc) == 0) 940 return; 941 942 /* 943 * Probe for the best parameters to use. 944 */ 945 enable = FALSE; 946 pcheck = FALSE; 947 fast = FALSE; 948 ahc_ext_scbram_config(ahc, /*enable*/TRUE, pcheck, fast); 949 num_scbs = ahc_probe_scbs(ahc); 950 if (num_scbs == 0) { 951 /* The SRAM wasn't really present. */ 952 goto done; 953 } 954 enable = TRUE; 955 956 /* 957 * Clear any outstanding parity error 958 * and ensure that parity error reporting 959 * is enabled. 960 */ 961 ahc_outb(ahc, SEQCTL, 0); 962 ahc_outb(ahc, CLRINT, CLRPARERR); 963 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 964 965 /* Now see if we can do parity */ 966 ahc_ext_scbram_config(ahc, enable, /*pcheck*/TRUE, fast); 967 num_scbs = ahc_probe_scbs(ahc); 968 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 969 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 970 pcheck = TRUE; 971 972 /* Clear any resulting parity error */ 973 ahc_outb(ahc, CLRINT, CLRPARERR); 974 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 975 976 /* Now see if we can do fast timing */ 977 ahc_ext_scbram_config(ahc, enable, pcheck, /*fast*/TRUE); 978 test_num_scbs = ahc_probe_scbs(ahc); 979 if (test_num_scbs == num_scbs 980 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 981 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 982 fast = TRUE; 983 984 done: 985 /* 986 * Disable parity error reporting until we 987 * can load instruction ram. 988 */ 989 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 990 /* Clear any latched parity error */ 991 ahc_outb(ahc, CLRINT, CLRPARERR); 992 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 993 if (bootverbose && enable) { 994 printf("%s: External SRAM, %s access%s\n", 995 ahc_name(ahc), fast ? "fast" : "slow", 996 pcheck ? ", parity checking enabled" : ""); 997 998 } 999 ahc_ext_scbram_config(ahc, enable, pcheck, fast); 1000 } 1001 1002 /* 1003 * Check the external port logic for a serial eeprom 1004 * and termination/cable detection contrls. 1005 */ 1006 static void 1007 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 1008 { 1009 struct seeprom_descriptor sd; 1010 struct seeprom_config sc; 1011 u_int scsi_conf; 1012 u_int adapter_control; 1013 int have_seeprom; 1014 int have_autoterm; 1015 1016 sd.sd_tag = ahc->tag; 1017 sd.sd_bsh = ahc->bsh; 1018 sd.sd_control_offset = SEECTL; 1019 sd.sd_status_offset = SEECTL; 1020 sd.sd_dataout_offset = SEECTL; 1021 1022 /* 1023 * For some multi-channel devices, the c46 is simply too 1024 * small to work. For the other controller types, we can 1025 * get our information from either SEEPROM type. Set the 1026 * type to start our probe with accordingly. 1027 */ 1028 if (ahc->flags & AHC_LARGE_SEEPROM) 1029 sd.sd_chip = C56_66; 1030 else 1031 sd.sd_chip = C46; 1032 1033 sd.sd_MS = SEEMS; 1034 sd.sd_RDY = SEERDY; 1035 sd.sd_CS = SEECS; 1036 sd.sd_CK = SEECK; 1037 sd.sd_DO = SEEDO; 1038 sd.sd_DI = SEEDI; 1039 1040 have_seeprom = acquire_seeprom(ahc, &sd); 1041 if (have_seeprom) { 1042 1043 if (bootverbose) 1044 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 1045 1046 for (;;) { 1047 bus_size_t start_addr; 1048 1049 start_addr = 32 * (ahc->channel - 'A'); 1050 1051 have_seeprom = read_seeprom(&sd, (u_int16_t *)&sc, 1052 start_addr, sizeof(sc)/2); 1053 1054 if (have_seeprom) { 1055 /* Check checksum */ 1056 int i; 1057 int maxaddr; 1058 u_int32_t checksum; 1059 u_int16_t *scarray; 1060 1061 maxaddr = (sizeof(sc)/2) - 1; 1062 checksum = 0; 1063 scarray = (u_int16_t *)≻ 1064 1065 for (i = 0; i < maxaddr; i++) 1066 checksum = checksum + scarray[i]; 1067 if (checksum == 0 1068 || (checksum & 0xFFFF) != sc.checksum) { 1069 if (bootverbose && sd.sd_chip == C56_66) 1070 printf ("checksum error\n"); 1071 have_seeprom = 0; 1072 } else { 1073 if (bootverbose) 1074 printf("done.\n"); 1075 break; 1076 } 1077 } 1078 1079 if (sd.sd_chip == C56_66) 1080 break; 1081 sd.sd_chip = C56_66; 1082 } 1083 } 1084 1085 if (!have_seeprom) { 1086 if (bootverbose) 1087 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 1088 ahc->flags |= AHC_USEDEFAULTS; 1089 } else { 1090 /* 1091 * Put the data we've collected down into SRAM 1092 * where ahc_init will find it. 1093 */ 1094 int i; 1095 int max_targ = sc.max_targets & CFMAXTARG; 1096 u_int16_t discenable; 1097 u_int16_t ultraenb; 1098 1099 discenable = 0; 1100 ultraenb = 0; 1101 if ((sc.adapter_control & CFULTRAEN) != 0) { 1102 /* 1103 * Determine if this adapter has a "newstyle" 1104 * SEEPROM format. 1105 */ 1106 for (i = 0; i < max_targ; i++) { 1107 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0){ 1108 ahc->flags |= AHC_NEWEEPROM_FMT; 1109 break; 1110 } 1111 } 1112 } 1113 1114 for (i = 0; i < max_targ; i++) { 1115 u_int scsirate; 1116 u_int16_t target_mask; 1117 1118 target_mask = 0x01 << i; 1119 if (sc.device_flags[i] & CFDISC) 1120 discenable |= target_mask; 1121 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1122 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) 1123 ultraenb |= target_mask; 1124 } else if ((sc.adapter_control & CFULTRAEN) != 0) { 1125 ultraenb |= target_mask; 1126 } 1127 if ((sc.device_flags[i] & CFXFER) == 0x04 1128 && (ultraenb & target_mask) != 0) { 1129 /* Treat 10MHz as a non-ultra speed */ 1130 sc.device_flags[i] &= ~CFXFER; 1131 ultraenb &= ~target_mask; 1132 } 1133 if ((ahc->features & AHC_ULTRA2) != 0) { 1134 u_int offset; 1135 1136 if (sc.device_flags[i] & CFSYNCH) 1137 offset = MAX_OFFSET_ULTRA2; 1138 else 1139 offset = 0; 1140 ahc_outb(ahc, TARG_OFFSET + i, offset); 1141 1142 scsirate = (sc.device_flags[i] & CFXFER) 1143 | ((ultraenb & target_mask) 1144 ? 0x8 : 0x0); 1145 if (sc.device_flags[i] & CFWIDEB) 1146 scsirate |= WIDEXFER; 1147 } else { 1148 scsirate = (sc.device_flags[i] & CFXFER) << 4; 1149 if (sc.device_flags[i] & CFSYNCH) 1150 scsirate |= SOFS; 1151 if (sc.device_flags[i] & CFWIDEB) 1152 scsirate |= WIDEXFER; 1153 } 1154 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1155 } 1156 ahc->our_id = sc.brtime_id & CFSCSIID; 1157 1158 scsi_conf = (ahc->our_id & 0x7); 1159 if (sc.adapter_control & CFSPARITY) 1160 scsi_conf |= ENSPCHK; 1161 if (sc.adapter_control & CFRESETB) 1162 scsi_conf |= RESET_SCSI; 1163 1164 if (sc.bios_control & CFEXTEND) 1165 ahc->flags |= AHC_EXTENDED_TRANS_A; 1166 if (ahc->features & AHC_ULTRA 1167 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1168 /* Should we enable Ultra mode? */ 1169 if (!(sc.adapter_control & CFULTRAEN)) 1170 /* Treat us as a non-ultra card */ 1171 ultraenb = 0; 1172 } 1173 /* Set SCSICONF info */ 1174 ahc_outb(ahc, SCSICONF, scsi_conf); 1175 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1176 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1177 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1178 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1179 } 1180 1181 /* 1182 * Cards that have the external logic necessary to talk to 1183 * a SEEPROM, are almost certain to have the remaining logic 1184 * necessary for auto-termination control. This assumption 1185 * hasn't failed yet... 1186 */ 1187 have_autoterm = have_seeprom; 1188 if (have_seeprom) 1189 adapter_control = sc.adapter_control; 1190 else 1191 adapter_control = CFAUTOTERM; 1192 1193 /* 1194 * Some low-cost chips have SEEPROM and auto-term control built 1195 * in, instead of using a GAL. They can tell us directly 1196 * if the termination logic is enabled. 1197 */ 1198 if ((ahc->features & AHC_SPIOCAP) != 0) { 1199 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0) 1200 have_autoterm = TRUE; 1201 else 1202 have_autoterm = FALSE; 1203 } 1204 1205 if (have_autoterm) 1206 configure_termination(ahc, &sd, adapter_control, sxfrctl1); 1207 1208 release_seeprom(&sd); 1209 } 1210 1211 static void 1212 configure_termination(struct ahc_softc *ahc, 1213 struct seeprom_descriptor *sd, 1214 u_int adapter_control, 1215 u_int *sxfrctl1) 1216 { 1217 u_int8_t brddat; 1218 1219 brddat = 0; 1220 1221 /* 1222 * Update the settings in sxfrctl1 to match the 1223 * termination settings 1224 */ 1225 *sxfrctl1 = 0; 1226 1227 /* 1228 * SEECS must be on for the GALS to latch 1229 * the data properly. Be sure to leave MS 1230 * on or we will release the seeprom. 1231 */ 1232 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1233 if ((adapter_control & CFAUTOTERM) != 0 1234 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 1235 int internal50_present; 1236 int internal68_present; 1237 int externalcable_present; 1238 int eeprom_present; 1239 int enableSEC_low; 1240 int enableSEC_high; 1241 int enablePRI_low; 1242 int enablePRI_high; 1243 1244 enableSEC_low = 0; 1245 enableSEC_high = 0; 1246 enablePRI_low = 0; 1247 enablePRI_high = 0; 1248 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 1249 ahc_new_term_detect(ahc, &enableSEC_low, 1250 &enableSEC_high, 1251 &enablePRI_low, 1252 &enablePRI_high, 1253 &eeprom_present); 1254 if ((adapter_control & CFSEAUTOTERM) == 0) { 1255 if (bootverbose) 1256 printf("%s: Manual SE Termination\n", 1257 ahc_name(ahc)); 1258 enableSEC_low = (adapter_control & CFSTERM); 1259 enableSEC_high = (adapter_control & CFWSTERM); 1260 } 1261 if ((adapter_control & CFAUTOTERM) == 0) { 1262 if (bootverbose) 1263 printf("%s: Manual LVD Termination\n", 1264 ahc_name(ahc)); 1265 enablePRI_low = enablePRI_high = 1266 (adapter_control & CFLVDSTERM); 1267 } 1268 /* Make the table calculations below happy */ 1269 internal50_present = 0; 1270 internal68_present = 1; 1271 externalcable_present = 1; 1272 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1273 aic785X_cable_detect(ahc, &internal50_present, 1274 &externalcable_present, 1275 &eeprom_present); 1276 } else { 1277 aic787X_cable_detect(ahc, &internal50_present, 1278 &internal68_present, 1279 &externalcable_present, 1280 &eeprom_present); 1281 } 1282 1283 if ((ahc->features & AHC_WIDE) == 0) 1284 internal68_present = 0; 1285 1286 if (bootverbose) { 1287 if ((ahc->features & AHC_ULTRA2) == 0) { 1288 printf("%s: internal 50 cable %s present, " 1289 "internal 68 cable %s present\n", 1290 ahc_name(ahc), 1291 internal50_present ? "is":"not", 1292 internal68_present ? "is":"not"); 1293 1294 printf("%s: external cable %s present\n", 1295 ahc_name(ahc), 1296 externalcable_present ? "is":"not"); 1297 } 1298 printf("%s: BIOS eeprom %s present\n", 1299 ahc_name(ahc), eeprom_present ? "is" : "not"); 1300 } 1301 1302 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1303 /* 1304 * The 50 pin connector is a separate bus, 1305 * so force it to always be terminated. 1306 * In the future, perform current sensing 1307 * to determine if we are in the middle of 1308 * a properly terminated bus. 1309 */ 1310 internal50_present = 0; 1311 } 1312 1313 /* 1314 * Now set the termination based on what 1315 * we found. 1316 * Flash Enable = BRDDAT7 1317 * Secondary High Term Enable = BRDDAT6 1318 * Secondary Low Term Enable = BRDDAT5 (7890) 1319 * Primary High Term Enable = BRDDAT4 (7890) 1320 */ 1321 if ((ahc->features & AHC_ULTRA2) == 0 1322 && (internal50_present != 0) 1323 && (internal68_present != 0) 1324 && (externalcable_present != 0)) { 1325 printf("%s: Illegal cable configuration!!. " 1326 "Only two connectors on the " 1327 "adapter may be used at a " 1328 "time!\n", ahc_name(ahc)); 1329 } 1330 1331 if ((ahc->features & AHC_WIDE) != 0 1332 && ((externalcable_present == 0) 1333 || (internal68_present == 0) 1334 || (enableSEC_high != 0))) { 1335 brddat |= BRDDAT6; 1336 if (bootverbose) { 1337 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1338 printf("%s: 68 pin termination " 1339 "Enabled\n", ahc_name(ahc)); 1340 else 1341 printf("%s: %sHigh byte termination " 1342 "Enabled\n", ahc_name(ahc), 1343 enableSEC_high ? "Secondary " 1344 : ""); 1345 } 1346 } 1347 1348 if (((internal50_present ? 1 : 0) 1349 + (internal68_present ? 1 : 0) 1350 + (externalcable_present ? 1 : 0)) <= 1 1351 || (enableSEC_low != 0)) { 1352 if ((ahc->features & AHC_ULTRA2) != 0) 1353 brddat |= BRDDAT5; 1354 else 1355 *sxfrctl1 |= STPWEN; 1356 if (bootverbose) { 1357 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1358 printf("%s: 50 pin termination " 1359 "Enabled\n", ahc_name(ahc)); 1360 else 1361 printf("%s: %sLow byte termination " 1362 "Enabled\n", ahc_name(ahc), 1363 enableSEC_low ? "Secondary " 1364 : ""); 1365 } 1366 } 1367 1368 if (enablePRI_low != 0) { 1369 *sxfrctl1 |= STPWEN; 1370 if (bootverbose) 1371 printf("%s: Primary Low Byte termination " 1372 "Enabled\n", ahc_name(ahc)); 1373 } 1374 1375 /* 1376 * Setup STPWEN before setting up the rest of 1377 * the termination per the tech note on the U160 cards. 1378 */ 1379 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1380 1381 if (enablePRI_high != 0) { 1382 brddat |= BRDDAT4; 1383 if (bootverbose) 1384 printf("%s: Primary High Byte " 1385 "termination Enabled\n", 1386 ahc_name(ahc)); 1387 } 1388 1389 write_brdctl(ahc, brddat); 1390 1391 } else { 1392 if ((adapter_control & CFSTERM) != 0) { 1393 *sxfrctl1 |= STPWEN; 1394 1395 if (bootverbose) 1396 printf("%s: %sLow byte termination Enabled\n", 1397 ahc_name(ahc), 1398 (ahc->features & AHC_ULTRA2) ? "Primary " 1399 : ""); 1400 } 1401 1402 if ((adapter_control & CFWSTERM) != 0) { 1403 brddat |= BRDDAT6; 1404 if (bootverbose) 1405 printf("%s: %sHigh byte termination Enabled\n", 1406 ahc_name(ahc), 1407 (ahc->features & AHC_ULTRA2) 1408 ? "Secondary " : ""); 1409 } 1410 1411 /* 1412 * Setup STPWEN before setting up the rest of 1413 * the termination per the tech note on the U160 cards. 1414 */ 1415 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1416 1417 write_brdctl(ahc, brddat); 1418 } 1419 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1420 } 1421 1422 static void 1423 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 1424 int *enableSEC_high, int *enablePRI_low, 1425 int *enablePRI_high, int *eeprom_present) 1426 { 1427 u_int8_t brdctl; 1428 1429 /* 1430 * BRDDAT7 = Eeprom 1431 * BRDDAT6 = Enable Secondary High Byte termination 1432 * BRDDAT5 = Enable Secondary Low Byte termination 1433 * BRDDAT4 = Enable Primary high byte termination 1434 * BRDDAT3 = Enable Primary low byte termination 1435 */ 1436 brdctl = read_brdctl(ahc); 1437 *eeprom_present = brdctl & BRDDAT7; 1438 *enableSEC_high = (brdctl & BRDDAT6); 1439 *enableSEC_low = (brdctl & BRDDAT5); 1440 *enablePRI_high = (brdctl & BRDDAT4); 1441 *enablePRI_low = (brdctl & BRDDAT3); 1442 } 1443 1444 static void 1445 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1446 int *internal68_present, int *externalcable_present, 1447 int *eeprom_present) 1448 { 1449 u_int8_t brdctl; 1450 1451 /* 1452 * First read the status of our cables. 1453 * Set the rom bank to 0 since the 1454 * bank setting serves as a multiplexor 1455 * for the cable detection logic. 1456 * BRDDAT5 controls the bank switch. 1457 */ 1458 write_brdctl(ahc, 0); 1459 1460 /* 1461 * Now read the state of the internal 1462 * connectors. BRDDAT6 is INT50 and 1463 * BRDDAT7 is INT68. 1464 */ 1465 brdctl = read_brdctl(ahc); 1466 *internal50_present = !(brdctl & BRDDAT6); 1467 *internal68_present = !(brdctl & BRDDAT7); 1468 1469 /* 1470 * Set the rom bank to 1 and determine 1471 * the other signals. 1472 */ 1473 write_brdctl(ahc, BRDDAT5); 1474 1475 /* 1476 * Now read the state of the external 1477 * connectors. BRDDAT6 is EXT68 and 1478 * BRDDAT7 is EPROMPS. 1479 */ 1480 brdctl = read_brdctl(ahc); 1481 *externalcable_present = !(brdctl & BRDDAT6); 1482 *eeprom_present = brdctl & BRDDAT7; 1483 } 1484 1485 static void 1486 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1487 int *externalcable_present, int *eeprom_present) 1488 { 1489 u_int8_t brdctl; 1490 1491 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1492 ahc_outb(ahc, BRDCTL, 0); 1493 brdctl = ahc_inb(ahc, BRDCTL); 1494 *internal50_present = !(brdctl & BRDDAT5); 1495 *externalcable_present = !(brdctl & BRDDAT6); 1496 1497 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) != 0; 1498 } 1499 1500 static int 1501 acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1502 { 1503 int wait; 1504 1505 if ((ahc->features & AHC_SPIOCAP) != 0 1506 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1507 return (0); 1508 1509 /* 1510 * Request access of the memory port. When access is 1511 * granted, SEERDY will go high. We use a 1 second 1512 * timeout which should be near 1 second more than 1513 * is needed. Reason: after the chip reset, there 1514 * should be no contention. 1515 */ 1516 SEEPROM_OUTB(sd, sd->sd_MS); 1517 wait = 1000; /* 1 second timeout in msec */ 1518 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1519 DELAY(1000); /* delay 1 msec */ 1520 } 1521 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1522 SEEPROM_OUTB(sd, 0); 1523 return (0); 1524 } 1525 return(1); 1526 } 1527 1528 static void 1529 release_seeprom(sd) 1530 struct seeprom_descriptor *sd; 1531 { 1532 /* Release access to the memory port and the serial EEPROM. */ 1533 SEEPROM_OUTB(sd, 0); 1534 } 1535 1536 static void 1537 write_brdctl(ahc, value) 1538 struct ahc_softc *ahc; 1539 u_int8_t value; 1540 { 1541 u_int8_t brdctl; 1542 1543 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1544 brdctl = BRDSTB; 1545 if (ahc->channel == 'B') 1546 brdctl |= BRDCS; 1547 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1548 brdctl = 0; 1549 } else { 1550 brdctl = BRDSTB|BRDCS; 1551 } 1552 ahc_outb(ahc, BRDCTL, brdctl); 1553 DELAY(20); 1554 brdctl |= value; 1555 ahc_outb(ahc, BRDCTL, brdctl); 1556 DELAY(20); 1557 if ((ahc->features & AHC_ULTRA2) != 0) 1558 brdctl |= BRDSTB_ULTRA2; 1559 else 1560 brdctl &= ~BRDSTB; 1561 ahc_outb(ahc, BRDCTL, brdctl); 1562 DELAY(20); 1563 if ((ahc->features & AHC_ULTRA2) != 0) 1564 brdctl = 0; 1565 else 1566 brdctl &= ~BRDCS; 1567 ahc_outb(ahc, BRDCTL, brdctl); 1568 } 1569 1570 static u_int8_t 1571 read_brdctl(ahc) 1572 struct ahc_softc *ahc; 1573 { 1574 u_int8_t brdctl; 1575 u_int8_t value; 1576 1577 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1578 brdctl = BRDRW; 1579 if (ahc->channel == 'B') 1580 brdctl |= BRDCS; 1581 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1582 brdctl = BRDRW_ULTRA2; 1583 } else { 1584 brdctl = BRDRW|BRDCS; 1585 } 1586 ahc_outb(ahc, BRDCTL, brdctl); 1587 DELAY(20); 1588 value = ahc_inb(ahc, BRDCTL); 1589 ahc_outb(ahc, BRDCTL, 0); 1590 return (value); 1591 } 1592 1593 #define DPE 0x80 1594 #define SSE 0x40 1595 #define RMA 0x20 1596 #define RTA 0x10 1597 #define STA 0x08 1598 #define DPR 0x01 1599 1600 void 1601 ahc_pci_intr(struct ahc_softc *ahc) 1602 { 1603 u_int8_t status1; 1604 1605 status1 = pci_read_config(ahc->device, PCIR_STATUS + 1, /*bytes*/1); 1606 1607 if (status1 & DPE) { 1608 printf("%s: Data Parity Error Detected during address " 1609 "or write data phase\n", ahc_name(ahc)); 1610 } 1611 if (status1 & SSE) { 1612 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1613 } 1614 if (status1 & RMA) { 1615 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1616 } 1617 if (status1 & RTA) { 1618 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1619 } 1620 if (status1 & STA) { 1621 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1622 } 1623 if (status1 & DPR) { 1624 printf("%s: Data Parity Error has been reported via PERR#\n", 1625 ahc_name(ahc)); 1626 } 1627 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1628 printf("%s: Latched PCIERR interrupt with " 1629 "no status bits set\n", ahc_name(ahc)); 1630 } 1631 pci_write_config(ahc->device, PCIR_STATUS + 1, status1, /*bytes*/1); 1632 1633 if (status1 & (DPR|RMA|RTA)) { 1634 ahc_outb(ahc, CLRINT, CLRPARERR); 1635 } 1636 } 1637 1638 static int 1639 ahc_aic7850_setup(device_t dev, char *channel, ahc_chip *chip, 1640 ahc_feature *features, ahc_flag *flags) 1641 { 1642 *channel = 'A'; 1643 *chip = AHC_AIC7850; 1644 *features = AHC_AIC7850_FE; 1645 return (0); 1646 } 1647 1648 static int 1649 ahc_aic7855_setup(device_t dev, char *channel, ahc_chip *chip, 1650 ahc_feature *features, ahc_flag *flags) 1651 { 1652 *channel = 'A'; 1653 *chip = AHC_AIC7855; 1654 *features = AHC_AIC7855_FE; 1655 return (0); 1656 } 1657 1658 static int 1659 ahc_aic7859_setup(device_t dev, char *channel, ahc_chip *chip, 1660 ahc_feature *features, ahc_flag *flags) 1661 { 1662 *channel = 'A'; 1663 *chip = AHC_AIC7859; 1664 *features = AHC_AIC7859_FE; 1665 return (0); 1666 } 1667 1668 static int 1669 ahc_aic7860_setup(device_t dev, char *channel, ahc_chip *chip, 1670 ahc_feature *features, ahc_flag *flags) 1671 { 1672 *channel = 'A'; 1673 *chip = AHC_AIC7860; 1674 *features = AHC_AIC7860_FE; 1675 return (0); 1676 } 1677 1678 static int 1679 ahc_aic7870_setup(device_t dev, char *channel, ahc_chip *chip, 1680 ahc_feature *features, ahc_flag *flags) 1681 { 1682 *channel = 'A'; 1683 *chip = AHC_AIC7870; 1684 *features = AHC_AIC7870_FE; 1685 return (0); 1686 } 1687 1688 static int 1689 ahc_aha394X_setup(device_t dev, char *channel, ahc_chip *chip, 1690 ahc_feature *features, ahc_flag *flags) 1691 { 1692 int error; 1693 1694 error = ahc_aic7870_setup(dev, channel, chip, features, flags); 1695 if (error == 0) 1696 error = ahc_aha394XX_setup(dev, channel, chip, features, flags); 1697 return (error); 1698 } 1699 1700 static int 1701 ahc_aha398X_setup(device_t dev, char *channel, ahc_chip *chip, 1702 ahc_feature *features, ahc_flag *flags) 1703 { 1704 int error; 1705 1706 error = ahc_aic7870_setup(dev, channel, chip, features, flags); 1707 if (error == 0) 1708 error = ahc_aha398XX_setup(dev, channel, chip, features, flags); 1709 return (error); 1710 } 1711 1712 static int 1713 ahc_aic7880_setup(device_t dev, char *channel, ahc_chip *chip, 1714 ahc_feature *features, ahc_flag *flags) 1715 { 1716 *channel = 'A'; 1717 *chip = AHC_AIC7880; 1718 *features = AHC_AIC7880_FE; 1719 return (0); 1720 } 1721 1722 static int 1723 ahc_2940Pro_setup(device_t dev, char *channel, ahc_chip *chip, 1724 ahc_feature *features, ahc_flag *flags) 1725 { 1726 int error; 1727 1728 *flags |= AHC_INT50_SPEEDFLEX; 1729 error = ahc_aic7880_setup(dev, channel, chip, features, flags); 1730 return (0); 1731 } 1732 1733 static int 1734 ahc_aha394XU_setup(device_t dev, char *channel, ahc_chip *chip, 1735 ahc_feature *features, ahc_flag *flags) 1736 { 1737 int error; 1738 1739 error = ahc_aic7880_setup(dev, channel, chip, features, flags); 1740 if (error == 0) 1741 error = ahc_aha394XX_setup(dev, channel, chip, features, flags); 1742 return (error); 1743 } 1744 1745 static int 1746 ahc_aha398XU_setup(device_t dev, char *channel, ahc_chip *chip, 1747 ahc_feature *features, ahc_flag *flags) 1748 { 1749 int error; 1750 1751 error = ahc_aic7880_setup(dev, channel, chip, features, flags); 1752 if (error == 0) 1753 error = ahc_aha398XX_setup(dev, channel, chip, features, flags); 1754 return (error); 1755 } 1756 1757 static int 1758 ahc_aic7890_setup(device_t dev, char *channel, ahc_chip *chip, 1759 ahc_feature *features, ahc_flag *flags) 1760 { 1761 *channel = 'A'; 1762 *chip = AHC_AIC7890; 1763 *features = AHC_AIC7890_FE; 1764 *flags |= AHC_NEWEEPROM_FMT; 1765 return (0); 1766 } 1767 1768 static int 1769 ahc_aic7892_setup(device_t dev, char *channel, ahc_chip *chip, 1770 ahc_feature *features, ahc_flag *flags) 1771 { 1772 *channel = 'A'; 1773 *chip = AHC_AIC7892; 1774 *features = AHC_AIC7892_FE; 1775 *flags |= AHC_NEWEEPROM_FMT; 1776 return (0); 1777 } 1778 1779 static int 1780 ahc_aic7895_setup(device_t dev, char *channel, ahc_chip *chip, 1781 ahc_feature *features, ahc_flag *flags) 1782 { 1783 u_int32_t devconfig; 1784 1785 *channel = pci_get_function(dev) == 1 ? 'B' : 'A'; 1786 *chip = AHC_AIC7895; 1787 /* The 'C' revision of the aic7895 has a few additional features */ 1788 if (pci_get_revid(dev) >= 4) 1789 *features = AHC_AIC7895C_FE; 1790 else 1791 *features = AHC_AIC7895_FE; 1792 *flags |= AHC_NEWEEPROM_FMT; 1793 devconfig = pci_read_config(dev, DEVCONFIG, /*bytes*/4); 1794 devconfig &= ~SCBSIZE32; 1795 pci_write_config(dev, DEVCONFIG, devconfig, /*bytes*/4); 1796 return (0); 1797 } 1798 1799 static int 1800 ahc_aic7896_setup(device_t dev, char *channel, ahc_chip *chip, 1801 ahc_feature *features, ahc_flag *flags) 1802 { 1803 *channel = pci_get_function(dev) == 1 ? 'B' : 'A'; 1804 *chip = AHC_AIC7896; 1805 *features = AHC_AIC7896_FE; 1806 *flags |= AHC_NEWEEPROM_FMT; 1807 return (0); 1808 } 1809 1810 static int 1811 ahc_aic7899_setup(device_t dev, char *channel, ahc_chip *chip, 1812 ahc_feature *features, ahc_flag *flags) 1813 { 1814 *channel = pci_get_function(dev) == 1 ? 'B' : 'A'; 1815 *chip = AHC_AIC7899; 1816 *features = AHC_AIC7899_FE; 1817 *flags |= AHC_NEWEEPROM_FMT; 1818 return (0); 1819 } 1820 1821 static int 1822 ahc_raid_setup(device_t dev, char *channel, ahc_chip *chip, 1823 ahc_feature *features, ahc_flag *flags) 1824 { 1825 printf("RAID functionality unsupported\n"); 1826 return (ENXIO); 1827 } 1828 1829 static int 1830 ahc_aha394XX_setup(device_t dev, char *channel, ahc_chip *chip, 1831 ahc_feature *features, ahc_flag *flags) 1832 { 1833 switch (pci_get_slot(dev)) { 1834 case AHC_394X_SLOT_CHANNEL_A: 1835 *channel = 'A'; 1836 break; 1837 case AHC_394X_SLOT_CHANNEL_B: 1838 *channel = 'B'; 1839 break; 1840 default: 1841 printf("adapter at unexpected slot %d\n" 1842 "unable to map to a channel\n", 1843 pci_get_slot(dev)); 1844 *channel = 'A'; 1845 } 1846 return (0); 1847 } 1848 1849 static int 1850 ahc_aha398XX_setup(device_t dev, char *channel, ahc_chip *chip, 1851 ahc_feature *features, ahc_flag *flags) 1852 { 1853 switch (pci_get_slot(dev)) { 1854 case AHC_398X_SLOT_CHANNEL_A: 1855 *channel = 'A'; 1856 break; 1857 case AHC_398X_SLOT_CHANNEL_B: 1858 *channel = 'B'; 1859 break; 1860 case AHC_398X_SLOT_CHANNEL_C: 1861 *channel = 'C'; 1862 break; 1863 default: 1864 printf("adapter at unexpected slot %d\n" 1865 "unable to map to a channel\n", 1866 pci_get_slot(dev)); 1867 *channel = 'A'; 1868 } 1869 *flags |= AHC_LARGE_SEEPROM; 1870 return (0); 1871 } 1872