1 /* 2 * FreeBSD, PCI product support functions 3 * 4 * Copyright (c) 1995-2001 Justin T. Gibbs 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * Alternatively, this software may be distributed under the terms of the 17 * GNU Public License ("GPL"). 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $Id$ 32 * 33 * $FreeBSD$ 34 */ 35 36 #include <dev/aic7xxx/aic7xxx_osm.h> 37 38 #define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ 39 #define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 40 41 static int ahc_pci_probe(device_t dev); 42 static int ahc_pci_attach(device_t dev); 43 44 static device_method_t ahc_pci_device_methods[] = { 45 /* Device interface */ 46 DEVMETHOD(device_probe, ahc_pci_probe), 47 DEVMETHOD(device_attach, ahc_pci_attach), 48 DEVMETHOD(device_detach, ahc_detach), 49 { 0, 0 } 50 }; 51 52 static driver_t ahc_pci_driver = { 53 "ahc_pci", 54 ahc_pci_device_methods, 55 sizeof(struct ahc_softc) 56 }; 57 58 static devclass_t ahc_pci_devclass; 59 60 DRIVER_MODULE(ahc_pci, pci, ahc_pci_driver, ahc_pci_devclass, 0, 0); 61 DRIVER_MODULE(ahc_pci, cardbus, ahc_pci_driver, ahc_pci_devclass, 0, 0); 62 MODULE_DEPEND(ahc_pci, ahc, 1, 1, 1); 63 MODULE_VERSION(ahc_pci, 1); 64 65 static int 66 ahc_pci_probe(device_t dev) 67 { 68 struct ahc_pci_identity *entry; 69 70 entry = ahc_find_pci_device(dev); 71 if (entry != NULL) { 72 device_set_desc(dev, entry->name); 73 return (0); 74 } 75 return (ENXIO); 76 } 77 78 static int 79 ahc_pci_attach(device_t dev) 80 { 81 struct ahc_pci_identity *entry; 82 struct ahc_softc *ahc; 83 char *name; 84 int error; 85 86 entry = ahc_find_pci_device(dev); 87 if (entry == NULL) 88 return (ENXIO); 89 90 /* 91 * Allocate a softc for this card and 92 * set it up for attachment by our 93 * common detect routine. 94 */ 95 name = malloc(strlen(device_get_nameunit(dev)) + 1, M_DEVBUF, M_NOWAIT); 96 if (name == NULL) 97 return (ENOMEM); 98 strcpy(name, device_get_nameunit(dev)); 99 ahc = ahc_alloc(dev, name); 100 if (ahc == NULL) 101 return (ENOMEM); 102 103 ahc_set_unit(ahc, device_get_unit(dev)); 104 105 /* 106 * Should we bother disabling 39Bit addressing 107 * based on installed memory? 108 */ 109 if (sizeof(bus_addr_t) > 4) 110 ahc->flags |= AHC_39BIT_ADDRESSING; 111 112 /* Allocate a dmatag for our SCB DMA maps */ 113 /* XXX Should be a child of the PCI bus dma tag */ 114 error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1, 115 /*boundary*/0, 116 (ahc->flags & AHC_39BIT_ADDRESSING) 117 ? 0x7FFFFFFFFF 118 : BUS_SPACE_MAXADDR_32BIT, 119 /*highaddr*/BUS_SPACE_MAXADDR, 120 /*filter*/NULL, /*filterarg*/NULL, 121 /*maxsize*/MAXBSIZE, /*nsegments*/AHC_NSEG, 122 /*maxsegsz*/AHC_MAXTRANSFER_SIZE, 123 /*flags*/BUS_DMA_ALLOCNOW, 124 &ahc->parent_dmat); 125 126 if (error != 0) { 127 printf("ahc_pci_attach: Could not allocate DMA tag " 128 "- error %d\n", error); 129 ahc_free(ahc); 130 return (ENOMEM); 131 } 132 ahc->dev_softc = dev; 133 error = ahc_pci_config(ahc, entry); 134 if (error != 0) { 135 ahc_free(ahc); 136 return (error); 137 } 138 139 ahc_attach(ahc); 140 return (0); 141 } 142 143 int 144 ahc_pci_map_registers(struct ahc_softc *ahc) 145 { 146 struct resource *regs; 147 u_int command; 148 int regs_type; 149 int regs_id; 150 151 command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1); 152 regs = NULL; 153 regs_type = 0; 154 regs_id = 0; 155 #ifdef AHC_ALLOW_MEMIO 156 if ((command & PCIM_CMD_MEMEN) != 0) { 157 158 regs_type = SYS_RES_MEMORY; 159 regs_id = AHC_PCI_MEMADDR; 160 regs = bus_alloc_resource(ahc->dev_softc, regs_type, 161 ®s_id, 0, ~0, 1, RF_ACTIVE); 162 if (regs != NULL) { 163 ahc->tag = rman_get_bustag(regs); 164 ahc->bsh = rman_get_bushandle(regs); 165 166 /* 167 * Do a quick test to see if memory mapped 168 * I/O is functioning correctly. 169 */ 170 if (ahc_inb(ahc, HCNTRL) == 0xFF) { 171 device_printf(ahc->dev_softc, 172 "PCI Device %d:%d:%d failed memory " 173 "mapped test. Using PIO.\n", 174 ahc_get_pci_bus(ahc->dev_softc), 175 ahc_get_pci_slot(ahc->dev_softc), 176 ahc_get_pci_function(ahc->dev_softc)); 177 bus_release_resource(ahc->dev_softc, regs_type, 178 regs_id, regs); 179 regs = NULL; 180 } else { 181 command &= ~PCIM_CMD_PORTEN; 182 ahc_pci_write_config(ahc->dev_softc, 183 PCIR_COMMAND, 184 command, /*bytes*/1); 185 } 186 } 187 } 188 #endif 189 if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) { 190 regs_type = SYS_RES_IOPORT; 191 regs_id = AHC_PCI_IOADDR; 192 regs = bus_alloc_resource(ahc->dev_softc, regs_type, 193 ®s_id, 0, ~0, 1, RF_ACTIVE); 194 if (regs != NULL) { 195 ahc->tag = rman_get_bustag(regs); 196 ahc->bsh = rman_get_bushandle(regs); 197 command &= ~PCIM_CMD_MEMEN; 198 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, 199 command, /*bytes*/1); 200 } 201 } 202 if (regs == NULL) { 203 device_printf(ahc->dev_softc, 204 "can't allocate register resources\n"); 205 return (ENOMEM); 206 } 207 ahc->platform_data->regs_res_type = regs_type; 208 ahc->platform_data->regs_res_id = regs_id; 209 ahc->platform_data->regs = regs; 210 return (0); 211 } 212 213 int 214 ahc_pci_map_int(struct ahc_softc *ahc) 215 { 216 int zero; 217 218 zero = 0; 219 ahc->platform_data->irq = 220 bus_alloc_resource(ahc->dev_softc, SYS_RES_IRQ, &zero, 221 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 222 if (ahc->platform_data->irq == NULL) 223 return (ENOMEM); 224 ahc->platform_data->irq_res_type = SYS_RES_IRQ; 225 return (ahc_map_int(ahc)); 226 } 227 228 void 229 ahc_power_state_change(struct ahc_softc *ahc, ahc_power_state new_state) 230 { 231 uint32_t cap; 232 u_int cap_offset; 233 234 /* 235 * Traverse the capability list looking for 236 * the power management capability. 237 */ 238 cap = 0; 239 cap_offset = ahc_pci_read_config(ahc->dev_softc, 240 PCIR_CAP_PTR, /*bytes*/1); 241 while (cap_offset != 0) { 242 243 cap = ahc_pci_read_config(ahc->dev_softc, 244 cap_offset, /*bytes*/4); 245 if ((cap & 0xFF) == 1 246 && ((cap >> 16) & 0x3) > 0) { 247 uint32_t pm_control; 248 249 pm_control = ahc_pci_read_config(ahc->dev_softc, 250 cap_offset + 4, 251 /*bytes*/2); 252 pm_control &= ~0x3; 253 pm_control |= new_state; 254 ahc_pci_write_config(ahc->dev_softc, 255 cap_offset + 4, 256 pm_control, /*bytes*/2); 257 break; 258 } 259 cap_offset = (cap >> 8) & 0xFF; 260 } 261 } 262