1 /* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1995, 1996, 1997, 1998 Justin T. Gibbs 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Where this Software is combined with software released under the terms of 19 * the GNU Public License ("GPL") and the terms of the GPL would require the 20 * combined work to also be released under the terms of the GPL, the terms 21 * and conditions of this License will apply in addition to those of the 22 * GPL with the exception of any terms or conditions of this License that 23 * conflict with, or are expressly prohibited by, the GPL. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $Id$ 38 */ 39 40 #include <pci.h> 41 #if NPCI > 0 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/queue.h> 46 47 #include <pci/pcireg.h> 48 #include <pci/pcivar.h> 49 50 #include <machine/bus_memio.h> 51 #include <machine/bus_pio.h> 52 #include <machine/bus.h> 53 #include <machine/clock.h> 54 55 #include <cam/cam.h> 56 #include <cam/cam_ccb.h> 57 #include <cam/cam_sim.h> 58 59 #include <cam/scsi/scsi_all.h> 60 61 #include <dev/aic7xxx/aic7xxx.h> 62 #include <dev/aic7xxx/93cx6.h> 63 64 #include <aic7xxx_reg.h> 65 66 #define PCI_BASEADR0 PCI_MAP_REG_START /* I/O Address */ 67 #define PCI_BASEADR1 PCI_MAP_REG_START + 4 /* Mem I/O Address */ 68 69 #define PCI_DEVICE_ID_ADAPTEC_398XU 0x83789004ul 70 #define PCI_DEVICE_ID_ADAPTEC_3940U 0x82789004ul 71 #define PCI_DEVICE_ID_ADAPTEC_2944U 0x84789004ul 72 #define PCI_DEVICE_ID_ADAPTEC_2940U 0x81789004ul 73 #define PCI_DEVICE_ID_ADAPTEC_2940AU 0x61789004ul 74 #define PCI_DEVICE_ID_ADAPTEC_2940U2 0x00109005ul 75 #define PCI_DEVICE_ID_ADAPTEC_398X 0x73789004ul 76 #define PCI_DEVICE_ID_ADAPTEC_3940 0x72789004ul 77 #define PCI_DEVICE_ID_ADAPTEC_2944 0x74789004ul 78 #define PCI_DEVICE_ID_ADAPTEC_2940 0x71789004ul 79 #define PCI_DEVICE_ID_ADAPTEC_AIC7890 0x001F9005ul 80 #define PCI_DEVICE_ID_ADAPTEC_AIC7895 0x78959004ul 81 #define PCI_DEVICE_ID_ADAPTEC_AIC7896 0x005F9005ul 82 #define PCI_DEVICE_ID_ADAPTEC_AIC7880 0x80789004ul 83 #define PCI_DEVICE_ID_ADAPTEC_AIC7870 0x70789004ul 84 #define PCI_DEVICE_ID_ADAPTEC_AIC7860 0x60789004ul 85 #define PCI_DEVICE_ID_ADAPTEC_AIC7855 0x55789004ul 86 #define PCI_DEVICE_ID_ADAPTEC_AIC7850 0x50789004ul 87 #define PCI_DEVICE_ID_ADAPTEC_AIC7810 0x10789004ul 88 89 #define AHC_394X_SLOT_CHANNEL_A 4 90 #define AHC_394X_SLOT_CHANNEL_B 5 91 92 #define AHC_398X_SLOT_CHANNEL_A 4 93 #define AHC_398X_SLOT_CHANNEL_B 8 94 #define AHC_398X_SLOT_CHANNEL_C 12 95 96 #define DEVCONFIG 0x40 97 #define SCBSIZE32 0x00010000ul /* aic789X only */ 98 #define MPORTMODE 0x00000400ul /* aic7870 only */ 99 #define RAMPSM 0x00000200ul /* aic7870 only */ 100 #define VOLSENSE 0x00000100ul 101 #define SCBRAMSEL 0x00000080ul 102 #define MRDCEN 0x00000040ul 103 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 104 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 105 #define BERREN 0x00000008ul 106 #define DACEN 0x00000004ul 107 #define STPWLEVEL 0x00000002ul 108 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 109 110 #define CSIZE_LATTIME 0x0c 111 #define CACHESIZE 0x0000003ful /* only 5 bits */ 112 #define LATTIME 0x0000ff00ul 113 114 static void check_extport(struct ahc_softc *ahc, u_int8_t *sxfrctl1); 115 static void configure_termination(struct ahc_softc *ahc, 116 struct seeprom_config *sc, 117 struct seeprom_descriptor *sd, 118 u_int8_t *sxfrctl1); 119 120 static void ahc_ultra2_term_detect(struct ahc_softc *ahc, 121 int *enableSEC_low, 122 int *enableSEC_high, 123 int *enablePRI_low, 124 int *enablePRI_high, 125 int *eeprom_present); 126 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 127 int *internal68_present, 128 int *externalcable_present, 129 int *eeprom_present); 130 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 131 int *externalcable_present, 132 int *eeprom_present); 133 static int acquire_seeprom(struct ahc_softc *ahc, 134 struct seeprom_descriptor *sd); 135 static void release_seeprom(struct seeprom_descriptor *sd); 136 static void write_brdctl(struct ahc_softc *ahc, u_int8_t value); 137 static u_int8_t read_brdctl(struct ahc_softc *ahc); 138 139 static struct ahc_softc *first_398X; 140 141 static char* ahc_pci_probe(pcici_t tag, pcidi_t type); 142 static void ahc_pci_attach(pcici_t config_id, int unit); 143 144 /* Exported for use in the ahc_intr routine */ 145 void ahc_pci_intr(struct ahc_softc *ahc); 146 147 static struct pci_device ahc_pci_driver = { 148 "ahc", 149 ahc_pci_probe, 150 ahc_pci_attach, 151 &ahc_unit, 152 NULL 153 }; 154 155 DATA_SET (pcidevice_set, ahc_pci_driver); 156 157 static char* 158 ahc_pci_probe (pcici_t tag, pcidi_t type) 159 { 160 switch (type) { 161 case PCI_DEVICE_ID_ADAPTEC_398XU: 162 return ("Adaptec 398X Ultra SCSI RAID adapter"); 163 break; 164 case PCI_DEVICE_ID_ADAPTEC_3940U: 165 return ("Adaptec 3940 Ultra SCSI host adapter"); 166 break; 167 case PCI_DEVICE_ID_ADAPTEC_398X: 168 return ("Adaptec 398X SCSI RAID adapter"); 169 break; 170 case PCI_DEVICE_ID_ADAPTEC_3940: 171 return ("Adaptec 3940 SCSI adapter"); 172 break; 173 case PCI_DEVICE_ID_ADAPTEC_2944U: 174 return ("Adaptec 2944 Ultra SCSI adapter"); 175 break; 176 case PCI_DEVICE_ID_ADAPTEC_2940U: 177 return ("Adaptec 2940 Ultra SCSI adapter"); 178 break; 179 case PCI_DEVICE_ID_ADAPTEC_2940U2: 180 return ("Adaptec 2940 Ultra2 SCSI adapter"); 181 break; 182 case PCI_DEVICE_ID_ADAPTEC_2944: 183 return ("Adaptec 2944 SCSI adapter"); 184 break; 185 case PCI_DEVICE_ID_ADAPTEC_2940: 186 return ("Adaptec 2940 SCSI adapter"); 187 break; 188 case PCI_DEVICE_ID_ADAPTEC_2940AU: 189 return ("Adaptec 2940A Ultra SCSI adapter"); 190 break; 191 case PCI_DEVICE_ID_ADAPTEC_AIC7895: 192 return ("Adaptec aic7895 Ultra SCSI adapter"); 193 break; 194 case PCI_DEVICE_ID_ADAPTEC_AIC7890: 195 return ("Adaptec aic7890/91 Ultra2 SCSI adapter"); 196 break; 197 case PCI_DEVICE_ID_ADAPTEC_AIC7896: 198 return ("Adaptec aic7896/97 Ultra2 SCSI adapter"); 199 break; 200 case PCI_DEVICE_ID_ADAPTEC_AIC7880: 201 return ("Adaptec aic7880 Ultra SCSI adapter"); 202 break; 203 case PCI_DEVICE_ID_ADAPTEC_AIC7870: 204 return ("Adaptec aic7870 SCSI adapter"); 205 break; 206 case PCI_DEVICE_ID_ADAPTEC_AIC7860: 207 return ("Adaptec aic7860 SCSI adapter"); 208 break; 209 case PCI_DEVICE_ID_ADAPTEC_AIC7855: 210 return ("Adaptec aic7855 SCSI adapter"); 211 break; 212 case PCI_DEVICE_ID_ADAPTEC_AIC7850: 213 return ("Adaptec aic7850 SCSI adapter"); 214 break; 215 case PCI_DEVICE_ID_ADAPTEC_AIC7810: 216 return ("Adaptec aic7810 RAID memory controller"); 217 break; 218 default: 219 break; 220 } 221 return (0); 222 223 } 224 225 static void 226 ahc_pci_attach(pcici_t config_id, int unit) 227 { 228 u_int16_t io_port; 229 struct ahc_softc *ahc; 230 u_int32_t id; 231 u_int32_t command; 232 struct scb_data *shared_scb_data; 233 int opri; 234 ahc_chip ahc_t = AHC_NONE; 235 ahc_feature ahc_fe = AHC_FENONE; 236 ahc_flag ahc_f = AHC_FNONE; 237 vm_offset_t vaddr; 238 vm_offset_t paddr; 239 u_int8_t our_id = 0; 240 u_int8_t sxfrctl1; 241 u_int8_t scsiseq; 242 int error; 243 char channel; 244 245 if (config_id->func == 1) 246 channel = 'B'; 247 else 248 channel = 'A'; 249 shared_scb_data = NULL; 250 vaddr = NULL; 251 paddr = NULL; 252 io_port = 0; 253 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 254 #ifdef AHC_ALLOW_MEMIO 255 if ((command & PCI_COMMAND_MEM_ENABLE) == 0 256 || (pci_map_mem(config_id, PCI_BASEADR1, &vaddr, &paddr)) == 0) 257 #endif 258 if ((command & PCI_COMMAND_IO_ENABLE) == 0 259 || (pci_map_port(config_id, PCI_BASEADR0, &io_port)) == 0) 260 return; 261 262 switch ((id = pci_conf_read(config_id, PCI_ID_REG))) { 263 case PCI_DEVICE_ID_ADAPTEC_398XU: 264 case PCI_DEVICE_ID_ADAPTEC_398X: 265 if (id == PCI_DEVICE_ID_ADAPTEC_398XU) { 266 ahc_t = AHC_AIC7880; 267 ahc_fe = AHC_AIC7880_FE; 268 } else { 269 ahc_t = AHC_AIC7870; 270 ahc_fe = AHC_AIC7870_FE; 271 } 272 273 switch (config_id->slot) { 274 case AHC_398X_SLOT_CHANNEL_A: 275 break; 276 case AHC_398X_SLOT_CHANNEL_B: 277 channel = 'B'; 278 break; 279 case AHC_398X_SLOT_CHANNEL_C: 280 channel = 'C'; 281 break; 282 default: 283 printf("adapter at unexpected slot %d\n" 284 "unable to map to a channel\n", 285 config_id->slot); 286 } 287 ahc_f |= AHC_LARGE_SEEPROM; 288 break; 289 case PCI_DEVICE_ID_ADAPTEC_3940U: 290 case PCI_DEVICE_ID_ADAPTEC_3940: 291 if (id == PCI_DEVICE_ID_ADAPTEC_3940U) { 292 ahc_t = AHC_AIC7880; 293 ahc_fe = AHC_AIC7880_FE; 294 } else { 295 ahc_t = AHC_AIC7870; 296 ahc_fe = AHC_AIC7870_FE; 297 } 298 299 switch (config_id->slot) { 300 case AHC_394X_SLOT_CHANNEL_A: 301 break; 302 case AHC_394X_SLOT_CHANNEL_B: 303 channel = 'B'; 304 break; 305 default: 306 printf("adapter at unexpected slot %d\n" 307 "unable to map to a channel\n", 308 config_id->slot); 309 } 310 break; 311 case PCI_DEVICE_ID_ADAPTEC_AIC7890: 312 case PCI_DEVICE_ID_ADAPTEC_2940U2: 313 { 314 ahc_t = AHC_AIC7890; 315 ahc_fe = AHC_AIC7890_FE; 316 break; 317 } 318 case PCI_DEVICE_ID_ADAPTEC_AIC7896: 319 { 320 ahc_t = AHC_AIC7896; 321 ahc_fe = AHC_AIC7896_FE; 322 break; 323 } 324 case PCI_DEVICE_ID_ADAPTEC_2944U: 325 case PCI_DEVICE_ID_ADAPTEC_2940U: 326 case PCI_DEVICE_ID_ADAPTEC_AIC7880: 327 ahc_t = AHC_AIC7880; 328 ahc_fe = AHC_AIC7880_FE; 329 break; 330 case PCI_DEVICE_ID_ADAPTEC_2944: 331 case PCI_DEVICE_ID_ADAPTEC_2940: 332 case PCI_DEVICE_ID_ADAPTEC_AIC7870: 333 ahc_t = AHC_AIC7870; 334 ahc_fe = AHC_AIC7870_FE; 335 break; 336 case PCI_DEVICE_ID_ADAPTEC_2940AU: 337 case PCI_DEVICE_ID_ADAPTEC_AIC7860: 338 ahc_fe = AHC_AIC7860_FE; 339 ahc_t = AHC_AIC7860; 340 break; 341 case PCI_DEVICE_ID_ADAPTEC_AIC7895: 342 { 343 u_int32_t devconfig; 344 345 ahc_t = AHC_AIC7895; 346 ahc_fe = AHC_AIC7895_FE; 347 devconfig = pci_conf_read(config_id, DEVCONFIG); 348 devconfig &= ~SCBSIZE32; 349 pci_conf_write(config_id, DEVCONFIG, devconfig); 350 break; 351 } 352 case PCI_DEVICE_ID_ADAPTEC_AIC7855: 353 case PCI_DEVICE_ID_ADAPTEC_AIC7850: 354 ahc_t = AHC_AIC7850; 355 ahc_fe = AHC_AIC7850_FE; 356 break; 357 case PCI_DEVICE_ID_ADAPTEC_AIC7810: 358 printf("RAID functionality unsupported\n"); 359 return; 360 default: 361 break; 362 } 363 364 /* On all PCI adapters, we allow SCB paging */ 365 ahc_f |= AHC_PAGESCBS; 366 if ((ahc = ahc_alloc(unit, io_port, vaddr, ahc_t|AHC_PCI, ahc_fe, ahc_f, 367 shared_scb_data)) == NULL) 368 return; /* XXX PCI code should take return status */ 369 370 ahc->channel = channel; 371 372 /* Allocate a dmatag for our SCB DMA maps */ 373 /* XXX Should be a child of the PCI bus dma tag */ 374 error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/0, 375 /*boundary*/0, 376 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 377 /*highaddr*/BUS_SPACE_MAXADDR, 378 /*filter*/NULL, /*filterarg*/NULL, 379 /*maxsize*/MAXBSIZE, /*nsegments*/AHC_NSEG, 380 /*maxsegsz*/AHC_MAXTRANSFER_SIZE, 381 /*flags*/BUS_DMA_ALLOCNOW, &ahc->dmat); 382 383 if (error != 0) { 384 printf("%s: Could not allocate DMA tag - error %d\n", 385 ahc_name(ahc), error); 386 ahc_free(ahc); 387 return; 388 } 389 390 391 /* Store our PCI bus information for use in our PCI error handler */ 392 ahc->pci_config_id = config_id; 393 394 /* Remeber how the card was setup in case there is no SEEPROM */ 395 ahc_outb(ahc, HCNTRL, ahc->pause); 396 if ((ahc->features & AHC_ULTRA2) != 0) 397 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 398 else 399 our_id = ahc_inb(ahc, SCSIID) & OID; 400 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 401 scsiseq = ahc_inb(ahc, SCSISEQ); 402 403 if (ahc_reset(ahc) != 0) { 404 /* Failed */ 405 ahc_free(ahc); 406 return; 407 } 408 409 /* 410 * Take a look to see if we have external SRAM. 411 * We currently do not attempt to use SRAM that is 412 * shared among multiple controllers. 413 */ 414 if ((ahc->features & AHC_ULTRA2) != 0) { 415 u_int dscommand0; 416 417 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 418 if ((dscommand0 & RAMPS) != 0) { 419 u_int32_t devconfig; 420 421 devconfig = pci_conf_read(config_id, DEVCONFIG); 422 if ((devconfig & MPORTMODE) != 0) { 423 /* Single user mode */ 424 425 /* 426 * XXX Assume 9bit SRAM and enable 427 * parity checking 428 */ 429 devconfig |= EXTSCBPEN; 430 pci_conf_write(config_id, DEVCONFIG, devconfig); 431 432 /* 433 * Set the bank select apropriately. 434 */ 435 if (ahc->channel == 'B') 436 ahc_outb(ahc, SCBBADDR, 1); 437 else 438 ahc_outb(ahc, SCBBADDR, 0); 439 440 /* Select external SCB SRAM */ 441 dscommand0 &= ~INTSCBRAMSEL; 442 ahc_outb(ahc, DSCOMMAND0, dscommand0); 443 444 if (ahc_probe_scbs(ahc) == 0) { 445 /* External ram isn't really there */ 446 dscommand0 |= INTSCBRAMSEL; 447 ahc_outb(ahc, DSCOMMAND0, dscommand0); 448 } else if (bootverbose) 449 printf("%s: External SRAM bank%d\n", 450 ahc_name(ahc), 451 ahc->channel == 'B' ? 1 : 0); 452 } 453 454 } 455 } else if ((ahc->chip & AHC_CHIPID_MASK) >= AHC_AIC7870) { 456 u_int32_t devconfig = pci_conf_read(config_id, DEVCONFIG); 457 if ((devconfig & RAMPSM) != 0 458 && (devconfig & MPORTMODE) != 0) { 459 460 /* XXX Assume 9bit SRAM and enable parity checking */ 461 devconfig |= EXTSCBPEN; 462 463 /* XXX Assume fast SRAM */ 464 devconfig &= ~EXTSCBTIME; 465 466 /* 467 * Set the bank select apropriately. 468 */ 469 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 470 if (ahc->channel == 'B') 471 ahc_outb(ahc, SCBBADDR, 1); 472 else 473 ahc_outb(ahc, SCBBADDR, 0); 474 } 475 476 /* Select external SRAM */ 477 devconfig &= ~SCBRAMSEL; 478 pci_conf_write(config_id, DEVCONFIG, devconfig); 479 480 if (ahc_probe_scbs(ahc) == 0) { 481 /* External ram isn't really there */ 482 devconfig |= SCBRAMSEL; 483 pci_conf_write(config_id, DEVCONFIG, devconfig); 484 } else if (bootverbose) 485 printf("%s: External SRAM bank%d\n", 486 ahc_name(ahc), 487 ahc->channel == 'B' ? 1 : 0); 488 } 489 } 490 491 if (!(pci_map_int(config_id, ahc_intr, (void *)ahc, &cam_imask))) { 492 ahc_free(ahc); 493 return; 494 } 495 /* 496 * Protect ourself from spurrious interrupts during 497 * intialization. 498 */ 499 opri = splcam(); 500 501 /* 502 * Do aic7880/aic7870/aic7860/aic7850 specific initialization 503 */ 504 { 505 u_int8_t sblkctl; 506 char *id_string; 507 508 switch(ahc_t) { 509 case AHC_AIC7896: 510 { 511 u_int dscommand0; 512 513 id_string = "aic7896/97 "; 514 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 515 dscommand0 &= ~USCBSIZE32; 516 dscommand0 |= CACHETHEN|DPARCKEN|MPARCKEN; 517 ahc_outb(ahc, DSCOMMAND0, dscommand0); 518 break; 519 } 520 case AHC_AIC7890: 521 { 522 u_int dscommand0; 523 524 id_string = "aic7890/91 "; 525 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 526 dscommand0 &= ~USCBSIZE32; 527 dscommand0 |= CACHETHEN|DPARCKEN|MPARCKEN; 528 ahc_outb(ahc, DSCOMMAND0, dscommand0); 529 break; 530 } 531 case AHC_AIC7895: 532 id_string = "aic7895 "; 533 break; 534 case AHC_AIC7880: 535 id_string = "aic7880 "; 536 break; 537 case AHC_AIC7870: 538 id_string = "aic7870 "; 539 break; 540 case AHC_AIC7860: 541 id_string = "aic7860 "; 542 break; 543 case AHC_AIC7850: 544 id_string = "aic7850 "; 545 break; 546 default: 547 printf("ahc: Unknown controller type. Ignoring.\n"); 548 ahc_free(ahc); 549 splx(opri); 550 return; 551 } 552 553 /* See if we have an SEEPROM and perform auto-term */ 554 check_extport(ahc, &sxfrctl1); 555 556 /* 557 * Take the LED out of diagnostic mode 558 */ 559 sblkctl = ahc_inb(ahc, SBLKCTL); 560 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 561 562 /* 563 * I don't know where this is set in the SEEPROM or by the 564 * BIOS, so we default to 100% on Ultra or slower controllers 565 * and 75% on ULTRA2 controllers. 566 */ 567 if ((ahc->features & AHC_ULTRA2) != 0) { 568 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 569 } else { 570 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 571 } 572 573 if (ahc->flags & AHC_USEDEFAULTS) { 574 /* 575 * PCI Adapter default setup 576 * Should only be used if the adapter does not have 577 * an SEEPROM. 578 */ 579 /* See if someone else set us up already */ 580 if (scsiseq != 0) { 581 printf("%s: Using left over BIOS settings\n", 582 ahc_name(ahc)); 583 ahc->flags &= ~AHC_USEDEFAULTS; 584 } else { 585 /* 586 * Assume only one connector and always turn 587 * on termination. 588 */ 589 our_id = 0x07; 590 sxfrctl1 = STPWEN; 591 } 592 ahc_outb(ahc, SCSICONF, 593 (our_id & 0x07)|ENSPCHK|RESET_SCSI); 594 595 ahc->our_id = our_id; 596 } 597 598 printf("%s: %s", ahc_name(ahc), id_string); 599 } 600 601 /* 602 * Record our termination setting for the 603 * generic initialization routine. 604 */ 605 if ((sxfrctl1 & STPWEN) != 0) 606 ahc->flags |= AHC_TERM_ENB_A; 607 608 if (ahc_init(ahc)) { 609 ahc_free(ahc); 610 splx(opri); 611 return; /* XXX PCI code should take return status */ 612 } 613 614 /* XXX Crude hack - fix sometime */ 615 if (ahc->flags & AHC_SHARED_SRAM) { 616 /* Only set this once we've successfully probed */ 617 if (shared_scb_data == NULL) 618 first_398X = ahc; 619 } 620 621 splx(opri); 622 623 ahc_attach(ahc); 624 } 625 626 /* 627 * Check the external port logic for a serial eeprom 628 * and termination/cable detection contrls. 629 */ 630 static void 631 check_extport(struct ahc_softc *ahc, u_int8_t *sxfrctl1) 632 { 633 struct seeprom_descriptor sd; 634 struct seeprom_config sc; 635 u_int8_t scsi_conf; 636 int have_seeprom; 637 638 sd.sd_tag = ahc->tag; 639 sd.sd_bsh = ahc->bsh; 640 sd.sd_control_offset = SEECTL; 641 sd.sd_status_offset = SEECTL; 642 sd.sd_dataout_offset = SEECTL; 643 644 /* 645 * For some multi-channel devices, the c46 is simply too 646 * small to work. For the other controller types, we can 647 * get our information from either SEEPROM type. Set the 648 * type to start our probe with accordingly. 649 */ 650 if (ahc->flags & AHC_LARGE_SEEPROM) 651 sd.sd_chip = C56_66; 652 else 653 sd.sd_chip = C46; 654 655 sd.sd_MS = SEEMS; 656 sd.sd_RDY = SEERDY; 657 sd.sd_CS = SEECS; 658 sd.sd_CK = SEECK; 659 sd.sd_DO = SEEDO; 660 sd.sd_DI = SEEDI; 661 662 have_seeprom = acquire_seeprom(ahc, &sd); 663 664 if (have_seeprom) { 665 666 if (bootverbose) 667 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 668 669 for (;;) { 670 bus_size_t start_addr; 671 672 start_addr = 32 * (ahc->channel - 'A'); 673 674 have_seeprom = read_seeprom(&sd, (u_int16_t *)&sc, 675 start_addr, sizeof(sc)/2); 676 677 if (have_seeprom) { 678 /* Check checksum */ 679 int i; 680 int maxaddr; 681 u_int16_t *scarray; 682 u_int16_t checksum; 683 684 maxaddr = (sizeof(sc)/2) - 1; 685 checksum = 0; 686 scarray = (u_int16_t *)≻ 687 688 for (i = 0; i < maxaddr; i++) 689 checksum = checksum + scarray[i]; 690 if (checksum == 0 || checksum != sc.checksum) { 691 if (bootverbose && sd.sd_chip == C56_66) 692 printf ("checksum error\n"); 693 have_seeprom = 0; 694 } else { 695 if (bootverbose) 696 printf("done.\n"); 697 break; 698 } 699 } 700 701 if (sd.sd_chip == C56_66) 702 break; 703 sd.sd_chip = C56_66; 704 } 705 } 706 707 if (!have_seeprom) { 708 if (bootverbose) 709 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 710 ahc->flags |= AHC_USEDEFAULTS; 711 } else { 712 /* 713 * Put the data we've collected down into SRAM 714 * where ahc_init will find it. 715 */ 716 int i; 717 int max_targ = sc.max_targets & CFMAXTARG; 718 719 if ((sc.adapter_control & CFULTRAEN) != 0) { 720 /* 721 * Determine if this adapter has a "newstyle" 722 * SEEPROM format. 723 */ 724 for (i = 0; i < max_targ; i++) { 725 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0){ 726 ahc->flags |= AHC_NEWEEPROM_FMT; 727 break; 728 } 729 } 730 } 731 732 for (i = 0; i < max_targ; i++) { 733 u_int scsirate; 734 u_int16_t target_mask; 735 736 target_mask = 0x01 << i; 737 if (sc.device_flags[i] & CFDISC) 738 ahc->discenable |= target_mask; 739 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 740 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) 741 ahc->ultraenb |= target_mask; 742 } else if ((sc.adapter_control & CFULTRAEN) != 0) { 743 ahc->ultraenb |= target_mask; 744 } 745 if ((sc.device_flags[i] & CFXFER) == 0x04 746 && (ahc->ultraenb & target_mask) != 0) { 747 /* Treat 10MHz as a non-ultra speed */ 748 sc.device_flags[i] &= ~CFXFER; 749 ahc->ultraenb &= ~target_mask; 750 } 751 if ((ahc->features & AHC_ULTRA2) != 0) { 752 u_int offset; 753 754 if (sc.device_flags[i] & CFSYNCH) 755 offset = MAX_OFFSET_ULTRA2; 756 else 757 offset = 0; 758 ahc_outb(ahc, TARG_OFFSET + i, offset); 759 760 scsirate = (sc.device_flags[i] & CFXFER) 761 | ((ahc->ultraenb & target_mask) 762 ? 0x18 : 0x10); 763 if (sc.device_flags[i] & CFWIDEB) 764 scsirate |= WIDEXFER; 765 } else { 766 scsirate = (sc.device_flags[i] & CFXFER) << 4; 767 if (sc.device_flags[i] & CFSYNCH) 768 scsirate |= SOFS; 769 if (sc.device_flags[i] & CFWIDEB) 770 scsirate |= WIDEXFER; 771 } 772 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 773 } 774 ahc_outb(ahc, DISC_DSB, ~(ahc->discenable & 0xff)); 775 ahc_outb(ahc, DISC_DSB + 1, ~((ahc->discenable >> 8) & 0xff)); 776 ahc_outb(ahc, ULTRA_ENB, ahc->ultraenb & 0xff); 777 ahc_outb(ahc, ULTRA_ENB + 1, (ahc->ultraenb >> 8) & 0xff); 778 779 ahc->our_id = sc.brtime_id & CFSCSIID; 780 781 scsi_conf = (ahc->our_id & 0x7); 782 if (sc.adapter_control & CFSPARITY) 783 scsi_conf |= ENSPCHK; 784 if (sc.adapter_control & CFRESETB) 785 scsi_conf |= RESET_SCSI; 786 787 if (sc.bios_control & CFEXTEND) 788 ahc->flags |= AHC_EXTENDED_TRANS_A; 789 if (ahc->features & AHC_ULTRA 790 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 791 /* Should we enable Ultra mode? */ 792 if (!(sc.adapter_control & CFULTRAEN)) 793 /* Treat us as a non-ultra card */ 794 ahc->ultraenb = 0; 795 } 796 /* Set SCSICONF info */ 797 ahc_outb(ahc, SCSICONF, scsi_conf); 798 } 799 800 if ((ahc->features & AHC_SPIOCAP) != 0) { 801 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0) { 802 configure_termination(ahc, &sc, &sd, sxfrctl1); 803 } 804 } else if (have_seeprom) { 805 configure_termination(ahc, &sc, &sd, sxfrctl1); 806 } 807 808 release_seeprom(&sd); 809 } 810 811 static void 812 configure_termination(struct ahc_softc *ahc, 813 struct seeprom_config *sc, 814 struct seeprom_descriptor *sd, 815 u_int8_t *sxfrctl1) 816 { 817 int max_targ = sc->max_targets & CFMAXTARG; 818 u_int8_t brddat; 819 820 brddat = 0; 821 822 /* 823 * Update the settings in sxfrctl1 to match the 824 *termination settings 825 */ 826 *sxfrctl1 = 0; 827 828 /* 829 * SEECS must be on for the GALS to latch 830 * the data properly. Be sure to leave MS 831 * on or we will release the seeprom. 832 */ 833 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 834 if ((sc->adapter_control & CFAUTOTERM) != 0 835 || (ahc->features & AHC_ULTRA2) != 0) { 836 int internal50_present; 837 int internal68_present; 838 int externalcable_present; 839 int eeprom_present; 840 int enableSEC_low; 841 int enableSEC_high; 842 int enablePRI_low; 843 int enablePRI_high; 844 845 enableSEC_low = 0; 846 enableSEC_high = 0; 847 enablePRI_low = 0; 848 enablePRI_high = 0; 849 if (ahc->features & AHC_ULTRA2) { 850 ahc_ultra2_term_detect(ahc, &enableSEC_low, 851 &enableSEC_high, 852 &enablePRI_low, 853 &enablePRI_high, 854 &eeprom_present); 855 if ((sc->adapter_control & CFSEAUTOTERM) == 0) { 856 enableSEC_low = (sc->adapter_control & CFSTERM); 857 enableSEC_high = 858 (sc->adapter_control & CFWSTERM); 859 } 860 if ((sc->adapter_control & CFAUTOTERM) == 0) { 861 enablePRI_low = enablePRI_high = 862 (sc->adapter_control & CFLVDSTERM); 863 } 864 /* Make the table calculations below happy */ 865 internal50_present = 0; 866 internal68_present = 1; 867 externalcable_present = 1; 868 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 869 aic785X_cable_detect(ahc, &internal50_present, 870 &externalcable_present, 871 &eeprom_present); 872 } else { 873 aic787X_cable_detect(ahc, &internal50_present, 874 &internal68_present, 875 &externalcable_present, 876 &eeprom_present); 877 } 878 879 if (max_targ <= 8) { 880 internal68_present = 0; 881 } 882 883 if (bootverbose) { 884 if ((ahc->features & AHC_ULTRA2) == 0) { 885 printf("%s: internal 50 cable %s present, " 886 "internal 68 cable %s present\n", 887 ahc_name(ahc), 888 internal50_present ? "is":"not", 889 internal68_present ? "is":"not"); 890 891 printf("%s: external cable %s present\n", 892 ahc_name(ahc), 893 externalcable_present ? "is":"not"); 894 } 895 printf("%s: BIOS eeprom %s present\n", 896 ahc_name(ahc), eeprom_present ? "is" : "not"); 897 898 } 899 900 /* 901 * Now set the termination based on what 902 * we found. 903 * Flash Enable = BRDDAT7 904 * Secondary High Term Enable = BRDDAT6 905 * Secondary Low Term Enable = BRDDAT5 (7890) 906 * Primary High Term Enable = BRDDAT4 (7890) 907 */ 908 if ((ahc->features & AHC_ULTRA2) == 0 909 && (internal50_present != 0) 910 && (internal68_present != 0) 911 && (externalcable_present != 0)) { 912 printf("%s: Illegal cable configuration!!. " 913 "Only two connectors on the " 914 "adapter may be used at a " 915 "time!\n", ahc_name(ahc)); 916 } 917 918 if ((max_targ > 8) 919 && ((externalcable_present == 0) 920 || (internal68_present == 0) 921 || (enableSEC_high != 0))) { 922 brddat |= BRDDAT6; 923 if (bootverbose) 924 printf("%s: %sHigh byte termination Enabled\n", 925 ahc_name(ahc), 926 enableSEC_high ? "Secondary " : ""); 927 } 928 929 if (((internal50_present ? 1 : 0) 930 + (internal68_present ? 1 : 0) 931 + (externalcable_present ? 1 : 0)) <= 1 932 || (enableSEC_low != 0)) { 933 if ((ahc->features & AHC_ULTRA2) != 0) 934 brddat |= BRDDAT5; 935 else 936 *sxfrctl1 |= STPWEN; 937 if (bootverbose) 938 printf("%s: %sLow byte termination Enabled\n", 939 ahc_name(ahc), 940 enableSEC_low ? "Secondary " : ""); 941 } 942 943 if (enablePRI_low != 0) { 944 *sxfrctl1 |= STPWEN; 945 if (bootverbose) 946 printf("%s: Primary Low Byte termination " 947 "Enabled\n", ahc_name(ahc)); 948 } 949 950 if (enablePRI_high != 0) { 951 brddat |= BRDDAT4; 952 if (bootverbose) 953 printf("%s: Primary High Byte " 954 "termination Enabled\n", 955 ahc_name(ahc)); 956 } 957 958 write_brdctl(ahc, brddat); 959 960 } else { 961 if (sc->adapter_control & CFSTERM) { 962 if ((ahc->features & AHC_ULTRA2) != 0) 963 brddat |= BRDDAT5; 964 else 965 *sxfrctl1 |= STPWEN; 966 967 if (bootverbose) 968 printf("%s: %sLow byte termination Enabled\n", 969 ahc_name(ahc), 970 (ahc->features & AHC_ULTRA2) ? "Primary " 971 : ""); 972 } 973 974 if (sc->adapter_control & CFWSTERM) { 975 brddat |= BRDDAT6; 976 if (bootverbose) 977 printf("%s: %sHigh byte termination Enabled\n", 978 ahc_name(ahc), 979 (ahc->features & AHC_ULTRA2) 980 ? "Secondary " : ""); 981 } 982 983 write_brdctl(ahc, brddat); 984 } 985 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 986 } 987 988 static void 989 ahc_ultra2_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 990 int *enableSEC_high, int *enablePRI_low, 991 int *enablePRI_high, int *eeprom_present) 992 { 993 u_int8_t brdctl; 994 995 /* 996 * BRDDAT7 = Eeprom 997 * BRDDAT6 = Enable Secondary High Byte termination 998 * BRDDAT5 = Enable Secondary Low Byte termination 999 * BRDDAT4 = Enable Primary low byte termination 1000 * BRDDAT3 = Enable Primary high byte termination 1001 */ 1002 brdctl = read_brdctl(ahc); 1003 1004 *eeprom_present = brdctl & BRDDAT7; 1005 *enableSEC_high = (brdctl & BRDDAT6); 1006 *enableSEC_low = (brdctl & BRDDAT5); 1007 *enablePRI_low = (brdctl & BRDDAT4); 1008 *enablePRI_high = (brdctl & BRDDAT3); 1009 } 1010 1011 static void 1012 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1013 int *internal68_present, int *externalcable_present, 1014 int *eeprom_present) 1015 { 1016 u_int8_t brdctl; 1017 1018 /* 1019 * First read the status of our cables. 1020 * Set the rom bank to 0 since the 1021 * bank setting serves as a multiplexor 1022 * for the cable detection logic. 1023 * BRDDAT5 controls the bank switch. 1024 */ 1025 write_brdctl(ahc, 0); 1026 1027 /* 1028 * Now read the state of the internal 1029 * connectors. BRDDAT6 is INT50 and 1030 * BRDDAT7 is INT68. 1031 */ 1032 brdctl = read_brdctl(ahc); 1033 *internal50_present = !(brdctl & BRDDAT6); 1034 *internal68_present = !(brdctl & BRDDAT7); 1035 1036 /* 1037 * Set the rom bank to 1 and determine 1038 * the other signals. 1039 */ 1040 write_brdctl(ahc, BRDDAT5); 1041 1042 /* 1043 * Now read the state of the external 1044 * connectors. BRDDAT6 is EXT68 and 1045 * BRDDAT7 is EPROMPS. 1046 */ 1047 brdctl = read_brdctl(ahc); 1048 *externalcable_present = !(brdctl & BRDDAT6); 1049 *eeprom_present = brdctl & BRDDAT7; 1050 } 1051 1052 static void 1053 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1054 int *externalcable_present, int *eeprom_present) 1055 { 1056 u_int8_t brdctl; 1057 1058 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1059 ahc_outb(ahc, BRDCTL, 0); 1060 brdctl = ahc_inb(ahc, BRDCTL); 1061 *internal50_present = !(brdctl & BRDDAT5); 1062 *externalcable_present = !(brdctl & BRDDAT6); 1063 1064 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) != 0; 1065 } 1066 1067 static int 1068 acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1069 { 1070 int wait; 1071 1072 if ((ahc->features & AHC_SPIOCAP) != 0 1073 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1074 return (0); 1075 1076 /* 1077 * Request access of the memory port. When access is 1078 * granted, SEERDY will go high. We use a 1 second 1079 * timeout which should be near 1 second more than 1080 * is needed. Reason: after the chip reset, there 1081 * should be no contention. 1082 */ 1083 SEEPROM_OUTB(sd, sd->sd_MS); 1084 wait = 1000; /* 1 second timeout in msec */ 1085 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1086 DELAY(1000); /* delay 1 msec */ 1087 } 1088 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1089 SEEPROM_OUTB(sd, 0); 1090 return (0); 1091 } 1092 return(1); 1093 } 1094 1095 static void 1096 release_seeprom(sd) 1097 struct seeprom_descriptor *sd; 1098 { 1099 /* Release access to the memory port and the serial EEPROM. */ 1100 SEEPROM_OUTB(sd, 0); 1101 } 1102 1103 static void 1104 write_brdctl(ahc, value) 1105 struct ahc_softc *ahc; 1106 u_int8_t value; 1107 { 1108 u_int8_t brdctl; 1109 1110 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1111 brdctl = BRDSTB; 1112 if (ahc->channel == 'B') 1113 brdctl |= BRDCS; 1114 } else if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7890) { 1115 brdctl = 0; 1116 } else { 1117 brdctl = BRDSTB|BRDCS; 1118 } 1119 ahc_outb(ahc, BRDCTL, brdctl); 1120 brdctl |= value; 1121 ahc_outb(ahc, BRDCTL, brdctl); 1122 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7890) 1123 brdctl |= BRDSTB_ULTRA2; 1124 else 1125 brdctl &= ~BRDSTB; 1126 ahc_outb(ahc, BRDCTL, brdctl); 1127 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7890) 1128 brdctl = 0; 1129 else 1130 brdctl &= ~BRDCS; 1131 ahc_outb(ahc, BRDCTL, brdctl); 1132 } 1133 1134 static u_int8_t 1135 read_brdctl(ahc) 1136 struct ahc_softc *ahc; 1137 { 1138 u_int8_t brdctl; 1139 u_int8_t value; 1140 1141 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1142 brdctl = BRDRW; 1143 if (ahc->channel == 'B') 1144 brdctl |= BRDCS; 1145 } else if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7890) { 1146 brdctl = BRDRW_ULTRA2; 1147 } else { 1148 brdctl = BRDRW|BRDCS; 1149 } 1150 ahc_outb(ahc, BRDCTL, brdctl); 1151 value = ahc_inb(ahc, BRDCTL); 1152 ahc_outb(ahc, BRDCTL, 0); 1153 return (value); 1154 } 1155 1156 #define DPE 0x80 1157 #define SSE 0x40 1158 #define RMA 0x20 1159 #define RTA 0x10 1160 #define STA 0x08 1161 #define DPR 0x01 1162 1163 void 1164 ahc_pci_intr(struct ahc_softc *ahc) 1165 { 1166 u_int8_t status1; 1167 pcici_t config_id; 1168 1169 status1 = pci_cfgread(ahc->pci_config_id, PCIR_STATUS + 1, /*bytes*/1); 1170 1171 if (status1 & DPE) { 1172 printf("%s: Data Parity Error Detected during address " 1173 "or write data phase\n", ahc_name(ahc)); 1174 } 1175 if (status1 & SSE) { 1176 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1177 } 1178 if (status1 & RMA) { 1179 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1180 } 1181 if (status1 & RTA) { 1182 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1183 } 1184 if (status1 & STA) { 1185 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1186 } 1187 if (status1 & DPR) { 1188 printf("%s: Data Parity Error has been reported via PERR#\n", 1189 ahc_name(ahc)); 1190 } 1191 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1192 printf("%s: Latched PCIERR interrupt with " 1193 "no status bits set\n", ahc_name(ahc)); 1194 } 1195 pci_cfgwrite(ahc->pci_config_id, PCIR_STATUS + 1, status1, /*bytes*/1); 1196 1197 if (status1 & (DPR|RMA|RTA)) { 1198 ahc_outb(ahc, CLRINT, CLRPARERR); 1199 } 1200 } 1201 1202 #endif /* NPCI > 0 */ 1203