1 /* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1995, 1996, 1997, 1998 Justin T. Gibbs 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Where this Software is combined with software released under the terms of 19 * the GNU Public License ("GPL") and the terms of the GPL would require the 20 * combined work to also be released under the terms of the GPL, the terms 21 * and conditions of this License will apply in addition to those of the 22 * GPL with the exception of any terms or conditions of this License that 23 * conflict with, or are expressly prohibited by, the GPL. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $Id: ahc_pci.c,v 1.14 1999/05/25 20:12:32 gibbs Exp $ 38 */ 39 40 #include <pci.h> 41 #if NPCI > 0 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/module.h> 46 #include <sys/bus.h> 47 48 #include <pci/pcireg.h> 49 #include <pci/pcivar.h> 50 51 #include <machine/bus_memio.h> 52 #include <machine/bus_pio.h> 53 #include <machine/bus.h> 54 #include <machine/resource.h> 55 #include <machine/clock.h> 56 #include <sys/rman.h> 57 58 #include <cam/cam.h> 59 #include <cam/cam_ccb.h> 60 #include <cam/cam_sim.h> 61 #include <cam/cam_xpt_sim.h> 62 63 #include <cam/scsi/scsi_all.h> 64 65 #include <dev/aic7xxx/aic7xxx.h> 66 #include <dev/aic7xxx/93cx6.h> 67 68 #include <aic7xxx_reg.h> 69 70 #define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ 71 #define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 72 73 static __inline u_int64_t 74 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 75 { 76 u_int64_t id; 77 78 id = subvendor 79 | (subdevice << 16) 80 | ((u_int64_t)vendor << 32) 81 | ((u_int64_t)device << 48); 82 83 return (id); 84 } 85 86 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 87 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 88 #define ID_AIC7850 0x5078900400000000ull 89 #define ID_AHA_2910_15_20_30C 0x5078900478509004ull 90 #define ID_AIC7855 0x5578900400000000ull 91 #define ID_AIC7860 0x6078900400000000ull 92 #define ID_AIC7860C 0x6078900478609004ull 93 #define ID_AHA_2940AU_0 0x6178900400000000ull 94 #define ID_AHA_2940AU_1 0x6178900478619004ull 95 #define ID_AHA_2930C_VAR 0x6038900438689004ull 96 97 #define ID_AIC7870 0x7078900400000000ull 98 #define ID_AHA_2940 0x7178900400000000ull 99 #define ID_AHA_3940 0x7278900400000000ull 100 #define ID_AHA_398X 0x7378900400000000ull 101 #define ID_AHA_2944 0x7478900400000000ull 102 #define ID_AHA_3944 0x7578900400000000ull 103 104 #define ID_AIC7880 0x8078900400000000ull 105 #define ID_AIC7880_B 0x8078900478809004ull 106 #define ID_AHA_2940AU_CN 0x2178900478219004ull 107 #define ID_AHA_2940U 0x8178900400000000ull 108 #define ID_AHA_3940U 0x8278900400000000ull 109 #define ID_AHA_2944U 0x8478900400000000ull 110 #define ID_AHA_3944U 0x8578900400000000ull 111 #define ID_AHA_398XU 0x8378900400000000ull 112 #define ID_AHA_4944U 0x8678900400000000ull 113 #define ID_AHA_2940UB 0x8178900478819004ull 114 #define ID_AHA_2930U 0x8878900478889004ull 115 #define ID_AHA_2940U_PRO 0x8778900478879004ull 116 #define ID_AHA_2940U_CN 0x0078900478009004ull 117 118 #define ID_AIC7895 0x7895900478959004ull 119 #define ID_AIC7895_RAID_PORT 0x7893900478939004ull 120 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 121 #define ID_AHA_3940AU 0x7895900478929004ull 122 #define ID_AHA_3944AU 0x7895900478949004ull 123 124 #define ID_AIC7890 0x001F9005000F9005ull 125 #define ID_AHA_2930U2 0x0011900501819005ull 126 #define ID_AHA_2940U2B 0x00109005A1009005ull 127 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 128 #define ID_AHA_2940U2 0x00109005A1809005ull 129 #define ID_AHA_2950U2B 0x00109005E1009005ull 130 131 #define ID_AIC7896 0x005F9005FFFF9005ull 132 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 133 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 134 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 135 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 136 137 #define ID_AIC7810 0x1078900400000000ull 138 #define ID_AIC7815 0x1578900400000000ull 139 140 typedef int (ahc_device_setup_t)(device_t, char *, ahc_chip *, 141 ahc_feature *, ahc_flag *); 142 143 static ahc_device_setup_t ahc_aic7850_setup; 144 static ahc_device_setup_t ahc_aic7860_setup; 145 static ahc_device_setup_t ahc_aic7870_setup; 146 static ahc_device_setup_t ahc_aha394X_setup; 147 static ahc_device_setup_t ahc_aha398X_setup; 148 static ahc_device_setup_t ahc_aic7880_setup; 149 static ahc_device_setup_t ahc_aha394XU_setup; 150 static ahc_device_setup_t ahc_aha398XU_setup; 151 static ahc_device_setup_t ahc_aic7890_setup; 152 static ahc_device_setup_t ahc_aic7895_setup; 153 static ahc_device_setup_t ahc_aic7896_setup; 154 static ahc_device_setup_t ahc_raid_setup; 155 static ahc_device_setup_t ahc_aha394XX_setup; 156 static ahc_device_setup_t ahc_aha398XX_setup; 157 158 struct ahc_pci_identity { 159 u_int64_t full_id; 160 u_int64_t id_mask; 161 char *name; 162 ahc_device_setup_t *setup; 163 }; 164 165 struct ahc_pci_identity ahc_pci_ident_table [] = 166 { 167 /* aic7850 based controllers */ 168 { 169 ID_AHA_2910_15_20_30C, 170 ID_ALL_MASK, 171 "Adaptec 2910/15/20/30C SCSI adapter", 172 ahc_aic7850_setup 173 }, 174 /* aic7860 based controllers */ 175 { 176 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 177 ID_DEV_VENDOR_MASK, 178 "Adaptec 2940A Ultra SCSI adapter", 179 ahc_aic7860_setup 180 }, 181 { 182 ID_AHA_2930C_VAR, 183 ID_ALL_MASK, 184 "Adaptec 2930C SCSI adapter (VAR)", 185 ahc_aic7860_setup 186 }, 187 /* aic7870 based controllers */ 188 { 189 ID_AHA_2940, 190 ID_ALL_MASK, 191 "Adaptec 2940 SCSI adapter", 192 ahc_aic7870_setup 193 }, 194 { 195 ID_AHA_3940, 196 ID_ALL_MASK, 197 "Adaptec 3940 SCSI adapter", 198 ahc_aha394X_setup 199 }, 200 { 201 ID_AHA_398X, 202 ID_ALL_MASK, 203 "Adaptec 398X SCSI RAID adapter", 204 ahc_aha398X_setup 205 }, 206 { 207 ID_AHA_2944, 208 ID_ALL_MASK, 209 "Adaptec 2944 SCSI adapter", 210 ahc_aic7870_setup 211 }, 212 { 213 ID_AHA_3944, 214 ID_ALL_MASK, 215 "Adaptec 3944 SCSI adapter", 216 ahc_aha394X_setup 217 }, 218 /* aic7880 based controllers */ 219 { 220 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 221 ID_DEV_VENDOR_MASK, 222 "Adaptec 2940A/CN Ultra SCSI adapter", 223 ahc_aic7880_setup 224 }, 225 { 226 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 227 ID_DEV_VENDOR_MASK, 228 "Adaptec 2940 Ultra SCSI adapter", 229 ahc_aic7880_setup 230 }, 231 { 232 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 233 ID_DEV_VENDOR_MASK, 234 "Adaptec 3940 Ultra SCSI adapter", 235 ahc_aha394XU_setup 236 }, 237 { 238 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 239 ID_DEV_VENDOR_MASK, 240 "Adaptec 2944 Ultra SCSI adapter", 241 ahc_aic7880_setup 242 }, 243 { 244 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 245 ID_DEV_VENDOR_MASK, 246 "Adaptec 3944 Ultra SCSI adapter", 247 ahc_aha394XU_setup 248 }, 249 { 250 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 251 ID_DEV_VENDOR_MASK, 252 "Adaptec 398X Ultra SCSI RAID adapter", 253 ahc_aha398XU_setup 254 }, 255 { 256 /* XXX Don't know the slot numbers so can't identify channels */ 257 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 258 ID_DEV_VENDOR_MASK, 259 "Adaptec 4944 Ultra SCSI adapter", 260 ahc_aic7880_setup 261 }, 262 { 263 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 264 ID_DEV_VENDOR_MASK, 265 "Adaptec 2930 Ultra SCSI adapter", 266 ahc_aic7880_setup 267 }, 268 { 269 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 270 ID_DEV_VENDOR_MASK, 271 "Adaptec 2940 Pro Ultra SCSI adapter", 272 ahc_aic7880_setup 273 }, 274 { 275 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 276 ID_DEV_VENDOR_MASK, 277 "Adaptec 2940/CN Ultra SCSI adapter", 278 ahc_aic7880_setup 279 }, 280 /* aic7890 based controllers */ 281 { 282 ID_AHA_2930U2, 283 ID_ALL_MASK, 284 "Adaptec 2930 Ultra2 SCSI adapter", 285 ahc_aic7890_setup 286 }, 287 { 288 ID_AHA_2940U2B, 289 ID_ALL_MASK, 290 "Adaptec 2940B Ultra2 SCSI adapter", 291 ahc_aic7890_setup 292 }, 293 { 294 ID_AHA_2940U2_OEM, 295 ID_ALL_MASK, 296 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 297 ahc_aic7890_setup 298 }, 299 { 300 ID_AHA_2940U2, 301 ID_ALL_MASK, 302 "Adaptec 2940 Ultra2 SCSI adapter", 303 ahc_aic7890_setup 304 }, 305 { 306 ID_AHA_2950U2B, 307 ID_ALL_MASK, 308 "Adaptec 2950 Ultra2 SCSI adapter", 309 ahc_aic7890_setup 310 }, 311 /* aic7895 based controllers */ 312 { 313 ID_AHA_2940U_DUAL, 314 ID_ALL_MASK, 315 "Adaptec 2940/DUAL Ultra SCSI adapter", 316 ahc_aic7895_setup 317 }, 318 { 319 ID_AHA_3940AU, 320 ID_ALL_MASK, 321 "Adaptec 3940A Ultra SCSI adapter", 322 ahc_aic7895_setup 323 }, 324 { 325 ID_AHA_3944AU, 326 ID_ALL_MASK, 327 "Adaptec 3944A Ultra SCSI adapter", 328 ahc_aic7895_setup 329 }, 330 /* aic7896/97 based controllers */ 331 { 332 ID_AHA_3950U2B_0, 333 ID_ALL_MASK, 334 "Adaptec 3950B Ultra2 SCSI adapter", 335 ahc_aic7896_setup 336 }, 337 { 338 ID_AHA_3950U2B_1, 339 ID_ALL_MASK, 340 "Adaptec 3950B Ultra2 SCSI adapter", 341 ahc_aic7896_setup 342 }, 343 { 344 ID_AHA_3950U2D_0, 345 ID_ALL_MASK, 346 "Adaptec 3950D Ultra2 SCSI adapter", 347 ahc_aic7896_setup 348 }, 349 { 350 ID_AHA_3950U2D_1, 351 ID_ALL_MASK, 352 "Adaptec 3950D Ultra2 SCSI adapter", 353 ahc_aic7896_setup 354 }, 355 /* Generic chip probes for devices we don't know 'exactly' */ 356 { 357 ID_AIC7850 & ID_DEV_VENDOR_MASK, 358 ID_DEV_VENDOR_MASK, 359 "Adaptec aic7850 SCSI adapter", 360 ahc_aic7850_setup 361 }, 362 { 363 ID_AIC7855 & ID_DEV_VENDOR_MASK, 364 ID_DEV_VENDOR_MASK, 365 "Adaptec aic7855 SCSI adapter", 366 ahc_aic7850_setup 367 }, 368 { 369 ID_AIC7860 & ID_DEV_VENDOR_MASK, 370 ID_DEV_VENDOR_MASK, 371 "Adaptec aic7860 SCSI adapter", 372 ahc_aic7860_setup 373 }, 374 { 375 ID_AIC7870 & ID_DEV_VENDOR_MASK, 376 ID_DEV_VENDOR_MASK, 377 "Adaptec aic7870 SCSI adapter", 378 ahc_aic7870_setup 379 }, 380 { 381 ID_AIC7880 & ID_DEV_VENDOR_MASK, 382 ID_DEV_VENDOR_MASK, 383 "Adaptec aic7880 Ultra SCSI adapter", 384 ahc_aic7880_setup 385 }, 386 { 387 ID_AIC7890 & ID_DEV_VENDOR_MASK, 388 ID_DEV_VENDOR_MASK, 389 "Adaptec aic7890/91 Ultra2 SCSI adapter", 390 ahc_aic7890_setup 391 }, 392 { 393 ID_AIC7895 & ID_DEV_VENDOR_MASK, 394 ID_DEV_VENDOR_MASK, 395 "Adaptec aic7895 Ultra SCSI adapter", 396 ahc_aic7895_setup 397 }, 398 { 399 ID_AIC7895_RAID_PORT & ID_DEV_VENDOR_MASK, 400 ID_DEV_VENDOR_MASK, 401 "Adaptec aic7895 Ultra SCSI adapter (RAID PORT)", 402 ahc_aic7895_setup 403 }, 404 { 405 ID_AIC7896 & ID_DEV_VENDOR_MASK, 406 ID_DEV_VENDOR_MASK, 407 "Adaptec aic7896/97 Ultra2 SCSI adapter", 408 ahc_aic7896_setup 409 }, 410 { 411 ID_AIC7810 & ID_DEV_VENDOR_MASK, 412 ID_DEV_VENDOR_MASK, 413 "Adaptec aic7810 RAID memory controller", 414 ahc_raid_setup 415 }, 416 { 417 ID_AIC7815 & ID_DEV_VENDOR_MASK, 418 ID_DEV_VENDOR_MASK, 419 "Adaptec aic7815 RAID memory controller", 420 ahc_raid_setup 421 } 422 }; 423 424 static const int ahc_num_pci_devs = 425 sizeof(ahc_pci_ident_table) / sizeof(*ahc_pci_ident_table); 426 427 #define AHC_394X_SLOT_CHANNEL_A 4 428 #define AHC_394X_SLOT_CHANNEL_B 5 429 430 #define AHC_398X_SLOT_CHANNEL_A 4 431 #define AHC_398X_SLOT_CHANNEL_B 8 432 #define AHC_398X_SLOT_CHANNEL_C 12 433 434 #define DEVCONFIG 0x40 435 #define SCBSIZE32 0x00010000ul /* aic789X only */ 436 #define MPORTMODE 0x00000400ul /* aic7870 only */ 437 #define RAMPSM 0x00000200ul /* aic7870 only */ 438 #define VOLSENSE 0x00000100ul 439 #define SCBRAMSEL 0x00000080ul 440 #define MRDCEN 0x00000040ul 441 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 442 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 443 #define BERREN 0x00000008ul 444 #define DACEN 0x00000004ul 445 #define STPWLEVEL 0x00000002ul 446 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 447 448 #define CSIZE_LATTIME 0x0c 449 #define CACHESIZE 0x0000003ful /* only 5 bits */ 450 #define LATTIME 0x0000ff00ul 451 452 static struct ahc_pci_identity *ahc_find_pci_device(device_t dev); 453 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 454 static void configure_termination(struct ahc_softc *ahc, 455 struct seeprom_config *sc, 456 struct seeprom_descriptor *sd, 457 u_int *sxfrctl1); 458 459 static void ahc_ultra2_term_detect(struct ahc_softc *ahc, 460 int *enableSEC_low, 461 int *enableSEC_high, 462 int *enablePRI_low, 463 int *enablePRI_high, 464 int *eeprom_present); 465 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 466 int *internal68_present, 467 int *externalcable_present, 468 int *eeprom_present); 469 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 470 int *externalcable_present, 471 int *eeprom_present); 472 static int acquire_seeprom(struct ahc_softc *ahc, 473 struct seeprom_descriptor *sd); 474 static void release_seeprom(struct seeprom_descriptor *sd); 475 static void write_brdctl(struct ahc_softc *ahc, u_int8_t value); 476 static u_int8_t read_brdctl(struct ahc_softc *ahc); 477 478 static struct ahc_softc *first_398X; 479 480 static int ahc_pci_probe(device_t dev); 481 static int ahc_pci_attach(device_t dev); 482 483 /* Exported for use in the ahc_intr routine */ 484 void ahc_pci_intr(struct ahc_softc *ahc); 485 486 static device_method_t ahc_pci_methods[] = { 487 /* Device interface */ 488 DEVMETHOD(device_probe, ahc_pci_probe), 489 DEVMETHOD(device_attach, ahc_pci_attach), 490 { 0, 0 } 491 }; 492 493 static driver_t ahc_pci_driver = { 494 "ahc", 495 ahc_pci_methods, 496 sizeof(struct ahc_softc) 497 }; 498 499 static devclass_t ahc_devclass; 500 501 DRIVER_MODULE(ahc, pci, ahc_pci_driver, ahc_devclass, 0, 0); 502 503 static struct ahc_pci_identity * 504 ahc_find_pci_device(device_t dev) 505 { 506 u_int64_t full_id; 507 struct ahc_pci_identity *entry; 508 u_int i; 509 510 full_id = ahc_compose_id(pci_get_device(dev), 511 pci_get_vendor(dev), 512 pci_get_subdevice(dev), 513 pci_get_subvendor(dev)); 514 515 for (i = 0; i < ahc_num_pci_devs; i++) { 516 entry = &ahc_pci_ident_table[i]; 517 if (entry->full_id == (full_id & entry->id_mask)) 518 return (entry); 519 } 520 return (NULL); 521 } 522 523 static int 524 ahc_pci_probe(device_t dev) 525 { 526 struct ahc_pci_identity *entry; 527 528 entry = ahc_find_pci_device(dev); 529 if (entry != NULL) { 530 device_set_desc(dev, entry->name); 531 return (0); 532 } 533 return (ENXIO); 534 } 535 536 static int 537 ahc_pci_attach(device_t dev) 538 { 539 bus_dma_tag_t parent_dmat; 540 struct ahc_pci_identity *entry; 541 struct resource *regs; 542 struct ahc_softc *ahc; 543 u_int command; 544 struct scb_data *shared_scb_data; 545 ahc_chip ahc_t = AHC_NONE; 546 ahc_feature ahc_fe = AHC_FENONE; 547 ahc_flag ahc_f = AHC_FNONE; 548 int regs_type; 549 int regs_id; 550 u_int our_id = 0; 551 u_int sxfrctl1; 552 u_int scsiseq; 553 int error; 554 int zero; 555 char channel; 556 557 shared_scb_data = NULL; 558 command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1); 559 entry = ahc_find_pci_device(dev); 560 if (entry == NULL) 561 return (ENXIO); 562 error = entry->setup(dev, &channel, &ahc_t, &ahc_fe, &ahc_f); 563 if (error != 0) 564 return (error); 565 566 regs = NULL; 567 regs_type = 0; 568 regs_id = 0; 569 #ifdef AHC_ALLOW_MEMIO 570 if ((command & PCIM_CMD_MEMEN) != 0) { 571 regs_type = SYS_RES_MEMORY; 572 regs_id = AHC_PCI_MEMADDR; 573 regs = bus_alloc_resource(dev, regs_type, 574 ®s_id, 0, ~0, 1, RF_ACTIVE); 575 } 576 #endif 577 578 if (regs == NULL && (command & PCI_COMMAND_IO_ENABLE) != 0) { 579 regs_type = SYS_RES_IOPORT; 580 regs_id = AHC_PCI_IOADDR; 581 regs = bus_alloc_resource(dev, regs_type, 582 ®s_id, 0, ~0, 1, RF_ACTIVE); 583 } 584 585 if (regs == NULL) { 586 device_printf(dev, "can't allocate register resources\n"); 587 return (ENOMEM); 588 } 589 590 /* Ensure busmastering is enabled */ 591 command |= PCIM_CMD_BUSMASTEREN; 592 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1); 593 594 /* Allocate a dmatag for our SCB DMA maps */ 595 /* XXX Should be a child of the PCI bus dma tag */ 596 error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/0, 597 /*boundary*/0, 598 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 599 /*highaddr*/BUS_SPACE_MAXADDR, 600 /*filter*/NULL, /*filterarg*/NULL, 601 /*maxsize*/MAXBSIZE, /*nsegments*/AHC_NSEG, 602 /*maxsegsz*/AHC_MAXTRANSFER_SIZE, 603 /*flags*/BUS_DMA_ALLOCNOW, &parent_dmat); 604 605 if (error != 0) { 606 printf("ahc_pci_attach: Could not allocate DMA tag " 607 "- error %d\n", error); 608 return (ENOMEM); 609 } 610 611 /* On all PCI adapters, we allow SCB paging */ 612 ahc_f |= AHC_PAGESCBS; 613 if ((ahc = ahc_alloc(dev, regs, regs_type, regs_id, parent_dmat, 614 ahc_t|AHC_PCI, ahc_fe, ahc_f, 615 shared_scb_data)) == NULL) 616 return (ENOMEM); 617 618 ahc->channel = channel; 619 620 /* Store our PCI bus information for use in our PCI error handler */ 621 ahc->device = dev; 622 623 /* Remeber how the card was setup in case there is no SEEPROM */ 624 ahc_outb(ahc, HCNTRL, ahc->pause); 625 if ((ahc->features & AHC_ULTRA2) != 0) 626 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 627 else 628 our_id = ahc_inb(ahc, SCSIID) & OID; 629 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 630 scsiseq = ahc_inb(ahc, SCSISEQ); 631 632 if (ahc_reset(ahc) != 0) { 633 /* Failed */ 634 ahc_free(ahc); 635 return (ENXIO); 636 } 637 638 /* 639 * Take a look to see if we have external SRAM. 640 * We currently do not attempt to use SRAM that is 641 * shared among multiple controllers. 642 */ 643 if ((ahc->features & AHC_ULTRA2) != 0) { 644 u_int dscommand0; 645 646 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 647 if ((dscommand0 & RAMPS) != 0) { 648 u_int32_t devconfig; 649 650 devconfig = pci_read_config(dev, DEVCONFIG, /*bytes*/4); 651 if ((devconfig & MPORTMODE) != 0) { 652 /* Single user mode */ 653 654 /* 655 * XXX Assume 9bit SRAM and enable 656 * parity checking 657 */ 658 devconfig |= EXTSCBPEN; 659 pci_write_config(dev, DEVCONFIG, 660 devconfig, /*bytes*/4); 661 662 /* 663 * Set the bank select apropriately. 664 */ 665 if (ahc->channel == 'B') 666 ahc_outb(ahc, SCBBADDR, 1); 667 else 668 ahc_outb(ahc, SCBBADDR, 0); 669 670 /* Select external SCB SRAM */ 671 dscommand0 &= ~INTSCBRAMSEL; 672 ahc_outb(ahc, DSCOMMAND0, dscommand0); 673 674 if (ahc_probe_scbs(ahc) == 0) { 675 /* External ram isn't really there */ 676 dscommand0 |= INTSCBRAMSEL; 677 ahc_outb(ahc, DSCOMMAND0, dscommand0); 678 } else if (bootverbose) 679 printf("%s: External SRAM bank%d\n", 680 ahc_name(ahc), 681 ahc->channel == 'B' ? 1 : 0); 682 } 683 684 } 685 } else if ((ahc->chip & AHC_CHIPID_MASK) >= AHC_AIC7870) { 686 u_int32_t devconfig; 687 688 devconfig = pci_read_config(dev, DEVCONFIG, /*bytes*/4); 689 if ((devconfig & RAMPSM) != 0 690 && (devconfig & MPORTMODE) != 0) { 691 692 /* XXX Assume 9bit SRAM and enable parity checking */ 693 devconfig |= EXTSCBPEN; 694 695 /* XXX Assume fast SRAM */ 696 devconfig &= ~EXTSCBTIME; 697 698 /* 699 * Set the bank select apropriately. 700 */ 701 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 702 if (ahc->channel == 'B') 703 ahc_outb(ahc, SCBBADDR, 1); 704 else 705 ahc_outb(ahc, SCBBADDR, 0); 706 } 707 708 /* Select external SRAM */ 709 devconfig &= ~SCBRAMSEL; 710 pci_write_config(dev, DEVCONFIG, devconfig, /*bytes*/4); 711 712 if (ahc_probe_scbs(ahc) == 0) { 713 /* External ram isn't really there */ 714 devconfig |= SCBRAMSEL; 715 pci_write_config(dev, DEVCONFIG, 716 devconfig, /*bytes*/4); 717 } else if (bootverbose) 718 printf("%s: External SRAM bank%d\n", 719 ahc_name(ahc), 720 ahc->channel == 'B' ? 1 : 0); 721 } 722 } 723 724 zero = 0; 725 ahc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &zero, 726 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 727 if (ahc->irq == NULL) { 728 ahc_free(ahc); 729 return (ENOMEM); 730 } 731 732 ahc->irq_res_type = SYS_RES_IRQ; 733 734 /* 735 * Do aic7880/aic7870/aic7860/aic7850 specific initialization 736 */ 737 { 738 u_int8_t sblkctl; 739 char *id_string; 740 741 switch(ahc_t) { 742 case AHC_AIC7896: 743 { 744 u_int dscommand0; 745 746 /* 747 * DPARCKEN doesn't work correctly on 748 * some MBs so don't use it. 749 */ 750 id_string = "aic7896/97 "; 751 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 752 dscommand0 &= ~(USCBSIZE32|DPARCKEN); 753 dscommand0 |= CACHETHEN|MPARCKEN; 754 ahc_outb(ahc, DSCOMMAND0, dscommand0); 755 break; 756 } 757 case AHC_AIC7890: 758 { 759 u_int dscommand0; 760 761 /* 762 * DPARCKEN doesn't work correctly on 763 * some MBs so don't use it. 764 */ 765 id_string = "aic7890/91 "; 766 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 767 dscommand0 &= ~(USCBSIZE32|DPARCKEN); 768 dscommand0 |= CACHETHEN|MPARCKEN; 769 ahc_outb(ahc, DSCOMMAND0, dscommand0); 770 break; 771 } 772 case AHC_AIC7895: 773 id_string = "aic7895 "; 774 break; 775 case AHC_AIC7880: 776 id_string = "aic7880 "; 777 break; 778 case AHC_AIC7870: 779 id_string = "aic7870 "; 780 break; 781 case AHC_AIC7860: 782 id_string = "aic7860 "; 783 break; 784 case AHC_AIC7850: 785 id_string = "aic7850 "; 786 break; 787 default: 788 printf("ahc: Unknown controller type. Ignoring.\n"); 789 ahc_free(ahc); 790 return (ENXIO); 791 } 792 793 /* See if we have an SEEPROM and perform auto-term */ 794 check_extport(ahc, &sxfrctl1); 795 796 /* 797 * Take the LED out of diagnostic mode 798 */ 799 sblkctl = ahc_inb(ahc, SBLKCTL); 800 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 801 802 /* 803 * I don't know where this is set in the SEEPROM or by the 804 * BIOS, so we default to 100% on Ultra or slower controllers 805 * and 75% on ULTRA2 controllers. 806 */ 807 if ((ahc->features & AHC_ULTRA2) != 0) { 808 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 809 } else { 810 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 811 } 812 813 if (ahc->flags & AHC_USEDEFAULTS) { 814 /* 815 * PCI Adapter default setup 816 * Should only be used if the adapter does not have 817 * an SEEPROM. 818 */ 819 /* See if someone else set us up already */ 820 if (scsiseq != 0) { 821 printf("%s: Using left over BIOS settings\n", 822 ahc_name(ahc)); 823 ahc->flags &= ~AHC_USEDEFAULTS; 824 } else { 825 /* 826 * Assume only one connector and always turn 827 * on termination. 828 */ 829 our_id = 0x07; 830 sxfrctl1 = STPWEN; 831 } 832 ahc_outb(ahc, SCSICONF, 833 (our_id & 0x07)|ENSPCHK|RESET_SCSI); 834 835 ahc->our_id = our_id; 836 } 837 838 printf("%s: %s", ahc_name(ahc), id_string); 839 } 840 841 /* 842 * Record our termination setting for the 843 * generic initialization routine. 844 */ 845 if ((sxfrctl1 & STPWEN) != 0) 846 ahc->flags |= AHC_TERM_ENB_A; 847 848 if (ahc_init(ahc)) { 849 ahc_free(ahc); 850 return (ENOMEM); 851 } 852 853 /* XXX Crude hack - fix sometime */ 854 if (ahc->flags & AHC_SHARED_SRAM) { 855 /* Only set this once we've successfully probed */ 856 if (shared_scb_data == NULL) 857 first_398X = ahc; 858 } 859 860 ahc_attach(ahc); 861 862 return (0); 863 } 864 865 /* 866 * Check the external port logic for a serial eeprom 867 * and termination/cable detection contrls. 868 */ 869 static void 870 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 871 { 872 struct seeprom_descriptor sd; 873 struct seeprom_config sc; 874 u_int8_t scsi_conf; 875 int have_seeprom; 876 877 sd.sd_tag = ahc->tag; 878 sd.sd_bsh = ahc->bsh; 879 sd.sd_control_offset = SEECTL; 880 sd.sd_status_offset = SEECTL; 881 sd.sd_dataout_offset = SEECTL; 882 883 /* 884 * For some multi-channel devices, the c46 is simply too 885 * small to work. For the other controller types, we can 886 * get our information from either SEEPROM type. Set the 887 * type to start our probe with accordingly. 888 */ 889 if (ahc->flags & AHC_LARGE_SEEPROM) 890 sd.sd_chip = C56_66; 891 else 892 sd.sd_chip = C46; 893 894 sd.sd_MS = SEEMS; 895 sd.sd_RDY = SEERDY; 896 sd.sd_CS = SEECS; 897 sd.sd_CK = SEECK; 898 sd.sd_DO = SEEDO; 899 sd.sd_DI = SEEDI; 900 901 have_seeprom = acquire_seeprom(ahc, &sd); 902 903 if (have_seeprom) { 904 905 if (bootverbose) 906 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 907 908 for (;;) { 909 bus_size_t start_addr; 910 911 start_addr = 32 * (ahc->channel - 'A'); 912 913 have_seeprom = read_seeprom(&sd, (u_int16_t *)&sc, 914 start_addr, sizeof(sc)/2); 915 916 if (have_seeprom) { 917 /* Check checksum */ 918 int i; 919 int maxaddr; 920 u_int16_t *scarray; 921 u_int16_t checksum; 922 923 maxaddr = (sizeof(sc)/2) - 1; 924 checksum = 0; 925 scarray = (u_int16_t *)≻ 926 927 for (i = 0; i < maxaddr; i++) 928 checksum = checksum + scarray[i]; 929 if (checksum == 0 || checksum != sc.checksum) { 930 if (bootverbose && sd.sd_chip == C56_66) 931 printf ("checksum error\n"); 932 have_seeprom = 0; 933 } else { 934 if (bootverbose) 935 printf("done.\n"); 936 break; 937 } 938 } 939 940 if (sd.sd_chip == C56_66) 941 break; 942 sd.sd_chip = C56_66; 943 } 944 } 945 946 if (!have_seeprom) { 947 if (bootverbose) 948 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 949 ahc->flags |= AHC_USEDEFAULTS; 950 } else { 951 /* 952 * Put the data we've collected down into SRAM 953 * where ahc_init will find it. 954 */ 955 int i; 956 int max_targ = sc.max_targets & CFMAXTARG; 957 u_int16_t discenable; 958 u_int16_t ultraenb; 959 960 discenable = 0; 961 ultraenb = 0; 962 if ((sc.adapter_control & CFULTRAEN) != 0) { 963 /* 964 * Determine if this adapter has a "newstyle" 965 * SEEPROM format. 966 */ 967 for (i = 0; i < max_targ; i++) { 968 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0){ 969 ahc->flags |= AHC_NEWEEPROM_FMT; 970 break; 971 } 972 } 973 } 974 975 for (i = 0; i < max_targ; i++) { 976 u_int scsirate; 977 u_int16_t target_mask; 978 979 target_mask = 0x01 << i; 980 if (sc.device_flags[i] & CFDISC) 981 discenable |= target_mask; 982 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 983 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) 984 ultraenb |= target_mask; 985 } else if ((sc.adapter_control & CFULTRAEN) != 0) { 986 ultraenb |= target_mask; 987 } 988 if ((sc.device_flags[i] & CFXFER) == 0x04 989 && (ultraenb & target_mask) != 0) { 990 /* Treat 10MHz as a non-ultra speed */ 991 sc.device_flags[i] &= ~CFXFER; 992 ultraenb &= ~target_mask; 993 } 994 if ((ahc->features & AHC_ULTRA2) != 0) { 995 u_int offset; 996 997 if (sc.device_flags[i] & CFSYNCH) 998 offset = MAX_OFFSET_ULTRA2; 999 else 1000 offset = 0; 1001 ahc_outb(ahc, TARG_OFFSET + i, offset); 1002 1003 scsirate = (sc.device_flags[i] & CFXFER) 1004 | ((ultraenb & target_mask) 1005 ? 0x18 : 0x10); 1006 if (sc.device_flags[i] & CFWIDEB) 1007 scsirate |= WIDEXFER; 1008 } else { 1009 scsirate = (sc.device_flags[i] & CFXFER) << 4; 1010 if (sc.device_flags[i] & CFSYNCH) 1011 scsirate |= SOFS; 1012 if (sc.device_flags[i] & CFWIDEB) 1013 scsirate |= WIDEXFER; 1014 } 1015 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1016 } 1017 ahc->our_id = sc.brtime_id & CFSCSIID; 1018 1019 scsi_conf = (ahc->our_id & 0x7); 1020 if (sc.adapter_control & CFSPARITY) 1021 scsi_conf |= ENSPCHK; 1022 if (sc.adapter_control & CFRESETB) 1023 scsi_conf |= RESET_SCSI; 1024 1025 if (sc.bios_control & CFEXTEND) 1026 ahc->flags |= AHC_EXTENDED_TRANS_A; 1027 if (ahc->features & AHC_ULTRA 1028 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1029 /* Should we enable Ultra mode? */ 1030 if (!(sc.adapter_control & CFULTRAEN)) 1031 /* Treat us as a non-ultra card */ 1032 ultraenb = 0; 1033 } 1034 /* Set SCSICONF info */ 1035 ahc_outb(ahc, SCSICONF, scsi_conf); 1036 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1037 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1038 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1039 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1040 } 1041 1042 if ((ahc->features & AHC_SPIOCAP) != 0) { 1043 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0) { 1044 configure_termination(ahc, &sc, &sd, sxfrctl1); 1045 } 1046 } else if (have_seeprom) { 1047 configure_termination(ahc, &sc, &sd, sxfrctl1); 1048 } 1049 1050 release_seeprom(&sd); 1051 } 1052 1053 static void 1054 configure_termination(struct ahc_softc *ahc, 1055 struct seeprom_config *sc, 1056 struct seeprom_descriptor *sd, 1057 u_int *sxfrctl1) 1058 { 1059 int max_targ = sc->max_targets & CFMAXTARG; 1060 u_int8_t brddat; 1061 1062 brddat = 0; 1063 1064 /* 1065 * Update the settings in sxfrctl1 to match the 1066 *termination settings 1067 */ 1068 *sxfrctl1 = 0; 1069 1070 /* 1071 * SEECS must be on for the GALS to latch 1072 * the data properly. Be sure to leave MS 1073 * on or we will release the seeprom. 1074 */ 1075 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1076 if ((sc->adapter_control & CFAUTOTERM) != 0 1077 || (ahc->features & AHC_ULTRA2) != 0) { 1078 int internal50_present; 1079 int internal68_present; 1080 int externalcable_present; 1081 int eeprom_present; 1082 int enableSEC_low; 1083 int enableSEC_high; 1084 int enablePRI_low; 1085 int enablePRI_high; 1086 1087 enableSEC_low = 0; 1088 enableSEC_high = 0; 1089 enablePRI_low = 0; 1090 enablePRI_high = 0; 1091 if (ahc->features & AHC_ULTRA2) { 1092 ahc_ultra2_term_detect(ahc, &enableSEC_low, 1093 &enableSEC_high, 1094 &enablePRI_low, 1095 &enablePRI_high, 1096 &eeprom_present); 1097 if ((sc->adapter_control & CFSEAUTOTERM) == 0) { 1098 enableSEC_low = (sc->adapter_control & CFSTERM); 1099 enableSEC_high = 1100 (sc->adapter_control & CFWSTERM); 1101 } 1102 if ((sc->adapter_control & CFAUTOTERM) == 0) { 1103 enablePRI_low = enablePRI_high = 1104 (sc->adapter_control & CFLVDSTERM); 1105 } 1106 /* Make the table calculations below happy */ 1107 internal50_present = 0; 1108 internal68_present = 1; 1109 externalcable_present = 1; 1110 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1111 aic785X_cable_detect(ahc, &internal50_present, 1112 &externalcable_present, 1113 &eeprom_present); 1114 } else { 1115 aic787X_cable_detect(ahc, &internal50_present, 1116 &internal68_present, 1117 &externalcable_present, 1118 &eeprom_present); 1119 } 1120 1121 if (max_targ <= 8) { 1122 internal68_present = 0; 1123 } 1124 1125 if (bootverbose) { 1126 if ((ahc->features & AHC_ULTRA2) == 0) { 1127 printf("%s: internal 50 cable %s present, " 1128 "internal 68 cable %s present\n", 1129 ahc_name(ahc), 1130 internal50_present ? "is":"not", 1131 internal68_present ? "is":"not"); 1132 1133 printf("%s: external cable %s present\n", 1134 ahc_name(ahc), 1135 externalcable_present ? "is":"not"); 1136 } 1137 printf("%s: BIOS eeprom %s present\n", 1138 ahc_name(ahc), eeprom_present ? "is" : "not"); 1139 1140 } 1141 1142 /* 1143 * Now set the termination based on what 1144 * we found. 1145 * Flash Enable = BRDDAT7 1146 * Secondary High Term Enable = BRDDAT6 1147 * Secondary Low Term Enable = BRDDAT5 (7890) 1148 * Primary High Term Enable = BRDDAT4 (7890) 1149 */ 1150 if ((ahc->features & AHC_ULTRA2) == 0 1151 && (internal50_present != 0) 1152 && (internal68_present != 0) 1153 && (externalcable_present != 0)) { 1154 printf("%s: Illegal cable configuration!!. " 1155 "Only two connectors on the " 1156 "adapter may be used at a " 1157 "time!\n", ahc_name(ahc)); 1158 } 1159 1160 if ((max_targ > 8) 1161 && ((externalcable_present == 0) 1162 || (internal68_present == 0) 1163 || (enableSEC_high != 0))) { 1164 brddat |= BRDDAT6; 1165 if (bootverbose) 1166 printf("%s: %sHigh byte termination Enabled\n", 1167 ahc_name(ahc), 1168 enableSEC_high ? "Secondary " : ""); 1169 } 1170 1171 if (((internal50_present ? 1 : 0) 1172 + (internal68_present ? 1 : 0) 1173 + (externalcable_present ? 1 : 0)) <= 1 1174 || (enableSEC_low != 0)) { 1175 if ((ahc->features & AHC_ULTRA2) != 0) 1176 brddat |= BRDDAT5; 1177 else 1178 *sxfrctl1 |= STPWEN; 1179 if (bootverbose) 1180 printf("%s: %sLow byte termination Enabled\n", 1181 ahc_name(ahc), 1182 enableSEC_low ? "Secondary " : ""); 1183 } 1184 1185 if (enablePRI_low != 0) { 1186 *sxfrctl1 |= STPWEN; 1187 if (bootverbose) 1188 printf("%s: Primary Low Byte termination " 1189 "Enabled\n", ahc_name(ahc)); 1190 } 1191 1192 if (enablePRI_high != 0) { 1193 brddat |= BRDDAT4; 1194 if (bootverbose) 1195 printf("%s: Primary High Byte " 1196 "termination Enabled\n", 1197 ahc_name(ahc)); 1198 } 1199 1200 write_brdctl(ahc, brddat); 1201 1202 } else { 1203 if (sc->adapter_control & CFSTERM) { 1204 if ((ahc->features & AHC_ULTRA2) != 0) 1205 brddat |= BRDDAT5; 1206 else 1207 *sxfrctl1 |= STPWEN; 1208 1209 if (bootverbose) 1210 printf("%s: %sLow byte termination Enabled\n", 1211 ahc_name(ahc), 1212 (ahc->features & AHC_ULTRA2) ? "Primary " 1213 : ""); 1214 } 1215 1216 if (sc->adapter_control & CFWSTERM) { 1217 brddat |= BRDDAT6; 1218 if (bootverbose) 1219 printf("%s: %sHigh byte termination Enabled\n", 1220 ahc_name(ahc), 1221 (ahc->features & AHC_ULTRA2) 1222 ? "Secondary " : ""); 1223 } 1224 1225 write_brdctl(ahc, brddat); 1226 } 1227 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1228 } 1229 1230 static void 1231 ahc_ultra2_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 1232 int *enableSEC_high, int *enablePRI_low, 1233 int *enablePRI_high, int *eeprom_present) 1234 { 1235 u_int8_t brdctl; 1236 1237 /* 1238 * BRDDAT7 = Eeprom 1239 * BRDDAT6 = Enable Secondary High Byte termination 1240 * BRDDAT5 = Enable Secondary Low Byte termination 1241 * BRDDAT4 = Enable Primary low byte termination 1242 * BRDDAT3 = Enable Primary high byte termination 1243 */ 1244 brdctl = read_brdctl(ahc); 1245 1246 *eeprom_present = brdctl & BRDDAT7; 1247 *enableSEC_high = (brdctl & BRDDAT6); 1248 *enableSEC_low = (brdctl & BRDDAT5); 1249 *enablePRI_low = (brdctl & BRDDAT4); 1250 *enablePRI_high = (brdctl & BRDDAT3); 1251 } 1252 1253 static void 1254 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1255 int *internal68_present, int *externalcable_present, 1256 int *eeprom_present) 1257 { 1258 u_int8_t brdctl; 1259 1260 /* 1261 * First read the status of our cables. 1262 * Set the rom bank to 0 since the 1263 * bank setting serves as a multiplexor 1264 * for the cable detection logic. 1265 * BRDDAT5 controls the bank switch. 1266 */ 1267 write_brdctl(ahc, 0); 1268 1269 /* 1270 * Now read the state of the internal 1271 * connectors. BRDDAT6 is INT50 and 1272 * BRDDAT7 is INT68. 1273 */ 1274 brdctl = read_brdctl(ahc); 1275 *internal50_present = !(brdctl & BRDDAT6); 1276 *internal68_present = !(brdctl & BRDDAT7); 1277 1278 /* 1279 * Set the rom bank to 1 and determine 1280 * the other signals. 1281 */ 1282 write_brdctl(ahc, BRDDAT5); 1283 1284 /* 1285 * Now read the state of the external 1286 * connectors. BRDDAT6 is EXT68 and 1287 * BRDDAT7 is EPROMPS. 1288 */ 1289 brdctl = read_brdctl(ahc); 1290 *externalcable_present = !(brdctl & BRDDAT6); 1291 *eeprom_present = brdctl & BRDDAT7; 1292 } 1293 1294 static void 1295 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1296 int *externalcable_present, int *eeprom_present) 1297 { 1298 u_int8_t brdctl; 1299 1300 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1301 ahc_outb(ahc, BRDCTL, 0); 1302 brdctl = ahc_inb(ahc, BRDCTL); 1303 *internal50_present = !(brdctl & BRDDAT5); 1304 *externalcable_present = !(brdctl & BRDDAT6); 1305 1306 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) != 0; 1307 } 1308 1309 static int 1310 acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1311 { 1312 int wait; 1313 1314 if ((ahc->features & AHC_SPIOCAP) != 0 1315 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1316 return (0); 1317 1318 /* 1319 * Request access of the memory port. When access is 1320 * granted, SEERDY will go high. We use a 1 second 1321 * timeout which should be near 1 second more than 1322 * is needed. Reason: after the chip reset, there 1323 * should be no contention. 1324 */ 1325 SEEPROM_OUTB(sd, sd->sd_MS); 1326 wait = 1000; /* 1 second timeout in msec */ 1327 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1328 DELAY(1000); /* delay 1 msec */ 1329 } 1330 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1331 SEEPROM_OUTB(sd, 0); 1332 return (0); 1333 } 1334 return(1); 1335 } 1336 1337 static void 1338 release_seeprom(sd) 1339 struct seeprom_descriptor *sd; 1340 { 1341 /* Release access to the memory port and the serial EEPROM. */ 1342 SEEPROM_OUTB(sd, 0); 1343 } 1344 1345 static void 1346 write_brdctl(ahc, value) 1347 struct ahc_softc *ahc; 1348 u_int8_t value; 1349 { 1350 u_int8_t brdctl; 1351 1352 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1353 brdctl = BRDSTB; 1354 if (ahc->channel == 'B') 1355 brdctl |= BRDCS; 1356 } else if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7890) { 1357 brdctl = 0; 1358 } else { 1359 brdctl = BRDSTB|BRDCS; 1360 } 1361 ahc_outb(ahc, BRDCTL, brdctl); 1362 brdctl |= value; 1363 ahc_outb(ahc, BRDCTL, brdctl); 1364 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7890) 1365 brdctl |= BRDSTB_ULTRA2; 1366 else 1367 brdctl &= ~BRDSTB; 1368 ahc_outb(ahc, BRDCTL, brdctl); 1369 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7890) 1370 brdctl = 0; 1371 else 1372 brdctl &= ~BRDCS; 1373 ahc_outb(ahc, BRDCTL, brdctl); 1374 } 1375 1376 static u_int8_t 1377 read_brdctl(ahc) 1378 struct ahc_softc *ahc; 1379 { 1380 u_int8_t brdctl; 1381 u_int8_t value; 1382 1383 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1384 brdctl = BRDRW; 1385 if (ahc->channel == 'B') 1386 brdctl |= BRDCS; 1387 } else if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7890) { 1388 brdctl = BRDRW_ULTRA2; 1389 } else { 1390 brdctl = BRDRW|BRDCS; 1391 } 1392 ahc_outb(ahc, BRDCTL, brdctl); 1393 value = ahc_inb(ahc, BRDCTL); 1394 ahc_outb(ahc, BRDCTL, 0); 1395 return (value); 1396 } 1397 1398 #define DPE 0x80 1399 #define SSE 0x40 1400 #define RMA 0x20 1401 #define RTA 0x10 1402 #define STA 0x08 1403 #define DPR 0x01 1404 1405 void 1406 ahc_pci_intr(struct ahc_softc *ahc) 1407 { 1408 u_int8_t status1; 1409 1410 status1 = pci_read_config(ahc->device, PCIR_STATUS + 1, /*bytes*/1); 1411 1412 if (status1 & DPE) { 1413 printf("%s: Data Parity Error Detected during address " 1414 "or write data phase\n", ahc_name(ahc)); 1415 } 1416 if (status1 & SSE) { 1417 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1418 } 1419 if (status1 & RMA) { 1420 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1421 } 1422 if (status1 & RTA) { 1423 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1424 } 1425 if (status1 & STA) { 1426 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1427 } 1428 if (status1 & DPR) { 1429 printf("%s: Data Parity Error has been reported via PERR#\n", 1430 ahc_name(ahc)); 1431 } 1432 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1433 printf("%s: Latched PCIERR interrupt with " 1434 "no status bits set\n", ahc_name(ahc)); 1435 } 1436 pci_write_config(ahc->device, PCIR_STATUS + 1, status1, /*bytes*/1); 1437 1438 if (status1 & (DPR|RMA|RTA)) { 1439 ahc_outb(ahc, CLRINT, CLRPARERR); 1440 } 1441 } 1442 1443 static int 1444 ahc_aic7850_setup(device_t dev, char *channel, ahc_chip *chip, 1445 ahc_feature *features, ahc_flag *flags) 1446 { 1447 *channel = 'A'; 1448 *chip = AHC_AIC7850; 1449 *features = AHC_AIC7850_FE; 1450 return (0); 1451 } 1452 1453 static int 1454 ahc_aic7860_setup(device_t dev, char *channel, ahc_chip *chip, 1455 ahc_feature *features, ahc_flag *flags) 1456 { 1457 *channel = 'A'; 1458 *chip = AHC_AIC7860; 1459 *features = AHC_AIC7860_FE; 1460 return (0); 1461 } 1462 1463 static int 1464 ahc_aic7870_setup(device_t dev, char *channel, ahc_chip *chip, 1465 ahc_feature *features, ahc_flag *flags) 1466 { 1467 *channel = 'A'; 1468 *chip = AHC_AIC7870; 1469 *features = AHC_AIC7870_FE; 1470 return (0); 1471 } 1472 1473 static int 1474 ahc_aha394X_setup(device_t dev, char *channel, ahc_chip *chip, 1475 ahc_feature *features, ahc_flag *flags) 1476 { 1477 int error; 1478 1479 error = ahc_aic7870_setup(dev, channel, chip, features, flags); 1480 if (error == 0) 1481 error = ahc_aha394XX_setup(dev, channel, chip, features, flags); 1482 return (error); 1483 } 1484 1485 static int 1486 ahc_aha398X_setup(device_t dev, char *channel, ahc_chip *chip, 1487 ahc_feature *features, ahc_flag *flags) 1488 { 1489 int error; 1490 1491 error = ahc_aic7870_setup(dev, channel, chip, features, flags); 1492 if (error == 0) 1493 error = ahc_aha398XX_setup(dev, channel, chip, features, flags); 1494 return (error); 1495 } 1496 1497 static int 1498 ahc_aic7880_setup(device_t dev, char *channel, ahc_chip *chip, 1499 ahc_feature *features, ahc_flag *flags) 1500 { 1501 *channel = 'A'; 1502 *chip = AHC_AIC7880; 1503 *features = AHC_AIC7880_FE; 1504 return (0); 1505 } 1506 1507 static int 1508 ahc_aha394XU_setup(device_t dev, char *channel, ahc_chip *chip, 1509 ahc_feature *features, ahc_flag *flags) 1510 { 1511 int error; 1512 1513 error = ahc_aic7880_setup(dev, channel, chip, features, flags); 1514 if (error == 0) 1515 error = ahc_aha394XX_setup(dev, channel, chip, features, flags); 1516 return (error); 1517 } 1518 1519 static int 1520 ahc_aha398XU_setup(device_t dev, char *channel, ahc_chip *chip, 1521 ahc_feature *features, ahc_flag *flags) 1522 { 1523 int error; 1524 1525 error = ahc_aic7880_setup(dev, channel, chip, features, flags); 1526 if (error == 0) 1527 error = ahc_aha398XX_setup(dev, channel, chip, features, flags); 1528 return (error); 1529 } 1530 1531 static int 1532 ahc_aic7890_setup(device_t dev, char *channel, ahc_chip *chip, 1533 ahc_feature *features, ahc_flag *flags) 1534 { 1535 *channel = 'A'; 1536 *chip = AHC_AIC7890; 1537 *features = AHC_AIC7890_FE; 1538 *flags |= AHC_NEWEEPROM_FMT; 1539 return (0); 1540 } 1541 1542 static int 1543 ahc_aic7895_setup(device_t dev, char *channel, ahc_chip *chip, 1544 ahc_feature *features, ahc_flag *flags) 1545 { 1546 u_int32_t devconfig; 1547 1548 *channel = pci_get_function(dev) == 1 ? 'B' : 'A'; 1549 *chip = AHC_AIC7895; 1550 *features = AHC_AIC7895_FE; 1551 *flags |= AHC_NEWEEPROM_FMT; 1552 devconfig = pci_read_config(dev, DEVCONFIG, /*bytes*/4); 1553 devconfig &= ~SCBSIZE32; 1554 pci_write_config(dev, DEVCONFIG, devconfig, /*bytes*/4); 1555 return (0); 1556 } 1557 1558 static int 1559 ahc_aic7896_setup(device_t dev, char *channel, ahc_chip *chip, 1560 ahc_feature *features, ahc_flag *flags) 1561 { 1562 *channel = pci_get_function(dev) == 1 ? 'B' : 'A'; 1563 *chip = AHC_AIC7896; 1564 *features = AHC_AIC7896_FE; 1565 *flags |= AHC_NEWEEPROM_FMT; 1566 return (0); 1567 } 1568 1569 static int 1570 ahc_raid_setup(device_t dev, char *channel, ahc_chip *chip, 1571 ahc_feature *features, ahc_flag *flags) 1572 { 1573 printf("RAID functionality unsupported\n"); 1574 return (ENXIO); 1575 } 1576 1577 static int 1578 ahc_aha394XX_setup(device_t dev, char *channel, ahc_chip *chip, 1579 ahc_feature *features, ahc_flag *flags) 1580 { 1581 switch (pci_get_slot(dev)) { 1582 case AHC_394X_SLOT_CHANNEL_A: 1583 *channel = 'A'; 1584 break; 1585 case AHC_394X_SLOT_CHANNEL_B: 1586 *channel = 'B'; 1587 break; 1588 default: 1589 printf("adapter at unexpected slot %d\n" 1590 "unable to map to a channel\n", 1591 pci_get_slot(dev)); 1592 } 1593 return (0); 1594 } 1595 1596 static int 1597 ahc_aha398XX_setup(device_t dev, char *channel, ahc_chip *chip, 1598 ahc_feature *features, ahc_flag *flags) 1599 { 1600 switch (pci_get_slot(dev)) { 1601 case AHC_398X_SLOT_CHANNEL_A: 1602 *channel = 'A'; 1603 break; 1604 case AHC_398X_SLOT_CHANNEL_B: 1605 *channel = 'B'; 1606 break; 1607 case AHC_398X_SLOT_CHANNEL_C: 1608 *channel = 'C'; 1609 break; 1610 default: 1611 printf("adapter at unexpected slot %d\n" 1612 "unable to map to a channel\n", 1613 pci_get_slot(dev)); 1614 } 1615 *flags |= AHC_LARGE_SEEPROM; 1616 return (0); 1617 } 1618 1619 #endif /* NPCI > 0 */ 1620