1 /* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1995, 1996, 1997, 1998 Justin T. Gibbs 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Where this Software is combined with software released under the terms of 19 * the GNU Public License ("GPL") and the terms of the GPL would require the 20 * combined work to also be released under the terms of the GPL, the terms 21 * and conditions of this License will apply in addition to those of the 22 * GPL with the exception of any terms or conditions of this License that 23 * conflict with, or are expressly prohibited by, the GPL. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $FreeBSD$ 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/bus.h> 45 46 #include <pci/pcireg.h> 47 #include <pci/pcivar.h> 48 49 #include <machine/bus_memio.h> 50 #include <machine/bus_pio.h> 51 #include <machine/bus.h> 52 #include <machine/resource.h> 53 #include <machine/clock.h> 54 #include <sys/rman.h> 55 56 #include <cam/cam.h> 57 #include <cam/cam_ccb.h> 58 #include <cam/cam_sim.h> 59 #include <cam/cam_xpt_sim.h> 60 61 #include <cam/scsi/scsi_all.h> 62 63 #include <dev/aic7xxx/aic7xxx.h> 64 #include <dev/aic7xxx/93cx6.h> 65 66 #include <aic7xxx_reg.h> 67 68 #define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ 69 #define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 70 71 static __inline u_int64_t 72 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 73 { 74 u_int64_t id; 75 76 id = subvendor 77 | (subdevice << 16) 78 | ((u_int64_t)vendor << 32) 79 | ((u_int64_t)device << 48); 80 81 return (id); 82 } 83 84 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 85 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 86 #define ID_AIC7850 0x5078900400000000ull 87 #define ID_AHA_2910_15_20_30C 0x5078900478509004ull 88 #define ID_AIC7855 0x5578900400000000ull 89 #define ID_AIC7859 0x3860900400000000ull 90 #define ID_AHA_2930CU 0x3860900438699004ull 91 #define ID_AIC7860 0x6078900400000000ull 92 #define ID_AIC7860C 0x6078900478609004ull 93 #define ID_AHA_2940AU_0 0x6178900400000000ull 94 #define ID_AHA_2940AU_1 0x6178900478619004ull 95 #define ID_AHA_2940AU_CN 0x2178900478219004ull 96 #define ID_AHA_2930C_VAR 0x6038900438689004ull 97 98 #define ID_AIC7870 0x7078900400000000ull 99 #define ID_AHA_2940 0x7178900400000000ull 100 #define ID_AHA_3940 0x7278900400000000ull 101 #define ID_AHA_398X 0x7378900400000000ull 102 #define ID_AHA_2944 0x7478900400000000ull 103 #define ID_AHA_3944 0x7578900400000000ull 104 105 #define ID_AIC7880 0x8078900400000000ull 106 #define ID_AIC7880_B 0x8078900478809004ull 107 #define ID_AHA_2940U 0x8178900400000000ull 108 #define ID_AHA_3940U 0x8278900400000000ull 109 #define ID_AHA_2944U 0x8478900400000000ull 110 #define ID_AHA_3944U 0x8578900400000000ull 111 #define ID_AHA_398XU 0x8378900400000000ull 112 #define ID_AHA_4944U 0x8678900400000000ull 113 #define ID_AHA_2940UB 0x8178900478819004ull 114 #define ID_AHA_2930U 0x8878900478889004ull 115 #define ID_AHA_2940U_PRO 0x8778900478879004ull 116 #define ID_AHA_2940U_CN 0x0078900478009004ull 117 118 #define ID_AIC7895 0x7895900478959004ull 119 #define ID_AIC7895_RAID_PORT 0x7893900478939004ull 120 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 121 #define ID_AHA_3940AU 0x7895900478929004ull 122 #define ID_AHA_3944AU 0x7895900478949004ull 123 124 #define ID_AIC7890 0x001F9005000F9005ull 125 #define ID_AHA_2930U2 0x0011900501819005ull 126 #define ID_AHA_2940U2B 0x00109005A1009005ull 127 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 128 #define ID_AHA_2940U2 0x00109005A1809005ull 129 #define ID_AHA_2950U2B 0x00109005E1009005ull 130 131 #define ID_AIC7896 0x005F9005FFFF9005ull 132 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 133 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 134 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 135 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 136 137 #define ID_AIC7810 0x1078900400000000ull 138 #define ID_AIC7815 0x1578900400000000ull 139 140 typedef int (ahc_device_setup_t)(device_t, char *, ahc_chip *, 141 ahc_feature *, ahc_flag *); 142 143 static ahc_device_setup_t ahc_aic7850_setup; 144 static ahc_device_setup_t ahc_aic7855_setup; 145 static ahc_device_setup_t ahc_aic7859_setup; 146 static ahc_device_setup_t ahc_aic7860_setup; 147 static ahc_device_setup_t ahc_aic7870_setup; 148 static ahc_device_setup_t ahc_aha394X_setup; 149 static ahc_device_setup_t ahc_aha398X_setup; 150 static ahc_device_setup_t ahc_aic7880_setup; 151 static ahc_device_setup_t ahc_aha394XU_setup; 152 static ahc_device_setup_t ahc_aha398XU_setup; 153 static ahc_device_setup_t ahc_aic7890_setup; 154 static ahc_device_setup_t ahc_aic7895_setup; 155 static ahc_device_setup_t ahc_aic7896_setup; 156 static ahc_device_setup_t ahc_raid_setup; 157 static ahc_device_setup_t ahc_aha394XX_setup; 158 static ahc_device_setup_t ahc_aha398XX_setup; 159 160 struct ahc_pci_identity { 161 u_int64_t full_id; 162 u_int64_t id_mask; 163 char *name; 164 ahc_device_setup_t *setup; 165 }; 166 167 struct ahc_pci_identity ahc_pci_ident_table [] = 168 { 169 /* aic7850 based controllers */ 170 { 171 ID_AHA_2910_15_20_30C, 172 ID_ALL_MASK, 173 "Adaptec 2910/15/20/30C SCSI adapter", 174 ahc_aic7850_setup 175 }, 176 /* aic7859 based controllers */ 177 { 178 ID_AHA_2930CU, 179 ID_ALL_MASK, 180 "Adaptec 2930CU SCSI adapter", 181 ahc_aic7859_setup 182 }, 183 /* aic7860 based controllers */ 184 { 185 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 186 ID_DEV_VENDOR_MASK, 187 "Adaptec 2940A Ultra SCSI adapter", 188 ahc_aic7860_setup 189 }, 190 { 191 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 192 ID_DEV_VENDOR_MASK, 193 "Adaptec 2940A/CN Ultra SCSI adapter", 194 ahc_aic7860_setup 195 }, 196 { 197 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 198 ID_DEV_VENDOR_MASK, 199 "Adaptec 2930C SCSI adapter (VAR)", 200 ahc_aic7860_setup 201 }, 202 /* aic7870 based controllers */ 203 { 204 ID_AHA_2940, 205 ID_ALL_MASK, 206 "Adaptec 2940 SCSI adapter", 207 ahc_aic7870_setup 208 }, 209 { 210 ID_AHA_3940, 211 ID_ALL_MASK, 212 "Adaptec 3940 SCSI adapter", 213 ahc_aha394X_setup 214 }, 215 { 216 ID_AHA_398X, 217 ID_ALL_MASK, 218 "Adaptec 398X SCSI RAID adapter", 219 ahc_aha398X_setup 220 }, 221 { 222 ID_AHA_2944, 223 ID_ALL_MASK, 224 "Adaptec 2944 SCSI adapter", 225 ahc_aic7870_setup 226 }, 227 { 228 ID_AHA_3944, 229 ID_ALL_MASK, 230 "Adaptec 3944 SCSI adapter", 231 ahc_aha394X_setup 232 }, 233 /* aic7880 based controllers */ 234 { 235 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 236 ID_DEV_VENDOR_MASK, 237 "Adaptec 2940 Ultra SCSI adapter", 238 ahc_aic7880_setup 239 }, 240 { 241 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 242 ID_DEV_VENDOR_MASK, 243 "Adaptec 3940 Ultra SCSI adapter", 244 ahc_aha394XU_setup 245 }, 246 { 247 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 248 ID_DEV_VENDOR_MASK, 249 "Adaptec 2944 Ultra SCSI adapter", 250 ahc_aic7880_setup 251 }, 252 { 253 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 254 ID_DEV_VENDOR_MASK, 255 "Adaptec 3944 Ultra SCSI adapter", 256 ahc_aha394XU_setup 257 }, 258 { 259 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 260 ID_DEV_VENDOR_MASK, 261 "Adaptec 398X Ultra SCSI RAID adapter", 262 ahc_aha398XU_setup 263 }, 264 { 265 /* XXX Don't know the slot numbers so can't identify channels */ 266 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 267 ID_DEV_VENDOR_MASK, 268 "Adaptec 4944 Ultra SCSI adapter", 269 ahc_aic7880_setup 270 }, 271 { 272 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 273 ID_DEV_VENDOR_MASK, 274 "Adaptec 2930 Ultra SCSI adapter", 275 ahc_aic7880_setup 276 }, 277 { 278 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 279 ID_DEV_VENDOR_MASK, 280 "Adaptec 2940 Pro Ultra SCSI adapter", 281 ahc_aic7880_setup 282 }, 283 { 284 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 285 ID_DEV_VENDOR_MASK, 286 "Adaptec 2940/CN Ultra SCSI adapter", 287 ahc_aic7880_setup 288 }, 289 /* aic7890 based controllers */ 290 { 291 ID_AHA_2930U2, 292 ID_ALL_MASK, 293 "Adaptec 2930 Ultra2 SCSI adapter", 294 ahc_aic7890_setup 295 }, 296 { 297 ID_AHA_2940U2B, 298 ID_ALL_MASK, 299 "Adaptec 2940B Ultra2 SCSI adapter", 300 ahc_aic7890_setup 301 }, 302 { 303 ID_AHA_2940U2_OEM, 304 ID_ALL_MASK, 305 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 306 ahc_aic7890_setup 307 }, 308 { 309 ID_AHA_2940U2, 310 ID_ALL_MASK, 311 "Adaptec 2940 Ultra2 SCSI adapter", 312 ahc_aic7890_setup 313 }, 314 { 315 ID_AHA_2950U2B, 316 ID_ALL_MASK, 317 "Adaptec 2950 Ultra2 SCSI adapter", 318 ahc_aic7890_setup 319 }, 320 /* aic7895 based controllers */ 321 { 322 ID_AHA_2940U_DUAL, 323 ID_ALL_MASK, 324 "Adaptec 2940/DUAL Ultra SCSI adapter", 325 ahc_aic7895_setup 326 }, 327 { 328 ID_AHA_3940AU, 329 ID_ALL_MASK, 330 "Adaptec 3940A Ultra SCSI adapter", 331 ahc_aic7895_setup 332 }, 333 { 334 ID_AHA_3944AU, 335 ID_ALL_MASK, 336 "Adaptec 3944A Ultra SCSI adapter", 337 ahc_aic7895_setup 338 }, 339 /* aic7896/97 based controllers */ 340 { 341 ID_AHA_3950U2B_0, 342 ID_ALL_MASK, 343 "Adaptec 3950B Ultra2 SCSI adapter", 344 ahc_aic7896_setup 345 }, 346 { 347 ID_AHA_3950U2B_1, 348 ID_ALL_MASK, 349 "Adaptec 3950B Ultra2 SCSI adapter", 350 ahc_aic7896_setup 351 }, 352 { 353 ID_AHA_3950U2D_0, 354 ID_ALL_MASK, 355 "Adaptec 3950D Ultra2 SCSI adapter", 356 ahc_aic7896_setup 357 }, 358 { 359 ID_AHA_3950U2D_1, 360 ID_ALL_MASK, 361 "Adaptec 3950D Ultra2 SCSI adapter", 362 ahc_aic7896_setup 363 }, 364 /* Generic chip probes for devices we don't know 'exactly' */ 365 { 366 ID_AIC7850 & ID_DEV_VENDOR_MASK, 367 ID_DEV_VENDOR_MASK, 368 "Adaptec aic7850 SCSI adapter", 369 ahc_aic7850_setup 370 }, 371 { 372 ID_AIC7855 & ID_DEV_VENDOR_MASK, 373 ID_DEV_VENDOR_MASK, 374 "Adaptec aic7855 SCSI adapter", 375 ahc_aic7855_setup 376 }, 377 { 378 ID_AIC7859 & ID_DEV_VENDOR_MASK, 379 ID_DEV_VENDOR_MASK, 380 "Adaptec aic7859 SCSI adapter", 381 ahc_aic7859_setup 382 }, 383 { 384 ID_AIC7860 & ID_DEV_VENDOR_MASK, 385 ID_DEV_VENDOR_MASK, 386 "Adaptec aic7860 SCSI adapter", 387 ahc_aic7860_setup 388 }, 389 { 390 ID_AIC7870 & ID_DEV_VENDOR_MASK, 391 ID_DEV_VENDOR_MASK, 392 "Adaptec aic7870 SCSI adapter", 393 ahc_aic7870_setup 394 }, 395 { 396 ID_AIC7880 & ID_DEV_VENDOR_MASK, 397 ID_DEV_VENDOR_MASK, 398 "Adaptec aic7880 Ultra SCSI adapter", 399 ahc_aic7880_setup 400 }, 401 { 402 ID_AIC7890 & ID_DEV_VENDOR_MASK, 403 ID_DEV_VENDOR_MASK, 404 "Adaptec aic7890/91 Ultra2 SCSI adapter", 405 ahc_aic7890_setup 406 }, 407 { 408 ID_AIC7895 & ID_DEV_VENDOR_MASK, 409 ID_DEV_VENDOR_MASK, 410 "Adaptec aic7895 Ultra SCSI adapter", 411 ahc_aic7895_setup 412 }, 413 { 414 ID_AIC7895_RAID_PORT & ID_DEV_VENDOR_MASK, 415 ID_DEV_VENDOR_MASK, 416 "Adaptec aic7895 Ultra SCSI adapter (RAID PORT)", 417 ahc_aic7895_setup 418 }, 419 { 420 ID_AIC7896 & ID_DEV_VENDOR_MASK, 421 ID_DEV_VENDOR_MASK, 422 "Adaptec aic7896/97 Ultra2 SCSI adapter", 423 ahc_aic7896_setup 424 }, 425 { 426 ID_AIC7810 & ID_DEV_VENDOR_MASK, 427 ID_DEV_VENDOR_MASK, 428 "Adaptec aic7810 RAID memory controller", 429 ahc_raid_setup 430 }, 431 { 432 ID_AIC7815 & ID_DEV_VENDOR_MASK, 433 ID_DEV_VENDOR_MASK, 434 "Adaptec aic7815 RAID memory controller", 435 ahc_raid_setup 436 } 437 }; 438 439 static const int ahc_num_pci_devs = 440 sizeof(ahc_pci_ident_table) / sizeof(*ahc_pci_ident_table); 441 442 #define AHC_394X_SLOT_CHANNEL_A 4 443 #define AHC_394X_SLOT_CHANNEL_B 5 444 445 #define AHC_398X_SLOT_CHANNEL_A 4 446 #define AHC_398X_SLOT_CHANNEL_B 8 447 #define AHC_398X_SLOT_CHANNEL_C 12 448 449 #define DEVCONFIG 0x40 450 #define SCBSIZE32 0x00010000ul /* aic789X only */ 451 #define MPORTMODE 0x00000400ul /* aic7870 only */ 452 #define RAMPSM 0x00000200ul /* aic7870 only */ 453 #define VOLSENSE 0x00000100ul 454 #define SCBRAMSEL 0x00000080ul 455 #define MRDCEN 0x00000040ul 456 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 457 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 458 #define BERREN 0x00000008ul 459 #define DACEN 0x00000004ul 460 #define STPWLEVEL 0x00000002ul 461 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 462 463 #define CSIZE_LATTIME 0x0c 464 #define CACHESIZE 0x0000003ful /* only 5 bits */ 465 #define LATTIME 0x0000ff00ul 466 467 static struct ahc_pci_identity *ahc_find_pci_device(device_t dev); 468 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 469 static void configure_termination(struct ahc_softc *ahc, 470 struct seeprom_descriptor *sd, 471 u_int adapter_control, 472 u_int *sxfrctl1); 473 474 static void ahc_ultra2_term_detect(struct ahc_softc *ahc, 475 int *enableSEC_low, 476 int *enableSEC_high, 477 int *enablePRI_low, 478 int *enablePRI_high, 479 int *eeprom_present); 480 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 481 int *internal68_present, 482 int *externalcable_present, 483 int *eeprom_present); 484 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 485 int *externalcable_present, 486 int *eeprom_present); 487 static int acquire_seeprom(struct ahc_softc *ahc, 488 struct seeprom_descriptor *sd); 489 static void release_seeprom(struct seeprom_descriptor *sd); 490 static void write_brdctl(struct ahc_softc *ahc, u_int8_t value); 491 static u_int8_t read_brdctl(struct ahc_softc *ahc); 492 493 static struct ahc_softc *first_398X; 494 495 static int ahc_pci_probe(device_t dev); 496 static int ahc_pci_attach(device_t dev); 497 498 /* Exported for use in the ahc_intr routine */ 499 void ahc_pci_intr(struct ahc_softc *ahc); 500 501 static device_method_t ahc_pci_methods[] = { 502 /* Device interface */ 503 DEVMETHOD(device_probe, ahc_pci_probe), 504 DEVMETHOD(device_attach, ahc_pci_attach), 505 { 0, 0 } 506 }; 507 508 static driver_t ahc_pci_driver = { 509 "ahc", 510 ahc_pci_methods, 511 sizeof(struct ahc_softc) 512 }; 513 514 static devclass_t ahc_devclass; 515 516 DRIVER_MODULE(ahc, pci, ahc_pci_driver, ahc_devclass, 0, 0); 517 518 static struct ahc_pci_identity * 519 ahc_find_pci_device(device_t dev) 520 { 521 u_int64_t full_id; 522 struct ahc_pci_identity *entry; 523 u_int i; 524 525 full_id = ahc_compose_id(pci_get_device(dev), 526 pci_get_vendor(dev), 527 pci_get_subdevice(dev), 528 pci_get_subvendor(dev)); 529 530 for (i = 0; i < ahc_num_pci_devs; i++) { 531 entry = &ahc_pci_ident_table[i]; 532 if (entry->full_id == (full_id & entry->id_mask)) 533 return (entry); 534 } 535 return (NULL); 536 } 537 538 static int 539 ahc_pci_probe(device_t dev) 540 { 541 struct ahc_pci_identity *entry; 542 543 entry = ahc_find_pci_device(dev); 544 if (entry != NULL) { 545 device_set_desc(dev, entry->name); 546 return (0); 547 } 548 return (ENXIO); 549 } 550 551 static int 552 ahc_pci_attach(device_t dev) 553 { 554 bus_dma_tag_t parent_dmat; 555 struct ahc_pci_identity *entry; 556 struct resource *regs; 557 struct ahc_softc *ahc; 558 u_int command; 559 struct scb_data *shared_scb_data; 560 ahc_chip ahc_t = AHC_NONE; 561 ahc_feature ahc_fe = AHC_FENONE; 562 ahc_flag ahc_f = AHC_FNONE; 563 int regs_type; 564 int regs_id; 565 u_int our_id = 0; 566 u_int sxfrctl1; 567 u_int scsiseq; 568 int error; 569 int zero; 570 char channel; 571 572 shared_scb_data = NULL; 573 command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1); 574 entry = ahc_find_pci_device(dev); 575 if (entry == NULL) 576 return (ENXIO); 577 error = entry->setup(dev, &channel, &ahc_t, &ahc_fe, &ahc_f); 578 if (error != 0) 579 return (error); 580 581 regs = NULL; 582 regs_type = 0; 583 regs_id = 0; 584 #ifdef AHC_ALLOW_MEMIO 585 if ((command & PCIM_CMD_MEMEN) != 0) { 586 regs_type = SYS_RES_MEMORY; 587 regs_id = AHC_PCI_MEMADDR; 588 regs = bus_alloc_resource(dev, regs_type, 589 ®s_id, 0, ~0, 1, RF_ACTIVE); 590 } 591 #endif 592 if (regs == NULL && (command & PCI_COMMAND_IO_ENABLE) != 0) { 593 regs_type = SYS_RES_IOPORT; 594 regs_id = AHC_PCI_IOADDR; 595 regs = bus_alloc_resource(dev, regs_type, 596 ®s_id, 0, ~0, 1, RF_ACTIVE); 597 } 598 599 if (regs == NULL) { 600 device_printf(dev, "can't allocate register resources\n"); 601 return (ENOMEM); 602 } 603 604 /* Ensure busmastering is enabled */ 605 command |= PCIM_CMD_BUSMASTEREN; 606 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1); 607 608 /* Allocate a dmatag for our SCB DMA maps */ 609 /* XXX Should be a child of the PCI bus dma tag */ 610 error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1, 611 /*boundary*/0, 612 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 613 /*highaddr*/BUS_SPACE_MAXADDR, 614 /*filter*/NULL, /*filterarg*/NULL, 615 /*maxsize*/MAXBSIZE, /*nsegments*/AHC_NSEG, 616 /*maxsegsz*/AHC_MAXTRANSFER_SIZE, 617 /*flags*/BUS_DMA_ALLOCNOW, &parent_dmat); 618 619 if (error != 0) { 620 printf("ahc_pci_attach: Could not allocate DMA tag " 621 "- error %d\n", error); 622 return (ENOMEM); 623 } 624 625 /* On all PCI adapters, we allow SCB paging */ 626 ahc_f |= AHC_PAGESCBS; 627 if ((ahc = ahc_alloc(dev, regs, regs_type, regs_id, parent_dmat, 628 ahc_t|AHC_PCI, ahc_fe, ahc_f, 629 shared_scb_data)) == NULL) 630 return (ENOMEM); 631 632 ahc->channel = channel; 633 634 /* Store our PCI bus information for use in our PCI error handler */ 635 ahc->device = dev; 636 637 /* Remeber how the card was setup in case there is no SEEPROM */ 638 ahc_outb(ahc, HCNTRL, ahc->pause); 639 if ((ahc->features & AHC_ULTRA2) != 0) 640 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 641 else 642 our_id = ahc_inb(ahc, SCSIID) & OID; 643 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 644 scsiseq = ahc_inb(ahc, SCSISEQ); 645 646 if (ahc_reset(ahc) != 0) { 647 /* Failed */ 648 ahc_free(ahc); 649 return (ENXIO); 650 } 651 652 /* 653 * Take a look to see if we have external SRAM. 654 * We currently do not attempt to use SRAM that is 655 * shared among multiple controllers. 656 */ 657 if ((ahc->features & AHC_ULTRA2) != 0) { 658 u_int dscommand0; 659 660 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 661 if ((dscommand0 & RAMPS) != 0) { 662 u_int32_t devconfig; 663 664 devconfig = pci_read_config(dev, DEVCONFIG, /*bytes*/4); 665 if ((devconfig & MPORTMODE) != 0) { 666 /* Single user mode */ 667 668 /* 669 * XXX Assume 9bit SRAM and enable 670 * parity checking 671 */ 672 devconfig |= EXTSCBPEN; 673 pci_write_config(dev, DEVCONFIG, 674 devconfig, /*bytes*/4); 675 676 /* 677 * Set the bank select apropriately. 678 */ 679 if (ahc->channel == 'B') 680 ahc_outb(ahc, SCBBADDR, 1); 681 else 682 ahc_outb(ahc, SCBBADDR, 0); 683 684 /* Select external SCB SRAM */ 685 dscommand0 &= ~INTSCBRAMSEL; 686 ahc_outb(ahc, DSCOMMAND0, dscommand0); 687 688 if (ahc_probe_scbs(ahc) == 0) { 689 /* External ram isn't really there */ 690 dscommand0 |= INTSCBRAMSEL; 691 ahc_outb(ahc, DSCOMMAND0, dscommand0); 692 } else if (bootverbose) 693 printf("%s: External SRAM bank%d\n", 694 ahc_name(ahc), 695 ahc->channel == 'B' ? 1 : 0); 696 } 697 698 } 699 } else if ((ahc->chip & AHC_CHIPID_MASK) >= AHC_AIC7870) { 700 u_int32_t devconfig; 701 702 devconfig = pci_read_config(dev, DEVCONFIG, /*bytes*/4); 703 if ((devconfig & RAMPSM) != 0 704 && (devconfig & MPORTMODE) != 0) { 705 706 /* XXX Assume 9bit SRAM and enable parity checking */ 707 devconfig |= EXTSCBPEN; 708 709 /* XXX Assume fast SRAM */ 710 devconfig &= ~EXTSCBTIME; 711 712 /* 713 * Set the bank select apropriately. 714 */ 715 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 716 if (ahc->channel == 'B') 717 ahc_outb(ahc, SCBBADDR, 1); 718 else 719 ahc_outb(ahc, SCBBADDR, 0); 720 } 721 722 /* Select external SRAM */ 723 devconfig &= ~SCBRAMSEL; 724 pci_write_config(dev, DEVCONFIG, devconfig, /*bytes*/4); 725 726 if (ahc_probe_scbs(ahc) == 0) { 727 /* External ram isn't really there */ 728 devconfig |= SCBRAMSEL; 729 pci_write_config(dev, DEVCONFIG, 730 devconfig, /*bytes*/4); 731 } else if (bootverbose) 732 printf("%s: External SRAM bank%d\n", 733 ahc_name(ahc), 734 ahc->channel == 'B' ? 1 : 0); 735 } 736 } 737 738 zero = 0; 739 ahc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &zero, 740 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 741 if (ahc->irq == NULL) { 742 ahc_free(ahc); 743 return (ENOMEM); 744 } 745 746 ahc->irq_res_type = SYS_RES_IRQ; 747 748 /* 749 * Do aic7880/aic7870/aic7860/aic7850 specific initialization 750 */ 751 { 752 u_int8_t sblkctl; 753 char *id_string; 754 755 switch(ahc_t) { 756 case AHC_AIC7896: 757 { 758 u_int dscommand0; 759 760 /* 761 * DPARCKEN doesn't work correctly on 762 * some MBs so don't use it. 763 */ 764 id_string = "aic7896/97 "; 765 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 766 dscommand0 &= ~(USCBSIZE32|DPARCKEN); 767 dscommand0 |= CACHETHEN|MPARCKEN; 768 ahc_outb(ahc, DSCOMMAND0, dscommand0); 769 break; 770 } 771 case AHC_AIC7890: 772 { 773 u_int dscommand0; 774 775 /* 776 * DPARCKEN doesn't work correctly on 777 * some MBs so don't use it. 778 */ 779 id_string = "aic7890/91 "; 780 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 781 dscommand0 &= ~(USCBSIZE32|DPARCKEN); 782 dscommand0 |= CACHETHEN|MPARCKEN; 783 ahc_outb(ahc, DSCOMMAND0, dscommand0); 784 break; 785 } 786 case AHC_AIC7895: 787 id_string = "aic7895 "; 788 break; 789 case AHC_AIC7880: 790 id_string = "aic7880 "; 791 break; 792 case AHC_AIC7870: 793 id_string = "aic7870 "; 794 break; 795 case AHC_AIC7860: 796 id_string = "aic7860 "; 797 break; 798 case AHC_AIC7859: 799 id_string = "aic7859 "; 800 break; 801 case AHC_AIC7855: 802 id_string = "aic7855 "; 803 break; 804 case AHC_AIC7850: 805 id_string = "aic7850 "; 806 break; 807 default: 808 printf("ahc: Unknown controller type. Ignoring.\n"); 809 ahc_free(ahc); 810 return (ENXIO); 811 } 812 813 /* See if we have an SEEPROM and perform auto-term */ 814 check_extport(ahc, &sxfrctl1); 815 816 /* 817 * Take the LED out of diagnostic mode 818 */ 819 sblkctl = ahc_inb(ahc, SBLKCTL); 820 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 821 822 /* 823 * I don't know where this is set in the SEEPROM or by the 824 * BIOS, so we default to 100% on Ultra or slower controllers 825 * and 75% on ULTRA2 controllers. 826 */ 827 if ((ahc->features & AHC_ULTRA2) != 0) { 828 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 829 } else { 830 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 831 } 832 833 if (ahc->flags & AHC_USEDEFAULTS) { 834 /* 835 * PCI Adapter default setup 836 * Should only be used if the adapter does not have 837 * an SEEPROM. 838 */ 839 /* See if someone else set us up already */ 840 if (scsiseq != 0) { 841 printf("%s: Using left over BIOS settings\n", 842 ahc_name(ahc)); 843 ahc->flags &= ~AHC_USEDEFAULTS; 844 } else { 845 /* 846 * Assume only one connector and always turn 847 * on termination. 848 */ 849 our_id = 0x07; 850 sxfrctl1 = STPWEN; 851 } 852 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 853 854 ahc->our_id = our_id; 855 } 856 857 printf("%s: %s", ahc_name(ahc), id_string); 858 } 859 860 /* 861 * Record our termination setting for the 862 * generic initialization routine. 863 */ 864 if ((sxfrctl1 & STPWEN) != 0) 865 ahc->flags |= AHC_TERM_ENB_A; 866 867 if (ahc_init(ahc)) { 868 ahc_free(ahc); 869 return (ENOMEM); 870 } 871 872 /* XXX Crude hack - fix sometime */ 873 if (ahc->flags & AHC_SHARED_SRAM) { 874 /* Only set this once we've successfully probed */ 875 if (shared_scb_data == NULL) 876 first_398X = ahc; 877 } 878 879 ahc_attach(ahc); 880 return (0); 881 } 882 883 /* 884 * Check the external port logic for a serial eeprom 885 * and termination/cable detection contrls. 886 */ 887 static void 888 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 889 { 890 struct seeprom_descriptor sd; 891 struct seeprom_config sc; 892 u_int scsi_conf; 893 u_int adapter_control; 894 int have_seeprom; 895 int have_autoterm; 896 897 sd.sd_tag = ahc->tag; 898 sd.sd_bsh = ahc->bsh; 899 sd.sd_control_offset = SEECTL; 900 sd.sd_status_offset = SEECTL; 901 sd.sd_dataout_offset = SEECTL; 902 903 /* 904 * For some multi-channel devices, the c46 is simply too 905 * small to work. For the other controller types, we can 906 * get our information from either SEEPROM type. Set the 907 * type to start our probe with accordingly. 908 */ 909 if (ahc->flags & AHC_LARGE_SEEPROM) 910 sd.sd_chip = C56_66; 911 else 912 sd.sd_chip = C46; 913 914 sd.sd_MS = SEEMS; 915 sd.sd_RDY = SEERDY; 916 sd.sd_CS = SEECS; 917 sd.sd_CK = SEECK; 918 sd.sd_DO = SEEDO; 919 sd.sd_DI = SEEDI; 920 921 have_seeprom = acquire_seeprom(ahc, &sd); 922 if (have_seeprom) { 923 924 if (bootverbose) 925 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 926 927 for (;;) { 928 bus_size_t start_addr; 929 930 start_addr = 32 * (ahc->channel - 'A'); 931 932 have_seeprom = read_seeprom(&sd, (u_int16_t *)&sc, 933 start_addr, sizeof(sc)/2); 934 935 if (have_seeprom) { 936 /* Check checksum */ 937 int i; 938 int maxaddr; 939 u_int32_t checksum; 940 u_int16_t *scarray; 941 942 maxaddr = (sizeof(sc)/2) - 1; 943 checksum = 0; 944 scarray = (u_int16_t *)≻ 945 946 for (i = 0; i < maxaddr; i++) 947 checksum = checksum + scarray[i]; 948 if (checksum == 0 949 || (checksum & 0xFFFF) != sc.checksum) { 950 if (bootverbose && sd.sd_chip == C56_66) 951 printf ("checksum error\n"); 952 have_seeprom = 0; 953 } else { 954 if (bootverbose) 955 printf("done.\n"); 956 break; 957 } 958 } 959 960 if (sd.sd_chip == C56_66) 961 break; 962 sd.sd_chip = C56_66; 963 } 964 } 965 966 if (!have_seeprom) { 967 if (bootverbose) 968 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 969 ahc->flags |= AHC_USEDEFAULTS; 970 } else { 971 /* 972 * Put the data we've collected down into SRAM 973 * where ahc_init will find it. 974 */ 975 int i; 976 int max_targ = sc.max_targets & CFMAXTARG; 977 u_int16_t discenable; 978 u_int16_t ultraenb; 979 980 discenable = 0; 981 ultraenb = 0; 982 if ((sc.adapter_control & CFULTRAEN) != 0) { 983 /* 984 * Determine if this adapter has a "newstyle" 985 * SEEPROM format. 986 */ 987 for (i = 0; i < max_targ; i++) { 988 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0){ 989 ahc->flags |= AHC_NEWEEPROM_FMT; 990 break; 991 } 992 } 993 } 994 995 for (i = 0; i < max_targ; i++) { 996 u_int scsirate; 997 u_int16_t target_mask; 998 999 target_mask = 0x01 << i; 1000 if (sc.device_flags[i] & CFDISC) 1001 discenable |= target_mask; 1002 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1003 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) 1004 ultraenb |= target_mask; 1005 } else if ((sc.adapter_control & CFULTRAEN) != 0) { 1006 ultraenb |= target_mask; 1007 } 1008 if ((sc.device_flags[i] & CFXFER) == 0x04 1009 && (ultraenb & target_mask) != 0) { 1010 /* Treat 10MHz as a non-ultra speed */ 1011 sc.device_flags[i] &= ~CFXFER; 1012 ultraenb &= ~target_mask; 1013 } 1014 if ((ahc->features & AHC_ULTRA2) != 0) { 1015 u_int offset; 1016 1017 if (sc.device_flags[i] & CFSYNCH) 1018 offset = MAX_OFFSET_ULTRA2; 1019 else 1020 offset = 0; 1021 ahc_outb(ahc, TARG_OFFSET + i, offset); 1022 1023 scsirate = (sc.device_flags[i] & CFXFER) 1024 | ((ultraenb & target_mask) 1025 ? 0x18 : 0x10); 1026 if (sc.device_flags[i] & CFWIDEB) 1027 scsirate |= WIDEXFER; 1028 } else { 1029 scsirate = (sc.device_flags[i] & CFXFER) << 4; 1030 if (sc.device_flags[i] & CFSYNCH) 1031 scsirate |= SOFS; 1032 if (sc.device_flags[i] & CFWIDEB) 1033 scsirate |= WIDEXFER; 1034 } 1035 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1036 } 1037 ahc->our_id = sc.brtime_id & CFSCSIID; 1038 1039 scsi_conf = (ahc->our_id & 0x7); 1040 if (sc.adapter_control & CFSPARITY) 1041 scsi_conf |= ENSPCHK; 1042 if (sc.adapter_control & CFRESETB) 1043 scsi_conf |= RESET_SCSI; 1044 1045 if (sc.bios_control & CFEXTEND) 1046 ahc->flags |= AHC_EXTENDED_TRANS_A; 1047 if (ahc->features & AHC_ULTRA 1048 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1049 /* Should we enable Ultra mode? */ 1050 if (!(sc.adapter_control & CFULTRAEN)) 1051 /* Treat us as a non-ultra card */ 1052 ultraenb = 0; 1053 } 1054 /* Set SCSICONF info */ 1055 ahc_outb(ahc, SCSICONF, scsi_conf); 1056 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1057 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1058 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1059 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1060 } 1061 1062 /* 1063 * Cards that have the external logic necessary to talk to 1064 * a SEEPROM, are almost certain to have the remaining logic 1065 * necessary for auto-termination control. This assumption 1066 * hasn't failed yet... 1067 */ 1068 have_autoterm = have_seeprom; 1069 if (have_seeprom) 1070 adapter_control = sc.adapter_control; 1071 else 1072 adapter_control = CFAUTOTERM; 1073 1074 /* 1075 * Some low-cost chips have SEEPROM and auto-term control built 1076 * in, instead of using a GAL. They can tell us directly 1077 * if the termination logic is enabled. 1078 */ 1079 if ((ahc->features & AHC_SPIOCAP) != 0) { 1080 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0) 1081 have_autoterm = TRUE; 1082 else 1083 have_autoterm = FALSE; 1084 } 1085 1086 if (have_autoterm) 1087 configure_termination(ahc, &sd, adapter_control, sxfrctl1); 1088 1089 release_seeprom(&sd); 1090 } 1091 1092 static void 1093 configure_termination(struct ahc_softc *ahc, 1094 struct seeprom_descriptor *sd, 1095 u_int adapter_control, 1096 u_int *sxfrctl1) 1097 { 1098 u_int8_t brddat; 1099 1100 brddat = 0; 1101 1102 /* 1103 * Update the settings in sxfrctl1 to match the 1104 *termination settings 1105 */ 1106 *sxfrctl1 = 0; 1107 1108 /* 1109 * SEECS must be on for the GALS to latch 1110 * the data properly. Be sure to leave MS 1111 * on or we will release the seeprom. 1112 */ 1113 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1114 if ((adapter_control & CFAUTOTERM) != 0 1115 || (ahc->features & AHC_ULTRA2) != 0) { 1116 int internal50_present; 1117 int internal68_present; 1118 int externalcable_present; 1119 int eeprom_present; 1120 int enableSEC_low; 1121 int enableSEC_high; 1122 int enablePRI_low; 1123 int enablePRI_high; 1124 1125 enableSEC_low = 0; 1126 enableSEC_high = 0; 1127 enablePRI_low = 0; 1128 enablePRI_high = 0; 1129 if (ahc->features & AHC_ULTRA2) { 1130 ahc_ultra2_term_detect(ahc, &enableSEC_low, 1131 &enableSEC_high, 1132 &enablePRI_low, 1133 &enablePRI_high, 1134 &eeprom_present); 1135 if ((adapter_control & CFSEAUTOTERM) == 0) { 1136 if (bootverbose) 1137 printf("%s: Manual SE Termination\n", 1138 ahc_name(ahc)); 1139 enableSEC_low = (adapter_control & CFSTERM); 1140 enableSEC_high = (adapter_control & CFWSTERM); 1141 } 1142 if ((adapter_control & CFAUTOTERM) == 0) { 1143 if (bootverbose) 1144 printf("%s: Manual LVD Termination\n", 1145 ahc_name(ahc)); 1146 enablePRI_low = enablePRI_high = 1147 (adapter_control & CFLVDSTERM); 1148 } 1149 /* Make the table calculations below happy */ 1150 internal50_present = 0; 1151 internal68_present = 1; 1152 externalcable_present = 1; 1153 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1154 aic785X_cable_detect(ahc, &internal50_present, 1155 &externalcable_present, 1156 &eeprom_present); 1157 } else { 1158 aic787X_cable_detect(ahc, &internal50_present, 1159 &internal68_present, 1160 &externalcable_present, 1161 &eeprom_present); 1162 } 1163 1164 if ((ahc->features & AHC_WIDE) == 0) 1165 internal68_present = 0; 1166 1167 if (bootverbose) { 1168 if ((ahc->features & AHC_ULTRA2) == 0) { 1169 printf("%s: internal 50 cable %s present, " 1170 "internal 68 cable %s present\n", 1171 ahc_name(ahc), 1172 internal50_present ? "is":"not", 1173 internal68_present ? "is":"not"); 1174 1175 printf("%s: external cable %s present\n", 1176 ahc_name(ahc), 1177 externalcable_present ? "is":"not"); 1178 } 1179 printf("%s: BIOS eeprom %s present\n", 1180 ahc_name(ahc), eeprom_present ? "is" : "not"); 1181 1182 } 1183 1184 /* 1185 * Now set the termination based on what 1186 * we found. 1187 * Flash Enable = BRDDAT7 1188 * Secondary High Term Enable = BRDDAT6 1189 * Secondary Low Term Enable = BRDDAT5 (7890) 1190 * Primary High Term Enable = BRDDAT4 (7890) 1191 */ 1192 if ((ahc->features & AHC_ULTRA2) == 0 1193 && (internal50_present != 0) 1194 && (internal68_present != 0) 1195 && (externalcable_present != 0)) { 1196 printf("%s: Illegal cable configuration!!. " 1197 "Only two connectors on the " 1198 "adapter may be used at a " 1199 "time!\n", ahc_name(ahc)); 1200 } 1201 1202 if ((ahc->features & AHC_WIDE) != 0 1203 && ((externalcable_present == 0) 1204 || (internal68_present == 0) 1205 || (enableSEC_high != 0))) { 1206 brddat |= BRDDAT6; 1207 if (bootverbose) 1208 printf("%s: %sHigh byte termination Enabled\n", 1209 ahc_name(ahc), 1210 enableSEC_high ? "Secondary " : ""); 1211 } 1212 1213 if (((internal50_present ? 1 : 0) 1214 + (internal68_present ? 1 : 0) 1215 + (externalcable_present ? 1 : 0)) <= 1 1216 || (enableSEC_low != 0)) { 1217 if ((ahc->features & AHC_ULTRA2) != 0) 1218 brddat |= BRDDAT5; 1219 else 1220 *sxfrctl1 |= STPWEN; 1221 if (bootverbose) 1222 printf("%s: %sLow byte termination Enabled\n", 1223 ahc_name(ahc), 1224 enableSEC_low ? "Secondary " : ""); 1225 } 1226 1227 if (enablePRI_low != 0) { 1228 *sxfrctl1 |= STPWEN; 1229 if (bootverbose) 1230 printf("%s: Primary Low Byte termination " 1231 "Enabled\n", ahc_name(ahc)); 1232 } 1233 1234 if (enablePRI_high != 0) { 1235 brddat |= BRDDAT4; 1236 if (bootverbose) 1237 printf("%s: Primary High Byte " 1238 "termination Enabled\n", 1239 ahc_name(ahc)); 1240 } 1241 1242 write_brdctl(ahc, brddat); 1243 1244 } else { 1245 if ((adapter_control & CFSTERM) != 0) { 1246 *sxfrctl1 |= STPWEN; 1247 1248 if (bootverbose) 1249 printf("%s: %sLow byte termination Enabled\n", 1250 ahc_name(ahc), 1251 (ahc->features & AHC_ULTRA2) ? "Primary " 1252 : ""); 1253 } 1254 1255 if ((adapter_control & CFWSTERM) != 0) { 1256 brddat |= BRDDAT6; 1257 if (bootverbose) 1258 printf("%s: %sHigh byte termination Enabled\n", 1259 ahc_name(ahc), 1260 (ahc->features & AHC_ULTRA2) 1261 ? "Secondary " : ""); 1262 } 1263 1264 write_brdctl(ahc, brddat); 1265 } 1266 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1267 } 1268 1269 static void 1270 ahc_ultra2_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 1271 int *enableSEC_high, int *enablePRI_low, 1272 int *enablePRI_high, int *eeprom_present) 1273 { 1274 u_int8_t brdctl; 1275 1276 /* 1277 * BRDDAT7 = Eeprom 1278 * BRDDAT6 = Enable Secondary High Byte termination 1279 * BRDDAT5 = Enable Secondary Low Byte termination 1280 * BRDDAT4 = Enable Primary high byte termination 1281 * BRDDAT3 = Enable Primary low byte termination 1282 */ 1283 brdctl = read_brdctl(ahc); 1284 *eeprom_present = brdctl & BRDDAT7; 1285 *enableSEC_high = (brdctl & BRDDAT6); 1286 *enableSEC_low = (brdctl & BRDDAT5); 1287 *enablePRI_high = (brdctl & BRDDAT4); 1288 *enablePRI_low = (brdctl & BRDDAT3); 1289 } 1290 1291 static void 1292 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1293 int *internal68_present, int *externalcable_present, 1294 int *eeprom_present) 1295 { 1296 u_int8_t brdctl; 1297 1298 /* 1299 * First read the status of our cables. 1300 * Set the rom bank to 0 since the 1301 * bank setting serves as a multiplexor 1302 * for the cable detection logic. 1303 * BRDDAT5 controls the bank switch. 1304 */ 1305 write_brdctl(ahc, 0); 1306 1307 /* 1308 * Now read the state of the internal 1309 * connectors. BRDDAT6 is INT50 and 1310 * BRDDAT7 is INT68. 1311 */ 1312 brdctl = read_brdctl(ahc); 1313 *internal50_present = !(brdctl & BRDDAT6); 1314 *internal68_present = !(brdctl & BRDDAT7); 1315 1316 /* 1317 * Set the rom bank to 1 and determine 1318 * the other signals. 1319 */ 1320 write_brdctl(ahc, BRDDAT5); 1321 1322 /* 1323 * Now read the state of the external 1324 * connectors. BRDDAT6 is EXT68 and 1325 * BRDDAT7 is EPROMPS. 1326 */ 1327 brdctl = read_brdctl(ahc); 1328 *externalcable_present = !(brdctl & BRDDAT6); 1329 *eeprom_present = brdctl & BRDDAT7; 1330 } 1331 1332 static void 1333 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1334 int *externalcable_present, int *eeprom_present) 1335 { 1336 u_int8_t brdctl; 1337 1338 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1339 ahc_outb(ahc, BRDCTL, 0); 1340 brdctl = ahc_inb(ahc, BRDCTL); 1341 *internal50_present = !(brdctl & BRDDAT5); 1342 *externalcable_present = !(brdctl & BRDDAT6); 1343 1344 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) != 0; 1345 } 1346 1347 static int 1348 acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1349 { 1350 int wait; 1351 1352 if ((ahc->features & AHC_SPIOCAP) != 0 1353 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1354 return (0); 1355 1356 /* 1357 * Request access of the memory port. When access is 1358 * granted, SEERDY will go high. We use a 1 second 1359 * timeout which should be near 1 second more than 1360 * is needed. Reason: after the chip reset, there 1361 * should be no contention. 1362 */ 1363 SEEPROM_OUTB(sd, sd->sd_MS); 1364 wait = 1000; /* 1 second timeout in msec */ 1365 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1366 DELAY(1000); /* delay 1 msec */ 1367 } 1368 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1369 SEEPROM_OUTB(sd, 0); 1370 return (0); 1371 } 1372 return(1); 1373 } 1374 1375 static void 1376 release_seeprom(sd) 1377 struct seeprom_descriptor *sd; 1378 { 1379 /* Release access to the memory port and the serial EEPROM. */ 1380 SEEPROM_OUTB(sd, 0); 1381 } 1382 1383 static void 1384 write_brdctl(ahc, value) 1385 struct ahc_softc *ahc; 1386 u_int8_t value; 1387 { 1388 u_int8_t brdctl; 1389 1390 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1391 brdctl = BRDSTB; 1392 if (ahc->channel == 'B') 1393 brdctl |= BRDCS; 1394 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1395 brdctl = 0; 1396 } else { 1397 brdctl = BRDSTB|BRDCS; 1398 } 1399 ahc_outb(ahc, BRDCTL, brdctl); 1400 brdctl |= value; 1401 ahc_outb(ahc, BRDCTL, brdctl); 1402 if ((ahc->features & AHC_ULTRA2) != 0) 1403 brdctl |= BRDSTB_ULTRA2; 1404 else 1405 brdctl &= ~BRDSTB; 1406 ahc_outb(ahc, BRDCTL, brdctl); 1407 if ((ahc->features & AHC_ULTRA2) != 0) 1408 brdctl = 0; 1409 else 1410 brdctl &= ~BRDCS; 1411 ahc_outb(ahc, BRDCTL, brdctl); 1412 } 1413 1414 static u_int8_t 1415 read_brdctl(ahc) 1416 struct ahc_softc *ahc; 1417 { 1418 u_int8_t brdctl; 1419 u_int8_t value; 1420 1421 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1422 brdctl = BRDRW; 1423 if (ahc->channel == 'B') 1424 brdctl |= BRDCS; 1425 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1426 brdctl = BRDRW_ULTRA2; 1427 } else { 1428 brdctl = BRDRW|BRDCS; 1429 } 1430 ahc_outb(ahc, BRDCTL, brdctl); 1431 value = ahc_inb(ahc, BRDCTL); 1432 ahc_outb(ahc, BRDCTL, 0); 1433 return (value); 1434 } 1435 1436 #define DPE 0x80 1437 #define SSE 0x40 1438 #define RMA 0x20 1439 #define RTA 0x10 1440 #define STA 0x08 1441 #define DPR 0x01 1442 1443 void 1444 ahc_pci_intr(struct ahc_softc *ahc) 1445 { 1446 u_int8_t status1; 1447 1448 status1 = pci_read_config(ahc->device, PCIR_STATUS + 1, /*bytes*/1); 1449 1450 if (status1 & DPE) { 1451 printf("%s: Data Parity Error Detected during address " 1452 "or write data phase\n", ahc_name(ahc)); 1453 } 1454 if (status1 & SSE) { 1455 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1456 } 1457 if (status1 & RMA) { 1458 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1459 } 1460 if (status1 & RTA) { 1461 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1462 } 1463 if (status1 & STA) { 1464 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1465 } 1466 if (status1 & DPR) { 1467 printf("%s: Data Parity Error has been reported via PERR#\n", 1468 ahc_name(ahc)); 1469 } 1470 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1471 printf("%s: Latched PCIERR interrupt with " 1472 "no status bits set\n", ahc_name(ahc)); 1473 } 1474 pci_write_config(ahc->device, PCIR_STATUS + 1, status1, /*bytes*/1); 1475 1476 if (status1 & (DPR|RMA|RTA)) { 1477 ahc_outb(ahc, CLRINT, CLRPARERR); 1478 } 1479 } 1480 1481 static int 1482 ahc_aic7850_setup(device_t dev, char *channel, ahc_chip *chip, 1483 ahc_feature *features, ahc_flag *flags) 1484 { 1485 *channel = 'A'; 1486 *chip = AHC_AIC7850; 1487 *features = AHC_AIC7850_FE; 1488 return (0); 1489 } 1490 1491 static int 1492 ahc_aic7855_setup(device_t dev, char *channel, ahc_chip *chip, 1493 ahc_feature *features, ahc_flag *flags) 1494 { 1495 *channel = 'A'; 1496 *chip = AHC_AIC7855; 1497 *features = AHC_AIC7855_FE; 1498 return (0); 1499 } 1500 1501 static int 1502 ahc_aic7859_setup(device_t dev, char *channel, ahc_chip *chip, 1503 ahc_feature *features, ahc_flag *flags) 1504 { 1505 *channel = 'A'; 1506 *chip = AHC_AIC7859; 1507 *features = AHC_AIC7859_FE; 1508 return (0); 1509 } 1510 1511 static int 1512 ahc_aic7860_setup(device_t dev, char *channel, ahc_chip *chip, 1513 ahc_feature *features, ahc_flag *flags) 1514 { 1515 *channel = 'A'; 1516 *chip = AHC_AIC7860; 1517 *features = AHC_AIC7860_FE; 1518 return (0); 1519 } 1520 1521 static int 1522 ahc_aic7870_setup(device_t dev, char *channel, ahc_chip *chip, 1523 ahc_feature *features, ahc_flag *flags) 1524 { 1525 *channel = 'A'; 1526 *chip = AHC_AIC7870; 1527 *features = AHC_AIC7870_FE; 1528 return (0); 1529 } 1530 1531 static int 1532 ahc_aha394X_setup(device_t dev, char *channel, ahc_chip *chip, 1533 ahc_feature *features, ahc_flag *flags) 1534 { 1535 int error; 1536 1537 error = ahc_aic7870_setup(dev, channel, chip, features, flags); 1538 if (error == 0) 1539 error = ahc_aha394XX_setup(dev, channel, chip, features, flags); 1540 return (error); 1541 } 1542 1543 static int 1544 ahc_aha398X_setup(device_t dev, char *channel, ahc_chip *chip, 1545 ahc_feature *features, ahc_flag *flags) 1546 { 1547 int error; 1548 1549 error = ahc_aic7870_setup(dev, channel, chip, features, flags); 1550 if (error == 0) 1551 error = ahc_aha398XX_setup(dev, channel, chip, features, flags); 1552 return (error); 1553 } 1554 1555 static int 1556 ahc_aic7880_setup(device_t dev, char *channel, ahc_chip *chip, 1557 ahc_feature *features, ahc_flag *flags) 1558 { 1559 *channel = 'A'; 1560 *chip = AHC_AIC7880; 1561 *features = AHC_AIC7880_FE; 1562 return (0); 1563 } 1564 1565 static int 1566 ahc_aha394XU_setup(device_t dev, char *channel, ahc_chip *chip, 1567 ahc_feature *features, ahc_flag *flags) 1568 { 1569 int error; 1570 1571 error = ahc_aic7880_setup(dev, channel, chip, features, flags); 1572 if (error == 0) 1573 error = ahc_aha394XX_setup(dev, channel, chip, features, flags); 1574 return (error); 1575 } 1576 1577 static int 1578 ahc_aha398XU_setup(device_t dev, char *channel, ahc_chip *chip, 1579 ahc_feature *features, ahc_flag *flags) 1580 { 1581 int error; 1582 1583 error = ahc_aic7880_setup(dev, channel, chip, features, flags); 1584 if (error == 0) 1585 error = ahc_aha398XX_setup(dev, channel, chip, features, flags); 1586 return (error); 1587 } 1588 1589 static int 1590 ahc_aic7890_setup(device_t dev, char *channel, ahc_chip *chip, 1591 ahc_feature *features, ahc_flag *flags) 1592 { 1593 *channel = 'A'; 1594 *chip = AHC_AIC7890; 1595 *features = AHC_AIC7890_FE; 1596 *flags |= AHC_NEWEEPROM_FMT; 1597 return (0); 1598 } 1599 1600 static int 1601 ahc_aic7895_setup(device_t dev, char *channel, ahc_chip *chip, 1602 ahc_feature *features, ahc_flag *flags) 1603 { 1604 u_int32_t devconfig; 1605 1606 *channel = pci_get_function(dev) == 1 ? 'B' : 'A'; 1607 *chip = AHC_AIC7895; 1608 /* The 'C' revision of the aic7895 has a few additional features */ 1609 if (pci_get_revid(dev) >= 4) 1610 *features = AHC_AIC7895C_FE; 1611 else 1612 *features = AHC_AIC7895_FE; 1613 *flags |= AHC_NEWEEPROM_FMT; 1614 devconfig = pci_read_config(dev, DEVCONFIG, /*bytes*/4); 1615 devconfig &= ~SCBSIZE32; 1616 pci_write_config(dev, DEVCONFIG, devconfig, /*bytes*/4); 1617 return (0); 1618 } 1619 1620 static int 1621 ahc_aic7896_setup(device_t dev, char *channel, ahc_chip *chip, 1622 ahc_feature *features, ahc_flag *flags) 1623 { 1624 *channel = pci_get_function(dev) == 1 ? 'B' : 'A'; 1625 *chip = AHC_AIC7896; 1626 *features = AHC_AIC7896_FE; 1627 *flags |= AHC_NEWEEPROM_FMT; 1628 return (0); 1629 } 1630 1631 static int 1632 ahc_raid_setup(device_t dev, char *channel, ahc_chip *chip, 1633 ahc_feature *features, ahc_flag *flags) 1634 { 1635 printf("RAID functionality unsupported\n"); 1636 return (ENXIO); 1637 } 1638 1639 static int 1640 ahc_aha394XX_setup(device_t dev, char *channel, ahc_chip *chip, 1641 ahc_feature *features, ahc_flag *flags) 1642 { 1643 switch (pci_get_slot(dev)) { 1644 case AHC_394X_SLOT_CHANNEL_A: 1645 *channel = 'A'; 1646 break; 1647 case AHC_394X_SLOT_CHANNEL_B: 1648 *channel = 'B'; 1649 break; 1650 default: 1651 printf("adapter at unexpected slot %d\n" 1652 "unable to map to a channel\n", 1653 pci_get_slot(dev)); 1654 *channel = 'A'; 1655 } 1656 return (0); 1657 } 1658 1659 static int 1660 ahc_aha398XX_setup(device_t dev, char *channel, ahc_chip *chip, 1661 ahc_feature *features, ahc_flag *flags) 1662 { 1663 switch (pci_get_slot(dev)) { 1664 case AHC_398X_SLOT_CHANNEL_A: 1665 *channel = 'A'; 1666 break; 1667 case AHC_398X_SLOT_CHANNEL_B: 1668 *channel = 'B'; 1669 break; 1670 case AHC_398X_SLOT_CHANNEL_C: 1671 *channel = 'C'; 1672 break; 1673 default: 1674 printf("adapter at unexpected slot %d\n" 1675 "unable to map to a channel\n", 1676 pci_get_slot(dev)); 1677 *channel = 'A'; 1678 } 1679 *flags |= AHC_LARGE_SEEPROM; 1680 return (0); 1681 } 1682