1 /* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1995, 1996, 1997, 1998 Justin T. Gibbs 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Where this Software is combined with software released under the terms of 19 * the GNU Public License ("GPL") and the terms of the GPL would require the 20 * combined work to also be released under the terms of the GPL, the terms 21 * and conditions of this License will apply in addition to those of the 22 * GPL with the exception of any terms or conditions of this License that 23 * conflict with, or are expressly prohibited by, the GPL. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $FreeBSD$ 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/bus.h> 45 46 #include <pci/pcireg.h> 47 #include <pci/pcivar.h> 48 49 #include <machine/bus_memio.h> 50 #include <machine/bus_pio.h> 51 #include <machine/bus.h> 52 #include <machine/resource.h> 53 #include <machine/clock.h> 54 #include <sys/rman.h> 55 56 #include <cam/cam.h> 57 #include <cam/cam_ccb.h> 58 #include <cam/cam_sim.h> 59 #include <cam/cam_xpt_sim.h> 60 61 #include <cam/scsi/scsi_all.h> 62 63 #include <dev/aic7xxx/aic7xxx.h> 64 #include <dev/aic7xxx/93cx6.h> 65 66 #include <aic7xxx_reg.h> 67 68 #define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ 69 #define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 70 71 static __inline u_int64_t 72 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 73 { 74 u_int64_t id; 75 76 id = subvendor 77 | (subdevice << 16) 78 | ((u_int64_t)vendor << 32) 79 | ((u_int64_t)device << 48); 80 81 return (id); 82 } 83 84 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull 85 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull 86 #define ID_AIC7850 0x5078900400000000ull 87 #define ID_AHA_2910_15_20_30C 0x5078900478509004ull 88 #define ID_AIC7855 0x5578900400000000ull 89 #define ID_AIC7859 0x3860900400000000ull 90 #define ID_AHA_2930CU 0x3860900438699004ull 91 #define ID_AIC7860 0x6078900400000000ull 92 #define ID_AIC7860C 0x6078900478609004ull 93 #define ID_AHA_2940AU_0 0x6178900400000000ull 94 #define ID_AHA_2940AU_1 0x6178900478619004ull 95 #define ID_AHA_2940AU_CN 0x2178900478219004ull 96 #define ID_AHA_2930C_VAR 0x6038900438689004ull 97 98 #define ID_AIC7870 0x7078900400000000ull 99 #define ID_AHA_2940 0x7178900400000000ull 100 #define ID_AHA_3940 0x7278900400000000ull 101 #define ID_AHA_398X 0x7378900400000000ull 102 #define ID_AHA_2944 0x7478900400000000ull 103 #define ID_AHA_3944 0x7578900400000000ull 104 105 #define ID_AIC7880 0x8078900400000000ull 106 #define ID_AIC7880_B 0x8078900478809004ull 107 #define ID_AHA_2940U 0x8178900400000000ull 108 #define ID_AHA_3940U 0x8278900400000000ull 109 #define ID_AHA_2944U 0x8478900400000000ull 110 #define ID_AHA_3944U 0x8578900400000000ull 111 #define ID_AHA_398XU 0x8378900400000000ull 112 #define ID_AHA_4944U 0x8678900400000000ull 113 #define ID_AHA_2940UB 0x8178900478819004ull 114 #define ID_AHA_2930U 0x8878900478889004ull 115 #define ID_AHA_2940U_PRO 0x8778900478879004ull 116 #define ID_AHA_2940U_CN 0x0078900478009004ull 117 118 #define ID_AIC7895 0x7895900478959004ull 119 #define ID_AIC7895_RAID_PORT 0x7893900478939004ull 120 #define ID_AHA_2940U_DUAL 0x7895900478919004ull 121 #define ID_AHA_3940AU 0x7895900478929004ull 122 #define ID_AHA_3944AU 0x7895900478949004ull 123 124 #define ID_AIC7890 0x001F9005000F9005ull 125 #define ID_AHA_2930U2 0x0011900501819005ull 126 #define ID_AHA_2940U2B 0x00109005A1009005ull 127 #define ID_AHA_2940U2_OEM 0x0010900521809005ull 128 #define ID_AHA_2940U2 0x00109005A1809005ull 129 #define ID_AHA_2950U2B 0x00109005E1009005ull 130 131 #define ID_AIC7896 0x005F9005FFFF9005ull 132 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull 133 #define ID_AHA_3950U2B_1 0x00509005F5009005ull 134 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull 135 #define ID_AHA_3950U2D_1 0x00519005B5009005ull 136 137 #define ID_AIC7810 0x1078900400000000ull 138 #define ID_AIC7815 0x1578900400000000ull 139 140 typedef int (ahc_device_setup_t)(device_t, char *, ahc_chip *, 141 ahc_feature *, ahc_flag *); 142 143 static ahc_device_setup_t ahc_aic7850_setup; 144 static ahc_device_setup_t ahc_aic7855_setup; 145 static ahc_device_setup_t ahc_aic7859_setup; 146 static ahc_device_setup_t ahc_aic7860_setup; 147 static ahc_device_setup_t ahc_aic7870_setup; 148 static ahc_device_setup_t ahc_aha394X_setup; 149 static ahc_device_setup_t ahc_aha398X_setup; 150 static ahc_device_setup_t ahc_aic7880_setup; 151 static ahc_device_setup_t ahc_aha394XU_setup; 152 static ahc_device_setup_t ahc_aha398XU_setup; 153 static ahc_device_setup_t ahc_aic7890_setup; 154 static ahc_device_setup_t ahc_aic7895_setup; 155 static ahc_device_setup_t ahc_aic7896_setup; 156 static ahc_device_setup_t ahc_raid_setup; 157 static ahc_device_setup_t ahc_aha394XX_setup; 158 static ahc_device_setup_t ahc_aha398XX_setup; 159 160 struct ahc_pci_identity { 161 u_int64_t full_id; 162 u_int64_t id_mask; 163 char *name; 164 ahc_device_setup_t *setup; 165 }; 166 167 struct ahc_pci_identity ahc_pci_ident_table [] = 168 { 169 /* aic7850 based controllers */ 170 { 171 ID_AHA_2910_15_20_30C, 172 ID_ALL_MASK, 173 "Adaptec 2910/15/20/30C SCSI adapter", 174 ahc_aic7850_setup 175 }, 176 /* aic7859 based controllers */ 177 { 178 ID_AHA_2930CU, 179 ID_DEV_VENDOR_MASK, 180 "Adaptec 2930CU SCSI adapter", 181 ahc_aic7859_setup 182 }, 183 /* aic7860 based controllers */ 184 { 185 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 186 ID_DEV_VENDOR_MASK, 187 "Adaptec 2940A Ultra SCSI adapter", 188 ahc_aic7860_setup 189 }, 190 { 191 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 192 ID_DEV_VENDOR_MASK, 193 "Adaptec 2940A/CN Ultra SCSI adapter", 194 ahc_aic7860_setup 195 }, 196 { 197 ID_AHA_2930C_VAR, 198 ID_DEV_VENDOR_MASK, 199 "Adaptec 2930C SCSI adapter (VAR)", 200 ahc_aic7860_setup 201 }, 202 /* aic7870 based controllers */ 203 { 204 ID_AHA_2940, 205 ID_ALL_MASK, 206 "Adaptec 2940 SCSI adapter", 207 ahc_aic7870_setup 208 }, 209 { 210 ID_AHA_3940, 211 ID_ALL_MASK, 212 "Adaptec 3940 SCSI adapter", 213 ahc_aha394X_setup 214 }, 215 { 216 ID_AHA_398X, 217 ID_ALL_MASK, 218 "Adaptec 398X SCSI RAID adapter", 219 ahc_aha398X_setup 220 }, 221 { 222 ID_AHA_2944, 223 ID_ALL_MASK, 224 "Adaptec 2944 SCSI adapter", 225 ahc_aic7870_setup 226 }, 227 { 228 ID_AHA_3944, 229 ID_ALL_MASK, 230 "Adaptec 3944 SCSI adapter", 231 ahc_aha394X_setup 232 }, 233 /* aic7880 based controllers */ 234 { 235 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 236 ID_DEV_VENDOR_MASK, 237 "Adaptec 2940 Ultra SCSI adapter", 238 ahc_aic7880_setup 239 }, 240 { 241 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 242 ID_DEV_VENDOR_MASK, 243 "Adaptec 3940 Ultra SCSI adapter", 244 ahc_aha394XU_setup 245 }, 246 { 247 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 248 ID_DEV_VENDOR_MASK, 249 "Adaptec 2944 Ultra SCSI adapter", 250 ahc_aic7880_setup 251 }, 252 { 253 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 254 ID_DEV_VENDOR_MASK, 255 "Adaptec 3944 Ultra SCSI adapter", 256 ahc_aha394XU_setup 257 }, 258 { 259 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 260 ID_DEV_VENDOR_MASK, 261 "Adaptec 398X Ultra SCSI RAID adapter", 262 ahc_aha398XU_setup 263 }, 264 { 265 /* XXX Don't know the slot numbers so can't identify channels */ 266 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 267 ID_DEV_VENDOR_MASK, 268 "Adaptec 4944 Ultra SCSI adapter", 269 ahc_aic7880_setup 270 }, 271 { 272 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 273 ID_DEV_VENDOR_MASK, 274 "Adaptec 2930 Ultra SCSI adapter", 275 ahc_aic7880_setup 276 }, 277 { 278 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 279 ID_DEV_VENDOR_MASK, 280 "Adaptec 2940 Pro Ultra SCSI adapter", 281 ahc_aic7880_setup 282 }, 283 { 284 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 285 ID_DEV_VENDOR_MASK, 286 "Adaptec 2940/CN Ultra SCSI adapter", 287 ahc_aic7880_setup 288 }, 289 /* aic7890 based controllers */ 290 { 291 ID_AHA_2930U2, 292 ID_ALL_MASK, 293 "Adaptec 2930 Ultra2 SCSI adapter", 294 ahc_aic7890_setup 295 }, 296 { 297 ID_AHA_2940U2B, 298 ID_ALL_MASK, 299 "Adaptec 2940B Ultra2 SCSI adapter", 300 ahc_aic7890_setup 301 }, 302 { 303 ID_AHA_2940U2_OEM, 304 ID_ALL_MASK, 305 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 306 ahc_aic7890_setup 307 }, 308 { 309 ID_AHA_2940U2, 310 ID_ALL_MASK, 311 "Adaptec 2940 Ultra2 SCSI adapter", 312 ahc_aic7890_setup 313 }, 314 { 315 ID_AHA_2950U2B, 316 ID_ALL_MASK, 317 "Adaptec 2950 Ultra2 SCSI adapter", 318 ahc_aic7890_setup 319 }, 320 /* aic7895 based controllers */ 321 { 322 ID_AHA_2940U_DUAL, 323 ID_ALL_MASK, 324 "Adaptec 2940/DUAL Ultra SCSI adapter", 325 ahc_aic7895_setup 326 }, 327 { 328 ID_AHA_3940AU, 329 ID_ALL_MASK, 330 "Adaptec 3940A Ultra SCSI adapter", 331 ahc_aic7895_setup 332 }, 333 { 334 ID_AHA_3944AU, 335 ID_ALL_MASK, 336 "Adaptec 3944A Ultra SCSI adapter", 337 ahc_aic7895_setup 338 }, 339 /* aic7896/97 based controllers */ 340 { 341 ID_AHA_3950U2B_0, 342 ID_ALL_MASK, 343 "Adaptec 3950B Ultra2 SCSI adapter", 344 ahc_aic7896_setup 345 }, 346 { 347 ID_AHA_3950U2B_1, 348 ID_ALL_MASK, 349 "Adaptec 3950B Ultra2 SCSI adapter", 350 ahc_aic7896_setup 351 }, 352 { 353 ID_AHA_3950U2D_0, 354 ID_ALL_MASK, 355 "Adaptec 3950D Ultra2 SCSI adapter", 356 ahc_aic7896_setup 357 }, 358 { 359 ID_AHA_3950U2D_1, 360 ID_ALL_MASK, 361 "Adaptec 3950D Ultra2 SCSI adapter", 362 ahc_aic7896_setup 363 }, 364 /* Generic chip probes for devices we don't know 'exactly' */ 365 { 366 ID_AIC7850 & ID_DEV_VENDOR_MASK, 367 ID_DEV_VENDOR_MASK, 368 "Adaptec aic7850 SCSI adapter", 369 ahc_aic7850_setup 370 }, 371 { 372 ID_AIC7855 & ID_DEV_VENDOR_MASK, 373 ID_DEV_VENDOR_MASK, 374 "Adaptec aic7855 SCSI adapter", 375 ahc_aic7855_setup 376 }, 377 { 378 ID_AIC7859 & ID_DEV_VENDOR_MASK, 379 ID_DEV_VENDOR_MASK, 380 "Adaptec aic7859 SCSI adapter", 381 ahc_aic7859_setup 382 }, 383 { 384 ID_AIC7860 & ID_DEV_VENDOR_MASK, 385 ID_DEV_VENDOR_MASK, 386 "Adaptec aic7860 SCSI adapter", 387 ahc_aic7860_setup 388 }, 389 { 390 ID_AIC7870 & ID_DEV_VENDOR_MASK, 391 ID_DEV_VENDOR_MASK, 392 "Adaptec aic7870 SCSI adapter", 393 ahc_aic7870_setup 394 }, 395 { 396 ID_AIC7880 & ID_DEV_VENDOR_MASK, 397 ID_DEV_VENDOR_MASK, 398 "Adaptec aic7880 Ultra SCSI adapter", 399 ahc_aic7880_setup 400 }, 401 { 402 ID_AIC7890 & ID_DEV_VENDOR_MASK, 403 ID_DEV_VENDOR_MASK, 404 "Adaptec aic7890/91 Ultra2 SCSI adapter", 405 ahc_aic7890_setup 406 }, 407 { 408 ID_AIC7895 & ID_DEV_VENDOR_MASK, 409 ID_DEV_VENDOR_MASK, 410 "Adaptec aic7895 Ultra SCSI adapter", 411 ahc_aic7895_setup 412 }, 413 { 414 ID_AIC7895_RAID_PORT & ID_DEV_VENDOR_MASK, 415 ID_DEV_VENDOR_MASK, 416 "Adaptec aic7895 Ultra SCSI adapter (RAID PORT)", 417 ahc_aic7895_setup 418 }, 419 { 420 ID_AIC7896 & ID_DEV_VENDOR_MASK, 421 ID_DEV_VENDOR_MASK, 422 "Adaptec aic7896/97 Ultra2 SCSI adapter", 423 ahc_aic7896_setup 424 }, 425 { 426 ID_AIC7810 & ID_DEV_VENDOR_MASK, 427 ID_DEV_VENDOR_MASK, 428 "Adaptec aic7810 RAID memory controller", 429 ahc_raid_setup 430 }, 431 { 432 ID_AIC7815 & ID_DEV_VENDOR_MASK, 433 ID_DEV_VENDOR_MASK, 434 "Adaptec aic7815 RAID memory controller", 435 ahc_raid_setup 436 } 437 }; 438 439 static const int ahc_num_pci_devs = 440 sizeof(ahc_pci_ident_table) / sizeof(*ahc_pci_ident_table); 441 442 #define AHC_394X_SLOT_CHANNEL_A 4 443 #define AHC_394X_SLOT_CHANNEL_B 5 444 445 #define AHC_398X_SLOT_CHANNEL_A 4 446 #define AHC_398X_SLOT_CHANNEL_B 8 447 #define AHC_398X_SLOT_CHANNEL_C 12 448 449 #define DEVCONFIG 0x40 450 #define SCBSIZE32 0x00010000ul /* aic789X only */ 451 #define MPORTMODE 0x00000400ul /* aic7870 only */ 452 #define RAMPSM 0x00000200ul /* aic7870 only */ 453 #define VOLSENSE 0x00000100ul 454 #define SCBRAMSEL 0x00000080ul 455 #define MRDCEN 0x00000040ul 456 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 457 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 458 #define BERREN 0x00000008ul 459 #define DACEN 0x00000004ul 460 #define STPWLEVEL 0x00000002ul 461 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 462 463 #define CSIZE_LATTIME 0x0c 464 #define CACHESIZE 0x0000003ful /* only 5 bits */ 465 #define LATTIME 0x0000ff00ul 466 467 static struct ahc_pci_identity *ahc_find_pci_device(device_t dev); 468 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 469 static void configure_termination(struct ahc_softc *ahc, 470 struct seeprom_config *sc, 471 struct seeprom_descriptor *sd, 472 u_int *sxfrctl1); 473 474 static void ahc_ultra2_term_detect(struct ahc_softc *ahc, 475 int *enableSEC_low, 476 int *enableSEC_high, 477 int *enablePRI_low, 478 int *enablePRI_high, 479 int *eeprom_present); 480 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 481 int *internal68_present, 482 int *externalcable_present, 483 int *eeprom_present); 484 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 485 int *externalcable_present, 486 int *eeprom_present); 487 static int acquire_seeprom(struct ahc_softc *ahc, 488 struct seeprom_descriptor *sd); 489 static void release_seeprom(struct seeprom_descriptor *sd); 490 static void write_brdctl(struct ahc_softc *ahc, u_int8_t value); 491 static u_int8_t read_brdctl(struct ahc_softc *ahc); 492 493 static struct ahc_softc *first_398X; 494 495 static int ahc_pci_probe(device_t dev); 496 static int ahc_pci_attach(device_t dev); 497 498 /* Exported for use in the ahc_intr routine */ 499 void ahc_pci_intr(struct ahc_softc *ahc); 500 501 static device_method_t ahc_pci_methods[] = { 502 /* Device interface */ 503 DEVMETHOD(device_probe, ahc_pci_probe), 504 DEVMETHOD(device_attach, ahc_pci_attach), 505 { 0, 0 } 506 }; 507 508 static driver_t ahc_pci_driver = { 509 "ahc", 510 ahc_pci_methods, 511 sizeof(struct ahc_softc) 512 }; 513 514 static devclass_t ahc_devclass; 515 516 DRIVER_MODULE(ahc, pci, ahc_pci_driver, ahc_devclass, 0, 0); 517 518 static struct ahc_pci_identity * 519 ahc_find_pci_device(device_t dev) 520 { 521 u_int64_t full_id; 522 struct ahc_pci_identity *entry; 523 u_int i; 524 525 full_id = ahc_compose_id(pci_get_device(dev), 526 pci_get_vendor(dev), 527 pci_get_subdevice(dev), 528 pci_get_subvendor(dev)); 529 530 for (i = 0; i < ahc_num_pci_devs; i++) { 531 entry = &ahc_pci_ident_table[i]; 532 if (entry->full_id == (full_id & entry->id_mask)) 533 return (entry); 534 } 535 return (NULL); 536 } 537 538 static int 539 ahc_pci_probe(device_t dev) 540 { 541 struct ahc_pci_identity *entry; 542 543 entry = ahc_find_pci_device(dev); 544 if (entry != NULL) { 545 device_set_desc(dev, entry->name); 546 return (0); 547 } 548 return (ENXIO); 549 } 550 551 static int 552 ahc_pci_attach(device_t dev) 553 { 554 bus_dma_tag_t parent_dmat; 555 struct ahc_pci_identity *entry; 556 struct resource *regs; 557 struct ahc_softc *ahc; 558 u_int command; 559 struct scb_data *shared_scb_data; 560 ahc_chip ahc_t = AHC_NONE; 561 ahc_feature ahc_fe = AHC_FENONE; 562 ahc_flag ahc_f = AHC_FNONE; 563 int regs_type; 564 int regs_id; 565 u_int our_id = 0; 566 u_int sxfrctl1; 567 u_int scsiseq; 568 int error; 569 int zero; 570 char channel; 571 572 shared_scb_data = NULL; 573 command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1); 574 entry = ahc_find_pci_device(dev); 575 if (entry == NULL) 576 return (ENXIO); 577 error = entry->setup(dev, &channel, &ahc_t, &ahc_fe, &ahc_f); 578 if (error != 0) 579 return (error); 580 581 regs = NULL; 582 regs_type = 0; 583 regs_id = 0; 584 #ifdef AHC_ALLOW_MEMIO 585 if ((command & PCIM_CMD_MEMEN) != 0) { 586 regs_type = SYS_RES_MEMORY; 587 regs_id = AHC_PCI_MEMADDR; 588 regs = bus_alloc_resource(dev, regs_type, 589 ®s_id, 0, ~0, 1, RF_ACTIVE); 590 } 591 #endif 592 593 if (regs == NULL && (command & PCI_COMMAND_IO_ENABLE) != 0) { 594 regs_type = SYS_RES_IOPORT; 595 regs_id = AHC_PCI_IOADDR; 596 regs = bus_alloc_resource(dev, regs_type, 597 ®s_id, 0, ~0, 1, RF_ACTIVE); 598 } 599 600 if (regs == NULL) { 601 device_printf(dev, "can't allocate register resources\n"); 602 return (ENOMEM); 603 } 604 605 /* Ensure busmastering is enabled */ 606 command |= PCIM_CMD_BUSMASTEREN; 607 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1); 608 609 /* Allocate a dmatag for our SCB DMA maps */ 610 /* XXX Should be a child of the PCI bus dma tag */ 611 error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1, 612 /*boundary*/0, 613 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 614 /*highaddr*/BUS_SPACE_MAXADDR, 615 /*filter*/NULL, /*filterarg*/NULL, 616 /*maxsize*/MAXBSIZE, /*nsegments*/AHC_NSEG, 617 /*maxsegsz*/AHC_MAXTRANSFER_SIZE, 618 /*flags*/BUS_DMA_ALLOCNOW, &parent_dmat); 619 620 if (error != 0) { 621 printf("ahc_pci_attach: Could not allocate DMA tag " 622 "- error %d\n", error); 623 return (ENOMEM); 624 } 625 626 /* On all PCI adapters, we allow SCB paging */ 627 ahc_f |= AHC_PAGESCBS; 628 if ((ahc = ahc_alloc(dev, regs, regs_type, regs_id, parent_dmat, 629 ahc_t|AHC_PCI, ahc_fe, ahc_f, 630 shared_scb_data)) == NULL) 631 return (ENOMEM); 632 633 ahc->channel = channel; 634 635 /* Store our PCI bus information for use in our PCI error handler */ 636 ahc->device = dev; 637 638 /* Remeber how the card was setup in case there is no SEEPROM */ 639 ahc_outb(ahc, HCNTRL, ahc->pause); 640 if ((ahc->features & AHC_ULTRA2) != 0) 641 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 642 else 643 our_id = ahc_inb(ahc, SCSIID) & OID; 644 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 645 scsiseq = ahc_inb(ahc, SCSISEQ); 646 647 if (ahc_reset(ahc) != 0) { 648 /* Failed */ 649 ahc_free(ahc); 650 return (ENXIO); 651 } 652 653 /* 654 * Take a look to see if we have external SRAM. 655 * We currently do not attempt to use SRAM that is 656 * shared among multiple controllers. 657 */ 658 if ((ahc->features & AHC_ULTRA2) != 0) { 659 u_int dscommand0; 660 661 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 662 if ((dscommand0 & RAMPS) != 0) { 663 u_int32_t devconfig; 664 665 devconfig = pci_read_config(dev, DEVCONFIG, /*bytes*/4); 666 if ((devconfig & MPORTMODE) != 0) { 667 /* Single user mode */ 668 669 /* 670 * XXX Assume 9bit SRAM and enable 671 * parity checking 672 */ 673 devconfig |= EXTSCBPEN; 674 pci_write_config(dev, DEVCONFIG, 675 devconfig, /*bytes*/4); 676 677 /* 678 * Set the bank select apropriately. 679 */ 680 if (ahc->channel == 'B') 681 ahc_outb(ahc, SCBBADDR, 1); 682 else 683 ahc_outb(ahc, SCBBADDR, 0); 684 685 /* Select external SCB SRAM */ 686 dscommand0 &= ~INTSCBRAMSEL; 687 ahc_outb(ahc, DSCOMMAND0, dscommand0); 688 689 if (ahc_probe_scbs(ahc) == 0) { 690 /* External ram isn't really there */ 691 dscommand0 |= INTSCBRAMSEL; 692 ahc_outb(ahc, DSCOMMAND0, dscommand0); 693 } else if (bootverbose) 694 printf("%s: External SRAM bank%d\n", 695 ahc_name(ahc), 696 ahc->channel == 'B' ? 1 : 0); 697 } 698 699 } 700 } else if ((ahc->chip & AHC_CHIPID_MASK) >= AHC_AIC7870) { 701 u_int32_t devconfig; 702 703 devconfig = pci_read_config(dev, DEVCONFIG, /*bytes*/4); 704 if ((devconfig & RAMPSM) != 0 705 && (devconfig & MPORTMODE) != 0) { 706 707 /* XXX Assume 9bit SRAM and enable parity checking */ 708 devconfig |= EXTSCBPEN; 709 710 /* XXX Assume fast SRAM */ 711 devconfig &= ~EXTSCBTIME; 712 713 /* 714 * Set the bank select apropriately. 715 */ 716 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 717 if (ahc->channel == 'B') 718 ahc_outb(ahc, SCBBADDR, 1); 719 else 720 ahc_outb(ahc, SCBBADDR, 0); 721 } 722 723 /* Select external SRAM */ 724 devconfig &= ~SCBRAMSEL; 725 pci_write_config(dev, DEVCONFIG, devconfig, /*bytes*/4); 726 727 if (ahc_probe_scbs(ahc) == 0) { 728 /* External ram isn't really there */ 729 devconfig |= SCBRAMSEL; 730 pci_write_config(dev, DEVCONFIG, 731 devconfig, /*bytes*/4); 732 } else if (bootverbose) 733 printf("%s: External SRAM bank%d\n", 734 ahc_name(ahc), 735 ahc->channel == 'B' ? 1 : 0); 736 } 737 } 738 739 zero = 0; 740 ahc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &zero, 741 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE); 742 if (ahc->irq == NULL) { 743 ahc_free(ahc); 744 return (ENOMEM); 745 } 746 747 ahc->irq_res_type = SYS_RES_IRQ; 748 749 /* 750 * Do aic7880/aic7870/aic7860/aic7850 specific initialization 751 */ 752 { 753 u_int8_t sblkctl; 754 char *id_string; 755 756 switch(ahc_t) { 757 case AHC_AIC7896: 758 { 759 u_int dscommand0; 760 761 /* 762 * DPARCKEN doesn't work correctly on 763 * some MBs so don't use it. 764 */ 765 id_string = "aic7896/97 "; 766 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 767 dscommand0 &= ~(USCBSIZE32|DPARCKEN); 768 dscommand0 |= CACHETHEN|MPARCKEN; 769 ahc_outb(ahc, DSCOMMAND0, dscommand0); 770 break; 771 } 772 case AHC_AIC7890: 773 { 774 u_int dscommand0; 775 776 /* 777 * DPARCKEN doesn't work correctly on 778 * some MBs so don't use it. 779 */ 780 id_string = "aic7890/91 "; 781 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 782 dscommand0 &= ~(USCBSIZE32|DPARCKEN); 783 dscommand0 |= CACHETHEN|MPARCKEN; 784 ahc_outb(ahc, DSCOMMAND0, dscommand0); 785 break; 786 } 787 case AHC_AIC7895: 788 id_string = "aic7895 "; 789 break; 790 case AHC_AIC7880: 791 id_string = "aic7880 "; 792 break; 793 case AHC_AIC7870: 794 id_string = "aic7870 "; 795 break; 796 case AHC_AIC7860: 797 id_string = "aic7860 "; 798 break; 799 case AHC_AIC7859: 800 id_string = "aic7859 "; 801 break; 802 case AHC_AIC7855: 803 id_string = "aic7855 "; 804 break; 805 case AHC_AIC7850: 806 id_string = "aic7850 "; 807 break; 808 default: 809 printf("ahc: Unknown controller type. Ignoring.\n"); 810 ahc_free(ahc); 811 return (ENXIO); 812 } 813 814 /* See if we have an SEEPROM and perform auto-term */ 815 check_extport(ahc, &sxfrctl1); 816 817 /* 818 * Take the LED out of diagnostic mode 819 */ 820 sblkctl = ahc_inb(ahc, SBLKCTL); 821 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 822 823 /* 824 * I don't know where this is set in the SEEPROM or by the 825 * BIOS, so we default to 100% on Ultra or slower controllers 826 * and 75% on ULTRA2 controllers. 827 */ 828 if ((ahc->features & AHC_ULTRA2) != 0) { 829 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 830 } else { 831 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 832 } 833 834 if (ahc->flags & AHC_USEDEFAULTS) { 835 /* 836 * PCI Adapter default setup 837 * Should only be used if the adapter does not have 838 * an SEEPROM. 839 */ 840 /* See if someone else set us up already */ 841 if (scsiseq != 0) { 842 printf("%s: Using left over BIOS settings\n", 843 ahc_name(ahc)); 844 ahc->flags &= ~AHC_USEDEFAULTS; 845 } else { 846 /* 847 * Assume only one connector and always turn 848 * on termination. 849 */ 850 our_id = 0x07; 851 sxfrctl1 = STPWEN; 852 } 853 ahc_outb(ahc, SCSICONF, 854 (our_id & 0x07)|ENSPCHK|RESET_SCSI); 855 856 ahc->our_id = our_id; 857 } 858 859 printf("%s: %s", ahc_name(ahc), id_string); 860 } 861 862 /* 863 * Record our termination setting for the 864 * generic initialization routine. 865 */ 866 if ((sxfrctl1 & STPWEN) != 0) 867 ahc->flags |= AHC_TERM_ENB_A; 868 869 if (ahc_init(ahc)) { 870 ahc_free(ahc); 871 return (ENOMEM); 872 } 873 874 /* XXX Crude hack - fix sometime */ 875 if (ahc->flags & AHC_SHARED_SRAM) { 876 /* Only set this once we've successfully probed */ 877 if (shared_scb_data == NULL) 878 first_398X = ahc; 879 } 880 881 ahc_attach(ahc); 882 883 return (0); 884 } 885 886 /* 887 * Check the external port logic for a serial eeprom 888 * and termination/cable detection contrls. 889 */ 890 static void 891 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 892 { 893 struct seeprom_descriptor sd; 894 struct seeprom_config sc; 895 u_int8_t scsi_conf; 896 int have_seeprom; 897 898 sd.sd_tag = ahc->tag; 899 sd.sd_bsh = ahc->bsh; 900 sd.sd_control_offset = SEECTL; 901 sd.sd_status_offset = SEECTL; 902 sd.sd_dataout_offset = SEECTL; 903 904 /* 905 * For some multi-channel devices, the c46 is simply too 906 * small to work. For the other controller types, we can 907 * get our information from either SEEPROM type. Set the 908 * type to start our probe with accordingly. 909 */ 910 if (ahc->flags & AHC_LARGE_SEEPROM) 911 sd.sd_chip = C56_66; 912 else 913 sd.sd_chip = C46; 914 915 sd.sd_MS = SEEMS; 916 sd.sd_RDY = SEERDY; 917 sd.sd_CS = SEECS; 918 sd.sd_CK = SEECK; 919 sd.sd_DO = SEEDO; 920 sd.sd_DI = SEEDI; 921 922 have_seeprom = acquire_seeprom(ahc, &sd); 923 924 if (have_seeprom) { 925 926 if (bootverbose) 927 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 928 929 for (;;) { 930 bus_size_t start_addr; 931 932 start_addr = 32 * (ahc->channel - 'A'); 933 934 have_seeprom = read_seeprom(&sd, (u_int16_t *)&sc, 935 start_addr, sizeof(sc)/2); 936 937 if (have_seeprom) { 938 /* Check checksum */ 939 int i; 940 int maxaddr; 941 u_int16_t *scarray; 942 u_int16_t checksum; 943 944 maxaddr = (sizeof(sc)/2) - 1; 945 checksum = 0; 946 scarray = (u_int16_t *)≻ 947 948 for (i = 0; i < maxaddr; i++) 949 checksum = checksum + scarray[i]; 950 if (checksum == 0 || checksum != sc.checksum) { 951 if (bootverbose && sd.sd_chip == C56_66) 952 printf ("checksum error\n"); 953 have_seeprom = 0; 954 } else { 955 if (bootverbose) 956 printf("done.\n"); 957 break; 958 } 959 } 960 961 if (sd.sd_chip == C56_66) 962 break; 963 sd.sd_chip = C56_66; 964 } 965 } 966 967 if (!have_seeprom) { 968 if (bootverbose) 969 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 970 ahc->flags |= AHC_USEDEFAULTS; 971 } else { 972 /* 973 * Put the data we've collected down into SRAM 974 * where ahc_init will find it. 975 */ 976 int i; 977 int max_targ = sc.max_targets & CFMAXTARG; 978 u_int16_t discenable; 979 u_int16_t ultraenb; 980 981 discenable = 0; 982 ultraenb = 0; 983 if ((sc.adapter_control & CFULTRAEN) != 0) { 984 /* 985 * Determine if this adapter has a "newstyle" 986 * SEEPROM format. 987 */ 988 for (i = 0; i < max_targ; i++) { 989 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0){ 990 ahc->flags |= AHC_NEWEEPROM_FMT; 991 break; 992 } 993 } 994 } 995 996 for (i = 0; i < max_targ; i++) { 997 u_int scsirate; 998 u_int16_t target_mask; 999 1000 target_mask = 0x01 << i; 1001 if (sc.device_flags[i] & CFDISC) 1002 discenable |= target_mask; 1003 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1004 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) 1005 ultraenb |= target_mask; 1006 } else if ((sc.adapter_control & CFULTRAEN) != 0) { 1007 ultraenb |= target_mask; 1008 } 1009 if ((sc.device_flags[i] & CFXFER) == 0x04 1010 && (ultraenb & target_mask) != 0) { 1011 /* Treat 10MHz as a non-ultra speed */ 1012 sc.device_flags[i] &= ~CFXFER; 1013 ultraenb &= ~target_mask; 1014 } 1015 if ((ahc->features & AHC_ULTRA2) != 0) { 1016 u_int offset; 1017 1018 if (sc.device_flags[i] & CFSYNCH) 1019 offset = MAX_OFFSET_ULTRA2; 1020 else 1021 offset = 0; 1022 ahc_outb(ahc, TARG_OFFSET + i, offset); 1023 1024 scsirate = (sc.device_flags[i] & CFXFER) 1025 | ((ultraenb & target_mask) 1026 ? 0x18 : 0x10); 1027 if (sc.device_flags[i] & CFWIDEB) 1028 scsirate |= WIDEXFER; 1029 } else { 1030 scsirate = (sc.device_flags[i] & CFXFER) << 4; 1031 if (sc.device_flags[i] & CFSYNCH) 1032 scsirate |= SOFS; 1033 if (sc.device_flags[i] & CFWIDEB) 1034 scsirate |= WIDEXFER; 1035 } 1036 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1037 } 1038 ahc->our_id = sc.brtime_id & CFSCSIID; 1039 1040 scsi_conf = (ahc->our_id & 0x7); 1041 if (sc.adapter_control & CFSPARITY) 1042 scsi_conf |= ENSPCHK; 1043 if (sc.adapter_control & CFRESETB) 1044 scsi_conf |= RESET_SCSI; 1045 1046 if (sc.bios_control & CFEXTEND) 1047 ahc->flags |= AHC_EXTENDED_TRANS_A; 1048 if (ahc->features & AHC_ULTRA 1049 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1050 /* Should we enable Ultra mode? */ 1051 if (!(sc.adapter_control & CFULTRAEN)) 1052 /* Treat us as a non-ultra card */ 1053 ultraenb = 0; 1054 } 1055 /* Set SCSICONF info */ 1056 ahc_outb(ahc, SCSICONF, scsi_conf); 1057 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1058 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1059 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1060 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1061 } 1062 1063 if ((ahc->features & AHC_SPIOCAP) != 0) { 1064 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0) { 1065 configure_termination(ahc, &sc, &sd, sxfrctl1); 1066 } 1067 } else if (have_seeprom) { 1068 configure_termination(ahc, &sc, &sd, sxfrctl1); 1069 } 1070 1071 release_seeprom(&sd); 1072 } 1073 1074 static void 1075 configure_termination(struct ahc_softc *ahc, 1076 struct seeprom_config *sc, 1077 struct seeprom_descriptor *sd, 1078 u_int *sxfrctl1) 1079 { 1080 int max_targ = sc->max_targets & CFMAXTARG; 1081 u_int8_t brddat; 1082 1083 brddat = 0; 1084 1085 /* 1086 * Update the settings in sxfrctl1 to match the 1087 *termination settings 1088 */ 1089 *sxfrctl1 = 0; 1090 1091 /* 1092 * SEECS must be on for the GALS to latch 1093 * the data properly. Be sure to leave MS 1094 * on or we will release the seeprom. 1095 */ 1096 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1097 if ((sc->adapter_control & CFAUTOTERM) != 0 1098 || (ahc->features & AHC_ULTRA2) != 0) { 1099 int internal50_present; 1100 int internal68_present; 1101 int externalcable_present; 1102 int eeprom_present; 1103 int enableSEC_low; 1104 int enableSEC_high; 1105 int enablePRI_low; 1106 int enablePRI_high; 1107 1108 enableSEC_low = 0; 1109 enableSEC_high = 0; 1110 enablePRI_low = 0; 1111 enablePRI_high = 0; 1112 if (ahc->features & AHC_ULTRA2) { 1113 ahc_ultra2_term_detect(ahc, &enableSEC_low, 1114 &enableSEC_high, 1115 &enablePRI_low, 1116 &enablePRI_high, 1117 &eeprom_present); 1118 if ((sc->adapter_control & CFSEAUTOTERM) == 0) { 1119 enableSEC_low = (sc->adapter_control & CFSTERM); 1120 enableSEC_high = 1121 (sc->adapter_control & CFWSTERM); 1122 } 1123 if ((sc->adapter_control & CFAUTOTERM) == 0) { 1124 enablePRI_low = enablePRI_high = 1125 (sc->adapter_control & CFLVDSTERM); 1126 } 1127 /* Make the table calculations below happy */ 1128 internal50_present = 0; 1129 internal68_present = 1; 1130 externalcable_present = 1; 1131 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1132 aic785X_cable_detect(ahc, &internal50_present, 1133 &externalcable_present, 1134 &eeprom_present); 1135 } else { 1136 aic787X_cable_detect(ahc, &internal50_present, 1137 &internal68_present, 1138 &externalcable_present, 1139 &eeprom_present); 1140 } 1141 1142 if (max_targ <= 8) { 1143 internal68_present = 0; 1144 } 1145 1146 if (bootverbose) { 1147 if ((ahc->features & AHC_ULTRA2) == 0) { 1148 printf("%s: internal 50 cable %s present, " 1149 "internal 68 cable %s present\n", 1150 ahc_name(ahc), 1151 internal50_present ? "is":"not", 1152 internal68_present ? "is":"not"); 1153 1154 printf("%s: external cable %s present\n", 1155 ahc_name(ahc), 1156 externalcable_present ? "is":"not"); 1157 } 1158 printf("%s: BIOS eeprom %s present\n", 1159 ahc_name(ahc), eeprom_present ? "is" : "not"); 1160 1161 } 1162 1163 /* 1164 * Now set the termination based on what 1165 * we found. 1166 * Flash Enable = BRDDAT7 1167 * Secondary High Term Enable = BRDDAT6 1168 * Secondary Low Term Enable = BRDDAT5 (7890) 1169 * Primary High Term Enable = BRDDAT4 (7890) 1170 */ 1171 if ((ahc->features & AHC_ULTRA2) == 0 1172 && (internal50_present != 0) 1173 && (internal68_present != 0) 1174 && (externalcable_present != 0)) { 1175 printf("%s: Illegal cable configuration!!. " 1176 "Only two connectors on the " 1177 "adapter may be used at a " 1178 "time!\n", ahc_name(ahc)); 1179 } 1180 1181 if ((max_targ > 8) 1182 && ((externalcable_present == 0) 1183 || (internal68_present == 0) 1184 || (enableSEC_high != 0))) { 1185 brddat |= BRDDAT6; 1186 if (bootverbose) 1187 printf("%s: %sHigh byte termination Enabled\n", 1188 ahc_name(ahc), 1189 enableSEC_high ? "Secondary " : ""); 1190 } 1191 1192 if (((internal50_present ? 1 : 0) 1193 + (internal68_present ? 1 : 0) 1194 + (externalcable_present ? 1 : 0)) <= 1 1195 || (enableSEC_low != 0)) { 1196 if ((ahc->features & AHC_ULTRA2) != 0) 1197 brddat |= BRDDAT5; 1198 else 1199 *sxfrctl1 |= STPWEN; 1200 if (bootverbose) 1201 printf("%s: %sLow byte termination Enabled\n", 1202 ahc_name(ahc), 1203 enableSEC_low ? "Secondary " : ""); 1204 } 1205 1206 if (enablePRI_low != 0) { 1207 *sxfrctl1 |= STPWEN; 1208 if (bootverbose) 1209 printf("%s: Primary Low Byte termination " 1210 "Enabled\n", ahc_name(ahc)); 1211 } 1212 1213 if (enablePRI_high != 0) { 1214 brddat |= BRDDAT4; 1215 if (bootverbose) 1216 printf("%s: Primary High Byte " 1217 "termination Enabled\n", 1218 ahc_name(ahc)); 1219 } 1220 1221 write_brdctl(ahc, brddat); 1222 1223 } else { 1224 if (sc->adapter_control & CFSTERM) { 1225 if ((ahc->features & AHC_ULTRA2) != 0) 1226 brddat |= BRDDAT5; 1227 else 1228 *sxfrctl1 |= STPWEN; 1229 1230 if (bootverbose) 1231 printf("%s: %sLow byte termination Enabled\n", 1232 ahc_name(ahc), 1233 (ahc->features & AHC_ULTRA2) ? "Primary " 1234 : ""); 1235 } 1236 1237 if (sc->adapter_control & CFWSTERM) { 1238 brddat |= BRDDAT6; 1239 if (bootverbose) 1240 printf("%s: %sHigh byte termination Enabled\n", 1241 ahc_name(ahc), 1242 (ahc->features & AHC_ULTRA2) 1243 ? "Secondary " : ""); 1244 } 1245 1246 write_brdctl(ahc, brddat); 1247 } 1248 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1249 } 1250 1251 static void 1252 ahc_ultra2_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 1253 int *enableSEC_high, int *enablePRI_low, 1254 int *enablePRI_high, int *eeprom_present) 1255 { 1256 u_int8_t brdctl; 1257 1258 /* 1259 * BRDDAT7 = Eeprom 1260 * BRDDAT6 = Enable Secondary High Byte termination 1261 * BRDDAT5 = Enable Secondary Low Byte termination 1262 * BRDDAT4 = Enable Primary high byte termination 1263 * BRDDAT3 = Enable Primary low byte termination 1264 */ 1265 brdctl = read_brdctl(ahc); 1266 1267 *eeprom_present = brdctl & BRDDAT7; 1268 *enableSEC_high = (brdctl & BRDDAT6); 1269 *enableSEC_low = (brdctl & BRDDAT5); 1270 *enablePRI_high = (brdctl & BRDDAT4); 1271 *enablePRI_low = (brdctl & BRDDAT3); 1272 } 1273 1274 static void 1275 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1276 int *internal68_present, int *externalcable_present, 1277 int *eeprom_present) 1278 { 1279 u_int8_t brdctl; 1280 1281 /* 1282 * First read the status of our cables. 1283 * Set the rom bank to 0 since the 1284 * bank setting serves as a multiplexor 1285 * for the cable detection logic. 1286 * BRDDAT5 controls the bank switch. 1287 */ 1288 write_brdctl(ahc, 0); 1289 1290 /* 1291 * Now read the state of the internal 1292 * connectors. BRDDAT6 is INT50 and 1293 * BRDDAT7 is INT68. 1294 */ 1295 brdctl = read_brdctl(ahc); 1296 *internal50_present = !(brdctl & BRDDAT6); 1297 *internal68_present = !(brdctl & BRDDAT7); 1298 1299 /* 1300 * Set the rom bank to 1 and determine 1301 * the other signals. 1302 */ 1303 write_brdctl(ahc, BRDDAT5); 1304 1305 /* 1306 * Now read the state of the external 1307 * connectors. BRDDAT6 is EXT68 and 1308 * BRDDAT7 is EPROMPS. 1309 */ 1310 brdctl = read_brdctl(ahc); 1311 *externalcable_present = !(brdctl & BRDDAT6); 1312 *eeprom_present = brdctl & BRDDAT7; 1313 } 1314 1315 static void 1316 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1317 int *externalcable_present, int *eeprom_present) 1318 { 1319 u_int8_t brdctl; 1320 1321 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1322 ahc_outb(ahc, BRDCTL, 0); 1323 brdctl = ahc_inb(ahc, BRDCTL); 1324 *internal50_present = !(brdctl & BRDDAT5); 1325 *externalcable_present = !(brdctl & BRDDAT6); 1326 1327 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) != 0; 1328 } 1329 1330 static int 1331 acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1332 { 1333 int wait; 1334 1335 if ((ahc->features & AHC_SPIOCAP) != 0 1336 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1337 return (0); 1338 1339 /* 1340 * Request access of the memory port. When access is 1341 * granted, SEERDY will go high. We use a 1 second 1342 * timeout which should be near 1 second more than 1343 * is needed. Reason: after the chip reset, there 1344 * should be no contention. 1345 */ 1346 SEEPROM_OUTB(sd, sd->sd_MS); 1347 wait = 1000; /* 1 second timeout in msec */ 1348 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1349 DELAY(1000); /* delay 1 msec */ 1350 } 1351 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1352 SEEPROM_OUTB(sd, 0); 1353 return (0); 1354 } 1355 return(1); 1356 } 1357 1358 static void 1359 release_seeprom(sd) 1360 struct seeprom_descriptor *sd; 1361 { 1362 /* Release access to the memory port and the serial EEPROM. */ 1363 SEEPROM_OUTB(sd, 0); 1364 } 1365 1366 static void 1367 write_brdctl(ahc, value) 1368 struct ahc_softc *ahc; 1369 u_int8_t value; 1370 { 1371 u_int8_t brdctl; 1372 1373 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1374 brdctl = BRDSTB; 1375 if (ahc->channel == 'B') 1376 brdctl |= BRDCS; 1377 } else if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7890) { 1378 brdctl = 0; 1379 } else { 1380 brdctl = BRDSTB|BRDCS; 1381 } 1382 ahc_outb(ahc, BRDCTL, brdctl); 1383 brdctl |= value; 1384 ahc_outb(ahc, BRDCTL, brdctl); 1385 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7890) 1386 brdctl |= BRDSTB_ULTRA2; 1387 else 1388 brdctl &= ~BRDSTB; 1389 ahc_outb(ahc, BRDCTL, brdctl); 1390 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7890) 1391 brdctl = 0; 1392 else 1393 brdctl &= ~BRDCS; 1394 ahc_outb(ahc, BRDCTL, brdctl); 1395 } 1396 1397 static u_int8_t 1398 read_brdctl(ahc) 1399 struct ahc_softc *ahc; 1400 { 1401 u_int8_t brdctl; 1402 u_int8_t value; 1403 1404 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1405 brdctl = BRDRW; 1406 if (ahc->channel == 'B') 1407 brdctl |= BRDCS; 1408 } else if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7890) { 1409 brdctl = BRDRW_ULTRA2; 1410 } else { 1411 brdctl = BRDRW|BRDCS; 1412 } 1413 ahc_outb(ahc, BRDCTL, brdctl); 1414 value = ahc_inb(ahc, BRDCTL); 1415 ahc_outb(ahc, BRDCTL, 0); 1416 return (value); 1417 } 1418 1419 #define DPE 0x80 1420 #define SSE 0x40 1421 #define RMA 0x20 1422 #define RTA 0x10 1423 #define STA 0x08 1424 #define DPR 0x01 1425 1426 void 1427 ahc_pci_intr(struct ahc_softc *ahc) 1428 { 1429 u_int8_t status1; 1430 1431 status1 = pci_read_config(ahc->device, PCIR_STATUS + 1, /*bytes*/1); 1432 1433 if (status1 & DPE) { 1434 printf("%s: Data Parity Error Detected during address " 1435 "or write data phase\n", ahc_name(ahc)); 1436 } 1437 if (status1 & SSE) { 1438 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1439 } 1440 if (status1 & RMA) { 1441 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1442 } 1443 if (status1 & RTA) { 1444 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1445 } 1446 if (status1 & STA) { 1447 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1448 } 1449 if (status1 & DPR) { 1450 printf("%s: Data Parity Error has been reported via PERR#\n", 1451 ahc_name(ahc)); 1452 } 1453 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1454 printf("%s: Latched PCIERR interrupt with " 1455 "no status bits set\n", ahc_name(ahc)); 1456 } 1457 pci_write_config(ahc->device, PCIR_STATUS + 1, status1, /*bytes*/1); 1458 1459 if (status1 & (DPR|RMA|RTA)) { 1460 ahc_outb(ahc, CLRINT, CLRPARERR); 1461 } 1462 } 1463 1464 static int 1465 ahc_aic7850_setup(device_t dev, char *channel, ahc_chip *chip, 1466 ahc_feature *features, ahc_flag *flags) 1467 { 1468 *channel = 'A'; 1469 *chip = AHC_AIC7850; 1470 *features = AHC_AIC7850_FE; 1471 return (0); 1472 } 1473 1474 static int 1475 ahc_aic7855_setup(device_t dev, char *channel, ahc_chip *chip, 1476 ahc_feature *features, ahc_flag *flags) 1477 { 1478 *channel = 'A'; 1479 *chip = AHC_AIC7855; 1480 *features = AHC_AIC7855_FE; 1481 return (0); 1482 } 1483 1484 static int 1485 ahc_aic7859_setup(device_t dev, char *channel, ahc_chip *chip, 1486 ahc_feature *features, ahc_flag *flags) 1487 { 1488 *channel = 'A'; 1489 *chip = AHC_AIC7859; 1490 *features = AHC_AIC7859_FE; 1491 return (0); 1492 } 1493 1494 static int 1495 ahc_aic7860_setup(device_t dev, char *channel, ahc_chip *chip, 1496 ahc_feature *features, ahc_flag *flags) 1497 { 1498 *channel = 'A'; 1499 *chip = AHC_AIC7860; 1500 *features = AHC_AIC7860_FE; 1501 return (0); 1502 } 1503 1504 static int 1505 ahc_aic7870_setup(device_t dev, char *channel, ahc_chip *chip, 1506 ahc_feature *features, ahc_flag *flags) 1507 { 1508 *channel = 'A'; 1509 *chip = AHC_AIC7870; 1510 *features = AHC_AIC7870_FE; 1511 return (0); 1512 } 1513 1514 static int 1515 ahc_aha394X_setup(device_t dev, char *channel, ahc_chip *chip, 1516 ahc_feature *features, ahc_flag *flags) 1517 { 1518 int error; 1519 1520 error = ahc_aic7870_setup(dev, channel, chip, features, flags); 1521 if (error == 0) 1522 error = ahc_aha394XX_setup(dev, channel, chip, features, flags); 1523 return (error); 1524 } 1525 1526 static int 1527 ahc_aha398X_setup(device_t dev, char *channel, ahc_chip *chip, 1528 ahc_feature *features, ahc_flag *flags) 1529 { 1530 int error; 1531 1532 error = ahc_aic7870_setup(dev, channel, chip, features, flags); 1533 if (error == 0) 1534 error = ahc_aha398XX_setup(dev, channel, chip, features, flags); 1535 return (error); 1536 } 1537 1538 static int 1539 ahc_aic7880_setup(device_t dev, char *channel, ahc_chip *chip, 1540 ahc_feature *features, ahc_flag *flags) 1541 { 1542 *channel = 'A'; 1543 *chip = AHC_AIC7880; 1544 *features = AHC_AIC7880_FE; 1545 return (0); 1546 } 1547 1548 static int 1549 ahc_aha394XU_setup(device_t dev, char *channel, ahc_chip *chip, 1550 ahc_feature *features, ahc_flag *flags) 1551 { 1552 int error; 1553 1554 error = ahc_aic7880_setup(dev, channel, chip, features, flags); 1555 if (error == 0) 1556 error = ahc_aha394XX_setup(dev, channel, chip, features, flags); 1557 return (error); 1558 } 1559 1560 static int 1561 ahc_aha398XU_setup(device_t dev, char *channel, ahc_chip *chip, 1562 ahc_feature *features, ahc_flag *flags) 1563 { 1564 int error; 1565 1566 error = ahc_aic7880_setup(dev, channel, chip, features, flags); 1567 if (error == 0) 1568 error = ahc_aha398XX_setup(dev, channel, chip, features, flags); 1569 return (error); 1570 } 1571 1572 static int 1573 ahc_aic7890_setup(device_t dev, char *channel, ahc_chip *chip, 1574 ahc_feature *features, ahc_flag *flags) 1575 { 1576 *channel = 'A'; 1577 *chip = AHC_AIC7890; 1578 *features = AHC_AIC7890_FE; 1579 *flags |= AHC_NEWEEPROM_FMT; 1580 return (0); 1581 } 1582 1583 static int 1584 ahc_aic7895_setup(device_t dev, char *channel, ahc_chip *chip, 1585 ahc_feature *features, ahc_flag *flags) 1586 { 1587 u_int32_t devconfig; 1588 1589 *channel = pci_get_function(dev) == 1 ? 'B' : 'A'; 1590 *chip = AHC_AIC7895; 1591 /* The 'C' revision of the aic7895 has a few additional features */ 1592 if (pci_get_revid(dev) >= 4) 1593 *features = AHC_AIC7895C_FE; 1594 else 1595 *features = AHC_AIC7895_FE; 1596 *flags |= AHC_NEWEEPROM_FMT; 1597 devconfig = pci_read_config(dev, DEVCONFIG, /*bytes*/4); 1598 devconfig &= ~SCBSIZE32; 1599 pci_write_config(dev, DEVCONFIG, devconfig, /*bytes*/4); 1600 return (0); 1601 } 1602 1603 static int 1604 ahc_aic7896_setup(device_t dev, char *channel, ahc_chip *chip, 1605 ahc_feature *features, ahc_flag *flags) 1606 { 1607 *channel = pci_get_function(dev) == 1 ? 'B' : 'A'; 1608 *chip = AHC_AIC7896; 1609 *features = AHC_AIC7896_FE; 1610 *flags |= AHC_NEWEEPROM_FMT; 1611 return (0); 1612 } 1613 1614 static int 1615 ahc_raid_setup(device_t dev, char *channel, ahc_chip *chip, 1616 ahc_feature *features, ahc_flag *flags) 1617 { 1618 printf("RAID functionality unsupported\n"); 1619 return (ENXIO); 1620 } 1621 1622 static int 1623 ahc_aha394XX_setup(device_t dev, char *channel, ahc_chip *chip, 1624 ahc_feature *features, ahc_flag *flags) 1625 { 1626 switch (pci_get_slot(dev)) { 1627 case AHC_394X_SLOT_CHANNEL_A: 1628 *channel = 'A'; 1629 break; 1630 case AHC_394X_SLOT_CHANNEL_B: 1631 *channel = 'B'; 1632 break; 1633 default: 1634 printf("adapter at unexpected slot %d\n" 1635 "unable to map to a channel\n", 1636 pci_get_slot(dev)); 1637 } 1638 return (0); 1639 } 1640 1641 static int 1642 ahc_aha398XX_setup(device_t dev, char *channel, ahc_chip *chip, 1643 ahc_feature *features, ahc_flag *flags) 1644 { 1645 switch (pci_get_slot(dev)) { 1646 case AHC_398X_SLOT_CHANNEL_A: 1647 *channel = 'A'; 1648 break; 1649 case AHC_398X_SLOT_CHANNEL_B: 1650 *channel = 'B'; 1651 break; 1652 case AHC_398X_SLOT_CHANNEL_C: 1653 *channel = 'C'; 1654 break; 1655 default: 1656 printf("adapter at unexpected slot %d\n" 1657 "unable to map to a channel\n", 1658 pci_get_slot(dev)); 1659 } 1660 *flags |= AHC_LARGE_SEEPROM; 1661 return (0); 1662 } 1663