xref: /freebsd/sys/dev/aic7xxx/ahc_pci.c (revision 4b2eaea43fec8e8792be611dea204071a10b655a)
1 /*
2  * FreeBSD, PCI product support functions
3  *
4  * Copyright (c) 1995-2001 Justin T. Gibbs
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions, and the following disclaimer,
12  *    without modification, immediately at the beginning of the file.
13  * 2. The name of the author may not be used to endorse or promote products
14  *    derived from this software without specific prior written permission.
15  *
16  * Alternatively, this software may be distributed under the terms of the
17  * GNU Public License ("GPL").
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
23  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29  * SUCH DAMAGE.
30  *
31  * $Id: //depot/aic7xxx/freebsd/dev/aic7xxx/ahc_pci.c#12 $
32  *
33  * $FreeBSD$
34  */
35 
36 #include <dev/aic7xxx/aic7xxx_osm.h>
37 
38 #define	AHC_PCI_IOADDR  PCIR_MAPS	/* I/O Address */
39 #define	AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */
40 
41 static int ahc_pci_probe(device_t dev);
42 static int ahc_pci_attach(device_t dev);
43 
44 static device_method_t ahc_pci_device_methods[] = {
45 	/* Device interface */
46 	DEVMETHOD(device_probe,		ahc_pci_probe),
47 	DEVMETHOD(device_attach,	ahc_pci_attach),
48 	DEVMETHOD(device_detach,	ahc_detach),
49 	{ 0, 0 }
50 };
51 
52 static driver_t ahc_pci_driver = {
53 	"ahc",
54 	ahc_pci_device_methods,
55 	sizeof(struct ahc_softc)
56 };
57 
58 DRIVER_MODULE(ahc_pci, pci, ahc_pci_driver, ahc_devclass, 0, 0);
59 DRIVER_MODULE(ahc_pci, cardbus, ahc_pci_driver, ahc_devclass, 0, 0);
60 MODULE_DEPEND(ahc_pci, ahc, 1, 1, 1);
61 MODULE_VERSION(ahc_pci, 1);
62 
63 static int
64 ahc_pci_probe(device_t dev)
65 {
66 	struct	ahc_pci_identity *entry;
67 
68 	entry = ahc_find_pci_device(dev);
69 	if (entry != NULL) {
70 		device_set_desc(dev, entry->name);
71 		return (0);
72 	}
73 	return (ENXIO);
74 }
75 
76 static int
77 ahc_pci_attach(device_t dev)
78 {
79 	struct	 ahc_pci_identity *entry;
80 	struct	 ahc_softc *ahc;
81 	char	*name;
82 	int	 error;
83 
84 	entry = ahc_find_pci_device(dev);
85 	if (entry == NULL)
86 		return (ENXIO);
87 
88 	/*
89 	 * Allocate a softc for this card and
90 	 * set it up for attachment by our
91 	 * common detect routine.
92 	 */
93 	name = malloc(strlen(device_get_nameunit(dev)) + 1, M_DEVBUF, M_NOWAIT);
94 	if (name == NULL)
95 		return (ENOMEM);
96 	strcpy(name, device_get_nameunit(dev));
97 	ahc = ahc_alloc(dev, name);
98 	if (ahc == NULL)
99 		return (ENOMEM);
100 
101 	ahc_set_unit(ahc, device_get_unit(dev));
102 
103 	/*
104 	 * Should we bother disabling 39Bit addressing
105 	 * based on installed memory?
106 	 */
107 	if (sizeof(bus_addr_t) > 4)
108                 ahc->flags |= AHC_39BIT_ADDRESSING;
109 
110 	/* Allocate a dmatag for our SCB DMA maps */
111 	/* XXX Should be a child of the PCI bus dma tag */
112 	error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1,
113 				   /*boundary*/0,
114 				   (ahc->flags & AHC_39BIT_ADDRESSING)
115 				   ? 0x7FFFFFFFFF
116 				   : BUS_SPACE_MAXADDR_32BIT,
117 				   /*highaddr*/BUS_SPACE_MAXADDR,
118 				   /*filter*/NULL, /*filterarg*/NULL,
119 				   /*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
120 				   /*nsegments*/AHC_NSEG,
121 				   /*maxsegsz*/AHC_MAXTRANSFER_SIZE,
122 				   /*flags*/BUS_DMA_ALLOCNOW,
123 				   &ahc->parent_dmat);
124 
125 	if (error != 0) {
126 		printf("ahc_pci_attach: Could not allocate DMA tag "
127 		       "- error %d\n", error);
128 		ahc_free(ahc);
129 		return (ENOMEM);
130 	}
131 	ahc->dev_softc = dev;
132 	error = ahc_pci_config(ahc, entry);
133 	if (error != 0) {
134 		ahc_free(ahc);
135 		return (error);
136 	}
137 
138 	ahc_attach(ahc);
139 	return (0);
140 }
141 
142 int
143 ahc_pci_map_registers(struct ahc_softc *ahc)
144 {
145 	struct	resource *regs;
146 	u_int	command;
147 	int	regs_type;
148 	int	regs_id;
149 	int	allow_memio;
150 
151 	command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
152 	regs = NULL;
153 	regs_type = 0;
154 	regs_id = 0;
155 
156 	/* Retrieve the per-device 'allow_memio' hint */
157 	if (resource_int_value(device_get_name(ahc->dev_softc),
158 			       device_get_unit(ahc->dev_softc),
159 			       "allow_memio", &allow_memio) != 0) {
160 		if (bootverbose)
161 			device_printf(ahc->dev_softc, "Defaulting to MEMIO ");
162 #ifdef AHC_ALLOW_MEMIO
163 		if (bootverbose)
164 			printf("on\n");
165 		allow_memio = 1;
166 #else
167 		if (bootverbose)
168 			printf("off\n");
169 		allow_memio = 0;
170 #endif
171 	}
172 
173 	if ((allow_memio != 0) && (command & PCIM_CMD_MEMEN) != 0) {
174 
175 		regs_type = SYS_RES_MEMORY;
176 		regs_id = AHC_PCI_MEMADDR;
177 		regs = bus_alloc_resource(ahc->dev_softc, regs_type,
178 					  &regs_id, 0, ~0, 1, RF_ACTIVE);
179 		if (regs != NULL) {
180 			ahc->tag = rman_get_bustag(regs);
181 			ahc->bsh = rman_get_bushandle(regs);
182 
183 			/*
184 			 * Do a quick test to see if memory mapped
185 			 * I/O is functioning correctly.
186 			 */
187 			if (ahc_pci_test_register_access(ahc) != 0) {
188 				device_printf(ahc->dev_softc,
189 				       "PCI Device %d:%d:%d failed memory "
190 				       "mapped test.  Using PIO.\n",
191 				       ahc_get_pci_bus(ahc->dev_softc),
192 				       ahc_get_pci_slot(ahc->dev_softc),
193 				       ahc_get_pci_function(ahc->dev_softc));
194 				bus_release_resource(ahc->dev_softc, regs_type,
195 						     regs_id, regs);
196 				regs = NULL;
197 			} else {
198 				command &= ~PCIM_CMD_PORTEN;
199 				ahc_pci_write_config(ahc->dev_softc,
200 						     PCIR_COMMAND,
201 						     command, /*bytes*/1);
202 			}
203 		}
204 	}
205 
206 	if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) {
207 		regs_type = SYS_RES_IOPORT;
208 		regs_id = AHC_PCI_IOADDR;
209 		regs = bus_alloc_resource(ahc->dev_softc, regs_type,
210 					  &regs_id, 0, ~0, 1, RF_ACTIVE);
211 		if (regs != NULL) {
212 			ahc->tag = rman_get_bustag(regs);
213 			ahc->bsh = rman_get_bushandle(regs);
214 			command &= ~PCIM_CMD_MEMEN;
215 			ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
216 					     command, /*bytes*/1);
217 		}
218 	}
219 	if (regs == NULL) {
220 		device_printf(ahc->dev_softc,
221 			      "can't allocate register resources\n");
222 		return (ENOMEM);
223 	}
224 	ahc->platform_data->regs_res_type = regs_type;
225 	ahc->platform_data->regs_res_id = regs_id;
226 	ahc->platform_data->regs = regs;
227 	return (0);
228 }
229 
230 int
231 ahc_pci_map_int(struct ahc_softc *ahc)
232 {
233 	int zero;
234 
235 	zero = 0;
236 	ahc->platform_data->irq =
237 	    bus_alloc_resource(ahc->dev_softc, SYS_RES_IRQ, &zero,
238 			       0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
239 	if (ahc->platform_data->irq == NULL) {
240 		device_printf(ahc->dev_softc,
241 			      "bus_alloc_resource() failed to allocate IRQ\n");
242 		return (ENOMEM);
243 	}
244 	ahc->platform_data->irq_res_type = SYS_RES_IRQ;
245 	return (ahc_map_int(ahc));
246 }
247 
248 void
249 ahc_power_state_change(struct ahc_softc *ahc, ahc_power_state new_state)
250 {
251 	uint32_t cap;
252 	u_int cap_offset;
253 
254 	/*
255 	 * Traverse the capability list looking for
256 	 * the power management capability.
257 	 */
258 	cap = 0;
259 	cap_offset = ahc_pci_read_config(ahc->dev_softc,
260 					 PCIR_CAP_PTR, /*bytes*/1);
261 	while (cap_offset != 0) {
262 
263 		cap = ahc_pci_read_config(ahc->dev_softc,
264 					  cap_offset, /*bytes*/4);
265 		if ((cap & 0xFF) == 1
266 		 && ((cap >> 16) & 0x3) > 0) {
267 			uint32_t pm_control;
268 
269 			pm_control = ahc_pci_read_config(ahc->dev_softc,
270 							 cap_offset + 4,
271 							 /*bytes*/2);
272 			pm_control &= ~0x3;
273 			pm_control |= new_state;
274 			ahc_pci_write_config(ahc->dev_softc,
275 					     cap_offset + 4,
276 					     pm_control, /*bytes*/2);
277 			break;
278 		}
279 		cap_offset = (cap >> 8) & 0xFF;
280 	}
281 }
282