1 /* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1995, 1996, 1997, 1998 Justin T. Gibbs 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification, immediately at the beginning of the file. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * Where this Software is combined with software released under the terms of 19 * the GNU Public License ("GPL") and the terms of the GPL would require the 20 * combined work to also be released under the terms of the GPL, the terms 21 * and conditions of this License will apply in addition to those of the 22 * GPL with the exception of any terms or conditions of this License that 23 * conflict with, or are expressly prohibited by, the GPL. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 29 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $Id: ahc_pci.c,v 1.4 1998/12/14 05:47:25 dillon Exp $ 38 */ 39 40 #include <pci.h> 41 #if NPCI > 0 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/queue.h> 46 47 #include <pci/pcireg.h> 48 #include <pci/pcivar.h> 49 50 #include <machine/bus_memio.h> 51 #include <machine/bus_pio.h> 52 #include <machine/bus.h> 53 #include <machine/clock.h> 54 55 #include <cam/cam.h> 56 #include <cam/cam_ccb.h> 57 #include <cam/cam_sim.h> 58 #include <cam/cam_xpt_sim.h> 59 60 #include <cam/scsi/scsi_all.h> 61 62 #include <dev/aic7xxx/aic7xxx.h> 63 #include <dev/aic7xxx/93cx6.h> 64 65 #include <aic7xxx_reg.h> 66 67 #define PCI_BASEADR0 PCI_MAP_REG_START /* I/O Address */ 68 #define PCI_BASEADR1 PCI_MAP_REG_START + 4 /* Mem I/O Address */ 69 70 #define PCI_DEVICE_ID_ADAPTEC_398XU 0x83789004ul 71 #define PCI_DEVICE_ID_ADAPTEC_3940U 0x82789004ul 72 #define PCI_DEVICE_ID_ADAPTEC_2944U 0x84789004ul 73 #define PCI_DEVICE_ID_ADAPTEC_2940U 0x81789004ul 74 #define PCI_DEVICE_ID_ADAPTEC_2940AU 0x61789004ul 75 #define PCI_DEVICE_ID_ADAPTEC_2940U2 0x00109005ul 76 #define PCI_DEVICE_ID_ADAPTEC_398X 0x73789004ul 77 #define PCI_DEVICE_ID_ADAPTEC_3940 0x72789004ul 78 #define PCI_DEVICE_ID_ADAPTEC_2944 0x74789004ul 79 #define PCI_DEVICE_ID_ADAPTEC_2940 0x71789004ul 80 #define PCI_DEVICE_ID_ADAPTEC_AIC7890 0x001F9005ul 81 #define PCI_DEVICE_ID_ADAPTEC_AIC7895 0x78959004ul 82 #define PCI_DEVICE_ID_ADAPTEC_AIC7896 0x005F9005ul 83 #define PCI_DEVICE_ID_ADAPTEC_AIC7880 0x80789004ul 84 #define PCI_DEVICE_ID_ADAPTEC_AIC7870 0x70789004ul 85 #define PCI_DEVICE_ID_ADAPTEC_AIC7860 0x60789004ul 86 #define PCI_DEVICE_ID_ADAPTEC_AIC7855 0x55789004ul 87 #define PCI_DEVICE_ID_ADAPTEC_AIC7850 0x50789004ul 88 #define PCI_DEVICE_ID_ADAPTEC_AIC7810 0x10789004ul 89 90 #define AHC_394X_SLOT_CHANNEL_A 4 91 #define AHC_394X_SLOT_CHANNEL_B 5 92 93 #define AHC_398X_SLOT_CHANNEL_A 4 94 #define AHC_398X_SLOT_CHANNEL_B 8 95 #define AHC_398X_SLOT_CHANNEL_C 12 96 97 #define DEVCONFIG 0x40 98 #define SCBSIZE32 0x00010000ul /* aic789X only */ 99 #define MPORTMODE 0x00000400ul /* aic7870 only */ 100 #define RAMPSM 0x00000200ul /* aic7870 only */ 101 #define VOLSENSE 0x00000100ul 102 #define SCBRAMSEL 0x00000080ul 103 #define MRDCEN 0x00000040ul 104 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 105 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 106 #define BERREN 0x00000008ul 107 #define DACEN 0x00000004ul 108 #define STPWLEVEL 0x00000002ul 109 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 110 111 #define CSIZE_LATTIME 0x0c 112 #define CACHESIZE 0x0000003ful /* only 5 bits */ 113 #define LATTIME 0x0000ff00ul 114 115 static void check_extport(struct ahc_softc *ahc, u_int8_t *sxfrctl1); 116 static void configure_termination(struct ahc_softc *ahc, 117 struct seeprom_config *sc, 118 struct seeprom_descriptor *sd, 119 u_int8_t *sxfrctl1); 120 121 static void ahc_ultra2_term_detect(struct ahc_softc *ahc, 122 int *enableSEC_low, 123 int *enableSEC_high, 124 int *enablePRI_low, 125 int *enablePRI_high, 126 int *eeprom_present); 127 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 128 int *internal68_present, 129 int *externalcable_present, 130 int *eeprom_present); 131 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 132 int *externalcable_present, 133 int *eeprom_present); 134 static int acquire_seeprom(struct ahc_softc *ahc, 135 struct seeprom_descriptor *sd); 136 static void release_seeprom(struct seeprom_descriptor *sd); 137 static void write_brdctl(struct ahc_softc *ahc, u_int8_t value); 138 static u_int8_t read_brdctl(struct ahc_softc *ahc); 139 140 static struct ahc_softc *first_398X; 141 142 static const char* ahc_pci_probe(pcici_t tag, pcidi_t type); 143 static void ahc_pci_attach(pcici_t config_id, int unit); 144 145 /* Exported for use in the ahc_intr routine */ 146 void ahc_pci_intr(struct ahc_softc *ahc); 147 148 static struct pci_device ahc_pci_driver = { 149 "ahc", 150 ahc_pci_probe, 151 ahc_pci_attach, 152 &ahc_unit, 153 NULL 154 }; 155 156 DATA_SET (pcidevice_set, ahc_pci_driver); 157 158 static const char* 159 ahc_pci_probe (pcici_t tag, pcidi_t type) 160 { 161 switch (type) { 162 case PCI_DEVICE_ID_ADAPTEC_398XU: 163 return ("Adaptec 398X Ultra SCSI RAID adapter"); 164 break; 165 case PCI_DEVICE_ID_ADAPTEC_3940U: 166 return ("Adaptec 3940 Ultra SCSI host adapter"); 167 break; 168 case PCI_DEVICE_ID_ADAPTEC_398X: 169 return ("Adaptec 398X SCSI RAID adapter"); 170 break; 171 case PCI_DEVICE_ID_ADAPTEC_3940: 172 return ("Adaptec 3940 SCSI adapter"); 173 break; 174 case PCI_DEVICE_ID_ADAPTEC_2944U: 175 return ("Adaptec 2944 Ultra SCSI adapter"); 176 break; 177 case PCI_DEVICE_ID_ADAPTEC_2940U: 178 return ("Adaptec 2940 Ultra SCSI adapter"); 179 break; 180 case PCI_DEVICE_ID_ADAPTEC_2940U2: 181 return ("Adaptec 2940 Ultra2 SCSI adapter"); 182 break; 183 case PCI_DEVICE_ID_ADAPTEC_2944: 184 return ("Adaptec 2944 SCSI adapter"); 185 break; 186 case PCI_DEVICE_ID_ADAPTEC_2940: 187 return ("Adaptec 2940 SCSI adapter"); 188 break; 189 case PCI_DEVICE_ID_ADAPTEC_2940AU: 190 return ("Adaptec 2940A Ultra SCSI adapter"); 191 break; 192 case PCI_DEVICE_ID_ADAPTEC_AIC7895: 193 return ("Adaptec aic7895 Ultra SCSI adapter"); 194 break; 195 case PCI_DEVICE_ID_ADAPTEC_AIC7890: 196 return ("Adaptec aic7890/91 Ultra2 SCSI adapter"); 197 break; 198 case PCI_DEVICE_ID_ADAPTEC_AIC7896: 199 return ("Adaptec aic7896/97 Ultra2 SCSI adapter"); 200 break; 201 case PCI_DEVICE_ID_ADAPTEC_AIC7880: 202 return ("Adaptec aic7880 Ultra SCSI adapter"); 203 break; 204 case PCI_DEVICE_ID_ADAPTEC_AIC7870: 205 return ("Adaptec aic7870 SCSI adapter"); 206 break; 207 case PCI_DEVICE_ID_ADAPTEC_AIC7860: 208 return ("Adaptec aic7860 SCSI adapter"); 209 break; 210 case PCI_DEVICE_ID_ADAPTEC_AIC7855: 211 return ("Adaptec aic7855 SCSI adapter"); 212 break; 213 case PCI_DEVICE_ID_ADAPTEC_AIC7850: 214 return ("Adaptec aic7850 SCSI adapter"); 215 break; 216 case PCI_DEVICE_ID_ADAPTEC_AIC7810: 217 return ("Adaptec aic7810 RAID memory controller"); 218 break; 219 default: 220 break; 221 } 222 return (0); 223 224 } 225 226 static void 227 ahc_pci_attach(pcici_t config_id, int unit) 228 { 229 u_int16_t io_port; 230 struct ahc_softc *ahc; 231 u_int32_t id; 232 u_int32_t command; 233 struct scb_data *shared_scb_data; 234 int opri; 235 ahc_chip ahc_t = AHC_NONE; 236 ahc_feature ahc_fe = AHC_FENONE; 237 ahc_flag ahc_f = AHC_FNONE; 238 vm_offset_t vaddr; 239 vm_offset_t paddr; 240 u_int8_t our_id = 0; 241 u_int8_t sxfrctl1; 242 u_int8_t scsiseq; 243 int error; 244 char channel; 245 246 if (config_id->func == 1) 247 channel = 'B'; 248 else 249 channel = 'A'; 250 shared_scb_data = NULL; 251 vaddr = NULL; 252 paddr = NULL; 253 io_port = 0; 254 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 255 #ifdef AHC_ALLOW_MEMIO 256 if ((command & PCI_COMMAND_MEM_ENABLE) == 0 257 || (pci_map_mem(config_id, PCI_BASEADR1, &vaddr, &paddr)) == 0) 258 #endif 259 if ((command & PCI_COMMAND_IO_ENABLE) == 0 260 || (pci_map_port(config_id, PCI_BASEADR0, &io_port)) == 0) 261 return; 262 263 switch ((id = pci_conf_read(config_id, PCI_ID_REG))) { 264 case PCI_DEVICE_ID_ADAPTEC_398XU: 265 case PCI_DEVICE_ID_ADAPTEC_398X: 266 if (id == PCI_DEVICE_ID_ADAPTEC_398XU) { 267 ahc_t = AHC_AIC7880; 268 ahc_fe = AHC_AIC7880_FE; 269 } else { 270 ahc_t = AHC_AIC7870; 271 ahc_fe = AHC_AIC7870_FE; 272 } 273 274 switch (config_id->slot) { 275 case AHC_398X_SLOT_CHANNEL_A: 276 break; 277 case AHC_398X_SLOT_CHANNEL_B: 278 channel = 'B'; 279 break; 280 case AHC_398X_SLOT_CHANNEL_C: 281 channel = 'C'; 282 break; 283 default: 284 printf("adapter at unexpected slot %d\n" 285 "unable to map to a channel\n", 286 config_id->slot); 287 } 288 ahc_f |= AHC_LARGE_SEEPROM; 289 break; 290 case PCI_DEVICE_ID_ADAPTEC_3940U: 291 case PCI_DEVICE_ID_ADAPTEC_3940: 292 if (id == PCI_DEVICE_ID_ADAPTEC_3940U) { 293 ahc_t = AHC_AIC7880; 294 ahc_fe = AHC_AIC7880_FE; 295 } else { 296 ahc_t = AHC_AIC7870; 297 ahc_fe = AHC_AIC7870_FE; 298 } 299 300 switch (config_id->slot) { 301 case AHC_394X_SLOT_CHANNEL_A: 302 break; 303 case AHC_394X_SLOT_CHANNEL_B: 304 channel = 'B'; 305 break; 306 default: 307 printf("adapter at unexpected slot %d\n" 308 "unable to map to a channel\n", 309 config_id->slot); 310 } 311 break; 312 case PCI_DEVICE_ID_ADAPTEC_AIC7890: 313 case PCI_DEVICE_ID_ADAPTEC_2940U2: 314 { 315 ahc_t = AHC_AIC7890; 316 ahc_fe = AHC_AIC7890_FE; 317 break; 318 } 319 case PCI_DEVICE_ID_ADAPTEC_AIC7896: 320 { 321 ahc_t = AHC_AIC7896; 322 ahc_fe = AHC_AIC7896_FE; 323 break; 324 } 325 case PCI_DEVICE_ID_ADAPTEC_2944U: 326 case PCI_DEVICE_ID_ADAPTEC_2940U: 327 case PCI_DEVICE_ID_ADAPTEC_AIC7880: 328 ahc_t = AHC_AIC7880; 329 ahc_fe = AHC_AIC7880_FE; 330 break; 331 case PCI_DEVICE_ID_ADAPTEC_2944: 332 case PCI_DEVICE_ID_ADAPTEC_2940: 333 case PCI_DEVICE_ID_ADAPTEC_AIC7870: 334 ahc_t = AHC_AIC7870; 335 ahc_fe = AHC_AIC7870_FE; 336 break; 337 case PCI_DEVICE_ID_ADAPTEC_2940AU: 338 case PCI_DEVICE_ID_ADAPTEC_AIC7860: 339 ahc_fe = AHC_AIC7860_FE; 340 ahc_t = AHC_AIC7860; 341 break; 342 case PCI_DEVICE_ID_ADAPTEC_AIC7895: 343 { 344 u_int32_t devconfig; 345 346 ahc_t = AHC_AIC7895; 347 ahc_fe = AHC_AIC7895_FE; 348 devconfig = pci_conf_read(config_id, DEVCONFIG); 349 devconfig &= ~SCBSIZE32; 350 pci_conf_write(config_id, DEVCONFIG, devconfig); 351 break; 352 } 353 case PCI_DEVICE_ID_ADAPTEC_AIC7855: 354 case PCI_DEVICE_ID_ADAPTEC_AIC7850: 355 ahc_t = AHC_AIC7850; 356 ahc_fe = AHC_AIC7850_FE; 357 break; 358 case PCI_DEVICE_ID_ADAPTEC_AIC7810: 359 printf("RAID functionality unsupported\n"); 360 return; 361 default: 362 break; 363 } 364 365 /* On all PCI adapters, we allow SCB paging */ 366 ahc_f |= AHC_PAGESCBS; 367 if ((ahc = ahc_alloc(unit, io_port, vaddr, ahc_t|AHC_PCI, ahc_fe, ahc_f, 368 shared_scb_data)) == NULL) 369 return; /* XXX PCI code should take return status */ 370 371 ahc->channel = channel; 372 373 /* Allocate a dmatag for our SCB DMA maps */ 374 /* XXX Should be a child of the PCI bus dma tag */ 375 error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/0, 376 /*boundary*/0, 377 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 378 /*highaddr*/BUS_SPACE_MAXADDR, 379 /*filter*/NULL, /*filterarg*/NULL, 380 /*maxsize*/MAXBSIZE, /*nsegments*/AHC_NSEG, 381 /*maxsegsz*/AHC_MAXTRANSFER_SIZE, 382 /*flags*/BUS_DMA_ALLOCNOW, &ahc->dmat); 383 384 if (error != 0) { 385 printf("%s: Could not allocate DMA tag - error %d\n", 386 ahc_name(ahc), error); 387 ahc_free(ahc); 388 return; 389 } 390 391 392 /* Store our PCI bus information for use in our PCI error handler */ 393 ahc->pci_config_id = config_id; 394 395 /* Remeber how the card was setup in case there is no SEEPROM */ 396 ahc_outb(ahc, HCNTRL, ahc->pause); 397 if ((ahc->features & AHC_ULTRA2) != 0) 398 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 399 else 400 our_id = ahc_inb(ahc, SCSIID) & OID; 401 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 402 scsiseq = ahc_inb(ahc, SCSISEQ); 403 404 if (ahc_reset(ahc) != 0) { 405 /* Failed */ 406 ahc_free(ahc); 407 return; 408 } 409 410 /* 411 * Take a look to see if we have external SRAM. 412 * We currently do not attempt to use SRAM that is 413 * shared among multiple controllers. 414 */ 415 if ((ahc->features & AHC_ULTRA2) != 0) { 416 u_int dscommand0; 417 418 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 419 if ((dscommand0 & RAMPS) != 0) { 420 u_int32_t devconfig; 421 422 devconfig = pci_conf_read(config_id, DEVCONFIG); 423 if ((devconfig & MPORTMODE) != 0) { 424 /* Single user mode */ 425 426 /* 427 * XXX Assume 9bit SRAM and enable 428 * parity checking 429 */ 430 devconfig |= EXTSCBPEN; 431 pci_conf_write(config_id, DEVCONFIG, devconfig); 432 433 /* 434 * Set the bank select apropriately. 435 */ 436 if (ahc->channel == 'B') 437 ahc_outb(ahc, SCBBADDR, 1); 438 else 439 ahc_outb(ahc, SCBBADDR, 0); 440 441 /* Select external SCB SRAM */ 442 dscommand0 &= ~INTSCBRAMSEL; 443 ahc_outb(ahc, DSCOMMAND0, dscommand0); 444 445 if (ahc_probe_scbs(ahc) == 0) { 446 /* External ram isn't really there */ 447 dscommand0 |= INTSCBRAMSEL; 448 ahc_outb(ahc, DSCOMMAND0, dscommand0); 449 } else if (bootverbose) 450 printf("%s: External SRAM bank%d\n", 451 ahc_name(ahc), 452 ahc->channel == 'B' ? 1 : 0); 453 } 454 455 } 456 } else if ((ahc->chip & AHC_CHIPID_MASK) >= AHC_AIC7870) { 457 u_int32_t devconfig = pci_conf_read(config_id, DEVCONFIG); 458 if ((devconfig & RAMPSM) != 0 459 && (devconfig & MPORTMODE) != 0) { 460 461 /* XXX Assume 9bit SRAM and enable parity checking */ 462 devconfig |= EXTSCBPEN; 463 464 /* XXX Assume fast SRAM */ 465 devconfig &= ~EXTSCBTIME; 466 467 /* 468 * Set the bank select apropriately. 469 */ 470 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 471 if (ahc->channel == 'B') 472 ahc_outb(ahc, SCBBADDR, 1); 473 else 474 ahc_outb(ahc, SCBBADDR, 0); 475 } 476 477 /* Select external SRAM */ 478 devconfig &= ~SCBRAMSEL; 479 pci_conf_write(config_id, DEVCONFIG, devconfig); 480 481 if (ahc_probe_scbs(ahc) == 0) { 482 /* External ram isn't really there */ 483 devconfig |= SCBRAMSEL; 484 pci_conf_write(config_id, DEVCONFIG, devconfig); 485 } else if (bootverbose) 486 printf("%s: External SRAM bank%d\n", 487 ahc_name(ahc), 488 ahc->channel == 'B' ? 1 : 0); 489 } 490 } 491 492 if (!(pci_map_int(config_id, ahc_intr, (void *)ahc, &cam_imask))) { 493 ahc_free(ahc); 494 return; 495 } 496 /* 497 * Protect ourself from spurrious interrupts during 498 * intialization. 499 */ 500 opri = splcam(); 501 502 /* 503 * Do aic7880/aic7870/aic7860/aic7850 specific initialization 504 */ 505 { 506 u_int8_t sblkctl; 507 char *id_string; 508 509 switch(ahc_t) { 510 case AHC_AIC7896: 511 { 512 u_int dscommand0; 513 514 /* 515 * DPARCKEN doesn't work correctly on 516 * some MBs so don't use it. 517 */ 518 id_string = "aic7896/97 "; 519 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 520 dscommand0 &= ~(USCBSIZE32|DPARCKEN); 521 dscommand0 |= CACHETHEN|MPARCKEN; 522 ahc_outb(ahc, DSCOMMAND0, dscommand0); 523 break; 524 } 525 case AHC_AIC7890: 526 { 527 u_int dscommand0; 528 529 /* 530 * DPARCKEN doesn't work correctly on 531 * some MBs so don't use it. 532 */ 533 id_string = "aic7890/91 "; 534 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 535 dscommand0 &= ~(USCBSIZE32|DPARCKEN); 536 dscommand0 |= CACHETHEN|MPARCKEN; 537 ahc_outb(ahc, DSCOMMAND0, dscommand0); 538 break; 539 } 540 case AHC_AIC7895: 541 id_string = "aic7895 "; 542 break; 543 case AHC_AIC7880: 544 id_string = "aic7880 "; 545 break; 546 case AHC_AIC7870: 547 id_string = "aic7870 "; 548 break; 549 case AHC_AIC7860: 550 id_string = "aic7860 "; 551 break; 552 case AHC_AIC7850: 553 id_string = "aic7850 "; 554 break; 555 default: 556 printf("ahc: Unknown controller type. Ignoring.\n"); 557 ahc_free(ahc); 558 splx(opri); 559 return; 560 } 561 562 /* See if we have an SEEPROM and perform auto-term */ 563 check_extport(ahc, &sxfrctl1); 564 565 /* 566 * Take the LED out of diagnostic mode 567 */ 568 sblkctl = ahc_inb(ahc, SBLKCTL); 569 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 570 571 /* 572 * I don't know where this is set in the SEEPROM or by the 573 * BIOS, so we default to 100% on Ultra or slower controllers 574 * and 75% on ULTRA2 controllers. 575 */ 576 if ((ahc->features & AHC_ULTRA2) != 0) { 577 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75); 578 } else { 579 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 580 } 581 582 if (ahc->flags & AHC_USEDEFAULTS) { 583 /* 584 * PCI Adapter default setup 585 * Should only be used if the adapter does not have 586 * an SEEPROM. 587 */ 588 /* See if someone else set us up already */ 589 if (scsiseq != 0) { 590 printf("%s: Using left over BIOS settings\n", 591 ahc_name(ahc)); 592 ahc->flags &= ~AHC_USEDEFAULTS; 593 } else { 594 /* 595 * Assume only one connector and always turn 596 * on termination. 597 */ 598 our_id = 0x07; 599 sxfrctl1 = STPWEN; 600 } 601 ahc_outb(ahc, SCSICONF, 602 (our_id & 0x07)|ENSPCHK|RESET_SCSI); 603 604 ahc->our_id = our_id; 605 } 606 607 printf("%s: %s", ahc_name(ahc), id_string); 608 } 609 610 /* 611 * Record our termination setting for the 612 * generic initialization routine. 613 */ 614 if ((sxfrctl1 & STPWEN) != 0) 615 ahc->flags |= AHC_TERM_ENB_A; 616 617 if (ahc_init(ahc)) { 618 ahc_free(ahc); 619 splx(opri); 620 return; /* XXX PCI code should take return status */ 621 } 622 623 /* XXX Crude hack - fix sometime */ 624 if (ahc->flags & AHC_SHARED_SRAM) { 625 /* Only set this once we've successfully probed */ 626 if (shared_scb_data == NULL) 627 first_398X = ahc; 628 } 629 630 splx(opri); 631 632 ahc_attach(ahc); 633 } 634 635 /* 636 * Check the external port logic for a serial eeprom 637 * and termination/cable detection contrls. 638 */ 639 static void 640 check_extport(struct ahc_softc *ahc, u_int8_t *sxfrctl1) 641 { 642 struct seeprom_descriptor sd; 643 struct seeprom_config sc; 644 u_int8_t scsi_conf; 645 int have_seeprom; 646 647 sd.sd_tag = ahc->tag; 648 sd.sd_bsh = ahc->bsh; 649 sd.sd_control_offset = SEECTL; 650 sd.sd_status_offset = SEECTL; 651 sd.sd_dataout_offset = SEECTL; 652 653 /* 654 * For some multi-channel devices, the c46 is simply too 655 * small to work. For the other controller types, we can 656 * get our information from either SEEPROM type. Set the 657 * type to start our probe with accordingly. 658 */ 659 if (ahc->flags & AHC_LARGE_SEEPROM) 660 sd.sd_chip = C56_66; 661 else 662 sd.sd_chip = C46; 663 664 sd.sd_MS = SEEMS; 665 sd.sd_RDY = SEERDY; 666 sd.sd_CS = SEECS; 667 sd.sd_CK = SEECK; 668 sd.sd_DO = SEEDO; 669 sd.sd_DI = SEEDI; 670 671 have_seeprom = acquire_seeprom(ahc, &sd); 672 673 if (have_seeprom) { 674 675 if (bootverbose) 676 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 677 678 for (;;) { 679 bus_size_t start_addr; 680 681 start_addr = 32 * (ahc->channel - 'A'); 682 683 have_seeprom = read_seeprom(&sd, (u_int16_t *)&sc, 684 start_addr, sizeof(sc)/2); 685 686 if (have_seeprom) { 687 /* Check checksum */ 688 int i; 689 int maxaddr; 690 u_int16_t *scarray; 691 u_int16_t checksum; 692 693 maxaddr = (sizeof(sc)/2) - 1; 694 checksum = 0; 695 scarray = (u_int16_t *)≻ 696 697 for (i = 0; i < maxaddr; i++) 698 checksum = checksum + scarray[i]; 699 if (checksum == 0 || checksum != sc.checksum) { 700 if (bootverbose && sd.sd_chip == C56_66) 701 printf ("checksum error\n"); 702 have_seeprom = 0; 703 } else { 704 if (bootverbose) 705 printf("done.\n"); 706 break; 707 } 708 } 709 710 if (sd.sd_chip == C56_66) 711 break; 712 sd.sd_chip = C56_66; 713 } 714 } 715 716 if (!have_seeprom) { 717 if (bootverbose) 718 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 719 ahc->flags |= AHC_USEDEFAULTS; 720 } else { 721 /* 722 * Put the data we've collected down into SRAM 723 * where ahc_init will find it. 724 */ 725 int i; 726 int max_targ = sc.max_targets & CFMAXTARG; 727 728 if ((sc.adapter_control & CFULTRAEN) != 0) { 729 /* 730 * Determine if this adapter has a "newstyle" 731 * SEEPROM format. 732 */ 733 for (i = 0; i < max_targ; i++) { 734 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0){ 735 ahc->flags |= AHC_NEWEEPROM_FMT; 736 break; 737 } 738 } 739 } 740 741 for (i = 0; i < max_targ; i++) { 742 u_int scsirate; 743 u_int16_t target_mask; 744 745 target_mask = 0x01 << i; 746 if (sc.device_flags[i] & CFDISC) 747 ahc->discenable |= target_mask; 748 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 749 if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0) 750 ahc->ultraenb |= target_mask; 751 } else if ((sc.adapter_control & CFULTRAEN) != 0) { 752 ahc->ultraenb |= target_mask; 753 } 754 if ((sc.device_flags[i] & CFXFER) == 0x04 755 && (ahc->ultraenb & target_mask) != 0) { 756 /* Treat 10MHz as a non-ultra speed */ 757 sc.device_flags[i] &= ~CFXFER; 758 ahc->ultraenb &= ~target_mask; 759 } 760 if ((ahc->features & AHC_ULTRA2) != 0) { 761 u_int offset; 762 763 if (sc.device_flags[i] & CFSYNCH) 764 offset = MAX_OFFSET_ULTRA2; 765 else 766 offset = 0; 767 ahc_outb(ahc, TARG_OFFSET + i, offset); 768 769 scsirate = (sc.device_flags[i] & CFXFER) 770 | ((ahc->ultraenb & target_mask) 771 ? 0x18 : 0x10); 772 if (sc.device_flags[i] & CFWIDEB) 773 scsirate |= WIDEXFER; 774 } else { 775 scsirate = (sc.device_flags[i] & CFXFER) << 4; 776 if (sc.device_flags[i] & CFSYNCH) 777 scsirate |= SOFS; 778 if (sc.device_flags[i] & CFWIDEB) 779 scsirate |= WIDEXFER; 780 } 781 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 782 } 783 ahc_outb(ahc, DISC_DSB, ~(ahc->discenable & 0xff)); 784 ahc_outb(ahc, DISC_DSB + 1, ~((ahc->discenable >> 8) & 0xff)); 785 ahc_outb(ahc, ULTRA_ENB, ahc->ultraenb & 0xff); 786 ahc_outb(ahc, ULTRA_ENB + 1, (ahc->ultraenb >> 8) & 0xff); 787 788 ahc->our_id = sc.brtime_id & CFSCSIID; 789 790 scsi_conf = (ahc->our_id & 0x7); 791 if (sc.adapter_control & CFSPARITY) 792 scsi_conf |= ENSPCHK; 793 if (sc.adapter_control & CFRESETB) 794 scsi_conf |= RESET_SCSI; 795 796 if (sc.bios_control & CFEXTEND) 797 ahc->flags |= AHC_EXTENDED_TRANS_A; 798 if (ahc->features & AHC_ULTRA 799 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 800 /* Should we enable Ultra mode? */ 801 if (!(sc.adapter_control & CFULTRAEN)) 802 /* Treat us as a non-ultra card */ 803 ahc->ultraenb = 0; 804 } 805 /* Set SCSICONF info */ 806 ahc_outb(ahc, SCSICONF, scsi_conf); 807 } 808 809 if ((ahc->features & AHC_SPIOCAP) != 0) { 810 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0) { 811 configure_termination(ahc, &sc, &sd, sxfrctl1); 812 } 813 } else if (have_seeprom) { 814 configure_termination(ahc, &sc, &sd, sxfrctl1); 815 } 816 817 release_seeprom(&sd); 818 } 819 820 static void 821 configure_termination(struct ahc_softc *ahc, 822 struct seeprom_config *sc, 823 struct seeprom_descriptor *sd, 824 u_int8_t *sxfrctl1) 825 { 826 int max_targ = sc->max_targets & CFMAXTARG; 827 u_int8_t brddat; 828 829 brddat = 0; 830 831 /* 832 * Update the settings in sxfrctl1 to match the 833 *termination settings 834 */ 835 *sxfrctl1 = 0; 836 837 /* 838 * SEECS must be on for the GALS to latch 839 * the data properly. Be sure to leave MS 840 * on or we will release the seeprom. 841 */ 842 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 843 if ((sc->adapter_control & CFAUTOTERM) != 0 844 || (ahc->features & AHC_ULTRA2) != 0) { 845 int internal50_present; 846 int internal68_present; 847 int externalcable_present; 848 int eeprom_present; 849 int enableSEC_low; 850 int enableSEC_high; 851 int enablePRI_low; 852 int enablePRI_high; 853 854 enableSEC_low = 0; 855 enableSEC_high = 0; 856 enablePRI_low = 0; 857 enablePRI_high = 0; 858 if (ahc->features & AHC_ULTRA2) { 859 ahc_ultra2_term_detect(ahc, &enableSEC_low, 860 &enableSEC_high, 861 &enablePRI_low, 862 &enablePRI_high, 863 &eeprom_present); 864 if ((sc->adapter_control & CFSEAUTOTERM) == 0) { 865 enableSEC_low = (sc->adapter_control & CFSTERM); 866 enableSEC_high = 867 (sc->adapter_control & CFWSTERM); 868 } 869 if ((sc->adapter_control & CFAUTOTERM) == 0) { 870 enablePRI_low = enablePRI_high = 871 (sc->adapter_control & CFLVDSTERM); 872 } 873 /* Make the table calculations below happy */ 874 internal50_present = 0; 875 internal68_present = 1; 876 externalcable_present = 1; 877 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 878 aic785X_cable_detect(ahc, &internal50_present, 879 &externalcable_present, 880 &eeprom_present); 881 } else { 882 aic787X_cable_detect(ahc, &internal50_present, 883 &internal68_present, 884 &externalcable_present, 885 &eeprom_present); 886 } 887 888 if (max_targ <= 8) { 889 internal68_present = 0; 890 } 891 892 if (bootverbose) { 893 if ((ahc->features & AHC_ULTRA2) == 0) { 894 printf("%s: internal 50 cable %s present, " 895 "internal 68 cable %s present\n", 896 ahc_name(ahc), 897 internal50_present ? "is":"not", 898 internal68_present ? "is":"not"); 899 900 printf("%s: external cable %s present\n", 901 ahc_name(ahc), 902 externalcable_present ? "is":"not"); 903 } 904 printf("%s: BIOS eeprom %s present\n", 905 ahc_name(ahc), eeprom_present ? "is" : "not"); 906 907 } 908 909 /* 910 * Now set the termination based on what 911 * we found. 912 * Flash Enable = BRDDAT7 913 * Secondary High Term Enable = BRDDAT6 914 * Secondary Low Term Enable = BRDDAT5 (7890) 915 * Primary High Term Enable = BRDDAT4 (7890) 916 */ 917 if ((ahc->features & AHC_ULTRA2) == 0 918 && (internal50_present != 0) 919 && (internal68_present != 0) 920 && (externalcable_present != 0)) { 921 printf("%s: Illegal cable configuration!!. " 922 "Only two connectors on the " 923 "adapter may be used at a " 924 "time!\n", ahc_name(ahc)); 925 } 926 927 if ((max_targ > 8) 928 && ((externalcable_present == 0) 929 || (internal68_present == 0) 930 || (enableSEC_high != 0))) { 931 brddat |= BRDDAT6; 932 if (bootverbose) 933 printf("%s: %sHigh byte termination Enabled\n", 934 ahc_name(ahc), 935 enableSEC_high ? "Secondary " : ""); 936 } 937 938 if (((internal50_present ? 1 : 0) 939 + (internal68_present ? 1 : 0) 940 + (externalcable_present ? 1 : 0)) <= 1 941 || (enableSEC_low != 0)) { 942 if ((ahc->features & AHC_ULTRA2) != 0) 943 brddat |= BRDDAT5; 944 else 945 *sxfrctl1 |= STPWEN; 946 if (bootverbose) 947 printf("%s: %sLow byte termination Enabled\n", 948 ahc_name(ahc), 949 enableSEC_low ? "Secondary " : ""); 950 } 951 952 if (enablePRI_low != 0) { 953 *sxfrctl1 |= STPWEN; 954 if (bootverbose) 955 printf("%s: Primary Low Byte termination " 956 "Enabled\n", ahc_name(ahc)); 957 } 958 959 if (enablePRI_high != 0) { 960 brddat |= BRDDAT4; 961 if (bootverbose) 962 printf("%s: Primary High Byte " 963 "termination Enabled\n", 964 ahc_name(ahc)); 965 } 966 967 write_brdctl(ahc, brddat); 968 969 } else { 970 if (sc->adapter_control & CFSTERM) { 971 if ((ahc->features & AHC_ULTRA2) != 0) 972 brddat |= BRDDAT5; 973 else 974 *sxfrctl1 |= STPWEN; 975 976 if (bootverbose) 977 printf("%s: %sLow byte termination Enabled\n", 978 ahc_name(ahc), 979 (ahc->features & AHC_ULTRA2) ? "Primary " 980 : ""); 981 } 982 983 if (sc->adapter_control & CFWSTERM) { 984 brddat |= BRDDAT6; 985 if (bootverbose) 986 printf("%s: %sHigh byte termination Enabled\n", 987 ahc_name(ahc), 988 (ahc->features & AHC_ULTRA2) 989 ? "Secondary " : ""); 990 } 991 992 write_brdctl(ahc, brddat); 993 } 994 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 995 } 996 997 static void 998 ahc_ultra2_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 999 int *enableSEC_high, int *enablePRI_low, 1000 int *enablePRI_high, int *eeprom_present) 1001 { 1002 u_int8_t brdctl; 1003 1004 /* 1005 * BRDDAT7 = Eeprom 1006 * BRDDAT6 = Enable Secondary High Byte termination 1007 * BRDDAT5 = Enable Secondary Low Byte termination 1008 * BRDDAT4 = Enable Primary low byte termination 1009 * BRDDAT3 = Enable Primary high byte termination 1010 */ 1011 brdctl = read_brdctl(ahc); 1012 1013 *eeprom_present = brdctl & BRDDAT7; 1014 *enableSEC_high = (brdctl & BRDDAT6); 1015 *enableSEC_low = (brdctl & BRDDAT5); 1016 *enablePRI_low = (brdctl & BRDDAT4); 1017 *enablePRI_high = (brdctl & BRDDAT3); 1018 } 1019 1020 static void 1021 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1022 int *internal68_present, int *externalcable_present, 1023 int *eeprom_present) 1024 { 1025 u_int8_t brdctl; 1026 1027 /* 1028 * First read the status of our cables. 1029 * Set the rom bank to 0 since the 1030 * bank setting serves as a multiplexor 1031 * for the cable detection logic. 1032 * BRDDAT5 controls the bank switch. 1033 */ 1034 write_brdctl(ahc, 0); 1035 1036 /* 1037 * Now read the state of the internal 1038 * connectors. BRDDAT6 is INT50 and 1039 * BRDDAT7 is INT68. 1040 */ 1041 brdctl = read_brdctl(ahc); 1042 *internal50_present = !(brdctl & BRDDAT6); 1043 *internal68_present = !(brdctl & BRDDAT7); 1044 1045 /* 1046 * Set the rom bank to 1 and determine 1047 * the other signals. 1048 */ 1049 write_brdctl(ahc, BRDDAT5); 1050 1051 /* 1052 * Now read the state of the external 1053 * connectors. BRDDAT6 is EXT68 and 1054 * BRDDAT7 is EPROMPS. 1055 */ 1056 brdctl = read_brdctl(ahc); 1057 *externalcable_present = !(brdctl & BRDDAT6); 1058 *eeprom_present = brdctl & BRDDAT7; 1059 } 1060 1061 static void 1062 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1063 int *externalcable_present, int *eeprom_present) 1064 { 1065 u_int8_t brdctl; 1066 1067 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1068 ahc_outb(ahc, BRDCTL, 0); 1069 brdctl = ahc_inb(ahc, BRDCTL); 1070 *internal50_present = !(brdctl & BRDDAT5); 1071 *externalcable_present = !(brdctl & BRDDAT6); 1072 1073 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) != 0; 1074 } 1075 1076 static int 1077 acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1078 { 1079 int wait; 1080 1081 if ((ahc->features & AHC_SPIOCAP) != 0 1082 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1083 return (0); 1084 1085 /* 1086 * Request access of the memory port. When access is 1087 * granted, SEERDY will go high. We use a 1 second 1088 * timeout which should be near 1 second more than 1089 * is needed. Reason: after the chip reset, there 1090 * should be no contention. 1091 */ 1092 SEEPROM_OUTB(sd, sd->sd_MS); 1093 wait = 1000; /* 1 second timeout in msec */ 1094 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1095 DELAY(1000); /* delay 1 msec */ 1096 } 1097 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1098 SEEPROM_OUTB(sd, 0); 1099 return (0); 1100 } 1101 return(1); 1102 } 1103 1104 static void 1105 release_seeprom(sd) 1106 struct seeprom_descriptor *sd; 1107 { 1108 /* Release access to the memory port and the serial EEPROM. */ 1109 SEEPROM_OUTB(sd, 0); 1110 } 1111 1112 static void 1113 write_brdctl(ahc, value) 1114 struct ahc_softc *ahc; 1115 u_int8_t value; 1116 { 1117 u_int8_t brdctl; 1118 1119 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1120 brdctl = BRDSTB; 1121 if (ahc->channel == 'B') 1122 brdctl |= BRDCS; 1123 } else if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7890) { 1124 brdctl = 0; 1125 } else { 1126 brdctl = BRDSTB|BRDCS; 1127 } 1128 ahc_outb(ahc, BRDCTL, brdctl); 1129 brdctl |= value; 1130 ahc_outb(ahc, BRDCTL, brdctl); 1131 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7890) 1132 brdctl |= BRDSTB_ULTRA2; 1133 else 1134 brdctl &= ~BRDSTB; 1135 ahc_outb(ahc, BRDCTL, brdctl); 1136 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7890) 1137 brdctl = 0; 1138 else 1139 brdctl &= ~BRDCS; 1140 ahc_outb(ahc, BRDCTL, brdctl); 1141 } 1142 1143 static u_int8_t 1144 read_brdctl(ahc) 1145 struct ahc_softc *ahc; 1146 { 1147 u_int8_t brdctl; 1148 u_int8_t value; 1149 1150 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1151 brdctl = BRDRW; 1152 if (ahc->channel == 'B') 1153 brdctl |= BRDCS; 1154 } else if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7890) { 1155 brdctl = BRDRW_ULTRA2; 1156 } else { 1157 brdctl = BRDRW|BRDCS; 1158 } 1159 ahc_outb(ahc, BRDCTL, brdctl); 1160 value = ahc_inb(ahc, BRDCTL); 1161 ahc_outb(ahc, BRDCTL, 0); 1162 return (value); 1163 } 1164 1165 #define DPE 0x80 1166 #define SSE 0x40 1167 #define RMA 0x20 1168 #define RTA 0x10 1169 #define STA 0x08 1170 #define DPR 0x01 1171 1172 void 1173 ahc_pci_intr(struct ahc_softc *ahc) 1174 { 1175 u_int8_t status1; 1176 1177 status1 = pci_cfgread(ahc->pci_config_id, PCIR_STATUS + 1, /*bytes*/1); 1178 1179 if (status1 & DPE) { 1180 printf("%s: Data Parity Error Detected during address " 1181 "or write data phase\n", ahc_name(ahc)); 1182 } 1183 if (status1 & SSE) { 1184 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1185 } 1186 if (status1 & RMA) { 1187 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1188 } 1189 if (status1 & RTA) { 1190 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1191 } 1192 if (status1 & STA) { 1193 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1194 } 1195 if (status1 & DPR) { 1196 printf("%s: Data Parity Error has been reported via PERR#\n", 1197 ahc_name(ahc)); 1198 } 1199 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1200 printf("%s: Latched PCIERR interrupt with " 1201 "no status bits set\n", ahc_name(ahc)); 1202 } 1203 pci_cfgwrite(ahc->pci_config_id, PCIR_STATUS + 1, status1, /*bytes*/1); 1204 1205 if (status1 & (DPR|RMA|RTA)) { 1206 ahc_outb(ahc, CLRINT, CLRPARERR); 1207 } 1208 } 1209 1210 #endif /* NPCI > 0 */ 1211