1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2020 Alstom Group 5 * Copyright (c) 2020 Semihalf 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* AHCI controller driver for NXP QorIQ Layerscape SoCs. */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/stdint.h> 35 #include <sys/stddef.h> 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/bus.h> 40 #include <sys/module.h> 41 #include <sys/sysctl.h> 42 #include <sys/rman.h> 43 #include <sys/unistd.h> 44 45 #include <machine/bus.h> 46 #include <machine/resource.h> 47 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 51 #include <dev/ahci/ahci.h> 52 53 #include <dev/extres/clk/clk.h> 54 55 #define AHCI_FSL_REG_PHY1 0xa8 56 #define AHCI_FSL_REG_PHY2 0xac 57 #define AHCI_FSL_REG_PHY3 0xb0 58 #define AHCI_FSL_REG_PHY4 0xb4 59 #define AHCI_FSL_REG_PHY5 0xb8 60 #define AHCI_FSL_REG_PTC 0xc8 61 62 #define AHCI_FSL_REG_PHY1_TTA_MASK 0x0001ffff 63 #define AHCI_FSL_REG_PHY1_SNM (1 << 17) 64 #define AHCI_FSL_REG_PHY1_SNR (1 << 18) 65 #define AHCI_FSL_REG_PHY1_FPR (1 << 20) 66 #define AHCI_FSL_REG_PHY1_PBPS_LBP 0 67 #define AHCI_FSL_REG_PHY1_PBPS_LFTP (0x01 << 21) 68 #define AHCI_FSL_REG_PHY1_PBPS_MFTP (0x02 << 21) 69 #define AHCI_FSL_REG_PHY1_PBPS_HFTP (0x03 << 21) 70 #define AHCI_FSL_REG_PHY1_PBPS_PRBS (0x04 << 21) 71 #define AHCI_FSL_REG_PHY1_PBPS_BIST (0x05 << 21) 72 #define AHCI_FSL_REG_PHY1_PBPE (1 << 24) 73 #define AHCI_FSL_REG_PHY1_PBCE (1 << 25) 74 #define AHCI_FSL_REG_PHY1_PBPNA (1 << 26) 75 #define AHCI_FSL_REG_PHY1_STB (1 << 27) 76 #define AHCI_FSL_REG_PHY1_PSSO (1 << 28) 77 #define AHCI_FSL_REG_PHY1_PSS (1 << 29) 78 #define AHCI_FSL_REG_PHY1_ERSN (1 << 30) 79 #define AHCI_FSL_REG_PHY1_ESDF (1 << 31) 80 81 #define AHCI_FSL_REG_PHY_MASK 0xff 82 83 #define AHCI_FSL_PHY2_CIBGMN_SHIFT 0 84 #define AHCI_FSL_PHY2_CIBGMX_SHIFT 8 85 #define AHCI_FSL_PHY2_CIBGN_SHIFT 16 86 #define AHCI_FSL_PHY2_CINMP_SHIFT 24 87 88 #define AHCI_FSL_PHY3_CWBGMN_SHIFT 0 89 #define AHCI_FSL_PHY3_CWBGMX_SHIFT 8 90 #define AHCI_FSL_PHY3_CWBGN_SHIFT 16 91 #define AHCI_FSL_PHY3_CWNMP_SHIFT 24 92 93 #define AHCI_FSL_REG_PTC_RXWM_MASK 0x0000007f 94 #define AHCI_FSL_REG_PTC_ENBD (1 << 8) 95 #define AHCI_FSL_REG_PTC_ITM (1 << 9) 96 97 #define AHCI_FSL_REG_PHY1_CFG ((0x1fffe & AHCI_FSL_REG_PHY1_TTA_MASK) \ 98 | AHCI_FSL_REG_PHY1_SNM | AHCI_FSL_REG_PHY1_PSS \ 99 | AHCI_FSL_REG_PHY1_ESDF) 100 #define AHCI_FSL_REG_PHY2_CFG ((0x1f << AHCI_FSL_PHY2_CIBGMN_SHIFT) \ 101 | (0x4d << AHCI_FSL_PHY2_CIBGMX_SHIFT) \ 102 | (0x18 << AHCI_FSL_PHY2_CIBGN_SHIFT) \ 103 | (0x28 << AHCI_FSL_PHY2_CINMP_SHIFT)) 104 #define AHCI_FSL_REG_PHY3_CFG ((0x09 << AHCI_FSL_PHY3_CWBGMN_SHIFT) \ 105 | (0x15 << AHCI_FSL_PHY3_CWBGMX_SHIFT) \ 106 | (0x08 << AHCI_FSL_PHY3_CWBGN_SHIFT) \ 107 | (0x0e << AHCI_FSL_PHY3_CWNMP_SHIFT)) 108 /* Bit 27 enabled so value of reserved bits remains as in documentation. */ 109 #define AHCI_FSL_REG_PTC_CFG ((0x29 & AHCI_FSL_REG_PTC_RXWM_MASK) \ 110 | (1 << 27)) 111 112 #define AHCI_FSL_REG_ECC 0x0 113 #define AHCI_FSL_REG_ECC_DIS 0x80000000 114 115 struct ahci_fsl_fdt_soc_data; 116 117 struct ahci_fsl_fdt_controller { 118 struct ahci_controller ctlr; /* Must be the first field. */ 119 const struct ahci_fsl_fdt_soc_data *soc_data; 120 struct resource *r_ecc; 121 int r_ecc_rid; 122 }; 123 124 static void 125 ahci_fsl_fdt_ls1046a_phy_init(struct ahci_fsl_fdt_controller *ctlr) 126 { 127 struct ahci_controller *ahci; 128 uint32_t val; 129 130 ahci = &ctlr->ctlr; 131 if (ctlr->r_ecc) { 132 val = ATA_INL(ctlr->r_ecc, AHCI_FSL_REG_ECC) | 133 AHCI_FSL_REG_ECC_DIS; 134 ATA_OUTL(ctlr->r_ecc, AHCI_FSL_REG_ECC, val); 135 } 136 ATA_OUTL(ahci->r_mem, AHCI_FSL_REG_PHY1, AHCI_FSL_REG_PHY1_CFG); 137 ATA_OUTL(ahci->r_mem, AHCI_FSL_REG_PHY2, AHCI_FSL_REG_PHY2_CFG); 138 ATA_OUTL(ahci->r_mem, AHCI_FSL_REG_PHY3, AHCI_FSL_REG_PHY3_CFG); 139 ATA_OUTL(ahci->r_mem, AHCI_FSL_REG_PTC, AHCI_FSL_REG_PTC_CFG); 140 } 141 142 struct ahci_fsl_fdt_soc_data { 143 void (* phy_init)(struct ahci_fsl_fdt_controller *ctlr); 144 }; 145 146 static const struct ahci_fsl_fdt_soc_data ahci_fsl_fdt_ls1046a_soc_data = { 147 .phy_init = ahci_fsl_fdt_ls1046a_phy_init, 148 }; 149 150 static const struct ofw_compat_data ahci_fsl_fdt_compat_data[] = { 151 {"fsl,ls1046a-ahci", (uintptr_t)&ahci_fsl_fdt_ls1046a_soc_data}, 152 {NULL, 0} 153 }; 154 155 static int 156 ahci_fsl_fdt_probe(device_t dev) 157 { 158 if (!ofw_bus_status_okay(dev)) 159 return (ENXIO); 160 161 if (!ofw_bus_search_compatible(dev, ahci_fsl_fdt_compat_data)->ocd_data) 162 return (ENXIO); 163 164 device_set_desc(dev, "NXP QorIQ Layerscape AHCI controller"); 165 return (BUS_PROBE_DEFAULT); 166 } 167 168 static int 169 ahci_fsl_fdt_attach(device_t dev) 170 { 171 struct ahci_fsl_fdt_controller *ctlr; 172 struct ahci_controller *ahci; 173 uintptr_t ocd_data; 174 phandle_t node; 175 clk_t clock; 176 int ret; 177 178 node = ofw_bus_get_node(dev); 179 ctlr = device_get_softc(dev); 180 ocd_data = ofw_bus_search_compatible(dev, 181 ahci_fsl_fdt_compat_data)->ocd_data; 182 ctlr->soc_data = (struct ahci_fsl_fdt_soc_data *)ocd_data; 183 ahci = &ctlr->ctlr; 184 ahci->dev = dev; 185 ahci->r_rid = 0; 186 ahci->quirks = AHCI_Q_NOPMP; 187 188 ret = clk_get_by_ofw_index(dev, node, 0, &clock); 189 if (ret != 0) { 190 device_printf(dev, "No clock found.\n"); 191 return (ENXIO); 192 } 193 194 ret = clk_enable(clock); 195 if (ret !=0) { 196 device_printf(dev, "Could not enable clock.\n"); 197 return (ENXIO); 198 } 199 200 if (OF_hasprop(node, "reg-names") && ofw_bus_find_string_index(node, 201 "reg-names", "ahci", &ahci->r_rid)) { 202 device_printf(dev, 203 "Could not locate \"ahci\" string in the \"reg-names\" property"); 204 return (ENOENT); 205 } 206 207 ahci->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 208 &ahci->r_rid, RF_ACTIVE); 209 if (!ahci->r_mem) { 210 device_printf(dev, 211 "Could not allocate resources for controller\n"); 212 return (ENOMEM); 213 } 214 215 if (!ofw_bus_find_string_index(node, "reg-names", "sata-ecc", 216 &ctlr->r_ecc_rid)) { 217 ctlr->r_ecc = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 218 &ctlr->r_ecc_rid, RF_ACTIVE); 219 if (!ctlr->r_ecc) { 220 device_printf(dev, 221 "Could not allocate resources for controller\n"); 222 ret = ENOMEM; 223 goto err_free_mem; 224 } 225 } 226 227 /* Setup controller defaults. */ 228 ahci->numirqs = 1; 229 ctlr->soc_data->phy_init(ctlr); 230 231 /* Reset controller. */ 232 ret = ahci_ctlr_reset(dev); 233 if (ret) 234 goto err_free_mem; 235 236 ret = ahci_attach(dev); 237 if (ret) { 238 device_printf(dev, 239 "Could not initialize AHCI, with error: %d\n", ret); 240 goto err_free_ecc; 241 } 242 return (0); 243 244 err_free_mem: 245 bus_free_resource(dev, SYS_RES_MEMORY, ahci->r_mem); 246 err_free_ecc: 247 if (ctlr->r_ecc) 248 bus_free_resource(dev, SYS_RES_MEMORY, ctlr->r_ecc); 249 return (ret); 250 } 251 252 static int 253 ahci_fsl_fdt_detach(device_t dev) 254 { 255 struct ahci_fsl_fdt_controller *ctlr; 256 257 ctlr = device_get_softc(dev); 258 if (ctlr->r_ecc) 259 bus_free_resource(dev, SYS_RES_MEMORY, ctlr->r_ecc); 260 return ahci_detach(dev); 261 } 262 263 static const device_method_t ahci_fsl_fdt_methods[] = { 264 DEVMETHOD(device_probe, ahci_fsl_fdt_probe), 265 DEVMETHOD(device_attach, ahci_fsl_fdt_attach), 266 DEVMETHOD(device_detach, ahci_fsl_fdt_detach), 267 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 268 DEVMETHOD(bus_release_resource, ahci_release_resource), 269 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 270 DEVMETHOD(bus_teardown_intr, ahci_teardown_intr), 271 DEVMETHOD(bus_print_child, ahci_print_child), 272 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 273 DEVMETHOD(bus_get_dma_tag, ahci_get_dma_tag), 274 DEVMETHOD_END 275 }; 276 277 static driver_t ahci_fsl_fdt_driver = { 278 "ahci", 279 ahci_fsl_fdt_methods, 280 sizeof(struct ahci_fsl_fdt_controller), 281 }; 282 283 static devclass_t ahci_fsl_fdt_devclass; 284 DRIVER_MODULE(ahci_fsl, simplebus, ahci_fsl_fdt_driver, ahci_fsl_fdt_devclass, 285 NULL, NULL); 286 DRIVER_MODULE(ahci_fsl, ofwbus, ahci_fsl_fdt_driver, ahci_fsl_fdt_devclass, 287 NULL, NULL); 288