xref: /freebsd/sys/dev/ahci/ahci.h (revision c93b6e5fa24ba172ab271432c6692f9cc604e15a)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5  * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org>
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer,
13  *    without modification, immediately at the beginning of the file.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28  *
29  * $FreeBSD$
30  */
31 
32 /* ATA register defines */
33 #define ATA_DATA                        0       /* (RW) data */
34 
35 #define ATA_FEATURE                     1       /* (W) feature */
36 #define         ATA_F_DMA               0x01    /* enable DMA */
37 #define         ATA_F_OVL               0x02    /* enable overlap */
38 
39 #define ATA_COUNT                       2       /* (W) sector count */
40 
41 #define ATA_SECTOR                      3       /* (RW) sector # */
42 #define ATA_CYL_LSB                     4       /* (RW) cylinder# LSB */
43 #define ATA_CYL_MSB                     5       /* (RW) cylinder# MSB */
44 #define ATA_DRIVE                       6       /* (W) Sector/Drive/Head */
45 #define         ATA_D_LBA               0x40    /* use LBA addressing */
46 #define         ATA_D_IBM               0xa0    /* 512 byte sectors, ECC */
47 
48 #define ATA_COMMAND                     7       /* (W) command */
49 
50 #define ATA_ERROR                       8       /* (R) error */
51 #define         ATA_E_ILI               0x01    /* illegal length */
52 #define         ATA_E_NM                0x02    /* no media */
53 #define         ATA_E_ABORT             0x04    /* command aborted */
54 #define         ATA_E_MCR               0x08    /* media change request */
55 #define         ATA_E_IDNF              0x10    /* ID not found */
56 #define         ATA_E_MC                0x20    /* media changed */
57 #define         ATA_E_UNC               0x40    /* uncorrectable data */
58 #define         ATA_E_ICRC              0x80    /* UDMA crc error */
59 #define		ATA_E_ATAPI_SENSE_MASK	0xf0	/* ATAPI sense key mask */
60 
61 #define ATA_IREASON                     9       /* (R) interrupt reason */
62 #define         ATA_I_CMD               0x01    /* cmd (1) | data (0) */
63 #define         ATA_I_IN                0x02    /* read (1) | write (0) */
64 #define         ATA_I_RELEASE           0x04    /* released bus (1) */
65 #define         ATA_I_TAGMASK           0xf8    /* tag mask */
66 
67 #define ATA_STATUS                      10      /* (R) status */
68 #define ATA_ALTSTAT                     11      /* (R) alternate status */
69 #define         ATA_S_ERROR             0x01    /* error */
70 #define         ATA_S_INDEX             0x02    /* index */
71 #define         ATA_S_CORR              0x04    /* data corrected */
72 #define         ATA_S_DRQ               0x08    /* data request */
73 #define         ATA_S_DSC               0x10    /* drive seek completed */
74 #define         ATA_S_SERVICE           0x10    /* drive needs service */
75 #define         ATA_S_DWF               0x20    /* drive write fault */
76 #define         ATA_S_DMA               0x20    /* DMA ready */
77 #define         ATA_S_READY             0x40    /* drive ready */
78 #define         ATA_S_BUSY              0x80    /* busy */
79 
80 #define ATA_CONTROL                     12      /* (W) control */
81 #define         ATA_A_IDS               0x02    /* disable interrupts */
82 #define         ATA_A_RESET             0x04    /* RESET controller */
83 #define         ATA_A_4BIT              0x08    /* 4 head bits */
84 #define         ATA_A_HOB               0x80    /* High Order Byte enable */
85 
86 /* SATA register defines */
87 #define ATA_SSTATUS                     13
88 #define         ATA_SS_DET_MASK         0x0000000f
89 #define         ATA_SS_DET_NO_DEVICE    0x00000000
90 #define         ATA_SS_DET_DEV_PRESENT  0x00000001
91 #define         ATA_SS_DET_PHY_ONLINE   0x00000003
92 #define         ATA_SS_DET_PHY_OFFLINE  0x00000004
93 
94 #define         ATA_SS_SPD_MASK         0x000000f0
95 #define         ATA_SS_SPD_NO_SPEED     0x00000000
96 #define         ATA_SS_SPD_GEN1         0x00000010
97 #define         ATA_SS_SPD_GEN2         0x00000020
98 #define         ATA_SS_SPD_GEN3         0x00000030
99 
100 #define         ATA_SS_IPM_MASK         0x00000f00
101 #define         ATA_SS_IPM_NO_DEVICE    0x00000000
102 #define         ATA_SS_IPM_ACTIVE       0x00000100
103 #define         ATA_SS_IPM_PARTIAL      0x00000200
104 #define         ATA_SS_IPM_SLUMBER      0x00000600
105 #define         ATA_SS_IPM_DEVSLEEP     0x00000800
106 
107 #define ATA_SERROR                      14
108 #define         ATA_SE_DATA_CORRECTED   0x00000001
109 #define         ATA_SE_COMM_CORRECTED   0x00000002
110 #define         ATA_SE_DATA_ERR         0x00000100
111 #define         ATA_SE_COMM_ERR         0x00000200
112 #define         ATA_SE_PROT_ERR         0x00000400
113 #define         ATA_SE_HOST_ERR         0x00000800
114 #define         ATA_SE_PHY_CHANGED      0x00010000
115 #define         ATA_SE_PHY_IERROR       0x00020000
116 #define         ATA_SE_COMM_WAKE        0x00040000
117 #define         ATA_SE_DECODE_ERR       0x00080000
118 #define         ATA_SE_PARITY_ERR       0x00100000
119 #define         ATA_SE_CRC_ERR          0x00200000
120 #define         ATA_SE_HANDSHAKE_ERR    0x00400000
121 #define         ATA_SE_LINKSEQ_ERR      0x00800000
122 #define         ATA_SE_TRANSPORT_ERR    0x01000000
123 #define         ATA_SE_UNKNOWN_FIS      0x02000000
124 #define         ATA_SE_EXCHANGED        0x04000000
125 
126 #define ATA_SCONTROL                    15
127 #define         ATA_SC_DET_MASK         0x0000000f
128 #define         ATA_SC_DET_IDLE         0x00000000
129 #define         ATA_SC_DET_RESET        0x00000001
130 #define         ATA_SC_DET_DISABLE      0x00000004
131 
132 #define         ATA_SC_SPD_MASK         0x000000f0
133 #define         ATA_SC_SPD_NO_SPEED     0x00000000
134 #define         ATA_SC_SPD_SPEED_GEN1   0x00000010
135 #define         ATA_SC_SPD_SPEED_GEN2   0x00000020
136 #define         ATA_SC_SPD_SPEED_GEN3   0x00000030
137 
138 #define         ATA_SC_IPM_MASK         0x00000f00
139 #define         ATA_SC_IPM_NONE         0x00000000
140 #define         ATA_SC_IPM_DIS_PARTIAL  0x00000100
141 #define         ATA_SC_IPM_DIS_SLUMBER  0x00000200
142 #define         ATA_SC_IPM_DIS_DEVSLEEP 0x00000400
143 
144 #define ATA_SACTIVE                     16
145 
146 #define AHCI_MAX_PORTS			32
147 #define AHCI_MAX_SLOTS			32
148 #define AHCI_MAX_IRQS			16
149 
150 /* SATA AHCI v1.0 register defines */
151 #define AHCI_CAP                    0x00
152 #define		AHCI_CAP_NPMASK	0x0000001f
153 #define		AHCI_CAP_SXS	0x00000020
154 #define		AHCI_CAP_EMS	0x00000040
155 #define		AHCI_CAP_CCCS	0x00000080
156 #define		AHCI_CAP_NCS	0x00001F00
157 #define		AHCI_CAP_NCS_SHIFT	8
158 #define		AHCI_CAP_PSC	0x00002000
159 #define		AHCI_CAP_SSC	0x00004000
160 #define		AHCI_CAP_PMD	0x00008000
161 #define		AHCI_CAP_FBSS	0x00010000
162 #define		AHCI_CAP_SPM	0x00020000
163 #define		AHCI_CAP_SAM	0x00080000
164 #define		AHCI_CAP_ISS	0x00F00000
165 #define		AHCI_CAP_ISS_SHIFT	20
166 #define		AHCI_CAP_SCLO	0x01000000
167 #define		AHCI_CAP_SAL	0x02000000
168 #define		AHCI_CAP_SALP	0x04000000
169 #define		AHCI_CAP_SSS	0x08000000
170 #define		AHCI_CAP_SMPS	0x10000000
171 #define		AHCI_CAP_SSNTF	0x20000000
172 #define		AHCI_CAP_SNCQ	0x40000000
173 #define		AHCI_CAP_64BIT	0x80000000
174 
175 #define AHCI_GHC                    0x04
176 #define         AHCI_GHC_AE         0x80000000
177 #define         AHCI_GHC_MRSM       0x00000004
178 #define         AHCI_GHC_IE         0x00000002
179 #define         AHCI_GHC_HR         0x00000001
180 
181 #define AHCI_IS                     0x08
182 #define AHCI_PI                     0x0c
183 #define AHCI_VS                     0x10
184 
185 #define AHCI_CCCC                   0x14
186 #define		AHCI_CCCC_TV_MASK	0xffff0000
187 #define		AHCI_CCCC_TV_SHIFT	16
188 #define		AHCI_CCCC_CC_MASK	0x0000ff00
189 #define		AHCI_CCCC_CC_SHIFT	8
190 #define		AHCI_CCCC_INT_MASK	0x000000f8
191 #define		AHCI_CCCC_INT_SHIFT	3
192 #define		AHCI_CCCC_EN		0x00000001
193 #define AHCI_CCCP                   0x18
194 
195 #define AHCI_EM_LOC                 0x1C
196 #define AHCI_EM_CTL                 0x20
197 #define 	AHCI_EM_MR              0x00000001
198 #define 	AHCI_EM_TM              0x00000100
199 #define 	AHCI_EM_RST             0x00000200
200 #define 	AHCI_EM_LED             0x00010000
201 #define 	AHCI_EM_SAFTE           0x00020000
202 #define 	AHCI_EM_SES2            0x00040000
203 #define 	AHCI_EM_SGPIO           0x00080000
204 #define 	AHCI_EM_SMB             0x01000000
205 #define 	AHCI_EM_XMT             0x02000000
206 #define 	AHCI_EM_ALHD            0x04000000
207 #define 	AHCI_EM_PM              0x08000000
208 
209 #define AHCI_CAP2                   0x24
210 #define		AHCI_CAP2_BOH	0x00000001
211 #define		AHCI_CAP2_NVMP	0x00000002
212 #define		AHCI_CAP2_APST	0x00000004
213 #define		AHCI_CAP2_SDS	0x00000008
214 #define		AHCI_CAP2_SADM	0x00000010
215 #define		AHCI_CAP2_DESO	0x00000020
216 
217 #define AHCI_OFFSET                 0x100
218 #define AHCI_STEP                   0x80
219 
220 #define AHCI_P_CLB                  0x00
221 #define AHCI_P_CLBU                 0x04
222 #define AHCI_P_FB                   0x08
223 #define AHCI_P_FBU                  0x0c
224 #define AHCI_P_IS                   0x10
225 #define AHCI_P_IE                   0x14
226 #define         AHCI_P_IX_DHR       0x00000001
227 #define         AHCI_P_IX_PS        0x00000002
228 #define         AHCI_P_IX_DS        0x00000004
229 #define         AHCI_P_IX_SDB       0x00000008
230 #define         AHCI_P_IX_UF        0x00000010
231 #define         AHCI_P_IX_DP        0x00000020
232 #define         AHCI_P_IX_PC        0x00000040
233 #define         AHCI_P_IX_MP        0x00000080
234 
235 #define         AHCI_P_IX_PRC       0x00400000
236 #define         AHCI_P_IX_IPM       0x00800000
237 #define         AHCI_P_IX_OF        0x01000000
238 #define         AHCI_P_IX_INF       0x04000000
239 #define         AHCI_P_IX_IF        0x08000000
240 #define         AHCI_P_IX_HBD       0x10000000
241 #define         AHCI_P_IX_HBF       0x20000000
242 #define         AHCI_P_IX_TFE       0x40000000
243 #define         AHCI_P_IX_CPD       0x80000000
244 
245 #define AHCI_P_CMD                  0x18
246 #define         AHCI_P_CMD_ST       0x00000001
247 #define         AHCI_P_CMD_SUD      0x00000002
248 #define         AHCI_P_CMD_POD      0x00000004
249 #define         AHCI_P_CMD_CLO      0x00000008
250 #define         AHCI_P_CMD_FRE      0x00000010
251 #define         AHCI_P_CMD_CCS_MASK 0x00001f00
252 #define         AHCI_P_CMD_CCS_SHIFT 8
253 #define         AHCI_P_CMD_ISS      0x00002000
254 #define         AHCI_P_CMD_FR       0x00004000
255 #define         AHCI_P_CMD_CR       0x00008000
256 #define         AHCI_P_CMD_CPS      0x00010000
257 #define         AHCI_P_CMD_PMA      0x00020000
258 #define         AHCI_P_CMD_HPCP     0x00040000
259 #define         AHCI_P_CMD_MPSP     0x00080000
260 #define         AHCI_P_CMD_CPD      0x00100000
261 #define         AHCI_P_CMD_ESP      0x00200000
262 #define         AHCI_P_CMD_FBSCP    0x00400000
263 #define         AHCI_P_CMD_APSTE    0x00800000
264 #define         AHCI_P_CMD_ATAPI    0x01000000
265 #define         AHCI_P_CMD_DLAE     0x02000000
266 #define         AHCI_P_CMD_ALPE     0x04000000
267 #define         AHCI_P_CMD_ASP      0x08000000
268 #define         AHCI_P_CMD_ICC_MASK 0xf0000000
269 #define         AHCI_P_CMD_NOOP     0x00000000
270 #define         AHCI_P_CMD_ACTIVE   0x10000000
271 #define         AHCI_P_CMD_PARTIAL  0x20000000
272 #define         AHCI_P_CMD_SLUMBER  0x60000000
273 #define         AHCI_P_CMD_DEVSLEEP 0x80000000
274 
275 #define AHCI_P_TFD                  0x20
276 #define AHCI_P_SIG                  0x24
277 #define AHCI_P_SSTS                 0x28
278 #define AHCI_P_SCTL                 0x2c
279 #define AHCI_P_SERR                 0x30
280 #define AHCI_P_SACT                 0x34
281 #define AHCI_P_CI                   0x38
282 #define AHCI_P_SNTF                 0x3C
283 #define AHCI_P_FBS                  0x40
284 #define 	AHCI_P_FBS_EN       0x00000001
285 #define 	AHCI_P_FBS_DEC      0x00000002
286 #define 	AHCI_P_FBS_SDE      0x00000004
287 #define 	AHCI_P_FBS_DEV      0x00000f00
288 #define 	AHCI_P_FBS_DEV_SHIFT 8
289 #define 	AHCI_P_FBS_ADO      0x0000f000
290 #define 	AHCI_P_FBS_ADO_SHIFT 12
291 #define 	AHCI_P_FBS_DWE      0x000f0000
292 #define 	AHCI_P_FBS_DWE_SHIFT 16
293 #define AHCI_P_DEVSLP               0x44
294 #define 	AHCI_P_DEVSLP_ADSE  0x00000001
295 #define 	AHCI_P_DEVSLP_DSP   0x00000002
296 #define 	AHCI_P_DEVSLP_DETO  0x000003fc
297 #define 	AHCI_P_DEVSLP_DETO_SHIFT 2
298 #define 	AHCI_P_DEVSLP_MDAT  0x00007c00
299 #define 	AHCI_P_DEVSLP_MDAT_SHIFT 10
300 #define 	AHCI_P_DEVSLP_DITO  0x01ff8000
301 #define 	AHCI_P_DEVSLP_DITO_SHIFT 15
302 #define 	AHCI_P_DEVSLP_DM    0x0e000000
303 #define 	AHCI_P_DEVSLP_DM_SHIFT 25
304 
305 /* Just to be sure, if building as module. */
306 #if MAXPHYS < 512 * 1024
307 #undef MAXPHYS
308 #define MAXPHYS				512 * 1024
309 #endif
310 /* Pessimistic prognosis on number of required S/G entries */
311 #define AHCI_SG_ENTRIES	(roundup(btoc(MAXPHYS) + 1, 8))
312 /* Command list. 32 commands. First, 1Kbyte aligned. */
313 #define AHCI_CL_OFFSET              0
314 #define AHCI_CL_SIZE                32
315 /* Command tables. Up to 32 commands, Each, 128byte aligned. */
316 #define AHCI_CT_OFFSET              (AHCI_CL_OFFSET + AHCI_CL_SIZE * AHCI_MAX_SLOTS)
317 #define AHCI_CT_SIZE                (128 + AHCI_SG_ENTRIES * 16)
318 /* Total main work area. */
319 #define AHCI_WORK_SIZE              (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots)
320 
321 struct ahci_dma_prd {
322     u_int64_t                   dba;
323     u_int32_t                   reserved;
324     u_int32_t                   dbc;            /* 0 based */
325 #define AHCI_PRD_MASK		0x003fffff      /* max 4MB */
326 #define AHCI_PRD_MAX		(AHCI_PRD_MASK + 1)
327 #define AHCI_PRD_IPC		(1U << 31)
328 } __packed;
329 
330 struct ahci_cmd_tab {
331     u_int8_t                    cfis[64];
332     u_int8_t                    acmd[32];
333     u_int8_t                    reserved[32];
334     struct ahci_dma_prd         prd_tab[AHCI_SG_ENTRIES];
335 } __packed;
336 
337 struct ahci_cmd_list {
338     u_int16_t                   cmd_flags;
339 #define AHCI_CMD_ATAPI		0x0020
340 #define AHCI_CMD_WRITE		0x0040
341 #define AHCI_CMD_PREFETCH		0x0080
342 #define AHCI_CMD_RESET		0x0100
343 #define AHCI_CMD_BIST		0x0200
344 #define AHCI_CMD_CLR_BUSY		0x0400
345 
346     u_int16_t                   prd_length;     /* PRD entries */
347     u_int32_t                   bytecount;
348     u_int64_t                   cmd_table_phys; /* 128byte aligned */
349 } __packed;
350 
351 /* misc defines */
352 #define ATA_IRQ_RID                     0
353 #define ATA_INTR_FLAGS                  (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY)
354 
355 struct ata_dmaslot {
356     bus_dmamap_t                data_map;       /* data DMA map */
357     int				nsegs;		/* Number of segs loaded */
358 };
359 
360 /* structure holding DMA related information */
361 struct ata_dma {
362     bus_dma_tag_t               work_tag;       /* workspace DMA tag */
363     bus_dmamap_t                work_map;       /* workspace DMA map */
364     uint8_t                     *work;          /* workspace */
365     bus_addr_t                  work_bus;       /* bus address of work */
366     bus_dma_tag_t               rfis_tag;       /* RFIS list DMA tag */
367     bus_dmamap_t                rfis_map;       /* RFIS list DMA map */
368     uint8_t                     *rfis;          /* FIS receive area */
369     bus_addr_t                  rfis_bus;       /* bus address of rfis */
370     bus_dma_tag_t               data_tag;       /* data DMA tag */
371 };
372 
373 enum ahci_slot_states {
374 	AHCI_SLOT_EMPTY,
375 	AHCI_SLOT_LOADING,
376 	AHCI_SLOT_RUNNING,
377 	AHCI_SLOT_EXECUTING
378 };
379 
380 struct ahci_slot {
381     struct ahci_channel		*ch;		/* Channel */
382     u_int8_t			slot;           /* Number of this slot */
383     enum ahci_slot_states	state;          /* Slot state */
384     union ccb			*ccb;		/* CCB occupying slot */
385     struct ata_dmaslot          dma;            /* DMA data of this slot */
386     struct callout              timeout;        /* Execution timeout */
387 };
388 
389 struct ahci_device {
390 	int			revision;
391 	int			mode;
392 	u_int			bytecount;
393 	u_int			atapi;
394 	u_int			tags;
395 	u_int			caps;
396 };
397 
398 struct ahci_led {
399 	device_t		dev;		/* Device handle */
400 	struct cdev		*led;
401 	uint8_t			num;		/* Number of this led */
402 	uint8_t			state;		/* State of this led */
403 };
404 
405 #define	AHCI_NUM_LEDS		3
406 
407 /* structure describing an ATA channel */
408 struct ahci_channel {
409 	device_t		dev;            /* Device handle */
410 	int			unit;           /* Physical channel */
411 	struct resource		*r_mem;		/* Memory of this channel */
412 	struct resource		*r_irq;         /* Interrupt of this channel */
413 	void			*ih;            /* Interrupt handle */
414 	struct ata_dma		dma;            /* DMA data */
415 	struct cam_sim		*sim;
416 	struct cam_path		*path;
417 	uint32_t		caps;		/* Controller capabilities */
418 	uint32_t		caps2;		/* Controller capabilities */
419 	uint32_t		chcaps;		/* Channel capabilities */
420 	uint32_t		chscaps;	/* Channel sleep capabilities */
421 	uint16_t		vendorid;	/* Vendor ID from the bus */
422 	uint16_t		deviceid;	/* Device ID from the bus */
423 	uint16_t		subvendorid;	/* Subvendor ID from the bus */
424 	uint16_t		subdeviceid;	/* Subdevice ID from the bus */
425 	int			quirks;
426 	int			numslots;	/* Number of present slots */
427 	int			pm_level;	/* power management level */
428 	int			devices;        /* What is present */
429 	int			pm_present;	/* PM presence reported */
430 	int			fbs_enabled;	/* FIS-based switching enabled */
431 
432 	void			(*start)(struct ahci_channel *);
433 
434 	union ccb		*hold[AHCI_MAX_SLOTS];
435 	struct ahci_slot	slot[AHCI_MAX_SLOTS];
436 	uint32_t		oslots;		/* Occupied slots */
437 	uint32_t		rslots;		/* Running slots */
438 	uint32_t		aslots;		/* Slots with atomic commands  */
439 	uint32_t		eslots;		/* Slots in error */
440 	uint32_t		toslots;	/* Slots in timeout */
441 	int			lastslot;	/* Last used slot */
442 	int			taggedtarget;	/* Last tagged target */
443 	int			numrslots;	/* Number of running slots */
444 	int			numrslotspd[16];/* Number of running slots per dev */
445 	int			numtslots;	/* Number of tagged slots */
446 	int			numtslotspd[16];/* Number of tagged slots per dev */
447 	int			numhslots;	/* Number of held slots */
448 	int			recoverycmd;	/* Our READ LOG active */
449 	int			fatalerr;	/* Fatal error happened */
450 	int			resetting;	/* Hard-reset in progress. */
451 	int			resetpolldiv;	/* Hard-reset poll divider. */
452 	int			listening;	/* SUD bit is cleared. */
453 	int			wrongccs;	/* CCS field in CMD was wrong */
454 	union ccb		*frozen;	/* Frozen command */
455 	struct callout		pm_timer;	/* Power management events */
456 	struct callout		reset_timer;	/* Hard-reset timeout */
457 
458 	struct ahci_device	user[16];	/* User-specified settings */
459 	struct ahci_device	curr[16];	/* Current settings */
460 
461 	struct mtx_padalign	mtx;		/* state lock */
462 	STAILQ_HEAD(, ccb_hdr)	doneq;		/* queue of completed CCBs */
463 	int			batch;		/* doneq is in use */
464 
465 	int			disablephy;	/* keep PHY disabled */
466 };
467 
468 struct ahci_enclosure {
469 	device_t		dev;            /* Device handle */
470 	struct resource		*r_memc;	/* Control register */
471 	struct resource		*r_memt;	/* Transmit buffer */
472 	struct resource		*r_memr;	/* Receive buffer */
473 	struct cam_sim		*sim;
474 	struct cam_path		*path;
475 	struct mtx		mtx;		/* state lock */
476 	struct ahci_led		leds[AHCI_MAX_PORTS * 3];
477 	uint32_t		capsem;		/* Controller capabilities */
478 	uint8_t			status[AHCI_MAX_PORTS][4]; /* ArrayDev statuses */
479 	int			quirks;
480 	int			channels;
481 	uint32_t		ichannels;
482 };
483 
484 /* structure describing a AHCI controller */
485 struct ahci_controller {
486 	device_t		dev;
487 	bus_dma_tag_t		dma_tag;
488 	int			r_rid;
489 	int			r_msix_tab_rid;
490 	int			r_msix_pba_rid;
491 	uint16_t		vendorid;	/* Vendor ID from the bus */
492 	uint16_t		deviceid;	/* Device ID from the bus */
493 	uint16_t		subvendorid;	/* Subvendor ID from the bus */
494 	uint16_t		subdeviceid;	/* Subdevice ID from the bus */
495 	struct resource		*r_mem;
496 	struct resource		*r_msix_table;
497 	struct resource		*r_msix_pba;
498 	struct rman		sc_iomem;
499 	struct ahci_controller_irq {
500 		struct ahci_controller	*ctlr;
501 		struct resource		*r_irq;
502 		void			*handle;
503 		int			r_irq_rid;
504 		int			mode;
505 #define	AHCI_IRQ_MODE_ALL	0
506 #define	AHCI_IRQ_MODE_AFTER	1
507 #define	AHCI_IRQ_MODE_ONE	2
508 	} irqs[AHCI_MAX_IRQS];
509 	uint32_t		caps;		/* Controller capabilities */
510 	uint32_t		caps2;		/* Controller capabilities */
511 	uint32_t		capsem;		/* Controller capabilities */
512 	uint32_t		emloc;		/* EM buffer location */
513 	int			quirks;
514 	int			numirqs;
515 	int			channels;
516 	uint32_t		ichannels;
517 	int			ccc;		/* CCC timeout */
518 	int			cccv;		/* CCC vector */
519 	int			direct;		/* Direct command completion */
520 	int			msi;		/* MSI interupts */
521 	struct {
522 		void			(*function)(void *);
523 		void			*argument;
524 	} interrupt[AHCI_MAX_PORTS];
525 	void			(*ch_start)(struct ahci_channel *);
526 	int			dma_coherent;	/* DMA is cache-coherent */
527 	struct mtx		ch_mtx;		/* Lock for attached channels */
528 	struct ahci_channel	*ch[AHCI_MAX_PORTS];	/* Attached channels */
529 };
530 
531 enum ahci_err_type {
532 	AHCI_ERR_NONE,		/* No error */
533 	AHCI_ERR_INVALID,	/* Error detected by us before submitting. */
534 	AHCI_ERR_INNOCENT,	/* Innocent victim. */
535 	AHCI_ERR_TFE,		/* Task File Error. */
536 	AHCI_ERR_SATA,		/* SATA error. */
537 	AHCI_ERR_TIMEOUT,	/* Command execution timeout. */
538 	AHCI_ERR_NCQ,		/* NCQ command error. CCB should be put on hold
539 				 * until READ LOG executed to reveal error. */
540 };
541 
542 /* macros to hide busspace uglyness */
543 #define ATA_INB(res, offset) \
544 	bus_read_1((res), (offset))
545 #define ATA_INW(res, offset) \
546 	bus_read_2((res), (offset))
547 #define ATA_INL(res, offset) \
548 	bus_read_4((res), (offset))
549 #define ATA_INSW(res, offset, addr, count) \
550 	bus_read_multi_2((res), (offset), (addr), (count))
551 #define ATA_INSW_STRM(res, offset, addr, count) \
552 	bus_read_multi_stream_2((res), (offset), (addr), (count))
553 #define ATA_INSL(res, offset, addr, count) \
554 	bus_read_multi_4((res), (offset), (addr), (count))
555 #define ATA_INSL_STRM(res, offset, addr, count) \
556 	bus_read_multi_stream_4((res), (offset), (addr), (count))
557 #define ATA_OUTB(res, offset, value) \
558 	bus_write_1((res), (offset), (value))
559 #define ATA_OUTW(res, offset, value) \
560 	bus_write_2((res), (offset), (value))
561 #define ATA_OUTL(res, offset, value) \
562 	bus_write_4((res), (offset), (value))
563 #define ATA_OUTSW(res, offset, addr, count) \
564 	bus_write_multi_2((res), (offset), (addr), (count))
565 #define ATA_OUTSW_STRM(res, offset, addr, count) \
566 	bus_write_multi_stream_2((res), (offset), (addr), (count))
567 #define ATA_OUTSL(res, offset, addr, count) \
568 	bus_write_multi_4((res), (offset), (addr), (count))
569 #define ATA_OUTSL_STRM(res, offset, addr, count) \
570 	bus_write_multi_stream_4((res), (offset), (addr), (count))
571 
572 /*
573  * On some platforms, we must ensure proper interdevice write ordering.
574  * The AHCI interrupt status register must be updated in HW before
575  * registers in interrupt controller.
576  * Unfortunately, only way how we can do it is readback.
577  *
578  * Currently, only ARM is known to have this issue.
579  */
580 #if defined(__arm__)
581 #define ATA_RBL(res, offset) \
582 	bus_read_4((res), (offset))
583 #else
584 #define ATA_RBL(res, offset)
585 #endif
586 
587 #define AHCI_Q_NOFORCE		0x00000001
588 #define AHCI_Q_NOPMP		0x00000002
589 #define AHCI_Q_NONCQ		0x00000004
590 #define AHCI_Q_1CH		0x00000008
591 #define AHCI_Q_2CH		0x00000010
592 #define AHCI_Q_4CH		0x00000020
593 #define AHCI_Q_EDGEIS		0x00000040
594 #define AHCI_Q_SATA2		0x00000080
595 #define AHCI_Q_NOBSYRES		0x00000100
596 #define AHCI_Q_NOAA		0x00000200
597 #define AHCI_Q_NOCOUNT		0x00000400
598 #define AHCI_Q_ALTSIG		0x00000800
599 #define AHCI_Q_NOMSI		0x00001000
600 #define AHCI_Q_ATI_PMP_BUG	0x00002000
601 #define AHCI_Q_MAXIO_64K	0x00004000
602 #define AHCI_Q_SATA1_UNIT0	0x00008000	/* need better method for this */
603 #define AHCI_Q_ABAR0		0x00010000
604 #define AHCI_Q_1MSI		0x00020000
605 #define AHCI_Q_FORCE_PI		0x00040000
606 #define AHCI_Q_RESTORE_CAP	0x00080000
607 #define AHCI_Q_NOMSIX		0x00100000
608 #define AHCI_Q_MRVL_SR_DEL	0x00200000
609 #define AHCI_Q_NOCCS		0x00400000
610 #define AHCI_Q_NOAUX		0x00800000
611 
612 #define AHCI_Q_BIT_STRING	\
613 	"\020"			\
614 	"\001NOFORCE"		\
615 	"\002NOPMP"		\
616 	"\003NONCQ"		\
617 	"\0041CH"		\
618 	"\0052CH"		\
619 	"\0064CH"		\
620 	"\007EDGEIS"		\
621 	"\010SATA2"		\
622 	"\011NOBSYRES"		\
623 	"\012NOAA"		\
624 	"\013NOCOUNT"		\
625 	"\014ALTSIG"		\
626 	"\015NOMSI"		\
627 	"\016ATI_PMP_BUG"	\
628 	"\017MAXIO_64K"		\
629 	"\020SATA1_UNIT0"	\
630 	"\021ABAR0"		\
631 	"\0221MSI"              \
632 	"\023FORCE_PI"          \
633 	"\024RESTORE_CAP"	\
634 	"\025NOMSIX"		\
635 	"\026MRVL_SR_DEL"	\
636 	"\027NOCCS"		\
637 	"\030NOAUX"
638 
639 int ahci_attach(device_t dev);
640 int ahci_detach(device_t dev);
641 int ahci_setup_interrupt(device_t dev);
642 int ahci_print_child(device_t dev, device_t child);
643 struct resource *ahci_alloc_resource(device_t dev, device_t child, int type, int *rid,
644     rman_res_t start, rman_res_t end, rman_res_t count, u_int flags);
645 int ahci_release_resource(device_t dev, device_t child, int type, int rid,
646     struct resource *r);
647 int ahci_setup_intr(device_t dev, device_t child, struct resource *irq,
648     int flags, driver_filter_t *filter, driver_intr_t *function,
649     void *argument, void **cookiep);
650 int ahci_teardown_intr(device_t dev, device_t child, struct resource *irq,
651     void *cookie);
652 int ahci_child_location_str(device_t dev, device_t child, char *buf,
653     size_t buflen);
654 bus_dma_tag_t ahci_get_dma_tag(device_t dev, device_t child);
655 int ahci_ctlr_reset(device_t dev);
656 int ahci_ctlr_setup(device_t dev);
657 void ahci_free_mem(device_t dev);
658 
659 /* Functions to allow AHCI EM to access other channels. */
660 void ahci_attached(device_t dev, struct ahci_channel *ch);
661 void ahci_detached(device_t dev, struct ahci_channel *ch);
662 struct ahci_channel * ahci_getch(device_t dev, int n);
663 void ahci_putch(struct ahci_channel *ch);
664 
665 extern devclass_t ahci_devclass;
666 
667