1 /*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 /* ATA register defines */ 31 #define ATA_DATA 0 /* (RW) data */ 32 33 #define ATA_FEATURE 1 /* (W) feature */ 34 #define ATA_F_DMA 0x01 /* enable DMA */ 35 #define ATA_F_OVL 0x02 /* enable overlap */ 36 37 #define ATA_COUNT 2 /* (W) sector count */ 38 39 #define ATA_SECTOR 3 /* (RW) sector # */ 40 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 41 #define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 42 #define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 43 #define ATA_D_LBA 0x40 /* use LBA addressing */ 44 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 45 46 #define ATA_COMMAND 7 /* (W) command */ 47 48 #define ATA_ERROR 8 /* (R) error */ 49 #define ATA_E_ILI 0x01 /* illegal length */ 50 #define ATA_E_NM 0x02 /* no media */ 51 #define ATA_E_ABORT 0x04 /* command aborted */ 52 #define ATA_E_MCR 0x08 /* media change request */ 53 #define ATA_E_IDNF 0x10 /* ID not found */ 54 #define ATA_E_MC 0x20 /* media changed */ 55 #define ATA_E_UNC 0x40 /* uncorrectable data */ 56 #define ATA_E_ICRC 0x80 /* UDMA crc error */ 57 #define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 58 59 #define ATA_IREASON 9 /* (R) interrupt reason */ 60 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 61 #define ATA_I_IN 0x02 /* read (1) | write (0) */ 62 #define ATA_I_RELEASE 0x04 /* released bus (1) */ 63 #define ATA_I_TAGMASK 0xf8 /* tag mask */ 64 65 #define ATA_STATUS 10 /* (R) status */ 66 #define ATA_ALTSTAT 11 /* (R) alternate status */ 67 #define ATA_S_ERROR 0x01 /* error */ 68 #define ATA_S_INDEX 0x02 /* index */ 69 #define ATA_S_CORR 0x04 /* data corrected */ 70 #define ATA_S_DRQ 0x08 /* data request */ 71 #define ATA_S_DSC 0x10 /* drive seek completed */ 72 #define ATA_S_SERVICE 0x10 /* drive needs service */ 73 #define ATA_S_DWF 0x20 /* drive write fault */ 74 #define ATA_S_DMA 0x20 /* DMA ready */ 75 #define ATA_S_READY 0x40 /* drive ready */ 76 #define ATA_S_BUSY 0x80 /* busy */ 77 78 #define ATA_CONTROL 12 /* (W) control */ 79 #define ATA_A_IDS 0x02 /* disable interrupts */ 80 #define ATA_A_RESET 0x04 /* RESET controller */ 81 #define ATA_A_4BIT 0x08 /* 4 head bits */ 82 #define ATA_A_HOB 0x80 /* High Order Byte enable */ 83 84 /* SATA register defines */ 85 #define ATA_SSTATUS 13 86 #define ATA_SS_DET_MASK 0x0000000f 87 #define ATA_SS_DET_NO_DEVICE 0x00000000 88 #define ATA_SS_DET_DEV_PRESENT 0x00000001 89 #define ATA_SS_DET_PHY_ONLINE 0x00000003 90 #define ATA_SS_DET_PHY_OFFLINE 0x00000004 91 92 #define ATA_SS_SPD_MASK 0x000000f0 93 #define ATA_SS_SPD_NO_SPEED 0x00000000 94 #define ATA_SS_SPD_GEN1 0x00000010 95 #define ATA_SS_SPD_GEN2 0x00000020 96 #define ATA_SS_SPD_GEN3 0x00000040 97 98 #define ATA_SS_IPM_MASK 0x00000f00 99 #define ATA_SS_IPM_NO_DEVICE 0x00000000 100 #define ATA_SS_IPM_ACTIVE 0x00000100 101 #define ATA_SS_IPM_PARTIAL 0x00000200 102 #define ATA_SS_IPM_SLUMBER 0x00000600 103 104 #define ATA_SERROR 14 105 #define ATA_SE_DATA_CORRECTED 0x00000001 106 #define ATA_SE_COMM_CORRECTED 0x00000002 107 #define ATA_SE_DATA_ERR 0x00000100 108 #define ATA_SE_COMM_ERR 0x00000200 109 #define ATA_SE_PROT_ERR 0x00000400 110 #define ATA_SE_HOST_ERR 0x00000800 111 #define ATA_SE_PHY_CHANGED 0x00010000 112 #define ATA_SE_PHY_IERROR 0x00020000 113 #define ATA_SE_COMM_WAKE 0x00040000 114 #define ATA_SE_DECODE_ERR 0x00080000 115 #define ATA_SE_PARITY_ERR 0x00100000 116 #define ATA_SE_CRC_ERR 0x00200000 117 #define ATA_SE_HANDSHAKE_ERR 0x00400000 118 #define ATA_SE_LINKSEQ_ERR 0x00800000 119 #define ATA_SE_TRANSPORT_ERR 0x01000000 120 #define ATA_SE_UNKNOWN_FIS 0x02000000 121 122 #define ATA_SCONTROL 15 123 #define ATA_SC_DET_MASK 0x0000000f 124 #define ATA_SC_DET_IDLE 0x00000000 125 #define ATA_SC_DET_RESET 0x00000001 126 #define ATA_SC_DET_DISABLE 0x00000004 127 128 #define ATA_SC_SPD_MASK 0x000000f0 129 #define ATA_SC_SPD_NO_SPEED 0x00000000 130 #define ATA_SC_SPD_SPEED_GEN1 0x00000010 131 #define ATA_SC_SPD_SPEED_GEN2 0x00000020 132 #define ATA_SC_SPD_SPEED_GEN3 0x00000040 133 134 #define ATA_SC_IPM_MASK 0x00000f00 135 #define ATA_SC_IPM_NONE 0x00000000 136 #define ATA_SC_IPM_DIS_PARTIAL 0x00000100 137 #define ATA_SC_IPM_DIS_SLUMBER 0x00000200 138 139 #define ATA_SACTIVE 16 140 141 #define AHCI_MAX_PORTS 32 142 #define AHCI_MAX_SLOTS 32 143 144 /* SATA AHCI v1.0 register defines */ 145 #define AHCI_CAP 0x00 146 #define AHCI_CAP_NPMASK 0x0000001f 147 #define AHCI_CAP_SXS 0x00000020 148 #define AHCI_CAP_EMS 0x00000040 149 #define AHCI_CAP_CCCS 0x00000080 150 #define AHCI_CAP_NCS 0x00001F00 151 #define AHCI_CAP_NCS_SHIFT 8 152 #define AHCI_CAP_PSC 0x00002000 153 #define AHCI_CAP_SSC 0x00004000 154 #define AHCI_CAP_PMD 0x00008000 155 #define AHCI_CAP_FBSS 0x00010000 156 #define AHCI_CAP_SPM 0x00020000 157 #define AHCI_CAP_SAM 0x00080000 158 #define AHCI_CAP_ISS 0x00F00000 159 #define AHCI_CAP_ISS_SHIFT 20 160 #define AHCI_CAP_SCLO 0x01000000 161 #define AHCI_CAP_SAL 0x02000000 162 #define AHCI_CAP_SALP 0x04000000 163 #define AHCI_CAP_SSS 0x08000000 164 #define AHCI_CAP_SMPS 0x10000000 165 #define AHCI_CAP_SSNTF 0x20000000 166 #define AHCI_CAP_SNCQ 0x40000000 167 #define AHCI_CAP_64BIT 0x80000000 168 169 #define AHCI_GHC 0x04 170 #define AHCI_GHC_AE 0x80000000 171 #define AHCI_GHC_MRSM 0x00000004 172 #define AHCI_GHC_IE 0x00000002 173 #define AHCI_GHC_HR 0x00000001 174 175 #define AHCI_IS 0x08 176 #define AHCI_PI 0x0c 177 #define AHCI_VS 0x10 178 179 #define AHCI_OFFSET 0x100 180 #define AHCI_STEP 0x80 181 182 #define AHCI_P_CLB 0x00 183 #define AHCI_P_CLBU 0x04 184 #define AHCI_P_FB 0x08 185 #define AHCI_P_FBU 0x0c 186 #define AHCI_P_IS 0x10 187 #define AHCI_P_IE 0x14 188 #define AHCI_P_IX_DHR 0x00000001 189 #define AHCI_P_IX_PS 0x00000002 190 #define AHCI_P_IX_DS 0x00000004 191 #define AHCI_P_IX_SDB 0x00000008 192 #define AHCI_P_IX_UF 0x00000010 193 #define AHCI_P_IX_DP 0x00000020 194 #define AHCI_P_IX_PC 0x00000040 195 #define AHCI_P_IX_DI 0x00000080 196 197 #define AHCI_P_IX_PRC 0x00400000 198 #define AHCI_P_IX_IPM 0x00800000 199 #define AHCI_P_IX_OF 0x01000000 200 #define AHCI_P_IX_INF 0x04000000 201 #define AHCI_P_IX_IF 0x08000000 202 #define AHCI_P_IX_HBD 0x10000000 203 #define AHCI_P_IX_HBF 0x20000000 204 #define AHCI_P_IX_TFE 0x40000000 205 #define AHCI_P_IX_CPD 0x80000000 206 207 #define AHCI_P_CMD 0x18 208 #define AHCI_P_CMD_ST 0x00000001 209 #define AHCI_P_CMD_SUD 0x00000002 210 #define AHCI_P_CMD_POD 0x00000004 211 #define AHCI_P_CMD_CLO 0x00000008 212 #define AHCI_P_CMD_FRE 0x00000010 213 #define AHCI_P_CMD_CCS_MASK 0x00001f00 214 #define AHCI_P_CMD_CCS_SHIFT 8 215 #define AHCI_P_CMD_ISS 0x00002000 216 #define AHCI_P_CMD_FR 0x00004000 217 #define AHCI_P_CMD_CR 0x00008000 218 #define AHCI_P_CMD_CPS 0x00010000 219 #define AHCI_P_CMD_PMA 0x00020000 220 #define AHCI_P_CMD_HPCP 0x00040000 221 #define AHCI_P_CMD_ISP 0x00080000 222 #define AHCI_P_CMD_CPD 0x00100000 223 #define AHCI_P_CMD_ATAPI 0x01000000 224 #define AHCI_P_CMD_DLAE 0x02000000 225 #define AHCI_P_CMD_ALPE 0x04000000 226 #define AHCI_P_CMD_ASP 0x08000000 227 #define AHCI_P_CMD_ICC_MASK 0xf0000000 228 #define AHCI_P_CMD_NOOP 0x00000000 229 #define AHCI_P_CMD_ACTIVE 0x10000000 230 #define AHCI_P_CMD_PARTIAL 0x20000000 231 #define AHCI_P_CMD_SLUMBER 0x60000000 232 233 #define AHCI_P_TFD 0x20 234 #define AHCI_P_SIG 0x24 235 #define AHCI_P_SSTS 0x28 236 #define AHCI_P_SCTL 0x2c 237 #define AHCI_P_SERR 0x30 238 #define AHCI_P_SACT 0x34 239 #define AHCI_P_CI 0x38 240 #define AHCI_P_SNTF 0x3C 241 #define AHCI_P_FBS 0x40 242 243 /* Just to be sure, if building as module. */ 244 #if MAXPHYS < 512 * 1024 245 #undef MAXPHYS 246 #define MAXPHYS 512 * 1024 247 #endif 248 /* Pessimistic prognosis on number of required S/G entries */ 249 #define AHCI_SG_ENTRIES (roundup(btoc(MAXPHYS) + 1, 8)) 250 /* Command list. 32 commands. First, 1Kbyte aligned. */ 251 #define AHCI_CL_OFFSET 0 252 #define AHCI_CL_SIZE 32 253 /* Command tables. Up to 32 commands, Each, 128byte aligned. */ 254 #define AHCI_CT_OFFSET (AHCI_CL_OFFSET + AHCI_CL_SIZE * AHCI_MAX_SLOTS) 255 #define AHCI_CT_SIZE (128 + AHCI_SG_ENTRIES * 16) 256 /* Total main work area. */ 257 #define AHCI_WORK_SIZE (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots) 258 259 struct ahci_dma_prd { 260 u_int64_t dba; 261 u_int32_t reserved; 262 u_int32_t dbc; /* 0 based */ 263 #define AHCI_PRD_MASK 0x003fffff /* max 4MB */ 264 #define AHCI_PRD_MAX (AHCI_PRD_MASK + 1) 265 #define AHCI_PRD_IPC (1 << 31) 266 } __packed; 267 268 struct ahci_cmd_tab { 269 u_int8_t cfis[64]; 270 u_int8_t acmd[32]; 271 u_int8_t reserved[32]; 272 struct ahci_dma_prd prd_tab[AHCI_SG_ENTRIES]; 273 } __packed; 274 275 struct ahci_cmd_list { 276 u_int16_t cmd_flags; 277 #define AHCI_CMD_ATAPI 0x0020 278 #define AHCI_CMD_WRITE 0x0040 279 #define AHCI_CMD_PREFETCH 0x0080 280 #define AHCI_CMD_RESET 0x0100 281 #define AHCI_CMD_BIST 0x0200 282 #define AHCI_CMD_CLR_BUSY 0x0400 283 284 u_int16_t prd_length; /* PRD entries */ 285 u_int32_t bytecount; 286 u_int64_t cmd_table_phys; /* 128byte aligned */ 287 } __packed; 288 289 /* misc defines */ 290 #define ATA_IRQ_RID 0 291 #define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 292 293 struct ata_dmaslot { 294 bus_dmamap_t data_map; /* data DMA map */ 295 int nsegs; /* Number of segs loaded */ 296 }; 297 298 /* structure holding DMA related information */ 299 struct ata_dma { 300 bus_dma_tag_t work_tag; /* workspace DMA tag */ 301 bus_dmamap_t work_map; /* workspace DMA map */ 302 uint8_t *work; /* workspace */ 303 bus_addr_t work_bus; /* bus address of work */ 304 bus_dma_tag_t rfis_tag; /* RFIS list DMA tag */ 305 bus_dmamap_t rfis_map; /* RFIS list DMA map */ 306 uint8_t *rfis; /* FIS receive area */ 307 bus_addr_t rfis_bus; /* bus address of rfis */ 308 bus_dma_tag_t data_tag; /* data DMA tag */ 309 u_int64_t max_address; /* highest DMA'able address */ 310 }; 311 312 enum ahci_slot_states { 313 AHCI_SLOT_EMPTY, 314 AHCI_SLOT_LOADING, 315 AHCI_SLOT_RUNNING, 316 AHCI_SLOT_WAITING 317 }; 318 319 struct ahci_slot { 320 device_t dev; /* Device handle */ 321 u_int8_t slot; /* Number of this slot */ 322 enum ahci_slot_states state; /* Slot state */ 323 union ccb *ccb; /* CCB occupying slot */ 324 struct ata_dmaslot dma; /* DMA data of this slot */ 325 struct callout timeout; /* Execution timeout */ 326 }; 327 328 /* structure describing an ATA channel */ 329 struct ahci_channel { 330 device_t dev; /* Device handle */ 331 int unit; /* Physical channel */ 332 struct resource *r_mem; /* Memory of this channel */ 333 struct resource *r_irq; /* Interrupt of this channel */ 334 void *ih; /* Interrupt handle */ 335 struct ata_dma dma; /* DMA data */ 336 struct cam_sim *sim; 337 struct cam_path *path; 338 uint32_t caps; /* Controller capabilities */ 339 int numslots; /* Number of present slots */ 340 int pm_level; /* power management level */ 341 int sata_rev; /* Maximum allowed SATA generation */ 342 343 struct ahci_slot slot[AHCI_MAX_SLOTS]; 344 union ccb *hold[AHCI_MAX_SLOTS]; 345 struct mtx mtx; /* state lock */ 346 int devices; /* What is present */ 347 int pm_present; /* PM presence reported */ 348 uint32_t rslots; /* Running slots */ 349 uint32_t aslots; /* Slots with atomic commands */ 350 int numrslots; /* Number of running slots */ 351 int numtslots; /* Number of tagged slots */ 352 int readlog; /* Our READ LOG active */ 353 int lastslot; /* Last used slot */ 354 int taggedtarget; /* Last tagged target */ 355 union ccb *frozen; /* Frozen command */ 356 }; 357 358 /* structure describing a AHCI controller */ 359 struct ahci_controller { 360 device_t dev; 361 int r_rid; 362 struct resource *r_mem; 363 struct rman sc_iomem; 364 struct ahci_controller_irq { 365 struct ahci_controller *ctlr; 366 struct resource *r_irq; 367 void *handle; 368 int r_irq_rid; 369 int mode; 370 #define AHCI_IRQ_MODE_ALL 0 371 #define AHCI_IRQ_MODE_AFTER 1 372 #define AHCI_IRQ_MODE_ONE 2 373 } irqs[16]; 374 int numirqs; 375 int channels; 376 int ichannels; 377 struct { 378 void (*function)(void *); 379 void *argument; 380 } interrupt[AHCI_MAX_PORTS]; 381 }; 382 383 enum ahci_err_type { 384 AHCI_ERR_NONE, /* No error */ 385 AHCI_ERR_INVALID, /* Error detected by us before submitting. */ 386 AHCI_ERR_INNOCENT, /* Innocent victim. */ 387 AHCI_ERR_TFE, /* Task File Error. */ 388 AHCI_ERR_SATA, /* SATA error. */ 389 AHCI_ERR_TIMEOUT, /* Command execution timeout. */ 390 AHCI_ERR_NCQ, /* NCQ command error. CCB should be put on hold 391 * until READ LOG executed to reveal error. */ 392 }; 393 394 /* macros to hide busspace uglyness */ 395 #define ATA_INB(res, offset) \ 396 bus_read_1((res), (offset)) 397 #define ATA_INW(res, offset) \ 398 bus_read_2((res), (offset)) 399 #define ATA_INL(res, offset) \ 400 bus_read_4((res), (offset)) 401 #define ATA_INSW(res, offset, addr, count) \ 402 bus_read_multi_2((res), (offset), (addr), (count)) 403 #define ATA_INSW_STRM(res, offset, addr, count) \ 404 bus_read_multi_stream_2((res), (offset), (addr), (count)) 405 #define ATA_INSL(res, offset, addr, count) \ 406 bus_read_multi_4((res), (offset), (addr), (count)) 407 #define ATA_INSL_STRM(res, offset, addr, count) \ 408 bus_read_multi_stream_4((res), (offset), (addr), (count)) 409 #define ATA_OUTB(res, offset, value) \ 410 bus_write_1((res), (offset), (value)) 411 #define ATA_OUTW(res, offset, value) \ 412 bus_write_2((res), (offset), (value)) 413 #define ATA_OUTL(res, offset, value) \ 414 bus_write_4((res), (offset), (value)) 415 #define ATA_OUTSW(res, offset, addr, count) \ 416 bus_write_multi_2((res), (offset), (addr), (count)) 417 #define ATA_OUTSW_STRM(res, offset, addr, count) \ 418 bus_write_multi_stream_2((res), (offset), (addr), (count)) 419 #define ATA_OUTSL(res, offset, addr, count) \ 420 bus_write_multi_4((res), (offset), (addr), (count)) 421 #define ATA_OUTSL_STRM(res, offset, addr, count) \ 422 bus_write_multi_stream_4((res), (offset), (addr), (count)) 423