1 /*- 2 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <sys/endian.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <machine/stdarg.h> 41 #include <machine/resource.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include "ahci.h" 47 48 #include <cam/cam.h> 49 #include <cam/cam_ccb.h> 50 #include <cam/cam_sim.h> 51 #include <cam/cam_xpt_sim.h> 52 #include <cam/cam_debug.h> 53 54 /* local prototypes */ 55 static int ahci_setup_interrupt(device_t dev); 56 static void ahci_intr(void *data); 57 static void ahci_intr_one(void *data); 58 static int ahci_suspend(device_t dev); 59 static int ahci_resume(device_t dev); 60 static int ahci_ch_init(device_t dev); 61 static int ahci_ch_deinit(device_t dev); 62 static int ahci_ch_suspend(device_t dev); 63 static int ahci_ch_resume(device_t dev); 64 static void ahci_ch_pm(void *arg); 65 static void ahci_ch_intr_locked(void *data); 66 static void ahci_ch_intr(void *data); 67 static int ahci_ctlr_reset(device_t dev); 68 static int ahci_ctlr_setup(device_t dev); 69 static void ahci_begin_transaction(device_t dev, union ccb *ccb); 70 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 71 static void ahci_execute_transaction(struct ahci_slot *slot); 72 static void ahci_timeout(struct ahci_slot *slot); 73 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 74 static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 75 static void ahci_dmainit(device_t dev); 76 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 77 static void ahci_dmafini(device_t dev); 78 static void ahci_slotsalloc(device_t dev); 79 static void ahci_slotsfree(device_t dev); 80 static void ahci_reset(device_t dev); 81 static void ahci_start(device_t dev, int fbs); 82 static void ahci_stop(device_t dev); 83 static void ahci_clo(device_t dev); 84 static void ahci_start_fr(device_t dev); 85 static void ahci_stop_fr(device_t dev); 86 87 static int ahci_sata_connect(struct ahci_channel *ch); 88 static int ahci_sata_phy_reset(device_t dev); 89 static int ahci_wait_ready(device_t dev, int t, int t0); 90 91 static void ahci_issue_recovery(device_t dev); 92 static void ahci_process_read_log(device_t dev, union ccb *ccb); 93 static void ahci_process_request_sense(device_t dev, union ccb *ccb); 94 95 static void ahciaction(struct cam_sim *sim, union ccb *ccb); 96 static void ahcipoll(struct cam_sim *sim); 97 98 static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 99 100 static struct { 101 uint32_t id; 102 uint8_t rev; 103 const char *name; 104 int quirks; 105 #define AHCI_Q_NOFORCE 1 106 #define AHCI_Q_NOPMP 2 107 #define AHCI_Q_NONCQ 4 108 #define AHCI_Q_1CH 8 109 #define AHCI_Q_2CH 16 110 #define AHCI_Q_4CH 32 111 #define AHCI_Q_EDGEIS 64 112 #define AHCI_Q_SATA2 128 113 #define AHCI_Q_NOBSYRES 256 114 #define AHCI_Q_NOAA 512 115 #define AHCI_Q_NOCOUNT 1024 116 #define AHCI_Q_ALTSIG 2048 117 } ahci_ids[] = { 118 {0x43801002, 0x00, "ATI IXP600", 0}, 119 {0x43901002, 0x00, "ATI IXP700", 0}, 120 {0x43911002, 0x00, "ATI IXP700", 0}, 121 {0x43921002, 0x00, "ATI IXP700", 0}, 122 {0x43931002, 0x00, "ATI IXP700", 0}, 123 {0x43941002, 0x00, "ATI IXP800", 0}, 124 {0x43951002, 0x00, "ATI IXP800", 0}, 125 {0x06121b21, 0x00, "ASMedia ASM1061", 0}, 126 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE}, 127 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE}, 128 {0x26818086, 0x00, "Intel ESB2", 0}, 129 {0x26828086, 0x00, "Intel ESB2", 0}, 130 {0x26838086, 0x00, "Intel ESB2", 0}, 131 {0x27c18086, 0x00, "Intel ICH7", 0}, 132 {0x27c38086, 0x00, "Intel ICH7", 0}, 133 {0x27c58086, 0x00, "Intel ICH7M", 0}, 134 {0x27c68086, 0x00, "Intel ICH7M", 0}, 135 {0x28218086, 0x00, "Intel ICH8", 0}, 136 {0x28228086, 0x00, "Intel ICH8", 0}, 137 {0x28248086, 0x00, "Intel ICH8", 0}, 138 {0x28298086, 0x00, "Intel ICH8M", 0}, 139 {0x282a8086, 0x00, "Intel ICH8M", 0}, 140 {0x29228086, 0x00, "Intel ICH9", 0}, 141 {0x29238086, 0x00, "Intel ICH9", 0}, 142 {0x29248086, 0x00, "Intel ICH9", 0}, 143 {0x29258086, 0x00, "Intel ICH9", 0}, 144 {0x29278086, 0x00, "Intel ICH9", 0}, 145 {0x29298086, 0x00, "Intel ICH9M", 0}, 146 {0x292a8086, 0x00, "Intel ICH9M", 0}, 147 {0x292b8086, 0x00, "Intel ICH9M", 0}, 148 {0x292c8086, 0x00, "Intel ICH9M", 0}, 149 {0x292f8086, 0x00, "Intel ICH9M", 0}, 150 {0x294d8086, 0x00, "Intel ICH9", 0}, 151 {0x294e8086, 0x00, "Intel ICH9M", 0}, 152 {0x3a058086, 0x00, "Intel ICH10", 0}, 153 {0x3a228086, 0x00, "Intel ICH10", 0}, 154 {0x3a258086, 0x00, "Intel ICH10", 0}, 155 {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0}, 156 {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0}, 157 {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0}, 158 {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0}, 159 {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0}, 160 {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0}, 161 {0x1c028086, 0x00, "Intel Cougar Point", 0}, 162 {0x1c038086, 0x00, "Intel Cougar Point", 0}, 163 {0x1c048086, 0x00, "Intel Cougar Point", 0}, 164 {0x1c058086, 0x00, "Intel Cougar Point", 0}, 165 {0x1d028086, 0x00, "Intel Patsburg", 0}, 166 {0x1d048086, 0x00, "Intel Patsburg", 0}, 167 {0x1d068086, 0x00, "Intel Patsburg", 0}, 168 {0x28268086, 0x00, "Intel Patsburg (RAID)", 0}, 169 {0x1e028086, 0x00, "Intel Panther Point", 0}, 170 {0x1e038086, 0x00, "Intel Panther Point", 0}, 171 {0x1e048086, 0x00, "Intel Panther Point", 0}, 172 {0x1e058086, 0x00, "Intel Panther Point", 0}, 173 {0x1e068086, 0x00, "Intel Panther Point", 0}, 174 {0x1e078086, 0x00, "Intel Panther Point", 0}, 175 {0x1e0e8086, 0x00, "Intel Panther Point", 0}, 176 {0x1e0f8086, 0x00, "Intel Panther Point", 0}, 177 {0x23238086, 0x00, "Intel DH89xxCC", 0}, 178 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE}, 179 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE}, 180 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE}, 181 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE}, 182 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE}, 183 {0x611111ab, 0x00, "Marvell 88SE6111", AHCI_Q_NOFORCE | AHCI_Q_1CH | 184 AHCI_Q_EDGEIS}, 185 {0x612111ab, 0x00, "Marvell 88SE6121", AHCI_Q_NOFORCE | AHCI_Q_2CH | 186 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 187 {0x614111ab, 0x00, "Marvell 88SE6141", AHCI_Q_NOFORCE | AHCI_Q_4CH | 188 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 189 {0x614511ab, 0x00, "Marvell 88SE6145", AHCI_Q_NOFORCE | AHCI_Q_4CH | 190 AHCI_Q_EDGEIS | AHCI_Q_NONCQ | AHCI_Q_NOCOUNT}, 191 {0x91201b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_NOBSYRES}, 192 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 193 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES}, 194 {0x91251b4b, 0x00, "Marvell 88SE9125", AHCI_Q_NOBSYRES}, 195 {0x91281b4b, 0x00, "Marvell 88SE9128", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 196 {0x91301b4b, 0x00, "Marvell 88SE9130", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 197 {0x91721b4b, 0x00, "Marvell 88SE9172", AHCI_Q_NOBSYRES}, 198 {0x91821b4b, 0x00, "Marvell 88SE9182", AHCI_Q_NOBSYRES}, 199 {0x92201b4b, 0x00, "Marvell 88SE9220", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 200 {0x92301b4b, 0x00, "Marvell 88SE9230", AHCI_Q_NOBSYRES|AHCI_Q_ALTSIG}, 201 {0x92351b4b, 0x00, "Marvell 88SE9235", AHCI_Q_NOBSYRES}, 202 {0x06201103, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 203 {0x06201b4b, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES}, 204 {0x06221103, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 205 {0x06221b4b, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES}, 206 {0x06401103, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 207 {0x06401b4b, 0x00, "HighPoint RocketRAID 640", AHCI_Q_NOBSYRES}, 208 {0x06441103, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 209 {0x06441b4b, 0x00, "HighPoint RocketRAID 644", AHCI_Q_NOBSYRES}, 210 {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 211 {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 212 {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 213 {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 214 {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 215 {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 216 {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 217 {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA}, 218 {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 219 {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 220 {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 221 {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 222 {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 223 {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 224 {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 225 {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 226 {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 227 {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 228 {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 229 {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 230 {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA}, 231 {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 232 {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 233 {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 234 {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 235 {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 236 {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 237 {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 238 {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 239 {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 240 {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 241 {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 242 {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA}, 243 {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 244 {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 245 {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 246 {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 247 {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 248 {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 249 {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 250 {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 251 {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 252 {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 253 {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 254 {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA}, 255 {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 256 {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 257 {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 258 {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 259 {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 260 {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 261 {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 262 {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 263 {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 264 {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 265 {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 266 {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA}, 267 {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 268 {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOFORCE|AHCI_Q_NOAA}, 269 {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 270 {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 271 {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 272 {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 273 {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 274 {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 275 {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 276 {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 277 {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 278 {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA}, 279 {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 280 {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ}, 281 {0x11841039, 0x00, "SiS 966", 0}, 282 {0x11851039, 0x00, "SiS 968", 0}, 283 {0x01861039, 0x00, "SiS 968", 0}, 284 {0x00000000, 0x00, NULL, 0} 285 }; 286 287 #define recovery_type spriv_field0 288 #define RECOVERY_NONE 0 289 #define RECOVERY_READ_LOG 1 290 #define RECOVERY_REQUEST_SENSE 2 291 #define recovery_slot spriv_field1 292 293 static int force_ahci = 1; 294 TUNABLE_INT("hw.ahci.force", &force_ahci); 295 296 static int 297 ahci_probe(device_t dev) 298 { 299 char buf[64]; 300 int i, valid = 0; 301 uint32_t devid = pci_get_devid(dev); 302 uint8_t revid = pci_get_revid(dev); 303 304 /* Is this a possible AHCI candidate? */ 305 if (pci_get_class(dev) == PCIC_STORAGE && 306 pci_get_subclass(dev) == PCIS_STORAGE_SATA && 307 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0) 308 valid = 1; 309 /* Is this a known AHCI chip? */ 310 for (i = 0; ahci_ids[i].id != 0; i++) { 311 if (ahci_ids[i].id == devid && 312 ahci_ids[i].rev <= revid && 313 (valid || (force_ahci == 1 && 314 !(ahci_ids[i].quirks & AHCI_Q_NOFORCE)))) { 315 /* Do not attach JMicrons with single PCI function. */ 316 if (pci_get_vendor(dev) == 0x197b && 317 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0) 318 return (ENXIO); 319 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 320 ahci_ids[i].name); 321 device_set_desc_copy(dev, buf); 322 return (BUS_PROBE_VENDOR); 323 } 324 } 325 if (!valid) 326 return (ENXIO); 327 device_set_desc_copy(dev, "AHCI SATA controller"); 328 return (BUS_PROBE_VENDOR); 329 } 330 331 static int 332 ahci_ata_probe(device_t dev) 333 { 334 char buf[64]; 335 int i; 336 uint32_t devid = pci_get_devid(dev); 337 uint8_t revid = pci_get_revid(dev); 338 339 if ((intptr_t)device_get_ivars(dev) >= 0) 340 return (ENXIO); 341 /* Is this a known AHCI chip? */ 342 for (i = 0; ahci_ids[i].id != 0; i++) { 343 if (ahci_ids[i].id == devid && 344 ahci_ids[i].rev <= revid) { 345 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 346 ahci_ids[i].name); 347 device_set_desc_copy(dev, buf); 348 return (BUS_PROBE_VENDOR); 349 } 350 } 351 device_set_desc_copy(dev, "AHCI SATA controller"); 352 return (BUS_PROBE_VENDOR); 353 } 354 355 static int 356 ahci_attach(device_t dev) 357 { 358 struct ahci_controller *ctlr = device_get_softc(dev); 359 device_t child; 360 int error, unit, speed, i; 361 uint32_t devid = pci_get_devid(dev); 362 uint8_t revid = pci_get_revid(dev); 363 u_int32_t version; 364 365 ctlr->dev = dev; 366 i = 0; 367 while (ahci_ids[i].id != 0 && 368 (ahci_ids[i].id != devid || 369 ahci_ids[i].rev > revid)) 370 i++; 371 ctlr->quirks = ahci_ids[i].quirks; 372 resource_int_value(device_get_name(dev), 373 device_get_unit(dev), "ccc", &ctlr->ccc); 374 /* if we have a memory BAR(5) we are likely on an AHCI part */ 375 ctlr->r_rid = PCIR_BAR(5); 376 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 377 &ctlr->r_rid, RF_ACTIVE))) 378 return ENXIO; 379 /* Setup our own memory management for channels. */ 380 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 381 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 382 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 383 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 384 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 385 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 386 return (error); 387 } 388 if ((error = rman_manage_region(&ctlr->sc_iomem, 389 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 390 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 391 rman_fini(&ctlr->sc_iomem); 392 return (error); 393 } 394 pci_enable_busmaster(dev); 395 /* Reset controller */ 396 if ((error = ahci_ctlr_reset(dev)) != 0) { 397 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 398 rman_fini(&ctlr->sc_iomem); 399 return (error); 400 }; 401 /* Get the HW capabilities */ 402 version = ATA_INL(ctlr->r_mem, AHCI_VS); 403 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 404 if (version >= 0x00010020) 405 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 406 if (ctlr->caps & AHCI_CAP_EMS) 407 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 408 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 409 410 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */ 411 if ((ctlr->quirks & AHCI_Q_NOBSYRES) && 412 (ctlr->quirks & AHCI_Q_ALTSIG) && 413 (ctlr->caps & AHCI_CAP_SPM) == 0) 414 ctlr->quirks &= ~AHCI_Q_NOBSYRES; 415 416 if (ctlr->quirks & AHCI_Q_1CH) { 417 ctlr->caps &= ~AHCI_CAP_NPMASK; 418 ctlr->ichannels &= 0x01; 419 } 420 if (ctlr->quirks & AHCI_Q_2CH) { 421 ctlr->caps &= ~AHCI_CAP_NPMASK; 422 ctlr->caps |= 1; 423 ctlr->ichannels &= 0x03; 424 } 425 if (ctlr->quirks & AHCI_Q_4CH) { 426 ctlr->caps &= ~AHCI_CAP_NPMASK; 427 ctlr->caps |= 3; 428 ctlr->ichannels &= 0x0f; 429 } 430 ctlr->channels = MAX(flsl(ctlr->ichannels), 431 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 432 if (ctlr->quirks & AHCI_Q_NOPMP) 433 ctlr->caps &= ~AHCI_CAP_SPM; 434 if (ctlr->quirks & AHCI_Q_NONCQ) 435 ctlr->caps &= ~AHCI_CAP_SNCQ; 436 if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 437 ctlr->ccc = 0; 438 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC); 439 ahci_ctlr_setup(dev); 440 /* Setup interrupts. */ 441 if (ahci_setup_interrupt(dev)) { 442 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 443 rman_fini(&ctlr->sc_iomem); 444 return ENXIO; 445 } 446 /* Announce HW capabilities. */ 447 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 448 device_printf(dev, 449 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 450 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 451 ((version >> 4) & 0xf0) + (version & 0x0f), 452 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 453 ((speed == 1) ? "1.5":((speed == 2) ? "3": 454 ((speed == 3) ? "6":"?"))), 455 (ctlr->caps & AHCI_CAP_SPM) ? 456 "supported" : "not supported", 457 (ctlr->caps & AHCI_CAP_FBSS) ? 458 " with FBS" : ""); 459 if (bootverbose) { 460 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 461 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 462 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 463 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 464 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 465 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 466 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 467 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 468 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 469 ((speed == 1) ? "1.5":((speed == 2) ? "3": 470 ((speed == 3) ? "6":"?")))); 471 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 472 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 473 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 474 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 475 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 476 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 477 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 478 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 479 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 480 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 481 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 482 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 483 } 484 if (bootverbose && version >= 0x00010020) { 485 device_printf(dev, "Caps2:%s%s%s\n", 486 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 487 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 488 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 489 } 490 /* Attach all channels on this controller */ 491 for (unit = 0; unit < ctlr->channels; unit++) { 492 child = device_add_child(dev, "ahcich", -1); 493 if (child == NULL) { 494 device_printf(dev, "failed to add channel device\n"); 495 continue; 496 } 497 device_set_ivars(child, (void *)(intptr_t)unit); 498 if ((ctlr->ichannels & (1 << unit)) == 0) 499 device_disable(child); 500 } 501 if (ctlr->caps & AHCI_CAP_EMS) { 502 child = device_add_child(dev, "ahciem", -1); 503 if (child == NULL) 504 device_printf(dev, "failed to add enclosure device\n"); 505 else 506 device_set_ivars(child, (void *)(intptr_t)-1); 507 } 508 bus_generic_attach(dev); 509 return 0; 510 } 511 512 static int 513 ahci_detach(device_t dev) 514 { 515 struct ahci_controller *ctlr = device_get_softc(dev); 516 int i; 517 518 /* Detach & delete all children */ 519 device_delete_children(dev); 520 521 /* Free interrupts. */ 522 for (i = 0; i < ctlr->numirqs; i++) { 523 if (ctlr->irqs[i].r_irq) { 524 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 525 ctlr->irqs[i].handle); 526 bus_release_resource(dev, SYS_RES_IRQ, 527 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 528 } 529 } 530 pci_release_msi(dev); 531 /* Free memory. */ 532 rman_fini(&ctlr->sc_iomem); 533 if (ctlr->r_mem) 534 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 535 return (0); 536 } 537 538 static int 539 ahci_ctlr_reset(device_t dev) 540 { 541 struct ahci_controller *ctlr = device_get_softc(dev); 542 int timeout; 543 544 if (pci_read_config(dev, 0x00, 4) == 0x28298086 && 545 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 546 pci_write_config(dev, 0x92, 0x01, 1); 547 /* Enable AHCI mode */ 548 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 549 /* Reset AHCI controller */ 550 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 551 for (timeout = 1000; timeout > 0; timeout--) { 552 DELAY(1000); 553 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 554 break; 555 } 556 if (timeout == 0) { 557 device_printf(dev, "AHCI controller reset failure\n"); 558 return ENXIO; 559 } 560 /* Reenable AHCI mode */ 561 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 562 return (0); 563 } 564 565 static int 566 ahci_ctlr_setup(device_t dev) 567 { 568 struct ahci_controller *ctlr = device_get_softc(dev); 569 /* Clear interrupts */ 570 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 571 /* Configure CCC */ 572 if (ctlr->ccc) { 573 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 574 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 575 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 576 (4 << AHCI_CCCC_CC_SHIFT) | 577 AHCI_CCCC_EN); 578 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 579 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 580 if (bootverbose) { 581 device_printf(dev, 582 "CCC with %dms/4cmd enabled on vector %d\n", 583 ctlr->ccc, ctlr->cccv); 584 } 585 } 586 /* Enable AHCI interrupts */ 587 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 588 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 589 return (0); 590 } 591 592 static int 593 ahci_suspend(device_t dev) 594 { 595 struct ahci_controller *ctlr = device_get_softc(dev); 596 597 bus_generic_suspend(dev); 598 /* Disable interupts, so the state change(s) doesn't trigger */ 599 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 600 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 601 return 0; 602 } 603 604 static int 605 ahci_resume(device_t dev) 606 { 607 int res; 608 609 if ((res = ahci_ctlr_reset(dev)) != 0) 610 return (res); 611 ahci_ctlr_setup(dev); 612 return (bus_generic_resume(dev)); 613 } 614 615 static int 616 ahci_setup_interrupt(device_t dev) 617 { 618 struct ahci_controller *ctlr = device_get_softc(dev); 619 int i, msi = 1; 620 621 /* Process hints. */ 622 resource_int_value(device_get_name(dev), 623 device_get_unit(dev), "msi", &msi); 624 if (msi < 0) 625 msi = 0; 626 else if (msi == 1) 627 msi = min(1, pci_msi_count(dev)); 628 else if (msi > 1) 629 msi = pci_msi_count(dev); 630 /* Allocate MSI if needed/present. */ 631 if (msi && pci_alloc_msi(dev, &msi) == 0) { 632 ctlr->numirqs = msi; 633 } else { 634 msi = 0; 635 ctlr->numirqs = 1; 636 } 637 /* Check for single MSI vector fallback. */ 638 if (ctlr->numirqs > 1 && 639 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 640 device_printf(dev, "Falling back to one MSI\n"); 641 ctlr->numirqs = 1; 642 } 643 /* Allocate all IRQs. */ 644 for (i = 0; i < ctlr->numirqs; i++) { 645 ctlr->irqs[i].ctlr = ctlr; 646 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0); 647 if (ctlr->numirqs == 1 || i >= ctlr->channels || 648 (ctlr->ccc && i == ctlr->cccv)) 649 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 650 else if (i == ctlr->numirqs - 1) 651 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 652 else 653 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 654 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 655 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 656 device_printf(dev, "unable to map interrupt\n"); 657 return ENXIO; 658 } 659 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 660 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr, 661 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 662 /* SOS XXX release r_irq */ 663 device_printf(dev, "unable to setup interrupt\n"); 664 return ENXIO; 665 } 666 if (ctlr->numirqs > 1) { 667 bus_describe_intr(dev, ctlr->irqs[i].r_irq, 668 ctlr->irqs[i].handle, 669 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 670 "ch%d" : "%d", i); 671 } 672 } 673 return (0); 674 } 675 676 /* 677 * Common case interrupt handler. 678 */ 679 static void 680 ahci_intr(void *data) 681 { 682 struct ahci_controller_irq *irq = data; 683 struct ahci_controller *ctlr = irq->ctlr; 684 u_int32_t is, ise = 0; 685 void *arg; 686 int unit; 687 688 if (irq->mode == AHCI_IRQ_MODE_ALL) { 689 unit = 0; 690 if (ctlr->ccc) 691 is = ctlr->ichannels; 692 else 693 is = ATA_INL(ctlr->r_mem, AHCI_IS); 694 } else { /* AHCI_IRQ_MODE_AFTER */ 695 unit = irq->r_irq_rid - 1; 696 is = ATA_INL(ctlr->r_mem, AHCI_IS); 697 } 698 /* CCC interrupt is edge triggered. */ 699 if (ctlr->ccc) 700 ise = 1 << ctlr->cccv; 701 /* Some controllers have edge triggered IS. */ 702 if (ctlr->quirks & AHCI_Q_EDGEIS) 703 ise |= is; 704 if (ise != 0) 705 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 706 for (; unit < ctlr->channels; unit++) { 707 if ((is & (1 << unit)) != 0 && 708 (arg = ctlr->interrupt[unit].argument)) { 709 ctlr->interrupt[unit].function(arg); 710 } 711 } 712 /* AHCI declares level triggered IS. */ 713 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 714 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 715 } 716 717 /* 718 * Simplified interrupt handler for multivector MSI mode. 719 */ 720 static void 721 ahci_intr_one(void *data) 722 { 723 struct ahci_controller_irq *irq = data; 724 struct ahci_controller *ctlr = irq->ctlr; 725 void *arg; 726 int unit; 727 728 unit = irq->r_irq_rid - 1; 729 /* Some controllers have edge triggered IS. */ 730 if (ctlr->quirks & AHCI_Q_EDGEIS) 731 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 732 if ((arg = ctlr->interrupt[unit].argument)) 733 ctlr->interrupt[unit].function(arg); 734 /* AHCI declares level triggered IS. */ 735 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 736 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 737 } 738 739 static struct resource * 740 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 741 u_long start, u_long end, u_long count, u_int flags) 742 { 743 struct ahci_controller *ctlr = device_get_softc(dev); 744 struct resource *res; 745 long st; 746 int offset, size, unit; 747 748 unit = (intptr_t)device_get_ivars(child); 749 res = NULL; 750 switch (type) { 751 case SYS_RES_MEMORY: 752 if (unit >= 0) { 753 offset = AHCI_OFFSET + (unit << 7); 754 size = 128; 755 } else if (*rid == 0) { 756 offset = AHCI_EM_CTL; 757 size = 4; 758 } else { 759 offset = (ctlr->emloc & 0xffff0000) >> 14; 760 size = (ctlr->emloc & 0x0000ffff) << 2; 761 if (*rid != 1) { 762 if (*rid == 2 && (ctlr->capsem & 763 (AHCI_EM_XMT | AHCI_EM_SMB)) == 0) 764 offset += size; 765 else 766 break; 767 } 768 } 769 st = rman_get_start(ctlr->r_mem); 770 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 771 st + offset + size - 1, size, RF_ACTIVE, child); 772 if (res) { 773 bus_space_handle_t bsh; 774 bus_space_tag_t bst; 775 bsh = rman_get_bushandle(ctlr->r_mem); 776 bst = rman_get_bustag(ctlr->r_mem); 777 bus_space_subregion(bst, bsh, offset, 128, &bsh); 778 rman_set_bushandle(res, bsh); 779 rman_set_bustag(res, bst); 780 } 781 break; 782 case SYS_RES_IRQ: 783 if (*rid == ATA_IRQ_RID) 784 res = ctlr->irqs[0].r_irq; 785 break; 786 } 787 return (res); 788 } 789 790 static int 791 ahci_release_resource(device_t dev, device_t child, int type, int rid, 792 struct resource *r) 793 { 794 795 switch (type) { 796 case SYS_RES_MEMORY: 797 rman_release_resource(r); 798 return (0); 799 case SYS_RES_IRQ: 800 if (rid != ATA_IRQ_RID) 801 return ENOENT; 802 return (0); 803 } 804 return (EINVAL); 805 } 806 807 static int 808 ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 809 int flags, driver_filter_t *filter, driver_intr_t *function, 810 void *argument, void **cookiep) 811 { 812 struct ahci_controller *ctlr = device_get_softc(dev); 813 int unit = (intptr_t)device_get_ivars(child); 814 815 if (filter != NULL) { 816 printf("ahci.c: we cannot use a filter here\n"); 817 return (EINVAL); 818 } 819 ctlr->interrupt[unit].function = function; 820 ctlr->interrupt[unit].argument = argument; 821 return (0); 822 } 823 824 static int 825 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 826 void *cookie) 827 { 828 struct ahci_controller *ctlr = device_get_softc(dev); 829 int unit = (intptr_t)device_get_ivars(child); 830 831 ctlr->interrupt[unit].function = NULL; 832 ctlr->interrupt[unit].argument = NULL; 833 return (0); 834 } 835 836 static int 837 ahci_print_child(device_t dev, device_t child) 838 { 839 int retval, channel; 840 841 retval = bus_print_child_header(dev, child); 842 channel = (int)(intptr_t)device_get_ivars(child); 843 if (channel >= 0) 844 retval += printf(" at channel %d", channel); 845 retval += bus_print_child_footer(dev, child); 846 return (retval); 847 } 848 849 static int 850 ahci_child_location_str(device_t dev, device_t child, char *buf, 851 size_t buflen) 852 { 853 int channel; 854 855 channel = (int)(intptr_t)device_get_ivars(child); 856 if (channel >= 0) 857 snprintf(buf, buflen, "channel=%d", channel); 858 return (0); 859 } 860 861 devclass_t ahci_devclass; 862 static device_method_t ahci_methods[] = { 863 DEVMETHOD(device_probe, ahci_probe), 864 DEVMETHOD(device_attach, ahci_attach), 865 DEVMETHOD(device_detach, ahci_detach), 866 DEVMETHOD(device_suspend, ahci_suspend), 867 DEVMETHOD(device_resume, ahci_resume), 868 DEVMETHOD(bus_print_child, ahci_print_child), 869 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 870 DEVMETHOD(bus_release_resource, ahci_release_resource), 871 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 872 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 873 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 874 { 0, 0 } 875 }; 876 static driver_t ahci_driver = { 877 "ahci", 878 ahci_methods, 879 sizeof(struct ahci_controller) 880 }; 881 DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 882 static device_method_t ahci_ata_methods[] = { 883 DEVMETHOD(device_probe, ahci_ata_probe), 884 DEVMETHOD(device_attach, ahci_attach), 885 DEVMETHOD(device_detach, ahci_detach), 886 DEVMETHOD(device_suspend, ahci_suspend), 887 DEVMETHOD(device_resume, ahci_resume), 888 DEVMETHOD(bus_print_child, ahci_print_child), 889 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 890 DEVMETHOD(bus_release_resource, ahci_release_resource), 891 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 892 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 893 DEVMETHOD(bus_child_location_str, ahci_child_location_str), 894 { 0, 0 } 895 }; 896 static driver_t ahci_ata_driver = { 897 "ahci", 898 ahci_ata_methods, 899 sizeof(struct ahci_controller) 900 }; 901 DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0); 902 MODULE_VERSION(ahci, 1); 903 MODULE_DEPEND(ahci, cam, 1, 1, 1); 904 905 static int 906 ahci_ch_probe(device_t dev) 907 { 908 909 device_set_desc_copy(dev, "AHCI channel"); 910 return (0); 911 } 912 913 static int 914 ahci_ch_attach(device_t dev) 915 { 916 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 917 struct ahci_channel *ch = device_get_softc(dev); 918 struct cam_devq *devq; 919 int rid, error, i, sata_rev = 0; 920 u_int32_t version; 921 922 ch->dev = dev; 923 ch->unit = (intptr_t)device_get_ivars(dev); 924 ch->caps = ctlr->caps; 925 ch->caps2 = ctlr->caps2; 926 ch->quirks = ctlr->quirks; 927 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1; 928 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 929 resource_int_value(device_get_name(dev), 930 device_get_unit(dev), "pm_level", &ch->pm_level); 931 if (ch->pm_level > 3) 932 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 933 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0); 934 /* Limit speed for my onboard JMicron external port. 935 * It is not eSATA really. */ 936 if (pci_get_devid(ctlr->dev) == 0x2363197b && 937 pci_get_subvendor(ctlr->dev) == 0x1043 && 938 pci_get_subdevice(ctlr->dev) == 0x81e4 && 939 ch->unit == 0) 940 sata_rev = 1; 941 if (ch->quirks & AHCI_Q_SATA2) 942 sata_rev = 2; 943 resource_int_value(device_get_name(dev), 944 device_get_unit(dev), "sata_rev", &sata_rev); 945 for (i = 0; i < 16; i++) { 946 ch->user[i].revision = sata_rev; 947 ch->user[i].mode = 0; 948 ch->user[i].bytecount = 8192; 949 ch->user[i].tags = ch->numslots; 950 ch->user[i].caps = 0; 951 ch->curr[i] = ch->user[i]; 952 if (ch->pm_level) { 953 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 954 CTS_SATA_CAPS_H_APST | 955 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 956 } 957 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA | 958 CTS_SATA_CAPS_H_AN; 959 } 960 rid = 0; 961 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 962 &rid, RF_ACTIVE))) 963 return (ENXIO); 964 ahci_dmainit(dev); 965 ahci_slotsalloc(dev); 966 ahci_ch_init(dev); 967 mtx_lock(&ch->mtx); 968 rid = ATA_IRQ_RID; 969 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 970 &rid, RF_SHAREABLE | RF_ACTIVE))) { 971 device_printf(dev, "Unable to map interrupt\n"); 972 error = ENXIO; 973 goto err0; 974 } 975 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 976 ahci_ch_intr_locked, dev, &ch->ih))) { 977 device_printf(dev, "Unable to setup interrupt\n"); 978 error = ENXIO; 979 goto err1; 980 } 981 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 982 version = ATA_INL(ctlr->r_mem, AHCI_VS); 983 if (version < 0x00010020 && (ctlr->caps & AHCI_CAP_FBSS)) 984 ch->chcaps |= AHCI_P_CMD_FBSCP; 985 if (bootverbose) { 986 device_printf(dev, "Caps:%s%s%s%s%s\n", 987 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 988 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 989 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 990 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 991 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":""); 992 } 993 /* Create the device queue for our SIM. */ 994 devq = cam_simq_alloc(ch->numslots); 995 if (devq == NULL) { 996 device_printf(dev, "Unable to allocate simq\n"); 997 error = ENOMEM; 998 goto err1; 999 } 1000 /* Construct SIM entry */ 1001 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 1002 device_get_unit(dev), &ch->mtx, 1003 min(2, ch->numslots), 1004 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 1005 devq); 1006 if (ch->sim == NULL) { 1007 cam_simq_free(devq); 1008 device_printf(dev, "unable to allocate sim\n"); 1009 error = ENOMEM; 1010 goto err1; 1011 } 1012 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 1013 device_printf(dev, "unable to register xpt bus\n"); 1014 error = ENXIO; 1015 goto err2; 1016 } 1017 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 1018 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1019 device_printf(dev, "unable to create path\n"); 1020 error = ENXIO; 1021 goto err3; 1022 } 1023 if (ch->pm_level > 3) { 1024 callout_reset(&ch->pm_timer, 1025 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 1026 ahci_ch_pm, dev); 1027 } 1028 mtx_unlock(&ch->mtx); 1029 return (0); 1030 1031 err3: 1032 xpt_bus_deregister(cam_sim_path(ch->sim)); 1033 err2: 1034 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1035 err1: 1036 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1037 err0: 1038 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1039 mtx_unlock(&ch->mtx); 1040 mtx_destroy(&ch->mtx); 1041 return (error); 1042 } 1043 1044 static int 1045 ahci_ch_detach(device_t dev) 1046 { 1047 struct ahci_channel *ch = device_get_softc(dev); 1048 1049 mtx_lock(&ch->mtx); 1050 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 1051 /* Forget about reset. */ 1052 if (ch->resetting) { 1053 ch->resetting = 0; 1054 xpt_release_simq(ch->sim, TRUE); 1055 } 1056 xpt_free_path(ch->path); 1057 xpt_bus_deregister(cam_sim_path(ch->sim)); 1058 cam_sim_free(ch->sim, /*free_devq*/TRUE); 1059 mtx_unlock(&ch->mtx); 1060 1061 if (ch->pm_level > 3) 1062 callout_drain(&ch->pm_timer); 1063 callout_drain(&ch->reset_timer); 1064 bus_teardown_intr(dev, ch->r_irq, ch->ih); 1065 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 1066 1067 ahci_ch_deinit(dev); 1068 ahci_slotsfree(dev); 1069 ahci_dmafini(dev); 1070 1071 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 1072 mtx_destroy(&ch->mtx); 1073 return (0); 1074 } 1075 1076 static int 1077 ahci_ch_init(device_t dev) 1078 { 1079 struct ahci_channel *ch = device_get_softc(dev); 1080 uint64_t work; 1081 1082 /* Disable port interrupts */ 1083 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1084 /* Setup work areas */ 1085 work = ch->dma.work_bus + AHCI_CL_OFFSET; 1086 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 1087 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 1088 work = ch->dma.rfis_bus; 1089 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 1090 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 1091 /* Activate the channel and power/spin up device */ 1092 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 1093 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1094 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 1095 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 1096 ahci_start_fr(dev); 1097 ahci_start(dev, 1); 1098 return (0); 1099 } 1100 1101 static int 1102 ahci_ch_deinit(device_t dev) 1103 { 1104 struct ahci_channel *ch = device_get_softc(dev); 1105 1106 /* Disable port interrupts. */ 1107 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1108 /* Reset command register. */ 1109 ahci_stop(dev); 1110 ahci_stop_fr(dev); 1111 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 1112 /* Allow everything, including partial and slumber modes. */ 1113 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 1114 /* Request slumber mode transition and give some time to get there. */ 1115 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 1116 DELAY(100); 1117 /* Disable PHY. */ 1118 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 1119 return (0); 1120 } 1121 1122 static int 1123 ahci_ch_suspend(device_t dev) 1124 { 1125 struct ahci_channel *ch = device_get_softc(dev); 1126 1127 mtx_lock(&ch->mtx); 1128 xpt_freeze_simq(ch->sim, 1); 1129 /* Forget about reset. */ 1130 if (ch->resetting) { 1131 ch->resetting = 0; 1132 callout_stop(&ch->reset_timer); 1133 xpt_release_simq(ch->sim, TRUE); 1134 } 1135 while (ch->oslots) 1136 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100); 1137 ahci_ch_deinit(dev); 1138 mtx_unlock(&ch->mtx); 1139 return (0); 1140 } 1141 1142 static int 1143 ahci_ch_resume(device_t dev) 1144 { 1145 struct ahci_channel *ch = device_get_softc(dev); 1146 1147 mtx_lock(&ch->mtx); 1148 ahci_ch_init(dev); 1149 ahci_reset(dev); 1150 xpt_release_simq(ch->sim, TRUE); 1151 mtx_unlock(&ch->mtx); 1152 return (0); 1153 } 1154 1155 devclass_t ahcich_devclass; 1156 static device_method_t ahcich_methods[] = { 1157 DEVMETHOD(device_probe, ahci_ch_probe), 1158 DEVMETHOD(device_attach, ahci_ch_attach), 1159 DEVMETHOD(device_detach, ahci_ch_detach), 1160 DEVMETHOD(device_suspend, ahci_ch_suspend), 1161 DEVMETHOD(device_resume, ahci_ch_resume), 1162 { 0, 0 } 1163 }; 1164 static driver_t ahcich_driver = { 1165 "ahcich", 1166 ahcich_methods, 1167 sizeof(struct ahci_channel) 1168 }; 1169 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0); 1170 1171 struct ahci_dc_cb_args { 1172 bus_addr_t maddr; 1173 int error; 1174 }; 1175 1176 static void 1177 ahci_dmainit(device_t dev) 1178 { 1179 struct ahci_channel *ch = device_get_softc(dev); 1180 struct ahci_dc_cb_args dcba; 1181 size_t rfsize; 1182 1183 if (ch->caps & AHCI_CAP_64BIT) 1184 ch->dma.max_address = BUS_SPACE_MAXADDR; 1185 else 1186 ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT; 1187 /* Command area. */ 1188 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 1189 ch->dma.max_address, BUS_SPACE_MAXADDR, 1190 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 1191 0, NULL, NULL, &ch->dma.work_tag)) 1192 goto error; 1193 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0, 1194 &ch->dma.work_map)) 1195 goto error; 1196 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 1197 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1198 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1199 goto error; 1200 } 1201 ch->dma.work_bus = dcba.maddr; 1202 /* FIS receive area. */ 1203 if (ch->chcaps & AHCI_P_CMD_FBSCP) 1204 rfsize = 4096; 1205 else 1206 rfsize = 256; 1207 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 1208 ch->dma.max_address, BUS_SPACE_MAXADDR, 1209 NULL, NULL, rfsize, 1, rfsize, 1210 0, NULL, NULL, &ch->dma.rfis_tag)) 1211 goto error; 1212 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 1213 &ch->dma.rfis_map)) 1214 goto error; 1215 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 1216 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1217 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1218 goto error; 1219 } 1220 ch->dma.rfis_bus = dcba.maddr; 1221 /* Data area. */ 1222 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 1223 ch->dma.max_address, BUS_SPACE_MAXADDR, 1224 NULL, NULL, 1225 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 1226 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 1227 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 1228 goto error; 1229 } 1230 return; 1231 1232 error: 1233 device_printf(dev, "WARNING - DMA initialization failed\n"); 1234 ahci_dmafini(dev); 1235 } 1236 1237 static void 1238 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1239 { 1240 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 1241 1242 if (!(dcba->error = error)) 1243 dcba->maddr = segs[0].ds_addr; 1244 } 1245 1246 static void 1247 ahci_dmafini(device_t dev) 1248 { 1249 struct ahci_channel *ch = device_get_softc(dev); 1250 1251 if (ch->dma.data_tag) { 1252 bus_dma_tag_destroy(ch->dma.data_tag); 1253 ch->dma.data_tag = NULL; 1254 } 1255 if (ch->dma.rfis_bus) { 1256 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1257 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1258 ch->dma.rfis_bus = 0; 1259 ch->dma.rfis_map = NULL; 1260 ch->dma.rfis = NULL; 1261 } 1262 if (ch->dma.work_bus) { 1263 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1264 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1265 ch->dma.work_bus = 0; 1266 ch->dma.work_map = NULL; 1267 ch->dma.work = NULL; 1268 } 1269 if (ch->dma.work_tag) { 1270 bus_dma_tag_destroy(ch->dma.work_tag); 1271 ch->dma.work_tag = NULL; 1272 } 1273 } 1274 1275 static void 1276 ahci_slotsalloc(device_t dev) 1277 { 1278 struct ahci_channel *ch = device_get_softc(dev); 1279 int i; 1280 1281 /* Alloc and setup command/dma slots */ 1282 bzero(ch->slot, sizeof(ch->slot)); 1283 for (i = 0; i < ch->numslots; i++) { 1284 struct ahci_slot *slot = &ch->slot[i]; 1285 1286 slot->dev = dev; 1287 slot->slot = i; 1288 slot->state = AHCI_SLOT_EMPTY; 1289 slot->ccb = NULL; 1290 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1291 1292 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1293 device_printf(ch->dev, "FAILURE - create data_map\n"); 1294 } 1295 } 1296 1297 static void 1298 ahci_slotsfree(device_t dev) 1299 { 1300 struct ahci_channel *ch = device_get_softc(dev); 1301 int i; 1302 1303 /* Free all dma slots */ 1304 for (i = 0; i < ch->numslots; i++) { 1305 struct ahci_slot *slot = &ch->slot[i]; 1306 1307 callout_drain(&slot->timeout); 1308 if (slot->dma.data_map) { 1309 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1310 slot->dma.data_map = NULL; 1311 } 1312 } 1313 } 1314 1315 static int 1316 ahci_phy_check_events(device_t dev, u_int32_t serr) 1317 { 1318 struct ahci_channel *ch = device_get_softc(dev); 1319 1320 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) || 1321 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) { 1322 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1323 union ccb *ccb; 1324 1325 if (bootverbose) { 1326 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 1327 device_printf(dev, "CONNECT requested\n"); 1328 else 1329 device_printf(dev, "DISCONNECT requested\n"); 1330 } 1331 ahci_reset(dev); 1332 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1333 return (0); 1334 if (xpt_create_path(&ccb->ccb_h.path, NULL, 1335 cam_sim_path(ch->sim), 1336 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1337 xpt_free_ccb(ccb); 1338 return (0); 1339 } 1340 xpt_rescan(ccb); 1341 return (1); 1342 } 1343 return (0); 1344 } 1345 1346 static void 1347 ahci_cpd_check_events(device_t dev) 1348 { 1349 struct ahci_channel *ch = device_get_softc(dev); 1350 u_int32_t status; 1351 union ccb *ccb; 1352 1353 if (ch->pm_level == 0) 1354 return; 1355 1356 status = ATA_INL(ch->r_mem, AHCI_P_CMD); 1357 if ((status & AHCI_P_CMD_CPD) == 0) 1358 return; 1359 1360 if (bootverbose) { 1361 if (status & AHCI_P_CMD_CPS) { 1362 device_printf(dev, "COLD CONNECT requested\n"); 1363 } else 1364 device_printf(dev, "COLD DISCONNECT requested\n"); 1365 } 1366 ahci_reset(dev); 1367 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1368 return; 1369 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim), 1370 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1371 xpt_free_ccb(ccb); 1372 return; 1373 } 1374 xpt_rescan(ccb); 1375 } 1376 1377 static void 1378 ahci_notify_events(device_t dev, u_int32_t status) 1379 { 1380 struct ahci_channel *ch = device_get_softc(dev); 1381 struct cam_path *dpath; 1382 int i; 1383 1384 if (ch->caps & AHCI_CAP_SSNTF) 1385 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1386 if (bootverbose) 1387 device_printf(dev, "SNTF 0x%04x\n", status); 1388 for (i = 0; i < 16; i++) { 1389 if ((status & (1 << i)) == 0) 1390 continue; 1391 if (xpt_create_path(&dpath, NULL, 1392 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1393 xpt_async(AC_SCSI_AEN, dpath, NULL); 1394 xpt_free_path(dpath); 1395 } 1396 } 1397 } 1398 1399 static void 1400 ahci_ch_intr_locked(void *data) 1401 { 1402 device_t dev = (device_t)data; 1403 struct ahci_channel *ch = device_get_softc(dev); 1404 1405 mtx_lock(&ch->mtx); 1406 xpt_batch_start(ch->sim); 1407 ahci_ch_intr(data); 1408 xpt_batch_done(ch->sim); 1409 mtx_unlock(&ch->mtx); 1410 } 1411 1412 static void 1413 ahci_ch_pm(void *arg) 1414 { 1415 device_t dev = (device_t)arg; 1416 struct ahci_channel *ch = device_get_softc(dev); 1417 uint32_t work; 1418 1419 if (ch->numrslots != 0) 1420 return; 1421 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1422 if (ch->pm_level == 4) 1423 work |= AHCI_P_CMD_PARTIAL; 1424 else 1425 work |= AHCI_P_CMD_SLUMBER; 1426 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1427 } 1428 1429 static void 1430 ahci_ch_intr(void *data) 1431 { 1432 device_t dev = (device_t)data; 1433 struct ahci_channel *ch = device_get_softc(dev); 1434 uint32_t istatus, sstatus, cstatus, serr = 0, sntf = 0, ok, err; 1435 enum ahci_err_type et; 1436 int i, ccs, port, reset = 0; 1437 1438 /* Read and clear interrupt statuses. */ 1439 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1440 if (istatus == 0) 1441 return; 1442 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1443 /* Read command statuses. */ 1444 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1445 cstatus = ATA_INL(ch->r_mem, AHCI_P_CI); 1446 if (istatus & AHCI_P_IX_SDB) { 1447 if (ch->caps & AHCI_CAP_SSNTF) 1448 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1449 else if (ch->fbs_enabled) { 1450 u_int8_t *fis = ch->dma.rfis + 0x58; 1451 1452 for (i = 0; i < 16; i++) { 1453 if (fis[1] & 0x80) { 1454 fis[1] &= 0x7f; 1455 sntf |= 1 << i; 1456 } 1457 fis += 256; 1458 } 1459 } else { 1460 u_int8_t *fis = ch->dma.rfis + 0x58; 1461 1462 if (fis[1] & 0x80) 1463 sntf = (1 << (fis[1] & 0x0f)); 1464 } 1465 } 1466 /* Process PHY events */ 1467 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1468 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1469 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1470 if (serr) { 1471 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1472 reset = ahci_phy_check_events(dev, serr); 1473 } 1474 } 1475 /* Process cold presence detection events */ 1476 if ((istatus & AHCI_P_IX_CPD) && !reset) 1477 ahci_cpd_check_events(dev); 1478 /* Process command errors */ 1479 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1480 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1481 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1482 >> AHCI_P_CMD_CCS_SHIFT; 1483 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1484 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1485 // serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1486 port = -1; 1487 if (ch->fbs_enabled) { 1488 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1489 if (fbs & AHCI_P_FBS_SDE) { 1490 port = (fbs & AHCI_P_FBS_DWE) 1491 >> AHCI_P_FBS_DWE_SHIFT; 1492 } else { 1493 for (i = 0; i < 16; i++) { 1494 if (ch->numrslotspd[i] == 0) 1495 continue; 1496 if (port == -1) 1497 port = i; 1498 else if (port != i) { 1499 port = -2; 1500 break; 1501 } 1502 } 1503 } 1504 } 1505 err = ch->rslots & (cstatus | sstatus); 1506 } else { 1507 ccs = 0; 1508 err = 0; 1509 port = -1; 1510 } 1511 /* Complete all successfull commands. */ 1512 ok = ch->rslots & ~(cstatus | sstatus); 1513 for (i = 0; i < ch->numslots; i++) { 1514 if ((ok >> i) & 1) 1515 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1516 } 1517 /* On error, complete the rest of commands with error statuses. */ 1518 if (err) { 1519 if (ch->frozen) { 1520 union ccb *fccb = ch->frozen; 1521 ch->frozen = NULL; 1522 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1523 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1524 xpt_freeze_devq(fccb->ccb_h.path, 1); 1525 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1526 } 1527 xpt_done(fccb); 1528 } 1529 for (i = 0; i < ch->numslots; i++) { 1530 /* XXX: reqests in loading state. */ 1531 if (((err >> i) & 1) == 0) 1532 continue; 1533 if (port >= 0 && 1534 ch->slot[i].ccb->ccb_h.target_id != port) 1535 continue; 1536 if (istatus & AHCI_P_IX_TFE) { 1537 if (port != -2) { 1538 /* Task File Error */ 1539 if (ch->numtslotspd[ 1540 ch->slot[i].ccb->ccb_h.target_id] == 0) { 1541 /* Untagged operation. */ 1542 if (i == ccs) 1543 et = AHCI_ERR_TFE; 1544 else 1545 et = AHCI_ERR_INNOCENT; 1546 } else { 1547 /* Tagged operation. */ 1548 et = AHCI_ERR_NCQ; 1549 } 1550 } else { 1551 et = AHCI_ERR_TFE; 1552 ch->fatalerr = 1; 1553 } 1554 } else if (istatus & AHCI_P_IX_IF) { 1555 if (ch->numtslots == 0 && i != ccs && port != -2) 1556 et = AHCI_ERR_INNOCENT; 1557 else 1558 et = AHCI_ERR_SATA; 1559 } else 1560 et = AHCI_ERR_INVALID; 1561 ahci_end_transaction(&ch->slot[i], et); 1562 } 1563 /* 1564 * We can't reinit port if there are some other 1565 * commands active, use resume to complete them. 1566 */ 1567 if (ch->rslots != 0 && !ch->recoverycmd) 1568 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1569 } 1570 /* Process NOTIFY events */ 1571 if (sntf) 1572 ahci_notify_events(dev, sntf); 1573 } 1574 1575 /* Must be called with channel locked. */ 1576 static int 1577 ahci_check_collision(device_t dev, union ccb *ccb) 1578 { 1579 struct ahci_channel *ch = device_get_softc(dev); 1580 int t = ccb->ccb_h.target_id; 1581 1582 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1583 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1584 /* Tagged command while we have no supported tag free. */ 1585 if (((~ch->oslots) & (0xffffffff >> (32 - 1586 ch->curr[t].tags))) == 0) 1587 return (1); 1588 /* If we have FBS */ 1589 if (ch->fbs_enabled) { 1590 /* Tagged command while untagged are active. */ 1591 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1592 return (1); 1593 } else { 1594 /* Tagged command while untagged are active. */ 1595 if (ch->numrslots != 0 && ch->numtslots == 0) 1596 return (1); 1597 /* Tagged command while tagged to other target is active. */ 1598 if (ch->numtslots != 0 && 1599 ch->taggedtarget != ccb->ccb_h.target_id) 1600 return (1); 1601 } 1602 } else { 1603 /* If we have FBS */ 1604 if (ch->fbs_enabled) { 1605 /* Untagged command while tagged are active. */ 1606 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1607 return (1); 1608 } else { 1609 /* Untagged command while tagged are active. */ 1610 if (ch->numrslots != 0 && ch->numtslots != 0) 1611 return (1); 1612 } 1613 } 1614 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1615 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1616 /* Atomic command while anything active. */ 1617 if (ch->numrslots != 0) 1618 return (1); 1619 } 1620 /* We have some atomic command running. */ 1621 if (ch->aslots != 0) 1622 return (1); 1623 return (0); 1624 } 1625 1626 /* Must be called with channel locked. */ 1627 static void 1628 ahci_begin_transaction(device_t dev, union ccb *ccb) 1629 { 1630 struct ahci_channel *ch = device_get_softc(dev); 1631 struct ahci_slot *slot; 1632 int tag, tags; 1633 1634 /* Choose empty slot. */ 1635 tags = ch->numslots; 1636 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1637 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1638 tags = ch->curr[ccb->ccb_h.target_id].tags; 1639 tag = ch->lastslot; 1640 while (1) { 1641 if (tag >= tags) 1642 tag = 0; 1643 if (ch->slot[tag].state == AHCI_SLOT_EMPTY) 1644 break; 1645 tag++; 1646 }; 1647 ch->lastslot = tag; 1648 /* Occupy chosen slot. */ 1649 slot = &ch->slot[tag]; 1650 slot->ccb = ccb; 1651 /* Stop PM timer. */ 1652 if (ch->numrslots == 0 && ch->pm_level > 3) 1653 callout_stop(&ch->pm_timer); 1654 /* Update channel stats. */ 1655 ch->oslots |= (1 << slot->slot); 1656 ch->numrslots++; 1657 ch->numrslotspd[ccb->ccb_h.target_id]++; 1658 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1659 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1660 ch->numtslots++; 1661 ch->numtslotspd[ccb->ccb_h.target_id]++; 1662 ch->taggedtarget = ccb->ccb_h.target_id; 1663 } 1664 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1665 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1666 ch->aslots |= (1 << slot->slot); 1667 slot->dma.nsegs = 0; 1668 /* If request moves data, setup and load SG list */ 1669 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1670 void *buf; 1671 bus_size_t size; 1672 1673 slot->state = AHCI_SLOT_LOADING; 1674 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1675 buf = ccb->ataio.data_ptr; 1676 size = ccb->ataio.dxfer_len; 1677 } else { 1678 buf = ccb->csio.data_ptr; 1679 size = ccb->csio.dxfer_len; 1680 } 1681 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map, 1682 buf, size, ahci_dmasetprd, slot, 0); 1683 } else 1684 ahci_execute_transaction(slot); 1685 } 1686 1687 /* Locked by busdma engine. */ 1688 static void 1689 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1690 { 1691 struct ahci_slot *slot = arg; 1692 struct ahci_channel *ch = device_get_softc(slot->dev); 1693 struct ahci_cmd_tab *ctp; 1694 struct ahci_dma_prd *prd; 1695 int i; 1696 1697 if (error) { 1698 device_printf(slot->dev, "DMA load error\n"); 1699 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1700 return; 1701 } 1702 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1703 /* Get a piece of the workspace for this request */ 1704 ctp = (struct ahci_cmd_tab *) 1705 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1706 /* Fill S/G table */ 1707 prd = &ctp->prd_tab[0]; 1708 for (i = 0; i < nsegs; i++) { 1709 prd[i].dba = htole64(segs[i].ds_addr); 1710 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1711 } 1712 slot->dma.nsegs = nsegs; 1713 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1714 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1715 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1716 ahci_execute_transaction(slot); 1717 } 1718 1719 /* Must be called with channel locked. */ 1720 static void 1721 ahci_execute_transaction(struct ahci_slot *slot) 1722 { 1723 device_t dev = slot->dev; 1724 struct ahci_channel *ch = device_get_softc(dev); 1725 struct ahci_cmd_tab *ctp; 1726 struct ahci_cmd_list *clp; 1727 union ccb *ccb = slot->ccb; 1728 int port = ccb->ccb_h.target_id & 0x0f; 1729 int fis_size, i, softreset; 1730 uint8_t *fis = ch->dma.rfis + 0x40; 1731 uint8_t val; 1732 1733 /* Get a piece of the workspace for this request */ 1734 ctp = (struct ahci_cmd_tab *) 1735 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1736 /* Setup the FIS for this request */ 1737 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) { 1738 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1739 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1740 return; 1741 } 1742 /* Setup the command list entry */ 1743 clp = (struct ahci_cmd_list *) 1744 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1745 clp->cmd_flags = htole16( 1746 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1747 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1748 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1749 (fis_size / sizeof(u_int32_t)) | 1750 (port << 12)); 1751 clp->prd_length = htole16(slot->dma.nsegs); 1752 /* Special handling for Soft Reset command. */ 1753 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1754 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1755 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1756 softreset = 1; 1757 /* Kick controller into sane state */ 1758 ahci_stop(dev); 1759 ahci_clo(dev); 1760 ahci_start(dev, 0); 1761 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1762 } else { 1763 softreset = 2; 1764 /* Prepare FIS receive area for check. */ 1765 for (i = 0; i < 20; i++) 1766 fis[i] = 0xff; 1767 } 1768 } else 1769 softreset = 0; 1770 clp->bytecount = 0; 1771 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1772 (AHCI_CT_SIZE * slot->slot)); 1773 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1774 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1775 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1776 BUS_DMASYNC_PREREAD); 1777 /* Set ACTIVE bit for NCQ commands. */ 1778 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1779 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1780 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1781 } 1782 /* If FBS is enabled, set PMP port. */ 1783 if (ch->fbs_enabled) { 1784 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1785 (port << AHCI_P_FBS_DEV_SHIFT)); 1786 } 1787 /* Issue command to the controller. */ 1788 slot->state = AHCI_SLOT_RUNNING; 1789 ch->rslots |= (1 << slot->slot); 1790 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1791 /* Device reset commands doesn't interrupt. Poll them. */ 1792 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1793 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) { 1794 int count, timeout = ccb->ccb_h.timeout * 100; 1795 enum ahci_err_type et = AHCI_ERR_NONE; 1796 1797 for (count = 0; count < timeout; count++) { 1798 DELAY(10); 1799 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1800 break; 1801 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) && 1802 softreset != 1) { 1803 #if 0 1804 device_printf(ch->dev, 1805 "Poll error on slot %d, TFD: %04x\n", 1806 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1807 #endif 1808 et = AHCI_ERR_TFE; 1809 break; 1810 } 1811 /* Workaround for ATI SB600/SB700 chipsets. */ 1812 if (ccb->ccb_h.target_id == 15 && 1813 pci_get_vendor(device_get_parent(dev)) == 0x1002 && 1814 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1815 et = AHCI_ERR_TIMEOUT; 1816 break; 1817 } 1818 } 1819 1820 /* Marvell controllers do not wait for readyness. */ 1821 if ((ch->quirks & AHCI_Q_NOBSYRES) && softreset == 2 && 1822 et == AHCI_ERR_NONE) { 1823 while ((val = fis[2]) & ATA_S_BUSY) { 1824 DELAY(10); 1825 if (count++ >= timeout) 1826 break; 1827 } 1828 } 1829 1830 if (timeout && (count >= timeout)) { 1831 device_printf(dev, "Poll timeout on slot %d port %d\n", 1832 slot->slot, port); 1833 device_printf(dev, "is %08x cs %08x ss %08x " 1834 "rs %08x tfd %02x serr %08x cmd %08x\n", 1835 ATA_INL(ch->r_mem, AHCI_P_IS), 1836 ATA_INL(ch->r_mem, AHCI_P_CI), 1837 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1838 ATA_INL(ch->r_mem, AHCI_P_TFD), 1839 ATA_INL(ch->r_mem, AHCI_P_SERR), 1840 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1841 et = AHCI_ERR_TIMEOUT; 1842 } 1843 1844 /* Kick controller into sane state and enable FBS. */ 1845 if (softreset == 2) 1846 ch->eslots |= (1 << slot->slot); 1847 ahci_end_transaction(slot, et); 1848 return; 1849 } 1850 /* Start command execution timeout */ 1851 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 1852 (timeout_t*)ahci_timeout, slot); 1853 return; 1854 } 1855 1856 /* Must be called with channel locked. */ 1857 static void 1858 ahci_process_timeout(device_t dev) 1859 { 1860 struct ahci_channel *ch = device_get_softc(dev); 1861 int i; 1862 1863 mtx_assert(&ch->mtx, MA_OWNED); 1864 /* Handle the rest of commands. */ 1865 for (i = 0; i < ch->numslots; i++) { 1866 /* Do we have a running request on slot? */ 1867 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1868 continue; 1869 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 1870 } 1871 } 1872 1873 /* Must be called with channel locked. */ 1874 static void 1875 ahci_rearm_timeout(device_t dev) 1876 { 1877 struct ahci_channel *ch = device_get_softc(dev); 1878 int i; 1879 1880 mtx_assert(&ch->mtx, MA_OWNED); 1881 for (i = 0; i < ch->numslots; i++) { 1882 struct ahci_slot *slot = &ch->slot[i]; 1883 1884 /* Do we have a running request on slot? */ 1885 if (slot->state < AHCI_SLOT_RUNNING) 1886 continue; 1887 if ((ch->toslots & (1 << i)) == 0) 1888 continue; 1889 callout_reset(&slot->timeout, 1890 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1891 (timeout_t*)ahci_timeout, slot); 1892 } 1893 } 1894 1895 /* Locked by callout mechanism. */ 1896 static void 1897 ahci_timeout(struct ahci_slot *slot) 1898 { 1899 device_t dev = slot->dev; 1900 struct ahci_channel *ch = device_get_softc(dev); 1901 uint32_t sstatus; 1902 int ccs; 1903 int i; 1904 1905 /* Check for stale timeout. */ 1906 if (slot->state < AHCI_SLOT_RUNNING) 1907 return; 1908 1909 /* Check if slot was not being executed last time we checked. */ 1910 if (slot->state < AHCI_SLOT_EXECUTING) { 1911 /* Check if slot started executing. */ 1912 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1913 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1914 >> AHCI_P_CMD_CCS_SHIFT; 1915 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 1916 ch->fbs_enabled || ch->wrongccs) 1917 slot->state = AHCI_SLOT_EXECUTING; 1918 else if ((ch->rslots & (1 << ccs)) == 0) { 1919 ch->wrongccs = 1; 1920 slot->state = AHCI_SLOT_EXECUTING; 1921 } 1922 1923 callout_reset(&slot->timeout, 1924 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1925 (timeout_t*)ahci_timeout, slot); 1926 return; 1927 } 1928 1929 device_printf(dev, "Timeout on slot %d port %d\n", 1930 slot->slot, slot->ccb->ccb_h.target_id & 0x0f); 1931 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x " 1932 "serr %08x cmd %08x\n", 1933 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 1934 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1935 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR), 1936 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1937 1938 /* Handle frozen command. */ 1939 if (ch->frozen) { 1940 union ccb *fccb = ch->frozen; 1941 ch->frozen = NULL; 1942 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1943 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1944 xpt_freeze_devq(fccb->ccb_h.path, 1); 1945 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1946 } 1947 xpt_done(fccb); 1948 } 1949 if (!ch->fbs_enabled && !ch->wrongccs) { 1950 /* Without FBS we know real timeout source. */ 1951 ch->fatalerr = 1; 1952 /* Handle command with timeout. */ 1953 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 1954 /* Handle the rest of commands. */ 1955 for (i = 0; i < ch->numslots; i++) { 1956 /* Do we have a running request on slot? */ 1957 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1958 continue; 1959 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1960 } 1961 } else { 1962 /* With FBS we wait for other commands timeout and pray. */ 1963 if (ch->toslots == 0) 1964 xpt_freeze_simq(ch->sim, 1); 1965 ch->toslots |= (1 << slot->slot); 1966 if ((ch->rslots & ~ch->toslots) == 0) 1967 ahci_process_timeout(dev); 1968 else 1969 device_printf(dev, " ... waiting for slots %08x\n", 1970 ch->rslots & ~ch->toslots); 1971 } 1972 } 1973 1974 /* Must be called with channel locked. */ 1975 static void 1976 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 1977 { 1978 device_t dev = slot->dev; 1979 struct ahci_channel *ch = device_get_softc(dev); 1980 union ccb *ccb = slot->ccb; 1981 struct ahci_cmd_list *clp; 1982 int lastto; 1983 uint32_t sig; 1984 1985 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1986 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1987 clp = (struct ahci_cmd_list *) 1988 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1989 /* Read result registers to the result struct 1990 * May be incorrect if several commands finished same time, 1991 * so read only when sure or have to. 1992 */ 1993 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1994 struct ata_res *res = &ccb->ataio.res; 1995 1996 if ((et == AHCI_ERR_TFE) || 1997 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1998 u_int8_t *fis = ch->dma.rfis + 0x40; 1999 2000 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 2001 BUS_DMASYNC_POSTREAD); 2002 if (ch->fbs_enabled) { 2003 fis += ccb->ccb_h.target_id * 256; 2004 res->status = fis[2]; 2005 res->error = fis[3]; 2006 } else { 2007 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 2008 2009 res->status = tfd; 2010 res->error = tfd >> 8; 2011 } 2012 res->lba_low = fis[4]; 2013 res->lba_mid = fis[5]; 2014 res->lba_high = fis[6]; 2015 res->device = fis[7]; 2016 res->lba_low_exp = fis[8]; 2017 res->lba_mid_exp = fis[9]; 2018 res->lba_high_exp = fis[10]; 2019 res->sector_count = fis[12]; 2020 res->sector_count_exp = fis[13]; 2021 2022 /* 2023 * Some weird controllers do not return signature in 2024 * FIS receive area. Read it from PxSIG register. 2025 */ 2026 if ((ch->quirks & AHCI_Q_ALTSIG) && 2027 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2028 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 2029 sig = ATA_INL(ch->r_mem, AHCI_P_SIG); 2030 res->lba_high = sig >> 24; 2031 res->lba_mid = sig >> 16; 2032 res->lba_low = sig >> 8; 2033 res->sector_count = sig; 2034 } 2035 } else 2036 bzero(res, sizeof(*res)); 2037 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 2038 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2039 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2040 ccb->ataio.resid = 2041 ccb->ataio.dxfer_len - le32toh(clp->bytecount); 2042 } 2043 } else { 2044 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2045 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2046 ccb->csio.resid = 2047 ccb->csio.dxfer_len - le32toh(clp->bytecount); 2048 } 2049 } 2050 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2051 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 2052 (ccb->ccb_h.flags & CAM_DIR_IN) ? 2053 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2054 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 2055 } 2056 if (et != AHCI_ERR_NONE) 2057 ch->eslots |= (1 << slot->slot); 2058 /* In case of error, freeze device for proper recovery. */ 2059 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) && 2060 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 2061 xpt_freeze_devq(ccb->ccb_h.path, 1); 2062 ccb->ccb_h.status |= CAM_DEV_QFRZN; 2063 } 2064 /* Set proper result status. */ 2065 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2066 switch (et) { 2067 case AHCI_ERR_NONE: 2068 ccb->ccb_h.status |= CAM_REQ_CMP; 2069 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 2070 ccb->csio.scsi_status = SCSI_STATUS_OK; 2071 break; 2072 case AHCI_ERR_INVALID: 2073 ch->fatalerr = 1; 2074 ccb->ccb_h.status |= CAM_REQ_INVALID; 2075 break; 2076 case AHCI_ERR_INNOCENT: 2077 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 2078 break; 2079 case AHCI_ERR_TFE: 2080 case AHCI_ERR_NCQ: 2081 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2082 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2083 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2084 } else { 2085 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 2086 } 2087 break; 2088 case AHCI_ERR_SATA: 2089 ch->fatalerr = 1; 2090 if (!ch->recoverycmd) { 2091 xpt_freeze_simq(ch->sim, 1); 2092 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2093 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2094 } 2095 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 2096 break; 2097 case AHCI_ERR_TIMEOUT: 2098 if (!ch->recoverycmd) { 2099 xpt_freeze_simq(ch->sim, 1); 2100 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2101 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2102 } 2103 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 2104 break; 2105 default: 2106 ch->fatalerr = 1; 2107 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 2108 } 2109 /* Free slot. */ 2110 ch->oslots &= ~(1 << slot->slot); 2111 ch->rslots &= ~(1 << slot->slot); 2112 ch->aslots &= ~(1 << slot->slot); 2113 slot->state = AHCI_SLOT_EMPTY; 2114 slot->ccb = NULL; 2115 /* Update channel stats. */ 2116 ch->numrslots--; 2117 ch->numrslotspd[ccb->ccb_h.target_id]--; 2118 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2119 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 2120 ch->numtslots--; 2121 ch->numtslotspd[ccb->ccb_h.target_id]--; 2122 } 2123 /* Cancel timeout state if request completed normally. */ 2124 if (et != AHCI_ERR_TIMEOUT) { 2125 lastto = (ch->toslots == (1 << slot->slot)); 2126 ch->toslots &= ~(1 << slot->slot); 2127 if (lastto) 2128 xpt_release_simq(ch->sim, TRUE); 2129 } 2130 /* If it was first request of reset sequence and there is no error, 2131 * proceed to second request. */ 2132 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2133 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2134 (ccb->ataio.cmd.control & ATA_A_RESET) && 2135 et == AHCI_ERR_NONE) { 2136 ccb->ataio.cmd.control &= ~ATA_A_RESET; 2137 ahci_begin_transaction(dev, ccb); 2138 return; 2139 } 2140 /* If it was our READ LOG command - process it. */ 2141 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 2142 ahci_process_read_log(dev, ccb); 2143 /* If it was our REQUEST SENSE command - process it. */ 2144 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 2145 ahci_process_request_sense(dev, ccb); 2146 /* If it was NCQ or ATAPI command error, put result on hold. */ 2147 } else if (et == AHCI_ERR_NCQ || 2148 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 2149 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 2150 ch->hold[slot->slot] = ccb; 2151 ch->numhslots++; 2152 } else 2153 xpt_done(ccb); 2154 /* If we have no other active commands, ... */ 2155 if (ch->rslots == 0) { 2156 /* if there was fatal error - reset port. */ 2157 if (ch->toslots != 0 || ch->fatalerr) { 2158 ahci_reset(dev); 2159 } else { 2160 /* if we have slots in error, we can reinit port. */ 2161 if (ch->eslots != 0) { 2162 ahci_stop(dev); 2163 ahci_clo(dev); 2164 ahci_start(dev, 1); 2165 } 2166 /* if there commands on hold, we can do READ LOG. */ 2167 if (!ch->recoverycmd && ch->numhslots) 2168 ahci_issue_recovery(dev); 2169 } 2170 /* If all the rest of commands are in timeout - give them chance. */ 2171 } else if ((ch->rslots & ~ch->toslots) == 0 && 2172 et != AHCI_ERR_TIMEOUT) 2173 ahci_rearm_timeout(dev); 2174 /* Unfreeze frozen command. */ 2175 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) { 2176 union ccb *fccb = ch->frozen; 2177 ch->frozen = NULL; 2178 ahci_begin_transaction(dev, fccb); 2179 xpt_release_simq(ch->sim, TRUE); 2180 } 2181 /* Start PM timer. */ 2182 if (ch->numrslots == 0 && ch->pm_level > 3 && 2183 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 2184 callout_schedule(&ch->pm_timer, 2185 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 2186 } 2187 } 2188 2189 static void 2190 ahci_issue_recovery(device_t dev) 2191 { 2192 struct ahci_channel *ch = device_get_softc(dev); 2193 union ccb *ccb; 2194 struct ccb_ataio *ataio; 2195 struct ccb_scsiio *csio; 2196 int i; 2197 2198 /* Find some held command. */ 2199 for (i = 0; i < ch->numslots; i++) { 2200 if (ch->hold[i]) 2201 break; 2202 } 2203 ccb = xpt_alloc_ccb_nowait(); 2204 if (ccb == NULL) { 2205 device_printf(dev, "Unable to allocate recovery command\n"); 2206 completeall: 2207 /* We can't do anything -- complete held commands. */ 2208 for (i = 0; i < ch->numslots; i++) { 2209 if (ch->hold[i] == NULL) 2210 continue; 2211 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2212 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 2213 xpt_done(ch->hold[i]); 2214 ch->hold[i] = NULL; 2215 ch->numhslots--; 2216 } 2217 ahci_reset(dev); 2218 return; 2219 } 2220 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 2221 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2222 /* READ LOG */ 2223 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 2224 ccb->ccb_h.func_code = XPT_ATA_IO; 2225 ccb->ccb_h.flags = CAM_DIR_IN; 2226 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2227 ataio = &ccb->ataio; 2228 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 2229 if (ataio->data_ptr == NULL) { 2230 xpt_free_ccb(ccb); 2231 device_printf(dev, 2232 "Unable to allocate memory for READ LOG command\n"); 2233 goto completeall; 2234 } 2235 ataio->dxfer_len = 512; 2236 bzero(&ataio->cmd, sizeof(ataio->cmd)); 2237 ataio->cmd.flags = CAM_ATAIO_48BIT; 2238 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 2239 ataio->cmd.sector_count = 1; 2240 ataio->cmd.sector_count_exp = 0; 2241 ataio->cmd.lba_low = 0x10; 2242 ataio->cmd.lba_mid = 0; 2243 ataio->cmd.lba_mid_exp = 0; 2244 } else { 2245 /* REQUEST SENSE */ 2246 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 2247 ccb->ccb_h.recovery_slot = i; 2248 ccb->ccb_h.func_code = XPT_SCSI_IO; 2249 ccb->ccb_h.flags = CAM_DIR_IN; 2250 ccb->ccb_h.status = 0; 2251 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2252 csio = &ccb->csio; 2253 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 2254 csio->dxfer_len = ch->hold[i]->csio.sense_len; 2255 csio->cdb_len = 6; 2256 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 2257 csio->cdb_io.cdb_bytes[0] = 0x03; 2258 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 2259 } 2260 /* Freeze SIM while doing recovery. */ 2261 ch->recoverycmd = 1; 2262 xpt_freeze_simq(ch->sim, 1); 2263 ahci_begin_transaction(dev, ccb); 2264 } 2265 2266 static void 2267 ahci_process_read_log(device_t dev, union ccb *ccb) 2268 { 2269 struct ahci_channel *ch = device_get_softc(dev); 2270 uint8_t *data; 2271 struct ata_res *res; 2272 int i; 2273 2274 ch->recoverycmd = 0; 2275 2276 data = ccb->ataio.data_ptr; 2277 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2278 (data[0] & 0x80) == 0) { 2279 for (i = 0; i < ch->numslots; i++) { 2280 if (!ch->hold[i]) 2281 continue; 2282 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2283 continue; 2284 if ((data[0] & 0x1F) == i) { 2285 res = &ch->hold[i]->ataio.res; 2286 res->status = data[2]; 2287 res->error = data[3]; 2288 res->lba_low = data[4]; 2289 res->lba_mid = data[5]; 2290 res->lba_high = data[6]; 2291 res->device = data[7]; 2292 res->lba_low_exp = data[8]; 2293 res->lba_mid_exp = data[9]; 2294 res->lba_high_exp = data[10]; 2295 res->sector_count = data[12]; 2296 res->sector_count_exp = data[13]; 2297 } else { 2298 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2299 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2300 } 2301 xpt_done(ch->hold[i]); 2302 ch->hold[i] = NULL; 2303 ch->numhslots--; 2304 } 2305 } else { 2306 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2307 device_printf(dev, "Error while READ LOG EXT\n"); 2308 else if ((data[0] & 0x80) == 0) { 2309 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 2310 } 2311 for (i = 0; i < ch->numslots; i++) { 2312 if (!ch->hold[i]) 2313 continue; 2314 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2315 continue; 2316 xpt_done(ch->hold[i]); 2317 ch->hold[i] = NULL; 2318 ch->numhslots--; 2319 } 2320 } 2321 free(ccb->ataio.data_ptr, M_AHCI); 2322 xpt_free_ccb(ccb); 2323 xpt_release_simq(ch->sim, TRUE); 2324 } 2325 2326 static void 2327 ahci_process_request_sense(device_t dev, union ccb *ccb) 2328 { 2329 struct ahci_channel *ch = device_get_softc(dev); 2330 int i; 2331 2332 ch->recoverycmd = 0; 2333 2334 i = ccb->ccb_h.recovery_slot; 2335 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 2336 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 2337 } else { 2338 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2339 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 2340 } 2341 xpt_done(ch->hold[i]); 2342 ch->hold[i] = NULL; 2343 ch->numhslots--; 2344 xpt_free_ccb(ccb); 2345 xpt_release_simq(ch->sim, TRUE); 2346 } 2347 2348 static void 2349 ahci_start(device_t dev, int fbs) 2350 { 2351 struct ahci_channel *ch = device_get_softc(dev); 2352 u_int32_t cmd; 2353 2354 /* Clear SATA error register */ 2355 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2356 /* Clear any interrupts pending on this channel */ 2357 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2358 /* Configure FIS-based switching if supported. */ 2359 if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2360 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2361 ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2362 ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2363 } 2364 /* Start operations on this channel */ 2365 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2366 cmd &= ~AHCI_P_CMD_PMA; 2367 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2368 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2369 } 2370 2371 static void 2372 ahci_stop(device_t dev) 2373 { 2374 struct ahci_channel *ch = device_get_softc(dev); 2375 u_int32_t cmd; 2376 int timeout; 2377 2378 /* Kill all activity on this channel */ 2379 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2380 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2381 /* Wait for activity stop. */ 2382 timeout = 0; 2383 do { 2384 DELAY(10); 2385 if (timeout++ > 50000) { 2386 device_printf(dev, "stopping AHCI engine failed\n"); 2387 break; 2388 } 2389 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2390 ch->eslots = 0; 2391 } 2392 2393 static void 2394 ahci_clo(device_t dev) 2395 { 2396 struct ahci_channel *ch = device_get_softc(dev); 2397 u_int32_t cmd; 2398 int timeout; 2399 2400 /* Issue Command List Override if supported */ 2401 if (ch->caps & AHCI_CAP_SCLO) { 2402 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2403 cmd |= AHCI_P_CMD_CLO; 2404 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2405 timeout = 0; 2406 do { 2407 DELAY(10); 2408 if (timeout++ > 50000) { 2409 device_printf(dev, "executing CLO failed\n"); 2410 break; 2411 } 2412 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2413 } 2414 } 2415 2416 static void 2417 ahci_stop_fr(device_t dev) 2418 { 2419 struct ahci_channel *ch = device_get_softc(dev); 2420 u_int32_t cmd; 2421 int timeout; 2422 2423 /* Kill all FIS reception on this channel */ 2424 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2425 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2426 /* Wait for FIS reception stop. */ 2427 timeout = 0; 2428 do { 2429 DELAY(10); 2430 if (timeout++ > 50000) { 2431 device_printf(dev, "stopping AHCI FR engine failed\n"); 2432 break; 2433 } 2434 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2435 } 2436 2437 static void 2438 ahci_start_fr(device_t dev) 2439 { 2440 struct ahci_channel *ch = device_get_softc(dev); 2441 u_int32_t cmd; 2442 2443 /* Start FIS reception on this channel */ 2444 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2445 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2446 } 2447 2448 static int 2449 ahci_wait_ready(device_t dev, int t, int t0) 2450 { 2451 struct ahci_channel *ch = device_get_softc(dev); 2452 int timeout = 0; 2453 uint32_t val; 2454 2455 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2456 (ATA_S_BUSY | ATA_S_DRQ)) { 2457 if (timeout > t) { 2458 if (t != 0) { 2459 device_printf(dev, 2460 "AHCI reset: device not ready after %dms " 2461 "(tfd = %08x)\n", 2462 MAX(t, 0) + t0, val); 2463 } 2464 return (EBUSY); 2465 } 2466 DELAY(1000); 2467 timeout++; 2468 } 2469 if (bootverbose) 2470 device_printf(dev, "AHCI reset: device ready after %dms\n", 2471 timeout + t0); 2472 return (0); 2473 } 2474 2475 static void 2476 ahci_reset_to(void *arg) 2477 { 2478 device_t dev = arg; 2479 struct ahci_channel *ch = device_get_softc(dev); 2480 2481 if (ch->resetting == 0) 2482 return; 2483 ch->resetting--; 2484 if (ahci_wait_ready(dev, ch->resetting == 0 ? -1 : 0, 2485 (310 - ch->resetting) * 100) == 0) { 2486 ch->resetting = 0; 2487 ahci_start(dev, 1); 2488 xpt_release_simq(ch->sim, TRUE); 2489 return; 2490 } 2491 if (ch->resetting == 0) { 2492 ahci_clo(dev); 2493 ahci_start(dev, 1); 2494 xpt_release_simq(ch->sim, TRUE); 2495 return; 2496 } 2497 callout_schedule(&ch->reset_timer, hz / 10); 2498 } 2499 2500 static void 2501 ahci_reset(device_t dev) 2502 { 2503 struct ahci_channel *ch = device_get_softc(dev); 2504 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2505 int i; 2506 2507 xpt_freeze_simq(ch->sim, 1); 2508 if (bootverbose) 2509 device_printf(dev, "AHCI reset...\n"); 2510 /* Forget about previous reset. */ 2511 if (ch->resetting) { 2512 ch->resetting = 0; 2513 callout_stop(&ch->reset_timer); 2514 xpt_release_simq(ch->sim, TRUE); 2515 } 2516 /* Requeue freezed command. */ 2517 if (ch->frozen) { 2518 union ccb *fccb = ch->frozen; 2519 ch->frozen = NULL; 2520 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2521 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2522 xpt_freeze_devq(fccb->ccb_h.path, 1); 2523 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2524 } 2525 xpt_done(fccb); 2526 } 2527 /* Kill the engine and requeue all running commands. */ 2528 ahci_stop(dev); 2529 for (i = 0; i < ch->numslots; i++) { 2530 /* Do we have a running request on slot? */ 2531 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2532 continue; 2533 /* XXX; Commands in loading state. */ 2534 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2535 } 2536 for (i = 0; i < ch->numslots; i++) { 2537 if (!ch->hold[i]) 2538 continue; 2539 xpt_done(ch->hold[i]); 2540 ch->hold[i] = NULL; 2541 ch->numhslots--; 2542 } 2543 if (ch->toslots != 0) 2544 xpt_release_simq(ch->sim, TRUE); 2545 ch->eslots = 0; 2546 ch->toslots = 0; 2547 ch->wrongccs = 0; 2548 ch->fatalerr = 0; 2549 /* Tell the XPT about the event */ 2550 xpt_async(AC_BUS_RESET, ch->path, NULL); 2551 /* Disable port interrupts */ 2552 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2553 /* Reset and reconnect PHY, */ 2554 if (!ahci_sata_phy_reset(dev)) { 2555 if (bootverbose) 2556 device_printf(dev, 2557 "AHCI reset: device not found\n"); 2558 ch->devices = 0; 2559 /* Enable wanted port interrupts */ 2560 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2561 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2562 AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2563 xpt_release_simq(ch->sim, TRUE); 2564 return; 2565 } 2566 if (bootverbose) 2567 device_printf(dev, "AHCI reset: device found\n"); 2568 /* Wait for clearing busy status. */ 2569 if (ahci_wait_ready(dev, dumping ? 31000 : 0, 0)) { 2570 if (dumping) 2571 ahci_clo(dev); 2572 else 2573 ch->resetting = 310; 2574 } 2575 ch->devices = 1; 2576 /* Enable wanted port interrupts */ 2577 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2578 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2579 AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2580 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2581 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC | 2582 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2583 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2584 if (ch->resetting) 2585 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, dev); 2586 else { 2587 ahci_start(dev, 1); 2588 xpt_release_simq(ch->sim, TRUE); 2589 } 2590 } 2591 2592 static int 2593 ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2594 { 2595 struct ahci_channel *ch = device_get_softc(dev); 2596 u_int8_t *fis = &ctp->cfis[0]; 2597 2598 bzero(ctp->cfis, 64); 2599 fis[0] = 0x27; /* host to device */ 2600 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2601 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2602 fis[1] |= 0x80; 2603 fis[2] = ATA_PACKET_CMD; 2604 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2605 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2606 fis[3] = ATA_F_DMA; 2607 else { 2608 fis[5] = ccb->csio.dxfer_len; 2609 fis[6] = ccb->csio.dxfer_len >> 8; 2610 } 2611 fis[7] = ATA_D_LBA; 2612 fis[15] = ATA_A_4BIT; 2613 bzero(ctp->acmd, 32); 2614 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2615 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2616 ctp->acmd, ccb->csio.cdb_len); 2617 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2618 fis[1] |= 0x80; 2619 fis[2] = ccb->ataio.cmd.command; 2620 fis[3] = ccb->ataio.cmd.features; 2621 fis[4] = ccb->ataio.cmd.lba_low; 2622 fis[5] = ccb->ataio.cmd.lba_mid; 2623 fis[6] = ccb->ataio.cmd.lba_high; 2624 fis[7] = ccb->ataio.cmd.device; 2625 fis[8] = ccb->ataio.cmd.lba_low_exp; 2626 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2627 fis[10] = ccb->ataio.cmd.lba_high_exp; 2628 fis[11] = ccb->ataio.cmd.features_exp; 2629 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2630 fis[12] = tag << 3; 2631 fis[13] = 0; 2632 } else { 2633 fis[12] = ccb->ataio.cmd.sector_count; 2634 fis[13] = ccb->ataio.cmd.sector_count_exp; 2635 } 2636 fis[15] = ATA_A_4BIT; 2637 } else { 2638 fis[15] = ccb->ataio.cmd.control; 2639 } 2640 return (20); 2641 } 2642 2643 static int 2644 ahci_sata_connect(struct ahci_channel *ch) 2645 { 2646 u_int32_t status; 2647 int timeout, found = 0; 2648 2649 /* Wait up to 100ms for "connect well" */ 2650 for (timeout = 0; timeout < 1000 ; timeout++) { 2651 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2652 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 2653 found = 1; 2654 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2655 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2656 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2657 break; 2658 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2659 if (bootverbose) { 2660 device_printf(ch->dev, "SATA offline status=%08x\n", 2661 status); 2662 } 2663 return (0); 2664 } 2665 if (found == 0 && timeout >= 100) 2666 break; 2667 DELAY(100); 2668 } 2669 if (timeout >= 1000 || !found) { 2670 if (bootverbose) { 2671 device_printf(ch->dev, 2672 "SATA connect timeout time=%dus status=%08x\n", 2673 timeout * 100, status); 2674 } 2675 return (0); 2676 } 2677 if (bootverbose) { 2678 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n", 2679 timeout * 100, status); 2680 } 2681 /* Clear SATA error register */ 2682 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2683 return (1); 2684 } 2685 2686 static int 2687 ahci_sata_phy_reset(device_t dev) 2688 { 2689 struct ahci_channel *ch = device_get_softc(dev); 2690 int sata_rev; 2691 uint32_t val; 2692 2693 if (ch->listening) { 2694 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2695 val |= AHCI_P_CMD_SUD; 2696 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2697 ch->listening = 0; 2698 } 2699 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2700 if (sata_rev == 1) 2701 val = ATA_SC_SPD_SPEED_GEN1; 2702 else if (sata_rev == 2) 2703 val = ATA_SC_SPD_SPEED_GEN2; 2704 else if (sata_rev == 3) 2705 val = ATA_SC_SPD_SPEED_GEN3; 2706 else 2707 val = 0; 2708 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2709 ATA_SC_DET_RESET | val | 2710 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2711 DELAY(1000); 2712 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2713 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2714 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2715 if (!ahci_sata_connect(ch)) { 2716 if (ch->caps & AHCI_CAP_SSS) { 2717 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2718 val &= ~AHCI_P_CMD_SUD; 2719 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2720 ch->listening = 1; 2721 } else if (ch->pm_level > 0) 2722 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2723 return (0); 2724 } 2725 return (1); 2726 } 2727 2728 static int 2729 ahci_check_ids(device_t dev, union ccb *ccb) 2730 { 2731 struct ahci_channel *ch = device_get_softc(dev); 2732 2733 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) { 2734 ccb->ccb_h.status = CAM_TID_INVALID; 2735 xpt_done(ccb); 2736 return (-1); 2737 } 2738 if (ccb->ccb_h.target_lun != 0) { 2739 ccb->ccb_h.status = CAM_LUN_INVALID; 2740 xpt_done(ccb); 2741 return (-1); 2742 } 2743 return (0); 2744 } 2745 2746 static void 2747 ahciaction(struct cam_sim *sim, union ccb *ccb) 2748 { 2749 device_t dev, parent; 2750 struct ahci_channel *ch; 2751 2752 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2753 ccb->ccb_h.func_code)); 2754 2755 ch = (struct ahci_channel *)cam_sim_softc(sim); 2756 dev = ch->dev; 2757 switch (ccb->ccb_h.func_code) { 2758 /* Common cases first */ 2759 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2760 case XPT_SCSI_IO: 2761 if (ahci_check_ids(dev, ccb)) 2762 return; 2763 if (ch->devices == 0 || 2764 (ch->pm_present == 0 && 2765 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2766 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2767 break; 2768 } 2769 ccb->ccb_h.recovery_type = RECOVERY_NONE; 2770 /* Check for command collision. */ 2771 if (ahci_check_collision(dev, ccb)) { 2772 /* Freeze command. */ 2773 ch->frozen = ccb; 2774 /* We have only one frozen slot, so freeze simq also. */ 2775 xpt_freeze_simq(ch->sim, 1); 2776 return; 2777 } 2778 ahci_begin_transaction(dev, ccb); 2779 return; 2780 case XPT_EN_LUN: /* Enable LUN as a target */ 2781 case XPT_TARGET_IO: /* Execute target I/O request */ 2782 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2783 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2784 case XPT_ABORT: /* Abort the specified CCB */ 2785 /* XXX Implement */ 2786 ccb->ccb_h.status = CAM_REQ_INVALID; 2787 break; 2788 case XPT_SET_TRAN_SETTINGS: 2789 { 2790 struct ccb_trans_settings *cts = &ccb->cts; 2791 struct ahci_device *d; 2792 2793 if (ahci_check_ids(dev, ccb)) 2794 return; 2795 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2796 d = &ch->curr[ccb->ccb_h.target_id]; 2797 else 2798 d = &ch->user[ccb->ccb_h.target_id]; 2799 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2800 d->revision = cts->xport_specific.sata.revision; 2801 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2802 d->mode = cts->xport_specific.sata.mode; 2803 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2804 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2805 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2806 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2807 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2808 ch->pm_present = cts->xport_specific.sata.pm_present; 2809 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2810 d->atapi = cts->xport_specific.sata.atapi; 2811 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2812 d->caps = cts->xport_specific.sata.caps; 2813 ccb->ccb_h.status = CAM_REQ_CMP; 2814 break; 2815 } 2816 case XPT_GET_TRAN_SETTINGS: 2817 /* Get default/user set transfer settings for the target */ 2818 { 2819 struct ccb_trans_settings *cts = &ccb->cts; 2820 struct ahci_device *d; 2821 uint32_t status; 2822 2823 if (ahci_check_ids(dev, ccb)) 2824 return; 2825 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2826 d = &ch->curr[ccb->ccb_h.target_id]; 2827 else 2828 d = &ch->user[ccb->ccb_h.target_id]; 2829 cts->protocol = PROTO_UNSPECIFIED; 2830 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2831 cts->transport = XPORT_SATA; 2832 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2833 cts->proto_specific.valid = 0; 2834 cts->xport_specific.sata.valid = 0; 2835 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2836 (ccb->ccb_h.target_id == 15 || 2837 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2838 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2839 if (status & 0x0f0) { 2840 cts->xport_specific.sata.revision = 2841 (status & 0x0f0) >> 4; 2842 cts->xport_specific.sata.valid |= 2843 CTS_SATA_VALID_REVISION; 2844 } 2845 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2846 if (ch->pm_level) { 2847 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC)) 2848 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2849 if (ch->caps2 & AHCI_CAP2_APST) 2850 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST; 2851 } 2852 if ((ch->caps & AHCI_CAP_SNCQ) && 2853 (ch->quirks & AHCI_Q_NOAA) == 0) 2854 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA; 2855 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 2856 cts->xport_specific.sata.caps &= 2857 ch->user[ccb->ccb_h.target_id].caps; 2858 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2859 } else { 2860 cts->xport_specific.sata.revision = d->revision; 2861 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2862 cts->xport_specific.sata.caps = d->caps; 2863 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2864 } 2865 cts->xport_specific.sata.mode = d->mode; 2866 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2867 cts->xport_specific.sata.bytecount = d->bytecount; 2868 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2869 cts->xport_specific.sata.pm_present = ch->pm_present; 2870 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2871 cts->xport_specific.sata.tags = d->tags; 2872 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2873 cts->xport_specific.sata.atapi = d->atapi; 2874 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2875 ccb->ccb_h.status = CAM_REQ_CMP; 2876 break; 2877 } 2878 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2879 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2880 ahci_reset(dev); 2881 ccb->ccb_h.status = CAM_REQ_CMP; 2882 break; 2883 case XPT_TERM_IO: /* Terminate the I/O process */ 2884 /* XXX Implement */ 2885 ccb->ccb_h.status = CAM_REQ_INVALID; 2886 break; 2887 case XPT_PATH_INQ: /* Path routing inquiry */ 2888 { 2889 struct ccb_pathinq *cpi = &ccb->cpi; 2890 2891 parent = device_get_parent(dev); 2892 cpi->version_num = 1; /* XXX??? */ 2893 cpi->hba_inquiry = PI_SDTR_ABLE; 2894 if (ch->caps & AHCI_CAP_SNCQ) 2895 cpi->hba_inquiry |= PI_TAG_ABLE; 2896 if (ch->caps & AHCI_CAP_SPM) 2897 cpi->hba_inquiry |= PI_SATAPM; 2898 cpi->target_sprt = 0; 2899 cpi->hba_misc = PIM_SEQSCAN; 2900 cpi->hba_eng_cnt = 0; 2901 if (ch->caps & AHCI_CAP_SPM) 2902 cpi->max_target = 15; 2903 else 2904 cpi->max_target = 0; 2905 cpi->max_lun = 0; 2906 cpi->initiator_id = 0; 2907 cpi->bus_id = cam_sim_bus(sim); 2908 cpi->base_transfer_speed = 150000; 2909 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2910 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 2911 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2912 cpi->unit_number = cam_sim_unit(sim); 2913 cpi->transport = XPORT_SATA; 2914 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2915 cpi->protocol = PROTO_ATA; 2916 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2917 cpi->maxio = MAXPHYS; 2918 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 2919 if (pci_get_devid(parent) == 0x43801002) 2920 cpi->maxio = min(cpi->maxio, 128 * 512); 2921 cpi->hba_vendor = pci_get_vendor(parent); 2922 cpi->hba_device = pci_get_device(parent); 2923 cpi->hba_subvendor = pci_get_subvendor(parent); 2924 cpi->hba_subdevice = pci_get_subdevice(parent); 2925 cpi->ccb_h.status = CAM_REQ_CMP; 2926 break; 2927 } 2928 default: 2929 ccb->ccb_h.status = CAM_REQ_INVALID; 2930 break; 2931 } 2932 xpt_done(ccb); 2933 } 2934 2935 static void 2936 ahcipoll(struct cam_sim *sim) 2937 { 2938 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 2939 2940 ahci_ch_intr(ch->dev); 2941 if (ch->resetting != 0 && 2942 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) { 2943 ch->resetpolldiv = 1000; 2944 ahci_reset_to(ch->dev); 2945 } 2946 } 2947