xref: /freebsd/sys/dev/ahci/ahci.c (revision eaa797943eeac5614edfdc8f6309f332343c3dd2)
1 /*-
2  * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer,
10  *    without modification, immediately at the beginning of the file.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  */
26 
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29 
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/bus.h>
35 #include <sys/conf.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <machine/stdarg.h>
41 #include <machine/resource.h>
42 #include <machine/bus.h>
43 #include <sys/rman.h>
44 #include "ahci.h"
45 
46 #include <cam/cam.h>
47 #include <cam/cam_ccb.h>
48 #include <cam/cam_sim.h>
49 #include <cam/cam_xpt_sim.h>
50 #include <cam/cam_debug.h>
51 
52 /* local prototypes */
53 static void ahci_intr(void *data);
54 static void ahci_intr_one(void *data);
55 static void ahci_intr_one_edge(void *data);
56 static int ahci_ch_init(device_t dev);
57 static int ahci_ch_deinit(device_t dev);
58 static int ahci_ch_suspend(device_t dev);
59 static int ahci_ch_resume(device_t dev);
60 static void ahci_ch_pm(void *arg);
61 static void ahci_ch_intr(void *arg);
62 static void ahci_ch_intr_direct(void *arg);
63 static void ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus);
64 static void ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb);
65 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
66 static void ahci_execute_transaction(struct ahci_slot *slot);
67 static void ahci_timeout(struct ahci_slot *slot);
68 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et);
69 static int ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag);
70 static void ahci_dmainit(device_t dev);
71 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
72 static void ahci_dmafini(device_t dev);
73 static void ahci_slotsalloc(device_t dev);
74 static void ahci_slotsfree(device_t dev);
75 static void ahci_reset(struct ahci_channel *ch);
76 static void ahci_start(struct ahci_channel *ch, int fbs);
77 static void ahci_stop(struct ahci_channel *ch);
78 static void ahci_clo(struct ahci_channel *ch);
79 static void ahci_start_fr(struct ahci_channel *ch);
80 static void ahci_stop_fr(struct ahci_channel *ch);
81 
82 static int ahci_sata_connect(struct ahci_channel *ch);
83 static int ahci_sata_phy_reset(struct ahci_channel *ch);
84 static int ahci_wait_ready(struct ahci_channel *ch, int t, int t0);
85 
86 static void ahci_issue_recovery(struct ahci_channel *ch);
87 static void ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb);
88 static void ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb);
89 
90 static void ahciaction(struct cam_sim *sim, union ccb *ccb);
91 static void ahcipoll(struct cam_sim *sim);
92 
93 static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers");
94 
95 #define recovery_type		spriv_field0
96 #define RECOVERY_NONE		0
97 #define RECOVERY_READ_LOG	1
98 #define RECOVERY_REQUEST_SENSE	2
99 #define recovery_slot		spriv_field1
100 
101 int
102 ahci_ctlr_setup(device_t dev)
103 {
104 	struct ahci_controller *ctlr = device_get_softc(dev);
105 	/* Clear interrupts */
106 	ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS));
107 	/* Configure CCC */
108 	if (ctlr->ccc) {
109 		ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI));
110 		ATA_OUTL(ctlr->r_mem, AHCI_CCCC,
111 		    (ctlr->ccc << AHCI_CCCC_TV_SHIFT) |
112 		    (4 << AHCI_CCCC_CC_SHIFT) |
113 		    AHCI_CCCC_EN);
114 		ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) &
115 		    AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT;
116 		if (bootverbose) {
117 			device_printf(dev,
118 			    "CCC with %dms/4cmd enabled on vector %d\n",
119 			    ctlr->ccc, ctlr->cccv);
120 		}
121 	}
122 	/* Enable AHCI interrupts */
123 	ATA_OUTL(ctlr->r_mem, AHCI_GHC,
124 	    ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE);
125 	return (0);
126 }
127 
128 int
129 ahci_ctlr_reset(device_t dev)
130 {
131 	struct ahci_controller *ctlr = device_get_softc(dev);
132 	int timeout;
133 
134 	/* Enable AHCI mode */
135 	ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
136 	/* Reset AHCI controller */
137 	ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR);
138 	for (timeout = 1000; timeout > 0; timeout--) {
139 		DELAY(1000);
140 		if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0)
141 			break;
142 	}
143 	if (timeout == 0) {
144 		device_printf(dev, "AHCI controller reset failure\n");
145 		return (ENXIO);
146 	}
147 	/* Reenable AHCI mode */
148 	ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
149 
150 	if (ctlr->quirks & AHCI_Q_RESTORE_CAP) {
151 		/*
152 		 * Restore capability field.
153 		 * This is write to a read-only register to restore its state.
154 		 * On fully standard-compliant hardware this is not needed and
155 		 * this operation shall not take place. See ahci_pci.c for
156 		 * platforms using this quirk.
157 		 */
158 		ATA_OUTL(ctlr->r_mem, AHCI_CAP, ctlr->caps);
159 	}
160 
161 	return (0);
162 }
163 
164 
165 int
166 ahci_attach(device_t dev)
167 {
168 	struct ahci_controller *ctlr = device_get_softc(dev);
169 	int error, i, speed, unit;
170 	uint32_t u, version;
171 	device_t child;
172 
173 	ctlr->dev = dev;
174 	ctlr->ccc = 0;
175 	resource_int_value(device_get_name(dev),
176 	    device_get_unit(dev), "ccc", &ctlr->ccc);
177 
178 	/* Setup our own memory management for channels. */
179 	ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
180 	ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
181 	ctlr->sc_iomem.rm_type = RMAN_ARRAY;
182 	ctlr->sc_iomem.rm_descr = "I/O memory addresses";
183 	if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
184 		ahci_free_mem(dev);
185 		return (error);
186 	}
187 	if ((error = rman_manage_region(&ctlr->sc_iomem,
188 	    rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
189 		ahci_free_mem(dev);
190 		rman_fini(&ctlr->sc_iomem);
191 		return (error);
192 	}
193 	/* Get the HW capabilities */
194 	version = ATA_INL(ctlr->r_mem, AHCI_VS);
195 	ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
196 	if (version >= 0x00010200)
197 		ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2);
198 	if (ctlr->caps & AHCI_CAP_EMS)
199 		ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL);
200 
201 	if (ctlr->quirks & AHCI_Q_FORCE_PI) {
202 		/*
203 		 * Enable ports.
204 		 * The spec says that BIOS sets up bits corresponding to
205 		 * available ports. On platforms where this information
206 		 * is missing, the driver can define available ports on its own.
207 		 */
208 		int nports = (ctlr->caps & AHCI_CAP_NPMASK) + 1;
209 		int nmask = (1 << nports) - 1;
210 
211 		ATA_OUTL(ctlr->r_mem, AHCI_PI, nmask);
212 		device_printf(dev, "Forcing PI to %d ports (mask = %x)\n",
213 		    nports, nmask);
214 	}
215 
216 	ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI);
217 
218 	/* Identify and set separate quirks for HBA and RAID f/w Marvells. */
219 	if ((ctlr->quirks & AHCI_Q_ALTSIG) &&
220 	    (ctlr->caps & AHCI_CAP_SPM) == 0)
221 		ctlr->quirks |= AHCI_Q_NOBSYRES;
222 
223 	if (ctlr->quirks & AHCI_Q_1CH) {
224 		ctlr->caps &= ~AHCI_CAP_NPMASK;
225 		ctlr->ichannels &= 0x01;
226 	}
227 	if (ctlr->quirks & AHCI_Q_2CH) {
228 		ctlr->caps &= ~AHCI_CAP_NPMASK;
229 		ctlr->caps |= 1;
230 		ctlr->ichannels &= 0x03;
231 	}
232 	if (ctlr->quirks & AHCI_Q_4CH) {
233 		ctlr->caps &= ~AHCI_CAP_NPMASK;
234 		ctlr->caps |= 3;
235 		ctlr->ichannels &= 0x0f;
236 	}
237 	ctlr->channels = MAX(flsl(ctlr->ichannels),
238 	    (ctlr->caps & AHCI_CAP_NPMASK) + 1);
239 	if (ctlr->quirks & AHCI_Q_NOPMP)
240 		ctlr->caps &= ~AHCI_CAP_SPM;
241 	if (ctlr->quirks & AHCI_Q_NONCQ)
242 		ctlr->caps &= ~AHCI_CAP_SNCQ;
243 	if ((ctlr->caps & AHCI_CAP_CCCS) == 0)
244 		ctlr->ccc = 0;
245 	ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC);
246 
247 	/* Create controller-wide DMA tag. */
248 	if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
249 	    (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR :
250 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
251 	    BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE,
252 	    0, NULL, NULL, &ctlr->dma_tag)) {
253 		ahci_free_mem(dev);
254 		rman_fini(&ctlr->sc_iomem);
255 		return (ENXIO);
256 	}
257 
258 	ahci_ctlr_setup(dev);
259 
260 	/* Setup interrupts. */
261 	if ((error = ahci_setup_interrupt(dev)) != 0) {
262 		bus_dma_tag_destroy(ctlr->dma_tag);
263 		ahci_free_mem(dev);
264 		rman_fini(&ctlr->sc_iomem);
265 		return (error);
266 	}
267 
268 	i = 0;
269 	for (u = ctlr->ichannels; u != 0; u >>= 1)
270 		i += (u & 1);
271 	ctlr->direct = (ctlr->msi && (ctlr->numirqs > 1 || i <= 3));
272 	resource_int_value(device_get_name(dev), device_get_unit(dev),
273 	    "direct", &ctlr->direct);
274 	/* Announce HW capabilities. */
275 	speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT;
276 	device_printf(dev,
277 		    "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n",
278 		    ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f),
279 		    ((version >> 4) & 0xf0) + (version & 0x0f),
280 		    (ctlr->caps & AHCI_CAP_NPMASK) + 1,
281 		    ((speed == 1) ? "1.5":((speed == 2) ? "3":
282 		    ((speed == 3) ? "6":"?"))),
283 		    (ctlr->caps & AHCI_CAP_SPM) ?
284 		    "supported" : "not supported",
285 		    (ctlr->caps & AHCI_CAP_FBSS) ?
286 		    " with FBS" : "");
287 	if (ctlr->quirks != 0) {
288 		device_printf(dev, "quirks=0x%b\n", ctlr->quirks,
289 		    AHCI_Q_BIT_STRING);
290 	}
291 	if (bootverbose) {
292 		device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps",
293 		    (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"",
294 		    (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"",
295 		    (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"",
296 		    (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"",
297 		    (ctlr->caps & AHCI_CAP_SSS) ? " SS":"",
298 		    (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"",
299 		    (ctlr->caps & AHCI_CAP_SAL) ? " AL":"",
300 		    (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"",
301 		    ((speed == 1) ? "1.5":((speed == 2) ? "3":
302 		    ((speed == 3) ? "6":"?"))));
303 		printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n",
304 		    (ctlr->caps & AHCI_CAP_SAM) ? " AM":"",
305 		    (ctlr->caps & AHCI_CAP_SPM) ? " PM":"",
306 		    (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"",
307 		    (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"",
308 		    (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"",
309 		    (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"",
310 		    ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1,
311 		    (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"",
312 		    (ctlr->caps & AHCI_CAP_EMS) ? " EM":"",
313 		    (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"",
314 		    (ctlr->caps & AHCI_CAP_NPMASK) + 1);
315 	}
316 	if (bootverbose && version >= 0x00010200) {
317 		device_printf(dev, "Caps2:%s%s%s%s%s%s\n",
318 		    (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"",
319 		    (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"",
320 		    (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"",
321 		    (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"",
322 		    (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"",
323 		    (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":"");
324 	}
325 	/* Attach all channels on this controller */
326 	for (unit = 0; unit < ctlr->channels; unit++) {
327 		child = device_add_child(dev, "ahcich", -1);
328 		if (child == NULL) {
329 			device_printf(dev, "failed to add channel device\n");
330 			continue;
331 		}
332 		device_set_ivars(child, (void *)(intptr_t)unit);
333 		if ((ctlr->ichannels & (1 << unit)) == 0)
334 			device_disable(child);
335 	}
336 	if (ctlr->caps & AHCI_CAP_EMS) {
337 		child = device_add_child(dev, "ahciem", -1);
338 		if (child == NULL)
339 			device_printf(dev, "failed to add enclosure device\n");
340 		else
341 			device_set_ivars(child, (void *)(intptr_t)-1);
342 	}
343 	bus_generic_attach(dev);
344 	return (0);
345 }
346 
347 int
348 ahci_detach(device_t dev)
349 {
350 	struct ahci_controller *ctlr = device_get_softc(dev);
351 	int i;
352 
353 	/* Detach & delete all children */
354 	device_delete_children(dev);
355 
356 	/* Free interrupts. */
357 	for (i = 0; i < ctlr->numirqs; i++) {
358 		if (ctlr->irqs[i].r_irq) {
359 			bus_teardown_intr(dev, ctlr->irqs[i].r_irq,
360 			    ctlr->irqs[i].handle);
361 			bus_release_resource(dev, SYS_RES_IRQ,
362 			    ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq);
363 		}
364 	}
365 	bus_dma_tag_destroy(ctlr->dma_tag);
366 	/* Free memory. */
367 	rman_fini(&ctlr->sc_iomem);
368 	ahci_free_mem(dev);
369 	return (0);
370 }
371 
372 void
373 ahci_free_mem(device_t dev)
374 {
375 	struct ahci_controller *ctlr = device_get_softc(dev);
376 
377 	/* Release memory resources */
378 	if (ctlr->r_mem)
379 		bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
380 	if (ctlr->r_msix_table)
381 		bus_release_resource(dev, SYS_RES_MEMORY,
382 		    ctlr->r_msix_tab_rid, ctlr->r_msix_table);
383 	if (ctlr->r_msix_pba)
384 		bus_release_resource(dev, SYS_RES_MEMORY,
385 		    ctlr->r_msix_pba_rid, ctlr->r_msix_pba);
386 
387 	ctlr->r_msix_pba = ctlr->r_mem = ctlr->r_msix_table = NULL;
388 }
389 
390 int
391 ahci_setup_interrupt(device_t dev)
392 {
393 	struct ahci_controller *ctlr = device_get_softc(dev);
394 	int i;
395 
396 	/* Check for single MSI vector fallback. */
397 	if (ctlr->numirqs > 1 &&
398 	    (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) {
399 		device_printf(dev, "Falling back to one MSI\n");
400 		ctlr->numirqs = 1;
401 	}
402 
403 	/* Ensure we don't overrun irqs. */
404 	if (ctlr->numirqs > AHCI_MAX_IRQS) {
405 		device_printf(dev, "Too many irqs %d > %d (clamping)\n",
406 		    ctlr->numirqs, AHCI_MAX_IRQS);
407 		ctlr->numirqs = AHCI_MAX_IRQS;
408 	}
409 
410 	/* Allocate all IRQs. */
411 	for (i = 0; i < ctlr->numirqs; i++) {
412 		ctlr->irqs[i].ctlr = ctlr;
413 		ctlr->irqs[i].r_irq_rid = i + (ctlr->msi ? 1 : 0);
414 		if (ctlr->channels == 1 && !ctlr->ccc && ctlr->msi)
415 			ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
416 		else if (ctlr->numirqs == 1 || i >= ctlr->channels ||
417 		    (ctlr->ccc && i == ctlr->cccv))
418 			ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL;
419 		else if (ctlr->channels > ctlr->numirqs &&
420 		    i == ctlr->numirqs - 1)
421 			ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER;
422 		else
423 			ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
424 		if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
425 		    &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
426 			device_printf(dev, "unable to map interrupt\n");
427 			return (ENXIO);
428 		}
429 		if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL,
430 		    (ctlr->irqs[i].mode != AHCI_IRQ_MODE_ONE) ? ahci_intr :
431 		     ((ctlr->quirks & AHCI_Q_EDGEIS) ? ahci_intr_one_edge :
432 		      ahci_intr_one),
433 		    &ctlr->irqs[i], &ctlr->irqs[i].handle))) {
434 			/* SOS XXX release r_irq */
435 			device_printf(dev, "unable to setup interrupt\n");
436 			return (ENXIO);
437 		}
438 		if (ctlr->numirqs > 1) {
439 			bus_describe_intr(dev, ctlr->irqs[i].r_irq,
440 			    ctlr->irqs[i].handle,
441 			    ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ?
442 			    "ch%d" : "%d", i);
443 		}
444 	}
445 	return (0);
446 }
447 
448 /*
449  * Common case interrupt handler.
450  */
451 static void
452 ahci_intr(void *data)
453 {
454 	struct ahci_controller_irq *irq = data;
455 	struct ahci_controller *ctlr = irq->ctlr;
456 	u_int32_t is, ise = 0;
457 	void *arg;
458 	int unit;
459 
460 	if (irq->mode == AHCI_IRQ_MODE_ALL) {
461 		unit = 0;
462 		if (ctlr->ccc)
463 			is = ctlr->ichannels;
464 		else
465 			is = ATA_INL(ctlr->r_mem, AHCI_IS);
466 	} else {	/* AHCI_IRQ_MODE_AFTER */
467 		unit = irq->r_irq_rid - 1;
468 		is = ATA_INL(ctlr->r_mem, AHCI_IS);
469 		is &= (0xffffffff << unit);
470 	}
471 	/* CCC interrupt is edge triggered. */
472 	if (ctlr->ccc)
473 		ise = 1 << ctlr->cccv;
474 	/* Some controllers have edge triggered IS. */
475 	if (ctlr->quirks & AHCI_Q_EDGEIS)
476 		ise |= is;
477 	if (ise != 0)
478 		ATA_OUTL(ctlr->r_mem, AHCI_IS, ise);
479 	for (; unit < ctlr->channels; unit++) {
480 		if ((is & (1 << unit)) != 0 &&
481 		    (arg = ctlr->interrupt[unit].argument)) {
482 				ctlr->interrupt[unit].function(arg);
483 		}
484 	}
485 	/* AHCI declares level triggered IS. */
486 	if (!(ctlr->quirks & AHCI_Q_EDGEIS))
487 		ATA_OUTL(ctlr->r_mem, AHCI_IS, is);
488 	ATA_RBL(ctlr->r_mem, AHCI_IS);
489 }
490 
491 /*
492  * Simplified interrupt handler for multivector MSI mode.
493  */
494 static void
495 ahci_intr_one(void *data)
496 {
497 	struct ahci_controller_irq *irq = data;
498 	struct ahci_controller *ctlr = irq->ctlr;
499 	void *arg;
500 	int unit;
501 
502 	unit = irq->r_irq_rid - 1;
503 	if ((arg = ctlr->interrupt[unit].argument))
504 	    ctlr->interrupt[unit].function(arg);
505 	/* AHCI declares level triggered IS. */
506 	ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
507 	ATA_RBL(ctlr->r_mem, AHCI_IS);
508 }
509 
510 static void
511 ahci_intr_one_edge(void *data)
512 {
513 	struct ahci_controller_irq *irq = data;
514 	struct ahci_controller *ctlr = irq->ctlr;
515 	void *arg;
516 	int unit;
517 
518 	unit = irq->r_irq_rid - 1;
519 	/* Some controllers have edge triggered IS. */
520 	ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
521 	if ((arg = ctlr->interrupt[unit].argument))
522 		ctlr->interrupt[unit].function(arg);
523 	ATA_RBL(ctlr->r_mem, AHCI_IS);
524 }
525 
526 struct resource *
527 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid,
528     rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
529 {
530 	struct ahci_controller *ctlr = device_get_softc(dev);
531 	struct resource *res;
532 	rman_res_t st;
533 	int offset, size, unit;
534 
535 	unit = (intptr_t)device_get_ivars(child);
536 	res = NULL;
537 	switch (type) {
538 	case SYS_RES_MEMORY:
539 		if (unit >= 0) {
540 			offset = AHCI_OFFSET + (unit << 7);
541 			size = 128;
542 		} else if (*rid == 0) {
543 			offset = AHCI_EM_CTL;
544 			size = 4;
545 		} else {
546 			offset = (ctlr->emloc & 0xffff0000) >> 14;
547 			size = (ctlr->emloc & 0x0000ffff) << 2;
548 			if (*rid != 1) {
549 				if (*rid == 2 && (ctlr->capsem &
550 				    (AHCI_EM_XMT | AHCI_EM_SMB)) == 0)
551 					offset += size;
552 				else
553 					break;
554 			}
555 		}
556 		st = rman_get_start(ctlr->r_mem);
557 		res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
558 		    st + offset + size - 1, size, RF_ACTIVE, child);
559 		if (res) {
560 			bus_space_handle_t bsh;
561 			bus_space_tag_t bst;
562 			bsh = rman_get_bushandle(ctlr->r_mem);
563 			bst = rman_get_bustag(ctlr->r_mem);
564 			bus_space_subregion(bst, bsh, offset, 128, &bsh);
565 			rman_set_bushandle(res, bsh);
566 			rman_set_bustag(res, bst);
567 		}
568 		break;
569 	case SYS_RES_IRQ:
570 		if (*rid == ATA_IRQ_RID)
571 			res = ctlr->irqs[0].r_irq;
572 		break;
573 	}
574 	return (res);
575 }
576 
577 int
578 ahci_release_resource(device_t dev, device_t child, int type, int rid,
579     struct resource *r)
580 {
581 
582 	switch (type) {
583 	case SYS_RES_MEMORY:
584 		rman_release_resource(r);
585 		return (0);
586 	case SYS_RES_IRQ:
587 		if (rid != ATA_IRQ_RID)
588 			return (ENOENT);
589 		return (0);
590 	}
591 	return (EINVAL);
592 }
593 
594 int
595 ahci_setup_intr(device_t dev, device_t child, struct resource *irq,
596     int flags, driver_filter_t *filter, driver_intr_t *function,
597     void *argument, void **cookiep)
598 {
599 	struct ahci_controller *ctlr = device_get_softc(dev);
600 	int unit = (intptr_t)device_get_ivars(child);
601 
602 	if (filter != NULL) {
603 		printf("ahci.c: we cannot use a filter here\n");
604 		return (EINVAL);
605 	}
606 	ctlr->interrupt[unit].function = function;
607 	ctlr->interrupt[unit].argument = argument;
608 	return (0);
609 }
610 
611 int
612 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq,
613     void *cookie)
614 {
615 	struct ahci_controller *ctlr = device_get_softc(dev);
616 	int unit = (intptr_t)device_get_ivars(child);
617 
618 	ctlr->interrupt[unit].function = NULL;
619 	ctlr->interrupt[unit].argument = NULL;
620 	return (0);
621 }
622 
623 int
624 ahci_print_child(device_t dev, device_t child)
625 {
626 	int retval, channel;
627 
628 	retval = bus_print_child_header(dev, child);
629 	channel = (int)(intptr_t)device_get_ivars(child);
630 	if (channel >= 0)
631 		retval += printf(" at channel %d", channel);
632 	retval += bus_print_child_footer(dev, child);
633 	return (retval);
634 }
635 
636 int
637 ahci_child_location_str(device_t dev, device_t child, char *buf,
638     size_t buflen)
639 {
640 	int channel;
641 
642 	channel = (int)(intptr_t)device_get_ivars(child);
643 	if (channel >= 0)
644 		snprintf(buf, buflen, "channel=%d", channel);
645 	return (0);
646 }
647 
648 bus_dma_tag_t
649 ahci_get_dma_tag(device_t dev, device_t child)
650 {
651 	struct ahci_controller *ctlr = device_get_softc(dev);
652 
653 	return (ctlr->dma_tag);
654 }
655 
656 static int
657 ahci_ch_probe(device_t dev)
658 {
659 
660 	device_set_desc_copy(dev, "AHCI channel");
661 	return (BUS_PROBE_DEFAULT);
662 }
663 
664 static int
665 ahci_ch_attach(device_t dev)
666 {
667 	struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
668 	struct ahci_channel *ch = device_get_softc(dev);
669 	struct cam_devq *devq;
670 	int rid, error, i, sata_rev = 0;
671 	u_int32_t version;
672 
673 	ch->dev = dev;
674 	ch->unit = (intptr_t)device_get_ivars(dev);
675 	ch->caps = ctlr->caps;
676 	ch->caps2 = ctlr->caps2;
677 	ch->start = ctlr->ch_start;
678 	ch->quirks = ctlr->quirks;
679 	ch->vendorid = ctlr->vendorid;
680 	ch->deviceid = ctlr->deviceid;
681 	ch->subvendorid = ctlr->subvendorid;
682 	ch->subdeviceid = ctlr->subdeviceid;
683 	ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1;
684 	mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF);
685 	ch->pm_level = 0;
686 	resource_int_value(device_get_name(dev),
687 	    device_get_unit(dev), "pm_level", &ch->pm_level);
688 	STAILQ_INIT(&ch->doneq);
689 	if (ch->pm_level > 3)
690 		callout_init_mtx(&ch->pm_timer, &ch->mtx, 0);
691 	callout_init_mtx(&ch->reset_timer, &ch->mtx, 0);
692 	/* JMicron external ports (0) sometimes limited */
693 	if ((ctlr->quirks & AHCI_Q_SATA1_UNIT0) && ch->unit == 0)
694 		sata_rev = 1;
695 	if (ch->quirks & AHCI_Q_SATA2)
696 		sata_rev = 2;
697 	resource_int_value(device_get_name(dev),
698 	    device_get_unit(dev), "sata_rev", &sata_rev);
699 	for (i = 0; i < 16; i++) {
700 		ch->user[i].revision = sata_rev;
701 		ch->user[i].mode = 0;
702 		ch->user[i].bytecount = 8192;
703 		ch->user[i].tags = ch->numslots;
704 		ch->user[i].caps = 0;
705 		ch->curr[i] = ch->user[i];
706 		if (ch->pm_level) {
707 			ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ |
708 			    CTS_SATA_CAPS_H_APST |
709 			    CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST;
710 		}
711 		ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA |
712 		    CTS_SATA_CAPS_H_AN;
713 	}
714 	rid = 0;
715 	if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
716 	    &rid, RF_ACTIVE)))
717 		return (ENXIO);
718 	ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD);
719 	version = ATA_INL(ctlr->r_mem, AHCI_VS);
720 	if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS))
721 		ch->chcaps |= AHCI_P_CMD_FBSCP;
722 	if (ch->caps2 & AHCI_CAP2_SDS)
723 		ch->chscaps = ATA_INL(ch->r_mem, AHCI_P_DEVSLP);
724 	if (bootverbose) {
725 		device_printf(dev, "Caps:%s%s%s%s%s%s\n",
726 		    (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"",
727 		    (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"",
728 		    (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"",
729 		    (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"",
730 		    (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"",
731 		    (ch->chscaps & AHCI_P_DEVSLP_DSP) ? " DSP":"");
732 	}
733 	ahci_dmainit(dev);
734 	ahci_slotsalloc(dev);
735 	mtx_lock(&ch->mtx);
736 	ahci_ch_init(dev);
737 	rid = ATA_IRQ_RID;
738 	if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
739 	    &rid, RF_SHAREABLE | RF_ACTIVE))) {
740 		device_printf(dev, "Unable to map interrupt\n");
741 		error = ENXIO;
742 		goto err0;
743 	}
744 	if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL,
745 	    ctlr->direct ? ahci_ch_intr_direct : ahci_ch_intr,
746 	    ch, &ch->ih))) {
747 		device_printf(dev, "Unable to setup interrupt\n");
748 		error = ENXIO;
749 		goto err1;
750 	}
751 	/* Create the device queue for our SIM. */
752 	devq = cam_simq_alloc(ch->numslots);
753 	if (devq == NULL) {
754 		device_printf(dev, "Unable to allocate simq\n");
755 		error = ENOMEM;
756 		goto err1;
757 	}
758 	/* Construct SIM entry */
759 	ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch,
760 	    device_get_unit(dev), (struct mtx *)&ch->mtx,
761 	    min(2, ch->numslots),
762 	    (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0,
763 	    devq);
764 	if (ch->sim == NULL) {
765 		cam_simq_free(devq);
766 		device_printf(dev, "unable to allocate sim\n");
767 		error = ENOMEM;
768 		goto err1;
769 	}
770 	if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) {
771 		device_printf(dev, "unable to register xpt bus\n");
772 		error = ENXIO;
773 		goto err2;
774 	}
775 	if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim),
776 	    CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
777 		device_printf(dev, "unable to create path\n");
778 		error = ENXIO;
779 		goto err3;
780 	}
781 	if (ch->pm_level > 3) {
782 		callout_reset(&ch->pm_timer,
783 		    (ch->pm_level == 4) ? hz / 1000 : hz / 8,
784 		    ahci_ch_pm, ch);
785 	}
786 	mtx_unlock(&ch->mtx);
787 	return (0);
788 
789 err3:
790 	xpt_bus_deregister(cam_sim_path(ch->sim));
791 err2:
792 	cam_sim_free(ch->sim, /*free_devq*/TRUE);
793 err1:
794 	bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
795 err0:
796 	bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
797 	mtx_unlock(&ch->mtx);
798 	mtx_destroy(&ch->mtx);
799 	return (error);
800 }
801 
802 static int
803 ahci_ch_detach(device_t dev)
804 {
805 	struct ahci_channel *ch = device_get_softc(dev);
806 
807 	mtx_lock(&ch->mtx);
808 	xpt_async(AC_LOST_DEVICE, ch->path, NULL);
809 	/* Forget about reset. */
810 	if (ch->resetting) {
811 		ch->resetting = 0;
812 		xpt_release_simq(ch->sim, TRUE);
813 	}
814 	xpt_free_path(ch->path);
815 	xpt_bus_deregister(cam_sim_path(ch->sim));
816 	cam_sim_free(ch->sim, /*free_devq*/TRUE);
817 	mtx_unlock(&ch->mtx);
818 
819 	if (ch->pm_level > 3)
820 		callout_drain(&ch->pm_timer);
821 	callout_drain(&ch->reset_timer);
822 	bus_teardown_intr(dev, ch->r_irq, ch->ih);
823 	bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
824 
825 	ahci_ch_deinit(dev);
826 	ahci_slotsfree(dev);
827 	ahci_dmafini(dev);
828 
829 	bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
830 	mtx_destroy(&ch->mtx);
831 	return (0);
832 }
833 
834 static int
835 ahci_ch_init(device_t dev)
836 {
837 	struct ahci_channel *ch = device_get_softc(dev);
838 	uint64_t work;
839 
840 	/* Disable port interrupts */
841 	ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
842 	/* Setup work areas */
843 	work = ch->dma.work_bus + AHCI_CL_OFFSET;
844 	ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff);
845 	ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32);
846 	work = ch->dma.rfis_bus;
847 	ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff);
848 	ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32);
849 	/* Activate the channel and power/spin up device */
850 	ATA_OUTL(ch->r_mem, AHCI_P_CMD,
851 	     (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD |
852 	     ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) |
853 	     ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 )));
854 	ahci_start_fr(ch);
855 	ahci_start(ch, 1);
856 	return (0);
857 }
858 
859 static int
860 ahci_ch_deinit(device_t dev)
861 {
862 	struct ahci_channel *ch = device_get_softc(dev);
863 
864 	/* Disable port interrupts. */
865 	ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
866 	/* Reset command register. */
867 	ahci_stop(ch);
868 	ahci_stop_fr(ch);
869 	ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0);
870 	/* Allow everything, including partial and slumber modes. */
871 	ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0);
872 	/* Request slumber mode transition and give some time to get there. */
873 	ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER);
874 	DELAY(100);
875 	/* Disable PHY. */
876 	ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
877 	return (0);
878 }
879 
880 static int
881 ahci_ch_suspend(device_t dev)
882 {
883 	struct ahci_channel *ch = device_get_softc(dev);
884 
885 	mtx_lock(&ch->mtx);
886 	xpt_freeze_simq(ch->sim, 1);
887 	/* Forget about reset. */
888 	if (ch->resetting) {
889 		ch->resetting = 0;
890 		callout_stop(&ch->reset_timer);
891 		xpt_release_simq(ch->sim, TRUE);
892 	}
893 	while (ch->oslots)
894 		msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100);
895 	ahci_ch_deinit(dev);
896 	mtx_unlock(&ch->mtx);
897 	return (0);
898 }
899 
900 static int
901 ahci_ch_resume(device_t dev)
902 {
903 	struct ahci_channel *ch = device_get_softc(dev);
904 
905 	mtx_lock(&ch->mtx);
906 	ahci_ch_init(dev);
907 	ahci_reset(ch);
908 	xpt_release_simq(ch->sim, TRUE);
909 	mtx_unlock(&ch->mtx);
910 	return (0);
911 }
912 
913 devclass_t ahcich_devclass;
914 static device_method_t ahcich_methods[] = {
915 	DEVMETHOD(device_probe,     ahci_ch_probe),
916 	DEVMETHOD(device_attach,    ahci_ch_attach),
917 	DEVMETHOD(device_detach,    ahci_ch_detach),
918 	DEVMETHOD(device_suspend,   ahci_ch_suspend),
919 	DEVMETHOD(device_resume,    ahci_ch_resume),
920 	DEVMETHOD_END
921 };
922 static driver_t ahcich_driver = {
923         "ahcich",
924         ahcich_methods,
925         sizeof(struct ahci_channel)
926 };
927 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, NULL, NULL);
928 
929 struct ahci_dc_cb_args {
930 	bus_addr_t maddr;
931 	int error;
932 };
933 
934 static void
935 ahci_dmainit(device_t dev)
936 {
937 	struct ahci_channel *ch = device_get_softc(dev);
938 	struct ahci_dc_cb_args dcba;
939 	size_t rfsize;
940 
941 	/* Command area. */
942 	if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0,
943 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
944 	    NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE,
945 	    0, NULL, NULL, &ch->dma.work_tag))
946 		goto error;
947 	if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work,
948 	    BUS_DMA_ZERO, &ch->dma.work_map))
949 		goto error;
950 	if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work,
951 	    AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
952 		bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
953 		goto error;
954 	}
955 	ch->dma.work_bus = dcba.maddr;
956 	/* FIS receive area. */
957 	if (ch->chcaps & AHCI_P_CMD_FBSCP)
958 	    rfsize = 4096;
959 	else
960 	    rfsize = 256;
961 	if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0,
962 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
963 	    NULL, NULL, rfsize, 1, rfsize,
964 	    0, NULL, NULL, &ch->dma.rfis_tag))
965 		goto error;
966 	if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0,
967 	    &ch->dma.rfis_map))
968 		goto error;
969 	if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis,
970 	    rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
971 		bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
972 		goto error;
973 	}
974 	ch->dma.rfis_bus = dcba.maddr;
975 	/* Data area. */
976 	if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
977 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
978 	    NULL, NULL,
979 	    AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots,
980 	    AHCI_SG_ENTRIES, AHCI_PRD_MAX,
981 	    0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) {
982 		goto error;
983 	}
984 	return;
985 
986 error:
987 	device_printf(dev, "WARNING - DMA initialization failed\n");
988 	ahci_dmafini(dev);
989 }
990 
991 static void
992 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
993 {
994 	struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc;
995 
996 	if (!(dcba->error = error))
997 		dcba->maddr = segs[0].ds_addr;
998 }
999 
1000 static void
1001 ahci_dmafini(device_t dev)
1002 {
1003 	struct ahci_channel *ch = device_get_softc(dev);
1004 
1005 	if (ch->dma.data_tag) {
1006 		bus_dma_tag_destroy(ch->dma.data_tag);
1007 		ch->dma.data_tag = NULL;
1008 	}
1009 	if (ch->dma.rfis_bus) {
1010 		bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map);
1011 		bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1012 		ch->dma.rfis_bus = 0;
1013 		ch->dma.rfis = NULL;
1014 	}
1015 	if (ch->dma.work_bus) {
1016 		bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map);
1017 		bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1018 		ch->dma.work_bus = 0;
1019 		ch->dma.work = NULL;
1020 	}
1021 	if (ch->dma.work_tag) {
1022 		bus_dma_tag_destroy(ch->dma.work_tag);
1023 		ch->dma.work_tag = NULL;
1024 	}
1025 }
1026 
1027 static void
1028 ahci_slotsalloc(device_t dev)
1029 {
1030 	struct ahci_channel *ch = device_get_softc(dev);
1031 	int i;
1032 
1033 	/* Alloc and setup command/dma slots */
1034 	bzero(ch->slot, sizeof(ch->slot));
1035 	for (i = 0; i < ch->numslots; i++) {
1036 		struct ahci_slot *slot = &ch->slot[i];
1037 
1038 		slot->ch = ch;
1039 		slot->slot = i;
1040 		slot->state = AHCI_SLOT_EMPTY;
1041 		slot->ccb = NULL;
1042 		callout_init_mtx(&slot->timeout, &ch->mtx, 0);
1043 
1044 		if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map))
1045 			device_printf(ch->dev, "FAILURE - create data_map\n");
1046 	}
1047 }
1048 
1049 static void
1050 ahci_slotsfree(device_t dev)
1051 {
1052 	struct ahci_channel *ch = device_get_softc(dev);
1053 	int i;
1054 
1055 	/* Free all dma slots */
1056 	for (i = 0; i < ch->numslots; i++) {
1057 		struct ahci_slot *slot = &ch->slot[i];
1058 
1059 		callout_drain(&slot->timeout);
1060 		if (slot->dma.data_map) {
1061 			bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map);
1062 			slot->dma.data_map = NULL;
1063 		}
1064 	}
1065 }
1066 
1067 static int
1068 ahci_phy_check_events(struct ahci_channel *ch, u_int32_t serr)
1069 {
1070 
1071 	if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) ||
1072 	    ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) {
1073 		u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
1074 		union ccb *ccb;
1075 
1076 		if (bootverbose) {
1077 			if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
1078 				device_printf(ch->dev, "CONNECT requested\n");
1079 			else
1080 				device_printf(ch->dev, "DISCONNECT requested\n");
1081 		}
1082 		ahci_reset(ch);
1083 		if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1084 			return (0);
1085 		if (xpt_create_path(&ccb->ccb_h.path, NULL,
1086 		    cam_sim_path(ch->sim),
1087 		    CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1088 			xpt_free_ccb(ccb);
1089 			return (0);
1090 		}
1091 		xpt_rescan(ccb);
1092 		return (1);
1093 	}
1094 	return (0);
1095 }
1096 
1097 static void
1098 ahci_cpd_check_events(struct ahci_channel *ch)
1099 {
1100 	u_int32_t status;
1101 	union ccb *ccb;
1102 	device_t dev;
1103 
1104 	if (ch->pm_level == 0)
1105 		return;
1106 
1107 	status = ATA_INL(ch->r_mem, AHCI_P_CMD);
1108 	if ((status & AHCI_P_CMD_CPD) == 0)
1109 		return;
1110 
1111 	if (bootverbose) {
1112 		dev = ch->dev;
1113 		if (status & AHCI_P_CMD_CPS) {
1114 			device_printf(dev, "COLD CONNECT requested\n");
1115 		} else
1116 			device_printf(dev, "COLD DISCONNECT requested\n");
1117 	}
1118 	ahci_reset(ch);
1119 	if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1120 		return;
1121 	if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim),
1122 	    CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1123 		xpt_free_ccb(ccb);
1124 		return;
1125 	}
1126 	xpt_rescan(ccb);
1127 }
1128 
1129 static void
1130 ahci_notify_events(struct ahci_channel *ch, u_int32_t status)
1131 {
1132 	struct cam_path *dpath;
1133 	int i;
1134 
1135 	if (ch->caps & AHCI_CAP_SSNTF)
1136 		ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status);
1137 	if (bootverbose)
1138 		device_printf(ch->dev, "SNTF 0x%04x\n", status);
1139 	for (i = 0; i < 16; i++) {
1140 		if ((status & (1 << i)) == 0)
1141 			continue;
1142 		if (xpt_create_path(&dpath, NULL,
1143 		    xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) {
1144 			xpt_async(AC_SCSI_AEN, dpath, NULL);
1145 			xpt_free_path(dpath);
1146 		}
1147 	}
1148 }
1149 
1150 static void
1151 ahci_done(struct ahci_channel *ch, union ccb *ccb)
1152 {
1153 
1154 	mtx_assert(&ch->mtx, MA_OWNED);
1155 	if ((ccb->ccb_h.func_code & XPT_FC_QUEUED) == 0 ||
1156 	    ch->batch == 0) {
1157 		xpt_done(ccb);
1158 		return;
1159 	}
1160 
1161 	STAILQ_INSERT_TAIL(&ch->doneq, &ccb->ccb_h, sim_links.stqe);
1162 }
1163 
1164 static void
1165 ahci_ch_intr(void *arg)
1166 {
1167 	struct ahci_channel *ch = (struct ahci_channel *)arg;
1168 	uint32_t istatus;
1169 
1170 	/* Read interrupt statuses. */
1171 	istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1172 	if (istatus == 0)
1173 		return;
1174 
1175 	mtx_lock(&ch->mtx);
1176 	ahci_ch_intr_main(ch, istatus);
1177 	mtx_unlock(&ch->mtx);
1178 }
1179 
1180 static void
1181 ahci_ch_intr_direct(void *arg)
1182 {
1183 	struct ahci_channel *ch = (struct ahci_channel *)arg;
1184 	struct ccb_hdr *ccb_h;
1185 	uint32_t istatus;
1186 	STAILQ_HEAD(, ccb_hdr) tmp_doneq = STAILQ_HEAD_INITIALIZER(tmp_doneq);
1187 
1188 	/* Read interrupt statuses. */
1189 	istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1190 	if (istatus == 0)
1191 		return;
1192 
1193 	mtx_lock(&ch->mtx);
1194 	ch->batch = 1;
1195 	ahci_ch_intr_main(ch, istatus);
1196 	ch->batch = 0;
1197 	/*
1198 	 * Prevent the possibility of issues caused by processing the queue
1199 	 * while unlocked below by moving the contents to a local queue.
1200 	 */
1201 	STAILQ_CONCAT(&tmp_doneq, &ch->doneq);
1202 	mtx_unlock(&ch->mtx);
1203 	while ((ccb_h = STAILQ_FIRST(&tmp_doneq)) != NULL) {
1204 		STAILQ_REMOVE_HEAD(&tmp_doneq, sim_links.stqe);
1205 		xpt_done_direct((union ccb *)ccb_h);
1206 	}
1207 }
1208 
1209 static void
1210 ahci_ch_pm(void *arg)
1211 {
1212 	struct ahci_channel *ch = (struct ahci_channel *)arg;
1213 	uint32_t work;
1214 
1215 	if (ch->numrslots != 0)
1216 		return;
1217 	work = ATA_INL(ch->r_mem, AHCI_P_CMD);
1218 	if (ch->pm_level == 4)
1219 		work |= AHCI_P_CMD_PARTIAL;
1220 	else
1221 		work |= AHCI_P_CMD_SLUMBER;
1222 	ATA_OUTL(ch->r_mem, AHCI_P_CMD, work);
1223 }
1224 
1225 static void
1226 ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus)
1227 {
1228 	uint32_t cstatus, serr = 0, sntf = 0, ok, err;
1229 	enum ahci_err_type et;
1230 	int i, ccs, port, reset = 0;
1231 
1232 	/* Clear interrupt statuses. */
1233 	ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus);
1234 	/* Read command statuses. */
1235 	if (ch->numtslots != 0)
1236 		cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1237 	else
1238 		cstatus = 0;
1239 	if (ch->numrslots != ch->numtslots)
1240 		cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI);
1241 	/* Read SNTF in one of possible ways. */
1242 	if ((istatus & AHCI_P_IX_SDB) &&
1243 	    (ch->pm_present || ch->curr[0].atapi != 0)) {
1244 		if (ch->caps & AHCI_CAP_SSNTF)
1245 			sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF);
1246 		else if (ch->fbs_enabled) {
1247 			u_int8_t *fis = ch->dma.rfis + 0x58;
1248 
1249 			for (i = 0; i < 16; i++) {
1250 				if (fis[1] & 0x80) {
1251 					fis[1] &= 0x7f;
1252 	    				sntf |= 1 << i;
1253 	    			}
1254 	    			fis += 256;
1255 	    		}
1256 		} else {
1257 			u_int8_t *fis = ch->dma.rfis + 0x58;
1258 
1259 			if (fis[1] & 0x80)
1260 				sntf = (1 << (fis[1] & 0x0f));
1261 		}
1262 	}
1263 	/* Process PHY events */
1264 	if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF |
1265 	    AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1266 		serr = ATA_INL(ch->r_mem, AHCI_P_SERR);
1267 		if (serr) {
1268 			ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr);
1269 			reset = ahci_phy_check_events(ch, serr);
1270 		}
1271 	}
1272 	/* Process cold presence detection events */
1273 	if ((istatus & AHCI_P_IX_CPD) && !reset)
1274 		ahci_cpd_check_events(ch);
1275 	/* Process command errors */
1276 	if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF |
1277 	    AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1278 		ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
1279 		    >> AHCI_P_CMD_CCS_SHIFT;
1280 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n",
1281 //    __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD),
1282 //    serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs);
1283 		port = -1;
1284 		if (ch->fbs_enabled) {
1285 			uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS);
1286 			if (fbs & AHCI_P_FBS_SDE) {
1287 				port = (fbs & AHCI_P_FBS_DWE)
1288 				    >> AHCI_P_FBS_DWE_SHIFT;
1289 			} else {
1290 				for (i = 0; i < 16; i++) {
1291 					if (ch->numrslotspd[i] == 0)
1292 						continue;
1293 					if (port == -1)
1294 						port = i;
1295 					else if (port != i) {
1296 						port = -2;
1297 						break;
1298 					}
1299 				}
1300 			}
1301 		}
1302 		err = ch->rslots & cstatus;
1303 	} else {
1304 		ccs = 0;
1305 		err = 0;
1306 		port = -1;
1307 	}
1308 	/* Complete all successful commands. */
1309 	ok = ch->rslots & ~cstatus;
1310 	for (i = 0; i < ch->numslots; i++) {
1311 		if ((ok >> i) & 1)
1312 			ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE);
1313 	}
1314 	/* On error, complete the rest of commands with error statuses. */
1315 	if (err) {
1316 		if (ch->frozen) {
1317 			union ccb *fccb = ch->frozen;
1318 			ch->frozen = NULL;
1319 			fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1320 			if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1321 				xpt_freeze_devq(fccb->ccb_h.path, 1);
1322 				fccb->ccb_h.status |= CAM_DEV_QFRZN;
1323 			}
1324 			ahci_done(ch, fccb);
1325 		}
1326 		for (i = 0; i < ch->numslots; i++) {
1327 			/* XXX: reqests in loading state. */
1328 			if (((err >> i) & 1) == 0)
1329 				continue;
1330 			if (port >= 0 &&
1331 			    ch->slot[i].ccb->ccb_h.target_id != port)
1332 				continue;
1333 			if (istatus & AHCI_P_IX_TFE) {
1334 			    if (port != -2) {
1335 				/* Task File Error */
1336 				if (ch->numtslotspd[
1337 				    ch->slot[i].ccb->ccb_h.target_id] == 0) {
1338 					/* Untagged operation. */
1339 					if (i == ccs)
1340 						et = AHCI_ERR_TFE;
1341 					else
1342 						et = AHCI_ERR_INNOCENT;
1343 				} else {
1344 					/* Tagged operation. */
1345 					et = AHCI_ERR_NCQ;
1346 				}
1347 			    } else {
1348 				et = AHCI_ERR_TFE;
1349 				ch->fatalerr = 1;
1350 			    }
1351 			} else if (istatus & AHCI_P_IX_IF) {
1352 				if (ch->numtslots == 0 && i != ccs && port != -2)
1353 					et = AHCI_ERR_INNOCENT;
1354 				else
1355 					et = AHCI_ERR_SATA;
1356 			} else
1357 				et = AHCI_ERR_INVALID;
1358 			ahci_end_transaction(&ch->slot[i], et);
1359 		}
1360 		/*
1361 		 * We can't reinit port if there are some other
1362 		 * commands active, use resume to complete them.
1363 		 */
1364 		if (ch->rslots != 0 && !ch->recoverycmd)
1365 			ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC);
1366 	}
1367 	/* Process NOTIFY events */
1368 	if (sntf)
1369 		ahci_notify_events(ch, sntf);
1370 }
1371 
1372 /* Must be called with channel locked. */
1373 static int
1374 ahci_check_collision(struct ahci_channel *ch, union ccb *ccb)
1375 {
1376 	int t = ccb->ccb_h.target_id;
1377 
1378 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1379 	    (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1380 		/* Tagged command while we have no supported tag free. */
1381 		if (((~ch->oslots) & (0xffffffff >> (32 -
1382 		    ch->curr[t].tags))) == 0)
1383 			return (1);
1384 		/* If we have FBS */
1385 		if (ch->fbs_enabled) {
1386 			/* Tagged command while untagged are active. */
1387 			if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0)
1388 				return (1);
1389 		} else {
1390 			/* Tagged command while untagged are active. */
1391 			if (ch->numrslots != 0 && ch->numtslots == 0)
1392 				return (1);
1393 			/* Tagged command while tagged to other target is active. */
1394 			if (ch->numtslots != 0 &&
1395 			    ch->taggedtarget != ccb->ccb_h.target_id)
1396 				return (1);
1397 		}
1398 	} else {
1399 		/* If we have FBS */
1400 		if (ch->fbs_enabled) {
1401 			/* Untagged command while tagged are active. */
1402 			if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0)
1403 				return (1);
1404 		} else {
1405 			/* Untagged command while tagged are active. */
1406 			if (ch->numrslots != 0 && ch->numtslots != 0)
1407 				return (1);
1408 		}
1409 	}
1410 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1411 	    (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) {
1412 		/* Atomic command while anything active. */
1413 		if (ch->numrslots != 0)
1414 			return (1);
1415 	}
1416        /* We have some atomic command running. */
1417        if (ch->aslots != 0)
1418                return (1);
1419 	return (0);
1420 }
1421 
1422 /* Must be called with channel locked. */
1423 static void
1424 ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb)
1425 {
1426 	struct ahci_slot *slot;
1427 	int tag, tags;
1428 
1429 	/* Choose empty slot. */
1430 	tags = ch->numslots;
1431 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1432 	    (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA))
1433 		tags = ch->curr[ccb->ccb_h.target_id].tags;
1434 	if (ch->lastslot + 1 < tags)
1435 		tag = ffs(~(ch->oslots >> (ch->lastslot + 1)));
1436 	else
1437 		tag = 0;
1438 	if (tag == 0 || tag + ch->lastslot >= tags)
1439 		tag = ffs(~ch->oslots) - 1;
1440 	else
1441 		tag += ch->lastslot;
1442 	ch->lastslot = tag;
1443 	/* Occupy chosen slot. */
1444 	slot = &ch->slot[tag];
1445 	slot->ccb = ccb;
1446 	/* Stop PM timer. */
1447 	if (ch->numrslots == 0 && ch->pm_level > 3)
1448 		callout_stop(&ch->pm_timer);
1449 	/* Update channel stats. */
1450 	ch->oslots |= (1 << tag);
1451 	ch->numrslots++;
1452 	ch->numrslotspd[ccb->ccb_h.target_id]++;
1453 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1454 	    (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1455 		ch->numtslots++;
1456 		ch->numtslotspd[ccb->ccb_h.target_id]++;
1457 		ch->taggedtarget = ccb->ccb_h.target_id;
1458 	}
1459 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1460 	    (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)))
1461 		ch->aslots |= (1 << tag);
1462 	if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1463 		slot->state = AHCI_SLOT_LOADING;
1464 		bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb,
1465 		    ahci_dmasetprd, slot, 0);
1466 	} else {
1467 		slot->dma.nsegs = 0;
1468 		ahci_execute_transaction(slot);
1469 	}
1470 }
1471 
1472 /* Locked by busdma engine. */
1473 static void
1474 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1475 {
1476 	struct ahci_slot *slot = arg;
1477 	struct ahci_channel *ch = slot->ch;
1478 	struct ahci_cmd_tab *ctp;
1479 	struct ahci_dma_prd *prd;
1480 	int i;
1481 
1482 	if (error) {
1483 		device_printf(ch->dev, "DMA load error\n");
1484 		ahci_end_transaction(slot, AHCI_ERR_INVALID);
1485 		return;
1486 	}
1487 	KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n"));
1488 	/* Get a piece of the workspace for this request */
1489 	ctp = (struct ahci_cmd_tab *)
1490 		(ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1491 	/* Fill S/G table */
1492 	prd = &ctp->prd_tab[0];
1493 	for (i = 0; i < nsegs; i++) {
1494 		prd[i].dba = htole64(segs[i].ds_addr);
1495 		prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK);
1496 	}
1497 	slot->dma.nsegs = nsegs;
1498 	bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1499 	    ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ?
1500 	    BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
1501 	ahci_execute_transaction(slot);
1502 }
1503 
1504 /* Must be called with channel locked. */
1505 static void
1506 ahci_execute_transaction(struct ahci_slot *slot)
1507 {
1508 	struct ahci_channel *ch = slot->ch;
1509 	struct ahci_cmd_tab *ctp;
1510 	struct ahci_cmd_list *clp;
1511 	union ccb *ccb = slot->ccb;
1512 	int port = ccb->ccb_h.target_id & 0x0f;
1513 	int fis_size, i, softreset;
1514 	uint8_t *fis = ch->dma.rfis + 0x40;
1515 	uint8_t val;
1516 
1517 	/* Get a piece of the workspace for this request */
1518 	ctp = (struct ahci_cmd_tab *)
1519 		(ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1520 	/* Setup the FIS for this request */
1521 	if (!(fis_size = ahci_setup_fis(ch, ctp, ccb, slot->slot))) {
1522 		device_printf(ch->dev, "Setting up SATA FIS failed\n");
1523 		ahci_end_transaction(slot, AHCI_ERR_INVALID);
1524 		return;
1525 	}
1526 	/* Setup the command list entry */
1527 	clp = (struct ahci_cmd_list *)
1528 	    (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1529 	clp->cmd_flags = htole16(
1530 		    (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) |
1531 		    (ccb->ccb_h.func_code == XPT_SCSI_IO ?
1532 		     (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) |
1533 		    (fis_size / sizeof(u_int32_t)) |
1534 		    (port << 12));
1535 	clp->prd_length = htole16(slot->dma.nsegs);
1536 	/* Special handling for Soft Reset command. */
1537 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1538 	    (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) {
1539 		if (ccb->ataio.cmd.control & ATA_A_RESET) {
1540 			softreset = 1;
1541 			/* Kick controller into sane state */
1542 			ahci_stop(ch);
1543 			ahci_clo(ch);
1544 			ahci_start(ch, 0);
1545 			clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY;
1546 		} else {
1547 			softreset = 2;
1548 			/* Prepare FIS receive area for check. */
1549 			for (i = 0; i < 20; i++)
1550 				fis[i] = 0xff;
1551 		}
1552 	} else
1553 		softreset = 0;
1554 	clp->bytecount = 0;
1555 	clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET +
1556 				  (AHCI_CT_SIZE * slot->slot));
1557 	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1558 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1559 	bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1560 	    BUS_DMASYNC_PREREAD);
1561 	/* Set ACTIVE bit for NCQ commands. */
1562 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1563 	    (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1564 		ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot);
1565 	}
1566 	/* If FBS is enabled, set PMP port. */
1567 	if (ch->fbs_enabled) {
1568 		ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN |
1569 		    (port << AHCI_P_FBS_DEV_SHIFT));
1570 	}
1571 	/* Issue command to the controller. */
1572 	slot->state = AHCI_SLOT_RUNNING;
1573 	ch->rslots |= (1 << slot->slot);
1574 	ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot));
1575 	/* Device reset commands doesn't interrupt. Poll them. */
1576 	if (ccb->ccb_h.func_code == XPT_ATA_IO &&
1577 	    (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) {
1578 		int count, timeout = ccb->ccb_h.timeout * 100;
1579 		enum ahci_err_type et = AHCI_ERR_NONE;
1580 
1581 		for (count = 0; count < timeout; count++) {
1582 			DELAY(10);
1583 			if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot)))
1584 				break;
1585 			if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) &&
1586 			    softreset != 1) {
1587 #if 0
1588 				device_printf(ch->dev,
1589 				    "Poll error on slot %d, TFD: %04x\n",
1590 				    slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD));
1591 #endif
1592 				et = AHCI_ERR_TFE;
1593 				break;
1594 			}
1595 			/* Workaround for ATI SB600/SB700 chipsets. */
1596 			if (ccb->ccb_h.target_id == 15 &&
1597 			    (ch->quirks & AHCI_Q_ATI_PMP_BUG) &&
1598 			    (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) {
1599 				et = AHCI_ERR_TIMEOUT;
1600 				break;
1601 			}
1602 		}
1603 
1604 		/*
1605 		 * Marvell HBAs with non-RAID firmware do not wait for
1606 		 * readiness after soft reset, so we have to wait here.
1607 		 * Marvell RAIDs do not have this problem, but instead
1608 		 * sometimes forget to update FIS receive area, breaking
1609 		 * this wait.
1610 		 */
1611 		if ((ch->quirks & AHCI_Q_NOBSYRES) == 0 &&
1612 		    (ch->quirks & AHCI_Q_ATI_PMP_BUG) == 0 &&
1613 		    softreset == 2 && et == AHCI_ERR_NONE) {
1614 			for ( ; count < timeout; count++) {
1615 				bus_dmamap_sync(ch->dma.rfis_tag,
1616 				    ch->dma.rfis_map, BUS_DMASYNC_POSTREAD);
1617 				val = fis[2];
1618 				bus_dmamap_sync(ch->dma.rfis_tag,
1619 				    ch->dma.rfis_map, BUS_DMASYNC_PREREAD);
1620 				if ((val & ATA_S_BUSY) == 0)
1621 					break;
1622 				DELAY(10);
1623 			}
1624 		}
1625 
1626 		if (timeout && (count >= timeout)) {
1627 			device_printf(ch->dev, "Poll timeout on slot %d port %d\n",
1628 			    slot->slot, port);
1629 			device_printf(ch->dev, "is %08x cs %08x ss %08x "
1630 			    "rs %08x tfd %02x serr %08x cmd %08x\n",
1631 			    ATA_INL(ch->r_mem, AHCI_P_IS),
1632 			    ATA_INL(ch->r_mem, AHCI_P_CI),
1633 			    ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1634 			    ATA_INL(ch->r_mem, AHCI_P_TFD),
1635 			    ATA_INL(ch->r_mem, AHCI_P_SERR),
1636 			    ATA_INL(ch->r_mem, AHCI_P_CMD));
1637 			et = AHCI_ERR_TIMEOUT;
1638 		}
1639 
1640 		/* Kick controller into sane state and enable FBS. */
1641 		if (softreset == 2)
1642 			ch->eslots |= (1 << slot->slot);
1643 		ahci_end_transaction(slot, et);
1644 		return;
1645 	}
1646 	/* Start command execution timeout */
1647 	callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout / 2,
1648 	    0, (timeout_t*)ahci_timeout, slot, 0);
1649 	return;
1650 }
1651 
1652 /* Must be called with channel locked. */
1653 static void
1654 ahci_process_timeout(struct ahci_channel *ch)
1655 {
1656 	int i;
1657 
1658 	mtx_assert(&ch->mtx, MA_OWNED);
1659 	/* Handle the rest of commands. */
1660 	for (i = 0; i < ch->numslots; i++) {
1661 		/* Do we have a running request on slot? */
1662 		if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1663 			continue;
1664 		ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT);
1665 	}
1666 }
1667 
1668 /* Must be called with channel locked. */
1669 static void
1670 ahci_rearm_timeout(struct ahci_channel *ch)
1671 {
1672 	int i;
1673 
1674 	mtx_assert(&ch->mtx, MA_OWNED);
1675 	for (i = 0; i < ch->numslots; i++) {
1676 		struct ahci_slot *slot = &ch->slot[i];
1677 
1678 		/* Do we have a running request on slot? */
1679 		if (slot->state < AHCI_SLOT_RUNNING)
1680 			continue;
1681 		if ((ch->toslots & (1 << i)) == 0)
1682 			continue;
1683 		callout_reset_sbt(&slot->timeout,
1684     	    	    SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0,
1685 		    (timeout_t*)ahci_timeout, slot, 0);
1686 	}
1687 }
1688 
1689 /* Locked by callout mechanism. */
1690 static void
1691 ahci_timeout(struct ahci_slot *slot)
1692 {
1693 	struct ahci_channel *ch = slot->ch;
1694 	device_t dev = ch->dev;
1695 	uint32_t sstatus;
1696 	int ccs;
1697 	int i;
1698 
1699 	/* Check for stale timeout. */
1700 	if (slot->state < AHCI_SLOT_RUNNING)
1701 		return;
1702 
1703 	/* Check if slot was not being executed last time we checked. */
1704 	if (slot->state < AHCI_SLOT_EXECUTING) {
1705 		/* Check if slot started executing. */
1706 		sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1707 		ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
1708 		    >> AHCI_P_CMD_CCS_SHIFT;
1709 		if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot ||
1710 		    ch->fbs_enabled || ch->wrongccs)
1711 			slot->state = AHCI_SLOT_EXECUTING;
1712 		else if ((ch->rslots & (1 << ccs)) == 0) {
1713 			ch->wrongccs = 1;
1714 			slot->state = AHCI_SLOT_EXECUTING;
1715 		}
1716 
1717 		callout_reset_sbt(&slot->timeout,
1718 	    	    SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0,
1719 		    (timeout_t*)ahci_timeout, slot, 0);
1720 		return;
1721 	}
1722 
1723 	device_printf(dev, "Timeout on slot %d port %d\n",
1724 	    slot->slot, slot->ccb->ccb_h.target_id & 0x0f);
1725 	device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x "
1726 	    "serr %08x cmd %08x\n",
1727 	    ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI),
1728 	    ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1729 	    ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR),
1730 	    ATA_INL(ch->r_mem, AHCI_P_CMD));
1731 
1732 	/* Handle frozen command. */
1733 	if (ch->frozen) {
1734 		union ccb *fccb = ch->frozen;
1735 		ch->frozen = NULL;
1736 		fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1737 		if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1738 			xpt_freeze_devq(fccb->ccb_h.path, 1);
1739 			fccb->ccb_h.status |= CAM_DEV_QFRZN;
1740 		}
1741 		ahci_done(ch, fccb);
1742 	}
1743 	if (!ch->fbs_enabled && !ch->wrongccs) {
1744 		/* Without FBS we know real timeout source. */
1745 		ch->fatalerr = 1;
1746 		/* Handle command with timeout. */
1747 		ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT);
1748 		/* Handle the rest of commands. */
1749 		for (i = 0; i < ch->numslots; i++) {
1750 			/* Do we have a running request on slot? */
1751 			if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1752 				continue;
1753 			ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
1754 		}
1755 	} else {
1756 		/* With FBS we wait for other commands timeout and pray. */
1757 		if (ch->toslots == 0)
1758 			xpt_freeze_simq(ch->sim, 1);
1759 		ch->toslots |= (1 << slot->slot);
1760 		if ((ch->rslots & ~ch->toslots) == 0)
1761 			ahci_process_timeout(ch);
1762 		else
1763 			device_printf(dev, " ... waiting for slots %08x\n",
1764 			    ch->rslots & ~ch->toslots);
1765 	}
1766 }
1767 
1768 /* Must be called with channel locked. */
1769 static void
1770 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et)
1771 {
1772 	struct ahci_channel *ch = slot->ch;
1773 	union ccb *ccb = slot->ccb;
1774 	struct ahci_cmd_list *clp;
1775 	int lastto;
1776 	uint32_t sig;
1777 
1778 	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1779 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1780 	clp = (struct ahci_cmd_list *)
1781 	    (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1782 	/* Read result registers to the result struct
1783 	 * May be incorrect if several commands finished same time,
1784 	 * so read only when sure or have to.
1785 	 */
1786 	if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1787 		struct ata_res *res = &ccb->ataio.res;
1788 
1789 		if ((et == AHCI_ERR_TFE) ||
1790 		    (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) {
1791 			u_int8_t *fis = ch->dma.rfis + 0x40;
1792 
1793 			bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1794 			    BUS_DMASYNC_POSTREAD);
1795 			if (ch->fbs_enabled) {
1796 				fis += ccb->ccb_h.target_id * 256;
1797 				res->status = fis[2];
1798 				res->error = fis[3];
1799 			} else {
1800 				uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD);
1801 
1802 				res->status = tfd;
1803 				res->error = tfd >> 8;
1804 			}
1805 			res->lba_low = fis[4];
1806 			res->lba_mid = fis[5];
1807 			res->lba_high = fis[6];
1808 			res->device = fis[7];
1809 			res->lba_low_exp = fis[8];
1810 			res->lba_mid_exp = fis[9];
1811 			res->lba_high_exp = fis[10];
1812 			res->sector_count = fis[12];
1813 			res->sector_count_exp = fis[13];
1814 
1815 			/*
1816 			 * Some weird controllers do not return signature in
1817 			 * FIS receive area. Read it from PxSIG register.
1818 			 */
1819 			if ((ch->quirks & AHCI_Q_ALTSIG) &&
1820 			    (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
1821 			    (ccb->ataio.cmd.control & ATA_A_RESET) == 0) {
1822 				sig = ATA_INL(ch->r_mem,  AHCI_P_SIG);
1823 				res->lba_high = sig >> 24;
1824 				res->lba_mid = sig >> 16;
1825 				res->lba_low = sig >> 8;
1826 				res->sector_count = sig;
1827 			}
1828 		} else
1829 			bzero(res, sizeof(*res));
1830 		if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 &&
1831 		    (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
1832 		    (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
1833 			ccb->ataio.resid =
1834 			    ccb->ataio.dxfer_len - le32toh(clp->bytecount);
1835 		}
1836 	} else {
1837 		if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
1838 		    (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
1839 			ccb->csio.resid =
1840 			    ccb->csio.dxfer_len - le32toh(clp->bytecount);
1841 		}
1842 	}
1843 	if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1844 		bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1845 		    (ccb->ccb_h.flags & CAM_DIR_IN) ?
1846 		    BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1847 		bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map);
1848 	}
1849 	if (et != AHCI_ERR_NONE)
1850 		ch->eslots |= (1 << slot->slot);
1851 	/* In case of error, freeze device for proper recovery. */
1852 	if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) &&
1853 	    !(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
1854 		xpt_freeze_devq(ccb->ccb_h.path, 1);
1855 		ccb->ccb_h.status |= CAM_DEV_QFRZN;
1856 	}
1857 	/* Set proper result status. */
1858 	ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1859 	switch (et) {
1860 	case AHCI_ERR_NONE:
1861 		ccb->ccb_h.status |= CAM_REQ_CMP;
1862 		if (ccb->ccb_h.func_code == XPT_SCSI_IO)
1863 			ccb->csio.scsi_status = SCSI_STATUS_OK;
1864 		break;
1865 	case AHCI_ERR_INVALID:
1866 		ch->fatalerr = 1;
1867 		ccb->ccb_h.status |= CAM_REQ_INVALID;
1868 		break;
1869 	case AHCI_ERR_INNOCENT:
1870 		ccb->ccb_h.status |= CAM_REQUEUE_REQ;
1871 		break;
1872 	case AHCI_ERR_TFE:
1873 	case AHCI_ERR_NCQ:
1874 		if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
1875 			ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
1876 			ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
1877 		} else {
1878 			ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
1879 		}
1880 		break;
1881 	case AHCI_ERR_SATA:
1882 		ch->fatalerr = 1;
1883 		if (!ch->recoverycmd) {
1884 			xpt_freeze_simq(ch->sim, 1);
1885 			ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1886 			ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
1887 		}
1888 		ccb->ccb_h.status |= CAM_UNCOR_PARITY;
1889 		break;
1890 	case AHCI_ERR_TIMEOUT:
1891 		if (!ch->recoverycmd) {
1892 			xpt_freeze_simq(ch->sim, 1);
1893 			ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1894 			ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
1895 		}
1896 		ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
1897 		break;
1898 	default:
1899 		ch->fatalerr = 1;
1900 		ccb->ccb_h.status |= CAM_REQ_CMP_ERR;
1901 	}
1902 	/* Free slot. */
1903 	ch->oslots &= ~(1 << slot->slot);
1904 	ch->rslots &= ~(1 << slot->slot);
1905 	ch->aslots &= ~(1 << slot->slot);
1906 	slot->state = AHCI_SLOT_EMPTY;
1907 	slot->ccb = NULL;
1908 	/* Update channel stats. */
1909 	ch->numrslots--;
1910 	ch->numrslotspd[ccb->ccb_h.target_id]--;
1911 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1912 	    (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1913 		ch->numtslots--;
1914 		ch->numtslotspd[ccb->ccb_h.target_id]--;
1915 	}
1916 	/* Cancel timeout state if request completed normally. */
1917 	if (et != AHCI_ERR_TIMEOUT) {
1918 		lastto = (ch->toslots == (1 << slot->slot));
1919 		ch->toslots &= ~(1 << slot->slot);
1920 		if (lastto)
1921 			xpt_release_simq(ch->sim, TRUE);
1922 	}
1923 	/* If it was first request of reset sequence and there is no error,
1924 	 * proceed to second request. */
1925 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1926 	    (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
1927 	    (ccb->ataio.cmd.control & ATA_A_RESET) &&
1928 	    et == AHCI_ERR_NONE) {
1929 		ccb->ataio.cmd.control &= ~ATA_A_RESET;
1930 		ahci_begin_transaction(ch, ccb);
1931 		return;
1932 	}
1933 	/* If it was our READ LOG command - process it. */
1934 	if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) {
1935 		ahci_process_read_log(ch, ccb);
1936 	/* If it was our REQUEST SENSE command - process it. */
1937 	} else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) {
1938 		ahci_process_request_sense(ch, ccb);
1939 	/* If it was NCQ or ATAPI command error, put result on hold. */
1940 	} else if (et == AHCI_ERR_NCQ ||
1941 	    ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR &&
1942 	     (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) {
1943 		ch->hold[slot->slot] = ccb;
1944 		ch->numhslots++;
1945 	} else
1946 		ahci_done(ch, ccb);
1947 	/* If we have no other active commands, ... */
1948 	if (ch->rslots == 0) {
1949 		/* if there was fatal error - reset port. */
1950 		if (ch->toslots != 0 || ch->fatalerr) {
1951 			ahci_reset(ch);
1952 		} else {
1953 			/* if we have slots in error, we can reinit port. */
1954 			if (ch->eslots != 0) {
1955 				ahci_stop(ch);
1956 				ahci_clo(ch);
1957 				ahci_start(ch, 1);
1958 			}
1959 			/* if there commands on hold, we can do READ LOG. */
1960 			if (!ch->recoverycmd && ch->numhslots)
1961 				ahci_issue_recovery(ch);
1962 		}
1963 	/* If all the rest of commands are in timeout - give them chance. */
1964 	} else if ((ch->rslots & ~ch->toslots) == 0 &&
1965 	    et != AHCI_ERR_TIMEOUT)
1966 		ahci_rearm_timeout(ch);
1967 	/* Unfreeze frozen command. */
1968 	if (ch->frozen && !ahci_check_collision(ch, ch->frozen)) {
1969 		union ccb *fccb = ch->frozen;
1970 		ch->frozen = NULL;
1971 		ahci_begin_transaction(ch, fccb);
1972 		xpt_release_simq(ch->sim, TRUE);
1973 	}
1974 	/* Start PM timer. */
1975 	if (ch->numrslots == 0 && ch->pm_level > 3 &&
1976 	    (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) {
1977 		callout_schedule(&ch->pm_timer,
1978 		    (ch->pm_level == 4) ? hz / 1000 : hz / 8);
1979 	}
1980 }
1981 
1982 static void
1983 ahci_issue_recovery(struct ahci_channel *ch)
1984 {
1985 	union ccb *ccb;
1986 	struct ccb_ataio *ataio;
1987 	struct ccb_scsiio *csio;
1988 	int i;
1989 
1990 	/* Find some held command. */
1991 	for (i = 0; i < ch->numslots; i++) {
1992 		if (ch->hold[i])
1993 			break;
1994 	}
1995 	ccb = xpt_alloc_ccb_nowait();
1996 	if (ccb == NULL) {
1997 		device_printf(ch->dev, "Unable to allocate recovery command\n");
1998 completeall:
1999 		/* We can't do anything -- complete held commands. */
2000 		for (i = 0; i < ch->numslots; i++) {
2001 			if (ch->hold[i] == NULL)
2002 				continue;
2003 			ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2004 			ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL;
2005 			ahci_done(ch, ch->hold[i]);
2006 			ch->hold[i] = NULL;
2007 			ch->numhslots--;
2008 		}
2009 		ahci_reset(ch);
2010 		return;
2011 	}
2012 	ccb->ccb_h = ch->hold[i]->ccb_h;	/* Reuse old header. */
2013 	if (ccb->ccb_h.func_code == XPT_ATA_IO) {
2014 		/* READ LOG */
2015 		ccb->ccb_h.recovery_type = RECOVERY_READ_LOG;
2016 		ccb->ccb_h.func_code = XPT_ATA_IO;
2017 		ccb->ccb_h.flags = CAM_DIR_IN;
2018 		ccb->ccb_h.timeout = 1000;	/* 1s should be enough. */
2019 		ataio = &ccb->ataio;
2020 		ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT);
2021 		if (ataio->data_ptr == NULL) {
2022 			xpt_free_ccb(ccb);
2023 			device_printf(ch->dev,
2024 			    "Unable to allocate memory for READ LOG command\n");
2025 			goto completeall;
2026 		}
2027 		ataio->dxfer_len = 512;
2028 		bzero(&ataio->cmd, sizeof(ataio->cmd));
2029 		ataio->cmd.flags = CAM_ATAIO_48BIT;
2030 		ataio->cmd.command = 0x2F;	/* READ LOG EXT */
2031 		ataio->cmd.sector_count = 1;
2032 		ataio->cmd.sector_count_exp = 0;
2033 		ataio->cmd.lba_low = 0x10;
2034 		ataio->cmd.lba_mid = 0;
2035 		ataio->cmd.lba_mid_exp = 0;
2036 	} else {
2037 		/* REQUEST SENSE */
2038 		ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE;
2039 		ccb->ccb_h.recovery_slot = i;
2040 		ccb->ccb_h.func_code = XPT_SCSI_IO;
2041 		ccb->ccb_h.flags = CAM_DIR_IN;
2042 		ccb->ccb_h.status = 0;
2043 		ccb->ccb_h.timeout = 1000;	/* 1s should be enough. */
2044 		csio = &ccb->csio;
2045 		csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data;
2046 		csio->dxfer_len = ch->hold[i]->csio.sense_len;
2047 		csio->cdb_len = 6;
2048 		bzero(&csio->cdb_io, sizeof(csio->cdb_io));
2049 		csio->cdb_io.cdb_bytes[0] = 0x03;
2050 		csio->cdb_io.cdb_bytes[4] = csio->dxfer_len;
2051 	}
2052 	/* Freeze SIM while doing recovery. */
2053 	ch->recoverycmd = 1;
2054 	xpt_freeze_simq(ch->sim, 1);
2055 	ahci_begin_transaction(ch, ccb);
2056 }
2057 
2058 static void
2059 ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb)
2060 {
2061 	uint8_t *data;
2062 	struct ata_res *res;
2063 	int i;
2064 
2065 	ch->recoverycmd = 0;
2066 
2067 	data = ccb->ataio.data_ptr;
2068 	if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP &&
2069 	    (data[0] & 0x80) == 0) {
2070 		for (i = 0; i < ch->numslots; i++) {
2071 			if (!ch->hold[i])
2072 				continue;
2073 			if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2074 				continue;
2075 			if ((data[0] & 0x1F) == i) {
2076 				res = &ch->hold[i]->ataio.res;
2077 				res->status = data[2];
2078 				res->error = data[3];
2079 				res->lba_low = data[4];
2080 				res->lba_mid = data[5];
2081 				res->lba_high = data[6];
2082 				res->device = data[7];
2083 				res->lba_low_exp = data[8];
2084 				res->lba_mid_exp = data[9];
2085 				res->lba_high_exp = data[10];
2086 				res->sector_count = data[12];
2087 				res->sector_count_exp = data[13];
2088 			} else {
2089 				ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2090 				ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ;
2091 			}
2092 			ahci_done(ch, ch->hold[i]);
2093 			ch->hold[i] = NULL;
2094 			ch->numhslots--;
2095 		}
2096 	} else {
2097 		if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP)
2098 			device_printf(ch->dev, "Error while READ LOG EXT\n");
2099 		else if ((data[0] & 0x80) == 0) {
2100 			device_printf(ch->dev, "Non-queued command error in READ LOG EXT\n");
2101 		}
2102 		for (i = 0; i < ch->numslots; i++) {
2103 			if (!ch->hold[i])
2104 				continue;
2105 			if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2106 				continue;
2107 			ahci_done(ch, ch->hold[i]);
2108 			ch->hold[i] = NULL;
2109 			ch->numhslots--;
2110 		}
2111 	}
2112 	free(ccb->ataio.data_ptr, M_AHCI);
2113 	xpt_free_ccb(ccb);
2114 	xpt_release_simq(ch->sim, TRUE);
2115 }
2116 
2117 static void
2118 ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb)
2119 {
2120 	int i;
2121 
2122 	ch->recoverycmd = 0;
2123 
2124 	i = ccb->ccb_h.recovery_slot;
2125 	if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) {
2126 		ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID;
2127 	} else {
2128 		ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2129 		ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL;
2130 	}
2131 	ahci_done(ch, ch->hold[i]);
2132 	ch->hold[i] = NULL;
2133 	ch->numhslots--;
2134 	xpt_free_ccb(ccb);
2135 	xpt_release_simq(ch->sim, TRUE);
2136 }
2137 
2138 static void
2139 ahci_start(struct ahci_channel *ch, int fbs)
2140 {
2141 	u_int32_t cmd;
2142 
2143 	/* Run the channel start callback, if any. */
2144 	if (ch->start)
2145 		ch->start(ch);
2146 
2147 	/* Clear SATA error register */
2148 	ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF);
2149 	/* Clear any interrupts pending on this channel */
2150 	ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF);
2151 	/* Configure FIS-based switching if supported. */
2152 	if (ch->chcaps & AHCI_P_CMD_FBSCP) {
2153 		ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0;
2154 		ATA_OUTL(ch->r_mem, AHCI_P_FBS,
2155 		    ch->fbs_enabled ? AHCI_P_FBS_EN : 0);
2156 	}
2157 	/* Start operations on this channel */
2158 	cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2159 	cmd &= ~AHCI_P_CMD_PMA;
2160 	ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST |
2161 	    (ch->pm_present ? AHCI_P_CMD_PMA : 0));
2162 }
2163 
2164 static void
2165 ahci_stop(struct ahci_channel *ch)
2166 {
2167 	u_int32_t cmd;
2168 	int timeout;
2169 
2170 	/* Kill all activity on this channel */
2171 	cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2172 	ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST);
2173 	/* Wait for activity stop. */
2174 	timeout = 0;
2175 	do {
2176 		DELAY(10);
2177 		if (timeout++ > 50000) {
2178 			device_printf(ch->dev, "stopping AHCI engine failed\n");
2179 			break;
2180 		}
2181 	} while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR);
2182 	ch->eslots = 0;
2183 }
2184 
2185 static void
2186 ahci_clo(struct ahci_channel *ch)
2187 {
2188 	u_int32_t cmd;
2189 	int timeout;
2190 
2191 	/* Issue Command List Override if supported */
2192 	if (ch->caps & AHCI_CAP_SCLO) {
2193 		cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2194 		cmd |= AHCI_P_CMD_CLO;
2195 		ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd);
2196 		timeout = 0;
2197 		do {
2198 			DELAY(10);
2199 			if (timeout++ > 50000) {
2200 			    device_printf(ch->dev, "executing CLO failed\n");
2201 			    break;
2202 			}
2203 		} while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO);
2204 	}
2205 }
2206 
2207 static void
2208 ahci_stop_fr(struct ahci_channel *ch)
2209 {
2210 	u_int32_t cmd;
2211 	int timeout;
2212 
2213 	/* Kill all FIS reception on this channel */
2214 	cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2215 	ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE);
2216 	/* Wait for FIS reception stop. */
2217 	timeout = 0;
2218 	do {
2219 		DELAY(10);
2220 		if (timeout++ > 50000) {
2221 			device_printf(ch->dev, "stopping AHCI FR engine failed\n");
2222 			break;
2223 		}
2224 	} while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR);
2225 }
2226 
2227 static void
2228 ahci_start_fr(struct ahci_channel *ch)
2229 {
2230 	u_int32_t cmd;
2231 
2232 	/* Start FIS reception on this channel */
2233 	cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2234 	ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE);
2235 }
2236 
2237 static int
2238 ahci_wait_ready(struct ahci_channel *ch, int t, int t0)
2239 {
2240 	int timeout = 0;
2241 	uint32_t val;
2242 
2243 	while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) &
2244 	    (ATA_S_BUSY | ATA_S_DRQ)) {
2245 		if (timeout > t) {
2246 			if (t != 0) {
2247 				device_printf(ch->dev,
2248 				    "AHCI reset: device not ready after %dms "
2249 				    "(tfd = %08x)\n",
2250 				    MAX(t, 0) + t0, val);
2251 			}
2252 			return (EBUSY);
2253 		}
2254 		DELAY(1000);
2255 		timeout++;
2256 	}
2257 	if (bootverbose)
2258 		device_printf(ch->dev, "AHCI reset: device ready after %dms\n",
2259 		    timeout + t0);
2260 	return (0);
2261 }
2262 
2263 static void
2264 ahci_reset_to(void *arg)
2265 {
2266 	struct ahci_channel *ch = arg;
2267 
2268 	if (ch->resetting == 0)
2269 		return;
2270 	ch->resetting--;
2271 	if (ahci_wait_ready(ch, ch->resetting == 0 ? -1 : 0,
2272 	    (310 - ch->resetting) * 100) == 0) {
2273 		ch->resetting = 0;
2274 		ahci_start(ch, 1);
2275 		xpt_release_simq(ch->sim, TRUE);
2276 		return;
2277 	}
2278 	if (ch->resetting == 0) {
2279 		ahci_clo(ch);
2280 		ahci_start(ch, 1);
2281 		xpt_release_simq(ch->sim, TRUE);
2282 		return;
2283 	}
2284 	callout_schedule(&ch->reset_timer, hz / 10);
2285 }
2286 
2287 static void
2288 ahci_reset(struct ahci_channel *ch)
2289 {
2290 	struct ahci_controller *ctlr = device_get_softc(device_get_parent(ch->dev));
2291 	int i;
2292 
2293 	xpt_freeze_simq(ch->sim, 1);
2294 	if (bootverbose)
2295 		device_printf(ch->dev, "AHCI reset...\n");
2296 	/* Forget about previous reset. */
2297 	if (ch->resetting) {
2298 		ch->resetting = 0;
2299 		callout_stop(&ch->reset_timer);
2300 		xpt_release_simq(ch->sim, TRUE);
2301 	}
2302 	/* Requeue freezed command. */
2303 	if (ch->frozen) {
2304 		union ccb *fccb = ch->frozen;
2305 		ch->frozen = NULL;
2306 		fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
2307 		if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
2308 			xpt_freeze_devq(fccb->ccb_h.path, 1);
2309 			fccb->ccb_h.status |= CAM_DEV_QFRZN;
2310 		}
2311 		ahci_done(ch, fccb);
2312 	}
2313 	/* Kill the engine and requeue all running commands. */
2314 	ahci_stop(ch);
2315 	for (i = 0; i < ch->numslots; i++) {
2316 		/* Do we have a running request on slot? */
2317 		if (ch->slot[i].state < AHCI_SLOT_RUNNING)
2318 			continue;
2319 		/* XXX; Commands in loading state. */
2320 		ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
2321 	}
2322 	for (i = 0; i < ch->numslots; i++) {
2323 		if (!ch->hold[i])
2324 			continue;
2325 		ahci_done(ch, ch->hold[i]);
2326 		ch->hold[i] = NULL;
2327 		ch->numhslots--;
2328 	}
2329 	if (ch->toslots != 0)
2330 		xpt_release_simq(ch->sim, TRUE);
2331 	ch->eslots = 0;
2332 	ch->toslots = 0;
2333 	ch->wrongccs = 0;
2334 	ch->fatalerr = 0;
2335 	/* Tell the XPT about the event */
2336 	xpt_async(AC_BUS_RESET, ch->path, NULL);
2337 	/* Disable port interrupts */
2338 	ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
2339 	/* Reset and reconnect PHY, */
2340 	if (!ahci_sata_phy_reset(ch)) {
2341 		if (bootverbose)
2342 			device_printf(ch->dev,
2343 			    "AHCI reset: device not found\n");
2344 		ch->devices = 0;
2345 		/* Enable wanted port interrupts */
2346 		ATA_OUTL(ch->r_mem, AHCI_P_IE,
2347 		    (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2348 		     AHCI_P_IX_PRC | AHCI_P_IX_PC));
2349 		xpt_release_simq(ch->sim, TRUE);
2350 		return;
2351 	}
2352 	if (bootverbose)
2353 		device_printf(ch->dev, "AHCI reset: device found\n");
2354 	/* Wait for clearing busy status. */
2355 	if (ahci_wait_ready(ch, dumping ? 31000 : 0, 0)) {
2356 		if (dumping)
2357 			ahci_clo(ch);
2358 		else
2359 			ch->resetting = 310;
2360 	}
2361 	ch->devices = 1;
2362 	/* Enable wanted port interrupts */
2363 	ATA_OUTL(ch->r_mem, AHCI_P_IE,
2364 	     (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2365 	      AHCI_P_IX_TFE | AHCI_P_IX_HBF |
2366 	      AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF |
2367 	      ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC |
2368 	      AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) |
2369 	      AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR)));
2370 	if (ch->resetting)
2371 		callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, ch);
2372 	else {
2373 		ahci_start(ch, 1);
2374 		xpt_release_simq(ch->sim, TRUE);
2375 	}
2376 }
2377 
2378 static int
2379 ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag)
2380 {
2381 	u_int8_t *fis = &ctp->cfis[0];
2382 
2383 	bzero(fis, 20);
2384 	fis[0] = 0x27;  		/* host to device */
2385 	fis[1] = (ccb->ccb_h.target_id & 0x0f);
2386 	if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2387 		fis[1] |= 0x80;
2388 		fis[2] = ATA_PACKET_CMD;
2389 		if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2390 		    ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA)
2391 			fis[3] = ATA_F_DMA;
2392 		else {
2393 			fis[5] = ccb->csio.dxfer_len;
2394 		        fis[6] = ccb->csio.dxfer_len >> 8;
2395 		}
2396 		fis[7] = ATA_D_LBA;
2397 		fis[15] = ATA_A_4BIT;
2398 		bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
2399 		    ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes,
2400 		    ctp->acmd, ccb->csio.cdb_len);
2401 		bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len);
2402 	} else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) {
2403 		fis[1] |= 0x80;
2404 		fis[2] = ccb->ataio.cmd.command;
2405 		fis[3] = ccb->ataio.cmd.features;
2406 		fis[4] = ccb->ataio.cmd.lba_low;
2407 		fis[5] = ccb->ataio.cmd.lba_mid;
2408 		fis[6] = ccb->ataio.cmd.lba_high;
2409 		fis[7] = ccb->ataio.cmd.device;
2410 		fis[8] = ccb->ataio.cmd.lba_low_exp;
2411 		fis[9] = ccb->ataio.cmd.lba_mid_exp;
2412 		fis[10] = ccb->ataio.cmd.lba_high_exp;
2413 		fis[11] = ccb->ataio.cmd.features_exp;
2414 		if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
2415 			fis[12] = tag << 3;
2416 		} else {
2417 			fis[12] = ccb->ataio.cmd.sector_count;
2418 		}
2419 		fis[13] = ccb->ataio.cmd.sector_count_exp;
2420 		fis[15] = ATA_A_4BIT;
2421 	} else {
2422 		fis[15] = ccb->ataio.cmd.control;
2423 	}
2424 	if (ccb->ataio.ata_flags & ATA_FLAG_AUX) {
2425 		fis[16] =  ccb->ataio.aux        & 0xff;
2426 		fis[17] = (ccb->ataio.aux >>  8) & 0xff;
2427 		fis[18] = (ccb->ataio.aux >> 16) & 0xff;
2428 		fis[19] = (ccb->ataio.aux >> 24) & 0xff;
2429 	}
2430 	return (20);
2431 }
2432 
2433 static int
2434 ahci_sata_connect(struct ahci_channel *ch)
2435 {
2436 	u_int32_t status;
2437 	int timeout, found = 0;
2438 
2439 	/* Wait up to 100ms for "connect well" */
2440 	for (timeout = 0; timeout < 1000 ; timeout++) {
2441 		status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
2442 		if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
2443 			found = 1;
2444 		if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
2445 		    ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
2446 		    ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE))
2447 			break;
2448 		if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) {
2449 			if (bootverbose) {
2450 				device_printf(ch->dev, "SATA offline status=%08x\n",
2451 				    status);
2452 			}
2453 			return (0);
2454 		}
2455 		if (found == 0 && timeout >= 100)
2456 			break;
2457 		DELAY(100);
2458 	}
2459 	if (timeout >= 1000 || !found) {
2460 		if (bootverbose) {
2461 			device_printf(ch->dev,
2462 			    "SATA connect timeout time=%dus status=%08x\n",
2463 			    timeout * 100, status);
2464 		}
2465 		return (0);
2466 	}
2467 	if (bootverbose) {
2468 		device_printf(ch->dev, "SATA connect time=%dus status=%08x\n",
2469 		    timeout * 100, status);
2470 	}
2471 	/* Clear SATA error register */
2472 	ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff);
2473 	return (1);
2474 }
2475 
2476 static int
2477 ahci_sata_phy_reset(struct ahci_channel *ch)
2478 {
2479 	int sata_rev;
2480 	uint32_t val;
2481 
2482 	if (ch->listening) {
2483 		val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2484 		val |= AHCI_P_CMD_SUD;
2485 		ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2486 		ch->listening = 0;
2487 	}
2488 	sata_rev = ch->user[ch->pm_present ? 15 : 0].revision;
2489 	if (sata_rev == 1)
2490 		val = ATA_SC_SPD_SPEED_GEN1;
2491 	else if (sata_rev == 2)
2492 		val = ATA_SC_SPD_SPEED_GEN2;
2493 	else if (sata_rev == 3)
2494 		val = ATA_SC_SPD_SPEED_GEN3;
2495 	else
2496 		val = 0;
2497 	ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2498 	    ATA_SC_DET_RESET | val |
2499 	    ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER);
2500 	DELAY(1000);
2501 	ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2502 	    ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 :
2503 	    (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)));
2504 	if (!ahci_sata_connect(ch)) {
2505 		if (ch->caps & AHCI_CAP_SSS) {
2506 			val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2507 			val &= ~AHCI_P_CMD_SUD;
2508 			ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2509 			ch->listening = 1;
2510 		} else if (ch->pm_level > 0)
2511 			ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
2512 		return (0);
2513 	}
2514 	return (1);
2515 }
2516 
2517 static int
2518 ahci_check_ids(struct ahci_channel *ch, union ccb *ccb)
2519 {
2520 
2521 	if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) {
2522 		ccb->ccb_h.status = CAM_TID_INVALID;
2523 		ahci_done(ch, ccb);
2524 		return (-1);
2525 	}
2526 	if (ccb->ccb_h.target_lun != 0) {
2527 		ccb->ccb_h.status = CAM_LUN_INVALID;
2528 		ahci_done(ch, ccb);
2529 		return (-1);
2530 	}
2531 	return (0);
2532 }
2533 
2534 static void
2535 ahciaction(struct cam_sim *sim, union ccb *ccb)
2536 {
2537 	struct ahci_channel *ch;
2538 
2539 	CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n",
2540 	    ccb->ccb_h.func_code));
2541 
2542 	ch = (struct ahci_channel *)cam_sim_softc(sim);
2543 	switch (ccb->ccb_h.func_code) {
2544 	/* Common cases first */
2545 	case XPT_ATA_IO:	/* Execute the requested I/O operation */
2546 	case XPT_SCSI_IO:
2547 		if (ahci_check_ids(ch, ccb))
2548 			return;
2549 		if (ch->devices == 0 ||
2550 		    (ch->pm_present == 0 &&
2551 		     ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) {
2552 			ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2553 			break;
2554 		}
2555 		ccb->ccb_h.recovery_type = RECOVERY_NONE;
2556 		/* Check for command collision. */
2557 		if (ahci_check_collision(ch, ccb)) {
2558 			/* Freeze command. */
2559 			ch->frozen = ccb;
2560 			/* We have only one frozen slot, so freeze simq also. */
2561 			xpt_freeze_simq(ch->sim, 1);
2562 			return;
2563 		}
2564 		ahci_begin_transaction(ch, ccb);
2565 		return;
2566 	case XPT_EN_LUN:		/* Enable LUN as a target */
2567 	case XPT_TARGET_IO:		/* Execute target I/O request */
2568 	case XPT_ACCEPT_TARGET_IO:	/* Accept Host Target Mode CDB */
2569 	case XPT_CONT_TARGET_IO:	/* Continue Host Target I/O Connection*/
2570 	case XPT_ABORT:			/* Abort the specified CCB */
2571 		/* XXX Implement */
2572 		ccb->ccb_h.status = CAM_REQ_INVALID;
2573 		break;
2574 	case XPT_SET_TRAN_SETTINGS:
2575 	{
2576 		struct	ccb_trans_settings *cts = &ccb->cts;
2577 		struct	ahci_device *d;
2578 
2579 		if (ahci_check_ids(ch, ccb))
2580 			return;
2581 		if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2582 			d = &ch->curr[ccb->ccb_h.target_id];
2583 		else
2584 			d = &ch->user[ccb->ccb_h.target_id];
2585 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION)
2586 			d->revision = cts->xport_specific.sata.revision;
2587 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE)
2588 			d->mode = cts->xport_specific.sata.mode;
2589 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT)
2590 			d->bytecount = min(8192, cts->xport_specific.sata.bytecount);
2591 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS)
2592 			d->tags = min(ch->numslots, cts->xport_specific.sata.tags);
2593 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM)
2594 			ch->pm_present = cts->xport_specific.sata.pm_present;
2595 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI)
2596 			d->atapi = cts->xport_specific.sata.atapi;
2597 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
2598 			d->caps = cts->xport_specific.sata.caps;
2599 		ccb->ccb_h.status = CAM_REQ_CMP;
2600 		break;
2601 	}
2602 	case XPT_GET_TRAN_SETTINGS:
2603 	/* Get default/user set transfer settings for the target */
2604 	{
2605 		struct	ccb_trans_settings *cts = &ccb->cts;
2606 		struct  ahci_device *d;
2607 		uint32_t status;
2608 
2609 		if (ahci_check_ids(ch, ccb))
2610 			return;
2611 		if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2612 			d = &ch->curr[ccb->ccb_h.target_id];
2613 		else
2614 			d = &ch->user[ccb->ccb_h.target_id];
2615 		cts->protocol = PROTO_UNSPECIFIED;
2616 		cts->protocol_version = PROTO_VERSION_UNSPECIFIED;
2617 		cts->transport = XPORT_SATA;
2618 		cts->transport_version = XPORT_VERSION_UNSPECIFIED;
2619 		cts->proto_specific.valid = 0;
2620 		cts->xport_specific.sata.valid = 0;
2621 		if (cts->type == CTS_TYPE_CURRENT_SETTINGS &&
2622 		    (ccb->ccb_h.target_id == 15 ||
2623 		    (ccb->ccb_h.target_id == 0 && !ch->pm_present))) {
2624 			status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK;
2625 			if (status & 0x0f0) {
2626 				cts->xport_specific.sata.revision =
2627 				    (status & 0x0f0) >> 4;
2628 				cts->xport_specific.sata.valid |=
2629 				    CTS_SATA_VALID_REVISION;
2630 			}
2631 			cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D;
2632 			if (ch->pm_level) {
2633 				if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC))
2634 					cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ;
2635 				if (ch->caps2 & AHCI_CAP2_APST)
2636 					cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST;
2637 			}
2638 			if ((ch->caps & AHCI_CAP_SNCQ) &&
2639 			    (ch->quirks & AHCI_Q_NOAA) == 0)
2640 				cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA;
2641 			cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN;
2642 			cts->xport_specific.sata.caps &=
2643 			    ch->user[ccb->ccb_h.target_id].caps;
2644 			cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2645 		} else {
2646 			cts->xport_specific.sata.revision = d->revision;
2647 			cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION;
2648 			cts->xport_specific.sata.caps = d->caps;
2649 			cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2650 		}
2651 		cts->xport_specific.sata.mode = d->mode;
2652 		cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE;
2653 		cts->xport_specific.sata.bytecount = d->bytecount;
2654 		cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT;
2655 		cts->xport_specific.sata.pm_present = ch->pm_present;
2656 		cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM;
2657 		cts->xport_specific.sata.tags = d->tags;
2658 		cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS;
2659 		cts->xport_specific.sata.atapi = d->atapi;
2660 		cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI;
2661 		ccb->ccb_h.status = CAM_REQ_CMP;
2662 		break;
2663 	}
2664 	case XPT_RESET_BUS:		/* Reset the specified SCSI bus */
2665 	case XPT_RESET_DEV:	/* Bus Device Reset the specified SCSI device */
2666 		ahci_reset(ch);
2667 		ccb->ccb_h.status = CAM_REQ_CMP;
2668 		break;
2669 	case XPT_TERM_IO:		/* Terminate the I/O process */
2670 		/* XXX Implement */
2671 		ccb->ccb_h.status = CAM_REQ_INVALID;
2672 		break;
2673 	case XPT_PATH_INQ:		/* Path routing inquiry */
2674 	{
2675 		struct ccb_pathinq *cpi = &ccb->cpi;
2676 
2677 		cpi->version_num = 1; /* XXX??? */
2678 		cpi->hba_inquiry = PI_SDTR_ABLE;
2679 		if (ch->caps & AHCI_CAP_SNCQ)
2680 			cpi->hba_inquiry |= PI_TAG_ABLE;
2681 		if (ch->caps & AHCI_CAP_SPM)
2682 			cpi->hba_inquiry |= PI_SATAPM;
2683 		cpi->target_sprt = 0;
2684 		cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED | PIM_ATA_EXT;
2685 		cpi->hba_eng_cnt = 0;
2686 		if (ch->caps & AHCI_CAP_SPM)
2687 			cpi->max_target = 15;
2688 		else
2689 			cpi->max_target = 0;
2690 		cpi->max_lun = 0;
2691 		cpi->initiator_id = 0;
2692 		cpi->bus_id = cam_sim_bus(sim);
2693 		cpi->base_transfer_speed = 150000;
2694 		strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2695 		strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN);
2696 		strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2697 		cpi->unit_number = cam_sim_unit(sim);
2698 		cpi->transport = XPORT_SATA;
2699 		cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
2700 		cpi->protocol = PROTO_ATA;
2701 		cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
2702 		cpi->maxio = MAXPHYS;
2703 		/* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */
2704 		if (ch->quirks & AHCI_Q_MAXIO_64K)
2705 			cpi->maxio = min(cpi->maxio, 128 * 512);
2706 		cpi->hba_vendor = ch->vendorid;
2707 		cpi->hba_device = ch->deviceid;
2708 		cpi->hba_subvendor = ch->subvendorid;
2709 		cpi->hba_subdevice = ch->subdeviceid;
2710 		cpi->ccb_h.status = CAM_REQ_CMP;
2711 		break;
2712 	}
2713 	default:
2714 		ccb->ccb_h.status = CAM_REQ_INVALID;
2715 		break;
2716 	}
2717 	ahci_done(ch, ccb);
2718 }
2719 
2720 static void
2721 ahcipoll(struct cam_sim *sim)
2722 {
2723 	struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim);
2724 	uint32_t istatus;
2725 
2726 	/* Read interrupt statuses and process if any. */
2727 	istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
2728 	if (istatus != 0)
2729 		ahci_ch_intr_main(ch, istatus);
2730 	if (ch->resetting != 0 &&
2731 	    (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) {
2732 		ch->resetpolldiv = 1000;
2733 		ahci_reset_to(ch);
2734 	}
2735 }
2736 MODULE_VERSION(ahci, 1);
2737 MODULE_DEPEND(ahci, cam, 1, 1, 1);
2738