1 /*- 2 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <sys/endian.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <machine/stdarg.h> 41 #include <machine/resource.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include "ahci.h" 45 46 #include <cam/cam.h> 47 #include <cam/cam_ccb.h> 48 #include <cam/cam_sim.h> 49 #include <cam/cam_xpt_sim.h> 50 #include <cam/cam_debug.h> 51 52 /* local prototypes */ 53 static void ahci_intr(void *data); 54 static void ahci_intr_one(void *data); 55 static void ahci_intr_one_edge(void *data); 56 static int ahci_ch_init(device_t dev); 57 static int ahci_ch_deinit(device_t dev); 58 static int ahci_ch_suspend(device_t dev); 59 static int ahci_ch_resume(device_t dev); 60 static void ahci_ch_pm(void *arg); 61 static void ahci_ch_intr(void *arg); 62 static void ahci_ch_intr_direct(void *arg); 63 static void ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus); 64 static void ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb); 65 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 66 static void ahci_execute_transaction(struct ahci_slot *slot); 67 static void ahci_timeout(struct ahci_slot *slot); 68 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 69 static int ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 70 static void ahci_dmainit(device_t dev); 71 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 72 static void ahci_dmafini(device_t dev); 73 static void ahci_slotsalloc(device_t dev); 74 static void ahci_slotsfree(device_t dev); 75 static void ahci_reset(struct ahci_channel *ch); 76 static void ahci_start(struct ahci_channel *ch, int fbs); 77 static void ahci_stop(struct ahci_channel *ch); 78 static void ahci_clo(struct ahci_channel *ch); 79 static void ahci_start_fr(struct ahci_channel *ch); 80 static void ahci_stop_fr(struct ahci_channel *ch); 81 82 static int ahci_sata_connect(struct ahci_channel *ch); 83 static int ahci_sata_phy_reset(struct ahci_channel *ch); 84 static int ahci_wait_ready(struct ahci_channel *ch, int t, int t0); 85 86 static void ahci_issue_recovery(struct ahci_channel *ch); 87 static void ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb); 88 static void ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb); 89 90 static void ahciaction(struct cam_sim *sim, union ccb *ccb); 91 static void ahcipoll(struct cam_sim *sim); 92 93 static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 94 95 #define recovery_type spriv_field0 96 #define RECOVERY_NONE 0 97 #define RECOVERY_READ_LOG 1 98 #define RECOVERY_REQUEST_SENSE 2 99 #define recovery_slot spriv_field1 100 101 int 102 ahci_ctlr_setup(device_t dev) 103 { 104 struct ahci_controller *ctlr = device_get_softc(dev); 105 /* Clear interrupts */ 106 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 107 /* Configure CCC */ 108 if (ctlr->ccc) { 109 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 110 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 111 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 112 (4 << AHCI_CCCC_CC_SHIFT) | 113 AHCI_CCCC_EN); 114 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 115 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 116 if (bootverbose) { 117 device_printf(dev, 118 "CCC with %dms/4cmd enabled on vector %d\n", 119 ctlr->ccc, ctlr->cccv); 120 } 121 } 122 /* Enable AHCI interrupts */ 123 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 124 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 125 return (0); 126 } 127 128 int 129 ahci_ctlr_reset(device_t dev) 130 { 131 struct ahci_controller *ctlr = device_get_softc(dev); 132 int timeout; 133 134 /* Enable AHCI mode */ 135 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 136 /* Reset AHCI controller */ 137 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 138 for (timeout = 1000; timeout > 0; timeout--) { 139 DELAY(1000); 140 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 141 break; 142 } 143 if (timeout == 0) { 144 device_printf(dev, "AHCI controller reset failure\n"); 145 return (ENXIO); 146 } 147 /* Reenable AHCI mode */ 148 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 149 150 if (ctlr->quirks & AHCI_Q_RESTORE_CAP) { 151 /* 152 * Restore capability field. 153 * This is write to a read-only register to restore its state. 154 * On fully standard-compliant hardware this is not needed and 155 * this operation shall not take place. See ahci_pci.c for 156 * platforms using this quirk. 157 */ 158 ATA_OUTL(ctlr->r_mem, AHCI_CAP, ctlr->caps); 159 } 160 161 return (0); 162 } 163 164 165 int 166 ahci_attach(device_t dev) 167 { 168 struct ahci_controller *ctlr = device_get_softc(dev); 169 int error, i, u, speed, unit; 170 u_int32_t version; 171 device_t child; 172 173 ctlr->dev = dev; 174 ctlr->ccc = 0; 175 resource_int_value(device_get_name(dev), 176 device_get_unit(dev), "ccc", &ctlr->ccc); 177 178 /* Setup our own memory management for channels. */ 179 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 180 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 181 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 182 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 183 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 184 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 185 return (error); 186 } 187 if ((error = rman_manage_region(&ctlr->sc_iomem, 188 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 189 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 190 rman_fini(&ctlr->sc_iomem); 191 return (error); 192 } 193 /* Get the HW capabilities */ 194 version = ATA_INL(ctlr->r_mem, AHCI_VS); 195 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 196 if (version >= 0x00010200) 197 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 198 if (ctlr->caps & AHCI_CAP_EMS) 199 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 200 201 if (ctlr->quirks & AHCI_Q_FORCE_PI) { 202 /* 203 * Enable ports. 204 * The spec says that BIOS sets up bits corresponding to 205 * available ports. On platforms where this information 206 * is missing, the driver can define available ports on its own. 207 */ 208 int nports = (ctlr->caps & AHCI_CAP_NPMASK) + 1; 209 int nmask = (1 << nports) - 1; 210 211 ATA_OUTL(ctlr->r_mem, AHCI_PI, nmask); 212 device_printf(dev, "Forcing PI to %d ports (mask = %x)\n", 213 nports, nmask); 214 } 215 216 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 217 218 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */ 219 if ((ctlr->quirks & AHCI_Q_ALTSIG) && 220 (ctlr->caps & AHCI_CAP_SPM) == 0) 221 ctlr->quirks |= AHCI_Q_NOBSYRES; 222 223 if (ctlr->quirks & AHCI_Q_1CH) { 224 ctlr->caps &= ~AHCI_CAP_NPMASK; 225 ctlr->ichannels &= 0x01; 226 } 227 if (ctlr->quirks & AHCI_Q_2CH) { 228 ctlr->caps &= ~AHCI_CAP_NPMASK; 229 ctlr->caps |= 1; 230 ctlr->ichannels &= 0x03; 231 } 232 if (ctlr->quirks & AHCI_Q_4CH) { 233 ctlr->caps &= ~AHCI_CAP_NPMASK; 234 ctlr->caps |= 3; 235 ctlr->ichannels &= 0x0f; 236 } 237 ctlr->channels = MAX(flsl(ctlr->ichannels), 238 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 239 if (ctlr->quirks & AHCI_Q_NOPMP) 240 ctlr->caps &= ~AHCI_CAP_SPM; 241 if (ctlr->quirks & AHCI_Q_NONCQ) 242 ctlr->caps &= ~AHCI_CAP_SNCQ; 243 if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 244 ctlr->ccc = 0; 245 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC); 246 247 /* Create controller-wide DMA tag. */ 248 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 249 (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR : 250 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 251 BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, 252 0, NULL, NULL, &ctlr->dma_tag)) { 253 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, 254 ctlr->r_mem); 255 rman_fini(&ctlr->sc_iomem); 256 return (ENXIO); 257 } 258 259 ahci_ctlr_setup(dev); 260 261 /* Setup interrupts. */ 262 if ((error = ahci_setup_interrupt(dev)) != 0) { 263 bus_dma_tag_destroy(ctlr->dma_tag); 264 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, 265 ctlr->r_mem); 266 rman_fini(&ctlr->sc_iomem); 267 return (error); 268 } 269 270 i = 0; 271 for (u = ctlr->ichannels; u != 0; u >>= 1) 272 i += (u & 1); 273 ctlr->direct = (ctlr->msi && (ctlr->numirqs > 1 || i <= 3)); 274 resource_int_value(device_get_name(dev), device_get_unit(dev), 275 "direct", &ctlr->direct); 276 /* Announce HW capabilities. */ 277 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 278 device_printf(dev, 279 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 280 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 281 ((version >> 4) & 0xf0) + (version & 0x0f), 282 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 283 ((speed == 1) ? "1.5":((speed == 2) ? "3": 284 ((speed == 3) ? "6":"?"))), 285 (ctlr->caps & AHCI_CAP_SPM) ? 286 "supported" : "not supported", 287 (ctlr->caps & AHCI_CAP_FBSS) ? 288 " with FBS" : ""); 289 if (ctlr->quirks != 0) { 290 device_printf(dev, "quirks=0x%b\n", ctlr->quirks, 291 AHCI_Q_BIT_STRING); 292 } 293 if (bootverbose) { 294 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 295 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 296 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 297 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 298 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 299 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 300 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 301 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 302 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 303 ((speed == 1) ? "1.5":((speed == 2) ? "3": 304 ((speed == 3) ? "6":"?")))); 305 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 306 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 307 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 308 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 309 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 310 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 311 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 312 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 313 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 314 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 315 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 316 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 317 } 318 if (bootverbose && version >= 0x00010200) { 319 device_printf(dev, "Caps2:%s%s%s%s%s%s\n", 320 (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"", 321 (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"", 322 (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"", 323 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 324 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 325 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 326 } 327 /* Attach all channels on this controller */ 328 for (unit = 0; unit < ctlr->channels; unit++) { 329 child = device_add_child(dev, "ahcich", -1); 330 if (child == NULL) { 331 device_printf(dev, "failed to add channel device\n"); 332 continue; 333 } 334 device_set_ivars(child, (void *)(intptr_t)unit); 335 if ((ctlr->ichannels & (1 << unit)) == 0) 336 device_disable(child); 337 } 338 if (ctlr->caps & AHCI_CAP_EMS) { 339 child = device_add_child(dev, "ahciem", -1); 340 if (child == NULL) 341 device_printf(dev, "failed to add enclosure device\n"); 342 else 343 device_set_ivars(child, (void *)(intptr_t)-1); 344 } 345 bus_generic_attach(dev); 346 return (0); 347 } 348 349 int 350 ahci_detach(device_t dev) 351 { 352 struct ahci_controller *ctlr = device_get_softc(dev); 353 int i; 354 355 /* Detach & delete all children */ 356 device_delete_children(dev); 357 358 /* Free interrupts. */ 359 for (i = 0; i < ctlr->numirqs; i++) { 360 if (ctlr->irqs[i].r_irq) { 361 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 362 ctlr->irqs[i].handle); 363 bus_release_resource(dev, SYS_RES_IRQ, 364 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 365 } 366 } 367 bus_dma_tag_destroy(ctlr->dma_tag); 368 /* Free memory. */ 369 rman_fini(&ctlr->sc_iomem); 370 if (ctlr->r_mem) 371 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 372 return (0); 373 } 374 375 int 376 ahci_setup_interrupt(device_t dev) 377 { 378 struct ahci_controller *ctlr = device_get_softc(dev); 379 int i; 380 381 /* Check for single MSI vector fallback. */ 382 if (ctlr->numirqs > 1 && 383 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 384 device_printf(dev, "Falling back to one MSI\n"); 385 ctlr->numirqs = 1; 386 } 387 388 /* Ensure we don't overrun irqs. */ 389 if (ctlr->numirqs > AHCI_MAX_IRQS) { 390 device_printf(dev, "Too many irqs %d > %d (clamping)\n", 391 ctlr->numirqs, AHCI_MAX_IRQS); 392 ctlr->numirqs = AHCI_MAX_IRQS; 393 } 394 395 /* Allocate all IRQs. */ 396 for (i = 0; i < ctlr->numirqs; i++) { 397 ctlr->irqs[i].ctlr = ctlr; 398 ctlr->irqs[i].r_irq_rid = i + (ctlr->msi ? 1 : 0); 399 if (ctlr->channels == 1 && !ctlr->ccc && ctlr->msi) 400 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 401 else if (ctlr->numirqs == 1 || i >= ctlr->channels || 402 (ctlr->ccc && i == ctlr->cccv)) 403 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 404 else if (i == ctlr->numirqs - 1) 405 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 406 else 407 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 408 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 409 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 410 device_printf(dev, "unable to map interrupt\n"); 411 return (ENXIO); 412 } 413 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 414 (ctlr->irqs[i].mode != AHCI_IRQ_MODE_ONE) ? ahci_intr : 415 ((ctlr->quirks & AHCI_Q_EDGEIS) ? ahci_intr_one_edge : 416 ahci_intr_one), 417 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 418 /* SOS XXX release r_irq */ 419 device_printf(dev, "unable to setup interrupt\n"); 420 return (ENXIO); 421 } 422 if (ctlr->numirqs > 1) { 423 bus_describe_intr(dev, ctlr->irqs[i].r_irq, 424 ctlr->irqs[i].handle, 425 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 426 "ch%d" : "%d", i); 427 } 428 } 429 return (0); 430 } 431 432 /* 433 * Common case interrupt handler. 434 */ 435 static void 436 ahci_intr(void *data) 437 { 438 struct ahci_controller_irq *irq = data; 439 struct ahci_controller *ctlr = irq->ctlr; 440 u_int32_t is, ise = 0; 441 void *arg; 442 int unit; 443 444 if (irq->mode == AHCI_IRQ_MODE_ALL) { 445 unit = 0; 446 if (ctlr->ccc) 447 is = ctlr->ichannels; 448 else 449 is = ATA_INL(ctlr->r_mem, AHCI_IS); 450 } else { /* AHCI_IRQ_MODE_AFTER */ 451 unit = irq->r_irq_rid - 1; 452 is = ATA_INL(ctlr->r_mem, AHCI_IS); 453 } 454 /* CCC interrupt is edge triggered. */ 455 if (ctlr->ccc) 456 ise = 1 << ctlr->cccv; 457 /* Some controllers have edge triggered IS. */ 458 if (ctlr->quirks & AHCI_Q_EDGEIS) 459 ise |= is; 460 if (ise != 0) 461 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 462 for (; unit < ctlr->channels; unit++) { 463 if ((is & (1 << unit)) != 0 && 464 (arg = ctlr->interrupt[unit].argument)) { 465 ctlr->interrupt[unit].function(arg); 466 } 467 } 468 /* AHCI declares level triggered IS. */ 469 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 470 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 471 } 472 473 /* 474 * Simplified interrupt handler for multivector MSI mode. 475 */ 476 static void 477 ahci_intr_one(void *data) 478 { 479 struct ahci_controller_irq *irq = data; 480 struct ahci_controller *ctlr = irq->ctlr; 481 void *arg; 482 int unit; 483 484 unit = irq->r_irq_rid - 1; 485 if ((arg = ctlr->interrupt[unit].argument)) 486 ctlr->interrupt[unit].function(arg); 487 /* AHCI declares level triggered IS. */ 488 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 489 } 490 491 static void 492 ahci_intr_one_edge(void *data) 493 { 494 struct ahci_controller_irq *irq = data; 495 struct ahci_controller *ctlr = irq->ctlr; 496 void *arg; 497 int unit; 498 499 unit = irq->r_irq_rid - 1; 500 /* Some controllers have edge triggered IS. */ 501 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 502 if ((arg = ctlr->interrupt[unit].argument)) 503 ctlr->interrupt[unit].function(arg); 504 } 505 506 struct resource * 507 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 508 u_long start, u_long end, u_long count, u_int flags) 509 { 510 struct ahci_controller *ctlr = device_get_softc(dev); 511 struct resource *res; 512 long st; 513 int offset, size, unit; 514 515 unit = (intptr_t)device_get_ivars(child); 516 res = NULL; 517 switch (type) { 518 case SYS_RES_MEMORY: 519 if (unit >= 0) { 520 offset = AHCI_OFFSET + (unit << 7); 521 size = 128; 522 } else if (*rid == 0) { 523 offset = AHCI_EM_CTL; 524 size = 4; 525 } else { 526 offset = (ctlr->emloc & 0xffff0000) >> 14; 527 size = (ctlr->emloc & 0x0000ffff) << 2; 528 if (*rid != 1) { 529 if (*rid == 2 && (ctlr->capsem & 530 (AHCI_EM_XMT | AHCI_EM_SMB)) == 0) 531 offset += size; 532 else 533 break; 534 } 535 } 536 st = rman_get_start(ctlr->r_mem); 537 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 538 st + offset + size - 1, size, RF_ACTIVE, child); 539 if (res) { 540 bus_space_handle_t bsh; 541 bus_space_tag_t bst; 542 bsh = rman_get_bushandle(ctlr->r_mem); 543 bst = rman_get_bustag(ctlr->r_mem); 544 bus_space_subregion(bst, bsh, offset, 128, &bsh); 545 rman_set_bushandle(res, bsh); 546 rman_set_bustag(res, bst); 547 } 548 break; 549 case SYS_RES_IRQ: 550 if (*rid == ATA_IRQ_RID) 551 res = ctlr->irqs[0].r_irq; 552 break; 553 } 554 return (res); 555 } 556 557 int 558 ahci_release_resource(device_t dev, device_t child, int type, int rid, 559 struct resource *r) 560 { 561 562 switch (type) { 563 case SYS_RES_MEMORY: 564 rman_release_resource(r); 565 return (0); 566 case SYS_RES_IRQ: 567 if (rid != ATA_IRQ_RID) 568 return (ENOENT); 569 return (0); 570 } 571 return (EINVAL); 572 } 573 574 int 575 ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 576 int flags, driver_filter_t *filter, driver_intr_t *function, 577 void *argument, void **cookiep) 578 { 579 struct ahci_controller *ctlr = device_get_softc(dev); 580 int unit = (intptr_t)device_get_ivars(child); 581 582 if (filter != NULL) { 583 printf("ahci.c: we cannot use a filter here\n"); 584 return (EINVAL); 585 } 586 ctlr->interrupt[unit].function = function; 587 ctlr->interrupt[unit].argument = argument; 588 return (0); 589 } 590 591 int 592 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 593 void *cookie) 594 { 595 struct ahci_controller *ctlr = device_get_softc(dev); 596 int unit = (intptr_t)device_get_ivars(child); 597 598 ctlr->interrupt[unit].function = NULL; 599 ctlr->interrupt[unit].argument = NULL; 600 return (0); 601 } 602 603 int 604 ahci_print_child(device_t dev, device_t child) 605 { 606 int retval, channel; 607 608 retval = bus_print_child_header(dev, child); 609 channel = (int)(intptr_t)device_get_ivars(child); 610 if (channel >= 0) 611 retval += printf(" at channel %d", channel); 612 retval += bus_print_child_footer(dev, child); 613 return (retval); 614 } 615 616 int 617 ahci_child_location_str(device_t dev, device_t child, char *buf, 618 size_t buflen) 619 { 620 int channel; 621 622 channel = (int)(intptr_t)device_get_ivars(child); 623 if (channel >= 0) 624 snprintf(buf, buflen, "channel=%d", channel); 625 return (0); 626 } 627 628 bus_dma_tag_t 629 ahci_get_dma_tag(device_t dev, device_t child) 630 { 631 struct ahci_controller *ctlr = device_get_softc(dev); 632 633 return (ctlr->dma_tag); 634 } 635 636 static int 637 ahci_ch_probe(device_t dev) 638 { 639 640 device_set_desc_copy(dev, "AHCI channel"); 641 return (BUS_PROBE_DEFAULT); 642 } 643 644 static int 645 ahci_ch_attach(device_t dev) 646 { 647 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 648 struct ahci_channel *ch = device_get_softc(dev); 649 struct cam_devq *devq; 650 int rid, error, i, sata_rev = 0; 651 u_int32_t version; 652 653 ch->dev = dev; 654 ch->unit = (intptr_t)device_get_ivars(dev); 655 ch->caps = ctlr->caps; 656 ch->caps2 = ctlr->caps2; 657 ch->start = ctlr->ch_start; 658 ch->quirks = ctlr->quirks; 659 ch->vendorid = ctlr->vendorid; 660 ch->deviceid = ctlr->deviceid; 661 ch->subvendorid = ctlr->subvendorid; 662 ch->subdeviceid = ctlr->subdeviceid; 663 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1; 664 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 665 ch->pm_level = 0; 666 resource_int_value(device_get_name(dev), 667 device_get_unit(dev), "pm_level", &ch->pm_level); 668 STAILQ_INIT(&ch->doneq); 669 if (ch->pm_level > 3) 670 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 671 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0); 672 /* JMicron external ports (0) sometimes limited */ 673 if ((ctlr->quirks & AHCI_Q_SATA1_UNIT0) && ch->unit == 0) 674 sata_rev = 1; 675 if (ch->quirks & AHCI_Q_SATA2) 676 sata_rev = 2; 677 resource_int_value(device_get_name(dev), 678 device_get_unit(dev), "sata_rev", &sata_rev); 679 for (i = 0; i < 16; i++) { 680 ch->user[i].revision = sata_rev; 681 ch->user[i].mode = 0; 682 ch->user[i].bytecount = 8192; 683 ch->user[i].tags = ch->numslots; 684 ch->user[i].caps = 0; 685 ch->curr[i] = ch->user[i]; 686 if (ch->pm_level) { 687 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 688 CTS_SATA_CAPS_H_APST | 689 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 690 } 691 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA | 692 CTS_SATA_CAPS_H_AN; 693 } 694 rid = 0; 695 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 696 &rid, RF_ACTIVE))) 697 return (ENXIO); 698 ahci_dmainit(dev); 699 ahci_slotsalloc(dev); 700 mtx_lock(&ch->mtx); 701 ahci_ch_init(dev); 702 rid = ATA_IRQ_RID; 703 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 704 &rid, RF_SHAREABLE | RF_ACTIVE))) { 705 device_printf(dev, "Unable to map interrupt\n"); 706 error = ENXIO; 707 goto err0; 708 } 709 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 710 ctlr->direct ? ahci_ch_intr_direct : ahci_ch_intr, 711 ch, &ch->ih))) { 712 device_printf(dev, "Unable to setup interrupt\n"); 713 error = ENXIO; 714 goto err1; 715 } 716 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 717 version = ATA_INL(ctlr->r_mem, AHCI_VS); 718 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS)) 719 ch->chcaps |= AHCI_P_CMD_FBSCP; 720 if (ch->caps2 & AHCI_CAP2_SDS) 721 ch->chscaps = ATA_INL(ch->r_mem, AHCI_P_DEVSLP); 722 if (bootverbose) { 723 device_printf(dev, "Caps:%s%s%s%s%s%s\n", 724 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 725 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 726 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 727 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 728 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"", 729 (ch->chscaps & AHCI_P_DEVSLP_DSP) ? " DSP":""); 730 } 731 /* Create the device queue for our SIM. */ 732 devq = cam_simq_alloc(ch->numslots); 733 if (devq == NULL) { 734 device_printf(dev, "Unable to allocate simq\n"); 735 error = ENOMEM; 736 goto err1; 737 } 738 /* Construct SIM entry */ 739 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 740 device_get_unit(dev), (struct mtx *)&ch->mtx, 741 min(2, ch->numslots), 742 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 743 devq); 744 if (ch->sim == NULL) { 745 cam_simq_free(devq); 746 device_printf(dev, "unable to allocate sim\n"); 747 error = ENOMEM; 748 goto err1; 749 } 750 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 751 device_printf(dev, "unable to register xpt bus\n"); 752 error = ENXIO; 753 goto err2; 754 } 755 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 756 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 757 device_printf(dev, "unable to create path\n"); 758 error = ENXIO; 759 goto err3; 760 } 761 if (ch->pm_level > 3) { 762 callout_reset(&ch->pm_timer, 763 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 764 ahci_ch_pm, ch); 765 } 766 mtx_unlock(&ch->mtx); 767 return (0); 768 769 err3: 770 xpt_bus_deregister(cam_sim_path(ch->sim)); 771 err2: 772 cam_sim_free(ch->sim, /*free_devq*/TRUE); 773 err1: 774 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 775 err0: 776 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 777 mtx_unlock(&ch->mtx); 778 mtx_destroy(&ch->mtx); 779 return (error); 780 } 781 782 static int 783 ahci_ch_detach(device_t dev) 784 { 785 struct ahci_channel *ch = device_get_softc(dev); 786 787 mtx_lock(&ch->mtx); 788 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 789 /* Forget about reset. */ 790 if (ch->resetting) { 791 ch->resetting = 0; 792 xpt_release_simq(ch->sim, TRUE); 793 } 794 xpt_free_path(ch->path); 795 xpt_bus_deregister(cam_sim_path(ch->sim)); 796 cam_sim_free(ch->sim, /*free_devq*/TRUE); 797 mtx_unlock(&ch->mtx); 798 799 if (ch->pm_level > 3) 800 callout_drain(&ch->pm_timer); 801 callout_drain(&ch->reset_timer); 802 bus_teardown_intr(dev, ch->r_irq, ch->ih); 803 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 804 805 ahci_ch_deinit(dev); 806 ahci_slotsfree(dev); 807 ahci_dmafini(dev); 808 809 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 810 mtx_destroy(&ch->mtx); 811 return (0); 812 } 813 814 static int 815 ahci_ch_init(device_t dev) 816 { 817 struct ahci_channel *ch = device_get_softc(dev); 818 uint64_t work; 819 820 /* Disable port interrupts */ 821 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 822 /* Setup work areas */ 823 work = ch->dma.work_bus + AHCI_CL_OFFSET; 824 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 825 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 826 work = ch->dma.rfis_bus; 827 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 828 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 829 /* Activate the channel and power/spin up device */ 830 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 831 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 832 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 833 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 834 ahci_start_fr(ch); 835 ahci_start(ch, 1); 836 return (0); 837 } 838 839 static int 840 ahci_ch_deinit(device_t dev) 841 { 842 struct ahci_channel *ch = device_get_softc(dev); 843 844 /* Disable port interrupts. */ 845 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 846 /* Reset command register. */ 847 ahci_stop(ch); 848 ahci_stop_fr(ch); 849 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 850 /* Allow everything, including partial and slumber modes. */ 851 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 852 /* Request slumber mode transition and give some time to get there. */ 853 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 854 DELAY(100); 855 /* Disable PHY. */ 856 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 857 return (0); 858 } 859 860 static int 861 ahci_ch_suspend(device_t dev) 862 { 863 struct ahci_channel *ch = device_get_softc(dev); 864 865 mtx_lock(&ch->mtx); 866 xpt_freeze_simq(ch->sim, 1); 867 /* Forget about reset. */ 868 if (ch->resetting) { 869 ch->resetting = 0; 870 callout_stop(&ch->reset_timer); 871 xpt_release_simq(ch->sim, TRUE); 872 } 873 while (ch->oslots) 874 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100); 875 ahci_ch_deinit(dev); 876 mtx_unlock(&ch->mtx); 877 return (0); 878 } 879 880 static int 881 ahci_ch_resume(device_t dev) 882 { 883 struct ahci_channel *ch = device_get_softc(dev); 884 885 mtx_lock(&ch->mtx); 886 ahci_ch_init(dev); 887 ahci_reset(ch); 888 xpt_release_simq(ch->sim, TRUE); 889 mtx_unlock(&ch->mtx); 890 return (0); 891 } 892 893 devclass_t ahcich_devclass; 894 static device_method_t ahcich_methods[] = { 895 DEVMETHOD(device_probe, ahci_ch_probe), 896 DEVMETHOD(device_attach, ahci_ch_attach), 897 DEVMETHOD(device_detach, ahci_ch_detach), 898 DEVMETHOD(device_suspend, ahci_ch_suspend), 899 DEVMETHOD(device_resume, ahci_ch_resume), 900 DEVMETHOD_END 901 }; 902 static driver_t ahcich_driver = { 903 "ahcich", 904 ahcich_methods, 905 sizeof(struct ahci_channel) 906 }; 907 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, NULL, NULL); 908 909 struct ahci_dc_cb_args { 910 bus_addr_t maddr; 911 int error; 912 }; 913 914 static void 915 ahci_dmainit(device_t dev) 916 { 917 struct ahci_channel *ch = device_get_softc(dev); 918 struct ahci_dc_cb_args dcba; 919 size_t rfsize; 920 921 /* Command area. */ 922 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 923 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 924 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 925 0, NULL, NULL, &ch->dma.work_tag)) 926 goto error; 927 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 928 BUS_DMA_ZERO, &ch->dma.work_map)) 929 goto error; 930 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 931 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 932 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 933 goto error; 934 } 935 ch->dma.work_bus = dcba.maddr; 936 /* FIS receive area. */ 937 if (ch->chcaps & AHCI_P_CMD_FBSCP) 938 rfsize = 4096; 939 else 940 rfsize = 256; 941 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 942 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 943 NULL, NULL, rfsize, 1, rfsize, 944 0, NULL, NULL, &ch->dma.rfis_tag)) 945 goto error; 946 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 947 &ch->dma.rfis_map)) 948 goto error; 949 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 950 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 951 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 952 goto error; 953 } 954 ch->dma.rfis_bus = dcba.maddr; 955 /* Data area. */ 956 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 957 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 958 NULL, NULL, 959 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 960 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 961 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 962 goto error; 963 } 964 return; 965 966 error: 967 device_printf(dev, "WARNING - DMA initialization failed\n"); 968 ahci_dmafini(dev); 969 } 970 971 static void 972 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 973 { 974 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 975 976 if (!(dcba->error = error)) 977 dcba->maddr = segs[0].ds_addr; 978 } 979 980 static void 981 ahci_dmafini(device_t dev) 982 { 983 struct ahci_channel *ch = device_get_softc(dev); 984 985 if (ch->dma.data_tag) { 986 bus_dma_tag_destroy(ch->dma.data_tag); 987 ch->dma.data_tag = NULL; 988 } 989 if (ch->dma.rfis_bus) { 990 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 991 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 992 ch->dma.rfis_bus = 0; 993 ch->dma.rfis = NULL; 994 } 995 if (ch->dma.work_bus) { 996 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 997 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 998 ch->dma.work_bus = 0; 999 ch->dma.work = NULL; 1000 } 1001 if (ch->dma.work_tag) { 1002 bus_dma_tag_destroy(ch->dma.work_tag); 1003 ch->dma.work_tag = NULL; 1004 } 1005 } 1006 1007 static void 1008 ahci_slotsalloc(device_t dev) 1009 { 1010 struct ahci_channel *ch = device_get_softc(dev); 1011 int i; 1012 1013 /* Alloc and setup command/dma slots */ 1014 bzero(ch->slot, sizeof(ch->slot)); 1015 for (i = 0; i < ch->numslots; i++) { 1016 struct ahci_slot *slot = &ch->slot[i]; 1017 1018 slot->ch = ch; 1019 slot->slot = i; 1020 slot->state = AHCI_SLOT_EMPTY; 1021 slot->ccb = NULL; 1022 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1023 1024 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1025 device_printf(ch->dev, "FAILURE - create data_map\n"); 1026 } 1027 } 1028 1029 static void 1030 ahci_slotsfree(device_t dev) 1031 { 1032 struct ahci_channel *ch = device_get_softc(dev); 1033 int i; 1034 1035 /* Free all dma slots */ 1036 for (i = 0; i < ch->numslots; i++) { 1037 struct ahci_slot *slot = &ch->slot[i]; 1038 1039 callout_drain(&slot->timeout); 1040 if (slot->dma.data_map) { 1041 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1042 slot->dma.data_map = NULL; 1043 } 1044 } 1045 } 1046 1047 static int 1048 ahci_phy_check_events(struct ahci_channel *ch, u_int32_t serr) 1049 { 1050 1051 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) || 1052 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) { 1053 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1054 union ccb *ccb; 1055 1056 if (bootverbose) { 1057 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 1058 device_printf(ch->dev, "CONNECT requested\n"); 1059 else 1060 device_printf(ch->dev, "DISCONNECT requested\n"); 1061 } 1062 ahci_reset(ch); 1063 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1064 return (0); 1065 if (xpt_create_path(&ccb->ccb_h.path, NULL, 1066 cam_sim_path(ch->sim), 1067 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1068 xpt_free_ccb(ccb); 1069 return (0); 1070 } 1071 xpt_rescan(ccb); 1072 return (1); 1073 } 1074 return (0); 1075 } 1076 1077 static void 1078 ahci_cpd_check_events(struct ahci_channel *ch) 1079 { 1080 u_int32_t status; 1081 union ccb *ccb; 1082 device_t dev; 1083 1084 if (ch->pm_level == 0) 1085 return; 1086 1087 status = ATA_INL(ch->r_mem, AHCI_P_CMD); 1088 if ((status & AHCI_P_CMD_CPD) == 0) 1089 return; 1090 1091 if (bootverbose) { 1092 dev = ch->dev; 1093 if (status & AHCI_P_CMD_CPS) { 1094 device_printf(dev, "COLD CONNECT requested\n"); 1095 } else 1096 device_printf(dev, "COLD DISCONNECT requested\n"); 1097 } 1098 ahci_reset(ch); 1099 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1100 return; 1101 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim), 1102 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1103 xpt_free_ccb(ccb); 1104 return; 1105 } 1106 xpt_rescan(ccb); 1107 } 1108 1109 static void 1110 ahci_notify_events(struct ahci_channel *ch, u_int32_t status) 1111 { 1112 struct cam_path *dpath; 1113 int i; 1114 1115 if (ch->caps & AHCI_CAP_SSNTF) 1116 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1117 if (bootverbose) 1118 device_printf(ch->dev, "SNTF 0x%04x\n", status); 1119 for (i = 0; i < 16; i++) { 1120 if ((status & (1 << i)) == 0) 1121 continue; 1122 if (xpt_create_path(&dpath, NULL, 1123 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1124 xpt_async(AC_SCSI_AEN, dpath, NULL); 1125 xpt_free_path(dpath); 1126 } 1127 } 1128 } 1129 1130 static void 1131 ahci_done(struct ahci_channel *ch, union ccb *ccb) 1132 { 1133 1134 mtx_assert(&ch->mtx, MA_OWNED); 1135 if ((ccb->ccb_h.func_code & XPT_FC_QUEUED) == 0 || 1136 ch->batch == 0) { 1137 xpt_done(ccb); 1138 return; 1139 } 1140 1141 STAILQ_INSERT_TAIL(&ch->doneq, &ccb->ccb_h, sim_links.stqe); 1142 } 1143 1144 static void 1145 ahci_ch_intr(void *arg) 1146 { 1147 struct ahci_channel *ch = (struct ahci_channel *)arg; 1148 uint32_t istatus; 1149 1150 /* Read interrupt statuses. */ 1151 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1152 if (istatus == 0) 1153 return; 1154 1155 mtx_lock(&ch->mtx); 1156 ahci_ch_intr_main(ch, istatus); 1157 mtx_unlock(&ch->mtx); 1158 } 1159 1160 static void 1161 ahci_ch_intr_direct(void *arg) 1162 { 1163 struct ahci_channel *ch = (struct ahci_channel *)arg; 1164 struct ccb_hdr *ccb_h; 1165 uint32_t istatus; 1166 STAILQ_HEAD(, ccb_hdr) tmp_doneq = STAILQ_HEAD_INITIALIZER(tmp_doneq); 1167 1168 /* Read interrupt statuses. */ 1169 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1170 if (istatus == 0) 1171 return; 1172 1173 mtx_lock(&ch->mtx); 1174 ch->batch = 1; 1175 ahci_ch_intr_main(ch, istatus); 1176 ch->batch = 0; 1177 /* 1178 * Prevent the possibility of issues caused by processing the queue 1179 * while unlocked below by moving the contents to a local queue. 1180 */ 1181 STAILQ_CONCAT(&tmp_doneq, &ch->doneq); 1182 mtx_unlock(&ch->mtx); 1183 while ((ccb_h = STAILQ_FIRST(&tmp_doneq)) != NULL) { 1184 STAILQ_REMOVE_HEAD(&tmp_doneq, sim_links.stqe); 1185 xpt_done_direct((union ccb *)ccb_h); 1186 } 1187 } 1188 1189 static void 1190 ahci_ch_pm(void *arg) 1191 { 1192 struct ahci_channel *ch = (struct ahci_channel *)arg; 1193 uint32_t work; 1194 1195 if (ch->numrslots != 0) 1196 return; 1197 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1198 if (ch->pm_level == 4) 1199 work |= AHCI_P_CMD_PARTIAL; 1200 else 1201 work |= AHCI_P_CMD_SLUMBER; 1202 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1203 } 1204 1205 static void 1206 ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus) 1207 { 1208 uint32_t cstatus, serr = 0, sntf = 0, ok, err; 1209 enum ahci_err_type et; 1210 int i, ccs, port, reset = 0; 1211 1212 /* Clear interrupt statuses. */ 1213 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1214 /* Read command statuses. */ 1215 if (ch->numtslots != 0) 1216 cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1217 else 1218 cstatus = 0; 1219 if (ch->numrslots != ch->numtslots) 1220 cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI); 1221 /* Read SNTF in one of possible ways. */ 1222 if ((istatus & AHCI_P_IX_SDB) && 1223 (ch->pm_present || ch->curr[0].atapi != 0)) { 1224 if (ch->caps & AHCI_CAP_SSNTF) 1225 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1226 else if (ch->fbs_enabled) { 1227 u_int8_t *fis = ch->dma.rfis + 0x58; 1228 1229 for (i = 0; i < 16; i++) { 1230 if (fis[1] & 0x80) { 1231 fis[1] &= 0x7f; 1232 sntf |= 1 << i; 1233 } 1234 fis += 256; 1235 } 1236 } else { 1237 u_int8_t *fis = ch->dma.rfis + 0x58; 1238 1239 if (fis[1] & 0x80) 1240 sntf = (1 << (fis[1] & 0x0f)); 1241 } 1242 } 1243 /* Process PHY events */ 1244 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1245 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1246 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1247 if (serr) { 1248 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1249 reset = ahci_phy_check_events(ch, serr); 1250 } 1251 } 1252 /* Process cold presence detection events */ 1253 if ((istatus & AHCI_P_IX_CPD) && !reset) 1254 ahci_cpd_check_events(ch); 1255 /* Process command errors */ 1256 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1257 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1258 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1259 >> AHCI_P_CMD_CCS_SHIFT; 1260 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1261 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1262 // serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1263 port = -1; 1264 if (ch->fbs_enabled) { 1265 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1266 if (fbs & AHCI_P_FBS_SDE) { 1267 port = (fbs & AHCI_P_FBS_DWE) 1268 >> AHCI_P_FBS_DWE_SHIFT; 1269 } else { 1270 for (i = 0; i < 16; i++) { 1271 if (ch->numrslotspd[i] == 0) 1272 continue; 1273 if (port == -1) 1274 port = i; 1275 else if (port != i) { 1276 port = -2; 1277 break; 1278 } 1279 } 1280 } 1281 } 1282 err = ch->rslots & cstatus; 1283 } else { 1284 ccs = 0; 1285 err = 0; 1286 port = -1; 1287 } 1288 /* Complete all successfull commands. */ 1289 ok = ch->rslots & ~cstatus; 1290 for (i = 0; i < ch->numslots; i++) { 1291 if ((ok >> i) & 1) 1292 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1293 } 1294 /* On error, complete the rest of commands with error statuses. */ 1295 if (err) { 1296 if (ch->frozen) { 1297 union ccb *fccb = ch->frozen; 1298 ch->frozen = NULL; 1299 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1300 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1301 xpt_freeze_devq(fccb->ccb_h.path, 1); 1302 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1303 } 1304 ahci_done(ch, fccb); 1305 } 1306 for (i = 0; i < ch->numslots; i++) { 1307 /* XXX: reqests in loading state. */ 1308 if (((err >> i) & 1) == 0) 1309 continue; 1310 if (port >= 0 && 1311 ch->slot[i].ccb->ccb_h.target_id != port) 1312 continue; 1313 if (istatus & AHCI_P_IX_TFE) { 1314 if (port != -2) { 1315 /* Task File Error */ 1316 if (ch->numtslotspd[ 1317 ch->slot[i].ccb->ccb_h.target_id] == 0) { 1318 /* Untagged operation. */ 1319 if (i == ccs) 1320 et = AHCI_ERR_TFE; 1321 else 1322 et = AHCI_ERR_INNOCENT; 1323 } else { 1324 /* Tagged operation. */ 1325 et = AHCI_ERR_NCQ; 1326 } 1327 } else { 1328 et = AHCI_ERR_TFE; 1329 ch->fatalerr = 1; 1330 } 1331 } else if (istatus & AHCI_P_IX_IF) { 1332 if (ch->numtslots == 0 && i != ccs && port != -2) 1333 et = AHCI_ERR_INNOCENT; 1334 else 1335 et = AHCI_ERR_SATA; 1336 } else 1337 et = AHCI_ERR_INVALID; 1338 ahci_end_transaction(&ch->slot[i], et); 1339 } 1340 /* 1341 * We can't reinit port if there are some other 1342 * commands active, use resume to complete them. 1343 */ 1344 if (ch->rslots != 0 && !ch->recoverycmd) 1345 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1346 } 1347 /* Process NOTIFY events */ 1348 if (sntf) 1349 ahci_notify_events(ch, sntf); 1350 } 1351 1352 /* Must be called with channel locked. */ 1353 static int 1354 ahci_check_collision(struct ahci_channel *ch, union ccb *ccb) 1355 { 1356 int t = ccb->ccb_h.target_id; 1357 1358 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1359 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1360 /* Tagged command while we have no supported tag free. */ 1361 if (((~ch->oslots) & (0xffffffff >> (32 - 1362 ch->curr[t].tags))) == 0) 1363 return (1); 1364 /* If we have FBS */ 1365 if (ch->fbs_enabled) { 1366 /* Tagged command while untagged are active. */ 1367 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1368 return (1); 1369 } else { 1370 /* Tagged command while untagged are active. */ 1371 if (ch->numrslots != 0 && ch->numtslots == 0) 1372 return (1); 1373 /* Tagged command while tagged to other target is active. */ 1374 if (ch->numtslots != 0 && 1375 ch->taggedtarget != ccb->ccb_h.target_id) 1376 return (1); 1377 } 1378 } else { 1379 /* If we have FBS */ 1380 if (ch->fbs_enabled) { 1381 /* Untagged command while tagged are active. */ 1382 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1383 return (1); 1384 } else { 1385 /* Untagged command while tagged are active. */ 1386 if (ch->numrslots != 0 && ch->numtslots != 0) 1387 return (1); 1388 } 1389 } 1390 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1391 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1392 /* Atomic command while anything active. */ 1393 if (ch->numrslots != 0) 1394 return (1); 1395 } 1396 /* We have some atomic command running. */ 1397 if (ch->aslots != 0) 1398 return (1); 1399 return (0); 1400 } 1401 1402 /* Must be called with channel locked. */ 1403 static void 1404 ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb) 1405 { 1406 struct ahci_slot *slot; 1407 int tag, tags; 1408 1409 /* Choose empty slot. */ 1410 tags = ch->numslots; 1411 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1412 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1413 tags = ch->curr[ccb->ccb_h.target_id].tags; 1414 if (ch->lastslot + 1 < tags) 1415 tag = ffs(~(ch->oslots >> (ch->lastslot + 1))); 1416 else 1417 tag = 0; 1418 if (tag == 0 || tag + ch->lastslot >= tags) 1419 tag = ffs(~ch->oslots) - 1; 1420 else 1421 tag += ch->lastslot; 1422 ch->lastslot = tag; 1423 /* Occupy chosen slot. */ 1424 slot = &ch->slot[tag]; 1425 slot->ccb = ccb; 1426 /* Stop PM timer. */ 1427 if (ch->numrslots == 0 && ch->pm_level > 3) 1428 callout_stop(&ch->pm_timer); 1429 /* Update channel stats. */ 1430 ch->oslots |= (1 << tag); 1431 ch->numrslots++; 1432 ch->numrslotspd[ccb->ccb_h.target_id]++; 1433 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1434 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1435 ch->numtslots++; 1436 ch->numtslotspd[ccb->ccb_h.target_id]++; 1437 ch->taggedtarget = ccb->ccb_h.target_id; 1438 } 1439 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1440 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1441 ch->aslots |= (1 << tag); 1442 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1443 slot->state = AHCI_SLOT_LOADING; 1444 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb, 1445 ahci_dmasetprd, slot, 0); 1446 } else { 1447 slot->dma.nsegs = 0; 1448 ahci_execute_transaction(slot); 1449 } 1450 } 1451 1452 /* Locked by busdma engine. */ 1453 static void 1454 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1455 { 1456 struct ahci_slot *slot = arg; 1457 struct ahci_channel *ch = slot->ch; 1458 struct ahci_cmd_tab *ctp; 1459 struct ahci_dma_prd *prd; 1460 int i; 1461 1462 if (error) { 1463 device_printf(ch->dev, "DMA load error\n"); 1464 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1465 return; 1466 } 1467 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1468 /* Get a piece of the workspace for this request */ 1469 ctp = (struct ahci_cmd_tab *) 1470 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1471 /* Fill S/G table */ 1472 prd = &ctp->prd_tab[0]; 1473 for (i = 0; i < nsegs; i++) { 1474 prd[i].dba = htole64(segs[i].ds_addr); 1475 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1476 } 1477 slot->dma.nsegs = nsegs; 1478 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1479 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1480 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1481 ahci_execute_transaction(slot); 1482 } 1483 1484 /* Must be called with channel locked. */ 1485 static void 1486 ahci_execute_transaction(struct ahci_slot *slot) 1487 { 1488 struct ahci_channel *ch = slot->ch; 1489 struct ahci_cmd_tab *ctp; 1490 struct ahci_cmd_list *clp; 1491 union ccb *ccb = slot->ccb; 1492 int port = ccb->ccb_h.target_id & 0x0f; 1493 int fis_size, i, softreset; 1494 uint8_t *fis = ch->dma.rfis + 0x40; 1495 uint8_t val; 1496 1497 /* Get a piece of the workspace for this request */ 1498 ctp = (struct ahci_cmd_tab *) 1499 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1500 /* Setup the FIS for this request */ 1501 if (!(fis_size = ahci_setup_fis(ch, ctp, ccb, slot->slot))) { 1502 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1503 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1504 return; 1505 } 1506 /* Setup the command list entry */ 1507 clp = (struct ahci_cmd_list *) 1508 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1509 clp->cmd_flags = htole16( 1510 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1511 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1512 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1513 (fis_size / sizeof(u_int32_t)) | 1514 (port << 12)); 1515 clp->prd_length = htole16(slot->dma.nsegs); 1516 /* Special handling for Soft Reset command. */ 1517 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1518 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1519 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1520 softreset = 1; 1521 /* Kick controller into sane state */ 1522 ahci_stop(ch); 1523 ahci_clo(ch); 1524 ahci_start(ch, 0); 1525 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1526 } else { 1527 softreset = 2; 1528 /* Prepare FIS receive area for check. */ 1529 for (i = 0; i < 20; i++) 1530 fis[i] = 0xff; 1531 } 1532 } else 1533 softreset = 0; 1534 clp->bytecount = 0; 1535 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1536 (AHCI_CT_SIZE * slot->slot)); 1537 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1538 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1539 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1540 BUS_DMASYNC_PREREAD); 1541 /* Set ACTIVE bit for NCQ commands. */ 1542 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1543 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1544 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1545 } 1546 /* If FBS is enabled, set PMP port. */ 1547 if (ch->fbs_enabled) { 1548 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1549 (port << AHCI_P_FBS_DEV_SHIFT)); 1550 } 1551 /* Issue command to the controller. */ 1552 slot->state = AHCI_SLOT_RUNNING; 1553 ch->rslots |= (1 << slot->slot); 1554 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1555 /* Device reset commands doesn't interrupt. Poll them. */ 1556 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1557 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) { 1558 int count, timeout = ccb->ccb_h.timeout * 100; 1559 enum ahci_err_type et = AHCI_ERR_NONE; 1560 1561 for (count = 0; count < timeout; count++) { 1562 DELAY(10); 1563 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1564 break; 1565 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) && 1566 softreset != 1) { 1567 #if 0 1568 device_printf(ch->dev, 1569 "Poll error on slot %d, TFD: %04x\n", 1570 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1571 #endif 1572 et = AHCI_ERR_TFE; 1573 break; 1574 } 1575 /* Workaround for ATI SB600/SB700 chipsets. */ 1576 if (ccb->ccb_h.target_id == 15 && 1577 (ch->quirks & AHCI_Q_ATI_PMP_BUG) && 1578 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1579 et = AHCI_ERR_TIMEOUT; 1580 break; 1581 } 1582 } 1583 1584 /* 1585 * Marvell HBAs with non-RAID firmware do not wait for 1586 * readiness after soft reset, so we have to wait here. 1587 * Marvell RAIDs do not have this problem, but instead 1588 * sometimes forget to update FIS receive area, breaking 1589 * this wait. 1590 */ 1591 if ((ch->quirks & AHCI_Q_NOBSYRES) == 0 && 1592 (ch->quirks & AHCI_Q_ATI_PMP_BUG) == 0 && 1593 softreset == 2 && et == AHCI_ERR_NONE) { 1594 while ((val = fis[2]) & ATA_S_BUSY) { 1595 DELAY(10); 1596 if (count++ >= timeout) 1597 break; 1598 } 1599 } 1600 1601 if (timeout && (count >= timeout)) { 1602 device_printf(ch->dev, "Poll timeout on slot %d port %d\n", 1603 slot->slot, port); 1604 device_printf(ch->dev, "is %08x cs %08x ss %08x " 1605 "rs %08x tfd %02x serr %08x cmd %08x\n", 1606 ATA_INL(ch->r_mem, AHCI_P_IS), 1607 ATA_INL(ch->r_mem, AHCI_P_CI), 1608 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1609 ATA_INL(ch->r_mem, AHCI_P_TFD), 1610 ATA_INL(ch->r_mem, AHCI_P_SERR), 1611 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1612 et = AHCI_ERR_TIMEOUT; 1613 } 1614 1615 /* Kick controller into sane state and enable FBS. */ 1616 if (softreset == 2) 1617 ch->eslots |= (1 << slot->slot); 1618 ahci_end_transaction(slot, et); 1619 return; 1620 } 1621 /* Start command execution timeout */ 1622 callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout / 2, 1623 0, (timeout_t*)ahci_timeout, slot, 0); 1624 return; 1625 } 1626 1627 /* Must be called with channel locked. */ 1628 static void 1629 ahci_process_timeout(struct ahci_channel *ch) 1630 { 1631 int i; 1632 1633 mtx_assert(&ch->mtx, MA_OWNED); 1634 /* Handle the rest of commands. */ 1635 for (i = 0; i < ch->numslots; i++) { 1636 /* Do we have a running request on slot? */ 1637 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1638 continue; 1639 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 1640 } 1641 } 1642 1643 /* Must be called with channel locked. */ 1644 static void 1645 ahci_rearm_timeout(struct ahci_channel *ch) 1646 { 1647 int i; 1648 1649 mtx_assert(&ch->mtx, MA_OWNED); 1650 for (i = 0; i < ch->numslots; i++) { 1651 struct ahci_slot *slot = &ch->slot[i]; 1652 1653 /* Do we have a running request on slot? */ 1654 if (slot->state < AHCI_SLOT_RUNNING) 1655 continue; 1656 if ((ch->toslots & (1 << i)) == 0) 1657 continue; 1658 callout_reset_sbt(&slot->timeout, 1659 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0, 1660 (timeout_t*)ahci_timeout, slot, 0); 1661 } 1662 } 1663 1664 /* Locked by callout mechanism. */ 1665 static void 1666 ahci_timeout(struct ahci_slot *slot) 1667 { 1668 struct ahci_channel *ch = slot->ch; 1669 device_t dev = ch->dev; 1670 uint32_t sstatus; 1671 int ccs; 1672 int i; 1673 1674 /* Check for stale timeout. */ 1675 if (slot->state < AHCI_SLOT_RUNNING) 1676 return; 1677 1678 /* Check if slot was not being executed last time we checked. */ 1679 if (slot->state < AHCI_SLOT_EXECUTING) { 1680 /* Check if slot started executing. */ 1681 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1682 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1683 >> AHCI_P_CMD_CCS_SHIFT; 1684 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 1685 ch->fbs_enabled || ch->wrongccs) 1686 slot->state = AHCI_SLOT_EXECUTING; 1687 else if ((ch->rslots & (1 << ccs)) == 0) { 1688 ch->wrongccs = 1; 1689 slot->state = AHCI_SLOT_EXECUTING; 1690 } 1691 1692 callout_reset_sbt(&slot->timeout, 1693 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0, 1694 (timeout_t*)ahci_timeout, slot, 0); 1695 return; 1696 } 1697 1698 device_printf(dev, "Timeout on slot %d port %d\n", 1699 slot->slot, slot->ccb->ccb_h.target_id & 0x0f); 1700 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x " 1701 "serr %08x cmd %08x\n", 1702 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 1703 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1704 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR), 1705 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1706 1707 /* Handle frozen command. */ 1708 if (ch->frozen) { 1709 union ccb *fccb = ch->frozen; 1710 ch->frozen = NULL; 1711 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1712 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1713 xpt_freeze_devq(fccb->ccb_h.path, 1); 1714 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1715 } 1716 ahci_done(ch, fccb); 1717 } 1718 if (!ch->fbs_enabled && !ch->wrongccs) { 1719 /* Without FBS we know real timeout source. */ 1720 ch->fatalerr = 1; 1721 /* Handle command with timeout. */ 1722 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 1723 /* Handle the rest of commands. */ 1724 for (i = 0; i < ch->numslots; i++) { 1725 /* Do we have a running request on slot? */ 1726 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1727 continue; 1728 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1729 } 1730 } else { 1731 /* With FBS we wait for other commands timeout and pray. */ 1732 if (ch->toslots == 0) 1733 xpt_freeze_simq(ch->sim, 1); 1734 ch->toslots |= (1 << slot->slot); 1735 if ((ch->rslots & ~ch->toslots) == 0) 1736 ahci_process_timeout(ch); 1737 else 1738 device_printf(dev, " ... waiting for slots %08x\n", 1739 ch->rslots & ~ch->toslots); 1740 } 1741 } 1742 1743 /* Must be called with channel locked. */ 1744 static void 1745 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 1746 { 1747 struct ahci_channel *ch = slot->ch; 1748 union ccb *ccb = slot->ccb; 1749 struct ahci_cmd_list *clp; 1750 int lastto; 1751 uint32_t sig; 1752 1753 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1754 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1755 clp = (struct ahci_cmd_list *) 1756 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1757 /* Read result registers to the result struct 1758 * May be incorrect if several commands finished same time, 1759 * so read only when sure or have to. 1760 */ 1761 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1762 struct ata_res *res = &ccb->ataio.res; 1763 1764 if ((et == AHCI_ERR_TFE) || 1765 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1766 u_int8_t *fis = ch->dma.rfis + 0x40; 1767 1768 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1769 BUS_DMASYNC_POSTREAD); 1770 if (ch->fbs_enabled) { 1771 fis += ccb->ccb_h.target_id * 256; 1772 res->status = fis[2]; 1773 res->error = fis[3]; 1774 } else { 1775 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 1776 1777 res->status = tfd; 1778 res->error = tfd >> 8; 1779 } 1780 res->lba_low = fis[4]; 1781 res->lba_mid = fis[5]; 1782 res->lba_high = fis[6]; 1783 res->device = fis[7]; 1784 res->lba_low_exp = fis[8]; 1785 res->lba_mid_exp = fis[9]; 1786 res->lba_high_exp = fis[10]; 1787 res->sector_count = fis[12]; 1788 res->sector_count_exp = fis[13]; 1789 1790 /* 1791 * Some weird controllers do not return signature in 1792 * FIS receive area. Read it from PxSIG register. 1793 */ 1794 if ((ch->quirks & AHCI_Q_ALTSIG) && 1795 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1796 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 1797 sig = ATA_INL(ch->r_mem, AHCI_P_SIG); 1798 res->lba_high = sig >> 24; 1799 res->lba_mid = sig >> 16; 1800 res->lba_low = sig >> 8; 1801 res->sector_count = sig; 1802 } 1803 } else 1804 bzero(res, sizeof(*res)); 1805 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 1806 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 1807 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 1808 ccb->ataio.resid = 1809 ccb->ataio.dxfer_len - le32toh(clp->bytecount); 1810 } 1811 } else { 1812 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 1813 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 1814 ccb->csio.resid = 1815 ccb->csio.dxfer_len - le32toh(clp->bytecount); 1816 } 1817 } 1818 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1819 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1820 (ccb->ccb_h.flags & CAM_DIR_IN) ? 1821 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1822 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 1823 } 1824 if (et != AHCI_ERR_NONE) 1825 ch->eslots |= (1 << slot->slot); 1826 /* In case of error, freeze device for proper recovery. */ 1827 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) && 1828 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 1829 xpt_freeze_devq(ccb->ccb_h.path, 1); 1830 ccb->ccb_h.status |= CAM_DEV_QFRZN; 1831 } 1832 /* Set proper result status. */ 1833 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1834 switch (et) { 1835 case AHCI_ERR_NONE: 1836 ccb->ccb_h.status |= CAM_REQ_CMP; 1837 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 1838 ccb->csio.scsi_status = SCSI_STATUS_OK; 1839 break; 1840 case AHCI_ERR_INVALID: 1841 ch->fatalerr = 1; 1842 ccb->ccb_h.status |= CAM_REQ_INVALID; 1843 break; 1844 case AHCI_ERR_INNOCENT: 1845 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 1846 break; 1847 case AHCI_ERR_TFE: 1848 case AHCI_ERR_NCQ: 1849 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1850 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1851 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1852 } else { 1853 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 1854 } 1855 break; 1856 case AHCI_ERR_SATA: 1857 ch->fatalerr = 1; 1858 if (!ch->recoverycmd) { 1859 xpt_freeze_simq(ch->sim, 1); 1860 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1861 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1862 } 1863 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 1864 break; 1865 case AHCI_ERR_TIMEOUT: 1866 if (!ch->recoverycmd) { 1867 xpt_freeze_simq(ch->sim, 1); 1868 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1869 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1870 } 1871 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1872 break; 1873 default: 1874 ch->fatalerr = 1; 1875 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 1876 } 1877 /* Free slot. */ 1878 ch->oslots &= ~(1 << slot->slot); 1879 ch->rslots &= ~(1 << slot->slot); 1880 ch->aslots &= ~(1 << slot->slot); 1881 slot->state = AHCI_SLOT_EMPTY; 1882 slot->ccb = NULL; 1883 /* Update channel stats. */ 1884 ch->numrslots--; 1885 ch->numrslotspd[ccb->ccb_h.target_id]--; 1886 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1887 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1888 ch->numtslots--; 1889 ch->numtslotspd[ccb->ccb_h.target_id]--; 1890 } 1891 /* Cancel timeout state if request completed normally. */ 1892 if (et != AHCI_ERR_TIMEOUT) { 1893 lastto = (ch->toslots == (1 << slot->slot)); 1894 ch->toslots &= ~(1 << slot->slot); 1895 if (lastto) 1896 xpt_release_simq(ch->sim, TRUE); 1897 } 1898 /* If it was first request of reset sequence and there is no error, 1899 * proceed to second request. */ 1900 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1901 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1902 (ccb->ataio.cmd.control & ATA_A_RESET) && 1903 et == AHCI_ERR_NONE) { 1904 ccb->ataio.cmd.control &= ~ATA_A_RESET; 1905 ahci_begin_transaction(ch, ccb); 1906 return; 1907 } 1908 /* If it was our READ LOG command - process it. */ 1909 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 1910 ahci_process_read_log(ch, ccb); 1911 /* If it was our REQUEST SENSE command - process it. */ 1912 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 1913 ahci_process_request_sense(ch, ccb); 1914 /* If it was NCQ or ATAPI command error, put result on hold. */ 1915 } else if (et == AHCI_ERR_NCQ || 1916 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 1917 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 1918 ch->hold[slot->slot] = ccb; 1919 ch->numhslots++; 1920 } else 1921 ahci_done(ch, ccb); 1922 /* If we have no other active commands, ... */ 1923 if (ch->rslots == 0) { 1924 /* if there was fatal error - reset port. */ 1925 if (ch->toslots != 0 || ch->fatalerr) { 1926 ahci_reset(ch); 1927 } else { 1928 /* if we have slots in error, we can reinit port. */ 1929 if (ch->eslots != 0) { 1930 ahci_stop(ch); 1931 ahci_clo(ch); 1932 ahci_start(ch, 1); 1933 } 1934 /* if there commands on hold, we can do READ LOG. */ 1935 if (!ch->recoverycmd && ch->numhslots) 1936 ahci_issue_recovery(ch); 1937 } 1938 /* If all the rest of commands are in timeout - give them chance. */ 1939 } else if ((ch->rslots & ~ch->toslots) == 0 && 1940 et != AHCI_ERR_TIMEOUT) 1941 ahci_rearm_timeout(ch); 1942 /* Unfreeze frozen command. */ 1943 if (ch->frozen && !ahci_check_collision(ch, ch->frozen)) { 1944 union ccb *fccb = ch->frozen; 1945 ch->frozen = NULL; 1946 ahci_begin_transaction(ch, fccb); 1947 xpt_release_simq(ch->sim, TRUE); 1948 } 1949 /* Start PM timer. */ 1950 if (ch->numrslots == 0 && ch->pm_level > 3 && 1951 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 1952 callout_schedule(&ch->pm_timer, 1953 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 1954 } 1955 } 1956 1957 static void 1958 ahci_issue_recovery(struct ahci_channel *ch) 1959 { 1960 union ccb *ccb; 1961 struct ccb_ataio *ataio; 1962 struct ccb_scsiio *csio; 1963 int i; 1964 1965 /* Find some held command. */ 1966 for (i = 0; i < ch->numslots; i++) { 1967 if (ch->hold[i]) 1968 break; 1969 } 1970 ccb = xpt_alloc_ccb_nowait(); 1971 if (ccb == NULL) { 1972 device_printf(ch->dev, "Unable to allocate recovery command\n"); 1973 completeall: 1974 /* We can't do anything -- complete held commands. */ 1975 for (i = 0; i < ch->numslots; i++) { 1976 if (ch->hold[i] == NULL) 1977 continue; 1978 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1979 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 1980 ahci_done(ch, ch->hold[i]); 1981 ch->hold[i] = NULL; 1982 ch->numhslots--; 1983 } 1984 ahci_reset(ch); 1985 return; 1986 } 1987 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 1988 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1989 /* READ LOG */ 1990 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 1991 ccb->ccb_h.func_code = XPT_ATA_IO; 1992 ccb->ccb_h.flags = CAM_DIR_IN; 1993 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 1994 ataio = &ccb->ataio; 1995 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 1996 if (ataio->data_ptr == NULL) { 1997 xpt_free_ccb(ccb); 1998 device_printf(ch->dev, 1999 "Unable to allocate memory for READ LOG command\n"); 2000 goto completeall; 2001 } 2002 ataio->dxfer_len = 512; 2003 bzero(&ataio->cmd, sizeof(ataio->cmd)); 2004 ataio->cmd.flags = CAM_ATAIO_48BIT; 2005 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 2006 ataio->cmd.sector_count = 1; 2007 ataio->cmd.sector_count_exp = 0; 2008 ataio->cmd.lba_low = 0x10; 2009 ataio->cmd.lba_mid = 0; 2010 ataio->cmd.lba_mid_exp = 0; 2011 } else { 2012 /* REQUEST SENSE */ 2013 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 2014 ccb->ccb_h.recovery_slot = i; 2015 ccb->ccb_h.func_code = XPT_SCSI_IO; 2016 ccb->ccb_h.flags = CAM_DIR_IN; 2017 ccb->ccb_h.status = 0; 2018 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2019 csio = &ccb->csio; 2020 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 2021 csio->dxfer_len = ch->hold[i]->csio.sense_len; 2022 csio->cdb_len = 6; 2023 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 2024 csio->cdb_io.cdb_bytes[0] = 0x03; 2025 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 2026 } 2027 /* Freeze SIM while doing recovery. */ 2028 ch->recoverycmd = 1; 2029 xpt_freeze_simq(ch->sim, 1); 2030 ahci_begin_transaction(ch, ccb); 2031 } 2032 2033 static void 2034 ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb) 2035 { 2036 uint8_t *data; 2037 struct ata_res *res; 2038 int i; 2039 2040 ch->recoverycmd = 0; 2041 2042 data = ccb->ataio.data_ptr; 2043 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2044 (data[0] & 0x80) == 0) { 2045 for (i = 0; i < ch->numslots; i++) { 2046 if (!ch->hold[i]) 2047 continue; 2048 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2049 continue; 2050 if ((data[0] & 0x1F) == i) { 2051 res = &ch->hold[i]->ataio.res; 2052 res->status = data[2]; 2053 res->error = data[3]; 2054 res->lba_low = data[4]; 2055 res->lba_mid = data[5]; 2056 res->lba_high = data[6]; 2057 res->device = data[7]; 2058 res->lba_low_exp = data[8]; 2059 res->lba_mid_exp = data[9]; 2060 res->lba_high_exp = data[10]; 2061 res->sector_count = data[12]; 2062 res->sector_count_exp = data[13]; 2063 } else { 2064 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2065 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2066 } 2067 ahci_done(ch, ch->hold[i]); 2068 ch->hold[i] = NULL; 2069 ch->numhslots--; 2070 } 2071 } else { 2072 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2073 device_printf(ch->dev, "Error while READ LOG EXT\n"); 2074 else if ((data[0] & 0x80) == 0) { 2075 device_printf(ch->dev, "Non-queued command error in READ LOG EXT\n"); 2076 } 2077 for (i = 0; i < ch->numslots; i++) { 2078 if (!ch->hold[i]) 2079 continue; 2080 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2081 continue; 2082 ahci_done(ch, ch->hold[i]); 2083 ch->hold[i] = NULL; 2084 ch->numhslots--; 2085 } 2086 } 2087 free(ccb->ataio.data_ptr, M_AHCI); 2088 xpt_free_ccb(ccb); 2089 xpt_release_simq(ch->sim, TRUE); 2090 } 2091 2092 static void 2093 ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb) 2094 { 2095 int i; 2096 2097 ch->recoverycmd = 0; 2098 2099 i = ccb->ccb_h.recovery_slot; 2100 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 2101 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 2102 } else { 2103 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2104 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 2105 } 2106 ahci_done(ch, ch->hold[i]); 2107 ch->hold[i] = NULL; 2108 ch->numhslots--; 2109 xpt_free_ccb(ccb); 2110 xpt_release_simq(ch->sim, TRUE); 2111 } 2112 2113 static void 2114 ahci_start(struct ahci_channel *ch, int fbs) 2115 { 2116 u_int32_t cmd; 2117 2118 /* Run the channel start callback, if any. */ 2119 if (ch->start) 2120 ch->start(ch); 2121 2122 /* Clear SATA error register */ 2123 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2124 /* Clear any interrupts pending on this channel */ 2125 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2126 /* Configure FIS-based switching if supported. */ 2127 if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2128 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2129 ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2130 ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2131 } 2132 /* Start operations on this channel */ 2133 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2134 cmd &= ~AHCI_P_CMD_PMA; 2135 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2136 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2137 } 2138 2139 static void 2140 ahci_stop(struct ahci_channel *ch) 2141 { 2142 u_int32_t cmd; 2143 int timeout; 2144 2145 /* Kill all activity on this channel */ 2146 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2147 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2148 /* Wait for activity stop. */ 2149 timeout = 0; 2150 do { 2151 DELAY(10); 2152 if (timeout++ > 50000) { 2153 device_printf(ch->dev, "stopping AHCI engine failed\n"); 2154 break; 2155 } 2156 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2157 ch->eslots = 0; 2158 } 2159 2160 static void 2161 ahci_clo(struct ahci_channel *ch) 2162 { 2163 u_int32_t cmd; 2164 int timeout; 2165 2166 /* Issue Command List Override if supported */ 2167 if (ch->caps & AHCI_CAP_SCLO) { 2168 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2169 cmd |= AHCI_P_CMD_CLO; 2170 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2171 timeout = 0; 2172 do { 2173 DELAY(10); 2174 if (timeout++ > 50000) { 2175 device_printf(ch->dev, "executing CLO failed\n"); 2176 break; 2177 } 2178 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2179 } 2180 } 2181 2182 static void 2183 ahci_stop_fr(struct ahci_channel *ch) 2184 { 2185 u_int32_t cmd; 2186 int timeout; 2187 2188 /* Kill all FIS reception on this channel */ 2189 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2190 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2191 /* Wait for FIS reception stop. */ 2192 timeout = 0; 2193 do { 2194 DELAY(10); 2195 if (timeout++ > 50000) { 2196 device_printf(ch->dev, "stopping AHCI FR engine failed\n"); 2197 break; 2198 } 2199 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2200 } 2201 2202 static void 2203 ahci_start_fr(struct ahci_channel *ch) 2204 { 2205 u_int32_t cmd; 2206 2207 /* Start FIS reception on this channel */ 2208 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2209 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2210 } 2211 2212 static int 2213 ahci_wait_ready(struct ahci_channel *ch, int t, int t0) 2214 { 2215 int timeout = 0; 2216 uint32_t val; 2217 2218 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2219 (ATA_S_BUSY | ATA_S_DRQ)) { 2220 if (timeout > t) { 2221 if (t != 0) { 2222 device_printf(ch->dev, 2223 "AHCI reset: device not ready after %dms " 2224 "(tfd = %08x)\n", 2225 MAX(t, 0) + t0, val); 2226 } 2227 return (EBUSY); 2228 } 2229 DELAY(1000); 2230 timeout++; 2231 } 2232 if (bootverbose) 2233 device_printf(ch->dev, "AHCI reset: device ready after %dms\n", 2234 timeout + t0); 2235 return (0); 2236 } 2237 2238 static void 2239 ahci_reset_to(void *arg) 2240 { 2241 struct ahci_channel *ch = arg; 2242 2243 if (ch->resetting == 0) 2244 return; 2245 ch->resetting--; 2246 if (ahci_wait_ready(ch, ch->resetting == 0 ? -1 : 0, 2247 (310 - ch->resetting) * 100) == 0) { 2248 ch->resetting = 0; 2249 ahci_start(ch, 1); 2250 xpt_release_simq(ch->sim, TRUE); 2251 return; 2252 } 2253 if (ch->resetting == 0) { 2254 ahci_clo(ch); 2255 ahci_start(ch, 1); 2256 xpt_release_simq(ch->sim, TRUE); 2257 return; 2258 } 2259 callout_schedule(&ch->reset_timer, hz / 10); 2260 } 2261 2262 static void 2263 ahci_reset(struct ahci_channel *ch) 2264 { 2265 struct ahci_controller *ctlr = device_get_softc(device_get_parent(ch->dev)); 2266 int i; 2267 2268 xpt_freeze_simq(ch->sim, 1); 2269 if (bootverbose) 2270 device_printf(ch->dev, "AHCI reset...\n"); 2271 /* Forget about previous reset. */ 2272 if (ch->resetting) { 2273 ch->resetting = 0; 2274 callout_stop(&ch->reset_timer); 2275 xpt_release_simq(ch->sim, TRUE); 2276 } 2277 /* Requeue freezed command. */ 2278 if (ch->frozen) { 2279 union ccb *fccb = ch->frozen; 2280 ch->frozen = NULL; 2281 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2282 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2283 xpt_freeze_devq(fccb->ccb_h.path, 1); 2284 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2285 } 2286 ahci_done(ch, fccb); 2287 } 2288 /* Kill the engine and requeue all running commands. */ 2289 ahci_stop(ch); 2290 for (i = 0; i < ch->numslots; i++) { 2291 /* Do we have a running request on slot? */ 2292 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2293 continue; 2294 /* XXX; Commands in loading state. */ 2295 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2296 } 2297 for (i = 0; i < ch->numslots; i++) { 2298 if (!ch->hold[i]) 2299 continue; 2300 ahci_done(ch, ch->hold[i]); 2301 ch->hold[i] = NULL; 2302 ch->numhslots--; 2303 } 2304 if (ch->toslots != 0) 2305 xpt_release_simq(ch->sim, TRUE); 2306 ch->eslots = 0; 2307 ch->toslots = 0; 2308 ch->wrongccs = 0; 2309 ch->fatalerr = 0; 2310 /* Tell the XPT about the event */ 2311 xpt_async(AC_BUS_RESET, ch->path, NULL); 2312 /* Disable port interrupts */ 2313 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2314 /* Reset and reconnect PHY, */ 2315 if (!ahci_sata_phy_reset(ch)) { 2316 if (bootverbose) 2317 device_printf(ch->dev, 2318 "AHCI reset: device not found\n"); 2319 ch->devices = 0; 2320 /* Enable wanted port interrupts */ 2321 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2322 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2323 AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2324 xpt_release_simq(ch->sim, TRUE); 2325 return; 2326 } 2327 if (bootverbose) 2328 device_printf(ch->dev, "AHCI reset: device found\n"); 2329 /* Wait for clearing busy status. */ 2330 if (ahci_wait_ready(ch, dumping ? 31000 : 0, 0)) { 2331 if (dumping) 2332 ahci_clo(ch); 2333 else 2334 ch->resetting = 310; 2335 } 2336 ch->devices = 1; 2337 /* Enable wanted port interrupts */ 2338 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2339 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2340 AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2341 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2342 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC | 2343 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2344 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2345 if (ch->resetting) 2346 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, ch); 2347 else { 2348 ahci_start(ch, 1); 2349 xpt_release_simq(ch->sim, TRUE); 2350 } 2351 } 2352 2353 static int 2354 ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2355 { 2356 u_int8_t *fis = &ctp->cfis[0]; 2357 2358 bzero(fis, 20); 2359 fis[0] = 0x27; /* host to device */ 2360 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2361 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2362 fis[1] |= 0x80; 2363 fis[2] = ATA_PACKET_CMD; 2364 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2365 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2366 fis[3] = ATA_F_DMA; 2367 else { 2368 fis[5] = ccb->csio.dxfer_len; 2369 fis[6] = ccb->csio.dxfer_len >> 8; 2370 } 2371 fis[7] = ATA_D_LBA; 2372 fis[15] = ATA_A_4BIT; 2373 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2374 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2375 ctp->acmd, ccb->csio.cdb_len); 2376 bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len); 2377 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2378 fis[1] |= 0x80; 2379 fis[2] = ccb->ataio.cmd.command; 2380 fis[3] = ccb->ataio.cmd.features; 2381 fis[4] = ccb->ataio.cmd.lba_low; 2382 fis[5] = ccb->ataio.cmd.lba_mid; 2383 fis[6] = ccb->ataio.cmd.lba_high; 2384 fis[7] = ccb->ataio.cmd.device; 2385 fis[8] = ccb->ataio.cmd.lba_low_exp; 2386 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2387 fis[10] = ccb->ataio.cmd.lba_high_exp; 2388 fis[11] = ccb->ataio.cmd.features_exp; 2389 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2390 fis[12] = tag << 3; 2391 fis[13] = 0; 2392 } else { 2393 fis[12] = ccb->ataio.cmd.sector_count; 2394 fis[13] = ccb->ataio.cmd.sector_count_exp; 2395 } 2396 fis[15] = ATA_A_4BIT; 2397 } else { 2398 fis[15] = ccb->ataio.cmd.control; 2399 } 2400 return (20); 2401 } 2402 2403 static int 2404 ahci_sata_connect(struct ahci_channel *ch) 2405 { 2406 u_int32_t status; 2407 int timeout, found = 0; 2408 2409 /* Wait up to 100ms for "connect well" */ 2410 for (timeout = 0; timeout < 1000 ; timeout++) { 2411 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2412 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 2413 found = 1; 2414 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2415 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2416 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2417 break; 2418 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2419 if (bootverbose) { 2420 device_printf(ch->dev, "SATA offline status=%08x\n", 2421 status); 2422 } 2423 return (0); 2424 } 2425 if (found == 0 && timeout >= 100) 2426 break; 2427 DELAY(100); 2428 } 2429 if (timeout >= 1000 || !found) { 2430 if (bootverbose) { 2431 device_printf(ch->dev, 2432 "SATA connect timeout time=%dus status=%08x\n", 2433 timeout * 100, status); 2434 } 2435 return (0); 2436 } 2437 if (bootverbose) { 2438 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n", 2439 timeout * 100, status); 2440 } 2441 /* Clear SATA error register */ 2442 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2443 return (1); 2444 } 2445 2446 static int 2447 ahci_sata_phy_reset(struct ahci_channel *ch) 2448 { 2449 int sata_rev; 2450 uint32_t val; 2451 2452 if (ch->listening) { 2453 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2454 val |= AHCI_P_CMD_SUD; 2455 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2456 ch->listening = 0; 2457 } 2458 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2459 if (sata_rev == 1) 2460 val = ATA_SC_SPD_SPEED_GEN1; 2461 else if (sata_rev == 2) 2462 val = ATA_SC_SPD_SPEED_GEN2; 2463 else if (sata_rev == 3) 2464 val = ATA_SC_SPD_SPEED_GEN3; 2465 else 2466 val = 0; 2467 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2468 ATA_SC_DET_RESET | val | 2469 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2470 DELAY(1000); 2471 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2472 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2473 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2474 if (!ahci_sata_connect(ch)) { 2475 if (ch->caps & AHCI_CAP_SSS) { 2476 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2477 val &= ~AHCI_P_CMD_SUD; 2478 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2479 ch->listening = 1; 2480 } else if (ch->pm_level > 0) 2481 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2482 return (0); 2483 } 2484 return (1); 2485 } 2486 2487 static int 2488 ahci_check_ids(struct ahci_channel *ch, union ccb *ccb) 2489 { 2490 2491 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) { 2492 ccb->ccb_h.status = CAM_TID_INVALID; 2493 ahci_done(ch, ccb); 2494 return (-1); 2495 } 2496 if (ccb->ccb_h.target_lun != 0) { 2497 ccb->ccb_h.status = CAM_LUN_INVALID; 2498 ahci_done(ch, ccb); 2499 return (-1); 2500 } 2501 return (0); 2502 } 2503 2504 static void 2505 ahciaction(struct cam_sim *sim, union ccb *ccb) 2506 { 2507 struct ahci_channel *ch; 2508 2509 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2510 ccb->ccb_h.func_code)); 2511 2512 ch = (struct ahci_channel *)cam_sim_softc(sim); 2513 switch (ccb->ccb_h.func_code) { 2514 /* Common cases first */ 2515 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2516 case XPT_SCSI_IO: 2517 if (ahci_check_ids(ch, ccb)) 2518 return; 2519 if (ch->devices == 0 || 2520 (ch->pm_present == 0 && 2521 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2522 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2523 break; 2524 } 2525 ccb->ccb_h.recovery_type = RECOVERY_NONE; 2526 /* Check for command collision. */ 2527 if (ahci_check_collision(ch, ccb)) { 2528 /* Freeze command. */ 2529 ch->frozen = ccb; 2530 /* We have only one frozen slot, so freeze simq also. */ 2531 xpt_freeze_simq(ch->sim, 1); 2532 return; 2533 } 2534 ahci_begin_transaction(ch, ccb); 2535 return; 2536 case XPT_EN_LUN: /* Enable LUN as a target */ 2537 case XPT_TARGET_IO: /* Execute target I/O request */ 2538 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2539 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2540 case XPT_ABORT: /* Abort the specified CCB */ 2541 /* XXX Implement */ 2542 ccb->ccb_h.status = CAM_REQ_INVALID; 2543 break; 2544 case XPT_SET_TRAN_SETTINGS: 2545 { 2546 struct ccb_trans_settings *cts = &ccb->cts; 2547 struct ahci_device *d; 2548 2549 if (ahci_check_ids(ch, ccb)) 2550 return; 2551 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2552 d = &ch->curr[ccb->ccb_h.target_id]; 2553 else 2554 d = &ch->user[ccb->ccb_h.target_id]; 2555 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2556 d->revision = cts->xport_specific.sata.revision; 2557 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2558 d->mode = cts->xport_specific.sata.mode; 2559 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2560 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2561 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2562 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2563 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2564 ch->pm_present = cts->xport_specific.sata.pm_present; 2565 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2566 d->atapi = cts->xport_specific.sata.atapi; 2567 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2568 d->caps = cts->xport_specific.sata.caps; 2569 ccb->ccb_h.status = CAM_REQ_CMP; 2570 break; 2571 } 2572 case XPT_GET_TRAN_SETTINGS: 2573 /* Get default/user set transfer settings for the target */ 2574 { 2575 struct ccb_trans_settings *cts = &ccb->cts; 2576 struct ahci_device *d; 2577 uint32_t status; 2578 2579 if (ahci_check_ids(ch, ccb)) 2580 return; 2581 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2582 d = &ch->curr[ccb->ccb_h.target_id]; 2583 else 2584 d = &ch->user[ccb->ccb_h.target_id]; 2585 cts->protocol = PROTO_UNSPECIFIED; 2586 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2587 cts->transport = XPORT_SATA; 2588 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2589 cts->proto_specific.valid = 0; 2590 cts->xport_specific.sata.valid = 0; 2591 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2592 (ccb->ccb_h.target_id == 15 || 2593 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2594 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2595 if (status & 0x0f0) { 2596 cts->xport_specific.sata.revision = 2597 (status & 0x0f0) >> 4; 2598 cts->xport_specific.sata.valid |= 2599 CTS_SATA_VALID_REVISION; 2600 } 2601 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2602 if (ch->pm_level) { 2603 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC)) 2604 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2605 if (ch->caps2 & AHCI_CAP2_APST) 2606 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST; 2607 } 2608 if ((ch->caps & AHCI_CAP_SNCQ) && 2609 (ch->quirks & AHCI_Q_NOAA) == 0) 2610 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA; 2611 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 2612 cts->xport_specific.sata.caps &= 2613 ch->user[ccb->ccb_h.target_id].caps; 2614 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2615 } else { 2616 cts->xport_specific.sata.revision = d->revision; 2617 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2618 cts->xport_specific.sata.caps = d->caps; 2619 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2620 } 2621 cts->xport_specific.sata.mode = d->mode; 2622 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2623 cts->xport_specific.sata.bytecount = d->bytecount; 2624 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2625 cts->xport_specific.sata.pm_present = ch->pm_present; 2626 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2627 cts->xport_specific.sata.tags = d->tags; 2628 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2629 cts->xport_specific.sata.atapi = d->atapi; 2630 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2631 ccb->ccb_h.status = CAM_REQ_CMP; 2632 break; 2633 } 2634 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2635 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2636 ahci_reset(ch); 2637 ccb->ccb_h.status = CAM_REQ_CMP; 2638 break; 2639 case XPT_TERM_IO: /* Terminate the I/O process */ 2640 /* XXX Implement */ 2641 ccb->ccb_h.status = CAM_REQ_INVALID; 2642 break; 2643 case XPT_PATH_INQ: /* Path routing inquiry */ 2644 { 2645 struct ccb_pathinq *cpi = &ccb->cpi; 2646 2647 cpi->version_num = 1; /* XXX??? */ 2648 cpi->hba_inquiry = PI_SDTR_ABLE; 2649 if (ch->caps & AHCI_CAP_SNCQ) 2650 cpi->hba_inquiry |= PI_TAG_ABLE; 2651 if (ch->caps & AHCI_CAP_SPM) 2652 cpi->hba_inquiry |= PI_SATAPM; 2653 cpi->target_sprt = 0; 2654 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED; 2655 cpi->hba_eng_cnt = 0; 2656 if (ch->caps & AHCI_CAP_SPM) 2657 cpi->max_target = 15; 2658 else 2659 cpi->max_target = 0; 2660 cpi->max_lun = 0; 2661 cpi->initiator_id = 0; 2662 cpi->bus_id = cam_sim_bus(sim); 2663 cpi->base_transfer_speed = 150000; 2664 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2665 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 2666 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2667 cpi->unit_number = cam_sim_unit(sim); 2668 cpi->transport = XPORT_SATA; 2669 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2670 cpi->protocol = PROTO_ATA; 2671 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2672 cpi->maxio = MAXPHYS; 2673 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 2674 if (ch->quirks & AHCI_Q_MAXIO_64K) 2675 cpi->maxio = min(cpi->maxio, 128 * 512); 2676 cpi->hba_vendor = ch->vendorid; 2677 cpi->hba_device = ch->deviceid; 2678 cpi->hba_subvendor = ch->subvendorid; 2679 cpi->hba_subdevice = ch->subdeviceid; 2680 cpi->ccb_h.status = CAM_REQ_CMP; 2681 break; 2682 } 2683 default: 2684 ccb->ccb_h.status = CAM_REQ_INVALID; 2685 break; 2686 } 2687 ahci_done(ch, ccb); 2688 } 2689 2690 static void 2691 ahcipoll(struct cam_sim *sim) 2692 { 2693 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 2694 uint32_t istatus; 2695 2696 /* Read interrupt statuses and process if any. */ 2697 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 2698 if (istatus != 0) 2699 ahci_ch_intr_main(ch, istatus); 2700 if (ch->resetting != 0 && 2701 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) { 2702 ch->resetpolldiv = 1000; 2703 ahci_reset_to(ch); 2704 } 2705 } 2706 MODULE_VERSION(ahci, 1); 2707 MODULE_DEPEND(ahci, cam, 1, 1, 1); 2708