1 /*- 2 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/sema.h> 41 #include <sys/taskqueue.h> 42 #include <vm/uma.h> 43 #include <machine/stdarg.h> 44 #include <machine/resource.h> 45 #include <machine/bus.h> 46 #include <sys/rman.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include "ahci.h" 50 51 #include <cam/cam.h> 52 #include <cam/cam_ccb.h> 53 #include <cam/cam_sim.h> 54 #include <cam/cam_xpt_sim.h> 55 #include <cam/cam_debug.h> 56 57 /* local prototypes */ 58 static int ahci_setup_interrupt(device_t dev); 59 static void ahci_intr(void *data); 60 static void ahci_intr_one(void *data); 61 static int ahci_suspend(device_t dev); 62 static int ahci_resume(device_t dev); 63 static int ahci_ch_suspend(device_t dev); 64 static int ahci_ch_resume(device_t dev); 65 static void ahci_ch_pm(void *arg); 66 static void ahci_ch_intr_locked(void *data); 67 static void ahci_ch_intr(void *data); 68 static int ahci_ctlr_reset(device_t dev); 69 static int ahci_ctlr_setup(device_t dev); 70 static void ahci_begin_transaction(device_t dev, union ccb *ccb); 71 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 72 static void ahci_execute_transaction(struct ahci_slot *slot); 73 static void ahci_timeout(struct ahci_slot *slot); 74 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 75 static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 76 static void ahci_dmainit(device_t dev); 77 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 78 static void ahci_dmafini(device_t dev); 79 static void ahci_slotsalloc(device_t dev); 80 static void ahci_slotsfree(device_t dev); 81 static void ahci_reset(device_t dev); 82 static void ahci_start(device_t dev, int fbs); 83 static void ahci_stop(device_t dev); 84 static void ahci_clo(device_t dev); 85 static void ahci_start_fr(device_t dev); 86 static void ahci_stop_fr(device_t dev); 87 88 static int ahci_sata_connect(struct ahci_channel *ch); 89 static int ahci_sata_phy_reset(device_t dev); 90 static int ahci_wait_ready(device_t dev, int t); 91 92 static void ahci_issue_read_log(device_t dev); 93 static void ahci_process_read_log(device_t dev, union ccb *ccb); 94 95 static void ahciaction(struct cam_sim *sim, union ccb *ccb); 96 static void ahcipoll(struct cam_sim *sim); 97 98 MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 99 100 static struct { 101 uint32_t id; 102 uint8_t rev; 103 const char *name; 104 int quirks; 105 #define AHCI_Q_NOFORCE 1 106 #define AHCI_Q_NOPMP 2 107 #define AHCI_Q_NONCQ 4 108 #define AHCI_Q_1CH 8 109 #define AHCI_Q_2CH 16 110 #define AHCI_Q_4CH 32 111 #define AHCI_Q_EDGEIS 64 112 #define AHCI_Q_SATA2 128 113 #define AHCI_Q_NOBSYRES 256 114 } ahci_ids[] = { 115 {0x43801002, 0x00, "ATI IXP600", 0}, 116 {0x43901002, 0x00, "ATI IXP700", 0}, 117 {0x43911002, 0x00, "ATI IXP700", 0}, 118 {0x43921002, 0x00, "ATI IXP700", 0}, 119 {0x43931002, 0x00, "ATI IXP700", 0}, 120 {0x43941002, 0x00, "ATI IXP800", 0}, 121 {0x43951002, 0x00, "ATI IXP800", 0}, 122 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE}, 123 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE}, 124 {0x26818086, 0x00, "Intel ESB2", 0}, 125 {0x26828086, 0x00, "Intel ESB2", 0}, 126 {0x26838086, 0x00, "Intel ESB2", 0}, 127 {0x27c18086, 0x00, "Intel ICH7", 0}, 128 {0x27c38086, 0x00, "Intel ICH7", 0}, 129 {0x27c58086, 0x00, "Intel ICH7M", 0}, 130 {0x27c68086, 0x00, "Intel ICH7M", 0}, 131 {0x28218086, 0x00, "Intel ICH8", 0}, 132 {0x28228086, 0x00, "Intel ICH8", 0}, 133 {0x28248086, 0x00, "Intel ICH8", 0}, 134 {0x28298086, 0x00, "Intel ICH8M", 0}, 135 {0x282a8086, 0x00, "Intel ICH8M", 0}, 136 {0x29228086, 0x00, "Intel ICH9", 0}, 137 {0x29238086, 0x00, "Intel ICH9", 0}, 138 {0x29248086, 0x00, "Intel ICH9", 0}, 139 {0x29258086, 0x00, "Intel ICH9", 0}, 140 {0x29278086, 0x00, "Intel ICH9", 0}, 141 {0x29298086, 0x00, "Intel ICH9M", 0}, 142 {0x292a8086, 0x00, "Intel ICH9M", 0}, 143 {0x292b8086, 0x00, "Intel ICH9M", 0}, 144 {0x292c8086, 0x00, "Intel ICH9M", 0}, 145 {0x292f8086, 0x00, "Intel ICH9M", 0}, 146 {0x294d8086, 0x00, "Intel ICH9", 0}, 147 {0x294e8086, 0x00, "Intel ICH9M", 0}, 148 {0x3a058086, 0x00, "Intel ICH10", 0}, 149 {0x3a228086, 0x00, "Intel ICH10", 0}, 150 {0x3a258086, 0x00, "Intel ICH10", 0}, 151 {0x3b228086, 0x00, "Intel PCH", 0}, 152 {0x3b238086, 0x00, "Intel PCH", 0}, 153 {0x3b248086, 0x00, "Intel PCH", 0}, 154 {0x3b258086, 0x00, "Intel PCH", 0}, 155 {0x3b298086, 0x00, "Intel PCH", 0}, 156 {0x3b2b8086, 0x00, "Intel PCH", 0}, 157 {0x3b2c8086, 0x00, "Intel PCH", 0}, 158 {0x3b2f8086, 0x00, "Intel PCH", 0}, 159 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE}, 160 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE}, 161 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE}, 162 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE}, 163 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE}, 164 {0x611111ab, 0x00, "Marvell 88SX6111", AHCI_Q_NOFORCE|AHCI_Q_1CH|AHCI_Q_EDGEIS}, 165 {0x612111ab, 0x00, "Marvell 88SX6121", AHCI_Q_NOFORCE|AHCI_Q_2CH|AHCI_Q_EDGEIS}, 166 {0x614111ab, 0x00, "Marvell 88SX6141", AHCI_Q_NOFORCE|AHCI_Q_4CH|AHCI_Q_EDGEIS}, 167 {0x614511ab, 0x00, "Marvell 88SX6145", AHCI_Q_NOFORCE|AHCI_Q_4CH|AHCI_Q_EDGEIS}, 168 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES}, 169 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES}, 170 {0x044c10de, 0x00, "NVIDIA MCP65", 0}, 171 {0x044d10de, 0x00, "NVIDIA MCP65", 0}, 172 {0x044e10de, 0x00, "NVIDIA MCP65", 0}, 173 {0x044f10de, 0x00, "NVIDIA MCP65", 0}, 174 {0x045c10de, 0x00, "NVIDIA MCP65", 0}, 175 {0x045d10de, 0x00, "NVIDIA MCP65", 0}, 176 {0x045e10de, 0x00, "NVIDIA MCP65", 0}, 177 {0x045f10de, 0x00, "NVIDIA MCP65", 0}, 178 {0x055010de, 0x00, "NVIDIA MCP67", 0}, 179 {0x055110de, 0x00, "NVIDIA MCP67", 0}, 180 {0x055210de, 0x00, "NVIDIA MCP67", 0}, 181 {0x055310de, 0x00, "NVIDIA MCP67", 0}, 182 {0x055410de, 0x00, "NVIDIA MCP67", 0}, 183 {0x055510de, 0x00, "NVIDIA MCP67", 0}, 184 {0x055610de, 0x00, "NVIDIA MCP67", 0}, 185 {0x055710de, 0x00, "NVIDIA MCP67", 0}, 186 {0x055810de, 0x00, "NVIDIA MCP67", 0}, 187 {0x055910de, 0x00, "NVIDIA MCP67", 0}, 188 {0x055A10de, 0x00, "NVIDIA MCP67", 0}, 189 {0x055B10de, 0x00, "NVIDIA MCP67", 0}, 190 {0x058410de, 0x00, "NVIDIA MCP67", 0}, 191 {0x07f010de, 0x00, "NVIDIA MCP73", 0}, 192 {0x07f110de, 0x00, "NVIDIA MCP73", 0}, 193 {0x07f210de, 0x00, "NVIDIA MCP73", 0}, 194 {0x07f310de, 0x00, "NVIDIA MCP73", 0}, 195 {0x07f410de, 0x00, "NVIDIA MCP73", 0}, 196 {0x07f510de, 0x00, "NVIDIA MCP73", 0}, 197 {0x07f610de, 0x00, "NVIDIA MCP73", 0}, 198 {0x07f710de, 0x00, "NVIDIA MCP73", 0}, 199 {0x07f810de, 0x00, "NVIDIA MCP73", 0}, 200 {0x07f910de, 0x00, "NVIDIA MCP73", 0}, 201 {0x07fa10de, 0x00, "NVIDIA MCP73", 0}, 202 {0x07fb10de, 0x00, "NVIDIA MCP73", 0}, 203 {0x0ad010de, 0x00, "NVIDIA MCP77", 0}, 204 {0x0ad110de, 0x00, "NVIDIA MCP77", 0}, 205 {0x0ad210de, 0x00, "NVIDIA MCP77", 0}, 206 {0x0ad310de, 0x00, "NVIDIA MCP77", 0}, 207 {0x0ad410de, 0x00, "NVIDIA MCP77", 0}, 208 {0x0ad510de, 0x00, "NVIDIA MCP77", 0}, 209 {0x0ad610de, 0x00, "NVIDIA MCP77", 0}, 210 {0x0ad710de, 0x00, "NVIDIA MCP77", 0}, 211 {0x0ad810de, 0x00, "NVIDIA MCP77", 0}, 212 {0x0ad910de, 0x00, "NVIDIA MCP77", 0}, 213 {0x0ada10de, 0x00, "NVIDIA MCP77", 0}, 214 {0x0adb10de, 0x00, "NVIDIA MCP77", 0}, 215 {0x0ab410de, 0x00, "NVIDIA MCP79", 0}, 216 {0x0ab510de, 0x00, "NVIDIA MCP79", 0}, 217 {0x0ab610de, 0x00, "NVIDIA MCP79", 0}, 218 {0x0ab710de, 0x00, "NVIDIA MCP79", 0}, 219 {0x0ab810de, 0x00, "NVIDIA MCP79", 0}, 220 {0x0ab910de, 0x00, "NVIDIA MCP79", 0}, 221 {0x0aba10de, 0x00, "NVIDIA MCP79", 0}, 222 {0x0abb10de, 0x00, "NVIDIA MCP79", 0}, 223 {0x0abc10de, 0x00, "NVIDIA MCP79", 0}, 224 {0x0abd10de, 0x00, "NVIDIA MCP79", 0}, 225 {0x0abe10de, 0x00, "NVIDIA MCP79", 0}, 226 {0x0abf10de, 0x00, "NVIDIA MCP79", 0}, 227 {0x0d8410de, 0x00, "NVIDIA MCP89", 0}, 228 {0x0d8510de, 0x00, "NVIDIA MCP89", 0}, 229 {0x0d8610de, 0x00, "NVIDIA MCP89", 0}, 230 {0x0d8710de, 0x00, "NVIDIA MCP89", 0}, 231 {0x0d8810de, 0x00, "NVIDIA MCP89", 0}, 232 {0x0d8910de, 0x00, "NVIDIA MCP89", 0}, 233 {0x0d8a10de, 0x00, "NVIDIA MCP89", 0}, 234 {0x0d8b10de, 0x00, "NVIDIA MCP89", 0}, 235 {0x0d8c10de, 0x00, "NVIDIA MCP89", 0}, 236 {0x0d8d10de, 0x00, "NVIDIA MCP89", 0}, 237 {0x0d8e10de, 0x00, "NVIDIA MCP89", 0}, 238 {0x0d8f10de, 0x00, "NVIDIA MCP89", 0}, 239 {0x33491106, 0x00, "VIA VT8251", 0}, 240 {0x62871106, 0x00, "VIA VT8251", 0}, 241 {0x11841039, 0x00, "SiS 966", 0}, 242 {0x11851039, 0x00, "SiS 968", 0}, 243 {0x01861039, 0x00, "SiS 968", 0}, 244 {0x00000000, 0x00, NULL, 0} 245 }; 246 247 static int 248 ahci_probe(device_t dev) 249 { 250 char buf[64]; 251 int i, valid = 0; 252 uint32_t devid = pci_get_devid(dev); 253 uint8_t revid = pci_get_revid(dev); 254 255 /* Is this a possible AHCI candidate? */ 256 if (pci_get_class(dev) == PCIC_STORAGE && 257 pci_get_subclass(dev) == PCIS_STORAGE_SATA && 258 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0) 259 valid = 1; 260 /* Is this a known AHCI chip? */ 261 for (i = 0; ahci_ids[i].id != 0; i++) { 262 if (ahci_ids[i].id == devid && 263 ahci_ids[i].rev <= revid && 264 (valid || !(ahci_ids[i].quirks & AHCI_Q_NOFORCE))) { 265 /* Do not attach JMicrons with single PCI function. */ 266 if (pci_get_vendor(dev) == 0x197b && 267 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0) 268 return (ENXIO); 269 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 270 ahci_ids[i].name); 271 device_set_desc_copy(dev, buf); 272 return (BUS_PROBE_VENDOR); 273 } 274 } 275 if (!valid) 276 return (ENXIO); 277 device_set_desc_copy(dev, "AHCI SATA controller"); 278 return (BUS_PROBE_VENDOR); 279 } 280 281 static int 282 ahci_ata_probe(device_t dev) 283 { 284 char buf[64]; 285 int i; 286 uint32_t devid = pci_get_devid(dev); 287 uint8_t revid = pci_get_revid(dev); 288 289 if ((intptr_t)device_get_ivars(dev) >= 0) 290 return (ENXIO); 291 /* Is this a known AHCI chip? */ 292 for (i = 0; ahci_ids[i].id != 0; i++) { 293 if (ahci_ids[i].id == devid && 294 ahci_ids[i].rev <= revid) { 295 snprintf(buf, sizeof(buf), "%s AHCI SATA controller", 296 ahci_ids[i].name); 297 device_set_desc_copy(dev, buf); 298 return (BUS_PROBE_VENDOR); 299 } 300 } 301 device_set_desc_copy(dev, "AHCI SATA controller"); 302 return (BUS_PROBE_VENDOR); 303 } 304 305 static int 306 ahci_attach(device_t dev) 307 { 308 struct ahci_controller *ctlr = device_get_softc(dev); 309 device_t child; 310 int error, unit, speed, i; 311 uint32_t devid = pci_get_devid(dev); 312 uint8_t revid = pci_get_revid(dev); 313 u_int32_t version; 314 315 ctlr->dev = dev; 316 i = 0; 317 while (ahci_ids[i].id != 0 && 318 (ahci_ids[i].id != devid || 319 ahci_ids[i].rev > revid)) 320 i++; 321 ctlr->quirks = ahci_ids[i].quirks; 322 resource_int_value(device_get_name(dev), 323 device_get_unit(dev), "ccc", &ctlr->ccc); 324 /* if we have a memory BAR(5) we are likely on an AHCI part */ 325 ctlr->r_rid = PCIR_BAR(5); 326 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 327 &ctlr->r_rid, RF_ACTIVE))) 328 return ENXIO; 329 /* Setup our own memory management for channels. */ 330 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 331 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 332 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 333 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 334 return (error); 335 } 336 if ((error = rman_manage_region(&ctlr->sc_iomem, 337 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 338 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 339 rman_fini(&ctlr->sc_iomem); 340 return (error); 341 } 342 /* Reset controller */ 343 if ((error = ahci_ctlr_reset(dev)) != 0) { 344 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 345 rman_fini(&ctlr->sc_iomem); 346 return (error); 347 }; 348 /* Get the HW capabilities */ 349 version = ATA_INL(ctlr->r_mem, AHCI_VS); 350 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 351 if (version >= 0x00010020) 352 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 353 if (ctlr->caps & AHCI_CAP_EMS) 354 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 355 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 356 if (ctlr->quirks & AHCI_Q_1CH) { 357 ctlr->caps &= ~AHCI_CAP_NPMASK; 358 ctlr->ichannels &= 0x01; 359 } 360 if (ctlr->quirks & AHCI_Q_2CH) { 361 ctlr->caps &= ~AHCI_CAP_NPMASK; 362 ctlr->caps |= 1; 363 ctlr->ichannels &= 0x03; 364 } 365 if (ctlr->quirks & AHCI_Q_4CH) { 366 ctlr->caps &= ~AHCI_CAP_NPMASK; 367 ctlr->caps |= 3; 368 ctlr->ichannels &= 0x0f; 369 } 370 ctlr->channels = MAX(flsl(ctlr->ichannels), 371 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 372 if (ctlr->quirks & AHCI_Q_NOPMP) 373 ctlr->caps &= ~AHCI_CAP_SPM; 374 if (ctlr->quirks & AHCI_Q_NONCQ) 375 ctlr->caps &= ~AHCI_CAP_SNCQ; 376 if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 377 ctlr->ccc = 0; 378 ahci_ctlr_setup(dev); 379 /* Setup interrupts. */ 380 if (ahci_setup_interrupt(dev)) { 381 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 382 rman_fini(&ctlr->sc_iomem); 383 return ENXIO; 384 } 385 /* Announce HW capabilities. */ 386 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 387 device_printf(dev, 388 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 389 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 390 ((version >> 4) & 0xf0) + (version & 0x0f), 391 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 392 ((speed == 1) ? "1.5":((speed == 2) ? "3": 393 ((speed == 3) ? "6":"?"))), 394 (ctlr->caps & AHCI_CAP_SPM) ? 395 "supported" : "not supported", 396 (ctlr->caps & AHCI_CAP_FBSS) ? 397 " with FBS" : ""); 398 if (bootverbose) { 399 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 400 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 401 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 402 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 403 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 404 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 405 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 406 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 407 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 408 ((speed == 1) ? "1.5":((speed == 2) ? "3": 409 ((speed == 3) ? "6":"?")))); 410 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 411 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 412 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 413 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 414 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 415 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 416 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 417 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 418 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 419 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 420 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 421 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 422 } 423 if (bootverbose && version >= 0x00010020) { 424 device_printf(dev, "Caps2:%s%s%s\n", 425 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 426 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 427 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 428 } 429 if (bootverbose && (ctlr->caps & AHCI_CAP_EMS)) { 430 device_printf(dev, "EM Caps:%s%s%s%s%s%s%s%s\n", 431 (ctlr->capsem & AHCI_EM_PM) ? " PM":"", 432 (ctlr->capsem & AHCI_EM_ALHD) ? " ALHD":"", 433 (ctlr->capsem & AHCI_EM_XMT) ? " XMT":"", 434 (ctlr->capsem & AHCI_EM_SMB) ? " SMB":"", 435 (ctlr->capsem & AHCI_EM_SGPIO) ? " SGPIO":"", 436 (ctlr->capsem & AHCI_EM_SES2) ? " SES-2":"", 437 (ctlr->capsem & AHCI_EM_SAFTE) ? " SAF-TE":"", 438 (ctlr->capsem & AHCI_EM_LED) ? " LED":""); 439 } 440 /* Attach all channels on this controller */ 441 for (unit = 0; unit < ctlr->channels; unit++) { 442 if ((ctlr->ichannels & (1 << unit)) == 0) 443 continue; 444 child = device_add_child(dev, "ahcich", -1); 445 if (child == NULL) 446 device_printf(dev, "failed to add channel device\n"); 447 else 448 device_set_ivars(child, (void *)(intptr_t)unit); 449 } 450 bus_generic_attach(dev); 451 return 0; 452 } 453 454 static int 455 ahci_detach(device_t dev) 456 { 457 struct ahci_controller *ctlr = device_get_softc(dev); 458 device_t *children; 459 int nchildren, i; 460 461 /* Detach & delete all children */ 462 if (!device_get_children(dev, &children, &nchildren)) { 463 for (i = 0; i < nchildren; i++) 464 device_delete_child(dev, children[i]); 465 free(children, M_TEMP); 466 } 467 /* Free interrupts. */ 468 for (i = 0; i < ctlr->numirqs; i++) { 469 if (ctlr->irqs[i].r_irq) { 470 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 471 ctlr->irqs[i].handle); 472 bus_release_resource(dev, SYS_RES_IRQ, 473 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 474 } 475 } 476 pci_release_msi(dev); 477 /* Free memory. */ 478 rman_fini(&ctlr->sc_iomem); 479 if (ctlr->r_mem) 480 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 481 return (0); 482 } 483 484 static int 485 ahci_ctlr_reset(device_t dev) 486 { 487 struct ahci_controller *ctlr = device_get_softc(dev); 488 int timeout; 489 490 if (pci_read_config(dev, 0x00, 4) == 0x28298086 && 491 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04) 492 pci_write_config(dev, 0x92, 0x01, 1); 493 /* Enable AHCI mode */ 494 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 495 /* Reset AHCI controller */ 496 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 497 for (timeout = 1000; timeout > 0; timeout--) { 498 DELAY(1000); 499 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 500 break; 501 } 502 if (timeout == 0) { 503 device_printf(dev, "AHCI controller reset failure\n"); 504 return ENXIO; 505 } 506 /* Reenable AHCI mode */ 507 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 508 return (0); 509 } 510 511 static int 512 ahci_ctlr_setup(device_t dev) 513 { 514 struct ahci_controller *ctlr = device_get_softc(dev); 515 /* Clear interrupts */ 516 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 517 /* Configure CCC */ 518 if (ctlr->ccc) { 519 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 520 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 521 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 522 (4 << AHCI_CCCC_CC_SHIFT) | 523 AHCI_CCCC_EN); 524 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 525 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 526 if (bootverbose) { 527 device_printf(dev, 528 "CCC with %dms/4cmd enabled on vector %d\n", 529 ctlr->ccc, ctlr->cccv); 530 } 531 } 532 /* Enable AHCI interrupts */ 533 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 534 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 535 return (0); 536 } 537 538 static int 539 ahci_suspend(device_t dev) 540 { 541 struct ahci_controller *ctlr = device_get_softc(dev); 542 543 bus_generic_suspend(dev); 544 /* Disable interupts, so the state change(s) doesn't trigger */ 545 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 546 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 547 return 0; 548 } 549 550 static int 551 ahci_resume(device_t dev) 552 { 553 int res; 554 555 if ((res = ahci_ctlr_reset(dev)) != 0) 556 return (res); 557 ahci_ctlr_setup(dev); 558 return (bus_generic_resume(dev)); 559 } 560 561 static int 562 ahci_setup_interrupt(device_t dev) 563 { 564 struct ahci_controller *ctlr = device_get_softc(dev); 565 int i, msi = 1; 566 567 /* Process hints. */ 568 resource_int_value(device_get_name(dev), 569 device_get_unit(dev), "msi", &msi); 570 if (msi < 0) 571 msi = 0; 572 else if (msi == 1) 573 msi = min(1, pci_msi_count(dev)); 574 else if (msi > 1) 575 msi = pci_msi_count(dev); 576 /* Allocate MSI if needed/present. */ 577 if (msi && pci_alloc_msi(dev, &msi) == 0) { 578 ctlr->numirqs = msi; 579 } else { 580 msi = 0; 581 ctlr->numirqs = 1; 582 } 583 /* Check for single MSI vector fallback. */ 584 if (ctlr->numirqs > 1 && 585 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 586 device_printf(dev, "Falling back to one MSI\n"); 587 ctlr->numirqs = 1; 588 } 589 /* Allocate all IRQs. */ 590 for (i = 0; i < ctlr->numirqs; i++) { 591 ctlr->irqs[i].ctlr = ctlr; 592 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0); 593 if (ctlr->numirqs == 1 || i >= ctlr->channels || 594 (ctlr->ccc && i == ctlr->cccv)) 595 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 596 else if (i == ctlr->numirqs - 1) 597 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 598 else 599 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 600 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 601 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 602 device_printf(dev, "unable to map interrupt\n"); 603 return ENXIO; 604 } 605 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 606 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr, 607 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 608 /* SOS XXX release r_irq */ 609 device_printf(dev, "unable to setup interrupt\n"); 610 return ENXIO; 611 } 612 if (ctlr->numirqs > 1) { 613 bus_describe_intr(dev, ctlr->irqs[i].r_irq, 614 ctlr->irqs[i].handle, 615 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 616 "ch%d" : "%d", i); 617 } 618 } 619 return (0); 620 } 621 622 /* 623 * Common case interrupt handler. 624 */ 625 static void 626 ahci_intr(void *data) 627 { 628 struct ahci_controller_irq *irq = data; 629 struct ahci_controller *ctlr = irq->ctlr; 630 u_int32_t is, ise = 0; 631 void *arg; 632 int unit; 633 634 if (irq->mode == AHCI_IRQ_MODE_ALL) { 635 unit = 0; 636 if (ctlr->ccc) 637 is = ctlr->ichannels; 638 else 639 is = ATA_INL(ctlr->r_mem, AHCI_IS); 640 } else { /* AHCI_IRQ_MODE_AFTER */ 641 unit = irq->r_irq_rid - 1; 642 is = ATA_INL(ctlr->r_mem, AHCI_IS); 643 } 644 /* CCC interrupt is edge triggered. */ 645 if (ctlr->ccc) 646 ise = 1 << ctlr->cccv; 647 /* Some controllers have edge triggered IS. */ 648 if (ctlr->quirks & AHCI_Q_EDGEIS) 649 ise |= is; 650 if (ise != 0) 651 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 652 for (; unit < ctlr->channels; unit++) { 653 if ((is & (1 << unit)) != 0 && 654 (arg = ctlr->interrupt[unit].argument)) { 655 ctlr->interrupt[unit].function(arg); 656 } 657 } 658 /* AHCI declares level triggered IS. */ 659 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 660 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 661 } 662 663 /* 664 * Simplified interrupt handler for multivector MSI mode. 665 */ 666 static void 667 ahci_intr_one(void *data) 668 { 669 struct ahci_controller_irq *irq = data; 670 struct ahci_controller *ctlr = irq->ctlr; 671 void *arg; 672 int unit; 673 674 unit = irq->r_irq_rid - 1; 675 /* Some controllers have edge triggered IS. */ 676 if (ctlr->quirks & AHCI_Q_EDGEIS) 677 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 678 if ((arg = ctlr->interrupt[unit].argument)) 679 ctlr->interrupt[unit].function(arg); 680 /* AHCI declares level triggered IS. */ 681 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 682 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 683 } 684 685 static struct resource * 686 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 687 u_long start, u_long end, u_long count, u_int flags) 688 { 689 struct ahci_controller *ctlr = device_get_softc(dev); 690 int unit = ((struct ahci_channel *)device_get_softc(child))->unit; 691 struct resource *res = NULL; 692 int offset = AHCI_OFFSET + (unit << 7); 693 long st; 694 695 switch (type) { 696 case SYS_RES_MEMORY: 697 st = rman_get_start(ctlr->r_mem); 698 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 699 st + offset + 127, 128, RF_ACTIVE, child); 700 if (res) { 701 bus_space_handle_t bsh; 702 bus_space_tag_t bst; 703 bsh = rman_get_bushandle(ctlr->r_mem); 704 bst = rman_get_bustag(ctlr->r_mem); 705 bus_space_subregion(bst, bsh, offset, 128, &bsh); 706 rman_set_bushandle(res, bsh); 707 rman_set_bustag(res, bst); 708 } 709 break; 710 case SYS_RES_IRQ: 711 if (*rid == ATA_IRQ_RID) 712 res = ctlr->irqs[0].r_irq; 713 break; 714 } 715 return (res); 716 } 717 718 static int 719 ahci_release_resource(device_t dev, device_t child, int type, int rid, 720 struct resource *r) 721 { 722 723 switch (type) { 724 case SYS_RES_MEMORY: 725 rman_release_resource(r); 726 return (0); 727 case SYS_RES_IRQ: 728 if (rid != ATA_IRQ_RID) 729 return ENOENT; 730 return (0); 731 } 732 return (EINVAL); 733 } 734 735 static int 736 ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 737 int flags, driver_filter_t *filter, driver_intr_t *function, 738 void *argument, void **cookiep) 739 { 740 struct ahci_controller *ctlr = device_get_softc(dev); 741 int unit = (intptr_t)device_get_ivars(child); 742 743 if (filter != NULL) { 744 printf("ahci.c: we cannot use a filter here\n"); 745 return (EINVAL); 746 } 747 ctlr->interrupt[unit].function = function; 748 ctlr->interrupt[unit].argument = argument; 749 return (0); 750 } 751 752 static int 753 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 754 void *cookie) 755 { 756 struct ahci_controller *ctlr = device_get_softc(dev); 757 int unit = (intptr_t)device_get_ivars(child); 758 759 ctlr->interrupt[unit].function = NULL; 760 ctlr->interrupt[unit].argument = NULL; 761 return (0); 762 } 763 764 static int 765 ahci_print_child(device_t dev, device_t child) 766 { 767 int retval; 768 769 retval = bus_print_child_header(dev, child); 770 retval += printf(" at channel %d", 771 (int)(intptr_t)device_get_ivars(child)); 772 retval += bus_print_child_footer(dev, child); 773 774 return (retval); 775 } 776 777 devclass_t ahci_devclass; 778 static device_method_t ahci_methods[] = { 779 DEVMETHOD(device_probe, ahci_probe), 780 DEVMETHOD(device_attach, ahci_attach), 781 DEVMETHOD(device_detach, ahci_detach), 782 DEVMETHOD(device_suspend, ahci_suspend), 783 DEVMETHOD(device_resume, ahci_resume), 784 DEVMETHOD(bus_print_child, ahci_print_child), 785 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 786 DEVMETHOD(bus_release_resource, ahci_release_resource), 787 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 788 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 789 { 0, 0 } 790 }; 791 static driver_t ahci_driver = { 792 "ahci", 793 ahci_methods, 794 sizeof(struct ahci_controller) 795 }; 796 DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0); 797 static device_method_t ahci_ata_methods[] = { 798 DEVMETHOD(device_probe, ahci_ata_probe), 799 DEVMETHOD(device_attach, ahci_attach), 800 DEVMETHOD(device_detach, ahci_detach), 801 DEVMETHOD(device_suspend, ahci_suspend), 802 DEVMETHOD(device_resume, ahci_resume), 803 DEVMETHOD(bus_print_child, ahci_print_child), 804 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 805 DEVMETHOD(bus_release_resource, ahci_release_resource), 806 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 807 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr), 808 { 0, 0 } 809 }; 810 static driver_t ahci_ata_driver = { 811 "ahci", 812 ahci_ata_methods, 813 sizeof(struct ahci_controller) 814 }; 815 DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0); 816 MODULE_VERSION(ahci, 1); 817 MODULE_DEPEND(ahci, cam, 1, 1, 1); 818 819 static int 820 ahci_ch_probe(device_t dev) 821 { 822 823 device_set_desc_copy(dev, "AHCI channel"); 824 return (0); 825 } 826 827 static int 828 ahci_ch_attach(device_t dev) 829 { 830 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 831 struct ahci_channel *ch = device_get_softc(dev); 832 struct cam_devq *devq; 833 int rid, error, i, sata_rev = 0; 834 u_int32_t version; 835 836 ch->dev = dev; 837 ch->unit = (intptr_t)device_get_ivars(dev); 838 ch->caps = ctlr->caps; 839 ch->caps2 = ctlr->caps2; 840 ch->quirks = ctlr->quirks; 841 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 842 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 843 resource_int_value(device_get_name(dev), 844 device_get_unit(dev), "pm_level", &ch->pm_level); 845 if (ch->pm_level > 3) 846 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 847 /* Limit speed for my onboard JMicron external port. 848 * It is not eSATA really. */ 849 if (pci_get_devid(ctlr->dev) == 0x2363197b && 850 pci_get_subvendor(ctlr->dev) == 0x1043 && 851 pci_get_subdevice(ctlr->dev) == 0x81e4 && 852 ch->unit == 0) 853 sata_rev = 1; 854 if (ch->quirks & AHCI_Q_SATA2) 855 sata_rev = 2; 856 resource_int_value(device_get_name(dev), 857 device_get_unit(dev), "sata_rev", &sata_rev); 858 for (i = 0; i < 16; i++) { 859 ch->user[i].revision = sata_rev; 860 ch->user[i].mode = 0; 861 ch->user[i].bytecount = 8192; 862 ch->user[i].tags = ch->numslots; 863 ch->curr[i] = ch->user[i]; 864 } 865 rid = ch->unit; 866 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 867 &rid, RF_ACTIVE))) 868 return (ENXIO); 869 ahci_dmainit(dev); 870 ahci_slotsalloc(dev); 871 ahci_ch_resume(dev); 872 mtx_lock(&ch->mtx); 873 rid = ATA_IRQ_RID; 874 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 875 &rid, RF_SHAREABLE | RF_ACTIVE))) { 876 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 877 device_printf(dev, "Unable to map interrupt\n"); 878 return (ENXIO); 879 } 880 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 881 ahci_ch_intr_locked, dev, &ch->ih))) { 882 device_printf(dev, "Unable to setup interrupt\n"); 883 error = ENXIO; 884 goto err1; 885 } 886 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 887 version = ATA_INL(ctlr->r_mem, AHCI_VS); 888 if (version < 0x00010020 && (ctlr->caps & AHCI_CAP_FBSS)) 889 ch->chcaps |= AHCI_P_CMD_FBSCP; 890 if (bootverbose) { 891 device_printf(dev, "Caps:%s%s%s%s%s\n", 892 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 893 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 894 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 895 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 896 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":""); 897 } 898 /* Create the device queue for our SIM. */ 899 devq = cam_simq_alloc(ch->numslots); 900 if (devq == NULL) { 901 device_printf(dev, "Unable to allocate simq\n"); 902 error = ENOMEM; 903 goto err1; 904 } 905 /* Construct SIM entry */ 906 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 907 device_get_unit(dev), &ch->mtx, 908 min(2, ch->numslots), 909 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 910 devq); 911 if (ch->sim == NULL) { 912 device_printf(dev, "unable to allocate sim\n"); 913 error = ENOMEM; 914 goto err2; 915 } 916 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 917 device_printf(dev, "unable to register xpt bus\n"); 918 error = ENXIO; 919 goto err2; 920 } 921 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 922 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 923 device_printf(dev, "unable to create path\n"); 924 error = ENXIO; 925 goto err3; 926 } 927 if (ch->pm_level > 3) { 928 callout_reset(&ch->pm_timer, 929 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 930 ahci_ch_pm, dev); 931 } 932 mtx_unlock(&ch->mtx); 933 return (0); 934 935 err3: 936 xpt_bus_deregister(cam_sim_path(ch->sim)); 937 err2: 938 cam_sim_free(ch->sim, /*free_devq*/TRUE); 939 err1: 940 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 941 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 942 mtx_unlock(&ch->mtx); 943 return (error); 944 } 945 946 static int 947 ahci_ch_detach(device_t dev) 948 { 949 struct ahci_channel *ch = device_get_softc(dev); 950 951 mtx_lock(&ch->mtx); 952 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 953 xpt_free_path(ch->path); 954 xpt_bus_deregister(cam_sim_path(ch->sim)); 955 cam_sim_free(ch->sim, /*free_devq*/TRUE); 956 mtx_unlock(&ch->mtx); 957 958 if (ch->pm_level > 3) 959 callout_drain(&ch->pm_timer); 960 bus_teardown_intr(dev, ch->r_irq, ch->ih); 961 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 962 963 ahci_ch_suspend(dev); 964 ahci_slotsfree(dev); 965 ahci_dmafini(dev); 966 967 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 968 mtx_destroy(&ch->mtx); 969 return (0); 970 } 971 972 static int 973 ahci_ch_suspend(device_t dev) 974 { 975 struct ahci_channel *ch = device_get_softc(dev); 976 977 /* Disable port interrupts. */ 978 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 979 /* Reset command register. */ 980 ahci_stop(dev); 981 ahci_stop_fr(dev); 982 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 983 /* Allow everything, including partial and slumber modes. */ 984 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 985 /* Request slumber mode transition and give some time to get there. */ 986 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 987 DELAY(100); 988 /* Disable PHY. */ 989 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 990 return (0); 991 } 992 993 static int 994 ahci_ch_resume(device_t dev) 995 { 996 struct ahci_channel *ch = device_get_softc(dev); 997 uint64_t work; 998 999 /* Disable port interrupts */ 1000 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1001 /* Setup work areas */ 1002 work = ch->dma.work_bus + AHCI_CL_OFFSET; 1003 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 1004 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 1005 work = ch->dma.rfis_bus; 1006 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 1007 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 1008 /* Activate the channel and power/spin up device */ 1009 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 1010 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1011 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 1012 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 1013 ahci_start_fr(dev); 1014 ahci_start(dev, 1); 1015 return (0); 1016 } 1017 1018 devclass_t ahcich_devclass; 1019 static device_method_t ahcich_methods[] = { 1020 DEVMETHOD(device_probe, ahci_ch_probe), 1021 DEVMETHOD(device_attach, ahci_ch_attach), 1022 DEVMETHOD(device_detach, ahci_ch_detach), 1023 DEVMETHOD(device_suspend, ahci_ch_suspend), 1024 DEVMETHOD(device_resume, ahci_ch_resume), 1025 { 0, 0 } 1026 }; 1027 static driver_t ahcich_driver = { 1028 "ahcich", 1029 ahcich_methods, 1030 sizeof(struct ahci_channel) 1031 }; 1032 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0); 1033 1034 struct ahci_dc_cb_args { 1035 bus_addr_t maddr; 1036 int error; 1037 }; 1038 1039 static void 1040 ahci_dmainit(device_t dev) 1041 { 1042 struct ahci_channel *ch = device_get_softc(dev); 1043 struct ahci_dc_cb_args dcba; 1044 size_t rfsize; 1045 1046 if (ch->caps & AHCI_CAP_64BIT) 1047 ch->dma.max_address = BUS_SPACE_MAXADDR; 1048 else 1049 ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT; 1050 /* Command area. */ 1051 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 1052 ch->dma.max_address, BUS_SPACE_MAXADDR, 1053 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 1054 0, NULL, NULL, &ch->dma.work_tag)) 1055 goto error; 1056 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0, 1057 &ch->dma.work_map)) 1058 goto error; 1059 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 1060 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1061 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1062 goto error; 1063 } 1064 ch->dma.work_bus = dcba.maddr; 1065 /* FIS receive area. */ 1066 if (ch->chcaps & AHCI_P_CMD_FBSCP) 1067 rfsize = 4096; 1068 else 1069 rfsize = 256; 1070 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 1071 ch->dma.max_address, BUS_SPACE_MAXADDR, 1072 NULL, NULL, rfsize, 1, rfsize, 1073 0, NULL, NULL, &ch->dma.rfis_tag)) 1074 goto error; 1075 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 1076 &ch->dma.rfis_map)) 1077 goto error; 1078 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 1079 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 1080 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1081 goto error; 1082 } 1083 ch->dma.rfis_bus = dcba.maddr; 1084 /* Data area. */ 1085 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 1086 ch->dma.max_address, BUS_SPACE_MAXADDR, 1087 NULL, NULL, 1088 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 1089 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 1090 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 1091 goto error; 1092 } 1093 return; 1094 1095 error: 1096 device_printf(dev, "WARNING - DMA initialization failed\n"); 1097 ahci_dmafini(dev); 1098 } 1099 1100 static void 1101 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1102 { 1103 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 1104 1105 if (!(dcba->error = error)) 1106 dcba->maddr = segs[0].ds_addr; 1107 } 1108 1109 static void 1110 ahci_dmafini(device_t dev) 1111 { 1112 struct ahci_channel *ch = device_get_softc(dev); 1113 1114 if (ch->dma.data_tag) { 1115 bus_dma_tag_destroy(ch->dma.data_tag); 1116 ch->dma.data_tag = NULL; 1117 } 1118 if (ch->dma.rfis_bus) { 1119 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1120 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1121 ch->dma.rfis_bus = 0; 1122 ch->dma.rfis_map = NULL; 1123 ch->dma.rfis = NULL; 1124 } 1125 if (ch->dma.work_bus) { 1126 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1127 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1128 ch->dma.work_bus = 0; 1129 ch->dma.work_map = NULL; 1130 ch->dma.work = NULL; 1131 } 1132 if (ch->dma.work_tag) { 1133 bus_dma_tag_destroy(ch->dma.work_tag); 1134 ch->dma.work_tag = NULL; 1135 } 1136 } 1137 1138 static void 1139 ahci_slotsalloc(device_t dev) 1140 { 1141 struct ahci_channel *ch = device_get_softc(dev); 1142 int i; 1143 1144 /* Alloc and setup command/dma slots */ 1145 bzero(ch->slot, sizeof(ch->slot)); 1146 for (i = 0; i < ch->numslots; i++) { 1147 struct ahci_slot *slot = &ch->slot[i]; 1148 1149 slot->dev = dev; 1150 slot->slot = i; 1151 slot->state = AHCI_SLOT_EMPTY; 1152 slot->ccb = NULL; 1153 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1154 1155 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1156 device_printf(ch->dev, "FAILURE - create data_map\n"); 1157 } 1158 } 1159 1160 static void 1161 ahci_slotsfree(device_t dev) 1162 { 1163 struct ahci_channel *ch = device_get_softc(dev); 1164 int i; 1165 1166 /* Free all dma slots */ 1167 for (i = 0; i < ch->numslots; i++) { 1168 struct ahci_slot *slot = &ch->slot[i]; 1169 1170 callout_drain(&slot->timeout); 1171 if (slot->dma.data_map) { 1172 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1173 slot->dma.data_map = NULL; 1174 } 1175 } 1176 } 1177 1178 static void 1179 ahci_phy_check_events(device_t dev, u_int32_t serr) 1180 { 1181 struct ahci_channel *ch = device_get_softc(dev); 1182 1183 if ((serr & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) { 1184 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1185 union ccb *ccb; 1186 1187 if (bootverbose) { 1188 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 1189 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 1190 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) { 1191 device_printf(dev, "CONNECT requested\n"); 1192 } else 1193 device_printf(dev, "DISCONNECT requested\n"); 1194 } 1195 ahci_reset(dev); 1196 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1197 return; 1198 if (xpt_create_path(&ccb->ccb_h.path, NULL, 1199 cam_sim_path(ch->sim), 1200 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1201 xpt_free_ccb(ccb); 1202 return; 1203 } 1204 xpt_rescan(ccb); 1205 } 1206 } 1207 1208 static void 1209 ahci_notify_events(device_t dev, u_int32_t status) 1210 { 1211 struct ahci_channel *ch = device_get_softc(dev); 1212 struct cam_path *dpath; 1213 int i; 1214 1215 if (ch->caps & AHCI_CAP_SSNTF) 1216 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1217 if (bootverbose) 1218 device_printf(dev, "SNTF 0x%04x\n", status); 1219 for (i = 0; i < 16; i++) { 1220 if ((status & (1 << i)) == 0) 1221 continue; 1222 if (xpt_create_path(&dpath, NULL, 1223 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1224 xpt_async(AC_SCSI_AEN, dpath, NULL); 1225 xpt_free_path(dpath); 1226 } 1227 } 1228 } 1229 1230 static void 1231 ahci_ch_intr_locked(void *data) 1232 { 1233 device_t dev = (device_t)data; 1234 struct ahci_channel *ch = device_get_softc(dev); 1235 1236 mtx_lock(&ch->mtx); 1237 ahci_ch_intr(data); 1238 mtx_unlock(&ch->mtx); 1239 } 1240 1241 static void 1242 ahci_ch_pm(void *arg) 1243 { 1244 device_t dev = (device_t)arg; 1245 struct ahci_channel *ch = device_get_softc(dev); 1246 uint32_t work; 1247 1248 if (ch->numrslots != 0) 1249 return; 1250 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1251 if (ch->pm_level == 4) 1252 work |= AHCI_P_CMD_PARTIAL; 1253 else 1254 work |= AHCI_P_CMD_SLUMBER; 1255 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1256 } 1257 1258 static void 1259 ahci_ch_intr(void *data) 1260 { 1261 device_t dev = (device_t)data; 1262 struct ahci_channel *ch = device_get_softc(dev); 1263 uint32_t istatus, sstatus, cstatus, serr = 0, sntf = 0, ok, err; 1264 enum ahci_err_type et; 1265 int i, ccs, port; 1266 1267 /* Read and clear interrupt statuses. */ 1268 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1269 if (istatus == 0) 1270 return; 1271 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1272 /* Read command statuses. */ 1273 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1274 cstatus = ATA_INL(ch->r_mem, AHCI_P_CI); 1275 if (istatus & AHCI_P_IX_SDB) { 1276 if (ch->caps & AHCI_CAP_SSNTF) 1277 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1278 else if (ch->fbs_enabled) { 1279 u_int8_t *fis = ch->dma.rfis + 0x58; 1280 1281 for (i = 0; i < 16; i++) { 1282 if (fis[1] & 0x80) { 1283 fis[1] &= 0x7f; 1284 sntf |= 1 << i; 1285 } 1286 fis += 256; 1287 } 1288 } else { 1289 u_int8_t *fis = ch->dma.rfis + 0x58; 1290 1291 if (fis[1] & 0x80) 1292 sntf = (1 << (fis[1] & 0x0f)); 1293 } 1294 } 1295 /* Process PHY events */ 1296 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1297 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1298 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1299 if (serr) { 1300 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1301 ahci_phy_check_events(dev, serr); 1302 } 1303 } 1304 /* Process command errors */ 1305 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1306 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1307 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1308 >> AHCI_P_CMD_CCS_SHIFT; 1309 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1310 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1311 // serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1312 port = -1; 1313 if (ch->fbs_enabled) { 1314 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1315 if (fbs & AHCI_P_FBS_SDE) { 1316 port = (fbs & AHCI_P_FBS_DWE) 1317 >> AHCI_P_FBS_DWE_SHIFT; 1318 } else { 1319 for (i = 0; i < 16; i++) { 1320 if (ch->numrslotspd[i] == 0) 1321 continue; 1322 if (port == -1) 1323 port = i; 1324 else if (port != i) { 1325 port = -2; 1326 break; 1327 } 1328 } 1329 } 1330 } 1331 err = ch->rslots & (cstatus | sstatus); 1332 } else { 1333 ccs = 0; 1334 err = 0; 1335 port = -1; 1336 } 1337 /* Complete all successfull commands. */ 1338 ok = ch->rslots & ~(cstatus | sstatus); 1339 for (i = 0; i < ch->numslots; i++) { 1340 if ((ok >> i) & 1) 1341 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1342 } 1343 /* On error, complete the rest of commands with error statuses. */ 1344 if (err) { 1345 if (ch->frozen) { 1346 union ccb *fccb = ch->frozen; 1347 ch->frozen = NULL; 1348 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1349 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1350 xpt_freeze_devq(fccb->ccb_h.path, 1); 1351 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1352 } 1353 xpt_done(fccb); 1354 } 1355 for (i = 0; i < ch->numslots; i++) { 1356 /* XXX: reqests in loading state. */ 1357 if (((err >> i) & 1) == 0) 1358 continue; 1359 if (port >= 0 && 1360 ch->slot[i].ccb->ccb_h.target_id != port) 1361 continue; 1362 if (istatus & AHCI_P_IX_TFE) { 1363 if (port != -2) { 1364 /* Task File Error */ 1365 if (ch->numtslotspd[ 1366 ch->slot[i].ccb->ccb_h.target_id] == 0) { 1367 /* Untagged operation. */ 1368 if (i == ccs) 1369 et = AHCI_ERR_TFE; 1370 else 1371 et = AHCI_ERR_INNOCENT; 1372 } else { 1373 /* Tagged operation. */ 1374 et = AHCI_ERR_NCQ; 1375 } 1376 } else { 1377 et = AHCI_ERR_TFE; 1378 ch->fatalerr = 1; 1379 } 1380 } else if (istatus & AHCI_P_IX_IF) { 1381 if (ch->numtslots == 0 && i != ccs && port != -2) 1382 et = AHCI_ERR_INNOCENT; 1383 else 1384 et = AHCI_ERR_SATA; 1385 } else 1386 et = AHCI_ERR_INVALID; 1387 ahci_end_transaction(&ch->slot[i], et); 1388 } 1389 /* 1390 * We can't reinit port if there are some other 1391 * commands active, use resume to complete them. 1392 */ 1393 if (ch->rslots != 0) 1394 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1395 } 1396 /* Process NOTIFY events */ 1397 if (sntf) 1398 ahci_notify_events(dev, sntf); 1399 } 1400 1401 /* Must be called with channel locked. */ 1402 static int 1403 ahci_check_collision(device_t dev, union ccb *ccb) 1404 { 1405 struct ahci_channel *ch = device_get_softc(dev); 1406 int t = ccb->ccb_h.target_id; 1407 1408 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1409 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1410 /* Tagged command while we have no supported tag free. */ 1411 if (((~ch->oslots) & (0xffffffff >> (32 - 1412 ch->curr[t].tags))) == 0) 1413 return (1); 1414 /* If we have FBS */ 1415 if (ch->fbs_enabled) { 1416 /* Tagged command while untagged are active. */ 1417 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1418 return (1); 1419 } else { 1420 /* Tagged command while untagged are active. */ 1421 if (ch->numrslots != 0 && ch->numtslots == 0) 1422 return (1); 1423 /* Tagged command while tagged to other target is active. */ 1424 if (ch->numtslots != 0 && 1425 ch->taggedtarget != ccb->ccb_h.target_id) 1426 return (1); 1427 } 1428 } else { 1429 /* If we have FBS */ 1430 if (ch->fbs_enabled) { 1431 /* Untagged command while tagged are active. */ 1432 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1433 return (1); 1434 } else { 1435 /* Untagged command while tagged are active. */ 1436 if (ch->numrslots != 0 && ch->numtslots != 0) 1437 return (1); 1438 } 1439 } 1440 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1441 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1442 /* Atomic command while anything active. */ 1443 if (ch->numrslots != 0) 1444 return (1); 1445 } 1446 /* We have some atomic command running. */ 1447 if (ch->aslots != 0) 1448 return (1); 1449 return (0); 1450 } 1451 1452 /* Must be called with channel locked. */ 1453 static void 1454 ahci_begin_transaction(device_t dev, union ccb *ccb) 1455 { 1456 struct ahci_channel *ch = device_get_softc(dev); 1457 struct ahci_slot *slot; 1458 int tag, tags; 1459 1460 /* Choose empty slot. */ 1461 tags = ch->numslots; 1462 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1463 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1464 tags = ch->curr[ccb->ccb_h.target_id].tags; 1465 tag = ch->lastslot; 1466 while (1) { 1467 if (tag >= tags) 1468 tag = 0; 1469 if (ch->slot[tag].state == AHCI_SLOT_EMPTY) 1470 break; 1471 tag++; 1472 }; 1473 ch->lastslot = tag; 1474 /* Occupy chosen slot. */ 1475 slot = &ch->slot[tag]; 1476 slot->ccb = ccb; 1477 /* Stop PM timer. */ 1478 if (ch->numrslots == 0 && ch->pm_level > 3) 1479 callout_stop(&ch->pm_timer); 1480 /* Update channel stats. */ 1481 ch->oslots |= (1 << slot->slot); 1482 ch->numrslots++; 1483 ch->numrslotspd[ccb->ccb_h.target_id]++; 1484 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1485 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1486 ch->numtslots++; 1487 ch->numtslotspd[ccb->ccb_h.target_id]++; 1488 ch->taggedtarget = ccb->ccb_h.target_id; 1489 } 1490 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1491 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1492 ch->aslots |= (1 << slot->slot); 1493 slot->dma.nsegs = 0; 1494 /* If request moves data, setup and load SG list */ 1495 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1496 void *buf; 1497 bus_size_t size; 1498 1499 slot->state = AHCI_SLOT_LOADING; 1500 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1501 buf = ccb->ataio.data_ptr; 1502 size = ccb->ataio.dxfer_len; 1503 } else { 1504 buf = ccb->csio.data_ptr; 1505 size = ccb->csio.dxfer_len; 1506 } 1507 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map, 1508 buf, size, ahci_dmasetprd, slot, 0); 1509 } else 1510 ahci_execute_transaction(slot); 1511 } 1512 1513 /* Locked by busdma engine. */ 1514 static void 1515 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1516 { 1517 struct ahci_slot *slot = arg; 1518 struct ahci_channel *ch = device_get_softc(slot->dev); 1519 struct ahci_cmd_tab *ctp; 1520 struct ahci_dma_prd *prd; 1521 int i; 1522 1523 if (error) { 1524 device_printf(slot->dev, "DMA load error\n"); 1525 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1526 return; 1527 } 1528 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1529 /* Get a piece of the workspace for this request */ 1530 ctp = (struct ahci_cmd_tab *) 1531 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1532 /* Fill S/G table */ 1533 prd = &ctp->prd_tab[0]; 1534 for (i = 0; i < nsegs; i++) { 1535 prd[i].dba = htole64(segs[i].ds_addr); 1536 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1537 } 1538 slot->dma.nsegs = nsegs; 1539 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1540 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1541 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1542 ahci_execute_transaction(slot); 1543 } 1544 1545 /* Must be called with channel locked. */ 1546 static void 1547 ahci_execute_transaction(struct ahci_slot *slot) 1548 { 1549 device_t dev = slot->dev; 1550 struct ahci_channel *ch = device_get_softc(dev); 1551 struct ahci_cmd_tab *ctp; 1552 struct ahci_cmd_list *clp; 1553 union ccb *ccb = slot->ccb; 1554 int port = ccb->ccb_h.target_id & 0x0f; 1555 int fis_size, i; 1556 uint8_t *fis = ch->dma.rfis + 0x40; 1557 uint8_t val; 1558 1559 /* Get a piece of the workspace for this request */ 1560 ctp = (struct ahci_cmd_tab *) 1561 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1562 /* Setup the FIS for this request */ 1563 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) { 1564 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1565 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1566 return; 1567 } 1568 /* Setup the command list entry */ 1569 clp = (struct ahci_cmd_list *) 1570 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1571 clp->prd_length = slot->dma.nsegs; 1572 clp->cmd_flags = (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1573 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1574 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1575 (fis_size / sizeof(u_int32_t)) | 1576 (port << 12); 1577 /* Special handling for Soft Reset command. */ 1578 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1579 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1580 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1581 /* Kick controller into sane state */ 1582 ahci_stop(dev); 1583 ahci_clo(dev); 1584 ahci_start(dev, 0); 1585 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1586 } else { 1587 /* Prepare FIS receive area for check. */ 1588 for (i = 0; i < 20; i++) 1589 fis[i] = 0xff; 1590 } 1591 } 1592 clp->bytecount = 0; 1593 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1594 (AHCI_CT_SIZE * slot->slot)); 1595 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1596 BUS_DMASYNC_PREWRITE); 1597 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1598 BUS_DMASYNC_PREREAD); 1599 /* Set ACTIVE bit for NCQ commands. */ 1600 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1601 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1602 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1603 } 1604 /* If FBS is enabled, set PMP port. */ 1605 if (ch->fbs_enabled) { 1606 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1607 (port << AHCI_P_FBS_DEV_SHIFT)); 1608 } 1609 /* Issue command to the controller. */ 1610 slot->state = AHCI_SLOT_RUNNING; 1611 ch->rslots |= (1 << slot->slot); 1612 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1613 /* Device reset commands doesn't interrupt. Poll them. */ 1614 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1615 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || 1616 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL))) { 1617 int count, timeout = ccb->ccb_h.timeout; 1618 enum ahci_err_type et = AHCI_ERR_NONE; 1619 1620 for (count = 0; count < timeout; count++) { 1621 DELAY(1000); 1622 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1623 break; 1624 if (ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) { 1625 device_printf(ch->dev, 1626 "Poll error on slot %d, TFD: %04x\n", 1627 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1628 et = AHCI_ERR_TFE; 1629 break; 1630 } 1631 /* Workaround for ATI SB600/SB700 chipsets. */ 1632 if (ccb->ccb_h.target_id == 15 && 1633 pci_get_vendor(device_get_parent(dev)) == 0x1002 && 1634 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1635 et = AHCI_ERR_TIMEOUT; 1636 break; 1637 } 1638 } 1639 if (timeout && (count >= timeout)) { 1640 device_printf(ch->dev, 1641 "Poll timeout on slot %d\n", slot->slot); 1642 device_printf(dev, "is %08x cs %08x ss %08x " 1643 "rs %08x tfd %02x serr %08x\n", 1644 ATA_INL(ch->r_mem, AHCI_P_IS), 1645 ATA_INL(ch->r_mem, AHCI_P_CI), 1646 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1647 ATA_INL(ch->r_mem, AHCI_P_TFD), 1648 ATA_INL(ch->r_mem, AHCI_P_SERR)); 1649 et = AHCI_ERR_TIMEOUT; 1650 } 1651 /* Marvell controllers do not wait for readyness. */ 1652 if ((ch->quirks & AHCI_Q_NOBSYRES) && 1653 (ccb->ccb_h.func_code == XPT_ATA_IO) && 1654 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1655 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 1656 while ((val = fis[2]) & (ATA_S_BUSY | ATA_S_DRQ)) { 1657 DELAY(1000); 1658 if (count++ >= timeout) { 1659 device_printf(dev, "device is not " 1660 "ready after soft-reset: " 1661 "tfd = %08x\n", val); 1662 et = AHCI_ERR_TIMEOUT; 1663 break; 1664 } 1665 } 1666 } 1667 ahci_end_transaction(slot, et); 1668 /* Kick controller into sane state and enable FBS. */ 1669 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1670 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1671 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 1672 ahci_stop(ch->dev); 1673 ahci_start(ch->dev, 1); 1674 } 1675 return; 1676 } 1677 /* Start command execution timeout */ 1678 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000, 1679 (timeout_t*)ahci_timeout, slot); 1680 return; 1681 } 1682 1683 /* Must be called with channel locked. */ 1684 static void 1685 ahci_process_timeout(device_t dev) 1686 { 1687 struct ahci_channel *ch = device_get_softc(dev); 1688 int i; 1689 1690 mtx_assert(&ch->mtx, MA_OWNED); 1691 /* Handle the rest of commands. */ 1692 for (i = 0; i < ch->numslots; i++) { 1693 /* Do we have a running request on slot? */ 1694 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1695 continue; 1696 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 1697 } 1698 } 1699 1700 /* Must be called with channel locked. */ 1701 static void 1702 ahci_rearm_timeout(device_t dev) 1703 { 1704 struct ahci_channel *ch = device_get_softc(dev); 1705 int i; 1706 1707 mtx_assert(&ch->mtx, MA_OWNED); 1708 for (i = 0; i < ch->numslots; i++) { 1709 struct ahci_slot *slot = &ch->slot[i]; 1710 1711 /* Do we have a running request on slot? */ 1712 if (slot->state < AHCI_SLOT_RUNNING) 1713 continue; 1714 if ((ch->toslots & (1 << i)) == 0) 1715 continue; 1716 callout_reset(&slot->timeout, 1717 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1718 (timeout_t*)ahci_timeout, slot); 1719 } 1720 } 1721 1722 /* Locked by callout mechanism. */ 1723 static void 1724 ahci_timeout(struct ahci_slot *slot) 1725 { 1726 device_t dev = slot->dev; 1727 struct ahci_channel *ch = device_get_softc(dev); 1728 uint32_t sstatus; 1729 int ccs; 1730 int i; 1731 1732 /* Check for stale timeout. */ 1733 if (slot->state < AHCI_SLOT_RUNNING) 1734 return; 1735 1736 /* Check if slot was not being executed last time we checked. */ 1737 if (slot->state < AHCI_SLOT_EXECUTING) { 1738 /* Check if slot started executing. */ 1739 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1740 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1741 >> AHCI_P_CMD_CCS_SHIFT; 1742 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 1743 ch->fbs_enabled) 1744 slot->state = AHCI_SLOT_EXECUTING; 1745 1746 callout_reset(&slot->timeout, 1747 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1748 (timeout_t*)ahci_timeout, slot); 1749 return; 1750 } 1751 1752 device_printf(dev, "Timeout on slot %d\n", slot->slot); 1753 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x\n", 1754 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 1755 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1756 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR)); 1757 1758 /* Handle frozen command. */ 1759 if (ch->frozen) { 1760 union ccb *fccb = ch->frozen; 1761 ch->frozen = NULL; 1762 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1763 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1764 xpt_freeze_devq(fccb->ccb_h.path, 1); 1765 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1766 } 1767 xpt_done(fccb); 1768 } 1769 if (!ch->fbs_enabled) { 1770 /* Without FBS we know real timeout source. */ 1771 ch->fatalerr = 1; 1772 /* Handle command with timeout. */ 1773 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 1774 /* Handle the rest of commands. */ 1775 for (i = 0; i < ch->numslots; i++) { 1776 /* Do we have a running request on slot? */ 1777 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1778 continue; 1779 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1780 } 1781 } else { 1782 /* With FBS we wait for other commands timeout and pray. */ 1783 if (ch->toslots == 0) 1784 xpt_freeze_simq(ch->sim, 1); 1785 ch->toslots |= (1 << slot->slot); 1786 if ((ch->rslots & ~ch->toslots) == 0) 1787 ahci_process_timeout(dev); 1788 else 1789 device_printf(dev, " ... waiting for slots %08x\n", 1790 ch->rslots & ~ch->toslots); 1791 } 1792 } 1793 1794 /* Must be called with channel locked. */ 1795 static void 1796 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 1797 { 1798 device_t dev = slot->dev; 1799 struct ahci_channel *ch = device_get_softc(dev); 1800 union ccb *ccb = slot->ccb; 1801 1802 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1803 BUS_DMASYNC_POSTWRITE); 1804 /* Read result registers to the result struct 1805 * May be incorrect if several commands finished same time, 1806 * so read only when sure or have to. 1807 */ 1808 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1809 struct ata_res *res = &ccb->ataio.res; 1810 1811 if ((et == AHCI_ERR_TFE) || 1812 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1813 u_int8_t *fis = ch->dma.rfis + 0x40; 1814 1815 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1816 BUS_DMASYNC_POSTREAD); 1817 if (ch->fbs_enabled) { 1818 fis += ccb->ccb_h.target_id * 256; 1819 res->status = fis[2]; 1820 res->error = fis[3]; 1821 } else { 1822 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 1823 1824 res->status = tfd; 1825 res->error = tfd >> 8; 1826 } 1827 res->lba_low = fis[4]; 1828 res->lba_mid = fis[5]; 1829 res->lba_high = fis[6]; 1830 res->device = fis[7]; 1831 res->lba_low_exp = fis[8]; 1832 res->lba_mid_exp = fis[9]; 1833 res->lba_high_exp = fis[10]; 1834 res->sector_count = fis[12]; 1835 res->sector_count_exp = fis[13]; 1836 } else 1837 bzero(res, sizeof(*res)); 1838 } 1839 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1840 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1841 (ccb->ccb_h.flags & CAM_DIR_IN) ? 1842 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1843 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 1844 } 1845 if (et != AHCI_ERR_NONE) 1846 ch->eslots |= (1 << slot->slot); 1847 /* In case of error, freeze device for proper recovery. */ 1848 if ((et != AHCI_ERR_NONE) && (!ch->readlog) && 1849 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 1850 xpt_freeze_devq(ccb->ccb_h.path, 1); 1851 ccb->ccb_h.status |= CAM_DEV_QFRZN; 1852 } 1853 /* Set proper result status. */ 1854 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1855 switch (et) { 1856 case AHCI_ERR_NONE: 1857 ccb->ccb_h.status |= CAM_REQ_CMP; 1858 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 1859 ccb->csio.scsi_status = SCSI_STATUS_OK; 1860 break; 1861 case AHCI_ERR_INVALID: 1862 ch->fatalerr = 1; 1863 ccb->ccb_h.status |= CAM_REQ_INVALID; 1864 break; 1865 case AHCI_ERR_INNOCENT: 1866 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 1867 break; 1868 case AHCI_ERR_TFE: 1869 case AHCI_ERR_NCQ: 1870 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1871 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1872 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1873 } else { 1874 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 1875 } 1876 break; 1877 case AHCI_ERR_SATA: 1878 ch->fatalerr = 1; 1879 if (!ch->readlog) { 1880 xpt_freeze_simq(ch->sim, 1); 1881 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1882 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1883 } 1884 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 1885 break; 1886 case AHCI_ERR_TIMEOUT: 1887 if (!ch->readlog) { 1888 xpt_freeze_simq(ch->sim, 1); 1889 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1890 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1891 } 1892 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1893 break; 1894 default: 1895 ch->fatalerr = 1; 1896 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 1897 } 1898 /* Free slot. */ 1899 ch->oslots &= ~(1 << slot->slot); 1900 ch->rslots &= ~(1 << slot->slot); 1901 ch->aslots &= ~(1 << slot->slot); 1902 if (et != AHCI_ERR_TIMEOUT) { 1903 if (ch->toslots == (1 << slot->slot)) 1904 xpt_release_simq(ch->sim, TRUE); 1905 ch->toslots &= ~(1 << slot->slot); 1906 } 1907 slot->state = AHCI_SLOT_EMPTY; 1908 slot->ccb = NULL; 1909 /* Update channel stats. */ 1910 ch->numrslots--; 1911 ch->numrslotspd[ccb->ccb_h.target_id]--; 1912 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1913 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1914 ch->numtslots--; 1915 ch->numtslotspd[ccb->ccb_h.target_id]--; 1916 } 1917 /* If it was first request of reset sequence and there is no error, 1918 * proceed to second request. */ 1919 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1920 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1921 (ccb->ataio.cmd.control & ATA_A_RESET) && 1922 et == AHCI_ERR_NONE) { 1923 ccb->ataio.cmd.control &= ~ATA_A_RESET; 1924 ahci_begin_transaction(dev, ccb); 1925 return; 1926 } 1927 /* If it was our READ LOG command - process it. */ 1928 if (ch->readlog) { 1929 ahci_process_read_log(dev, ccb); 1930 /* If it was NCQ command error, put result on hold. */ 1931 } else if (et == AHCI_ERR_NCQ) { 1932 ch->hold[slot->slot] = ccb; 1933 ch->numhslots++; 1934 } else 1935 xpt_done(ccb); 1936 /* Unfreeze frozen command. */ 1937 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) { 1938 union ccb *fccb = ch->frozen; 1939 ch->frozen = NULL; 1940 ahci_begin_transaction(dev, fccb); 1941 xpt_release_simq(ch->sim, TRUE); 1942 } 1943 /* If we have no other active commands, ... */ 1944 if (ch->rslots == 0) { 1945 /* if there was fatal error - reset port. */ 1946 if (ch->toslots != 0 || ch->fatalerr) { 1947 ahci_reset(dev); 1948 } else { 1949 /* if we have slots in error, we can reinit port. */ 1950 if (ch->eslots != 0) { 1951 ahci_stop(dev); 1952 ahci_start(dev, 1); 1953 } 1954 /* if there commands on hold, we can do READ LOG. */ 1955 if (!ch->readlog && ch->numhslots) 1956 ahci_issue_read_log(dev); 1957 } 1958 /* If all the rest of commands are in timeout - give them chance. */ 1959 } else if ((ch->rslots & ~ch->toslots) == 0 && 1960 et != AHCI_ERR_TIMEOUT) 1961 ahci_rearm_timeout(dev); 1962 /* Start PM timer. */ 1963 if (ch->numrslots == 0 && ch->pm_level > 3) { 1964 callout_schedule(&ch->pm_timer, 1965 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 1966 } 1967 } 1968 1969 static void 1970 ahci_issue_read_log(device_t dev) 1971 { 1972 struct ahci_channel *ch = device_get_softc(dev); 1973 union ccb *ccb; 1974 struct ccb_ataio *ataio; 1975 int i; 1976 1977 ch->readlog = 1; 1978 /* Find some holden command. */ 1979 for (i = 0; i < ch->numslots; i++) { 1980 if (ch->hold[i]) 1981 break; 1982 } 1983 ccb = xpt_alloc_ccb_nowait(); 1984 if (ccb == NULL) { 1985 device_printf(dev, "Unable allocate READ LOG command"); 1986 return; /* XXX */ 1987 } 1988 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 1989 ccb->ccb_h.func_code = XPT_ATA_IO; 1990 ccb->ccb_h.flags = CAM_DIR_IN; 1991 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 1992 ataio = &ccb->ataio; 1993 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 1994 if (ataio->data_ptr == NULL) { 1995 device_printf(dev, "Unable allocate memory for READ LOG command"); 1996 return; /* XXX */ 1997 } 1998 ataio->dxfer_len = 512; 1999 bzero(&ataio->cmd, sizeof(ataio->cmd)); 2000 ataio->cmd.flags = CAM_ATAIO_48BIT; 2001 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 2002 ataio->cmd.sector_count = 1; 2003 ataio->cmd.sector_count_exp = 0; 2004 ataio->cmd.lba_low = 0x10; 2005 ataio->cmd.lba_mid = 0; 2006 ataio->cmd.lba_mid_exp = 0; 2007 /* Freeze SIM while doing READ LOG EXT. */ 2008 xpt_freeze_simq(ch->sim, 1); 2009 ahci_begin_transaction(dev, ccb); 2010 } 2011 2012 static void 2013 ahci_process_read_log(device_t dev, union ccb *ccb) 2014 { 2015 struct ahci_channel *ch = device_get_softc(dev); 2016 uint8_t *data; 2017 struct ata_res *res; 2018 int i; 2019 2020 ch->readlog = 0; 2021 2022 data = ccb->ataio.data_ptr; 2023 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2024 (data[0] & 0x80) == 0) { 2025 for (i = 0; i < ch->numslots; i++) { 2026 if (!ch->hold[i]) 2027 continue; 2028 if ((data[0] & 0x1F) == i) { 2029 res = &ch->hold[i]->ataio.res; 2030 res->status = data[2]; 2031 res->error = data[3]; 2032 res->lba_low = data[4]; 2033 res->lba_mid = data[5]; 2034 res->lba_high = data[6]; 2035 res->device = data[7]; 2036 res->lba_low_exp = data[8]; 2037 res->lba_mid_exp = data[9]; 2038 res->lba_high_exp = data[10]; 2039 res->sector_count = data[12]; 2040 res->sector_count_exp = data[13]; 2041 } else { 2042 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2043 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2044 } 2045 xpt_done(ch->hold[i]); 2046 ch->hold[i] = NULL; 2047 ch->numhslots--; 2048 } 2049 } else { 2050 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2051 device_printf(dev, "Error while READ LOG EXT\n"); 2052 else if ((data[0] & 0x80) == 0) { 2053 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 2054 } 2055 for (i = 0; i < ch->numslots; i++) { 2056 if (!ch->hold[i]) 2057 continue; 2058 xpt_done(ch->hold[i]); 2059 ch->hold[i] = NULL; 2060 ch->numhslots--; 2061 } 2062 } 2063 free(ccb->ataio.data_ptr, M_AHCI); 2064 xpt_free_ccb(ccb); 2065 xpt_release_simq(ch->sim, TRUE); 2066 } 2067 2068 static void 2069 ahci_start(device_t dev, int fbs) 2070 { 2071 struct ahci_channel *ch = device_get_softc(dev); 2072 u_int32_t cmd; 2073 2074 /* Clear SATA error register */ 2075 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2076 /* Clear any interrupts pending on this channel */ 2077 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2078 /* Configure FIS-based switching if supported. */ 2079 if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2080 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2081 ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2082 ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2083 } 2084 /* Start operations on this channel */ 2085 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2086 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2087 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2088 } 2089 2090 static void 2091 ahci_stop(device_t dev) 2092 { 2093 struct ahci_channel *ch = device_get_softc(dev); 2094 u_int32_t cmd; 2095 int timeout; 2096 2097 /* Kill all activity on this channel */ 2098 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2099 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2100 /* Wait for activity stop. */ 2101 timeout = 0; 2102 do { 2103 DELAY(1000); 2104 if (timeout++ > 1000) { 2105 device_printf(dev, "stopping AHCI engine failed\n"); 2106 break; 2107 } 2108 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2109 ch->eslots = 0; 2110 } 2111 2112 static void 2113 ahci_clo(device_t dev) 2114 { 2115 struct ahci_channel *ch = device_get_softc(dev); 2116 u_int32_t cmd; 2117 int timeout; 2118 2119 /* Issue Command List Override if supported */ 2120 if (ch->caps & AHCI_CAP_SCLO) { 2121 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2122 cmd |= AHCI_P_CMD_CLO; 2123 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2124 timeout = 0; 2125 do { 2126 DELAY(1000); 2127 if (timeout++ > 1000) { 2128 device_printf(dev, "executing CLO failed\n"); 2129 break; 2130 } 2131 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2132 } 2133 } 2134 2135 static void 2136 ahci_stop_fr(device_t dev) 2137 { 2138 struct ahci_channel *ch = device_get_softc(dev); 2139 u_int32_t cmd; 2140 int timeout; 2141 2142 /* Kill all FIS reception on this channel */ 2143 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2144 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2145 /* Wait for FIS reception stop. */ 2146 timeout = 0; 2147 do { 2148 DELAY(1000); 2149 if (timeout++ > 1000) { 2150 device_printf(dev, "stopping AHCI FR engine failed\n"); 2151 break; 2152 } 2153 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2154 } 2155 2156 static void 2157 ahci_start_fr(device_t dev) 2158 { 2159 struct ahci_channel *ch = device_get_softc(dev); 2160 u_int32_t cmd; 2161 2162 /* Start FIS reception on this channel */ 2163 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2164 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2165 } 2166 2167 static int 2168 ahci_wait_ready(device_t dev, int t) 2169 { 2170 struct ahci_channel *ch = device_get_softc(dev); 2171 int timeout = 0; 2172 uint32_t val; 2173 2174 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2175 (ATA_S_BUSY | ATA_S_DRQ)) { 2176 DELAY(1000); 2177 if (timeout++ > t) { 2178 device_printf(dev, "device is not ready (timeout %dms) " 2179 "tfd = %08x\n", t, val); 2180 return (EBUSY); 2181 } 2182 } 2183 if (bootverbose) 2184 device_printf(dev, "ready wait time=%dms\n", timeout); 2185 return (0); 2186 } 2187 2188 static void 2189 ahci_reset(device_t dev) 2190 { 2191 struct ahci_channel *ch = device_get_softc(dev); 2192 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 2193 int i; 2194 2195 xpt_freeze_simq(ch->sim, 1); 2196 if (bootverbose) 2197 device_printf(dev, "AHCI reset...\n"); 2198 /* Requeue freezed command. */ 2199 if (ch->frozen) { 2200 union ccb *fccb = ch->frozen; 2201 ch->frozen = NULL; 2202 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2203 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2204 xpt_freeze_devq(fccb->ccb_h.path, 1); 2205 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2206 } 2207 xpt_done(fccb); 2208 } 2209 /* Kill the engine and requeue all running commands. */ 2210 ahci_stop(dev); 2211 for (i = 0; i < ch->numslots; i++) { 2212 /* Do we have a running request on slot? */ 2213 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2214 continue; 2215 /* XXX; Commands in loading state. */ 2216 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2217 } 2218 for (i = 0; i < ch->numslots; i++) { 2219 if (!ch->hold[i]) 2220 continue; 2221 xpt_done(ch->hold[i]); 2222 ch->hold[i] = NULL; 2223 ch->numhslots--; 2224 } 2225 if (ch->toslots != 0) 2226 xpt_release_simq(ch->sim, TRUE); 2227 ch->eslots = 0; 2228 ch->toslots = 0; 2229 ch->fatalerr = 0; 2230 /* Tell the XPT about the event */ 2231 xpt_async(AC_BUS_RESET, ch->path, NULL); 2232 /* Disable port interrupts */ 2233 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2234 /* Reset and reconnect PHY, */ 2235 if (!ahci_sata_phy_reset(dev)) { 2236 if (bootverbose) 2237 device_printf(dev, 2238 "AHCI reset done: phy reset found no device\n"); 2239 ch->devices = 0; 2240 /* Enable wanted port interrupts */ 2241 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2242 (AHCI_P_IX_CPD | AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2243 xpt_release_simq(ch->sim, TRUE); 2244 return; 2245 } 2246 /* Wait for clearing busy status. */ 2247 if (ahci_wait_ready(dev, 15000)) 2248 ahci_clo(dev); 2249 ahci_start(dev, 1); 2250 ch->devices = 1; 2251 /* Enable wanted port interrupts */ 2252 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2253 (AHCI_P_IX_CPD | AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2254 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2255 ((ch->pm_level == 0) ? AHCI_P_IX_PRC | AHCI_P_IX_PC : 0) | 2256 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2257 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2258 if (bootverbose) 2259 device_printf(dev, "AHCI reset done: device found\n"); 2260 xpt_release_simq(ch->sim, TRUE); 2261 } 2262 2263 static int 2264 ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2265 { 2266 struct ahci_channel *ch = device_get_softc(dev); 2267 u_int8_t *fis = &ctp->cfis[0]; 2268 2269 bzero(ctp->cfis, 64); 2270 fis[0] = 0x27; /* host to device */ 2271 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2272 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2273 fis[1] |= 0x80; 2274 fis[2] = ATA_PACKET_CMD; 2275 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2276 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2277 fis[3] = ATA_F_DMA; 2278 else { 2279 fis[5] = ccb->csio.dxfer_len; 2280 fis[6] = ccb->csio.dxfer_len >> 8; 2281 } 2282 fis[7] = ATA_D_LBA; 2283 fis[15] = ATA_A_4BIT; 2284 bzero(ctp->acmd, 32); 2285 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2286 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2287 ctp->acmd, ccb->csio.cdb_len); 2288 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2289 fis[1] |= 0x80; 2290 fis[2] = ccb->ataio.cmd.command; 2291 fis[3] = ccb->ataio.cmd.features; 2292 fis[4] = ccb->ataio.cmd.lba_low; 2293 fis[5] = ccb->ataio.cmd.lba_mid; 2294 fis[6] = ccb->ataio.cmd.lba_high; 2295 fis[7] = ccb->ataio.cmd.device; 2296 fis[8] = ccb->ataio.cmd.lba_low_exp; 2297 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2298 fis[10] = ccb->ataio.cmd.lba_high_exp; 2299 fis[11] = ccb->ataio.cmd.features_exp; 2300 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2301 fis[12] = tag << 3; 2302 fis[13] = 0; 2303 } else { 2304 fis[12] = ccb->ataio.cmd.sector_count; 2305 fis[13] = ccb->ataio.cmd.sector_count_exp; 2306 } 2307 fis[15] = ATA_A_4BIT; 2308 } else { 2309 fis[15] = ccb->ataio.cmd.control; 2310 } 2311 return (20); 2312 } 2313 2314 static int 2315 ahci_sata_connect(struct ahci_channel *ch) 2316 { 2317 u_int32_t status; 2318 int timeout; 2319 2320 /* Wait up to 100ms for "connect well" */ 2321 for (timeout = 0; timeout < 100 ; timeout++) { 2322 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2323 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2324 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2325 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2326 break; 2327 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2328 if (bootverbose) { 2329 device_printf(ch->dev, "SATA offline status=%08x\n", 2330 status); 2331 } 2332 return (0); 2333 } 2334 DELAY(1000); 2335 } 2336 if (timeout >= 100) { 2337 if (bootverbose) { 2338 device_printf(ch->dev, "SATA connect timeout status=%08x\n", 2339 status); 2340 } 2341 return (0); 2342 } 2343 if (bootverbose) { 2344 device_printf(ch->dev, "SATA connect time=%dms status=%08x\n", 2345 timeout, status); 2346 } 2347 /* Clear SATA error register */ 2348 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2349 return (1); 2350 } 2351 2352 static int 2353 ahci_sata_phy_reset(device_t dev) 2354 { 2355 struct ahci_channel *ch = device_get_softc(dev); 2356 int sata_rev; 2357 uint32_t val; 2358 2359 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2360 if (sata_rev == 1) 2361 val = ATA_SC_SPD_SPEED_GEN1; 2362 else if (sata_rev == 2) 2363 val = ATA_SC_SPD_SPEED_GEN2; 2364 else if (sata_rev == 3) 2365 val = ATA_SC_SPD_SPEED_GEN3; 2366 else 2367 val = 0; 2368 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2369 ATA_SC_DET_RESET | val | 2370 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2371 DELAY(5000); 2372 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2373 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2374 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2375 DELAY(5000); 2376 if (!ahci_sata_connect(ch)) { 2377 if (ch->pm_level > 0) 2378 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2379 return (0); 2380 } 2381 return (1); 2382 } 2383 2384 static void 2385 ahciaction(struct cam_sim *sim, union ccb *ccb) 2386 { 2387 device_t dev; 2388 struct ahci_channel *ch; 2389 2390 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2391 ccb->ccb_h.func_code)); 2392 2393 ch = (struct ahci_channel *)cam_sim_softc(sim); 2394 dev = ch->dev; 2395 switch (ccb->ccb_h.func_code) { 2396 /* Common cases first */ 2397 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2398 case XPT_SCSI_IO: 2399 if (ch->devices == 0) { 2400 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2401 xpt_done(ccb); 2402 break; 2403 } 2404 /* Check for command collision. */ 2405 if (ahci_check_collision(dev, ccb)) { 2406 /* Freeze command. */ 2407 ch->frozen = ccb; 2408 /* We have only one frozen slot, so freeze simq also. */ 2409 xpt_freeze_simq(ch->sim, 1); 2410 return; 2411 } 2412 ahci_begin_transaction(dev, ccb); 2413 break; 2414 case XPT_EN_LUN: /* Enable LUN as a target */ 2415 case XPT_TARGET_IO: /* Execute target I/O request */ 2416 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2417 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2418 case XPT_ABORT: /* Abort the specified CCB */ 2419 /* XXX Implement */ 2420 ccb->ccb_h.status = CAM_REQ_INVALID; 2421 xpt_done(ccb); 2422 break; 2423 case XPT_SET_TRAN_SETTINGS: 2424 { 2425 struct ccb_trans_settings *cts = &ccb->cts; 2426 struct ahci_device *d; 2427 2428 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2429 d = &ch->curr[ccb->ccb_h.target_id]; 2430 else 2431 d = &ch->user[ccb->ccb_h.target_id]; 2432 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2433 d->revision = cts->xport_specific.sata.revision; 2434 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2435 d->mode = cts->xport_specific.sata.mode; 2436 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2437 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2438 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2439 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2440 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2441 ch->pm_present = cts->xport_specific.sata.pm_present; 2442 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2443 d->atapi = cts->xport_specific.sata.atapi; 2444 ccb->ccb_h.status = CAM_REQ_CMP; 2445 xpt_done(ccb); 2446 break; 2447 } 2448 case XPT_GET_TRAN_SETTINGS: 2449 /* Get default/user set transfer settings for the target */ 2450 { 2451 struct ccb_trans_settings *cts = &ccb->cts; 2452 struct ahci_device *d; 2453 uint32_t status; 2454 2455 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2456 d = &ch->curr[ccb->ccb_h.target_id]; 2457 else 2458 d = &ch->user[ccb->ccb_h.target_id]; 2459 cts->protocol = PROTO_ATA; 2460 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2461 cts->transport = XPORT_SATA; 2462 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2463 cts->proto_specific.valid = 0; 2464 cts->xport_specific.sata.valid = 0; 2465 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2466 (ccb->ccb_h.target_id == 15 || 2467 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2468 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2469 if (status & 0x0f0) { 2470 cts->xport_specific.sata.revision = 2471 (status & 0x0f0) >> 4; 2472 cts->xport_specific.sata.valid |= 2473 CTS_SATA_VALID_REVISION; 2474 } 2475 } else { 2476 cts->xport_specific.sata.revision = d->revision; 2477 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2478 } 2479 cts->xport_specific.sata.mode = d->mode; 2480 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2481 cts->xport_specific.sata.bytecount = d->bytecount; 2482 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2483 cts->xport_specific.sata.pm_present = ch->pm_present; 2484 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2485 cts->xport_specific.sata.tags = d->tags; 2486 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2487 cts->xport_specific.sata.atapi = d->atapi; 2488 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2489 ccb->ccb_h.status = CAM_REQ_CMP; 2490 xpt_done(ccb); 2491 break; 2492 } 2493 #if 0 2494 case XPT_CALC_GEOMETRY: 2495 { 2496 struct ccb_calc_geometry *ccg; 2497 uint32_t size_mb; 2498 uint32_t secs_per_cylinder; 2499 2500 ccg = &ccb->ccg; 2501 size_mb = ccg->volume_size 2502 / ((1024L * 1024L) / ccg->block_size); 2503 if (size_mb >= 1024 && (aha->extended_trans != 0)) { 2504 if (size_mb >= 2048) { 2505 ccg->heads = 255; 2506 ccg->secs_per_track = 63; 2507 } else { 2508 ccg->heads = 128; 2509 ccg->secs_per_track = 32; 2510 } 2511 } else { 2512 ccg->heads = 64; 2513 ccg->secs_per_track = 32; 2514 } 2515 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 2516 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 2517 ccb->ccb_h.status = CAM_REQ_CMP; 2518 xpt_done(ccb); 2519 break; 2520 } 2521 #endif 2522 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2523 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2524 ahci_reset(dev); 2525 ccb->ccb_h.status = CAM_REQ_CMP; 2526 xpt_done(ccb); 2527 break; 2528 case XPT_TERM_IO: /* Terminate the I/O process */ 2529 /* XXX Implement */ 2530 ccb->ccb_h.status = CAM_REQ_INVALID; 2531 xpt_done(ccb); 2532 break; 2533 case XPT_PATH_INQ: /* Path routing inquiry */ 2534 { 2535 struct ccb_pathinq *cpi = &ccb->cpi; 2536 2537 cpi->version_num = 1; /* XXX??? */ 2538 cpi->hba_inquiry = PI_SDTR_ABLE; 2539 if (ch->caps & AHCI_CAP_SNCQ) 2540 cpi->hba_inquiry |= PI_TAG_ABLE; 2541 if (ch->caps & AHCI_CAP_SPM) 2542 cpi->hba_inquiry |= PI_SATAPM; 2543 cpi->target_sprt = 0; 2544 cpi->hba_misc = PIM_SEQSCAN; 2545 cpi->hba_eng_cnt = 0; 2546 if (ch->caps & AHCI_CAP_SPM) 2547 cpi->max_target = 15; 2548 else 2549 cpi->max_target = 0; 2550 cpi->max_lun = 0; 2551 cpi->initiator_id = 0; 2552 cpi->bus_id = cam_sim_bus(sim); 2553 cpi->base_transfer_speed = 150000; 2554 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2555 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 2556 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2557 cpi->unit_number = cam_sim_unit(sim); 2558 cpi->transport = XPORT_SATA; 2559 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2560 cpi->protocol = PROTO_ATA; 2561 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2562 cpi->maxio = MAXPHYS; 2563 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 2564 if (pci_get_devid(device_get_parent(dev)) == 0x43801002) 2565 cpi->maxio = min(cpi->maxio, 128 * 512); 2566 cpi->ccb_h.status = CAM_REQ_CMP; 2567 xpt_done(ccb); 2568 break; 2569 } 2570 default: 2571 ccb->ccb_h.status = CAM_REQ_INVALID; 2572 xpt_done(ccb); 2573 break; 2574 } 2575 } 2576 2577 static void 2578 ahcipoll(struct cam_sim *sim) 2579 { 2580 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 2581 2582 ahci_ch_intr(ch->dev); 2583 } 2584