1 /*- 2 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <sys/endian.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <machine/stdarg.h> 41 #include <machine/resource.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include "ahci.h" 45 46 #include <cam/cam.h> 47 #include <cam/cam_ccb.h> 48 #include <cam/cam_sim.h> 49 #include <cam/cam_xpt_sim.h> 50 #include <cam/cam_debug.h> 51 52 /* local prototypes */ 53 static void ahci_intr(void *data); 54 static void ahci_intr_one(void *data); 55 static void ahci_intr_one_edge(void *data); 56 static int ahci_ch_init(device_t dev); 57 static int ahci_ch_deinit(device_t dev); 58 static int ahci_ch_suspend(device_t dev); 59 static int ahci_ch_resume(device_t dev); 60 static void ahci_ch_pm(void *arg); 61 static void ahci_ch_intr(void *arg); 62 static void ahci_ch_intr_direct(void *arg); 63 static void ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus); 64 static void ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb); 65 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 66 static void ahci_execute_transaction(struct ahci_slot *slot); 67 static void ahci_timeout(struct ahci_slot *slot); 68 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 69 static int ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 70 static void ahci_dmainit(device_t dev); 71 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 72 static void ahci_dmafini(device_t dev); 73 static void ahci_slotsalloc(device_t dev); 74 static void ahci_slotsfree(device_t dev); 75 static void ahci_reset(struct ahci_channel *ch); 76 static void ahci_start(struct ahci_channel *ch, int fbs); 77 static void ahci_stop(struct ahci_channel *ch); 78 static void ahci_clo(struct ahci_channel *ch); 79 static void ahci_start_fr(struct ahci_channel *ch); 80 static void ahci_stop_fr(struct ahci_channel *ch); 81 82 static int ahci_sata_connect(struct ahci_channel *ch); 83 static int ahci_sata_phy_reset(struct ahci_channel *ch); 84 static int ahci_wait_ready(struct ahci_channel *ch, int t, int t0); 85 86 static void ahci_issue_recovery(struct ahci_channel *ch); 87 static void ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb); 88 static void ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb); 89 90 static void ahciaction(struct cam_sim *sim, union ccb *ccb); 91 static void ahcipoll(struct cam_sim *sim); 92 93 static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 94 95 #define recovery_type spriv_field0 96 #define RECOVERY_NONE 0 97 #define RECOVERY_READ_LOG 1 98 #define RECOVERY_REQUEST_SENSE 2 99 #define recovery_slot spriv_field1 100 101 int 102 ahci_ctlr_setup(device_t dev) 103 { 104 struct ahci_controller *ctlr = device_get_softc(dev); 105 /* Clear interrupts */ 106 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 107 /* Configure CCC */ 108 if (ctlr->ccc) { 109 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 110 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 111 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 112 (4 << AHCI_CCCC_CC_SHIFT) | 113 AHCI_CCCC_EN); 114 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 115 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 116 if (bootverbose) { 117 device_printf(dev, 118 "CCC with %dms/4cmd enabled on vector %d\n", 119 ctlr->ccc, ctlr->cccv); 120 } 121 } 122 /* Enable AHCI interrupts */ 123 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 124 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 125 return (0); 126 } 127 128 int 129 ahci_ctlr_reset(device_t dev) 130 { 131 struct ahci_controller *ctlr = device_get_softc(dev); 132 int timeout; 133 134 /* Enable AHCI mode */ 135 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 136 /* Reset AHCI controller */ 137 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 138 for (timeout = 1000; timeout > 0; timeout--) { 139 DELAY(1000); 140 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 141 break; 142 } 143 if (timeout == 0) { 144 device_printf(dev, "AHCI controller reset failure\n"); 145 return (ENXIO); 146 } 147 /* Reenable AHCI mode */ 148 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 149 150 if (ctlr->quirks & AHCI_Q_RESTORE_CAP) { 151 /* 152 * Restore capability field. 153 * This is write to a read-only register to restore its state. 154 * On fully standard-compliant hardware this is not needed and 155 * this operation shall not take place. See ahci_pci.c for 156 * platforms using this quirk. 157 */ 158 ATA_OUTL(ctlr->r_mem, AHCI_CAP, ctlr->caps); 159 } 160 161 return (0); 162 } 163 164 165 int 166 ahci_attach(device_t dev) 167 { 168 struct ahci_controller *ctlr = device_get_softc(dev); 169 int error, i, speed, unit; 170 uint32_t u, version; 171 device_t child; 172 173 ctlr->dev = dev; 174 ctlr->ccc = 0; 175 resource_int_value(device_get_name(dev), 176 device_get_unit(dev), "ccc", &ctlr->ccc); 177 178 /* Setup our own memory management for channels. */ 179 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 180 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 181 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 182 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 183 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 184 ahci_free_mem(dev); 185 return (error); 186 } 187 if ((error = rman_manage_region(&ctlr->sc_iomem, 188 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 189 ahci_free_mem(dev); 190 rman_fini(&ctlr->sc_iomem); 191 return (error); 192 } 193 /* Get the HW capabilities */ 194 version = ATA_INL(ctlr->r_mem, AHCI_VS); 195 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 196 if (version >= 0x00010200) 197 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 198 if (ctlr->caps & AHCI_CAP_EMS) 199 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 200 201 if (ctlr->quirks & AHCI_Q_FORCE_PI) { 202 /* 203 * Enable ports. 204 * The spec says that BIOS sets up bits corresponding to 205 * available ports. On platforms where this information 206 * is missing, the driver can define available ports on its own. 207 */ 208 int nports = (ctlr->caps & AHCI_CAP_NPMASK) + 1; 209 int nmask = (1 << nports) - 1; 210 211 ATA_OUTL(ctlr->r_mem, AHCI_PI, nmask); 212 device_printf(dev, "Forcing PI to %d ports (mask = %x)\n", 213 nports, nmask); 214 } 215 216 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 217 218 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */ 219 if ((ctlr->quirks & AHCI_Q_ALTSIG) && 220 (ctlr->caps & AHCI_CAP_SPM) == 0) 221 ctlr->quirks |= AHCI_Q_NOBSYRES; 222 223 if (ctlr->quirks & AHCI_Q_1CH) { 224 ctlr->caps &= ~AHCI_CAP_NPMASK; 225 ctlr->ichannels &= 0x01; 226 } 227 if (ctlr->quirks & AHCI_Q_2CH) { 228 ctlr->caps &= ~AHCI_CAP_NPMASK; 229 ctlr->caps |= 1; 230 ctlr->ichannels &= 0x03; 231 } 232 if (ctlr->quirks & AHCI_Q_4CH) { 233 ctlr->caps &= ~AHCI_CAP_NPMASK; 234 ctlr->caps |= 3; 235 ctlr->ichannels &= 0x0f; 236 } 237 ctlr->channels = MAX(flsl(ctlr->ichannels), 238 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 239 if (ctlr->quirks & AHCI_Q_NOPMP) 240 ctlr->caps &= ~AHCI_CAP_SPM; 241 if (ctlr->quirks & AHCI_Q_NONCQ) 242 ctlr->caps &= ~AHCI_CAP_SNCQ; 243 if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 244 ctlr->ccc = 0; 245 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC); 246 247 /* Create controller-wide DMA tag. */ 248 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 249 (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR : 250 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 251 BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, 252 0, NULL, NULL, &ctlr->dma_tag)) { 253 ahci_free_mem(dev); 254 rman_fini(&ctlr->sc_iomem); 255 return (ENXIO); 256 } 257 258 ahci_ctlr_setup(dev); 259 260 /* Setup interrupts. */ 261 if ((error = ahci_setup_interrupt(dev)) != 0) { 262 bus_dma_tag_destroy(ctlr->dma_tag); 263 ahci_free_mem(dev); 264 rman_fini(&ctlr->sc_iomem); 265 return (error); 266 } 267 268 i = 0; 269 for (u = ctlr->ichannels; u != 0; u >>= 1) 270 i += (u & 1); 271 ctlr->direct = (ctlr->msi && (ctlr->numirqs > 1 || i <= 3)); 272 resource_int_value(device_get_name(dev), device_get_unit(dev), 273 "direct", &ctlr->direct); 274 /* Announce HW capabilities. */ 275 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 276 device_printf(dev, 277 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 278 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 279 ((version >> 4) & 0xf0) + (version & 0x0f), 280 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 281 ((speed == 1) ? "1.5":((speed == 2) ? "3": 282 ((speed == 3) ? "6":"?"))), 283 (ctlr->caps & AHCI_CAP_SPM) ? 284 "supported" : "not supported", 285 (ctlr->caps & AHCI_CAP_FBSS) ? 286 " with FBS" : ""); 287 if (ctlr->quirks != 0) { 288 device_printf(dev, "quirks=0x%b\n", ctlr->quirks, 289 AHCI_Q_BIT_STRING); 290 } 291 if (bootverbose) { 292 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 293 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 294 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 295 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 296 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 297 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 298 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 299 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 300 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 301 ((speed == 1) ? "1.5":((speed == 2) ? "3": 302 ((speed == 3) ? "6":"?")))); 303 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 304 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 305 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 306 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 307 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 308 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 309 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 310 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 311 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 312 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 313 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 314 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 315 } 316 if (bootverbose && version >= 0x00010200) { 317 device_printf(dev, "Caps2:%s%s%s%s%s%s\n", 318 (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"", 319 (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"", 320 (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"", 321 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 322 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 323 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 324 } 325 /* Attach all channels on this controller */ 326 for (unit = 0; unit < ctlr->channels; unit++) { 327 child = device_add_child(dev, "ahcich", -1); 328 if (child == NULL) { 329 device_printf(dev, "failed to add channel device\n"); 330 continue; 331 } 332 device_set_ivars(child, (void *)(intptr_t)unit); 333 if ((ctlr->ichannels & (1 << unit)) == 0) 334 device_disable(child); 335 } 336 if (ctlr->caps & AHCI_CAP_EMS) { 337 child = device_add_child(dev, "ahciem", -1); 338 if (child == NULL) 339 device_printf(dev, "failed to add enclosure device\n"); 340 else 341 device_set_ivars(child, (void *)(intptr_t)-1); 342 } 343 bus_generic_attach(dev); 344 return (0); 345 } 346 347 int 348 ahci_detach(device_t dev) 349 { 350 struct ahci_controller *ctlr = device_get_softc(dev); 351 int i; 352 353 /* Detach & delete all children */ 354 device_delete_children(dev); 355 356 /* Free interrupts. */ 357 for (i = 0; i < ctlr->numirqs; i++) { 358 if (ctlr->irqs[i].r_irq) { 359 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 360 ctlr->irqs[i].handle); 361 bus_release_resource(dev, SYS_RES_IRQ, 362 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 363 } 364 } 365 bus_dma_tag_destroy(ctlr->dma_tag); 366 /* Free memory. */ 367 rman_fini(&ctlr->sc_iomem); 368 ahci_free_mem(dev); 369 return (0); 370 } 371 372 void 373 ahci_free_mem(device_t dev) 374 { 375 struct ahci_controller *ctlr = device_get_softc(dev); 376 377 /* Release memory resources */ 378 if (ctlr->r_mem) 379 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 380 if (ctlr->r_msix_table) 381 bus_release_resource(dev, SYS_RES_MEMORY, 382 ctlr->r_msix_tab_rid, ctlr->r_msix_table); 383 if (ctlr->r_msix_pba) 384 bus_release_resource(dev, SYS_RES_MEMORY, 385 ctlr->r_msix_pba_rid, ctlr->r_msix_pba); 386 387 ctlr->r_msix_pba = ctlr->r_mem = ctlr->r_msix_table = NULL; 388 } 389 390 int 391 ahci_setup_interrupt(device_t dev) 392 { 393 struct ahci_controller *ctlr = device_get_softc(dev); 394 int i; 395 396 /* Check for single MSI vector fallback. */ 397 if (ctlr->numirqs > 1 && 398 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 399 device_printf(dev, "Falling back to one MSI\n"); 400 ctlr->numirqs = 1; 401 } 402 403 /* Ensure we don't overrun irqs. */ 404 if (ctlr->numirqs > AHCI_MAX_IRQS) { 405 device_printf(dev, "Too many irqs %d > %d (clamping)\n", 406 ctlr->numirqs, AHCI_MAX_IRQS); 407 ctlr->numirqs = AHCI_MAX_IRQS; 408 } 409 410 /* Allocate all IRQs. */ 411 for (i = 0; i < ctlr->numirqs; i++) { 412 ctlr->irqs[i].ctlr = ctlr; 413 ctlr->irqs[i].r_irq_rid = i + (ctlr->msi ? 1 : 0); 414 if (ctlr->channels == 1 && !ctlr->ccc && ctlr->msi) 415 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 416 else if (ctlr->numirqs == 1 || i >= ctlr->channels || 417 (ctlr->ccc && i == ctlr->cccv)) 418 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 419 else if (ctlr->channels > ctlr->numirqs && 420 i == ctlr->numirqs - 1) 421 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 422 else 423 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 424 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 425 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 426 device_printf(dev, "unable to map interrupt\n"); 427 return (ENXIO); 428 } 429 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 430 (ctlr->irqs[i].mode != AHCI_IRQ_MODE_ONE) ? ahci_intr : 431 ((ctlr->quirks & AHCI_Q_EDGEIS) ? ahci_intr_one_edge : 432 ahci_intr_one), 433 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 434 /* SOS XXX release r_irq */ 435 device_printf(dev, "unable to setup interrupt\n"); 436 return (ENXIO); 437 } 438 if (ctlr->numirqs > 1) { 439 bus_describe_intr(dev, ctlr->irqs[i].r_irq, 440 ctlr->irqs[i].handle, 441 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 442 "ch%d" : "%d", i); 443 } 444 } 445 return (0); 446 } 447 448 /* 449 * Common case interrupt handler. 450 */ 451 static void 452 ahci_intr(void *data) 453 { 454 struct ahci_controller_irq *irq = data; 455 struct ahci_controller *ctlr = irq->ctlr; 456 u_int32_t is, ise = 0; 457 void *arg; 458 int unit; 459 460 if (irq->mode == AHCI_IRQ_MODE_ALL) { 461 unit = 0; 462 if (ctlr->ccc) 463 is = ctlr->ichannels; 464 else 465 is = ATA_INL(ctlr->r_mem, AHCI_IS); 466 } else { /* AHCI_IRQ_MODE_AFTER */ 467 unit = irq->r_irq_rid - 1; 468 is = ATA_INL(ctlr->r_mem, AHCI_IS); 469 is &= (0xffffffff << unit); 470 } 471 /* CCC interrupt is edge triggered. */ 472 if (ctlr->ccc) 473 ise = 1 << ctlr->cccv; 474 /* Some controllers have edge triggered IS. */ 475 if (ctlr->quirks & AHCI_Q_EDGEIS) 476 ise |= is; 477 if (ise != 0) 478 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 479 for (; unit < ctlr->channels; unit++) { 480 if ((is & (1 << unit)) != 0 && 481 (arg = ctlr->interrupt[unit].argument)) { 482 ctlr->interrupt[unit].function(arg); 483 } 484 } 485 /* AHCI declares level triggered IS. */ 486 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 487 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 488 ATA_RBL(ctlr->r_mem, AHCI_IS); 489 } 490 491 /* 492 * Simplified interrupt handler for multivector MSI mode. 493 */ 494 static void 495 ahci_intr_one(void *data) 496 { 497 struct ahci_controller_irq *irq = data; 498 struct ahci_controller *ctlr = irq->ctlr; 499 void *arg; 500 int unit; 501 502 unit = irq->r_irq_rid - 1; 503 if ((arg = ctlr->interrupt[unit].argument)) 504 ctlr->interrupt[unit].function(arg); 505 /* AHCI declares level triggered IS. */ 506 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 507 ATA_RBL(ctlr->r_mem, AHCI_IS); 508 } 509 510 static void 511 ahci_intr_one_edge(void *data) 512 { 513 struct ahci_controller_irq *irq = data; 514 struct ahci_controller *ctlr = irq->ctlr; 515 void *arg; 516 int unit; 517 518 unit = irq->r_irq_rid - 1; 519 /* Some controllers have edge triggered IS. */ 520 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 521 if ((arg = ctlr->interrupt[unit].argument)) 522 ctlr->interrupt[unit].function(arg); 523 ATA_RBL(ctlr->r_mem, AHCI_IS); 524 } 525 526 struct resource * 527 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 528 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 529 { 530 struct ahci_controller *ctlr = device_get_softc(dev); 531 struct resource *res; 532 rman_res_t st; 533 int offset, size, unit; 534 535 unit = (intptr_t)device_get_ivars(child); 536 res = NULL; 537 switch (type) { 538 case SYS_RES_MEMORY: 539 if (unit >= 0) { 540 offset = AHCI_OFFSET + (unit << 7); 541 size = 128; 542 } else if (*rid == 0) { 543 offset = AHCI_EM_CTL; 544 size = 4; 545 } else { 546 offset = (ctlr->emloc & 0xffff0000) >> 14; 547 size = (ctlr->emloc & 0x0000ffff) << 2; 548 if (*rid != 1) { 549 if (*rid == 2 && (ctlr->capsem & 550 (AHCI_EM_XMT | AHCI_EM_SMB)) == 0) 551 offset += size; 552 else 553 break; 554 } 555 } 556 st = rman_get_start(ctlr->r_mem); 557 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 558 st + offset + size - 1, size, RF_ACTIVE, child); 559 if (res) { 560 bus_space_handle_t bsh; 561 bus_space_tag_t bst; 562 bsh = rman_get_bushandle(ctlr->r_mem); 563 bst = rman_get_bustag(ctlr->r_mem); 564 bus_space_subregion(bst, bsh, offset, 128, &bsh); 565 rman_set_bushandle(res, bsh); 566 rman_set_bustag(res, bst); 567 } 568 break; 569 case SYS_RES_IRQ: 570 if (*rid == ATA_IRQ_RID) 571 res = ctlr->irqs[0].r_irq; 572 break; 573 } 574 return (res); 575 } 576 577 int 578 ahci_release_resource(device_t dev, device_t child, int type, int rid, 579 struct resource *r) 580 { 581 582 switch (type) { 583 case SYS_RES_MEMORY: 584 rman_release_resource(r); 585 return (0); 586 case SYS_RES_IRQ: 587 if (rid != ATA_IRQ_RID) 588 return (ENOENT); 589 return (0); 590 } 591 return (EINVAL); 592 } 593 594 int 595 ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 596 int flags, driver_filter_t *filter, driver_intr_t *function, 597 void *argument, void **cookiep) 598 { 599 struct ahci_controller *ctlr = device_get_softc(dev); 600 int unit = (intptr_t)device_get_ivars(child); 601 602 if (filter != NULL) { 603 printf("ahci.c: we cannot use a filter here\n"); 604 return (EINVAL); 605 } 606 ctlr->interrupt[unit].function = function; 607 ctlr->interrupt[unit].argument = argument; 608 return (0); 609 } 610 611 int 612 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 613 void *cookie) 614 { 615 struct ahci_controller *ctlr = device_get_softc(dev); 616 int unit = (intptr_t)device_get_ivars(child); 617 618 ctlr->interrupt[unit].function = NULL; 619 ctlr->interrupt[unit].argument = NULL; 620 return (0); 621 } 622 623 int 624 ahci_print_child(device_t dev, device_t child) 625 { 626 int retval, channel; 627 628 retval = bus_print_child_header(dev, child); 629 channel = (int)(intptr_t)device_get_ivars(child); 630 if (channel >= 0) 631 retval += printf(" at channel %d", channel); 632 retval += bus_print_child_footer(dev, child); 633 return (retval); 634 } 635 636 int 637 ahci_child_location_str(device_t dev, device_t child, char *buf, 638 size_t buflen) 639 { 640 int channel; 641 642 channel = (int)(intptr_t)device_get_ivars(child); 643 if (channel >= 0) 644 snprintf(buf, buflen, "channel=%d", channel); 645 return (0); 646 } 647 648 bus_dma_tag_t 649 ahci_get_dma_tag(device_t dev, device_t child) 650 { 651 struct ahci_controller *ctlr = device_get_softc(dev); 652 653 return (ctlr->dma_tag); 654 } 655 656 static int 657 ahci_ch_probe(device_t dev) 658 { 659 660 device_set_desc_copy(dev, "AHCI channel"); 661 return (BUS_PROBE_DEFAULT); 662 } 663 664 static int 665 ahci_ch_attach(device_t dev) 666 { 667 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 668 struct ahci_channel *ch = device_get_softc(dev); 669 struct cam_devq *devq; 670 int rid, error, i, sata_rev = 0; 671 u_int32_t version; 672 673 ch->dev = dev; 674 ch->unit = (intptr_t)device_get_ivars(dev); 675 ch->caps = ctlr->caps; 676 ch->caps2 = ctlr->caps2; 677 ch->start = ctlr->ch_start; 678 ch->quirks = ctlr->quirks; 679 ch->vendorid = ctlr->vendorid; 680 ch->deviceid = ctlr->deviceid; 681 ch->subvendorid = ctlr->subvendorid; 682 ch->subdeviceid = ctlr->subdeviceid; 683 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1; 684 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 685 ch->pm_level = 0; 686 resource_int_value(device_get_name(dev), 687 device_get_unit(dev), "pm_level", &ch->pm_level); 688 STAILQ_INIT(&ch->doneq); 689 if (ch->pm_level > 3) 690 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 691 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0); 692 /* JMicron external ports (0) sometimes limited */ 693 if ((ctlr->quirks & AHCI_Q_SATA1_UNIT0) && ch->unit == 0) 694 sata_rev = 1; 695 if (ch->quirks & AHCI_Q_SATA2) 696 sata_rev = 2; 697 resource_int_value(device_get_name(dev), 698 device_get_unit(dev), "sata_rev", &sata_rev); 699 for (i = 0; i < 16; i++) { 700 ch->user[i].revision = sata_rev; 701 ch->user[i].mode = 0; 702 ch->user[i].bytecount = 8192; 703 ch->user[i].tags = ch->numslots; 704 ch->user[i].caps = 0; 705 ch->curr[i] = ch->user[i]; 706 if (ch->pm_level) { 707 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 708 CTS_SATA_CAPS_H_APST | 709 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 710 } 711 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA | 712 CTS_SATA_CAPS_H_AN; 713 } 714 rid = 0; 715 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 716 &rid, RF_ACTIVE))) 717 return (ENXIO); 718 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 719 version = ATA_INL(ctlr->r_mem, AHCI_VS); 720 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS)) 721 ch->chcaps |= AHCI_P_CMD_FBSCP; 722 if (ch->caps2 & AHCI_CAP2_SDS) 723 ch->chscaps = ATA_INL(ch->r_mem, AHCI_P_DEVSLP); 724 if (bootverbose) { 725 device_printf(dev, "Caps:%s%s%s%s%s%s\n", 726 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 727 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 728 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 729 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 730 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"", 731 (ch->chscaps & AHCI_P_DEVSLP_DSP) ? " DSP":""); 732 } 733 ahci_dmainit(dev); 734 ahci_slotsalloc(dev); 735 mtx_lock(&ch->mtx); 736 ahci_ch_init(dev); 737 rid = ATA_IRQ_RID; 738 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 739 &rid, RF_SHAREABLE | RF_ACTIVE))) { 740 device_printf(dev, "Unable to map interrupt\n"); 741 error = ENXIO; 742 goto err0; 743 } 744 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 745 ctlr->direct ? ahci_ch_intr_direct : ahci_ch_intr, 746 ch, &ch->ih))) { 747 device_printf(dev, "Unable to setup interrupt\n"); 748 error = ENXIO; 749 goto err1; 750 } 751 /* Create the device queue for our SIM. */ 752 devq = cam_simq_alloc(ch->numslots); 753 if (devq == NULL) { 754 device_printf(dev, "Unable to allocate simq\n"); 755 error = ENOMEM; 756 goto err1; 757 } 758 /* Construct SIM entry */ 759 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 760 device_get_unit(dev), (struct mtx *)&ch->mtx, 761 (ch->quirks & AHCI_Q_NOCCS) ? 1 : min(2, ch->numslots), 762 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 763 devq); 764 if (ch->sim == NULL) { 765 cam_simq_free(devq); 766 device_printf(dev, "unable to allocate sim\n"); 767 error = ENOMEM; 768 goto err1; 769 } 770 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 771 device_printf(dev, "unable to register xpt bus\n"); 772 error = ENXIO; 773 goto err2; 774 } 775 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 776 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 777 device_printf(dev, "unable to create path\n"); 778 error = ENXIO; 779 goto err3; 780 } 781 if (ch->pm_level > 3) { 782 callout_reset(&ch->pm_timer, 783 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 784 ahci_ch_pm, ch); 785 } 786 mtx_unlock(&ch->mtx); 787 return (0); 788 789 err3: 790 xpt_bus_deregister(cam_sim_path(ch->sim)); 791 err2: 792 cam_sim_free(ch->sim, /*free_devq*/TRUE); 793 err1: 794 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 795 err0: 796 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 797 mtx_unlock(&ch->mtx); 798 mtx_destroy(&ch->mtx); 799 return (error); 800 } 801 802 static int 803 ahci_ch_detach(device_t dev) 804 { 805 struct ahci_channel *ch = device_get_softc(dev); 806 807 mtx_lock(&ch->mtx); 808 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 809 /* Forget about reset. */ 810 if (ch->resetting) { 811 ch->resetting = 0; 812 xpt_release_simq(ch->sim, TRUE); 813 } 814 xpt_free_path(ch->path); 815 xpt_bus_deregister(cam_sim_path(ch->sim)); 816 cam_sim_free(ch->sim, /*free_devq*/TRUE); 817 mtx_unlock(&ch->mtx); 818 819 if (ch->pm_level > 3) 820 callout_drain(&ch->pm_timer); 821 callout_drain(&ch->reset_timer); 822 bus_teardown_intr(dev, ch->r_irq, ch->ih); 823 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 824 825 ahci_ch_deinit(dev); 826 ahci_slotsfree(dev); 827 ahci_dmafini(dev); 828 829 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 830 mtx_destroy(&ch->mtx); 831 return (0); 832 } 833 834 static int 835 ahci_ch_init(device_t dev) 836 { 837 struct ahci_channel *ch = device_get_softc(dev); 838 uint64_t work; 839 840 /* Disable port interrupts */ 841 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 842 /* Setup work areas */ 843 work = ch->dma.work_bus + AHCI_CL_OFFSET; 844 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 845 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 846 work = ch->dma.rfis_bus; 847 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 848 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 849 /* Activate the channel and power/spin up device */ 850 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 851 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 852 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 853 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 854 ahci_start_fr(ch); 855 ahci_start(ch, 1); 856 return (0); 857 } 858 859 static int 860 ahci_ch_deinit(device_t dev) 861 { 862 struct ahci_channel *ch = device_get_softc(dev); 863 864 /* Disable port interrupts. */ 865 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 866 /* Reset command register. */ 867 ahci_stop(ch); 868 ahci_stop_fr(ch); 869 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 870 /* Allow everything, including partial and slumber modes. */ 871 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 872 /* Request slumber mode transition and give some time to get there. */ 873 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 874 DELAY(100); 875 /* Disable PHY. */ 876 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 877 return (0); 878 } 879 880 static int 881 ahci_ch_suspend(device_t dev) 882 { 883 struct ahci_channel *ch = device_get_softc(dev); 884 885 mtx_lock(&ch->mtx); 886 xpt_freeze_simq(ch->sim, 1); 887 /* Forget about reset. */ 888 if (ch->resetting) { 889 ch->resetting = 0; 890 callout_stop(&ch->reset_timer); 891 xpt_release_simq(ch->sim, TRUE); 892 } 893 while (ch->oslots) 894 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100); 895 ahci_ch_deinit(dev); 896 mtx_unlock(&ch->mtx); 897 return (0); 898 } 899 900 static int 901 ahci_ch_resume(device_t dev) 902 { 903 struct ahci_channel *ch = device_get_softc(dev); 904 905 mtx_lock(&ch->mtx); 906 ahci_ch_init(dev); 907 ahci_reset(ch); 908 xpt_release_simq(ch->sim, TRUE); 909 mtx_unlock(&ch->mtx); 910 return (0); 911 } 912 913 devclass_t ahcich_devclass; 914 static device_method_t ahcich_methods[] = { 915 DEVMETHOD(device_probe, ahci_ch_probe), 916 DEVMETHOD(device_attach, ahci_ch_attach), 917 DEVMETHOD(device_detach, ahci_ch_detach), 918 DEVMETHOD(device_suspend, ahci_ch_suspend), 919 DEVMETHOD(device_resume, ahci_ch_resume), 920 DEVMETHOD_END 921 }; 922 static driver_t ahcich_driver = { 923 "ahcich", 924 ahcich_methods, 925 sizeof(struct ahci_channel) 926 }; 927 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, NULL, NULL); 928 929 struct ahci_dc_cb_args { 930 bus_addr_t maddr; 931 int error; 932 }; 933 934 static void 935 ahci_dmainit(device_t dev) 936 { 937 struct ahci_channel *ch = device_get_softc(dev); 938 struct ahci_dc_cb_args dcba; 939 size_t rfsize; 940 941 /* Command area. */ 942 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 943 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 944 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 945 0, NULL, NULL, &ch->dma.work_tag)) 946 goto error; 947 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 948 BUS_DMA_ZERO, &ch->dma.work_map)) 949 goto error; 950 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 951 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 952 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 953 goto error; 954 } 955 ch->dma.work_bus = dcba.maddr; 956 /* FIS receive area. */ 957 if (ch->chcaps & AHCI_P_CMD_FBSCP) 958 rfsize = 4096; 959 else 960 rfsize = 256; 961 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 962 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 963 NULL, NULL, rfsize, 1, rfsize, 964 0, NULL, NULL, &ch->dma.rfis_tag)) 965 goto error; 966 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 967 &ch->dma.rfis_map)) 968 goto error; 969 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 970 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 971 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 972 goto error; 973 } 974 ch->dma.rfis_bus = dcba.maddr; 975 /* Data area. */ 976 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 977 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 978 NULL, NULL, 979 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 980 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 981 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 982 goto error; 983 } 984 return; 985 986 error: 987 device_printf(dev, "WARNING - DMA initialization failed\n"); 988 ahci_dmafini(dev); 989 } 990 991 static void 992 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 993 { 994 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 995 996 if (!(dcba->error = error)) 997 dcba->maddr = segs[0].ds_addr; 998 } 999 1000 static void 1001 ahci_dmafini(device_t dev) 1002 { 1003 struct ahci_channel *ch = device_get_softc(dev); 1004 1005 if (ch->dma.data_tag) { 1006 bus_dma_tag_destroy(ch->dma.data_tag); 1007 ch->dma.data_tag = NULL; 1008 } 1009 if (ch->dma.rfis_bus) { 1010 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1011 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1012 ch->dma.rfis_bus = 0; 1013 ch->dma.rfis = NULL; 1014 } 1015 if (ch->dma.work_bus) { 1016 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1017 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1018 ch->dma.work_bus = 0; 1019 ch->dma.work = NULL; 1020 } 1021 if (ch->dma.work_tag) { 1022 bus_dma_tag_destroy(ch->dma.work_tag); 1023 ch->dma.work_tag = NULL; 1024 } 1025 } 1026 1027 static void 1028 ahci_slotsalloc(device_t dev) 1029 { 1030 struct ahci_channel *ch = device_get_softc(dev); 1031 int i; 1032 1033 /* Alloc and setup command/dma slots */ 1034 bzero(ch->slot, sizeof(ch->slot)); 1035 for (i = 0; i < ch->numslots; i++) { 1036 struct ahci_slot *slot = &ch->slot[i]; 1037 1038 slot->ch = ch; 1039 slot->slot = i; 1040 slot->state = AHCI_SLOT_EMPTY; 1041 slot->ccb = NULL; 1042 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1043 1044 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1045 device_printf(ch->dev, "FAILURE - create data_map\n"); 1046 } 1047 } 1048 1049 static void 1050 ahci_slotsfree(device_t dev) 1051 { 1052 struct ahci_channel *ch = device_get_softc(dev); 1053 int i; 1054 1055 /* Free all dma slots */ 1056 for (i = 0; i < ch->numslots; i++) { 1057 struct ahci_slot *slot = &ch->slot[i]; 1058 1059 callout_drain(&slot->timeout); 1060 if (slot->dma.data_map) { 1061 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1062 slot->dma.data_map = NULL; 1063 } 1064 } 1065 } 1066 1067 static int 1068 ahci_phy_check_events(struct ahci_channel *ch, u_int32_t serr) 1069 { 1070 1071 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) || 1072 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) { 1073 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1074 union ccb *ccb; 1075 1076 if (bootverbose) { 1077 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 1078 device_printf(ch->dev, "CONNECT requested\n"); 1079 else 1080 device_printf(ch->dev, "DISCONNECT requested\n"); 1081 } 1082 ahci_reset(ch); 1083 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1084 return (0); 1085 if (xpt_create_path(&ccb->ccb_h.path, NULL, 1086 cam_sim_path(ch->sim), 1087 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1088 xpt_free_ccb(ccb); 1089 return (0); 1090 } 1091 xpt_rescan(ccb); 1092 return (1); 1093 } 1094 return (0); 1095 } 1096 1097 static void 1098 ahci_cpd_check_events(struct ahci_channel *ch) 1099 { 1100 u_int32_t status; 1101 union ccb *ccb; 1102 device_t dev; 1103 1104 if (ch->pm_level == 0) 1105 return; 1106 1107 status = ATA_INL(ch->r_mem, AHCI_P_CMD); 1108 if ((status & AHCI_P_CMD_CPD) == 0) 1109 return; 1110 1111 if (bootverbose) { 1112 dev = ch->dev; 1113 if (status & AHCI_P_CMD_CPS) { 1114 device_printf(dev, "COLD CONNECT requested\n"); 1115 } else 1116 device_printf(dev, "COLD DISCONNECT requested\n"); 1117 } 1118 ahci_reset(ch); 1119 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1120 return; 1121 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim), 1122 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1123 xpt_free_ccb(ccb); 1124 return; 1125 } 1126 xpt_rescan(ccb); 1127 } 1128 1129 static void 1130 ahci_notify_events(struct ahci_channel *ch, u_int32_t status) 1131 { 1132 struct cam_path *dpath; 1133 int i; 1134 1135 if (ch->caps & AHCI_CAP_SSNTF) 1136 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1137 if (bootverbose) 1138 device_printf(ch->dev, "SNTF 0x%04x\n", status); 1139 for (i = 0; i < 16; i++) { 1140 if ((status & (1 << i)) == 0) 1141 continue; 1142 if (xpt_create_path(&dpath, NULL, 1143 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1144 xpt_async(AC_SCSI_AEN, dpath, NULL); 1145 xpt_free_path(dpath); 1146 } 1147 } 1148 } 1149 1150 static void 1151 ahci_done(struct ahci_channel *ch, union ccb *ccb) 1152 { 1153 1154 mtx_assert(&ch->mtx, MA_OWNED); 1155 if ((ccb->ccb_h.func_code & XPT_FC_QUEUED) == 0 || 1156 ch->batch == 0) { 1157 xpt_done(ccb); 1158 return; 1159 } 1160 1161 STAILQ_INSERT_TAIL(&ch->doneq, &ccb->ccb_h, sim_links.stqe); 1162 } 1163 1164 static void 1165 ahci_ch_intr(void *arg) 1166 { 1167 struct ahci_channel *ch = (struct ahci_channel *)arg; 1168 uint32_t istatus; 1169 1170 /* Read interrupt statuses. */ 1171 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1172 1173 mtx_lock(&ch->mtx); 1174 ahci_ch_intr_main(ch, istatus); 1175 mtx_unlock(&ch->mtx); 1176 } 1177 1178 static void 1179 ahci_ch_intr_direct(void *arg) 1180 { 1181 struct ahci_channel *ch = (struct ahci_channel *)arg; 1182 struct ccb_hdr *ccb_h; 1183 uint32_t istatus; 1184 STAILQ_HEAD(, ccb_hdr) tmp_doneq = STAILQ_HEAD_INITIALIZER(tmp_doneq); 1185 1186 /* Read interrupt statuses. */ 1187 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1188 1189 mtx_lock(&ch->mtx); 1190 ch->batch = 1; 1191 ahci_ch_intr_main(ch, istatus); 1192 ch->batch = 0; 1193 /* 1194 * Prevent the possibility of issues caused by processing the queue 1195 * while unlocked below by moving the contents to a local queue. 1196 */ 1197 STAILQ_CONCAT(&tmp_doneq, &ch->doneq); 1198 mtx_unlock(&ch->mtx); 1199 while ((ccb_h = STAILQ_FIRST(&tmp_doneq)) != NULL) { 1200 STAILQ_REMOVE_HEAD(&tmp_doneq, sim_links.stqe); 1201 xpt_done_direct((union ccb *)ccb_h); 1202 } 1203 } 1204 1205 static void 1206 ahci_ch_pm(void *arg) 1207 { 1208 struct ahci_channel *ch = (struct ahci_channel *)arg; 1209 uint32_t work; 1210 1211 if (ch->numrslots != 0) 1212 return; 1213 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1214 if (ch->pm_level == 4) 1215 work |= AHCI_P_CMD_PARTIAL; 1216 else 1217 work |= AHCI_P_CMD_SLUMBER; 1218 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1219 } 1220 1221 static void 1222 ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus) 1223 { 1224 uint32_t cstatus, serr = 0, sntf = 0, ok, err; 1225 enum ahci_err_type et; 1226 int i, ccs, port, reset = 0; 1227 1228 /* Clear interrupt statuses. */ 1229 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1230 /* Read command statuses. */ 1231 if (ch->numtslots != 0) 1232 cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1233 else 1234 cstatus = 0; 1235 if (ch->numrslots != ch->numtslots) 1236 cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI); 1237 /* Read SNTF in one of possible ways. */ 1238 if ((istatus & AHCI_P_IX_SDB) && 1239 (ch->pm_present || ch->curr[0].atapi != 0)) { 1240 if (ch->caps & AHCI_CAP_SSNTF) 1241 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1242 else if (ch->fbs_enabled) { 1243 u_int8_t *fis = ch->dma.rfis + 0x58; 1244 1245 for (i = 0; i < 16; i++) { 1246 if (fis[1] & 0x80) { 1247 fis[1] &= 0x7f; 1248 sntf |= 1 << i; 1249 } 1250 fis += 256; 1251 } 1252 } else { 1253 u_int8_t *fis = ch->dma.rfis + 0x58; 1254 1255 if (fis[1] & 0x80) 1256 sntf = (1 << (fis[1] & 0x0f)); 1257 } 1258 } 1259 /* Process PHY events */ 1260 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1261 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1262 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1263 if (serr) { 1264 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1265 reset = ahci_phy_check_events(ch, serr); 1266 } 1267 } 1268 /* Process cold presence detection events */ 1269 if ((istatus & AHCI_P_IX_CPD) && !reset) 1270 ahci_cpd_check_events(ch); 1271 /* Process command errors */ 1272 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1273 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1274 if (ch->quirks & AHCI_Q_NOCCS) { 1275 /* 1276 * ASMedia chips sometimes report failed commands as 1277 * completed. Count all running commands as failed. 1278 */ 1279 cstatus |= ch->rslots; 1280 1281 /* They also report wrong CCS, so try to guess one. */ 1282 ccs = powerof2(cstatus) ? ffs(cstatus) - 1 : -1; 1283 } else { 1284 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & 1285 AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 1286 } 1287 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1288 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1289 // serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1290 port = -1; 1291 if (ch->fbs_enabled) { 1292 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1293 if (fbs & AHCI_P_FBS_SDE) { 1294 port = (fbs & AHCI_P_FBS_DWE) 1295 >> AHCI_P_FBS_DWE_SHIFT; 1296 } else { 1297 for (i = 0; i < 16; i++) { 1298 if (ch->numrslotspd[i] == 0) 1299 continue; 1300 if (port == -1) 1301 port = i; 1302 else if (port != i) { 1303 port = -2; 1304 break; 1305 } 1306 } 1307 } 1308 } 1309 err = ch->rslots & cstatus; 1310 } else { 1311 ccs = 0; 1312 err = 0; 1313 port = -1; 1314 } 1315 /* Complete all successful commands. */ 1316 ok = ch->rslots & ~cstatus; 1317 for (i = 0; i < ch->numslots; i++) { 1318 if ((ok >> i) & 1) 1319 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1320 } 1321 /* On error, complete the rest of commands with error statuses. */ 1322 if (err) { 1323 if (ch->frozen) { 1324 union ccb *fccb = ch->frozen; 1325 ch->frozen = NULL; 1326 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1327 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1328 xpt_freeze_devq(fccb->ccb_h.path, 1); 1329 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1330 } 1331 ahci_done(ch, fccb); 1332 } 1333 for (i = 0; i < ch->numslots; i++) { 1334 /* XXX: reqests in loading state. */ 1335 if (((err >> i) & 1) == 0) 1336 continue; 1337 if (port >= 0 && 1338 ch->slot[i].ccb->ccb_h.target_id != port) 1339 continue; 1340 if (istatus & AHCI_P_IX_TFE) { 1341 if (port != -2) { 1342 /* Task File Error */ 1343 if (ch->numtslotspd[ 1344 ch->slot[i].ccb->ccb_h.target_id] == 0) { 1345 /* Untagged operation. */ 1346 if (i == ccs) 1347 et = AHCI_ERR_TFE; 1348 else 1349 et = AHCI_ERR_INNOCENT; 1350 } else { 1351 /* Tagged operation. */ 1352 et = AHCI_ERR_NCQ; 1353 } 1354 } else { 1355 et = AHCI_ERR_TFE; 1356 ch->fatalerr = 1; 1357 } 1358 } else if (istatus & AHCI_P_IX_IF) { 1359 if (ch->numtslots == 0 && i != ccs && port != -2) 1360 et = AHCI_ERR_INNOCENT; 1361 else 1362 et = AHCI_ERR_SATA; 1363 } else 1364 et = AHCI_ERR_INVALID; 1365 ahci_end_transaction(&ch->slot[i], et); 1366 } 1367 /* 1368 * We can't reinit port if there are some other 1369 * commands active, use resume to complete them. 1370 */ 1371 if (ch->rslots != 0 && !ch->recoverycmd) 1372 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1373 } 1374 /* Process NOTIFY events */ 1375 if (sntf) 1376 ahci_notify_events(ch, sntf); 1377 } 1378 1379 /* Must be called with channel locked. */ 1380 static int 1381 ahci_check_collision(struct ahci_channel *ch, union ccb *ccb) 1382 { 1383 int t = ccb->ccb_h.target_id; 1384 1385 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1386 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1387 /* Tagged command while we have no supported tag free. */ 1388 if (((~ch->oslots) & (0xffffffff >> (32 - 1389 ch->curr[t].tags))) == 0) 1390 return (1); 1391 /* If we have FBS */ 1392 if (ch->fbs_enabled) { 1393 /* Tagged command while untagged are active. */ 1394 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1395 return (1); 1396 } else { 1397 /* Tagged command while untagged are active. */ 1398 if (ch->numrslots != 0 && ch->numtslots == 0) 1399 return (1); 1400 /* Tagged command while tagged to other target is active. */ 1401 if (ch->numtslots != 0 && 1402 ch->taggedtarget != ccb->ccb_h.target_id) 1403 return (1); 1404 } 1405 } else { 1406 /* If we have FBS */ 1407 if (ch->fbs_enabled) { 1408 /* Untagged command while tagged are active. */ 1409 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1410 return (1); 1411 } else { 1412 /* Untagged command while tagged are active. */ 1413 if (ch->numrslots != 0 && ch->numtslots != 0) 1414 return (1); 1415 } 1416 } 1417 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1418 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1419 /* Atomic command while anything active. */ 1420 if (ch->numrslots != 0) 1421 return (1); 1422 } 1423 /* We have some atomic command running. */ 1424 if (ch->aslots != 0) 1425 return (1); 1426 return (0); 1427 } 1428 1429 /* Must be called with channel locked. */ 1430 static void 1431 ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb) 1432 { 1433 struct ahci_slot *slot; 1434 int tag, tags; 1435 1436 /* Choose empty slot. */ 1437 tags = ch->numslots; 1438 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1439 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1440 tags = ch->curr[ccb->ccb_h.target_id].tags; 1441 if (ch->lastslot + 1 < tags) 1442 tag = ffs(~(ch->oslots >> (ch->lastslot + 1))); 1443 else 1444 tag = 0; 1445 if (tag == 0 || tag + ch->lastslot >= tags) 1446 tag = ffs(~ch->oslots) - 1; 1447 else 1448 tag += ch->lastslot; 1449 ch->lastslot = tag; 1450 /* Occupy chosen slot. */ 1451 slot = &ch->slot[tag]; 1452 slot->ccb = ccb; 1453 /* Stop PM timer. */ 1454 if (ch->numrslots == 0 && ch->pm_level > 3) 1455 callout_stop(&ch->pm_timer); 1456 /* Update channel stats. */ 1457 ch->oslots |= (1 << tag); 1458 ch->numrslots++; 1459 ch->numrslotspd[ccb->ccb_h.target_id]++; 1460 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1461 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1462 ch->numtslots++; 1463 ch->numtslotspd[ccb->ccb_h.target_id]++; 1464 ch->taggedtarget = ccb->ccb_h.target_id; 1465 } 1466 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1467 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1468 ch->aslots |= (1 << tag); 1469 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1470 slot->state = AHCI_SLOT_LOADING; 1471 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb, 1472 ahci_dmasetprd, slot, 0); 1473 } else { 1474 slot->dma.nsegs = 0; 1475 ahci_execute_transaction(slot); 1476 } 1477 } 1478 1479 /* Locked by busdma engine. */ 1480 static void 1481 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1482 { 1483 struct ahci_slot *slot = arg; 1484 struct ahci_channel *ch = slot->ch; 1485 struct ahci_cmd_tab *ctp; 1486 struct ahci_dma_prd *prd; 1487 int i; 1488 1489 if (error) { 1490 device_printf(ch->dev, "DMA load error\n"); 1491 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1492 return; 1493 } 1494 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1495 /* Get a piece of the workspace for this request */ 1496 ctp = (struct ahci_cmd_tab *) 1497 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1498 /* Fill S/G table */ 1499 prd = &ctp->prd_tab[0]; 1500 for (i = 0; i < nsegs; i++) { 1501 prd[i].dba = htole64(segs[i].ds_addr); 1502 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1503 } 1504 slot->dma.nsegs = nsegs; 1505 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1506 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1507 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1508 ahci_execute_transaction(slot); 1509 } 1510 1511 /* Must be called with channel locked. */ 1512 static void 1513 ahci_execute_transaction(struct ahci_slot *slot) 1514 { 1515 struct ahci_channel *ch = slot->ch; 1516 struct ahci_cmd_tab *ctp; 1517 struct ahci_cmd_list *clp; 1518 union ccb *ccb = slot->ccb; 1519 int port = ccb->ccb_h.target_id & 0x0f; 1520 int fis_size, i, softreset; 1521 uint8_t *fis = ch->dma.rfis + 0x40; 1522 uint8_t val; 1523 1524 /* Get a piece of the workspace for this request */ 1525 ctp = (struct ahci_cmd_tab *) 1526 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1527 /* Setup the FIS for this request */ 1528 if (!(fis_size = ahci_setup_fis(ch, ctp, ccb, slot->slot))) { 1529 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1530 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1531 return; 1532 } 1533 /* Setup the command list entry */ 1534 clp = (struct ahci_cmd_list *) 1535 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1536 clp->cmd_flags = htole16( 1537 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1538 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1539 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1540 (fis_size / sizeof(u_int32_t)) | 1541 (port << 12)); 1542 clp->prd_length = htole16(slot->dma.nsegs); 1543 /* Special handling for Soft Reset command. */ 1544 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1545 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1546 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1547 softreset = 1; 1548 /* Kick controller into sane state */ 1549 ahci_stop(ch); 1550 ahci_clo(ch); 1551 ahci_start(ch, 0); 1552 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1553 } else { 1554 softreset = 2; 1555 /* Prepare FIS receive area for check. */ 1556 for (i = 0; i < 20; i++) 1557 fis[i] = 0xff; 1558 } 1559 } else 1560 softreset = 0; 1561 clp->bytecount = 0; 1562 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1563 (AHCI_CT_SIZE * slot->slot)); 1564 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1565 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1566 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1567 BUS_DMASYNC_PREREAD); 1568 /* Set ACTIVE bit for NCQ commands. */ 1569 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1570 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1571 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1572 } 1573 /* If FBS is enabled, set PMP port. */ 1574 if (ch->fbs_enabled) { 1575 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1576 (port << AHCI_P_FBS_DEV_SHIFT)); 1577 } 1578 /* Issue command to the controller. */ 1579 slot->state = AHCI_SLOT_RUNNING; 1580 ch->rslots |= (1 << slot->slot); 1581 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1582 /* Device reset commands doesn't interrupt. Poll them. */ 1583 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1584 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) { 1585 int count, timeout = ccb->ccb_h.timeout * 100; 1586 enum ahci_err_type et = AHCI_ERR_NONE; 1587 1588 for (count = 0; count < timeout; count++) { 1589 DELAY(10); 1590 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1591 break; 1592 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) && 1593 softreset != 1) { 1594 #if 0 1595 device_printf(ch->dev, 1596 "Poll error on slot %d, TFD: %04x\n", 1597 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1598 #endif 1599 et = AHCI_ERR_TFE; 1600 break; 1601 } 1602 /* Workaround for ATI SB600/SB700 chipsets. */ 1603 if (ccb->ccb_h.target_id == 15 && 1604 (ch->quirks & AHCI_Q_ATI_PMP_BUG) && 1605 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1606 et = AHCI_ERR_TIMEOUT; 1607 break; 1608 } 1609 } 1610 1611 /* 1612 * Some Marvell controllers require additional time 1613 * after soft reset to work properly. Setup delay 1614 * to 50ms after soft reset. 1615 */ 1616 if (ch->quirks & AHCI_Q_MRVL_SR_DEL) 1617 DELAY(50000); 1618 1619 /* 1620 * Marvell HBAs with non-RAID firmware do not wait for 1621 * readiness after soft reset, so we have to wait here. 1622 * Marvell RAIDs do not have this problem, but instead 1623 * sometimes forget to update FIS receive area, breaking 1624 * this wait. 1625 */ 1626 if ((ch->quirks & AHCI_Q_NOBSYRES) == 0 && 1627 (ch->quirks & AHCI_Q_ATI_PMP_BUG) == 0 && 1628 softreset == 2 && et == AHCI_ERR_NONE) { 1629 for ( ; count < timeout; count++) { 1630 bus_dmamap_sync(ch->dma.rfis_tag, 1631 ch->dma.rfis_map, BUS_DMASYNC_POSTREAD); 1632 val = fis[2]; 1633 bus_dmamap_sync(ch->dma.rfis_tag, 1634 ch->dma.rfis_map, BUS_DMASYNC_PREREAD); 1635 if ((val & ATA_S_BUSY) == 0) 1636 break; 1637 DELAY(10); 1638 } 1639 } 1640 1641 if (timeout && (count >= timeout)) { 1642 device_printf(ch->dev, "Poll timeout on slot %d port %d\n", 1643 slot->slot, port); 1644 device_printf(ch->dev, "is %08x cs %08x ss %08x " 1645 "rs %08x tfd %02x serr %08x cmd %08x\n", 1646 ATA_INL(ch->r_mem, AHCI_P_IS), 1647 ATA_INL(ch->r_mem, AHCI_P_CI), 1648 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1649 ATA_INL(ch->r_mem, AHCI_P_TFD), 1650 ATA_INL(ch->r_mem, AHCI_P_SERR), 1651 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1652 et = AHCI_ERR_TIMEOUT; 1653 } 1654 1655 /* Kick controller into sane state and enable FBS. */ 1656 if (softreset == 2) 1657 ch->eslots |= (1 << slot->slot); 1658 ahci_end_transaction(slot, et); 1659 return; 1660 } 1661 /* Start command execution timeout */ 1662 callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout / 2, 1663 0, (timeout_t*)ahci_timeout, slot, 0); 1664 return; 1665 } 1666 1667 /* Must be called with channel locked. */ 1668 static void 1669 ahci_process_timeout(struct ahci_channel *ch) 1670 { 1671 int i; 1672 1673 mtx_assert(&ch->mtx, MA_OWNED); 1674 /* Handle the rest of commands. */ 1675 for (i = 0; i < ch->numslots; i++) { 1676 /* Do we have a running request on slot? */ 1677 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1678 continue; 1679 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 1680 } 1681 } 1682 1683 /* Must be called with channel locked. */ 1684 static void 1685 ahci_rearm_timeout(struct ahci_channel *ch) 1686 { 1687 int i; 1688 1689 mtx_assert(&ch->mtx, MA_OWNED); 1690 for (i = 0; i < ch->numslots; i++) { 1691 struct ahci_slot *slot = &ch->slot[i]; 1692 1693 /* Do we have a running request on slot? */ 1694 if (slot->state < AHCI_SLOT_RUNNING) 1695 continue; 1696 if ((ch->toslots & (1 << i)) == 0) 1697 continue; 1698 callout_reset_sbt(&slot->timeout, 1699 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0, 1700 (timeout_t*)ahci_timeout, slot, 0); 1701 } 1702 } 1703 1704 /* Locked by callout mechanism. */ 1705 static void 1706 ahci_timeout(struct ahci_slot *slot) 1707 { 1708 struct ahci_channel *ch = slot->ch; 1709 device_t dev = ch->dev; 1710 uint32_t sstatus; 1711 int ccs; 1712 int i; 1713 1714 /* Check for stale timeout. */ 1715 if (slot->state < AHCI_SLOT_RUNNING) 1716 return; 1717 1718 /* Check if slot was not being executed last time we checked. */ 1719 if (slot->state < AHCI_SLOT_EXECUTING) { 1720 /* Check if slot started executing. */ 1721 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1722 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1723 >> AHCI_P_CMD_CCS_SHIFT; 1724 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 1725 ch->fbs_enabled || ch->wrongccs) 1726 slot->state = AHCI_SLOT_EXECUTING; 1727 else if ((ch->rslots & (1 << ccs)) == 0) { 1728 ch->wrongccs = 1; 1729 slot->state = AHCI_SLOT_EXECUTING; 1730 } 1731 1732 callout_reset_sbt(&slot->timeout, 1733 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0, 1734 (timeout_t*)ahci_timeout, slot, 0); 1735 return; 1736 } 1737 1738 device_printf(dev, "Timeout on slot %d port %d\n", 1739 slot->slot, slot->ccb->ccb_h.target_id & 0x0f); 1740 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x " 1741 "serr %08x cmd %08x\n", 1742 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 1743 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1744 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR), 1745 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1746 1747 /* Handle frozen command. */ 1748 if (ch->frozen) { 1749 union ccb *fccb = ch->frozen; 1750 ch->frozen = NULL; 1751 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1752 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1753 xpt_freeze_devq(fccb->ccb_h.path, 1); 1754 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1755 } 1756 ahci_done(ch, fccb); 1757 } 1758 if (!ch->fbs_enabled && !ch->wrongccs) { 1759 /* Without FBS we know real timeout source. */ 1760 ch->fatalerr = 1; 1761 /* Handle command with timeout. */ 1762 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 1763 /* Handle the rest of commands. */ 1764 for (i = 0; i < ch->numslots; i++) { 1765 /* Do we have a running request on slot? */ 1766 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1767 continue; 1768 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1769 } 1770 } else { 1771 /* With FBS we wait for other commands timeout and pray. */ 1772 if (ch->toslots == 0) 1773 xpt_freeze_simq(ch->sim, 1); 1774 ch->toslots |= (1 << slot->slot); 1775 if ((ch->rslots & ~ch->toslots) == 0) 1776 ahci_process_timeout(ch); 1777 else 1778 device_printf(dev, " ... waiting for slots %08x\n", 1779 ch->rslots & ~ch->toslots); 1780 } 1781 } 1782 1783 /* Must be called with channel locked. */ 1784 static void 1785 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 1786 { 1787 struct ahci_channel *ch = slot->ch; 1788 union ccb *ccb = slot->ccb; 1789 struct ahci_cmd_list *clp; 1790 int lastto; 1791 uint32_t sig; 1792 1793 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1794 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1795 clp = (struct ahci_cmd_list *) 1796 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1797 /* Read result registers to the result struct 1798 * May be incorrect if several commands finished same time, 1799 * so read only when sure or have to. 1800 */ 1801 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1802 struct ata_res *res = &ccb->ataio.res; 1803 1804 if ((et == AHCI_ERR_TFE) || 1805 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1806 u_int8_t *fis = ch->dma.rfis + 0x40; 1807 1808 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1809 BUS_DMASYNC_POSTREAD); 1810 if (ch->fbs_enabled) { 1811 fis += ccb->ccb_h.target_id * 256; 1812 res->status = fis[2]; 1813 res->error = fis[3]; 1814 } else { 1815 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 1816 1817 res->status = tfd; 1818 res->error = tfd >> 8; 1819 } 1820 res->lba_low = fis[4]; 1821 res->lba_mid = fis[5]; 1822 res->lba_high = fis[6]; 1823 res->device = fis[7]; 1824 res->lba_low_exp = fis[8]; 1825 res->lba_mid_exp = fis[9]; 1826 res->lba_high_exp = fis[10]; 1827 res->sector_count = fis[12]; 1828 res->sector_count_exp = fis[13]; 1829 1830 /* 1831 * Some weird controllers do not return signature in 1832 * FIS receive area. Read it from PxSIG register. 1833 */ 1834 if ((ch->quirks & AHCI_Q_ALTSIG) && 1835 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1836 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 1837 sig = ATA_INL(ch->r_mem, AHCI_P_SIG); 1838 res->lba_high = sig >> 24; 1839 res->lba_mid = sig >> 16; 1840 res->lba_low = sig >> 8; 1841 res->sector_count = sig; 1842 } 1843 } else 1844 bzero(res, sizeof(*res)); 1845 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 1846 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 1847 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 1848 ccb->ataio.resid = 1849 ccb->ataio.dxfer_len - le32toh(clp->bytecount); 1850 } 1851 } else { 1852 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 1853 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 1854 ccb->csio.resid = 1855 ccb->csio.dxfer_len - le32toh(clp->bytecount); 1856 } 1857 } 1858 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1859 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1860 (ccb->ccb_h.flags & CAM_DIR_IN) ? 1861 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1862 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 1863 } 1864 if (et != AHCI_ERR_NONE) 1865 ch->eslots |= (1 << slot->slot); 1866 /* In case of error, freeze device for proper recovery. */ 1867 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) && 1868 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 1869 xpt_freeze_devq(ccb->ccb_h.path, 1); 1870 ccb->ccb_h.status |= CAM_DEV_QFRZN; 1871 } 1872 /* Set proper result status. */ 1873 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1874 switch (et) { 1875 case AHCI_ERR_NONE: 1876 ccb->ccb_h.status |= CAM_REQ_CMP; 1877 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 1878 ccb->csio.scsi_status = SCSI_STATUS_OK; 1879 break; 1880 case AHCI_ERR_INVALID: 1881 ch->fatalerr = 1; 1882 ccb->ccb_h.status |= CAM_REQ_INVALID; 1883 break; 1884 case AHCI_ERR_INNOCENT: 1885 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 1886 break; 1887 case AHCI_ERR_TFE: 1888 case AHCI_ERR_NCQ: 1889 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1890 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1891 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1892 } else { 1893 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 1894 } 1895 break; 1896 case AHCI_ERR_SATA: 1897 ch->fatalerr = 1; 1898 if (!ch->recoverycmd) { 1899 xpt_freeze_simq(ch->sim, 1); 1900 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1901 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1902 } 1903 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 1904 break; 1905 case AHCI_ERR_TIMEOUT: 1906 if (!ch->recoverycmd) { 1907 xpt_freeze_simq(ch->sim, 1); 1908 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1909 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1910 } 1911 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1912 break; 1913 default: 1914 ch->fatalerr = 1; 1915 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 1916 } 1917 /* Free slot. */ 1918 ch->oslots &= ~(1 << slot->slot); 1919 ch->rslots &= ~(1 << slot->slot); 1920 ch->aslots &= ~(1 << slot->slot); 1921 slot->state = AHCI_SLOT_EMPTY; 1922 slot->ccb = NULL; 1923 /* Update channel stats. */ 1924 ch->numrslots--; 1925 ch->numrslotspd[ccb->ccb_h.target_id]--; 1926 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1927 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1928 ch->numtslots--; 1929 ch->numtslotspd[ccb->ccb_h.target_id]--; 1930 } 1931 /* Cancel timeout state if request completed normally. */ 1932 if (et != AHCI_ERR_TIMEOUT) { 1933 lastto = (ch->toslots == (1 << slot->slot)); 1934 ch->toslots &= ~(1 << slot->slot); 1935 if (lastto) 1936 xpt_release_simq(ch->sim, TRUE); 1937 } 1938 /* If it was first request of reset sequence and there is no error, 1939 * proceed to second request. */ 1940 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1941 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1942 (ccb->ataio.cmd.control & ATA_A_RESET) && 1943 et == AHCI_ERR_NONE) { 1944 ccb->ataio.cmd.control &= ~ATA_A_RESET; 1945 ahci_begin_transaction(ch, ccb); 1946 return; 1947 } 1948 /* If it was our READ LOG command - process it. */ 1949 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 1950 ahci_process_read_log(ch, ccb); 1951 /* If it was our REQUEST SENSE command - process it. */ 1952 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 1953 ahci_process_request_sense(ch, ccb); 1954 /* If it was NCQ or ATAPI command error, put result on hold. */ 1955 } else if (et == AHCI_ERR_NCQ || 1956 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 1957 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 1958 ch->hold[slot->slot] = ccb; 1959 ch->numhslots++; 1960 } else 1961 ahci_done(ch, ccb); 1962 /* If we have no other active commands, ... */ 1963 if (ch->rslots == 0) { 1964 /* if there was fatal error - reset port. */ 1965 if (ch->toslots != 0 || ch->fatalerr) { 1966 ahci_reset(ch); 1967 } else { 1968 /* if we have slots in error, we can reinit port. */ 1969 if (ch->eslots != 0) { 1970 ahci_stop(ch); 1971 ahci_clo(ch); 1972 ahci_start(ch, 1); 1973 } 1974 /* if there commands on hold, we can do READ LOG. */ 1975 if (!ch->recoverycmd && ch->numhslots) 1976 ahci_issue_recovery(ch); 1977 } 1978 /* If all the rest of commands are in timeout - give them chance. */ 1979 } else if ((ch->rslots & ~ch->toslots) == 0 && 1980 et != AHCI_ERR_TIMEOUT) 1981 ahci_rearm_timeout(ch); 1982 /* Unfreeze frozen command. */ 1983 if (ch->frozen && !ahci_check_collision(ch, ch->frozen)) { 1984 union ccb *fccb = ch->frozen; 1985 ch->frozen = NULL; 1986 ahci_begin_transaction(ch, fccb); 1987 xpt_release_simq(ch->sim, TRUE); 1988 } 1989 /* Start PM timer. */ 1990 if (ch->numrslots == 0 && ch->pm_level > 3 && 1991 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 1992 callout_schedule(&ch->pm_timer, 1993 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 1994 } 1995 } 1996 1997 static void 1998 ahci_issue_recovery(struct ahci_channel *ch) 1999 { 2000 union ccb *ccb; 2001 struct ccb_ataio *ataio; 2002 struct ccb_scsiio *csio; 2003 int i; 2004 2005 /* Find some held command. */ 2006 for (i = 0; i < ch->numslots; i++) { 2007 if (ch->hold[i]) 2008 break; 2009 } 2010 ccb = xpt_alloc_ccb_nowait(); 2011 if (ccb == NULL) { 2012 device_printf(ch->dev, "Unable to allocate recovery command\n"); 2013 completeall: 2014 /* We can't do anything -- complete held commands. */ 2015 for (i = 0; i < ch->numslots; i++) { 2016 if (ch->hold[i] == NULL) 2017 continue; 2018 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2019 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 2020 ahci_done(ch, ch->hold[i]); 2021 ch->hold[i] = NULL; 2022 ch->numhslots--; 2023 } 2024 ahci_reset(ch); 2025 return; 2026 } 2027 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 2028 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2029 /* READ LOG */ 2030 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 2031 ccb->ccb_h.func_code = XPT_ATA_IO; 2032 ccb->ccb_h.flags = CAM_DIR_IN; 2033 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2034 ataio = &ccb->ataio; 2035 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 2036 if (ataio->data_ptr == NULL) { 2037 xpt_free_ccb(ccb); 2038 device_printf(ch->dev, 2039 "Unable to allocate memory for READ LOG command\n"); 2040 goto completeall; 2041 } 2042 ataio->dxfer_len = 512; 2043 bzero(&ataio->cmd, sizeof(ataio->cmd)); 2044 ataio->cmd.flags = CAM_ATAIO_48BIT; 2045 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 2046 ataio->cmd.sector_count = 1; 2047 ataio->cmd.sector_count_exp = 0; 2048 ataio->cmd.lba_low = 0x10; 2049 ataio->cmd.lba_mid = 0; 2050 ataio->cmd.lba_mid_exp = 0; 2051 } else { 2052 /* REQUEST SENSE */ 2053 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 2054 ccb->ccb_h.recovery_slot = i; 2055 ccb->ccb_h.func_code = XPT_SCSI_IO; 2056 ccb->ccb_h.flags = CAM_DIR_IN; 2057 ccb->ccb_h.status = 0; 2058 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2059 csio = &ccb->csio; 2060 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 2061 csio->dxfer_len = ch->hold[i]->csio.sense_len; 2062 csio->cdb_len = 6; 2063 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 2064 csio->cdb_io.cdb_bytes[0] = 0x03; 2065 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 2066 } 2067 /* Freeze SIM while doing recovery. */ 2068 ch->recoverycmd = 1; 2069 xpt_freeze_simq(ch->sim, 1); 2070 ahci_begin_transaction(ch, ccb); 2071 } 2072 2073 static void 2074 ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb) 2075 { 2076 uint8_t *data; 2077 struct ata_res *res; 2078 int i; 2079 2080 ch->recoverycmd = 0; 2081 2082 data = ccb->ataio.data_ptr; 2083 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2084 (data[0] & 0x80) == 0) { 2085 for (i = 0; i < ch->numslots; i++) { 2086 if (!ch->hold[i]) 2087 continue; 2088 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2089 continue; 2090 if ((data[0] & 0x1F) == i) { 2091 res = &ch->hold[i]->ataio.res; 2092 res->status = data[2]; 2093 res->error = data[3]; 2094 res->lba_low = data[4]; 2095 res->lba_mid = data[5]; 2096 res->lba_high = data[6]; 2097 res->device = data[7]; 2098 res->lba_low_exp = data[8]; 2099 res->lba_mid_exp = data[9]; 2100 res->lba_high_exp = data[10]; 2101 res->sector_count = data[12]; 2102 res->sector_count_exp = data[13]; 2103 } else { 2104 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2105 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2106 } 2107 ahci_done(ch, ch->hold[i]); 2108 ch->hold[i] = NULL; 2109 ch->numhslots--; 2110 } 2111 } else { 2112 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2113 device_printf(ch->dev, "Error while READ LOG EXT\n"); 2114 else if ((data[0] & 0x80) == 0) { 2115 device_printf(ch->dev, "Non-queued command error in READ LOG EXT\n"); 2116 } 2117 for (i = 0; i < ch->numslots; i++) { 2118 if (!ch->hold[i]) 2119 continue; 2120 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2121 continue; 2122 ahci_done(ch, ch->hold[i]); 2123 ch->hold[i] = NULL; 2124 ch->numhslots--; 2125 } 2126 } 2127 free(ccb->ataio.data_ptr, M_AHCI); 2128 xpt_free_ccb(ccb); 2129 xpt_release_simq(ch->sim, TRUE); 2130 } 2131 2132 static void 2133 ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb) 2134 { 2135 int i; 2136 2137 ch->recoverycmd = 0; 2138 2139 i = ccb->ccb_h.recovery_slot; 2140 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 2141 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 2142 } else { 2143 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2144 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 2145 } 2146 ahci_done(ch, ch->hold[i]); 2147 ch->hold[i] = NULL; 2148 ch->numhslots--; 2149 xpt_free_ccb(ccb); 2150 xpt_release_simq(ch->sim, TRUE); 2151 } 2152 2153 static void 2154 ahci_start(struct ahci_channel *ch, int fbs) 2155 { 2156 u_int32_t cmd; 2157 2158 /* Run the channel start callback, if any. */ 2159 if (ch->start) 2160 ch->start(ch); 2161 2162 /* Clear SATA error register */ 2163 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2164 /* Clear any interrupts pending on this channel */ 2165 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2166 /* Configure FIS-based switching if supported. */ 2167 if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2168 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2169 ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2170 ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2171 } 2172 /* Start operations on this channel */ 2173 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2174 cmd &= ~AHCI_P_CMD_PMA; 2175 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2176 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2177 } 2178 2179 static void 2180 ahci_stop(struct ahci_channel *ch) 2181 { 2182 u_int32_t cmd; 2183 int timeout; 2184 2185 /* Kill all activity on this channel */ 2186 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2187 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2188 /* Wait for activity stop. */ 2189 timeout = 0; 2190 do { 2191 DELAY(10); 2192 if (timeout++ > 50000) { 2193 device_printf(ch->dev, "stopping AHCI engine failed\n"); 2194 break; 2195 } 2196 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2197 ch->eslots = 0; 2198 } 2199 2200 static void 2201 ahci_clo(struct ahci_channel *ch) 2202 { 2203 u_int32_t cmd; 2204 int timeout; 2205 2206 /* Issue Command List Override if supported */ 2207 if (ch->caps & AHCI_CAP_SCLO) { 2208 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2209 cmd |= AHCI_P_CMD_CLO; 2210 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2211 timeout = 0; 2212 do { 2213 DELAY(10); 2214 if (timeout++ > 50000) { 2215 device_printf(ch->dev, "executing CLO failed\n"); 2216 break; 2217 } 2218 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2219 } 2220 } 2221 2222 static void 2223 ahci_stop_fr(struct ahci_channel *ch) 2224 { 2225 u_int32_t cmd; 2226 int timeout; 2227 2228 /* Kill all FIS reception on this channel */ 2229 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2230 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2231 /* Wait for FIS reception stop. */ 2232 timeout = 0; 2233 do { 2234 DELAY(10); 2235 if (timeout++ > 50000) { 2236 device_printf(ch->dev, "stopping AHCI FR engine failed\n"); 2237 break; 2238 } 2239 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2240 } 2241 2242 static void 2243 ahci_start_fr(struct ahci_channel *ch) 2244 { 2245 u_int32_t cmd; 2246 2247 /* Start FIS reception on this channel */ 2248 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2249 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2250 } 2251 2252 static int 2253 ahci_wait_ready(struct ahci_channel *ch, int t, int t0) 2254 { 2255 int timeout = 0; 2256 uint32_t val; 2257 2258 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2259 (ATA_S_BUSY | ATA_S_DRQ)) { 2260 if (timeout > t) { 2261 if (t != 0) { 2262 device_printf(ch->dev, 2263 "AHCI reset: device not ready after %dms " 2264 "(tfd = %08x)\n", 2265 MAX(t, 0) + t0, val); 2266 } 2267 return (EBUSY); 2268 } 2269 DELAY(1000); 2270 timeout++; 2271 } 2272 if (bootverbose) 2273 device_printf(ch->dev, "AHCI reset: device ready after %dms\n", 2274 timeout + t0); 2275 return (0); 2276 } 2277 2278 static void 2279 ahci_reset_to(void *arg) 2280 { 2281 struct ahci_channel *ch = arg; 2282 2283 if (ch->resetting == 0) 2284 return; 2285 ch->resetting--; 2286 if (ahci_wait_ready(ch, ch->resetting == 0 ? -1 : 0, 2287 (310 - ch->resetting) * 100) == 0) { 2288 ch->resetting = 0; 2289 ahci_start(ch, 1); 2290 xpt_release_simq(ch->sim, TRUE); 2291 return; 2292 } 2293 if (ch->resetting == 0) { 2294 ahci_clo(ch); 2295 ahci_start(ch, 1); 2296 xpt_release_simq(ch->sim, TRUE); 2297 return; 2298 } 2299 callout_schedule(&ch->reset_timer, hz / 10); 2300 } 2301 2302 static void 2303 ahci_reset(struct ahci_channel *ch) 2304 { 2305 struct ahci_controller *ctlr = device_get_softc(device_get_parent(ch->dev)); 2306 int i; 2307 2308 xpt_freeze_simq(ch->sim, 1); 2309 if (bootverbose) 2310 device_printf(ch->dev, "AHCI reset...\n"); 2311 /* Forget about previous reset. */ 2312 if (ch->resetting) { 2313 ch->resetting = 0; 2314 callout_stop(&ch->reset_timer); 2315 xpt_release_simq(ch->sim, TRUE); 2316 } 2317 /* Requeue freezed command. */ 2318 if (ch->frozen) { 2319 union ccb *fccb = ch->frozen; 2320 ch->frozen = NULL; 2321 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2322 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2323 xpt_freeze_devq(fccb->ccb_h.path, 1); 2324 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2325 } 2326 ahci_done(ch, fccb); 2327 } 2328 /* Kill the engine and requeue all running commands. */ 2329 ahci_stop(ch); 2330 for (i = 0; i < ch->numslots; i++) { 2331 /* Do we have a running request on slot? */ 2332 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2333 continue; 2334 /* XXX; Commands in loading state. */ 2335 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2336 } 2337 for (i = 0; i < ch->numslots; i++) { 2338 if (!ch->hold[i]) 2339 continue; 2340 ahci_done(ch, ch->hold[i]); 2341 ch->hold[i] = NULL; 2342 ch->numhslots--; 2343 } 2344 if (ch->toslots != 0) 2345 xpt_release_simq(ch->sim, TRUE); 2346 ch->eslots = 0; 2347 ch->toslots = 0; 2348 ch->wrongccs = 0; 2349 ch->fatalerr = 0; 2350 /* Tell the XPT about the event */ 2351 xpt_async(AC_BUS_RESET, ch->path, NULL); 2352 /* Disable port interrupts */ 2353 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2354 /* Reset and reconnect PHY, */ 2355 if (!ahci_sata_phy_reset(ch)) { 2356 if (bootverbose) 2357 device_printf(ch->dev, 2358 "AHCI reset: device not found\n"); 2359 ch->devices = 0; 2360 /* Enable wanted port interrupts */ 2361 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2362 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2363 AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2364 xpt_release_simq(ch->sim, TRUE); 2365 return; 2366 } 2367 if (bootverbose) 2368 device_printf(ch->dev, "AHCI reset: device found\n"); 2369 /* Wait for clearing busy status. */ 2370 if (ahci_wait_ready(ch, dumping ? 31000 : 0, 0)) { 2371 if (dumping) 2372 ahci_clo(ch); 2373 else 2374 ch->resetting = 310; 2375 } 2376 ch->devices = 1; 2377 /* Enable wanted port interrupts */ 2378 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2379 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2380 AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2381 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2382 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC | 2383 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2384 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2385 if (ch->resetting) 2386 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, ch); 2387 else { 2388 ahci_start(ch, 1); 2389 xpt_release_simq(ch->sim, TRUE); 2390 } 2391 } 2392 2393 static int 2394 ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2395 { 2396 u_int8_t *fis = &ctp->cfis[0]; 2397 2398 bzero(fis, 20); 2399 fis[0] = 0x27; /* host to device */ 2400 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2401 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2402 fis[1] |= 0x80; 2403 fis[2] = ATA_PACKET_CMD; 2404 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2405 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2406 fis[3] = ATA_F_DMA; 2407 else { 2408 fis[5] = ccb->csio.dxfer_len; 2409 fis[6] = ccb->csio.dxfer_len >> 8; 2410 } 2411 fis[7] = ATA_D_LBA; 2412 fis[15] = ATA_A_4BIT; 2413 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2414 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2415 ctp->acmd, ccb->csio.cdb_len); 2416 bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len); 2417 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2418 fis[1] |= 0x80; 2419 fis[2] = ccb->ataio.cmd.command; 2420 fis[3] = ccb->ataio.cmd.features; 2421 fis[4] = ccb->ataio.cmd.lba_low; 2422 fis[5] = ccb->ataio.cmd.lba_mid; 2423 fis[6] = ccb->ataio.cmd.lba_high; 2424 fis[7] = ccb->ataio.cmd.device; 2425 fis[8] = ccb->ataio.cmd.lba_low_exp; 2426 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2427 fis[10] = ccb->ataio.cmd.lba_high_exp; 2428 fis[11] = ccb->ataio.cmd.features_exp; 2429 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2430 fis[12] = tag << 3; 2431 } else { 2432 fis[12] = ccb->ataio.cmd.sector_count; 2433 } 2434 fis[13] = ccb->ataio.cmd.sector_count_exp; 2435 fis[15] = ATA_A_4BIT; 2436 } else { 2437 fis[15] = ccb->ataio.cmd.control; 2438 } 2439 if (ccb->ataio.ata_flags & ATA_FLAG_AUX) { 2440 fis[16] = ccb->ataio.aux & 0xff; 2441 fis[17] = (ccb->ataio.aux >> 8) & 0xff; 2442 fis[18] = (ccb->ataio.aux >> 16) & 0xff; 2443 fis[19] = (ccb->ataio.aux >> 24) & 0xff; 2444 } 2445 return (20); 2446 } 2447 2448 static int 2449 ahci_sata_connect(struct ahci_channel *ch) 2450 { 2451 u_int32_t status; 2452 int timeout, found = 0; 2453 2454 /* Wait up to 100ms for "connect well" */ 2455 for (timeout = 0; timeout < 1000 ; timeout++) { 2456 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2457 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 2458 found = 1; 2459 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2460 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2461 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2462 break; 2463 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2464 if (bootverbose) { 2465 device_printf(ch->dev, "SATA offline status=%08x\n", 2466 status); 2467 } 2468 return (0); 2469 } 2470 if (found == 0 && timeout >= 100) 2471 break; 2472 DELAY(100); 2473 } 2474 if (timeout >= 1000 || !found) { 2475 if (bootverbose) { 2476 device_printf(ch->dev, 2477 "SATA connect timeout time=%dus status=%08x\n", 2478 timeout * 100, status); 2479 } 2480 return (0); 2481 } 2482 if (bootverbose) { 2483 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n", 2484 timeout * 100, status); 2485 } 2486 /* Clear SATA error register */ 2487 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2488 return (1); 2489 } 2490 2491 static int 2492 ahci_sata_phy_reset(struct ahci_channel *ch) 2493 { 2494 int sata_rev; 2495 uint32_t val; 2496 2497 if (ch->listening) { 2498 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2499 val |= AHCI_P_CMD_SUD; 2500 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2501 ch->listening = 0; 2502 } 2503 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2504 if (sata_rev == 1) 2505 val = ATA_SC_SPD_SPEED_GEN1; 2506 else if (sata_rev == 2) 2507 val = ATA_SC_SPD_SPEED_GEN2; 2508 else if (sata_rev == 3) 2509 val = ATA_SC_SPD_SPEED_GEN3; 2510 else 2511 val = 0; 2512 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2513 ATA_SC_DET_RESET | val | 2514 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2515 DELAY(1000); 2516 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2517 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2518 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2519 if (!ahci_sata_connect(ch)) { 2520 if (ch->caps & AHCI_CAP_SSS) { 2521 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2522 val &= ~AHCI_P_CMD_SUD; 2523 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2524 ch->listening = 1; 2525 } else if (ch->pm_level > 0) 2526 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2527 return (0); 2528 } 2529 return (1); 2530 } 2531 2532 static int 2533 ahci_check_ids(struct ahci_channel *ch, union ccb *ccb) 2534 { 2535 2536 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) { 2537 ccb->ccb_h.status = CAM_TID_INVALID; 2538 ahci_done(ch, ccb); 2539 return (-1); 2540 } 2541 if (ccb->ccb_h.target_lun != 0) { 2542 ccb->ccb_h.status = CAM_LUN_INVALID; 2543 ahci_done(ch, ccb); 2544 return (-1); 2545 } 2546 return (0); 2547 } 2548 2549 static void 2550 ahciaction(struct cam_sim *sim, union ccb *ccb) 2551 { 2552 struct ahci_channel *ch; 2553 2554 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2555 ccb->ccb_h.func_code)); 2556 2557 ch = (struct ahci_channel *)cam_sim_softc(sim); 2558 switch (ccb->ccb_h.func_code) { 2559 /* Common cases first */ 2560 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2561 case XPT_SCSI_IO: 2562 if (ahci_check_ids(ch, ccb)) 2563 return; 2564 if (ch->devices == 0 || 2565 (ch->pm_present == 0 && 2566 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2567 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2568 break; 2569 } 2570 ccb->ccb_h.recovery_type = RECOVERY_NONE; 2571 /* Check for command collision. */ 2572 if (ahci_check_collision(ch, ccb)) { 2573 /* Freeze command. */ 2574 ch->frozen = ccb; 2575 /* We have only one frozen slot, so freeze simq also. */ 2576 xpt_freeze_simq(ch->sim, 1); 2577 return; 2578 } 2579 ahci_begin_transaction(ch, ccb); 2580 return; 2581 case XPT_ABORT: /* Abort the specified CCB */ 2582 /* XXX Implement */ 2583 ccb->ccb_h.status = CAM_REQ_INVALID; 2584 break; 2585 case XPT_SET_TRAN_SETTINGS: 2586 { 2587 struct ccb_trans_settings *cts = &ccb->cts; 2588 struct ahci_device *d; 2589 2590 if (ahci_check_ids(ch, ccb)) 2591 return; 2592 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2593 d = &ch->curr[ccb->ccb_h.target_id]; 2594 else 2595 d = &ch->user[ccb->ccb_h.target_id]; 2596 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2597 d->revision = cts->xport_specific.sata.revision; 2598 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2599 d->mode = cts->xport_specific.sata.mode; 2600 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2601 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2602 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2603 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2604 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2605 ch->pm_present = cts->xport_specific.sata.pm_present; 2606 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2607 d->atapi = cts->xport_specific.sata.atapi; 2608 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2609 d->caps = cts->xport_specific.sata.caps; 2610 ccb->ccb_h.status = CAM_REQ_CMP; 2611 break; 2612 } 2613 case XPT_GET_TRAN_SETTINGS: 2614 /* Get default/user set transfer settings for the target */ 2615 { 2616 struct ccb_trans_settings *cts = &ccb->cts; 2617 struct ahci_device *d; 2618 uint32_t status; 2619 2620 if (ahci_check_ids(ch, ccb)) 2621 return; 2622 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2623 d = &ch->curr[ccb->ccb_h.target_id]; 2624 else 2625 d = &ch->user[ccb->ccb_h.target_id]; 2626 cts->protocol = PROTO_UNSPECIFIED; 2627 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2628 cts->transport = XPORT_SATA; 2629 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2630 cts->proto_specific.valid = 0; 2631 cts->xport_specific.sata.valid = 0; 2632 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2633 (ccb->ccb_h.target_id == 15 || 2634 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2635 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2636 if (status & 0x0f0) { 2637 cts->xport_specific.sata.revision = 2638 (status & 0x0f0) >> 4; 2639 cts->xport_specific.sata.valid |= 2640 CTS_SATA_VALID_REVISION; 2641 } 2642 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2643 if (ch->pm_level) { 2644 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC)) 2645 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2646 if (ch->caps2 & AHCI_CAP2_APST) 2647 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST; 2648 } 2649 if ((ch->caps & AHCI_CAP_SNCQ) && 2650 (ch->quirks & AHCI_Q_NOAA) == 0) 2651 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA; 2652 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 2653 cts->xport_specific.sata.caps &= 2654 ch->user[ccb->ccb_h.target_id].caps; 2655 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2656 } else { 2657 cts->xport_specific.sata.revision = d->revision; 2658 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2659 cts->xport_specific.sata.caps = d->caps; 2660 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2661 } 2662 cts->xport_specific.sata.mode = d->mode; 2663 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2664 cts->xport_specific.sata.bytecount = d->bytecount; 2665 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2666 cts->xport_specific.sata.pm_present = ch->pm_present; 2667 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2668 cts->xport_specific.sata.tags = d->tags; 2669 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2670 cts->xport_specific.sata.atapi = d->atapi; 2671 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2672 ccb->ccb_h.status = CAM_REQ_CMP; 2673 break; 2674 } 2675 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2676 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2677 ahci_reset(ch); 2678 ccb->ccb_h.status = CAM_REQ_CMP; 2679 break; 2680 case XPT_TERM_IO: /* Terminate the I/O process */ 2681 /* XXX Implement */ 2682 ccb->ccb_h.status = CAM_REQ_INVALID; 2683 break; 2684 case XPT_PATH_INQ: /* Path routing inquiry */ 2685 { 2686 struct ccb_pathinq *cpi = &ccb->cpi; 2687 2688 cpi->version_num = 1; /* XXX??? */ 2689 cpi->hba_inquiry = PI_SDTR_ABLE; 2690 if (ch->caps & AHCI_CAP_SNCQ) 2691 cpi->hba_inquiry |= PI_TAG_ABLE; 2692 if (ch->caps & AHCI_CAP_SPM) 2693 cpi->hba_inquiry |= PI_SATAPM; 2694 cpi->target_sprt = 0; 2695 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED | PIM_ATA_EXT; 2696 cpi->hba_eng_cnt = 0; 2697 if (ch->caps & AHCI_CAP_SPM) 2698 cpi->max_target = 15; 2699 else 2700 cpi->max_target = 0; 2701 cpi->max_lun = 0; 2702 cpi->initiator_id = 0; 2703 cpi->bus_id = cam_sim_bus(sim); 2704 cpi->base_transfer_speed = 150000; 2705 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2706 strlcpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 2707 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2708 cpi->unit_number = cam_sim_unit(sim); 2709 cpi->transport = XPORT_SATA; 2710 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2711 cpi->protocol = PROTO_ATA; 2712 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2713 cpi->maxio = MAXPHYS; 2714 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 2715 if (ch->quirks & AHCI_Q_MAXIO_64K) 2716 cpi->maxio = min(cpi->maxio, 128 * 512); 2717 cpi->hba_vendor = ch->vendorid; 2718 cpi->hba_device = ch->deviceid; 2719 cpi->hba_subvendor = ch->subvendorid; 2720 cpi->hba_subdevice = ch->subdeviceid; 2721 cpi->ccb_h.status = CAM_REQ_CMP; 2722 break; 2723 } 2724 default: 2725 ccb->ccb_h.status = CAM_REQ_INVALID; 2726 break; 2727 } 2728 ahci_done(ch, ccb); 2729 } 2730 2731 static void 2732 ahcipoll(struct cam_sim *sim) 2733 { 2734 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 2735 uint32_t istatus; 2736 2737 /* Read interrupt statuses and process if any. */ 2738 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 2739 if (istatus != 0) 2740 ahci_ch_intr_main(ch, istatus); 2741 if (ch->resetting != 0 && 2742 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) { 2743 ch->resetpolldiv = 1000; 2744 ahci_reset_to(ch); 2745 } 2746 } 2747 MODULE_VERSION(ahci, 1); 2748 MODULE_DEPEND(ahci, cam, 1, 1, 1); 2749