xref: /freebsd/sys/dev/ahci/ahci.c (revision a521f2116473fbd8c09db395518f060a27d02334)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer,
12  *    without modification, immediately at the beginning of the file.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31 
32 #include <sys/param.h>
33 #include <sys/module.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/bus.h>
37 #include <sys/conf.h>
38 #include <sys/endian.h>
39 #include <sys/malloc.h>
40 #include <sys/lock.h>
41 #include <sys/mutex.h>
42 #include <sys/sysctl.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
46 #include <sys/rman.h>
47 #include "ahci.h"
48 
49 #include <cam/cam.h>
50 #include <cam/cam_ccb.h>
51 #include <cam/cam_sim.h>
52 #include <cam/cam_xpt_sim.h>
53 #include <cam/cam_debug.h>
54 
55 /* local prototypes */
56 static void ahci_intr(void *data);
57 static void ahci_intr_one(void *data);
58 static void ahci_intr_one_edge(void *data);
59 static int ahci_ch_init(device_t dev);
60 static int ahci_ch_deinit(device_t dev);
61 static int ahci_ch_suspend(device_t dev);
62 static int ahci_ch_resume(device_t dev);
63 static void ahci_ch_pm(void *arg);
64 static void ahci_ch_intr(void *arg);
65 static void ahci_ch_intr_direct(void *arg);
66 static void ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus);
67 static void ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb);
68 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
69 static void ahci_execute_transaction(struct ahci_slot *slot);
70 static void ahci_timeout(void *arg);
71 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et);
72 static int ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag);
73 static void ahci_dmainit(device_t dev);
74 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
75 static void ahci_dmafini(device_t dev);
76 static void ahci_slotsalloc(device_t dev);
77 static void ahci_slotsfree(device_t dev);
78 static void ahci_reset(struct ahci_channel *ch);
79 static void ahci_start(struct ahci_channel *ch, int fbs);
80 static void ahci_stop(struct ahci_channel *ch);
81 static void ahci_clo(struct ahci_channel *ch);
82 static void ahci_start_fr(struct ahci_channel *ch);
83 static void ahci_stop_fr(struct ahci_channel *ch);
84 static int ahci_phy_check_events(struct ahci_channel *ch, u_int32_t serr);
85 static uint32_t ahci_ch_detval(struct ahci_channel *ch, uint32_t val);
86 
87 static int ahci_sata_connect(struct ahci_channel *ch);
88 static int ahci_sata_phy_reset(struct ahci_channel *ch);
89 static int ahci_wait_ready(struct ahci_channel *ch, int t, int t0);
90 
91 static void ahci_issue_recovery(struct ahci_channel *ch);
92 static void ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb);
93 static void ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb);
94 
95 static void ahciaction(struct cam_sim *sim, union ccb *ccb);
96 static void ahcipoll(struct cam_sim *sim);
97 
98 static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers");
99 
100 #define recovery_type		spriv_field0
101 #define RECOVERY_NONE		0
102 #define RECOVERY_READ_LOG	1
103 #define RECOVERY_REQUEST_SENSE	2
104 #define recovery_slot		spriv_field1
105 
106 static uint32_t
107 ahci_ch_detval(struct ahci_channel *ch, uint32_t val)
108 {
109 
110 	return ch->disablephy ? ATA_SC_DET_DISABLE : val;
111 }
112 
113 int
114 ahci_ctlr_setup(device_t dev)
115 {
116 	struct ahci_controller *ctlr = device_get_softc(dev);
117 	/* Clear interrupts */
118 	ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS));
119 	/* Configure CCC */
120 	if (ctlr->ccc) {
121 		ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI));
122 		ATA_OUTL(ctlr->r_mem, AHCI_CCCC,
123 		    (ctlr->ccc << AHCI_CCCC_TV_SHIFT) |
124 		    (4 << AHCI_CCCC_CC_SHIFT) |
125 		    AHCI_CCCC_EN);
126 		ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) &
127 		    AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT;
128 		if (bootverbose) {
129 			device_printf(dev,
130 			    "CCC with %dms/4cmd enabled on vector %d\n",
131 			    ctlr->ccc, ctlr->cccv);
132 		}
133 	}
134 	/* Enable AHCI interrupts */
135 	ATA_OUTL(ctlr->r_mem, AHCI_GHC,
136 	    ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE);
137 	return (0);
138 }
139 
140 int
141 ahci_ctlr_reset(device_t dev)
142 {
143 	struct ahci_controller *ctlr = device_get_softc(dev);
144 	uint32_t v;
145 	int timeout;
146 
147 	/* BIOS/OS Handoff */
148 	if ((ATA_INL(ctlr->r_mem, AHCI_VS) >= 0x00010200) &&
149 	    (ATA_INL(ctlr->r_mem, AHCI_CAP2) & AHCI_CAP2_BOH) &&
150 	    ((v = ATA_INL(ctlr->r_mem, AHCI_BOHC)) & AHCI_BOHC_OOS) == 0) {
151 		/* Request OS ownership. */
152 		ATA_OUTL(ctlr->r_mem, AHCI_BOHC, v | AHCI_BOHC_OOS);
153 
154 		/* Wait up to 2s for BIOS ownership release. */
155 		for (timeout = 0; timeout < 80; timeout++) {
156 			DELAY(25000);
157 			v = ATA_INL(ctlr->r_mem, AHCI_BOHC);
158 			if ((v & AHCI_BOHC_BOS) == 0)
159 				break;
160 			if ((v & AHCI_BOHC_BB) == 0)
161 				break;
162 		}
163 	}
164 
165 	/* Enable AHCI mode */
166 	ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
167 	/* Reset AHCI controller */
168 	ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR);
169 	for (timeout = 1000; timeout > 0; timeout--) {
170 		DELAY(1000);
171 		if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0)
172 			break;
173 	}
174 	if (timeout == 0) {
175 		device_printf(dev, "AHCI controller reset failure\n");
176 		return (ENXIO);
177 	}
178 	/* Reenable AHCI mode */
179 	ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
180 
181 	if (ctlr->quirks & AHCI_Q_RESTORE_CAP) {
182 		/*
183 		 * Restore capability field.
184 		 * This is write to a read-only register to restore its state.
185 		 * On fully standard-compliant hardware this is not needed and
186 		 * this operation shall not take place. See ahci_pci.c for
187 		 * platforms using this quirk.
188 		 */
189 		ATA_OUTL(ctlr->r_mem, AHCI_CAP, ctlr->caps);
190 	}
191 
192 	return (0);
193 }
194 
195 int
196 ahci_attach(device_t dev)
197 {
198 	struct ahci_controller *ctlr = device_get_softc(dev);
199 	int error, i, speed, unit;
200 	uint32_t u, version;
201 	device_t child;
202 
203 	ctlr->dev = dev;
204 	ctlr->ccc = 0;
205 	resource_int_value(device_get_name(dev),
206 	    device_get_unit(dev), "ccc", &ctlr->ccc);
207 	mtx_init(&ctlr->ch_mtx, "AHCI channels lock", NULL, MTX_DEF);
208 
209 	/* Setup our own memory management for channels. */
210 	ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
211 	ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
212 	ctlr->sc_iomem.rm_type = RMAN_ARRAY;
213 	ctlr->sc_iomem.rm_descr = "I/O memory addresses";
214 	if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
215 		ahci_free_mem(dev);
216 		return (error);
217 	}
218 	if ((error = rman_manage_region(&ctlr->sc_iomem,
219 	    rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
220 		ahci_free_mem(dev);
221 		rman_fini(&ctlr->sc_iomem);
222 		return (error);
223 	}
224 	/* Get the HW capabilities */
225 	version = ATA_INL(ctlr->r_mem, AHCI_VS);
226 	ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
227 	if (version >= 0x00010200)
228 		ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2);
229 	if (ctlr->caps & AHCI_CAP_EMS)
230 		ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL);
231 
232 	if (ctlr->quirks & AHCI_Q_FORCE_PI) {
233 		/*
234 		 * Enable ports.
235 		 * The spec says that BIOS sets up bits corresponding to
236 		 * available ports. On platforms where this information
237 		 * is missing, the driver can define available ports on its own.
238 		 */
239 		int nports = (ctlr->caps & AHCI_CAP_NPMASK) + 1;
240 		int nmask = (1 << nports) - 1;
241 
242 		ATA_OUTL(ctlr->r_mem, AHCI_PI, nmask);
243 		device_printf(dev, "Forcing PI to %d ports (mask = %x)\n",
244 		    nports, nmask);
245 	}
246 
247 	ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI);
248 
249 	/* Identify and set separate quirks for HBA and RAID f/w Marvells. */
250 	if ((ctlr->quirks & AHCI_Q_ALTSIG) &&
251 	    (ctlr->caps & AHCI_CAP_SPM) == 0)
252 		ctlr->quirks |= AHCI_Q_NOBSYRES;
253 
254 	if (ctlr->quirks & AHCI_Q_1CH) {
255 		ctlr->caps &= ~AHCI_CAP_NPMASK;
256 		ctlr->ichannels &= 0x01;
257 	}
258 	if (ctlr->quirks & AHCI_Q_2CH) {
259 		ctlr->caps &= ~AHCI_CAP_NPMASK;
260 		ctlr->caps |= 1;
261 		ctlr->ichannels &= 0x03;
262 	}
263 	if (ctlr->quirks & AHCI_Q_4CH) {
264 		ctlr->caps &= ~AHCI_CAP_NPMASK;
265 		ctlr->caps |= 3;
266 		ctlr->ichannels &= 0x0f;
267 	}
268 	ctlr->channels = MAX(flsl(ctlr->ichannels),
269 	    (ctlr->caps & AHCI_CAP_NPMASK) + 1);
270 	if (ctlr->quirks & AHCI_Q_NOPMP)
271 		ctlr->caps &= ~AHCI_CAP_SPM;
272 	if (ctlr->quirks & AHCI_Q_NONCQ)
273 		ctlr->caps &= ~AHCI_CAP_SNCQ;
274 	if ((ctlr->caps & AHCI_CAP_CCCS) == 0)
275 		ctlr->ccc = 0;
276 	ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC);
277 
278 	/* Create controller-wide DMA tag. */
279 	if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
280 	    (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR :
281 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
282 	    BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE,
283 	    ctlr->dma_coherent ? BUS_DMA_COHERENT : 0, NULL, NULL,
284 	    &ctlr->dma_tag)) {
285 		ahci_free_mem(dev);
286 		rman_fini(&ctlr->sc_iomem);
287 		return (ENXIO);
288 	}
289 
290 	ahci_ctlr_setup(dev);
291 
292 	/* Setup interrupts. */
293 	if ((error = ahci_setup_interrupt(dev)) != 0) {
294 		bus_dma_tag_destroy(ctlr->dma_tag);
295 		ahci_free_mem(dev);
296 		rman_fini(&ctlr->sc_iomem);
297 		return (error);
298 	}
299 
300 	i = 0;
301 	for (u = ctlr->ichannels; u != 0; u >>= 1)
302 		i += (u & 1);
303 	ctlr->direct = (ctlr->msi && (ctlr->numirqs > 1 || i <= 3));
304 	resource_int_value(device_get_name(dev), device_get_unit(dev),
305 	    "direct", &ctlr->direct);
306 	/* Announce HW capabilities. */
307 	speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT;
308 	device_printf(dev,
309 		    "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n",
310 		    ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f),
311 		    ((version >> 4) & 0xf0) + (version & 0x0f),
312 		    (ctlr->caps & AHCI_CAP_NPMASK) + 1,
313 		    ((speed == 1) ? "1.5":((speed == 2) ? "3":
314 		    ((speed == 3) ? "6":"?"))),
315 		    (ctlr->caps & AHCI_CAP_SPM) ?
316 		    "supported" : "not supported",
317 		    (ctlr->caps & AHCI_CAP_FBSS) ?
318 		    " with FBS" : "");
319 	if (ctlr->quirks != 0) {
320 		device_printf(dev, "quirks=0x%b\n", ctlr->quirks,
321 		    AHCI_Q_BIT_STRING);
322 	}
323 	if (bootverbose) {
324 		device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps",
325 		    (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"",
326 		    (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"",
327 		    (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"",
328 		    (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"",
329 		    (ctlr->caps & AHCI_CAP_SSS) ? " SS":"",
330 		    (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"",
331 		    (ctlr->caps & AHCI_CAP_SAL) ? " AL":"",
332 		    (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"",
333 		    ((speed == 1) ? "1.5":((speed == 2) ? "3":
334 		    ((speed == 3) ? "6":"?"))));
335 		printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n",
336 		    (ctlr->caps & AHCI_CAP_SAM) ? " AM":"",
337 		    (ctlr->caps & AHCI_CAP_SPM) ? " PM":"",
338 		    (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"",
339 		    (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"",
340 		    (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"",
341 		    (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"",
342 		    ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1,
343 		    (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"",
344 		    (ctlr->caps & AHCI_CAP_EMS) ? " EM":"",
345 		    (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"",
346 		    (ctlr->caps & AHCI_CAP_NPMASK) + 1);
347 	}
348 	if (bootverbose && version >= 0x00010200) {
349 		device_printf(dev, "Caps2:%s%s%s%s%s%s\n",
350 		    (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"",
351 		    (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"",
352 		    (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"",
353 		    (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"",
354 		    (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"",
355 		    (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":"");
356 	}
357 	/* Attach all channels on this controller */
358 	for (unit = 0; unit < ctlr->channels; unit++) {
359 		child = device_add_child(dev, "ahcich", -1);
360 		if (child == NULL) {
361 			device_printf(dev, "failed to add channel device\n");
362 			continue;
363 		}
364 		device_set_ivars(child, (void *)(intptr_t)unit);
365 		if ((ctlr->ichannels & (1 << unit)) == 0)
366 			device_disable(child);
367 	}
368 	/* Attach any remapped NVME device */
369 	for (; unit < ctlr->channels + ctlr->remapped_devices; unit++) {
370 		child = device_add_child(dev, "nvme", -1);
371 		if (child == NULL) {
372 			device_printf(dev, "failed to add remapped NVMe device");
373 			    continue;
374 		}
375 		device_set_ivars(child, (void *)(intptr_t)(unit | AHCI_REMAPPED_UNIT));
376 	}
377 
378 	if (ctlr->caps & AHCI_CAP_EMS) {
379 		child = device_add_child(dev, "ahciem", -1);
380 		if (child == NULL)
381 			device_printf(dev, "failed to add enclosure device\n");
382 		else
383 			device_set_ivars(child, (void *)(intptr_t)AHCI_EM_UNIT);
384 	}
385 	bus_generic_attach(dev);
386 	return (0);
387 }
388 
389 int
390 ahci_detach(device_t dev)
391 {
392 	struct ahci_controller *ctlr = device_get_softc(dev);
393 	int i;
394 
395 	/* Detach & delete all children */
396 	device_delete_children(dev);
397 
398 	/* Free interrupts. */
399 	for (i = 0; i < ctlr->numirqs; i++) {
400 		if (ctlr->irqs[i].r_irq) {
401 			bus_teardown_intr(dev, ctlr->irqs[i].r_irq,
402 			    ctlr->irqs[i].handle);
403 			bus_release_resource(dev, SYS_RES_IRQ,
404 			    ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq);
405 		}
406 	}
407 	bus_dma_tag_destroy(ctlr->dma_tag);
408 	/* Free memory. */
409 	rman_fini(&ctlr->sc_iomem);
410 	ahci_free_mem(dev);
411 	mtx_destroy(&ctlr->ch_mtx);
412 	return (0);
413 }
414 
415 void
416 ahci_free_mem(device_t dev)
417 {
418 	struct ahci_controller *ctlr = device_get_softc(dev);
419 
420 	/* Release memory resources */
421 	if (ctlr->r_mem)
422 		bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
423 	if (ctlr->r_msix_table)
424 		bus_release_resource(dev, SYS_RES_MEMORY,
425 		    ctlr->r_msix_tab_rid, ctlr->r_msix_table);
426 	if (ctlr->r_msix_pba)
427 		bus_release_resource(dev, SYS_RES_MEMORY,
428 		    ctlr->r_msix_pba_rid, ctlr->r_msix_pba);
429 
430 	ctlr->r_msix_pba = ctlr->r_mem = ctlr->r_msix_table = NULL;
431 }
432 
433 int
434 ahci_setup_interrupt(device_t dev)
435 {
436 	struct ahci_controller *ctlr = device_get_softc(dev);
437 	int i;
438 
439 	/* Check for single MSI vector fallback. */
440 	if (ctlr->numirqs > 1 &&
441 	    (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) {
442 		device_printf(dev, "Falling back to one MSI\n");
443 		ctlr->numirqs = 1;
444 	}
445 
446 	/* Ensure we don't overrun irqs. */
447 	if (ctlr->numirqs > AHCI_MAX_IRQS) {
448 		device_printf(dev, "Too many irqs %d > %d (clamping)\n",
449 		    ctlr->numirqs, AHCI_MAX_IRQS);
450 		ctlr->numirqs = AHCI_MAX_IRQS;
451 	}
452 
453 	/* Allocate all IRQs. */
454 	for (i = 0; i < ctlr->numirqs; i++) {
455 		ctlr->irqs[i].ctlr = ctlr;
456 		ctlr->irqs[i].r_irq_rid = i + (ctlr->msi ? 1 : 0);
457 		if (ctlr->channels == 1 && !ctlr->ccc && ctlr->msi)
458 			ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
459 		else if (ctlr->numirqs == 1 || i >= ctlr->channels ||
460 		    (ctlr->ccc && i == ctlr->cccv))
461 			ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL;
462 		else if (ctlr->channels > ctlr->numirqs &&
463 		    i == ctlr->numirqs - 1)
464 			ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER;
465 		else
466 			ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
467 		if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
468 		    &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
469 			device_printf(dev, "unable to map interrupt\n");
470 			return (ENXIO);
471 		}
472 		if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL,
473 		    (ctlr->irqs[i].mode != AHCI_IRQ_MODE_ONE) ? ahci_intr :
474 		     ((ctlr->quirks & AHCI_Q_EDGEIS) ? ahci_intr_one_edge :
475 		      ahci_intr_one),
476 		    &ctlr->irqs[i], &ctlr->irqs[i].handle))) {
477 			/* SOS XXX release r_irq */
478 			device_printf(dev, "unable to setup interrupt\n");
479 			return (ENXIO);
480 		}
481 		if (ctlr->numirqs > 1) {
482 			bus_describe_intr(dev, ctlr->irqs[i].r_irq,
483 			    ctlr->irqs[i].handle,
484 			    ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ?
485 			    "ch%d" : "%d", i);
486 		}
487 	}
488 	return (0);
489 }
490 
491 /*
492  * Common case interrupt handler.
493  */
494 static void
495 ahci_intr(void *data)
496 {
497 	struct ahci_controller_irq *irq = data;
498 	struct ahci_controller *ctlr = irq->ctlr;
499 	u_int32_t is, ise = 0;
500 	void *arg;
501 	int unit;
502 
503 	if (irq->mode == AHCI_IRQ_MODE_ALL) {
504 		unit = 0;
505 		if (ctlr->ccc)
506 			is = ctlr->ichannels;
507 		else
508 			is = ATA_INL(ctlr->r_mem, AHCI_IS);
509 	} else {	/* AHCI_IRQ_MODE_AFTER */
510 		unit = irq->r_irq_rid - 1;
511 		is = ATA_INL(ctlr->r_mem, AHCI_IS);
512 		is &= (0xffffffff << unit);
513 	}
514 	/* CCC interrupt is edge triggered. */
515 	if (ctlr->ccc)
516 		ise = 1 << ctlr->cccv;
517 	/* Some controllers have edge triggered IS. */
518 	if (ctlr->quirks & AHCI_Q_EDGEIS)
519 		ise |= is;
520 	if (ise != 0)
521 		ATA_OUTL(ctlr->r_mem, AHCI_IS, ise);
522 	for (; unit < ctlr->channels; unit++) {
523 		if ((is & (1 << unit)) != 0 &&
524 		    (arg = ctlr->interrupt[unit].argument)) {
525 				ctlr->interrupt[unit].function(arg);
526 		}
527 	}
528 	for (; unit < ctlr->channels + ctlr->remapped_devices; unit++) {
529 		if ((arg = ctlr->interrupt[unit].argument)) {
530 			ctlr->interrupt[unit].function(arg);
531 		}
532 	}
533 
534 	/* AHCI declares level triggered IS. */
535 	if (!(ctlr->quirks & AHCI_Q_EDGEIS))
536 		ATA_OUTL(ctlr->r_mem, AHCI_IS, is);
537 	ATA_RBL(ctlr->r_mem, AHCI_IS);
538 }
539 
540 /*
541  * Simplified interrupt handler for multivector MSI mode.
542  */
543 static void
544 ahci_intr_one(void *data)
545 {
546 	struct ahci_controller_irq *irq = data;
547 	struct ahci_controller *ctlr = irq->ctlr;
548 	void *arg;
549 	int unit;
550 
551 	unit = irq->r_irq_rid - 1;
552 	if ((arg = ctlr->interrupt[unit].argument))
553 	    ctlr->interrupt[unit].function(arg);
554 	/* AHCI declares level triggered IS. */
555 	ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
556 	ATA_RBL(ctlr->r_mem, AHCI_IS);
557 }
558 
559 static void
560 ahci_intr_one_edge(void *data)
561 {
562 	struct ahci_controller_irq *irq = data;
563 	struct ahci_controller *ctlr = irq->ctlr;
564 	void *arg;
565 	int unit;
566 
567 	unit = irq->r_irq_rid - 1;
568 	/* Some controllers have edge triggered IS. */
569 	ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
570 	if ((arg = ctlr->interrupt[unit].argument))
571 		ctlr->interrupt[unit].function(arg);
572 	ATA_RBL(ctlr->r_mem, AHCI_IS);
573 }
574 
575 struct resource *
576 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid,
577     rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
578 {
579 	struct ahci_controller *ctlr = device_get_softc(dev);
580 	struct resource *res;
581 	rman_res_t st;
582 	int offset, size, unit;
583 	bool is_em, is_remapped;
584 
585 	unit = (intptr_t)device_get_ivars(child);
586 	is_em = is_remapped = false;
587 	if (unit & AHCI_REMAPPED_UNIT) {
588 		unit &= AHCI_UNIT;
589 		unit -= ctlr->channels;
590 		is_remapped = true;
591 	} else if (unit & AHCI_EM_UNIT) {
592 		unit &= AHCI_UNIT;
593 		is_em = true;
594 	}
595 	res = NULL;
596 	switch (type) {
597 	case SYS_RES_MEMORY:
598 		if (is_remapped) {
599 			offset = ctlr->remap_offset + unit * ctlr->remap_size;
600 			size = ctlr->remap_size;
601 		} else if (!is_em) {
602 			offset = AHCI_OFFSET + (unit << 7);
603 			size = 128;
604 		} else if (*rid == 0) {
605 			offset = AHCI_EM_CTL;
606 			size = 4;
607 		} else {
608 			offset = (ctlr->emloc & 0xffff0000) >> 14;
609 			size = (ctlr->emloc & 0x0000ffff) << 2;
610 			if (*rid != 1) {
611 				if (*rid == 2 && (ctlr->capsem &
612 				    (AHCI_EM_XMT | AHCI_EM_SMB)) == 0)
613 					offset += size;
614 				else
615 					break;
616 			}
617 		}
618 		st = rman_get_start(ctlr->r_mem);
619 		res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
620 		    st + offset + size - 1, size, RF_ACTIVE, child);
621 		if (res) {
622 			bus_space_handle_t bsh;
623 			bus_space_tag_t bst;
624 			bsh = rman_get_bushandle(ctlr->r_mem);
625 			bst = rman_get_bustag(ctlr->r_mem);
626 			bus_space_subregion(bst, bsh, offset, 128, &bsh);
627 			rman_set_bushandle(res, bsh);
628 			rman_set_bustag(res, bst);
629 		}
630 		break;
631 	case SYS_RES_IRQ:
632 		if (*rid == ATA_IRQ_RID)
633 			res = ctlr->irqs[0].r_irq;
634 		break;
635 	}
636 	return (res);
637 }
638 
639 int
640 ahci_release_resource(device_t dev, device_t child, int type, int rid,
641     struct resource *r)
642 {
643 
644 	switch (type) {
645 	case SYS_RES_MEMORY:
646 		rman_release_resource(r);
647 		return (0);
648 	case SYS_RES_IRQ:
649 		if (rid != ATA_IRQ_RID)
650 			return (ENOENT);
651 		return (0);
652 	}
653 	return (EINVAL);
654 }
655 
656 int
657 ahci_setup_intr(device_t dev, device_t child, struct resource *irq,
658     int flags, driver_filter_t *filter, driver_intr_t *function,
659     void *argument, void **cookiep)
660 {
661 	struct ahci_controller *ctlr = device_get_softc(dev);
662 	int unit = (intptr_t)device_get_ivars(child) & AHCI_UNIT;
663 
664 	if (filter != NULL) {
665 		printf("ahci.c: we cannot use a filter here\n");
666 		return (EINVAL);
667 	}
668 	ctlr->interrupt[unit].function = function;
669 	ctlr->interrupt[unit].argument = argument;
670 	return (0);
671 }
672 
673 int
674 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq,
675     void *cookie)
676 {
677 	struct ahci_controller *ctlr = device_get_softc(dev);
678 	int unit = (intptr_t)device_get_ivars(child) & AHCI_UNIT;
679 
680 	ctlr->interrupt[unit].function = NULL;
681 	ctlr->interrupt[unit].argument = NULL;
682 	return (0);
683 }
684 
685 int
686 ahci_print_child(device_t dev, device_t child)
687 {
688 	intptr_t ivars;
689 	int retval;
690 
691 	retval = bus_print_child_header(dev, child);
692 	ivars = (intptr_t)device_get_ivars(child);
693 	if ((ivars & AHCI_EM_UNIT) == 0)
694 		retval += printf(" at channel %d", (int)ivars & AHCI_UNIT);
695 	retval += bus_print_child_footer(dev, child);
696 	return (retval);
697 }
698 
699 int
700 ahci_child_location_str(device_t dev, device_t child, char *buf,
701     size_t buflen)
702 {
703 	intptr_t ivars;
704 
705 	ivars = (intptr_t)device_get_ivars(child);
706 	if ((ivars & AHCI_EM_UNIT) == 0)
707 		snprintf(buf, buflen, "channel=%d", (int)ivars & AHCI_UNIT);
708 	return (0);
709 }
710 
711 bus_dma_tag_t
712 ahci_get_dma_tag(device_t dev, device_t child)
713 {
714 	struct ahci_controller *ctlr = device_get_softc(dev);
715 
716 	return (ctlr->dma_tag);
717 }
718 
719 void
720 ahci_attached(device_t dev, struct ahci_channel *ch)
721 {
722 	struct ahci_controller *ctlr = device_get_softc(dev);
723 
724 	mtx_lock(&ctlr->ch_mtx);
725 	ctlr->ch[ch->unit] = ch;
726 	mtx_unlock(&ctlr->ch_mtx);
727 }
728 
729 void
730 ahci_detached(device_t dev, struct ahci_channel *ch)
731 {
732 	struct ahci_controller *ctlr = device_get_softc(dev);
733 
734 	mtx_lock(&ctlr->ch_mtx);
735 	mtx_lock(&ch->mtx);
736 	ctlr->ch[ch->unit] = NULL;
737 	mtx_unlock(&ch->mtx);
738 	mtx_unlock(&ctlr->ch_mtx);
739 }
740 
741 struct ahci_channel *
742 ahci_getch(device_t dev, int n)
743 {
744 	struct ahci_controller *ctlr = device_get_softc(dev);
745 	struct ahci_channel *ch;
746 
747 	KASSERT(n >= 0 && n < AHCI_MAX_PORTS, ("Bad channel number %d", n));
748 	mtx_lock(&ctlr->ch_mtx);
749 	ch = ctlr->ch[n];
750 	if (ch != NULL)
751 		mtx_lock(&ch->mtx);
752 	mtx_unlock(&ctlr->ch_mtx);
753 	return (ch);
754 }
755 
756 void
757 ahci_putch(struct ahci_channel *ch)
758 {
759 
760 	mtx_unlock(&ch->mtx);
761 }
762 
763 static int
764 ahci_ch_probe(device_t dev)
765 {
766 
767 	device_set_desc_copy(dev, "AHCI channel");
768 	return (BUS_PROBE_DEFAULT);
769 }
770 
771 static int
772 ahci_ch_disablephy_proc(SYSCTL_HANDLER_ARGS)
773 {
774 	struct ahci_channel *ch;
775 	int error, value;
776 
777 	ch = arg1;
778 	value = ch->disablephy;
779 	error = sysctl_handle_int(oidp, &value, 0, req);
780 	if (error != 0 || req->newptr == NULL || (value != 0 && value != 1))
781 		return (error);
782 
783 	mtx_lock(&ch->mtx);
784 	ch->disablephy = value;
785 	if (value) {
786 		ahci_ch_deinit(ch->dev);
787 	} else {
788 		ahci_ch_init(ch->dev);
789 		ahci_phy_check_events(ch, ATA_SE_PHY_CHANGED | ATA_SE_EXCHANGED);
790 	}
791 	mtx_unlock(&ch->mtx);
792 
793 	return (0);
794 }
795 
796 static int
797 ahci_ch_attach(device_t dev)
798 {
799 	struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
800 	struct ahci_channel *ch = device_get_softc(dev);
801 	struct cam_devq *devq;
802 	struct sysctl_ctx_list *ctx;
803 	struct sysctl_oid *tree;
804 	int rid, error, i, sata_rev = 0;
805 	u_int32_t version;
806 
807 	ch->dev = dev;
808 	ch->unit = (intptr_t)device_get_ivars(dev);
809 	ch->caps = ctlr->caps;
810 	ch->caps2 = ctlr->caps2;
811 	ch->start = ctlr->ch_start;
812 	ch->quirks = ctlr->quirks;
813 	ch->vendorid = ctlr->vendorid;
814 	ch->deviceid = ctlr->deviceid;
815 	ch->subvendorid = ctlr->subvendorid;
816 	ch->subdeviceid = ctlr->subdeviceid;
817 	ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1;
818 	mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF);
819 	ch->pm_level = 0;
820 	resource_int_value(device_get_name(dev),
821 	    device_get_unit(dev), "pm_level", &ch->pm_level);
822 	STAILQ_INIT(&ch->doneq);
823 	if (ch->pm_level > 3)
824 		callout_init_mtx(&ch->pm_timer, &ch->mtx, 0);
825 	callout_init_mtx(&ch->reset_timer, &ch->mtx, 0);
826 	/* JMicron external ports (0) sometimes limited */
827 	if ((ctlr->quirks & AHCI_Q_SATA1_UNIT0) && ch->unit == 0)
828 		sata_rev = 1;
829 	if (ch->quirks & AHCI_Q_SATA2)
830 		sata_rev = 2;
831 	resource_int_value(device_get_name(dev),
832 	    device_get_unit(dev), "sata_rev", &sata_rev);
833 	for (i = 0; i < 16; i++) {
834 		ch->user[i].revision = sata_rev;
835 		ch->user[i].mode = 0;
836 		ch->user[i].bytecount = 8192;
837 		ch->user[i].tags = ch->numslots;
838 		ch->user[i].caps = 0;
839 		ch->curr[i] = ch->user[i];
840 		if (ch->pm_level) {
841 			ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ |
842 			    CTS_SATA_CAPS_H_APST |
843 			    CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST;
844 		}
845 		ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA |
846 		    CTS_SATA_CAPS_H_AN;
847 	}
848 	rid = 0;
849 	if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
850 	    &rid, RF_ACTIVE)))
851 		return (ENXIO);
852 	ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD);
853 	version = ATA_INL(ctlr->r_mem, AHCI_VS);
854 	if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS))
855 		ch->chcaps |= AHCI_P_CMD_FBSCP;
856 	if (ch->caps2 & AHCI_CAP2_SDS)
857 		ch->chscaps = ATA_INL(ch->r_mem, AHCI_P_DEVSLP);
858 	if (bootverbose) {
859 		device_printf(dev, "Caps:%s%s%s%s%s%s\n",
860 		    (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"",
861 		    (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"",
862 		    (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"",
863 		    (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"",
864 		    (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"",
865 		    (ch->chscaps & AHCI_P_DEVSLP_DSP) ? " DSP":"");
866 	}
867 	ahci_dmainit(dev);
868 	ahci_slotsalloc(dev);
869 	mtx_lock(&ch->mtx);
870 	ahci_ch_init(dev);
871 	rid = ATA_IRQ_RID;
872 	if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
873 	    &rid, RF_SHAREABLE | RF_ACTIVE))) {
874 		device_printf(dev, "Unable to map interrupt\n");
875 		error = ENXIO;
876 		goto err0;
877 	}
878 	if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL,
879 	    ctlr->direct ? ahci_ch_intr_direct : ahci_ch_intr,
880 	    ch, &ch->ih))) {
881 		device_printf(dev, "Unable to setup interrupt\n");
882 		error = ENXIO;
883 		goto err1;
884 	}
885 	/* Create the device queue for our SIM. */
886 	devq = cam_simq_alloc(ch->numslots);
887 	if (devq == NULL) {
888 		device_printf(dev, "Unable to allocate simq\n");
889 		error = ENOMEM;
890 		goto err1;
891 	}
892 	/* Construct SIM entry */
893 	ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch,
894 	    device_get_unit(dev), (struct mtx *)&ch->mtx,
895 	    (ch->quirks & AHCI_Q_NOCCS) ? 1 : min(2, ch->numslots),
896 	    (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0,
897 	    devq);
898 	if (ch->sim == NULL) {
899 		cam_simq_free(devq);
900 		device_printf(dev, "unable to allocate sim\n");
901 		error = ENOMEM;
902 		goto err1;
903 	}
904 	if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) {
905 		device_printf(dev, "unable to register xpt bus\n");
906 		error = ENXIO;
907 		goto err2;
908 	}
909 	if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim),
910 	    CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
911 		device_printf(dev, "unable to create path\n");
912 		error = ENXIO;
913 		goto err3;
914 	}
915 	if (ch->pm_level > 3) {
916 		callout_reset(&ch->pm_timer,
917 		    (ch->pm_level == 4) ? hz / 1000 : hz / 8,
918 		    ahci_ch_pm, ch);
919 	}
920 	mtx_unlock(&ch->mtx);
921 	ahci_attached(device_get_parent(dev), ch);
922 	ctx = device_get_sysctl_ctx(dev);
923 	tree = device_get_sysctl_tree(dev);
924 	SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "disable_phy",
925 	    CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, ch,
926 	    0, ahci_ch_disablephy_proc, "IU", "Disable PHY");
927 	return (0);
928 
929 err3:
930 	xpt_bus_deregister(cam_sim_path(ch->sim));
931 err2:
932 	cam_sim_free(ch->sim, /*free_devq*/TRUE);
933 err1:
934 	bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
935 err0:
936 	bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
937 	mtx_unlock(&ch->mtx);
938 	mtx_destroy(&ch->mtx);
939 	return (error);
940 }
941 
942 static int
943 ahci_ch_detach(device_t dev)
944 {
945 	struct ahci_channel *ch = device_get_softc(dev);
946 
947 	ahci_detached(device_get_parent(dev), ch);
948 	mtx_lock(&ch->mtx);
949 	xpt_async(AC_LOST_DEVICE, ch->path, NULL);
950 	/* Forget about reset. */
951 	if (ch->resetting) {
952 		ch->resetting = 0;
953 		xpt_release_simq(ch->sim, TRUE);
954 	}
955 	xpt_free_path(ch->path);
956 	xpt_bus_deregister(cam_sim_path(ch->sim));
957 	cam_sim_free(ch->sim, /*free_devq*/TRUE);
958 	mtx_unlock(&ch->mtx);
959 
960 	if (ch->pm_level > 3)
961 		callout_drain(&ch->pm_timer);
962 	callout_drain(&ch->reset_timer);
963 	bus_teardown_intr(dev, ch->r_irq, ch->ih);
964 	bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
965 
966 	ahci_ch_deinit(dev);
967 	ahci_slotsfree(dev);
968 	ahci_dmafini(dev);
969 
970 	bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
971 	mtx_destroy(&ch->mtx);
972 	return (0);
973 }
974 
975 static int
976 ahci_ch_init(device_t dev)
977 {
978 	struct ahci_channel *ch = device_get_softc(dev);
979 	uint64_t work;
980 
981 	/* Disable port interrupts */
982 	ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
983 	/* Setup work areas */
984 	work = ch->dma.work_bus + AHCI_CL_OFFSET;
985 	ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff);
986 	ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32);
987 	work = ch->dma.rfis_bus;
988 	ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff);
989 	ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32);
990 	/* Activate the channel and power/spin up device */
991 	ATA_OUTL(ch->r_mem, AHCI_P_CMD,
992 	     (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD |
993 	     ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) |
994 	     ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 )));
995 	ahci_start_fr(ch);
996 	ahci_start(ch, 1);
997 	return (0);
998 }
999 
1000 static int
1001 ahci_ch_deinit(device_t dev)
1002 {
1003 	struct ahci_channel *ch = device_get_softc(dev);
1004 
1005 	/* Disable port interrupts. */
1006 	ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
1007 	/* Reset command register. */
1008 	ahci_stop(ch);
1009 	ahci_stop_fr(ch);
1010 	ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0);
1011 	/* Allow everything, including partial and slumber modes. */
1012 	ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0);
1013 	/* Request slumber mode transition and give some time to get there. */
1014 	ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER);
1015 	DELAY(100);
1016 	/* Disable PHY. */
1017 	ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
1018 	return (0);
1019 }
1020 
1021 static int
1022 ahci_ch_suspend(device_t dev)
1023 {
1024 	struct ahci_channel *ch = device_get_softc(dev);
1025 
1026 	mtx_lock(&ch->mtx);
1027 	xpt_freeze_simq(ch->sim, 1);
1028 	/* Forget about reset. */
1029 	if (ch->resetting) {
1030 		ch->resetting = 0;
1031 		callout_stop(&ch->reset_timer);
1032 		xpt_release_simq(ch->sim, TRUE);
1033 	}
1034 	while (ch->oslots)
1035 		msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100);
1036 	ahci_ch_deinit(dev);
1037 	mtx_unlock(&ch->mtx);
1038 	return (0);
1039 }
1040 
1041 static int
1042 ahci_ch_resume(device_t dev)
1043 {
1044 	struct ahci_channel *ch = device_get_softc(dev);
1045 
1046 	mtx_lock(&ch->mtx);
1047 	ahci_ch_init(dev);
1048 	ahci_reset(ch);
1049 	xpt_release_simq(ch->sim, TRUE);
1050 	mtx_unlock(&ch->mtx);
1051 	return (0);
1052 }
1053 
1054 devclass_t ahcich_devclass;
1055 static device_method_t ahcich_methods[] = {
1056 	DEVMETHOD(device_probe,     ahci_ch_probe),
1057 	DEVMETHOD(device_attach,    ahci_ch_attach),
1058 	DEVMETHOD(device_detach,    ahci_ch_detach),
1059 	DEVMETHOD(device_suspend,   ahci_ch_suspend),
1060 	DEVMETHOD(device_resume,    ahci_ch_resume),
1061 	DEVMETHOD_END
1062 };
1063 static driver_t ahcich_driver = {
1064         "ahcich",
1065         ahcich_methods,
1066         sizeof(struct ahci_channel)
1067 };
1068 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, NULL, NULL);
1069 
1070 struct ahci_dc_cb_args {
1071 	bus_addr_t maddr;
1072 	int error;
1073 };
1074 
1075 static void
1076 ahci_dmainit(device_t dev)
1077 {
1078 	struct ahci_channel *ch = device_get_softc(dev);
1079 	struct ahci_dc_cb_args dcba;
1080 	size_t rfsize;
1081 	int error;
1082 
1083 	/* Command area. */
1084 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0,
1085 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1086 	    NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE,
1087 	    0, NULL, NULL, &ch->dma.work_tag);
1088 	if (error != 0)
1089 		goto error;
1090 	error = bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work,
1091 	    BUS_DMA_ZERO, &ch->dma.work_map);
1092 	if (error != 0)
1093 		goto error;
1094 	error = bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work,
1095 	    AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, BUS_DMA_NOWAIT);
1096 	if (error != 0 || (error = dcba.error) != 0) {
1097 		bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1098 		goto error;
1099 	}
1100 	ch->dma.work_bus = dcba.maddr;
1101 	/* FIS receive area. */
1102 	if (ch->chcaps & AHCI_P_CMD_FBSCP)
1103 	    rfsize = 4096;
1104 	else
1105 	    rfsize = 256;
1106 	error = bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0,
1107 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1108 	    NULL, NULL, rfsize, 1, rfsize,
1109 	    0, NULL, NULL, &ch->dma.rfis_tag);
1110 	if (error != 0)
1111 		goto error;
1112 	error = bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0,
1113 	    &ch->dma.rfis_map);
1114 	if (error != 0)
1115 		goto error;
1116 	error = bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis,
1117 	    rfsize, ahci_dmasetupc_cb, &dcba, BUS_DMA_NOWAIT);
1118 	if (error != 0 || (error = dcba.error) != 0) {
1119 		bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1120 		goto error;
1121 	}
1122 	ch->dma.rfis_bus = dcba.maddr;
1123 	/* Data area. */
1124 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
1125 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1126 	    NULL, NULL,
1127 	    AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots,
1128 	    AHCI_SG_ENTRIES, AHCI_PRD_MAX,
1129 	    0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag);
1130 	if (error != 0)
1131 		goto error;
1132 	return;
1133 
1134 error:
1135 	device_printf(dev, "WARNING - DMA initialization failed, error %d\n",
1136 	    error);
1137 	ahci_dmafini(dev);
1138 }
1139 
1140 static void
1141 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
1142 {
1143 	struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc;
1144 
1145 	if (!(dcba->error = error))
1146 		dcba->maddr = segs[0].ds_addr;
1147 }
1148 
1149 static void
1150 ahci_dmafini(device_t dev)
1151 {
1152 	struct ahci_channel *ch = device_get_softc(dev);
1153 
1154 	if (ch->dma.data_tag) {
1155 		bus_dma_tag_destroy(ch->dma.data_tag);
1156 		ch->dma.data_tag = NULL;
1157 	}
1158 	if (ch->dma.rfis_bus) {
1159 		bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map);
1160 		bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1161 		ch->dma.rfis_bus = 0;
1162 		ch->dma.rfis = NULL;
1163 	}
1164 	if (ch->dma.work_bus) {
1165 		bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map);
1166 		bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1167 		ch->dma.work_bus = 0;
1168 		ch->dma.work = NULL;
1169 	}
1170 	if (ch->dma.work_tag) {
1171 		bus_dma_tag_destroy(ch->dma.work_tag);
1172 		ch->dma.work_tag = NULL;
1173 	}
1174 }
1175 
1176 static void
1177 ahci_slotsalloc(device_t dev)
1178 {
1179 	struct ahci_channel *ch = device_get_softc(dev);
1180 	int i;
1181 
1182 	/* Alloc and setup command/dma slots */
1183 	bzero(ch->slot, sizeof(ch->slot));
1184 	for (i = 0; i < ch->numslots; i++) {
1185 		struct ahci_slot *slot = &ch->slot[i];
1186 
1187 		slot->ch = ch;
1188 		slot->slot = i;
1189 		slot->state = AHCI_SLOT_EMPTY;
1190 		slot->ccb = NULL;
1191 		callout_init_mtx(&slot->timeout, &ch->mtx, 0);
1192 
1193 		if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map))
1194 			device_printf(ch->dev, "FAILURE - create data_map\n");
1195 	}
1196 }
1197 
1198 static void
1199 ahci_slotsfree(device_t dev)
1200 {
1201 	struct ahci_channel *ch = device_get_softc(dev);
1202 	int i;
1203 
1204 	/* Free all dma slots */
1205 	for (i = 0; i < ch->numslots; i++) {
1206 		struct ahci_slot *slot = &ch->slot[i];
1207 
1208 		callout_drain(&slot->timeout);
1209 		if (slot->dma.data_map) {
1210 			bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map);
1211 			slot->dma.data_map = NULL;
1212 		}
1213 	}
1214 }
1215 
1216 static int
1217 ahci_phy_check_events(struct ahci_channel *ch, u_int32_t serr)
1218 {
1219 
1220 	if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) ||
1221 	    ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) {
1222 		u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
1223 		union ccb *ccb;
1224 
1225 		if (bootverbose) {
1226 			if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
1227 				device_printf(ch->dev, "CONNECT requested\n");
1228 			else
1229 				device_printf(ch->dev, "DISCONNECT requested\n");
1230 		}
1231 		ahci_reset(ch);
1232 		if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1233 			return (0);
1234 		if (xpt_create_path(&ccb->ccb_h.path, NULL,
1235 		    cam_sim_path(ch->sim),
1236 		    CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1237 			xpt_free_ccb(ccb);
1238 			return (0);
1239 		}
1240 		xpt_rescan(ccb);
1241 		return (1);
1242 	}
1243 	return (0);
1244 }
1245 
1246 static void
1247 ahci_cpd_check_events(struct ahci_channel *ch)
1248 {
1249 	u_int32_t status;
1250 	union ccb *ccb;
1251 	device_t dev;
1252 
1253 	if (ch->pm_level == 0)
1254 		return;
1255 
1256 	status = ATA_INL(ch->r_mem, AHCI_P_CMD);
1257 	if ((status & AHCI_P_CMD_CPD) == 0)
1258 		return;
1259 
1260 	if (bootverbose) {
1261 		dev = ch->dev;
1262 		if (status & AHCI_P_CMD_CPS) {
1263 			device_printf(dev, "COLD CONNECT requested\n");
1264 		} else
1265 			device_printf(dev, "COLD DISCONNECT requested\n");
1266 	}
1267 	ahci_reset(ch);
1268 	if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1269 		return;
1270 	if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim),
1271 	    CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1272 		xpt_free_ccb(ccb);
1273 		return;
1274 	}
1275 	xpt_rescan(ccb);
1276 }
1277 
1278 static void
1279 ahci_notify_events(struct ahci_channel *ch, u_int32_t status)
1280 {
1281 	struct cam_path *dpath;
1282 	int i;
1283 
1284 	if (ch->caps & AHCI_CAP_SSNTF)
1285 		ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status);
1286 	if (bootverbose)
1287 		device_printf(ch->dev, "SNTF 0x%04x\n", status);
1288 	for (i = 0; i < 16; i++) {
1289 		if ((status & (1 << i)) == 0)
1290 			continue;
1291 		if (xpt_create_path(&dpath, NULL,
1292 		    xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) {
1293 			xpt_async(AC_SCSI_AEN, dpath, NULL);
1294 			xpt_free_path(dpath);
1295 		}
1296 	}
1297 }
1298 
1299 static void
1300 ahci_done(struct ahci_channel *ch, union ccb *ccb)
1301 {
1302 
1303 	mtx_assert(&ch->mtx, MA_OWNED);
1304 	if ((ccb->ccb_h.func_code & XPT_FC_QUEUED) == 0 ||
1305 	    ch->batch == 0) {
1306 		xpt_done(ccb);
1307 		return;
1308 	}
1309 
1310 	STAILQ_INSERT_TAIL(&ch->doneq, &ccb->ccb_h, sim_links.stqe);
1311 }
1312 
1313 static void
1314 ahci_ch_intr(void *arg)
1315 {
1316 	struct ahci_channel *ch = (struct ahci_channel *)arg;
1317 	uint32_t istatus;
1318 
1319 	/* Read interrupt statuses. */
1320 	istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1321 
1322 	mtx_lock(&ch->mtx);
1323 	ahci_ch_intr_main(ch, istatus);
1324 	mtx_unlock(&ch->mtx);
1325 }
1326 
1327 static void
1328 ahci_ch_intr_direct(void *arg)
1329 {
1330 	struct ahci_channel *ch = (struct ahci_channel *)arg;
1331 	struct ccb_hdr *ccb_h;
1332 	uint32_t istatus;
1333 	STAILQ_HEAD(, ccb_hdr) tmp_doneq = STAILQ_HEAD_INITIALIZER(tmp_doneq);
1334 
1335 	/* Read interrupt statuses. */
1336 	istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1337 
1338 	mtx_lock(&ch->mtx);
1339 	ch->batch = 1;
1340 	ahci_ch_intr_main(ch, istatus);
1341 	ch->batch = 0;
1342 	/*
1343 	 * Prevent the possibility of issues caused by processing the queue
1344 	 * while unlocked below by moving the contents to a local queue.
1345 	 */
1346 	STAILQ_CONCAT(&tmp_doneq, &ch->doneq);
1347 	mtx_unlock(&ch->mtx);
1348 	while ((ccb_h = STAILQ_FIRST(&tmp_doneq)) != NULL) {
1349 		STAILQ_REMOVE_HEAD(&tmp_doneq, sim_links.stqe);
1350 		xpt_done_direct((union ccb *)ccb_h);
1351 	}
1352 }
1353 
1354 static void
1355 ahci_ch_pm(void *arg)
1356 {
1357 	struct ahci_channel *ch = (struct ahci_channel *)arg;
1358 	uint32_t work;
1359 
1360 	if (ch->numrslots != 0)
1361 		return;
1362 	work = ATA_INL(ch->r_mem, AHCI_P_CMD);
1363 	if (ch->pm_level == 4)
1364 		work |= AHCI_P_CMD_PARTIAL;
1365 	else
1366 		work |= AHCI_P_CMD_SLUMBER;
1367 	ATA_OUTL(ch->r_mem, AHCI_P_CMD, work);
1368 }
1369 
1370 static void
1371 ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus)
1372 {
1373 	uint32_t cstatus, serr = 0, sntf = 0, ok, err;
1374 	enum ahci_err_type et;
1375 	int i, ccs, port, reset = 0;
1376 
1377 	/* Clear interrupt statuses. */
1378 	ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus);
1379 	/* Read command statuses. */
1380 	if (ch->numtslots != 0)
1381 		cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1382 	else
1383 		cstatus = 0;
1384 	if (ch->numrslots != ch->numtslots)
1385 		cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI);
1386 	/* Read SNTF in one of possible ways. */
1387 	if ((istatus & AHCI_P_IX_SDB) &&
1388 	    (ch->pm_present || ch->curr[0].atapi != 0)) {
1389 		if (ch->caps & AHCI_CAP_SSNTF)
1390 			sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF);
1391 		else if (ch->fbs_enabled) {
1392 			u_int8_t *fis = ch->dma.rfis + 0x58;
1393 
1394 			for (i = 0; i < 16; i++) {
1395 				if (fis[1] & 0x80) {
1396 					fis[1] &= 0x7f;
1397 	    				sntf |= 1 << i;
1398 	    			}
1399 	    			fis += 256;
1400 	    		}
1401 		} else {
1402 			u_int8_t *fis = ch->dma.rfis + 0x58;
1403 
1404 			if (fis[1] & 0x80)
1405 				sntf = (1 << (fis[1] & 0x0f));
1406 		}
1407 	}
1408 	/* Process PHY events */
1409 	if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF |
1410 	    AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1411 		serr = ATA_INL(ch->r_mem, AHCI_P_SERR);
1412 		if (serr) {
1413 			ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr);
1414 			reset = ahci_phy_check_events(ch, serr);
1415 		}
1416 	}
1417 	/* Process cold presence detection events */
1418 	if ((istatus & AHCI_P_IX_CPD) && !reset)
1419 		ahci_cpd_check_events(ch);
1420 	/* Process command errors */
1421 	if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF |
1422 	    AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1423 		if (ch->quirks & AHCI_Q_NOCCS) {
1424 			/*
1425 			 * ASMedia chips sometimes report failed commands as
1426 			 * completed.  Count all running commands as failed.
1427 			 */
1428 			cstatus |= ch->rslots;
1429 
1430 			/* They also report wrong CCS, so try to guess one. */
1431 			ccs = powerof2(cstatus) ? ffs(cstatus) - 1 : -1;
1432 		} else {
1433 			ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) &
1434 			    AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT;
1435 		}
1436 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n",
1437 //    __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD),
1438 //    serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs);
1439 		port = -1;
1440 		if (ch->fbs_enabled) {
1441 			uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS);
1442 			if (fbs & AHCI_P_FBS_SDE) {
1443 				port = (fbs & AHCI_P_FBS_DWE)
1444 				    >> AHCI_P_FBS_DWE_SHIFT;
1445 			} else {
1446 				for (i = 0; i < 16; i++) {
1447 					if (ch->numrslotspd[i] == 0)
1448 						continue;
1449 					if (port == -1)
1450 						port = i;
1451 					else if (port != i) {
1452 						port = -2;
1453 						break;
1454 					}
1455 				}
1456 			}
1457 		}
1458 		err = ch->rslots & cstatus;
1459 	} else {
1460 		ccs = 0;
1461 		err = 0;
1462 		port = -1;
1463 	}
1464 	/* Complete all successful commands. */
1465 	ok = ch->rslots & ~cstatus;
1466 	for (i = 0; i < ch->numslots; i++) {
1467 		if ((ok >> i) & 1)
1468 			ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE);
1469 	}
1470 	/* On error, complete the rest of commands with error statuses. */
1471 	if (err) {
1472 		if (ch->frozen) {
1473 			union ccb *fccb = ch->frozen;
1474 			ch->frozen = NULL;
1475 			fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1476 			if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1477 				xpt_freeze_devq(fccb->ccb_h.path, 1);
1478 				fccb->ccb_h.status |= CAM_DEV_QFRZN;
1479 			}
1480 			ahci_done(ch, fccb);
1481 		}
1482 		for (i = 0; i < ch->numslots; i++) {
1483 			/* XXX: reqests in loading state. */
1484 			if (((err >> i) & 1) == 0)
1485 				continue;
1486 			if (port >= 0 &&
1487 			    ch->slot[i].ccb->ccb_h.target_id != port)
1488 				continue;
1489 			if (istatus & AHCI_P_IX_TFE) {
1490 			    if (port != -2) {
1491 				/* Task File Error */
1492 				if (ch->numtslotspd[
1493 				    ch->slot[i].ccb->ccb_h.target_id] == 0) {
1494 					/* Untagged operation. */
1495 					if (i == ccs)
1496 						et = AHCI_ERR_TFE;
1497 					else
1498 						et = AHCI_ERR_INNOCENT;
1499 				} else {
1500 					/* Tagged operation. */
1501 					et = AHCI_ERR_NCQ;
1502 				}
1503 			    } else {
1504 				et = AHCI_ERR_TFE;
1505 				ch->fatalerr = 1;
1506 			    }
1507 			} else if (istatus & AHCI_P_IX_IF) {
1508 				if (ch->numtslots == 0 && i != ccs && port != -2)
1509 					et = AHCI_ERR_INNOCENT;
1510 				else
1511 					et = AHCI_ERR_SATA;
1512 			} else
1513 				et = AHCI_ERR_INVALID;
1514 			ahci_end_transaction(&ch->slot[i], et);
1515 		}
1516 		/*
1517 		 * We can't reinit port if there are some other
1518 		 * commands active, use resume to complete them.
1519 		 */
1520 		if (ch->rslots != 0 && !ch->recoverycmd)
1521 			ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC);
1522 	}
1523 	/* Process NOTIFY events */
1524 	if (sntf)
1525 		ahci_notify_events(ch, sntf);
1526 }
1527 
1528 /* Must be called with channel locked. */
1529 static int
1530 ahci_check_collision(struct ahci_channel *ch, union ccb *ccb)
1531 {
1532 	int t = ccb->ccb_h.target_id;
1533 
1534 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1535 	    (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1536 		/* Tagged command while we have no supported tag free. */
1537 		if (((~ch->oslots) & (0xffffffff >> (32 -
1538 		    ch->curr[t].tags))) == 0)
1539 			return (1);
1540 		/* If we have FBS */
1541 		if (ch->fbs_enabled) {
1542 			/* Tagged command while untagged are active. */
1543 			if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0)
1544 				return (1);
1545 		} else {
1546 			/* Tagged command while untagged are active. */
1547 			if (ch->numrslots != 0 && ch->numtslots == 0)
1548 				return (1);
1549 			/* Tagged command while tagged to other target is active. */
1550 			if (ch->numtslots != 0 &&
1551 			    ch->taggedtarget != ccb->ccb_h.target_id)
1552 				return (1);
1553 		}
1554 	} else {
1555 		/* If we have FBS */
1556 		if (ch->fbs_enabled) {
1557 			/* Untagged command while tagged are active. */
1558 			if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0)
1559 				return (1);
1560 		} else {
1561 			/* Untagged command while tagged are active. */
1562 			if (ch->numrslots != 0 && ch->numtslots != 0)
1563 				return (1);
1564 		}
1565 	}
1566 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1567 	    (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) {
1568 		/* Atomic command while anything active. */
1569 		if (ch->numrslots != 0)
1570 			return (1);
1571 	}
1572        /* We have some atomic command running. */
1573        if (ch->aslots != 0)
1574                return (1);
1575 	return (0);
1576 }
1577 
1578 /* Must be called with channel locked. */
1579 static void
1580 ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb)
1581 {
1582 	struct ahci_slot *slot;
1583 	int tag, tags;
1584 
1585 	/* Choose empty slot. */
1586 	tags = ch->numslots;
1587 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1588 	    (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA))
1589 		tags = ch->curr[ccb->ccb_h.target_id].tags;
1590 	if (ch->lastslot + 1 < tags)
1591 		tag = ffs(~(ch->oslots >> (ch->lastslot + 1)));
1592 	else
1593 		tag = 0;
1594 	if (tag == 0 || tag + ch->lastslot >= tags)
1595 		tag = ffs(~ch->oslots) - 1;
1596 	else
1597 		tag += ch->lastslot;
1598 	ch->lastslot = tag;
1599 	/* Occupy chosen slot. */
1600 	slot = &ch->slot[tag];
1601 	slot->ccb = ccb;
1602 	/* Stop PM timer. */
1603 	if (ch->numrslots == 0 && ch->pm_level > 3)
1604 		callout_stop(&ch->pm_timer);
1605 	/* Update channel stats. */
1606 	ch->oslots |= (1 << tag);
1607 	ch->numrslots++;
1608 	ch->numrslotspd[ccb->ccb_h.target_id]++;
1609 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1610 	    (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1611 		ch->numtslots++;
1612 		ch->numtslotspd[ccb->ccb_h.target_id]++;
1613 		ch->taggedtarget = ccb->ccb_h.target_id;
1614 	}
1615 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1616 	    (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)))
1617 		ch->aslots |= (1 << tag);
1618 	if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1619 		slot->state = AHCI_SLOT_LOADING;
1620 		bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb,
1621 		    ahci_dmasetprd, slot, 0);
1622 	} else {
1623 		slot->dma.nsegs = 0;
1624 		ahci_execute_transaction(slot);
1625 	}
1626 }
1627 
1628 /* Locked by busdma engine. */
1629 static void
1630 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1631 {
1632 	struct ahci_slot *slot = arg;
1633 	struct ahci_channel *ch = slot->ch;
1634 	struct ahci_cmd_tab *ctp;
1635 	struct ahci_dma_prd *prd;
1636 	int i;
1637 
1638 	if (error) {
1639 		device_printf(ch->dev, "DMA load error\n");
1640 		ahci_end_transaction(slot, AHCI_ERR_INVALID);
1641 		return;
1642 	}
1643 	KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n"));
1644 	/* Get a piece of the workspace for this request */
1645 	ctp = (struct ahci_cmd_tab *)
1646 		(ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1647 	/* Fill S/G table */
1648 	prd = &ctp->prd_tab[0];
1649 	for (i = 0; i < nsegs; i++) {
1650 		prd[i].dba = htole64(segs[i].ds_addr);
1651 		prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK);
1652 	}
1653 	slot->dma.nsegs = nsegs;
1654 	bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1655 	    ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ?
1656 	    BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
1657 	ahci_execute_transaction(slot);
1658 }
1659 
1660 /* Must be called with channel locked. */
1661 static void
1662 ahci_execute_transaction(struct ahci_slot *slot)
1663 {
1664 	struct ahci_channel *ch = slot->ch;
1665 	struct ahci_cmd_tab *ctp;
1666 	struct ahci_cmd_list *clp;
1667 	union ccb *ccb = slot->ccb;
1668 	int port = ccb->ccb_h.target_id & 0x0f;
1669 	int fis_size, i, softreset;
1670 	uint8_t *fis = ch->dma.rfis + 0x40;
1671 	uint8_t val;
1672 	uint16_t cmd_flags;
1673 
1674 	/* Get a piece of the workspace for this request */
1675 	ctp = (struct ahci_cmd_tab *)
1676 		(ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1677 	/* Setup the FIS for this request */
1678 	if (!(fis_size = ahci_setup_fis(ch, ctp, ccb, slot->slot))) {
1679 		device_printf(ch->dev, "Setting up SATA FIS failed\n");
1680 		ahci_end_transaction(slot, AHCI_ERR_INVALID);
1681 		return;
1682 	}
1683 	/* Setup the command list entry */
1684 	clp = (struct ahci_cmd_list *)
1685 	    (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1686 	cmd_flags =
1687 		    (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) |
1688 		    (ccb->ccb_h.func_code == XPT_SCSI_IO ?
1689 		     (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) |
1690 		    (fis_size / sizeof(u_int32_t)) |
1691 		    (port << 12);
1692 	clp->prd_length = htole16(slot->dma.nsegs);
1693 	/* Special handling for Soft Reset command. */
1694 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1695 	    (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) {
1696 		if (ccb->ataio.cmd.control & ATA_A_RESET) {
1697 			softreset = 1;
1698 			/* Kick controller into sane state */
1699 			ahci_stop(ch);
1700 			ahci_clo(ch);
1701 			ahci_start(ch, 0);
1702 			cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY;
1703 		} else {
1704 			softreset = 2;
1705 			/* Prepare FIS receive area for check. */
1706 			for (i = 0; i < 20; i++)
1707 				fis[i] = 0xff;
1708 		}
1709 	} else
1710 		softreset = 0;
1711 	clp->bytecount = 0;
1712 	clp->cmd_flags = htole16(cmd_flags);
1713 	clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET +
1714 				  (AHCI_CT_SIZE * slot->slot));
1715 	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1716 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1717 	bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1718 	    BUS_DMASYNC_PREREAD);
1719 	/* Set ACTIVE bit for NCQ commands. */
1720 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1721 	    (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1722 		ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot);
1723 	}
1724 	/* If FBS is enabled, set PMP port. */
1725 	if (ch->fbs_enabled) {
1726 		ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN |
1727 		    (port << AHCI_P_FBS_DEV_SHIFT));
1728 	}
1729 	/* Issue command to the controller. */
1730 	slot->state = AHCI_SLOT_RUNNING;
1731 	ch->rslots |= (1 << slot->slot);
1732 	ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot));
1733 	/* Device reset commands doesn't interrupt. Poll them. */
1734 	if (ccb->ccb_h.func_code == XPT_ATA_IO &&
1735 	    (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) {
1736 		int count, timeout = ccb->ccb_h.timeout * 100;
1737 		enum ahci_err_type et = AHCI_ERR_NONE;
1738 
1739 		for (count = 0; count < timeout; count++) {
1740 			DELAY(10);
1741 			if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot)))
1742 				break;
1743 			if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) &&
1744 			    softreset != 1) {
1745 #if 0
1746 				device_printf(ch->dev,
1747 				    "Poll error on slot %d, TFD: %04x\n",
1748 				    slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD));
1749 #endif
1750 				et = AHCI_ERR_TFE;
1751 				break;
1752 			}
1753 			/* Workaround for ATI SB600/SB700 chipsets. */
1754 			if (ccb->ccb_h.target_id == 15 &&
1755 			    (ch->quirks & AHCI_Q_ATI_PMP_BUG) &&
1756 			    (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) {
1757 				et = AHCI_ERR_TIMEOUT;
1758 				break;
1759 			}
1760 		}
1761 
1762 		/*
1763 		 * Some Marvell controllers require additional time
1764 		 * after soft reset to work properly. Setup delay
1765 		 * to 50ms after soft reset.
1766 		 */
1767 		if (ch->quirks & AHCI_Q_MRVL_SR_DEL)
1768 			DELAY(50000);
1769 
1770 		/*
1771 		 * Marvell HBAs with non-RAID firmware do not wait for
1772 		 * readiness after soft reset, so we have to wait here.
1773 		 * Marvell RAIDs do not have this problem, but instead
1774 		 * sometimes forget to update FIS receive area, breaking
1775 		 * this wait.
1776 		 */
1777 		if ((ch->quirks & AHCI_Q_NOBSYRES) == 0 &&
1778 		    (ch->quirks & AHCI_Q_ATI_PMP_BUG) == 0 &&
1779 		    softreset == 2 && et == AHCI_ERR_NONE) {
1780 			for ( ; count < timeout; count++) {
1781 				bus_dmamap_sync(ch->dma.rfis_tag,
1782 				    ch->dma.rfis_map, BUS_DMASYNC_POSTREAD);
1783 				val = fis[2];
1784 				bus_dmamap_sync(ch->dma.rfis_tag,
1785 				    ch->dma.rfis_map, BUS_DMASYNC_PREREAD);
1786 				if ((val & ATA_S_BUSY) == 0)
1787 					break;
1788 				DELAY(10);
1789 			}
1790 		}
1791 
1792 		if (timeout && (count >= timeout)) {
1793 			device_printf(ch->dev, "Poll timeout on slot %d port %d\n",
1794 			    slot->slot, port);
1795 			device_printf(ch->dev, "is %08x cs %08x ss %08x "
1796 			    "rs %08x tfd %02x serr %08x cmd %08x\n",
1797 			    ATA_INL(ch->r_mem, AHCI_P_IS),
1798 			    ATA_INL(ch->r_mem, AHCI_P_CI),
1799 			    ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1800 			    ATA_INL(ch->r_mem, AHCI_P_TFD),
1801 			    ATA_INL(ch->r_mem, AHCI_P_SERR),
1802 			    ATA_INL(ch->r_mem, AHCI_P_CMD));
1803 			et = AHCI_ERR_TIMEOUT;
1804 		}
1805 
1806 		/* Kick controller into sane state and enable FBS. */
1807 		if (softreset == 2)
1808 			ch->eslots |= (1 << slot->slot);
1809 		ahci_end_transaction(slot, et);
1810 		return;
1811 	}
1812 	/* Start command execution timeout */
1813 	callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout / 2,
1814 	    0, ahci_timeout, slot, 0);
1815 	return;
1816 }
1817 
1818 /* Must be called with channel locked. */
1819 static void
1820 ahci_process_timeout(struct ahci_channel *ch)
1821 {
1822 	int i;
1823 
1824 	mtx_assert(&ch->mtx, MA_OWNED);
1825 	/* Handle the rest of commands. */
1826 	for (i = 0; i < ch->numslots; i++) {
1827 		/* Do we have a running request on slot? */
1828 		if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1829 			continue;
1830 		ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT);
1831 	}
1832 }
1833 
1834 /* Must be called with channel locked. */
1835 static void
1836 ahci_rearm_timeout(struct ahci_channel *ch)
1837 {
1838 	int i;
1839 
1840 	mtx_assert(&ch->mtx, MA_OWNED);
1841 	for (i = 0; i < ch->numslots; i++) {
1842 		struct ahci_slot *slot = &ch->slot[i];
1843 
1844 		/* Do we have a running request on slot? */
1845 		if (slot->state < AHCI_SLOT_RUNNING)
1846 			continue;
1847 		if ((ch->toslots & (1 << i)) == 0)
1848 			continue;
1849 		callout_reset_sbt(&slot->timeout,
1850     	    	    SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0,
1851 		    ahci_timeout, slot, 0);
1852 	}
1853 }
1854 
1855 /* Locked by callout mechanism. */
1856 static void
1857 ahci_timeout(void *arg)
1858 {
1859 	struct ahci_slot *slot = arg;
1860 	struct ahci_channel *ch = slot->ch;
1861 	device_t dev = ch->dev;
1862 	uint32_t sstatus;
1863 	int ccs;
1864 	int i;
1865 
1866 	/* Check for stale timeout. */
1867 	if (slot->state < AHCI_SLOT_RUNNING)
1868 		return;
1869 
1870 	/* Check if slot was not being executed last time we checked. */
1871 	if (slot->state < AHCI_SLOT_EXECUTING) {
1872 		/* Check if slot started executing. */
1873 		sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1874 		ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
1875 		    >> AHCI_P_CMD_CCS_SHIFT;
1876 		if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot ||
1877 		    ch->fbs_enabled || ch->wrongccs)
1878 			slot->state = AHCI_SLOT_EXECUTING;
1879 		else if ((ch->rslots & (1 << ccs)) == 0) {
1880 			ch->wrongccs = 1;
1881 			slot->state = AHCI_SLOT_EXECUTING;
1882 		}
1883 
1884 		callout_reset_sbt(&slot->timeout,
1885 	    	    SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0,
1886 		    ahci_timeout, slot, 0);
1887 		return;
1888 	}
1889 
1890 	device_printf(dev, "Timeout on slot %d port %d\n",
1891 	    slot->slot, slot->ccb->ccb_h.target_id & 0x0f);
1892 	device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x "
1893 	    "serr %08x cmd %08x\n",
1894 	    ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI),
1895 	    ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1896 	    ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR),
1897 	    ATA_INL(ch->r_mem, AHCI_P_CMD));
1898 
1899 	/* Handle frozen command. */
1900 	if (ch->frozen) {
1901 		union ccb *fccb = ch->frozen;
1902 		ch->frozen = NULL;
1903 		fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1904 		if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1905 			xpt_freeze_devq(fccb->ccb_h.path, 1);
1906 			fccb->ccb_h.status |= CAM_DEV_QFRZN;
1907 		}
1908 		ahci_done(ch, fccb);
1909 	}
1910 	if (!ch->fbs_enabled && !ch->wrongccs) {
1911 		/* Without FBS we know real timeout source. */
1912 		ch->fatalerr = 1;
1913 		/* Handle command with timeout. */
1914 		ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT);
1915 		/* Handle the rest of commands. */
1916 		for (i = 0; i < ch->numslots; i++) {
1917 			/* Do we have a running request on slot? */
1918 			if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1919 				continue;
1920 			ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
1921 		}
1922 	} else {
1923 		/* With FBS we wait for other commands timeout and pray. */
1924 		if (ch->toslots == 0)
1925 			xpt_freeze_simq(ch->sim, 1);
1926 		ch->toslots |= (1 << slot->slot);
1927 		if ((ch->rslots & ~ch->toslots) == 0)
1928 			ahci_process_timeout(ch);
1929 		else
1930 			device_printf(dev, " ... waiting for slots %08x\n",
1931 			    ch->rslots & ~ch->toslots);
1932 	}
1933 }
1934 
1935 /* Must be called with channel locked. */
1936 static void
1937 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et)
1938 {
1939 	struct ahci_channel *ch = slot->ch;
1940 	union ccb *ccb = slot->ccb;
1941 	struct ahci_cmd_list *clp;
1942 	int lastto;
1943 	uint32_t sig;
1944 
1945 	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1946 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1947 	clp = (struct ahci_cmd_list *)
1948 	    (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1949 	/* Read result registers to the result struct
1950 	 * May be incorrect if several commands finished same time,
1951 	 * so read only when sure or have to.
1952 	 */
1953 	if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1954 		struct ata_res *res = &ccb->ataio.res;
1955 
1956 		if ((et == AHCI_ERR_TFE) ||
1957 		    (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) {
1958 			u_int8_t *fis = ch->dma.rfis + 0x40;
1959 
1960 			bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1961 			    BUS_DMASYNC_POSTREAD);
1962 			if (ch->fbs_enabled) {
1963 				fis += ccb->ccb_h.target_id * 256;
1964 				res->status = fis[2];
1965 				res->error = fis[3];
1966 			} else {
1967 				uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD);
1968 
1969 				res->status = tfd;
1970 				res->error = tfd >> 8;
1971 			}
1972 			res->lba_low = fis[4];
1973 			res->lba_mid = fis[5];
1974 			res->lba_high = fis[6];
1975 			res->device = fis[7];
1976 			res->lba_low_exp = fis[8];
1977 			res->lba_mid_exp = fis[9];
1978 			res->lba_high_exp = fis[10];
1979 			res->sector_count = fis[12];
1980 			res->sector_count_exp = fis[13];
1981 
1982 			/*
1983 			 * Some weird controllers do not return signature in
1984 			 * FIS receive area. Read it from PxSIG register.
1985 			 */
1986 			if ((ch->quirks & AHCI_Q_ALTSIG) &&
1987 			    (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
1988 			    (ccb->ataio.cmd.control & ATA_A_RESET) == 0) {
1989 				sig = ATA_INL(ch->r_mem,  AHCI_P_SIG);
1990 				res->lba_high = sig >> 24;
1991 				res->lba_mid = sig >> 16;
1992 				res->lba_low = sig >> 8;
1993 				res->sector_count = sig;
1994 			}
1995 		} else
1996 			bzero(res, sizeof(*res));
1997 		if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 &&
1998 		    (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
1999 		    (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
2000 			ccb->ataio.resid =
2001 			    ccb->ataio.dxfer_len - le32toh(clp->bytecount);
2002 		}
2003 	} else {
2004 		if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2005 		    (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
2006 			ccb->csio.resid =
2007 			    ccb->csio.dxfer_len - le32toh(clp->bytecount);
2008 		}
2009 	}
2010 	if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
2011 		bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
2012 		    (ccb->ccb_h.flags & CAM_DIR_IN) ?
2013 		    BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
2014 		bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map);
2015 	}
2016 	if (et != AHCI_ERR_NONE)
2017 		ch->eslots |= (1 << slot->slot);
2018 	/* In case of error, freeze device for proper recovery. */
2019 	if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) &&
2020 	    !(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
2021 		xpt_freeze_devq(ccb->ccb_h.path, 1);
2022 		ccb->ccb_h.status |= CAM_DEV_QFRZN;
2023 	}
2024 	/* Set proper result status. */
2025 	ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2026 	switch (et) {
2027 	case AHCI_ERR_NONE:
2028 		ccb->ccb_h.status |= CAM_REQ_CMP;
2029 		if (ccb->ccb_h.func_code == XPT_SCSI_IO)
2030 			ccb->csio.scsi_status = SCSI_STATUS_OK;
2031 		break;
2032 	case AHCI_ERR_INVALID:
2033 		ch->fatalerr = 1;
2034 		ccb->ccb_h.status |= CAM_REQ_INVALID;
2035 		break;
2036 	case AHCI_ERR_INNOCENT:
2037 		ccb->ccb_h.status |= CAM_REQUEUE_REQ;
2038 		break;
2039 	case AHCI_ERR_TFE:
2040 	case AHCI_ERR_NCQ:
2041 		if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2042 			ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
2043 			ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
2044 		} else {
2045 			ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
2046 		}
2047 		break;
2048 	case AHCI_ERR_SATA:
2049 		ch->fatalerr = 1;
2050 		if (!ch->recoverycmd) {
2051 			xpt_freeze_simq(ch->sim, 1);
2052 			ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2053 			ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2054 		}
2055 		ccb->ccb_h.status |= CAM_UNCOR_PARITY;
2056 		break;
2057 	case AHCI_ERR_TIMEOUT:
2058 		if (!ch->recoverycmd) {
2059 			xpt_freeze_simq(ch->sim, 1);
2060 			ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2061 			ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2062 		}
2063 		ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
2064 		break;
2065 	default:
2066 		ch->fatalerr = 1;
2067 		ccb->ccb_h.status |= CAM_REQ_CMP_ERR;
2068 	}
2069 	/* Free slot. */
2070 	ch->oslots &= ~(1 << slot->slot);
2071 	ch->rslots &= ~(1 << slot->slot);
2072 	ch->aslots &= ~(1 << slot->slot);
2073 	slot->state = AHCI_SLOT_EMPTY;
2074 	slot->ccb = NULL;
2075 	/* Update channel stats. */
2076 	ch->numrslots--;
2077 	ch->numrslotspd[ccb->ccb_h.target_id]--;
2078 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
2079 	    (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
2080 		ch->numtslots--;
2081 		ch->numtslotspd[ccb->ccb_h.target_id]--;
2082 	}
2083 	/* Cancel timeout state if request completed normally. */
2084 	if (et != AHCI_ERR_TIMEOUT) {
2085 		lastto = (ch->toslots == (1 << slot->slot));
2086 		ch->toslots &= ~(1 << slot->slot);
2087 		if (lastto)
2088 			xpt_release_simq(ch->sim, TRUE);
2089 	}
2090 	/* If it was first request of reset sequence and there is no error,
2091 	 * proceed to second request. */
2092 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
2093 	    (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
2094 	    (ccb->ataio.cmd.control & ATA_A_RESET) &&
2095 	    et == AHCI_ERR_NONE) {
2096 		ccb->ataio.cmd.control &= ~ATA_A_RESET;
2097 		ahci_begin_transaction(ch, ccb);
2098 		return;
2099 	}
2100 	/* If it was our READ LOG command - process it. */
2101 	if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) {
2102 		ahci_process_read_log(ch, ccb);
2103 	/* If it was our REQUEST SENSE command - process it. */
2104 	} else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) {
2105 		ahci_process_request_sense(ch, ccb);
2106 	/* If it was NCQ or ATAPI command error, put result on hold. */
2107 	} else if (et == AHCI_ERR_NCQ ||
2108 	    ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR &&
2109 	     (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) {
2110 		ch->hold[slot->slot] = ccb;
2111 		ch->numhslots++;
2112 	} else
2113 		ahci_done(ch, ccb);
2114 	/* If we have no other active commands, ... */
2115 	if (ch->rslots == 0) {
2116 		/* if there was fatal error - reset port. */
2117 		if (ch->toslots != 0 || ch->fatalerr) {
2118 			ahci_reset(ch);
2119 		} else {
2120 			/* if we have slots in error, we can reinit port. */
2121 			if (ch->eslots != 0) {
2122 				ahci_stop(ch);
2123 				ahci_clo(ch);
2124 				ahci_start(ch, 1);
2125 			}
2126 			/* if there commands on hold, we can do READ LOG. */
2127 			if (!ch->recoverycmd && ch->numhslots)
2128 				ahci_issue_recovery(ch);
2129 		}
2130 	/* If all the rest of commands are in timeout - give them chance. */
2131 	} else if ((ch->rslots & ~ch->toslots) == 0 &&
2132 	    et != AHCI_ERR_TIMEOUT)
2133 		ahci_rearm_timeout(ch);
2134 	/* Unfreeze frozen command. */
2135 	if (ch->frozen && !ahci_check_collision(ch, ch->frozen)) {
2136 		union ccb *fccb = ch->frozen;
2137 		ch->frozen = NULL;
2138 		ahci_begin_transaction(ch, fccb);
2139 		xpt_release_simq(ch->sim, TRUE);
2140 	}
2141 	/* Start PM timer. */
2142 	if (ch->numrslots == 0 && ch->pm_level > 3 &&
2143 	    (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) {
2144 		callout_schedule(&ch->pm_timer,
2145 		    (ch->pm_level == 4) ? hz / 1000 : hz / 8);
2146 	}
2147 }
2148 
2149 static void
2150 ahci_issue_recovery(struct ahci_channel *ch)
2151 {
2152 	union ccb *ccb;
2153 	struct ccb_ataio *ataio;
2154 	struct ccb_scsiio *csio;
2155 	int i;
2156 
2157 	/* Find some held command. */
2158 	for (i = 0; i < ch->numslots; i++) {
2159 		if (ch->hold[i])
2160 			break;
2161 	}
2162 	ccb = xpt_alloc_ccb_nowait();
2163 	if (ccb == NULL) {
2164 		device_printf(ch->dev, "Unable to allocate recovery command\n");
2165 completeall:
2166 		/* We can't do anything -- complete held commands. */
2167 		for (i = 0; i < ch->numslots; i++) {
2168 			if (ch->hold[i] == NULL)
2169 				continue;
2170 			ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2171 			ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL;
2172 			ahci_done(ch, ch->hold[i]);
2173 			ch->hold[i] = NULL;
2174 			ch->numhslots--;
2175 		}
2176 		ahci_reset(ch);
2177 		return;
2178 	}
2179 	ccb->ccb_h = ch->hold[i]->ccb_h;	/* Reuse old header. */
2180 	if (ccb->ccb_h.func_code == XPT_ATA_IO) {
2181 		/* READ LOG */
2182 		ccb->ccb_h.recovery_type = RECOVERY_READ_LOG;
2183 		ccb->ccb_h.func_code = XPT_ATA_IO;
2184 		ccb->ccb_h.flags = CAM_DIR_IN;
2185 		ccb->ccb_h.timeout = 1000;	/* 1s should be enough. */
2186 		ataio = &ccb->ataio;
2187 		ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT);
2188 		if (ataio->data_ptr == NULL) {
2189 			xpt_free_ccb(ccb);
2190 			device_printf(ch->dev,
2191 			    "Unable to allocate memory for READ LOG command\n");
2192 			goto completeall;
2193 		}
2194 		ataio->dxfer_len = 512;
2195 		bzero(&ataio->cmd, sizeof(ataio->cmd));
2196 		ataio->cmd.flags = CAM_ATAIO_48BIT;
2197 		ataio->cmd.command = 0x2F;	/* READ LOG EXT */
2198 		ataio->cmd.sector_count = 1;
2199 		ataio->cmd.sector_count_exp = 0;
2200 		ataio->cmd.lba_low = 0x10;
2201 		ataio->cmd.lba_mid = 0;
2202 		ataio->cmd.lba_mid_exp = 0;
2203 	} else {
2204 		/* REQUEST SENSE */
2205 		ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE;
2206 		ccb->ccb_h.recovery_slot = i;
2207 		ccb->ccb_h.func_code = XPT_SCSI_IO;
2208 		ccb->ccb_h.flags = CAM_DIR_IN;
2209 		ccb->ccb_h.status = 0;
2210 		ccb->ccb_h.timeout = 1000;	/* 1s should be enough. */
2211 		csio = &ccb->csio;
2212 		csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data;
2213 		csio->dxfer_len = ch->hold[i]->csio.sense_len;
2214 		csio->cdb_len = 6;
2215 		bzero(&csio->cdb_io, sizeof(csio->cdb_io));
2216 		csio->cdb_io.cdb_bytes[0] = 0x03;
2217 		csio->cdb_io.cdb_bytes[4] = csio->dxfer_len;
2218 	}
2219 	/* Freeze SIM while doing recovery. */
2220 	ch->recoverycmd = 1;
2221 	xpt_freeze_simq(ch->sim, 1);
2222 	ahci_begin_transaction(ch, ccb);
2223 }
2224 
2225 static void
2226 ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb)
2227 {
2228 	uint8_t *data;
2229 	struct ata_res *res;
2230 	int i;
2231 
2232 	ch->recoverycmd = 0;
2233 
2234 	data = ccb->ataio.data_ptr;
2235 	if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP &&
2236 	    (data[0] & 0x80) == 0) {
2237 		for (i = 0; i < ch->numslots; i++) {
2238 			if (!ch->hold[i])
2239 				continue;
2240 			if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2241 				continue;
2242 			if ((data[0] & 0x1F) == i) {
2243 				res = &ch->hold[i]->ataio.res;
2244 				res->status = data[2];
2245 				res->error = data[3];
2246 				res->lba_low = data[4];
2247 				res->lba_mid = data[5];
2248 				res->lba_high = data[6];
2249 				res->device = data[7];
2250 				res->lba_low_exp = data[8];
2251 				res->lba_mid_exp = data[9];
2252 				res->lba_high_exp = data[10];
2253 				res->sector_count = data[12];
2254 				res->sector_count_exp = data[13];
2255 			} else {
2256 				ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2257 				ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ;
2258 			}
2259 			ahci_done(ch, ch->hold[i]);
2260 			ch->hold[i] = NULL;
2261 			ch->numhslots--;
2262 		}
2263 	} else {
2264 		if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP)
2265 			device_printf(ch->dev, "Error while READ LOG EXT\n");
2266 		else if ((data[0] & 0x80) == 0) {
2267 			device_printf(ch->dev, "Non-queued command error in READ LOG EXT\n");
2268 		}
2269 		for (i = 0; i < ch->numslots; i++) {
2270 			if (!ch->hold[i])
2271 				continue;
2272 			if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2273 				continue;
2274 			ahci_done(ch, ch->hold[i]);
2275 			ch->hold[i] = NULL;
2276 			ch->numhslots--;
2277 		}
2278 	}
2279 	free(ccb->ataio.data_ptr, M_AHCI);
2280 	xpt_free_ccb(ccb);
2281 	xpt_release_simq(ch->sim, TRUE);
2282 }
2283 
2284 static void
2285 ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb)
2286 {
2287 	int i;
2288 
2289 	ch->recoverycmd = 0;
2290 
2291 	i = ccb->ccb_h.recovery_slot;
2292 	if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) {
2293 		ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID;
2294 	} else {
2295 		ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2296 		ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL;
2297 	}
2298 	ahci_done(ch, ch->hold[i]);
2299 	ch->hold[i] = NULL;
2300 	ch->numhslots--;
2301 	xpt_free_ccb(ccb);
2302 	xpt_release_simq(ch->sim, TRUE);
2303 }
2304 
2305 static void
2306 ahci_start(struct ahci_channel *ch, int fbs)
2307 {
2308 	u_int32_t cmd;
2309 
2310 	/* Run the channel start callback, if any. */
2311 	if (ch->start)
2312 		ch->start(ch);
2313 
2314 	/* Clear SATA error register */
2315 	ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF);
2316 	/* Clear any interrupts pending on this channel */
2317 	ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF);
2318 	/* Configure FIS-based switching if supported. */
2319 	if (ch->chcaps & AHCI_P_CMD_FBSCP) {
2320 		ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0;
2321 		ATA_OUTL(ch->r_mem, AHCI_P_FBS,
2322 		    ch->fbs_enabled ? AHCI_P_FBS_EN : 0);
2323 	}
2324 	/* Start operations on this channel */
2325 	cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2326 	cmd &= ~AHCI_P_CMD_PMA;
2327 	ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST |
2328 	    (ch->pm_present ? AHCI_P_CMD_PMA : 0));
2329 }
2330 
2331 static void
2332 ahci_stop(struct ahci_channel *ch)
2333 {
2334 	u_int32_t cmd;
2335 	int timeout;
2336 
2337 	/* Kill all activity on this channel */
2338 	cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2339 	ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST);
2340 	/* Wait for activity stop. */
2341 	timeout = 0;
2342 	do {
2343 		DELAY(10);
2344 		if (timeout++ > 50000) {
2345 			device_printf(ch->dev, "stopping AHCI engine failed\n");
2346 			break;
2347 		}
2348 	} while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR);
2349 	ch->eslots = 0;
2350 }
2351 
2352 static void
2353 ahci_clo(struct ahci_channel *ch)
2354 {
2355 	u_int32_t cmd;
2356 	int timeout;
2357 
2358 	/* Issue Command List Override if supported */
2359 	if (ch->caps & AHCI_CAP_SCLO) {
2360 		cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2361 		cmd |= AHCI_P_CMD_CLO;
2362 		ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd);
2363 		timeout = 0;
2364 		do {
2365 			DELAY(10);
2366 			if (timeout++ > 50000) {
2367 			    device_printf(ch->dev, "executing CLO failed\n");
2368 			    break;
2369 			}
2370 		} while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO);
2371 	}
2372 }
2373 
2374 static void
2375 ahci_stop_fr(struct ahci_channel *ch)
2376 {
2377 	u_int32_t cmd;
2378 	int timeout;
2379 
2380 	/* Kill all FIS reception on this channel */
2381 	cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2382 	ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE);
2383 	/* Wait for FIS reception stop. */
2384 	timeout = 0;
2385 	do {
2386 		DELAY(10);
2387 		if (timeout++ > 50000) {
2388 			device_printf(ch->dev, "stopping AHCI FR engine failed\n");
2389 			break;
2390 		}
2391 	} while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR);
2392 }
2393 
2394 static void
2395 ahci_start_fr(struct ahci_channel *ch)
2396 {
2397 	u_int32_t cmd;
2398 
2399 	/* Start FIS reception on this channel */
2400 	cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2401 	ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE);
2402 }
2403 
2404 static int
2405 ahci_wait_ready(struct ahci_channel *ch, int t, int t0)
2406 {
2407 	int timeout = 0;
2408 	uint32_t val;
2409 
2410 	while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) &
2411 	    (ATA_S_BUSY | ATA_S_DRQ)) {
2412 		if (timeout > t) {
2413 			if (t != 0) {
2414 				device_printf(ch->dev,
2415 				    "AHCI reset: device not ready after %dms "
2416 				    "(tfd = %08x)\n",
2417 				    MAX(t, 0) + t0, val);
2418 			}
2419 			return (EBUSY);
2420 		}
2421 		DELAY(1000);
2422 		timeout++;
2423 	}
2424 	if (bootverbose)
2425 		device_printf(ch->dev, "AHCI reset: device ready after %dms\n",
2426 		    timeout + t0);
2427 	return (0);
2428 }
2429 
2430 static void
2431 ahci_reset_to(void *arg)
2432 {
2433 	struct ahci_channel *ch = arg;
2434 
2435 	if (ch->resetting == 0)
2436 		return;
2437 	ch->resetting--;
2438 	if (ahci_wait_ready(ch, ch->resetting == 0 ? -1 : 0,
2439 	    (310 - ch->resetting) * 100) == 0) {
2440 		ch->resetting = 0;
2441 		ahci_start(ch, 1);
2442 		xpt_release_simq(ch->sim, TRUE);
2443 		return;
2444 	}
2445 	if (ch->resetting == 0) {
2446 		ahci_clo(ch);
2447 		ahci_start(ch, 1);
2448 		xpt_release_simq(ch->sim, TRUE);
2449 		return;
2450 	}
2451 	callout_schedule(&ch->reset_timer, hz / 10);
2452 }
2453 
2454 static void
2455 ahci_reset(struct ahci_channel *ch)
2456 {
2457 	struct ahci_controller *ctlr = device_get_softc(device_get_parent(ch->dev));
2458 	int i;
2459 
2460 	xpt_freeze_simq(ch->sim, 1);
2461 	if (bootverbose)
2462 		device_printf(ch->dev, "AHCI reset...\n");
2463 	/* Forget about previous reset. */
2464 	if (ch->resetting) {
2465 		ch->resetting = 0;
2466 		callout_stop(&ch->reset_timer);
2467 		xpt_release_simq(ch->sim, TRUE);
2468 	}
2469 	/* Requeue freezed command. */
2470 	if (ch->frozen) {
2471 		union ccb *fccb = ch->frozen;
2472 		ch->frozen = NULL;
2473 		fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
2474 		if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
2475 			xpt_freeze_devq(fccb->ccb_h.path, 1);
2476 			fccb->ccb_h.status |= CAM_DEV_QFRZN;
2477 		}
2478 		ahci_done(ch, fccb);
2479 	}
2480 	/* Kill the engine and requeue all running commands. */
2481 	ahci_stop(ch);
2482 	for (i = 0; i < ch->numslots; i++) {
2483 		/* Do we have a running request on slot? */
2484 		if (ch->slot[i].state < AHCI_SLOT_RUNNING)
2485 			continue;
2486 		/* XXX; Commands in loading state. */
2487 		ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
2488 	}
2489 	for (i = 0; i < ch->numslots; i++) {
2490 		if (!ch->hold[i])
2491 			continue;
2492 		ahci_done(ch, ch->hold[i]);
2493 		ch->hold[i] = NULL;
2494 		ch->numhslots--;
2495 	}
2496 	if (ch->toslots != 0)
2497 		xpt_release_simq(ch->sim, TRUE);
2498 	ch->eslots = 0;
2499 	ch->toslots = 0;
2500 	ch->wrongccs = 0;
2501 	ch->fatalerr = 0;
2502 	/* Tell the XPT about the event */
2503 	xpt_async(AC_BUS_RESET, ch->path, NULL);
2504 	/* Disable port interrupts */
2505 	ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
2506 	/* Reset and reconnect PHY, */
2507 	if (!ahci_sata_phy_reset(ch)) {
2508 		if (bootverbose)
2509 			device_printf(ch->dev,
2510 			    "AHCI reset: device not found\n");
2511 		ch->devices = 0;
2512 		/* Enable wanted port interrupts */
2513 		ATA_OUTL(ch->r_mem, AHCI_P_IE,
2514 		    (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2515 		     AHCI_P_IX_PRC | AHCI_P_IX_PC));
2516 		xpt_release_simq(ch->sim, TRUE);
2517 		return;
2518 	}
2519 	if (bootverbose)
2520 		device_printf(ch->dev, "AHCI reset: device found\n");
2521 	/* Wait for clearing busy status. */
2522 	if (ahci_wait_ready(ch, dumping ? 31000 : 0, 0)) {
2523 		if (dumping)
2524 			ahci_clo(ch);
2525 		else
2526 			ch->resetting = 310;
2527 	}
2528 	ch->devices = 1;
2529 	/* Enable wanted port interrupts */
2530 	ATA_OUTL(ch->r_mem, AHCI_P_IE,
2531 	     (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2532 	      AHCI_P_IX_TFE | AHCI_P_IX_HBF |
2533 	      AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF |
2534 	      ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC |
2535 	      AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) |
2536 	      AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR)));
2537 	if (ch->resetting)
2538 		callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, ch);
2539 	else {
2540 		ahci_start(ch, 1);
2541 		xpt_release_simq(ch->sim, TRUE);
2542 	}
2543 }
2544 
2545 static int
2546 ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag)
2547 {
2548 	u_int8_t *fis = &ctp->cfis[0];
2549 
2550 	bzero(fis, 20);
2551 	fis[0] = 0x27;  		/* host to device */
2552 	fis[1] = (ccb->ccb_h.target_id & 0x0f);
2553 	if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2554 		fis[1] |= 0x80;
2555 		fis[2] = ATA_PACKET_CMD;
2556 		if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2557 		    ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA)
2558 			fis[3] = ATA_F_DMA;
2559 		else {
2560 			fis[5] = ccb->csio.dxfer_len;
2561 		        fis[6] = ccb->csio.dxfer_len >> 8;
2562 		}
2563 		fis[7] = ATA_D_LBA;
2564 		fis[15] = ATA_A_4BIT;
2565 		bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
2566 		    ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes,
2567 		    ctp->acmd, ccb->csio.cdb_len);
2568 		bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len);
2569 	} else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) {
2570 		fis[1] |= 0x80;
2571 		fis[2] = ccb->ataio.cmd.command;
2572 		fis[3] = ccb->ataio.cmd.features;
2573 		fis[4] = ccb->ataio.cmd.lba_low;
2574 		fis[5] = ccb->ataio.cmd.lba_mid;
2575 		fis[6] = ccb->ataio.cmd.lba_high;
2576 		fis[7] = ccb->ataio.cmd.device;
2577 		fis[8] = ccb->ataio.cmd.lba_low_exp;
2578 		fis[9] = ccb->ataio.cmd.lba_mid_exp;
2579 		fis[10] = ccb->ataio.cmd.lba_high_exp;
2580 		fis[11] = ccb->ataio.cmd.features_exp;
2581 		fis[12] = ccb->ataio.cmd.sector_count;
2582 		if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
2583 			fis[12] &= 0xf8;
2584 			fis[12] |= tag << 3;
2585 		}
2586 		fis[13] = ccb->ataio.cmd.sector_count_exp;
2587 		if (ccb->ataio.ata_flags & ATA_FLAG_ICC)
2588 			fis[14] = ccb->ataio.icc;
2589 		fis[15] = ATA_A_4BIT;
2590 		if (ccb->ataio.ata_flags & ATA_FLAG_AUX) {
2591 			fis[16] =  ccb->ataio.aux        & 0xff;
2592 			fis[17] = (ccb->ataio.aux >>  8) & 0xff;
2593 			fis[18] = (ccb->ataio.aux >> 16) & 0xff;
2594 			fis[19] = (ccb->ataio.aux >> 24) & 0xff;
2595 		}
2596 	} else {
2597 		fis[15] = ccb->ataio.cmd.control;
2598 	}
2599 	return (20);
2600 }
2601 
2602 static int
2603 ahci_sata_connect(struct ahci_channel *ch)
2604 {
2605 	u_int32_t status;
2606 	int timeout, found = 0;
2607 
2608 	/* Wait up to 100ms for "connect well" */
2609 	for (timeout = 0; timeout < 1000 ; timeout++) {
2610 		status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
2611 		if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
2612 			found = 1;
2613 		if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
2614 		    ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
2615 		    ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE))
2616 			break;
2617 		if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) {
2618 			if (bootverbose) {
2619 				device_printf(ch->dev, "SATA offline status=%08x\n",
2620 				    status);
2621 			}
2622 			return (0);
2623 		}
2624 		if (found == 0 && timeout >= 100)
2625 			break;
2626 		DELAY(100);
2627 	}
2628 	if (timeout >= 1000 || !found) {
2629 		if (bootverbose) {
2630 			device_printf(ch->dev,
2631 			    "SATA connect timeout time=%dus status=%08x\n",
2632 			    timeout * 100, status);
2633 		}
2634 		return (0);
2635 	}
2636 	if (bootverbose) {
2637 		device_printf(ch->dev, "SATA connect time=%dus status=%08x\n",
2638 		    timeout * 100, status);
2639 	}
2640 	/* Clear SATA error register */
2641 	ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff);
2642 	return (1);
2643 }
2644 
2645 static int
2646 ahci_sata_phy_reset(struct ahci_channel *ch)
2647 {
2648 	int sata_rev;
2649 	uint32_t val, detval;
2650 
2651 	if (ch->listening) {
2652 		val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2653 		val |= AHCI_P_CMD_SUD;
2654 		ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2655 		ch->listening = 0;
2656 	}
2657 	sata_rev = ch->user[ch->pm_present ? 15 : 0].revision;
2658 	if (sata_rev == 1)
2659 		val = ATA_SC_SPD_SPEED_GEN1;
2660 	else if (sata_rev == 2)
2661 		val = ATA_SC_SPD_SPEED_GEN2;
2662 	else if (sata_rev == 3)
2663 		val = ATA_SC_SPD_SPEED_GEN3;
2664 	else
2665 		val = 0;
2666 	detval = ahci_ch_detval(ch, ATA_SC_DET_RESET);
2667 	ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2668 	    detval | val |
2669 	    ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER);
2670 	DELAY(1000);
2671 	detval = ahci_ch_detval(ch, ATA_SC_DET_IDLE);
2672 	ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2673 	    detval | val | ((ch->pm_level > 0) ? 0 :
2674 	    (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)));
2675 	if (!ahci_sata_connect(ch)) {
2676 		if (ch->caps & AHCI_CAP_SSS) {
2677 			val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2678 			val &= ~AHCI_P_CMD_SUD;
2679 			ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2680 			ch->listening = 1;
2681 		} else if (ch->pm_level > 0)
2682 			ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
2683 		return (0);
2684 	}
2685 	return (1);
2686 }
2687 
2688 static int
2689 ahci_check_ids(struct ahci_channel *ch, union ccb *ccb)
2690 {
2691 
2692 	if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) {
2693 		ccb->ccb_h.status = CAM_TID_INVALID;
2694 		ahci_done(ch, ccb);
2695 		return (-1);
2696 	}
2697 	if (ccb->ccb_h.target_lun != 0) {
2698 		ccb->ccb_h.status = CAM_LUN_INVALID;
2699 		ahci_done(ch, ccb);
2700 		return (-1);
2701 	}
2702 	return (0);
2703 }
2704 
2705 static void
2706 ahciaction(struct cam_sim *sim, union ccb *ccb)
2707 {
2708 	struct ahci_channel *ch;
2709 
2710 	CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n",
2711 	    ccb->ccb_h.func_code));
2712 
2713 	ch = (struct ahci_channel *)cam_sim_softc(sim);
2714 	switch (ccb->ccb_h.func_code) {
2715 	/* Common cases first */
2716 	case XPT_ATA_IO:	/* Execute the requested I/O operation */
2717 	case XPT_SCSI_IO:
2718 		if (ahci_check_ids(ch, ccb))
2719 			return;
2720 		if (ch->devices == 0 ||
2721 		    (ch->pm_present == 0 &&
2722 		     ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) {
2723 			ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2724 			break;
2725 		}
2726 		ccb->ccb_h.recovery_type = RECOVERY_NONE;
2727 		/* Check for command collision. */
2728 		if (ahci_check_collision(ch, ccb)) {
2729 			/* Freeze command. */
2730 			ch->frozen = ccb;
2731 			/* We have only one frozen slot, so freeze simq also. */
2732 			xpt_freeze_simq(ch->sim, 1);
2733 			return;
2734 		}
2735 		ahci_begin_transaction(ch, ccb);
2736 		return;
2737 	case XPT_ABORT:			/* Abort the specified CCB */
2738 		/* XXX Implement */
2739 		ccb->ccb_h.status = CAM_REQ_INVALID;
2740 		break;
2741 	case XPT_SET_TRAN_SETTINGS:
2742 	{
2743 		struct	ccb_trans_settings *cts = &ccb->cts;
2744 		struct	ahci_device *d;
2745 
2746 		if (ahci_check_ids(ch, ccb))
2747 			return;
2748 		if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2749 			d = &ch->curr[ccb->ccb_h.target_id];
2750 		else
2751 			d = &ch->user[ccb->ccb_h.target_id];
2752 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION)
2753 			d->revision = cts->xport_specific.sata.revision;
2754 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE)
2755 			d->mode = cts->xport_specific.sata.mode;
2756 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT)
2757 			d->bytecount = min(8192, cts->xport_specific.sata.bytecount);
2758 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS)
2759 			d->tags = min(ch->numslots, cts->xport_specific.sata.tags);
2760 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM)
2761 			ch->pm_present = cts->xport_specific.sata.pm_present;
2762 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI)
2763 			d->atapi = cts->xport_specific.sata.atapi;
2764 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
2765 			d->caps = cts->xport_specific.sata.caps;
2766 		ccb->ccb_h.status = CAM_REQ_CMP;
2767 		break;
2768 	}
2769 	case XPT_GET_TRAN_SETTINGS:
2770 	/* Get default/user set transfer settings for the target */
2771 	{
2772 		struct	ccb_trans_settings *cts = &ccb->cts;
2773 		struct  ahci_device *d;
2774 		uint32_t status;
2775 
2776 		if (ahci_check_ids(ch, ccb))
2777 			return;
2778 		if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2779 			d = &ch->curr[ccb->ccb_h.target_id];
2780 		else
2781 			d = &ch->user[ccb->ccb_h.target_id];
2782 		cts->protocol = PROTO_UNSPECIFIED;
2783 		cts->protocol_version = PROTO_VERSION_UNSPECIFIED;
2784 		cts->transport = XPORT_SATA;
2785 		cts->transport_version = XPORT_VERSION_UNSPECIFIED;
2786 		cts->proto_specific.valid = 0;
2787 		cts->xport_specific.sata.valid = 0;
2788 		if (cts->type == CTS_TYPE_CURRENT_SETTINGS &&
2789 		    (ccb->ccb_h.target_id == 15 ||
2790 		    (ccb->ccb_h.target_id == 0 && !ch->pm_present))) {
2791 			status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK;
2792 			if (status & 0x0f0) {
2793 				cts->xport_specific.sata.revision =
2794 				    (status & 0x0f0) >> 4;
2795 				cts->xport_specific.sata.valid |=
2796 				    CTS_SATA_VALID_REVISION;
2797 			}
2798 			cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D;
2799 			if (ch->pm_level) {
2800 				if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC))
2801 					cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ;
2802 				if (ch->caps2 & AHCI_CAP2_APST)
2803 					cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST;
2804 			}
2805 			if ((ch->caps & AHCI_CAP_SNCQ) &&
2806 			    (ch->quirks & AHCI_Q_NOAA) == 0)
2807 				cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA;
2808 			cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN;
2809 			cts->xport_specific.sata.caps &=
2810 			    ch->user[ccb->ccb_h.target_id].caps;
2811 			cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2812 		} else {
2813 			cts->xport_specific.sata.revision = d->revision;
2814 			cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION;
2815 			cts->xport_specific.sata.caps = d->caps;
2816 			cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2817 		}
2818 		cts->xport_specific.sata.mode = d->mode;
2819 		cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE;
2820 		cts->xport_specific.sata.bytecount = d->bytecount;
2821 		cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT;
2822 		cts->xport_specific.sata.pm_present = ch->pm_present;
2823 		cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM;
2824 		cts->xport_specific.sata.tags = d->tags;
2825 		cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS;
2826 		cts->xport_specific.sata.atapi = d->atapi;
2827 		cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI;
2828 		ccb->ccb_h.status = CAM_REQ_CMP;
2829 		break;
2830 	}
2831 	case XPT_RESET_BUS:		/* Reset the specified SCSI bus */
2832 	case XPT_RESET_DEV:	/* Bus Device Reset the specified SCSI device */
2833 		ahci_reset(ch);
2834 		ccb->ccb_h.status = CAM_REQ_CMP;
2835 		break;
2836 	case XPT_TERM_IO:		/* Terminate the I/O process */
2837 		/* XXX Implement */
2838 		ccb->ccb_h.status = CAM_REQ_INVALID;
2839 		break;
2840 	case XPT_PATH_INQ:		/* Path routing inquiry */
2841 	{
2842 		struct ccb_pathinq *cpi = &ccb->cpi;
2843 
2844 		cpi->version_num = 1; /* XXX??? */
2845 		cpi->hba_inquiry = PI_SDTR_ABLE;
2846 		if (ch->caps & AHCI_CAP_SNCQ)
2847 			cpi->hba_inquiry |= PI_TAG_ABLE;
2848 		if (ch->caps & AHCI_CAP_SPM)
2849 			cpi->hba_inquiry |= PI_SATAPM;
2850 		cpi->target_sprt = 0;
2851 		cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED;
2852 		if ((ch->quirks & AHCI_Q_NOAUX) == 0)
2853 			cpi->hba_misc |= PIM_ATA_EXT;
2854 		cpi->hba_eng_cnt = 0;
2855 		if (ch->caps & AHCI_CAP_SPM)
2856 			cpi->max_target = 15;
2857 		else
2858 			cpi->max_target = 0;
2859 		cpi->max_lun = 0;
2860 		cpi->initiator_id = 0;
2861 		cpi->bus_id = cam_sim_bus(sim);
2862 		cpi->base_transfer_speed = 150000;
2863 		strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2864 		strlcpy(cpi->hba_vid, "AHCI", HBA_IDLEN);
2865 		strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2866 		cpi->unit_number = cam_sim_unit(sim);
2867 		cpi->transport = XPORT_SATA;
2868 		cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
2869 		cpi->protocol = PROTO_ATA;
2870 		cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
2871 		cpi->maxio = MAXPHYS;
2872 		/* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */
2873 		if (ch->quirks & AHCI_Q_MAXIO_64K)
2874 			cpi->maxio = min(cpi->maxio, 128 * 512);
2875 		cpi->hba_vendor = ch->vendorid;
2876 		cpi->hba_device = ch->deviceid;
2877 		cpi->hba_subvendor = ch->subvendorid;
2878 		cpi->hba_subdevice = ch->subdeviceid;
2879 		cpi->ccb_h.status = CAM_REQ_CMP;
2880 		break;
2881 	}
2882 	default:
2883 		ccb->ccb_h.status = CAM_REQ_INVALID;
2884 		break;
2885 	}
2886 	ahci_done(ch, ccb);
2887 }
2888 
2889 static void
2890 ahcipoll(struct cam_sim *sim)
2891 {
2892 	struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim);
2893 	uint32_t istatus;
2894 
2895 	/* Read interrupt statuses and process if any. */
2896 	istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
2897 	if (istatus != 0)
2898 		ahci_ch_intr_main(ch, istatus);
2899 	if (ch->resetting != 0 &&
2900 	    (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) {
2901 		ch->resetpolldiv = 1000;
2902 		ahci_reset_to(ch);
2903 	}
2904 }
2905 
2906 devclass_t ahci_devclass;
2907 
2908 MODULE_VERSION(ahci, 1);
2909 MODULE_DEPEND(ahci, cam, 1, 1, 1);
2910