1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/module.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/conf.h> 38 #include <sys/endian.h> 39 #include <sys/malloc.h> 40 #include <sys/lock.h> 41 #include <sys/mutex.h> 42 #include <sys/sysctl.h> 43 #include <machine/stdarg.h> 44 #include <machine/resource.h> 45 #include <machine/bus.h> 46 #include <sys/rman.h> 47 #include "ahci.h" 48 49 #include <cam/cam.h> 50 #include <cam/cam_ccb.h> 51 #include <cam/cam_sim.h> 52 #include <cam/cam_xpt_sim.h> 53 #include <cam/cam_debug.h> 54 55 /* local prototypes */ 56 static void ahci_intr(void *data); 57 static void ahci_intr_one(void *data); 58 static void ahci_intr_one_edge(void *data); 59 static int ahci_ch_init(device_t dev); 60 static int ahci_ch_deinit(device_t dev); 61 static int ahci_ch_suspend(device_t dev); 62 static int ahci_ch_resume(device_t dev); 63 static void ahci_ch_pm(void *arg); 64 static void ahci_ch_intr(void *arg); 65 static void ahci_ch_intr_direct(void *arg); 66 static void ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus); 67 static void ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb); 68 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 69 static void ahci_execute_transaction(struct ahci_slot *slot); 70 static void ahci_timeout(void *arg); 71 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 72 static int ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 73 static void ahci_dmainit(device_t dev); 74 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 75 static void ahci_dmafini(device_t dev); 76 static void ahci_slotsalloc(device_t dev); 77 static void ahci_slotsfree(device_t dev); 78 static void ahci_reset(struct ahci_channel *ch); 79 static void ahci_start(struct ahci_channel *ch, int fbs); 80 static void ahci_stop(struct ahci_channel *ch); 81 static void ahci_clo(struct ahci_channel *ch); 82 static void ahci_start_fr(struct ahci_channel *ch); 83 static void ahci_stop_fr(struct ahci_channel *ch); 84 static int ahci_phy_check_events(struct ahci_channel *ch, u_int32_t serr); 85 static uint32_t ahci_ch_detval(struct ahci_channel *ch, uint32_t val); 86 87 static int ahci_sata_connect(struct ahci_channel *ch); 88 static int ahci_sata_phy_reset(struct ahci_channel *ch); 89 static int ahci_wait_ready(struct ahci_channel *ch, int t, int t0); 90 91 static void ahci_issue_recovery(struct ahci_channel *ch); 92 static void ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb); 93 static void ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb); 94 95 static void ahciaction(struct cam_sim *sim, union ccb *ccb); 96 static void ahcipoll(struct cam_sim *sim); 97 98 static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 99 100 #define recovery_type spriv_field0 101 #define RECOVERY_NONE 0 102 #define RECOVERY_READ_LOG 1 103 #define RECOVERY_REQUEST_SENSE 2 104 #define recovery_slot spriv_field1 105 106 static uint32_t 107 ahci_ch_detval(struct ahci_channel *ch, uint32_t val) 108 { 109 110 return ch->disablephy ? ATA_SC_DET_DISABLE : val; 111 } 112 113 int 114 ahci_ctlr_setup(device_t dev) 115 { 116 struct ahci_controller *ctlr = device_get_softc(dev); 117 /* Clear interrupts */ 118 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 119 /* Configure CCC */ 120 if (ctlr->ccc) { 121 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 122 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 123 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 124 (4 << AHCI_CCCC_CC_SHIFT) | 125 AHCI_CCCC_EN); 126 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 127 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 128 if (bootverbose) { 129 device_printf(dev, 130 "CCC with %dms/4cmd enabled on vector %d\n", 131 ctlr->ccc, ctlr->cccv); 132 } 133 } 134 /* Enable AHCI interrupts */ 135 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 136 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 137 return (0); 138 } 139 140 int 141 ahci_ctlr_reset(device_t dev) 142 { 143 struct ahci_controller *ctlr = device_get_softc(dev); 144 uint32_t v; 145 int timeout; 146 147 /* BIOS/OS Handoff */ 148 if ((ATA_INL(ctlr->r_mem, AHCI_VS) >= 0x00010200) && 149 (ATA_INL(ctlr->r_mem, AHCI_CAP2) & AHCI_CAP2_BOH) && 150 ((v = ATA_INL(ctlr->r_mem, AHCI_BOHC)) & AHCI_BOHC_OOS) == 0) { 151 152 /* Request OS ownership. */ 153 ATA_OUTL(ctlr->r_mem, AHCI_BOHC, v | AHCI_BOHC_OOS); 154 155 /* Wait up to 2s for BIOS ownership release. */ 156 for (timeout = 0; timeout < 80; timeout++) { 157 DELAY(25000); 158 v = ATA_INL(ctlr->r_mem, AHCI_BOHC); 159 if ((v & AHCI_BOHC_BOS) == 0) 160 break; 161 if ((v & AHCI_BOHC_BB) == 0) 162 break; 163 } 164 } 165 166 /* Enable AHCI mode */ 167 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 168 /* Reset AHCI controller */ 169 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 170 for (timeout = 1000; timeout > 0; timeout--) { 171 DELAY(1000); 172 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 173 break; 174 } 175 if (timeout == 0) { 176 device_printf(dev, "AHCI controller reset failure\n"); 177 return (ENXIO); 178 } 179 /* Reenable AHCI mode */ 180 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 181 182 if (ctlr->quirks & AHCI_Q_RESTORE_CAP) { 183 /* 184 * Restore capability field. 185 * This is write to a read-only register to restore its state. 186 * On fully standard-compliant hardware this is not needed and 187 * this operation shall not take place. See ahci_pci.c for 188 * platforms using this quirk. 189 */ 190 ATA_OUTL(ctlr->r_mem, AHCI_CAP, ctlr->caps); 191 } 192 193 return (0); 194 } 195 196 197 int 198 ahci_attach(device_t dev) 199 { 200 struct ahci_controller *ctlr = device_get_softc(dev); 201 int error, i, speed, unit; 202 uint32_t u, version; 203 device_t child; 204 205 ctlr->dev = dev; 206 ctlr->ccc = 0; 207 resource_int_value(device_get_name(dev), 208 device_get_unit(dev), "ccc", &ctlr->ccc); 209 mtx_init(&ctlr->ch_mtx, "AHCI channels lock", NULL, MTX_DEF); 210 211 /* Setup our own memory management for channels. */ 212 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 213 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 214 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 215 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 216 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 217 ahci_free_mem(dev); 218 return (error); 219 } 220 if ((error = rman_manage_region(&ctlr->sc_iomem, 221 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 222 ahci_free_mem(dev); 223 rman_fini(&ctlr->sc_iomem); 224 return (error); 225 } 226 /* Get the HW capabilities */ 227 version = ATA_INL(ctlr->r_mem, AHCI_VS); 228 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 229 if (version >= 0x00010200) 230 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 231 if (ctlr->caps & AHCI_CAP_EMS) 232 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 233 234 if (ctlr->quirks & AHCI_Q_FORCE_PI) { 235 /* 236 * Enable ports. 237 * The spec says that BIOS sets up bits corresponding to 238 * available ports. On platforms where this information 239 * is missing, the driver can define available ports on its own. 240 */ 241 int nports = (ctlr->caps & AHCI_CAP_NPMASK) + 1; 242 int nmask = (1 << nports) - 1; 243 244 ATA_OUTL(ctlr->r_mem, AHCI_PI, nmask); 245 device_printf(dev, "Forcing PI to %d ports (mask = %x)\n", 246 nports, nmask); 247 } 248 249 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 250 251 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */ 252 if ((ctlr->quirks & AHCI_Q_ALTSIG) && 253 (ctlr->caps & AHCI_CAP_SPM) == 0) 254 ctlr->quirks |= AHCI_Q_NOBSYRES; 255 256 if (ctlr->quirks & AHCI_Q_1CH) { 257 ctlr->caps &= ~AHCI_CAP_NPMASK; 258 ctlr->ichannels &= 0x01; 259 } 260 if (ctlr->quirks & AHCI_Q_2CH) { 261 ctlr->caps &= ~AHCI_CAP_NPMASK; 262 ctlr->caps |= 1; 263 ctlr->ichannels &= 0x03; 264 } 265 if (ctlr->quirks & AHCI_Q_4CH) { 266 ctlr->caps &= ~AHCI_CAP_NPMASK; 267 ctlr->caps |= 3; 268 ctlr->ichannels &= 0x0f; 269 } 270 ctlr->channels = MAX(flsl(ctlr->ichannels), 271 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 272 if (ctlr->quirks & AHCI_Q_NOPMP) 273 ctlr->caps &= ~AHCI_CAP_SPM; 274 if (ctlr->quirks & AHCI_Q_NONCQ) 275 ctlr->caps &= ~AHCI_CAP_SNCQ; 276 if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 277 ctlr->ccc = 0; 278 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC); 279 280 /* Create controller-wide DMA tag. */ 281 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 282 (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR : 283 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 284 BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, 285 ctlr->dma_coherent ? BUS_DMA_COHERENT : 0, NULL, NULL, 286 &ctlr->dma_tag)) { 287 ahci_free_mem(dev); 288 rman_fini(&ctlr->sc_iomem); 289 return (ENXIO); 290 } 291 292 ahci_ctlr_setup(dev); 293 294 /* Setup interrupts. */ 295 if ((error = ahci_setup_interrupt(dev)) != 0) { 296 bus_dma_tag_destroy(ctlr->dma_tag); 297 ahci_free_mem(dev); 298 rman_fini(&ctlr->sc_iomem); 299 return (error); 300 } 301 302 i = 0; 303 for (u = ctlr->ichannels; u != 0; u >>= 1) 304 i += (u & 1); 305 ctlr->direct = (ctlr->msi && (ctlr->numirqs > 1 || i <= 3)); 306 resource_int_value(device_get_name(dev), device_get_unit(dev), 307 "direct", &ctlr->direct); 308 /* Announce HW capabilities. */ 309 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 310 device_printf(dev, 311 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 312 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 313 ((version >> 4) & 0xf0) + (version & 0x0f), 314 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 315 ((speed == 1) ? "1.5":((speed == 2) ? "3": 316 ((speed == 3) ? "6":"?"))), 317 (ctlr->caps & AHCI_CAP_SPM) ? 318 "supported" : "not supported", 319 (ctlr->caps & AHCI_CAP_FBSS) ? 320 " with FBS" : ""); 321 if (ctlr->quirks != 0) { 322 device_printf(dev, "quirks=0x%b\n", ctlr->quirks, 323 AHCI_Q_BIT_STRING); 324 } 325 if (bootverbose) { 326 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 327 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 328 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 329 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 330 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 331 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 332 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 333 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 334 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 335 ((speed == 1) ? "1.5":((speed == 2) ? "3": 336 ((speed == 3) ? "6":"?")))); 337 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 338 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 339 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 340 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 341 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 342 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 343 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 344 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 345 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 346 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 347 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 348 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 349 } 350 if (bootverbose && version >= 0x00010200) { 351 device_printf(dev, "Caps2:%s%s%s%s%s%s\n", 352 (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"", 353 (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"", 354 (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"", 355 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 356 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 357 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 358 } 359 /* Attach all channels on this controller */ 360 for (unit = 0; unit < ctlr->channels; unit++) { 361 child = device_add_child(dev, "ahcich", -1); 362 if (child == NULL) { 363 device_printf(dev, "failed to add channel device\n"); 364 continue; 365 } 366 device_set_ivars(child, (void *)(intptr_t)unit); 367 if ((ctlr->ichannels & (1 << unit)) == 0) 368 device_disable(child); 369 } 370 /* Attach any remapped NVME device */ 371 for (; unit < ctlr->channels + ctlr->remapped_devices; unit++) { 372 child = device_add_child(dev, "nvme", -1); 373 if (child == NULL) { 374 device_printf(dev, "failed to add remapped NVMe device"); 375 continue; 376 } 377 device_set_ivars(child, (void *)(intptr_t)(unit | AHCI_REMAPPED_UNIT)); 378 } 379 380 if (ctlr->caps & AHCI_CAP_EMS) { 381 child = device_add_child(dev, "ahciem", -1); 382 if (child == NULL) 383 device_printf(dev, "failed to add enclosure device\n"); 384 else 385 device_set_ivars(child, (void *)(intptr_t)AHCI_EM_UNIT); 386 } 387 bus_generic_attach(dev); 388 return (0); 389 } 390 391 int 392 ahci_detach(device_t dev) 393 { 394 struct ahci_controller *ctlr = device_get_softc(dev); 395 int i; 396 397 /* Detach & delete all children */ 398 device_delete_children(dev); 399 400 /* Free interrupts. */ 401 for (i = 0; i < ctlr->numirqs; i++) { 402 if (ctlr->irqs[i].r_irq) { 403 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 404 ctlr->irqs[i].handle); 405 bus_release_resource(dev, SYS_RES_IRQ, 406 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 407 } 408 } 409 bus_dma_tag_destroy(ctlr->dma_tag); 410 /* Free memory. */ 411 rman_fini(&ctlr->sc_iomem); 412 ahci_free_mem(dev); 413 mtx_destroy(&ctlr->ch_mtx); 414 return (0); 415 } 416 417 void 418 ahci_free_mem(device_t dev) 419 { 420 struct ahci_controller *ctlr = device_get_softc(dev); 421 422 /* Release memory resources */ 423 if (ctlr->r_mem) 424 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 425 if (ctlr->r_msix_table) 426 bus_release_resource(dev, SYS_RES_MEMORY, 427 ctlr->r_msix_tab_rid, ctlr->r_msix_table); 428 if (ctlr->r_msix_pba) 429 bus_release_resource(dev, SYS_RES_MEMORY, 430 ctlr->r_msix_pba_rid, ctlr->r_msix_pba); 431 432 ctlr->r_msix_pba = ctlr->r_mem = ctlr->r_msix_table = NULL; 433 } 434 435 int 436 ahci_setup_interrupt(device_t dev) 437 { 438 struct ahci_controller *ctlr = device_get_softc(dev); 439 int i; 440 441 /* Check for single MSI vector fallback. */ 442 if (ctlr->numirqs > 1 && 443 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 444 device_printf(dev, "Falling back to one MSI\n"); 445 ctlr->numirqs = 1; 446 } 447 448 /* Ensure we don't overrun irqs. */ 449 if (ctlr->numirqs > AHCI_MAX_IRQS) { 450 device_printf(dev, "Too many irqs %d > %d (clamping)\n", 451 ctlr->numirqs, AHCI_MAX_IRQS); 452 ctlr->numirqs = AHCI_MAX_IRQS; 453 } 454 455 /* Allocate all IRQs. */ 456 for (i = 0; i < ctlr->numirqs; i++) { 457 ctlr->irqs[i].ctlr = ctlr; 458 ctlr->irqs[i].r_irq_rid = i + (ctlr->msi ? 1 : 0); 459 if (ctlr->channels == 1 && !ctlr->ccc && ctlr->msi) 460 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 461 else if (ctlr->numirqs == 1 || i >= ctlr->channels || 462 (ctlr->ccc && i == ctlr->cccv)) 463 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 464 else if (ctlr->channels > ctlr->numirqs && 465 i == ctlr->numirqs - 1) 466 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 467 else 468 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 469 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 470 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 471 device_printf(dev, "unable to map interrupt\n"); 472 return (ENXIO); 473 } 474 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 475 (ctlr->irqs[i].mode != AHCI_IRQ_MODE_ONE) ? ahci_intr : 476 ((ctlr->quirks & AHCI_Q_EDGEIS) ? ahci_intr_one_edge : 477 ahci_intr_one), 478 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 479 /* SOS XXX release r_irq */ 480 device_printf(dev, "unable to setup interrupt\n"); 481 return (ENXIO); 482 } 483 if (ctlr->numirqs > 1) { 484 bus_describe_intr(dev, ctlr->irqs[i].r_irq, 485 ctlr->irqs[i].handle, 486 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 487 "ch%d" : "%d", i); 488 } 489 } 490 return (0); 491 } 492 493 /* 494 * Common case interrupt handler. 495 */ 496 static void 497 ahci_intr(void *data) 498 { 499 struct ahci_controller_irq *irq = data; 500 struct ahci_controller *ctlr = irq->ctlr; 501 u_int32_t is, ise = 0; 502 void *arg; 503 int unit; 504 505 if (irq->mode == AHCI_IRQ_MODE_ALL) { 506 unit = 0; 507 if (ctlr->ccc) 508 is = ctlr->ichannels; 509 else 510 is = ATA_INL(ctlr->r_mem, AHCI_IS); 511 } else { /* AHCI_IRQ_MODE_AFTER */ 512 unit = irq->r_irq_rid - 1; 513 is = ATA_INL(ctlr->r_mem, AHCI_IS); 514 is &= (0xffffffff << unit); 515 } 516 /* CCC interrupt is edge triggered. */ 517 if (ctlr->ccc) 518 ise = 1 << ctlr->cccv; 519 /* Some controllers have edge triggered IS. */ 520 if (ctlr->quirks & AHCI_Q_EDGEIS) 521 ise |= is; 522 if (ise != 0) 523 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 524 for (; unit < ctlr->channels; unit++) { 525 if ((is & (1 << unit)) != 0 && 526 (arg = ctlr->interrupt[unit].argument)) { 527 ctlr->interrupt[unit].function(arg); 528 } 529 } 530 for (; unit < ctlr->channels + ctlr->remapped_devices; unit++) { 531 if ((arg = ctlr->interrupt[unit].argument)) { 532 ctlr->interrupt[unit].function(arg); 533 } 534 } 535 536 /* AHCI declares level triggered IS. */ 537 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 538 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 539 ATA_RBL(ctlr->r_mem, AHCI_IS); 540 } 541 542 /* 543 * Simplified interrupt handler for multivector MSI mode. 544 */ 545 static void 546 ahci_intr_one(void *data) 547 { 548 struct ahci_controller_irq *irq = data; 549 struct ahci_controller *ctlr = irq->ctlr; 550 void *arg; 551 int unit; 552 553 unit = irq->r_irq_rid - 1; 554 if ((arg = ctlr->interrupt[unit].argument)) 555 ctlr->interrupt[unit].function(arg); 556 /* AHCI declares level triggered IS. */ 557 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 558 ATA_RBL(ctlr->r_mem, AHCI_IS); 559 } 560 561 static void 562 ahci_intr_one_edge(void *data) 563 { 564 struct ahci_controller_irq *irq = data; 565 struct ahci_controller *ctlr = irq->ctlr; 566 void *arg; 567 int unit; 568 569 unit = irq->r_irq_rid - 1; 570 /* Some controllers have edge triggered IS. */ 571 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 572 if ((arg = ctlr->interrupt[unit].argument)) 573 ctlr->interrupt[unit].function(arg); 574 ATA_RBL(ctlr->r_mem, AHCI_IS); 575 } 576 577 struct resource * 578 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 579 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 580 { 581 struct ahci_controller *ctlr = device_get_softc(dev); 582 struct resource *res; 583 rman_res_t st; 584 int offset, size, unit; 585 bool is_em, is_remapped; 586 587 unit = (intptr_t)device_get_ivars(child); 588 is_em = is_remapped = false; 589 if (unit & AHCI_REMAPPED_UNIT) { 590 unit &= AHCI_UNIT; 591 unit -= ctlr->channels; 592 is_remapped = true; 593 } else if (unit & AHCI_EM_UNIT) { 594 unit &= AHCI_UNIT; 595 is_em = true; 596 } 597 res = NULL; 598 switch (type) { 599 case SYS_RES_MEMORY: 600 if (is_remapped) { 601 offset = ctlr->remap_offset + unit * ctlr->remap_size; 602 size = ctlr->remap_size; 603 } else if (!is_em) { 604 offset = AHCI_OFFSET + (unit << 7); 605 size = 128; 606 } else if (*rid == 0) { 607 offset = AHCI_EM_CTL; 608 size = 4; 609 } else { 610 offset = (ctlr->emloc & 0xffff0000) >> 14; 611 size = (ctlr->emloc & 0x0000ffff) << 2; 612 if (*rid != 1) { 613 if (*rid == 2 && (ctlr->capsem & 614 (AHCI_EM_XMT | AHCI_EM_SMB)) == 0) 615 offset += size; 616 else 617 break; 618 } 619 } 620 st = rman_get_start(ctlr->r_mem); 621 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 622 st + offset + size - 1, size, RF_ACTIVE, child); 623 if (res) { 624 bus_space_handle_t bsh; 625 bus_space_tag_t bst; 626 bsh = rman_get_bushandle(ctlr->r_mem); 627 bst = rman_get_bustag(ctlr->r_mem); 628 bus_space_subregion(bst, bsh, offset, 128, &bsh); 629 rman_set_bushandle(res, bsh); 630 rman_set_bustag(res, bst); 631 } 632 break; 633 case SYS_RES_IRQ: 634 if (*rid == ATA_IRQ_RID) 635 res = ctlr->irqs[0].r_irq; 636 break; 637 } 638 return (res); 639 } 640 641 int 642 ahci_release_resource(device_t dev, device_t child, int type, int rid, 643 struct resource *r) 644 { 645 646 switch (type) { 647 case SYS_RES_MEMORY: 648 rman_release_resource(r); 649 return (0); 650 case SYS_RES_IRQ: 651 if (rid != ATA_IRQ_RID) 652 return (ENOENT); 653 return (0); 654 } 655 return (EINVAL); 656 } 657 658 int 659 ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 660 int flags, driver_filter_t *filter, driver_intr_t *function, 661 void *argument, void **cookiep) 662 { 663 struct ahci_controller *ctlr = device_get_softc(dev); 664 int unit = (intptr_t)device_get_ivars(child) & AHCI_UNIT; 665 666 if (filter != NULL) { 667 printf("ahci.c: we cannot use a filter here\n"); 668 return (EINVAL); 669 } 670 ctlr->interrupt[unit].function = function; 671 ctlr->interrupt[unit].argument = argument; 672 return (0); 673 } 674 675 int 676 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 677 void *cookie) 678 { 679 struct ahci_controller *ctlr = device_get_softc(dev); 680 int unit = (intptr_t)device_get_ivars(child) & AHCI_UNIT; 681 682 ctlr->interrupt[unit].function = NULL; 683 ctlr->interrupt[unit].argument = NULL; 684 return (0); 685 } 686 687 int 688 ahci_print_child(device_t dev, device_t child) 689 { 690 intptr_t ivars; 691 int retval; 692 693 retval = bus_print_child_header(dev, child); 694 ivars = (intptr_t)device_get_ivars(child); 695 if ((ivars & AHCI_EM_UNIT) == 0) 696 retval += printf(" at channel %d", (int)ivars & AHCI_UNIT); 697 retval += bus_print_child_footer(dev, child); 698 return (retval); 699 } 700 701 int 702 ahci_child_location_str(device_t dev, device_t child, char *buf, 703 size_t buflen) 704 { 705 intptr_t ivars; 706 707 ivars = (intptr_t)device_get_ivars(child); 708 if ((ivars & AHCI_EM_UNIT) == 0) 709 snprintf(buf, buflen, "channel=%d", (int)ivars & AHCI_UNIT); 710 return (0); 711 } 712 713 bus_dma_tag_t 714 ahci_get_dma_tag(device_t dev, device_t child) 715 { 716 struct ahci_controller *ctlr = device_get_softc(dev); 717 718 return (ctlr->dma_tag); 719 } 720 721 void 722 ahci_attached(device_t dev, struct ahci_channel *ch) 723 { 724 struct ahci_controller *ctlr = device_get_softc(dev); 725 726 mtx_lock(&ctlr->ch_mtx); 727 ctlr->ch[ch->unit] = ch; 728 mtx_unlock(&ctlr->ch_mtx); 729 } 730 731 void 732 ahci_detached(device_t dev, struct ahci_channel *ch) 733 { 734 struct ahci_controller *ctlr = device_get_softc(dev); 735 736 mtx_lock(&ctlr->ch_mtx); 737 mtx_lock(&ch->mtx); 738 ctlr->ch[ch->unit] = NULL; 739 mtx_unlock(&ch->mtx); 740 mtx_unlock(&ctlr->ch_mtx); 741 } 742 743 struct ahci_channel * 744 ahci_getch(device_t dev, int n) 745 { 746 struct ahci_controller *ctlr = device_get_softc(dev); 747 struct ahci_channel *ch; 748 749 KASSERT(n >= 0 && n < AHCI_MAX_PORTS, ("Bad channel number %d", n)); 750 mtx_lock(&ctlr->ch_mtx); 751 ch = ctlr->ch[n]; 752 if (ch != NULL) 753 mtx_lock(&ch->mtx); 754 mtx_unlock(&ctlr->ch_mtx); 755 return (ch); 756 } 757 758 void 759 ahci_putch(struct ahci_channel *ch) 760 { 761 762 mtx_unlock(&ch->mtx); 763 } 764 765 static int 766 ahci_ch_probe(device_t dev) 767 { 768 769 device_set_desc_copy(dev, "AHCI channel"); 770 return (BUS_PROBE_DEFAULT); 771 } 772 773 static int 774 ahci_ch_disablephy_proc(SYSCTL_HANDLER_ARGS) 775 { 776 struct ahci_channel *ch; 777 int error, value; 778 779 ch = arg1; 780 value = ch->disablephy; 781 error = sysctl_handle_int(oidp, &value, 0, req); 782 if (error != 0 || req->newptr == NULL || (value != 0 && value != 1)) 783 return (error); 784 785 mtx_lock(&ch->mtx); 786 ch->disablephy = value; 787 if (value) { 788 ahci_ch_deinit(ch->dev); 789 } else { 790 ahci_ch_init(ch->dev); 791 ahci_phy_check_events(ch, ATA_SE_PHY_CHANGED | ATA_SE_EXCHANGED); 792 } 793 mtx_unlock(&ch->mtx); 794 795 return (0); 796 } 797 798 static int 799 ahci_ch_attach(device_t dev) 800 { 801 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 802 struct ahci_channel *ch = device_get_softc(dev); 803 struct cam_devq *devq; 804 struct sysctl_ctx_list *ctx; 805 struct sysctl_oid *tree; 806 int rid, error, i, sata_rev = 0; 807 u_int32_t version; 808 809 ch->dev = dev; 810 ch->unit = (intptr_t)device_get_ivars(dev); 811 ch->caps = ctlr->caps; 812 ch->caps2 = ctlr->caps2; 813 ch->start = ctlr->ch_start; 814 ch->quirks = ctlr->quirks; 815 ch->vendorid = ctlr->vendorid; 816 ch->deviceid = ctlr->deviceid; 817 ch->subvendorid = ctlr->subvendorid; 818 ch->subdeviceid = ctlr->subdeviceid; 819 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1; 820 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 821 ch->pm_level = 0; 822 resource_int_value(device_get_name(dev), 823 device_get_unit(dev), "pm_level", &ch->pm_level); 824 STAILQ_INIT(&ch->doneq); 825 if (ch->pm_level > 3) 826 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 827 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0); 828 /* JMicron external ports (0) sometimes limited */ 829 if ((ctlr->quirks & AHCI_Q_SATA1_UNIT0) && ch->unit == 0) 830 sata_rev = 1; 831 if (ch->quirks & AHCI_Q_SATA2) 832 sata_rev = 2; 833 resource_int_value(device_get_name(dev), 834 device_get_unit(dev), "sata_rev", &sata_rev); 835 for (i = 0; i < 16; i++) { 836 ch->user[i].revision = sata_rev; 837 ch->user[i].mode = 0; 838 ch->user[i].bytecount = 8192; 839 ch->user[i].tags = ch->numslots; 840 ch->user[i].caps = 0; 841 ch->curr[i] = ch->user[i]; 842 if (ch->pm_level) { 843 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 844 CTS_SATA_CAPS_H_APST | 845 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 846 } 847 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA | 848 CTS_SATA_CAPS_H_AN; 849 } 850 rid = 0; 851 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 852 &rid, RF_ACTIVE))) 853 return (ENXIO); 854 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 855 version = ATA_INL(ctlr->r_mem, AHCI_VS); 856 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS)) 857 ch->chcaps |= AHCI_P_CMD_FBSCP; 858 if (ch->caps2 & AHCI_CAP2_SDS) 859 ch->chscaps = ATA_INL(ch->r_mem, AHCI_P_DEVSLP); 860 if (bootverbose) { 861 device_printf(dev, "Caps:%s%s%s%s%s%s\n", 862 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 863 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 864 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 865 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 866 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"", 867 (ch->chscaps & AHCI_P_DEVSLP_DSP) ? " DSP":""); 868 } 869 ahci_dmainit(dev); 870 ahci_slotsalloc(dev); 871 mtx_lock(&ch->mtx); 872 ahci_ch_init(dev); 873 rid = ATA_IRQ_RID; 874 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 875 &rid, RF_SHAREABLE | RF_ACTIVE))) { 876 device_printf(dev, "Unable to map interrupt\n"); 877 error = ENXIO; 878 goto err0; 879 } 880 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 881 ctlr->direct ? ahci_ch_intr_direct : ahci_ch_intr, 882 ch, &ch->ih))) { 883 device_printf(dev, "Unable to setup interrupt\n"); 884 error = ENXIO; 885 goto err1; 886 } 887 /* Create the device queue for our SIM. */ 888 devq = cam_simq_alloc(ch->numslots); 889 if (devq == NULL) { 890 device_printf(dev, "Unable to allocate simq\n"); 891 error = ENOMEM; 892 goto err1; 893 } 894 /* Construct SIM entry */ 895 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 896 device_get_unit(dev), (struct mtx *)&ch->mtx, 897 (ch->quirks & AHCI_Q_NOCCS) ? 1 : min(2, ch->numslots), 898 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 899 devq); 900 if (ch->sim == NULL) { 901 cam_simq_free(devq); 902 device_printf(dev, "unable to allocate sim\n"); 903 error = ENOMEM; 904 goto err1; 905 } 906 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 907 device_printf(dev, "unable to register xpt bus\n"); 908 error = ENXIO; 909 goto err2; 910 } 911 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 912 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 913 device_printf(dev, "unable to create path\n"); 914 error = ENXIO; 915 goto err3; 916 } 917 if (ch->pm_level > 3) { 918 callout_reset(&ch->pm_timer, 919 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 920 ahci_ch_pm, ch); 921 } 922 mtx_unlock(&ch->mtx); 923 ahci_attached(device_get_parent(dev), ch); 924 ctx = device_get_sysctl_ctx(dev); 925 tree = device_get_sysctl_tree(dev); 926 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "disable_phy", 927 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, ch, 928 0, ahci_ch_disablephy_proc, "IU", "Disable PHY"); 929 return (0); 930 931 err3: 932 xpt_bus_deregister(cam_sim_path(ch->sim)); 933 err2: 934 cam_sim_free(ch->sim, /*free_devq*/TRUE); 935 err1: 936 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 937 err0: 938 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 939 mtx_unlock(&ch->mtx); 940 mtx_destroy(&ch->mtx); 941 return (error); 942 } 943 944 static int 945 ahci_ch_detach(device_t dev) 946 { 947 struct ahci_channel *ch = device_get_softc(dev); 948 949 ahci_detached(device_get_parent(dev), ch); 950 mtx_lock(&ch->mtx); 951 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 952 /* Forget about reset. */ 953 if (ch->resetting) { 954 ch->resetting = 0; 955 xpt_release_simq(ch->sim, TRUE); 956 } 957 xpt_free_path(ch->path); 958 xpt_bus_deregister(cam_sim_path(ch->sim)); 959 cam_sim_free(ch->sim, /*free_devq*/TRUE); 960 mtx_unlock(&ch->mtx); 961 962 if (ch->pm_level > 3) 963 callout_drain(&ch->pm_timer); 964 callout_drain(&ch->reset_timer); 965 bus_teardown_intr(dev, ch->r_irq, ch->ih); 966 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 967 968 ahci_ch_deinit(dev); 969 ahci_slotsfree(dev); 970 ahci_dmafini(dev); 971 972 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 973 mtx_destroy(&ch->mtx); 974 return (0); 975 } 976 977 static int 978 ahci_ch_init(device_t dev) 979 { 980 struct ahci_channel *ch = device_get_softc(dev); 981 uint64_t work; 982 983 /* Disable port interrupts */ 984 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 985 /* Setup work areas */ 986 work = ch->dma.work_bus + AHCI_CL_OFFSET; 987 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 988 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 989 work = ch->dma.rfis_bus; 990 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 991 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 992 /* Activate the channel and power/spin up device */ 993 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 994 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 995 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 996 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 997 ahci_start_fr(ch); 998 ahci_start(ch, 1); 999 return (0); 1000 } 1001 1002 static int 1003 ahci_ch_deinit(device_t dev) 1004 { 1005 struct ahci_channel *ch = device_get_softc(dev); 1006 1007 /* Disable port interrupts. */ 1008 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1009 /* Reset command register. */ 1010 ahci_stop(ch); 1011 ahci_stop_fr(ch); 1012 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 1013 /* Allow everything, including partial and slumber modes. */ 1014 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 1015 /* Request slumber mode transition and give some time to get there. */ 1016 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 1017 DELAY(100); 1018 /* Disable PHY. */ 1019 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 1020 return (0); 1021 } 1022 1023 static int 1024 ahci_ch_suspend(device_t dev) 1025 { 1026 struct ahci_channel *ch = device_get_softc(dev); 1027 1028 mtx_lock(&ch->mtx); 1029 xpt_freeze_simq(ch->sim, 1); 1030 /* Forget about reset. */ 1031 if (ch->resetting) { 1032 ch->resetting = 0; 1033 callout_stop(&ch->reset_timer); 1034 xpt_release_simq(ch->sim, TRUE); 1035 } 1036 while (ch->oslots) 1037 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100); 1038 ahci_ch_deinit(dev); 1039 mtx_unlock(&ch->mtx); 1040 return (0); 1041 } 1042 1043 static int 1044 ahci_ch_resume(device_t dev) 1045 { 1046 struct ahci_channel *ch = device_get_softc(dev); 1047 1048 mtx_lock(&ch->mtx); 1049 ahci_ch_init(dev); 1050 ahci_reset(ch); 1051 xpt_release_simq(ch->sim, TRUE); 1052 mtx_unlock(&ch->mtx); 1053 return (0); 1054 } 1055 1056 devclass_t ahcich_devclass; 1057 static device_method_t ahcich_methods[] = { 1058 DEVMETHOD(device_probe, ahci_ch_probe), 1059 DEVMETHOD(device_attach, ahci_ch_attach), 1060 DEVMETHOD(device_detach, ahci_ch_detach), 1061 DEVMETHOD(device_suspend, ahci_ch_suspend), 1062 DEVMETHOD(device_resume, ahci_ch_resume), 1063 DEVMETHOD_END 1064 }; 1065 static driver_t ahcich_driver = { 1066 "ahcich", 1067 ahcich_methods, 1068 sizeof(struct ahci_channel) 1069 }; 1070 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, NULL, NULL); 1071 1072 struct ahci_dc_cb_args { 1073 bus_addr_t maddr; 1074 int error; 1075 }; 1076 1077 static void 1078 ahci_dmainit(device_t dev) 1079 { 1080 struct ahci_channel *ch = device_get_softc(dev); 1081 struct ahci_dc_cb_args dcba; 1082 size_t rfsize; 1083 int error; 1084 1085 /* Command area. */ 1086 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 1087 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1088 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 1089 0, NULL, NULL, &ch->dma.work_tag); 1090 if (error != 0) 1091 goto error; 1092 error = bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 1093 BUS_DMA_ZERO, &ch->dma.work_map); 1094 if (error != 0) 1095 goto error; 1096 error = bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 1097 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, BUS_DMA_NOWAIT); 1098 if (error != 0 || (error = dcba.error) != 0) { 1099 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1100 goto error; 1101 } 1102 ch->dma.work_bus = dcba.maddr; 1103 /* FIS receive area. */ 1104 if (ch->chcaps & AHCI_P_CMD_FBSCP) 1105 rfsize = 4096; 1106 else 1107 rfsize = 256; 1108 error = bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 1109 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1110 NULL, NULL, rfsize, 1, rfsize, 1111 0, NULL, NULL, &ch->dma.rfis_tag); 1112 if (error != 0) 1113 goto error; 1114 error = bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 1115 &ch->dma.rfis_map); 1116 if (error != 0) 1117 goto error; 1118 error = bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 1119 rfsize, ahci_dmasetupc_cb, &dcba, BUS_DMA_NOWAIT); 1120 if (error != 0 || (error = dcba.error) != 0) { 1121 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1122 goto error; 1123 } 1124 ch->dma.rfis_bus = dcba.maddr; 1125 /* Data area. */ 1126 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 1127 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1128 NULL, NULL, 1129 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 1130 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 1131 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag); 1132 if (error != 0) 1133 goto error; 1134 return; 1135 1136 error: 1137 device_printf(dev, "WARNING - DMA initialization failed, error %d\n", 1138 error); 1139 ahci_dmafini(dev); 1140 } 1141 1142 static void 1143 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1144 { 1145 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 1146 1147 if (!(dcba->error = error)) 1148 dcba->maddr = segs[0].ds_addr; 1149 } 1150 1151 static void 1152 ahci_dmafini(device_t dev) 1153 { 1154 struct ahci_channel *ch = device_get_softc(dev); 1155 1156 if (ch->dma.data_tag) { 1157 bus_dma_tag_destroy(ch->dma.data_tag); 1158 ch->dma.data_tag = NULL; 1159 } 1160 if (ch->dma.rfis_bus) { 1161 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1162 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1163 ch->dma.rfis_bus = 0; 1164 ch->dma.rfis = NULL; 1165 } 1166 if (ch->dma.work_bus) { 1167 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1168 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1169 ch->dma.work_bus = 0; 1170 ch->dma.work = NULL; 1171 } 1172 if (ch->dma.work_tag) { 1173 bus_dma_tag_destroy(ch->dma.work_tag); 1174 ch->dma.work_tag = NULL; 1175 } 1176 } 1177 1178 static void 1179 ahci_slotsalloc(device_t dev) 1180 { 1181 struct ahci_channel *ch = device_get_softc(dev); 1182 int i; 1183 1184 /* Alloc and setup command/dma slots */ 1185 bzero(ch->slot, sizeof(ch->slot)); 1186 for (i = 0; i < ch->numslots; i++) { 1187 struct ahci_slot *slot = &ch->slot[i]; 1188 1189 slot->ch = ch; 1190 slot->slot = i; 1191 slot->state = AHCI_SLOT_EMPTY; 1192 slot->ccb = NULL; 1193 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1194 1195 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1196 device_printf(ch->dev, "FAILURE - create data_map\n"); 1197 } 1198 } 1199 1200 static void 1201 ahci_slotsfree(device_t dev) 1202 { 1203 struct ahci_channel *ch = device_get_softc(dev); 1204 int i; 1205 1206 /* Free all dma slots */ 1207 for (i = 0; i < ch->numslots; i++) { 1208 struct ahci_slot *slot = &ch->slot[i]; 1209 1210 callout_drain(&slot->timeout); 1211 if (slot->dma.data_map) { 1212 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1213 slot->dma.data_map = NULL; 1214 } 1215 } 1216 } 1217 1218 static int 1219 ahci_phy_check_events(struct ahci_channel *ch, u_int32_t serr) 1220 { 1221 1222 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) || 1223 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) { 1224 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1225 union ccb *ccb; 1226 1227 if (bootverbose) { 1228 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 1229 device_printf(ch->dev, "CONNECT requested\n"); 1230 else 1231 device_printf(ch->dev, "DISCONNECT requested\n"); 1232 } 1233 ahci_reset(ch); 1234 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1235 return (0); 1236 if (xpt_create_path(&ccb->ccb_h.path, NULL, 1237 cam_sim_path(ch->sim), 1238 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1239 xpt_free_ccb(ccb); 1240 return (0); 1241 } 1242 xpt_rescan(ccb); 1243 return (1); 1244 } 1245 return (0); 1246 } 1247 1248 static void 1249 ahci_cpd_check_events(struct ahci_channel *ch) 1250 { 1251 u_int32_t status; 1252 union ccb *ccb; 1253 device_t dev; 1254 1255 if (ch->pm_level == 0) 1256 return; 1257 1258 status = ATA_INL(ch->r_mem, AHCI_P_CMD); 1259 if ((status & AHCI_P_CMD_CPD) == 0) 1260 return; 1261 1262 if (bootverbose) { 1263 dev = ch->dev; 1264 if (status & AHCI_P_CMD_CPS) { 1265 device_printf(dev, "COLD CONNECT requested\n"); 1266 } else 1267 device_printf(dev, "COLD DISCONNECT requested\n"); 1268 } 1269 ahci_reset(ch); 1270 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1271 return; 1272 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim), 1273 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1274 xpt_free_ccb(ccb); 1275 return; 1276 } 1277 xpt_rescan(ccb); 1278 } 1279 1280 static void 1281 ahci_notify_events(struct ahci_channel *ch, u_int32_t status) 1282 { 1283 struct cam_path *dpath; 1284 int i; 1285 1286 if (ch->caps & AHCI_CAP_SSNTF) 1287 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1288 if (bootverbose) 1289 device_printf(ch->dev, "SNTF 0x%04x\n", status); 1290 for (i = 0; i < 16; i++) { 1291 if ((status & (1 << i)) == 0) 1292 continue; 1293 if (xpt_create_path(&dpath, NULL, 1294 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1295 xpt_async(AC_SCSI_AEN, dpath, NULL); 1296 xpt_free_path(dpath); 1297 } 1298 } 1299 } 1300 1301 static void 1302 ahci_done(struct ahci_channel *ch, union ccb *ccb) 1303 { 1304 1305 mtx_assert(&ch->mtx, MA_OWNED); 1306 if ((ccb->ccb_h.func_code & XPT_FC_QUEUED) == 0 || 1307 ch->batch == 0) { 1308 xpt_done(ccb); 1309 return; 1310 } 1311 1312 STAILQ_INSERT_TAIL(&ch->doneq, &ccb->ccb_h, sim_links.stqe); 1313 } 1314 1315 static void 1316 ahci_ch_intr(void *arg) 1317 { 1318 struct ahci_channel *ch = (struct ahci_channel *)arg; 1319 uint32_t istatus; 1320 1321 /* Read interrupt statuses. */ 1322 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1323 1324 mtx_lock(&ch->mtx); 1325 ahci_ch_intr_main(ch, istatus); 1326 mtx_unlock(&ch->mtx); 1327 } 1328 1329 static void 1330 ahci_ch_intr_direct(void *arg) 1331 { 1332 struct ahci_channel *ch = (struct ahci_channel *)arg; 1333 struct ccb_hdr *ccb_h; 1334 uint32_t istatus; 1335 STAILQ_HEAD(, ccb_hdr) tmp_doneq = STAILQ_HEAD_INITIALIZER(tmp_doneq); 1336 1337 /* Read interrupt statuses. */ 1338 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1339 1340 mtx_lock(&ch->mtx); 1341 ch->batch = 1; 1342 ahci_ch_intr_main(ch, istatus); 1343 ch->batch = 0; 1344 /* 1345 * Prevent the possibility of issues caused by processing the queue 1346 * while unlocked below by moving the contents to a local queue. 1347 */ 1348 STAILQ_CONCAT(&tmp_doneq, &ch->doneq); 1349 mtx_unlock(&ch->mtx); 1350 while ((ccb_h = STAILQ_FIRST(&tmp_doneq)) != NULL) { 1351 STAILQ_REMOVE_HEAD(&tmp_doneq, sim_links.stqe); 1352 xpt_done_direct((union ccb *)ccb_h); 1353 } 1354 } 1355 1356 static void 1357 ahci_ch_pm(void *arg) 1358 { 1359 struct ahci_channel *ch = (struct ahci_channel *)arg; 1360 uint32_t work; 1361 1362 if (ch->numrslots != 0) 1363 return; 1364 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1365 if (ch->pm_level == 4) 1366 work |= AHCI_P_CMD_PARTIAL; 1367 else 1368 work |= AHCI_P_CMD_SLUMBER; 1369 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1370 } 1371 1372 static void 1373 ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus) 1374 { 1375 uint32_t cstatus, serr = 0, sntf = 0, ok, err; 1376 enum ahci_err_type et; 1377 int i, ccs, port, reset = 0; 1378 1379 /* Clear interrupt statuses. */ 1380 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1381 /* Read command statuses. */ 1382 if (ch->numtslots != 0) 1383 cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1384 else 1385 cstatus = 0; 1386 if (ch->numrslots != ch->numtslots) 1387 cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI); 1388 /* Read SNTF in one of possible ways. */ 1389 if ((istatus & AHCI_P_IX_SDB) && 1390 (ch->pm_present || ch->curr[0].atapi != 0)) { 1391 if (ch->caps & AHCI_CAP_SSNTF) 1392 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1393 else if (ch->fbs_enabled) { 1394 u_int8_t *fis = ch->dma.rfis + 0x58; 1395 1396 for (i = 0; i < 16; i++) { 1397 if (fis[1] & 0x80) { 1398 fis[1] &= 0x7f; 1399 sntf |= 1 << i; 1400 } 1401 fis += 256; 1402 } 1403 } else { 1404 u_int8_t *fis = ch->dma.rfis + 0x58; 1405 1406 if (fis[1] & 0x80) 1407 sntf = (1 << (fis[1] & 0x0f)); 1408 } 1409 } 1410 /* Process PHY events */ 1411 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1412 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1413 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1414 if (serr) { 1415 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1416 reset = ahci_phy_check_events(ch, serr); 1417 } 1418 } 1419 /* Process cold presence detection events */ 1420 if ((istatus & AHCI_P_IX_CPD) && !reset) 1421 ahci_cpd_check_events(ch); 1422 /* Process command errors */ 1423 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1424 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1425 if (ch->quirks & AHCI_Q_NOCCS) { 1426 /* 1427 * ASMedia chips sometimes report failed commands as 1428 * completed. Count all running commands as failed. 1429 */ 1430 cstatus |= ch->rslots; 1431 1432 /* They also report wrong CCS, so try to guess one. */ 1433 ccs = powerof2(cstatus) ? ffs(cstatus) - 1 : -1; 1434 } else { 1435 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & 1436 AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 1437 } 1438 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1439 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1440 // serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1441 port = -1; 1442 if (ch->fbs_enabled) { 1443 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1444 if (fbs & AHCI_P_FBS_SDE) { 1445 port = (fbs & AHCI_P_FBS_DWE) 1446 >> AHCI_P_FBS_DWE_SHIFT; 1447 } else { 1448 for (i = 0; i < 16; i++) { 1449 if (ch->numrslotspd[i] == 0) 1450 continue; 1451 if (port == -1) 1452 port = i; 1453 else if (port != i) { 1454 port = -2; 1455 break; 1456 } 1457 } 1458 } 1459 } 1460 err = ch->rslots & cstatus; 1461 } else { 1462 ccs = 0; 1463 err = 0; 1464 port = -1; 1465 } 1466 /* Complete all successful commands. */ 1467 ok = ch->rslots & ~cstatus; 1468 for (i = 0; i < ch->numslots; i++) { 1469 if ((ok >> i) & 1) 1470 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1471 } 1472 /* On error, complete the rest of commands with error statuses. */ 1473 if (err) { 1474 if (ch->frozen) { 1475 union ccb *fccb = ch->frozen; 1476 ch->frozen = NULL; 1477 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1478 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1479 xpt_freeze_devq(fccb->ccb_h.path, 1); 1480 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1481 } 1482 ahci_done(ch, fccb); 1483 } 1484 for (i = 0; i < ch->numslots; i++) { 1485 /* XXX: reqests in loading state. */ 1486 if (((err >> i) & 1) == 0) 1487 continue; 1488 if (port >= 0 && 1489 ch->slot[i].ccb->ccb_h.target_id != port) 1490 continue; 1491 if (istatus & AHCI_P_IX_TFE) { 1492 if (port != -2) { 1493 /* Task File Error */ 1494 if (ch->numtslotspd[ 1495 ch->slot[i].ccb->ccb_h.target_id] == 0) { 1496 /* Untagged operation. */ 1497 if (i == ccs) 1498 et = AHCI_ERR_TFE; 1499 else 1500 et = AHCI_ERR_INNOCENT; 1501 } else { 1502 /* Tagged operation. */ 1503 et = AHCI_ERR_NCQ; 1504 } 1505 } else { 1506 et = AHCI_ERR_TFE; 1507 ch->fatalerr = 1; 1508 } 1509 } else if (istatus & AHCI_P_IX_IF) { 1510 if (ch->numtslots == 0 && i != ccs && port != -2) 1511 et = AHCI_ERR_INNOCENT; 1512 else 1513 et = AHCI_ERR_SATA; 1514 } else 1515 et = AHCI_ERR_INVALID; 1516 ahci_end_transaction(&ch->slot[i], et); 1517 } 1518 /* 1519 * We can't reinit port if there are some other 1520 * commands active, use resume to complete them. 1521 */ 1522 if (ch->rslots != 0 && !ch->recoverycmd) 1523 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1524 } 1525 /* Process NOTIFY events */ 1526 if (sntf) 1527 ahci_notify_events(ch, sntf); 1528 } 1529 1530 /* Must be called with channel locked. */ 1531 static int 1532 ahci_check_collision(struct ahci_channel *ch, union ccb *ccb) 1533 { 1534 int t = ccb->ccb_h.target_id; 1535 1536 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1537 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1538 /* Tagged command while we have no supported tag free. */ 1539 if (((~ch->oslots) & (0xffffffff >> (32 - 1540 ch->curr[t].tags))) == 0) 1541 return (1); 1542 /* If we have FBS */ 1543 if (ch->fbs_enabled) { 1544 /* Tagged command while untagged are active. */ 1545 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1546 return (1); 1547 } else { 1548 /* Tagged command while untagged are active. */ 1549 if (ch->numrslots != 0 && ch->numtslots == 0) 1550 return (1); 1551 /* Tagged command while tagged to other target is active. */ 1552 if (ch->numtslots != 0 && 1553 ch->taggedtarget != ccb->ccb_h.target_id) 1554 return (1); 1555 } 1556 } else { 1557 /* If we have FBS */ 1558 if (ch->fbs_enabled) { 1559 /* Untagged command while tagged are active. */ 1560 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1561 return (1); 1562 } else { 1563 /* Untagged command while tagged are active. */ 1564 if (ch->numrslots != 0 && ch->numtslots != 0) 1565 return (1); 1566 } 1567 } 1568 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1569 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1570 /* Atomic command while anything active. */ 1571 if (ch->numrslots != 0) 1572 return (1); 1573 } 1574 /* We have some atomic command running. */ 1575 if (ch->aslots != 0) 1576 return (1); 1577 return (0); 1578 } 1579 1580 /* Must be called with channel locked. */ 1581 static void 1582 ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb) 1583 { 1584 struct ahci_slot *slot; 1585 int tag, tags; 1586 1587 /* Choose empty slot. */ 1588 tags = ch->numslots; 1589 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1590 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1591 tags = ch->curr[ccb->ccb_h.target_id].tags; 1592 if (ch->lastslot + 1 < tags) 1593 tag = ffs(~(ch->oslots >> (ch->lastslot + 1))); 1594 else 1595 tag = 0; 1596 if (tag == 0 || tag + ch->lastslot >= tags) 1597 tag = ffs(~ch->oslots) - 1; 1598 else 1599 tag += ch->lastslot; 1600 ch->lastslot = tag; 1601 /* Occupy chosen slot. */ 1602 slot = &ch->slot[tag]; 1603 slot->ccb = ccb; 1604 /* Stop PM timer. */ 1605 if (ch->numrslots == 0 && ch->pm_level > 3) 1606 callout_stop(&ch->pm_timer); 1607 /* Update channel stats. */ 1608 ch->oslots |= (1 << tag); 1609 ch->numrslots++; 1610 ch->numrslotspd[ccb->ccb_h.target_id]++; 1611 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1612 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1613 ch->numtslots++; 1614 ch->numtslotspd[ccb->ccb_h.target_id]++; 1615 ch->taggedtarget = ccb->ccb_h.target_id; 1616 } 1617 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1618 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1619 ch->aslots |= (1 << tag); 1620 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1621 slot->state = AHCI_SLOT_LOADING; 1622 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb, 1623 ahci_dmasetprd, slot, 0); 1624 } else { 1625 slot->dma.nsegs = 0; 1626 ahci_execute_transaction(slot); 1627 } 1628 } 1629 1630 /* Locked by busdma engine. */ 1631 static void 1632 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1633 { 1634 struct ahci_slot *slot = arg; 1635 struct ahci_channel *ch = slot->ch; 1636 struct ahci_cmd_tab *ctp; 1637 struct ahci_dma_prd *prd; 1638 int i; 1639 1640 if (error) { 1641 device_printf(ch->dev, "DMA load error\n"); 1642 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1643 return; 1644 } 1645 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1646 /* Get a piece of the workspace for this request */ 1647 ctp = (struct ahci_cmd_tab *) 1648 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1649 /* Fill S/G table */ 1650 prd = &ctp->prd_tab[0]; 1651 for (i = 0; i < nsegs; i++) { 1652 prd[i].dba = htole64(segs[i].ds_addr); 1653 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1654 } 1655 slot->dma.nsegs = nsegs; 1656 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1657 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1658 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1659 ahci_execute_transaction(slot); 1660 } 1661 1662 /* Must be called with channel locked. */ 1663 static void 1664 ahci_execute_transaction(struct ahci_slot *slot) 1665 { 1666 struct ahci_channel *ch = slot->ch; 1667 struct ahci_cmd_tab *ctp; 1668 struct ahci_cmd_list *clp; 1669 union ccb *ccb = slot->ccb; 1670 int port = ccb->ccb_h.target_id & 0x0f; 1671 int fis_size, i, softreset; 1672 uint8_t *fis = ch->dma.rfis + 0x40; 1673 uint8_t val; 1674 uint16_t cmd_flags; 1675 1676 /* Get a piece of the workspace for this request */ 1677 ctp = (struct ahci_cmd_tab *) 1678 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1679 /* Setup the FIS for this request */ 1680 if (!(fis_size = ahci_setup_fis(ch, ctp, ccb, slot->slot))) { 1681 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1682 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1683 return; 1684 } 1685 /* Setup the command list entry */ 1686 clp = (struct ahci_cmd_list *) 1687 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1688 cmd_flags = 1689 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1690 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1691 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1692 (fis_size / sizeof(u_int32_t)) | 1693 (port << 12); 1694 clp->prd_length = htole16(slot->dma.nsegs); 1695 /* Special handling for Soft Reset command. */ 1696 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1697 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1698 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1699 softreset = 1; 1700 /* Kick controller into sane state */ 1701 ahci_stop(ch); 1702 ahci_clo(ch); 1703 ahci_start(ch, 0); 1704 cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1705 } else { 1706 softreset = 2; 1707 /* Prepare FIS receive area for check. */ 1708 for (i = 0; i < 20; i++) 1709 fis[i] = 0xff; 1710 } 1711 } else 1712 softreset = 0; 1713 clp->bytecount = 0; 1714 clp->cmd_flags = htole16(cmd_flags); 1715 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1716 (AHCI_CT_SIZE * slot->slot)); 1717 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1718 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1719 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1720 BUS_DMASYNC_PREREAD); 1721 /* Set ACTIVE bit for NCQ commands. */ 1722 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1723 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1724 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1725 } 1726 /* If FBS is enabled, set PMP port. */ 1727 if (ch->fbs_enabled) { 1728 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1729 (port << AHCI_P_FBS_DEV_SHIFT)); 1730 } 1731 /* Issue command to the controller. */ 1732 slot->state = AHCI_SLOT_RUNNING; 1733 ch->rslots |= (1 << slot->slot); 1734 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1735 /* Device reset commands doesn't interrupt. Poll them. */ 1736 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1737 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) { 1738 int count, timeout = ccb->ccb_h.timeout * 100; 1739 enum ahci_err_type et = AHCI_ERR_NONE; 1740 1741 for (count = 0; count < timeout; count++) { 1742 DELAY(10); 1743 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1744 break; 1745 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) && 1746 softreset != 1) { 1747 #if 0 1748 device_printf(ch->dev, 1749 "Poll error on slot %d, TFD: %04x\n", 1750 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1751 #endif 1752 et = AHCI_ERR_TFE; 1753 break; 1754 } 1755 /* Workaround for ATI SB600/SB700 chipsets. */ 1756 if (ccb->ccb_h.target_id == 15 && 1757 (ch->quirks & AHCI_Q_ATI_PMP_BUG) && 1758 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1759 et = AHCI_ERR_TIMEOUT; 1760 break; 1761 } 1762 } 1763 1764 /* 1765 * Some Marvell controllers require additional time 1766 * after soft reset to work properly. Setup delay 1767 * to 50ms after soft reset. 1768 */ 1769 if (ch->quirks & AHCI_Q_MRVL_SR_DEL) 1770 DELAY(50000); 1771 1772 /* 1773 * Marvell HBAs with non-RAID firmware do not wait for 1774 * readiness after soft reset, so we have to wait here. 1775 * Marvell RAIDs do not have this problem, but instead 1776 * sometimes forget to update FIS receive area, breaking 1777 * this wait. 1778 */ 1779 if ((ch->quirks & AHCI_Q_NOBSYRES) == 0 && 1780 (ch->quirks & AHCI_Q_ATI_PMP_BUG) == 0 && 1781 softreset == 2 && et == AHCI_ERR_NONE) { 1782 for ( ; count < timeout; count++) { 1783 bus_dmamap_sync(ch->dma.rfis_tag, 1784 ch->dma.rfis_map, BUS_DMASYNC_POSTREAD); 1785 val = fis[2]; 1786 bus_dmamap_sync(ch->dma.rfis_tag, 1787 ch->dma.rfis_map, BUS_DMASYNC_PREREAD); 1788 if ((val & ATA_S_BUSY) == 0) 1789 break; 1790 DELAY(10); 1791 } 1792 } 1793 1794 if (timeout && (count >= timeout)) { 1795 device_printf(ch->dev, "Poll timeout on slot %d port %d\n", 1796 slot->slot, port); 1797 device_printf(ch->dev, "is %08x cs %08x ss %08x " 1798 "rs %08x tfd %02x serr %08x cmd %08x\n", 1799 ATA_INL(ch->r_mem, AHCI_P_IS), 1800 ATA_INL(ch->r_mem, AHCI_P_CI), 1801 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1802 ATA_INL(ch->r_mem, AHCI_P_TFD), 1803 ATA_INL(ch->r_mem, AHCI_P_SERR), 1804 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1805 et = AHCI_ERR_TIMEOUT; 1806 } 1807 1808 /* Kick controller into sane state and enable FBS. */ 1809 if (softreset == 2) 1810 ch->eslots |= (1 << slot->slot); 1811 ahci_end_transaction(slot, et); 1812 return; 1813 } 1814 /* Start command execution timeout */ 1815 callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout / 2, 1816 0, ahci_timeout, slot, 0); 1817 return; 1818 } 1819 1820 /* Must be called with channel locked. */ 1821 static void 1822 ahci_process_timeout(struct ahci_channel *ch) 1823 { 1824 int i; 1825 1826 mtx_assert(&ch->mtx, MA_OWNED); 1827 /* Handle the rest of commands. */ 1828 for (i = 0; i < ch->numslots; i++) { 1829 /* Do we have a running request on slot? */ 1830 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1831 continue; 1832 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 1833 } 1834 } 1835 1836 /* Must be called with channel locked. */ 1837 static void 1838 ahci_rearm_timeout(struct ahci_channel *ch) 1839 { 1840 int i; 1841 1842 mtx_assert(&ch->mtx, MA_OWNED); 1843 for (i = 0; i < ch->numslots; i++) { 1844 struct ahci_slot *slot = &ch->slot[i]; 1845 1846 /* Do we have a running request on slot? */ 1847 if (slot->state < AHCI_SLOT_RUNNING) 1848 continue; 1849 if ((ch->toslots & (1 << i)) == 0) 1850 continue; 1851 callout_reset_sbt(&slot->timeout, 1852 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0, 1853 ahci_timeout, slot, 0); 1854 } 1855 } 1856 1857 /* Locked by callout mechanism. */ 1858 static void 1859 ahci_timeout(void *arg) 1860 { 1861 struct ahci_slot *slot = arg; 1862 struct ahci_channel *ch = slot->ch; 1863 device_t dev = ch->dev; 1864 uint32_t sstatus; 1865 int ccs; 1866 int i; 1867 1868 /* Check for stale timeout. */ 1869 if (slot->state < AHCI_SLOT_RUNNING) 1870 return; 1871 1872 /* Check if slot was not being executed last time we checked. */ 1873 if (slot->state < AHCI_SLOT_EXECUTING) { 1874 /* Check if slot started executing. */ 1875 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1876 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1877 >> AHCI_P_CMD_CCS_SHIFT; 1878 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 1879 ch->fbs_enabled || ch->wrongccs) 1880 slot->state = AHCI_SLOT_EXECUTING; 1881 else if ((ch->rslots & (1 << ccs)) == 0) { 1882 ch->wrongccs = 1; 1883 slot->state = AHCI_SLOT_EXECUTING; 1884 } 1885 1886 callout_reset_sbt(&slot->timeout, 1887 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0, 1888 ahci_timeout, slot, 0); 1889 return; 1890 } 1891 1892 device_printf(dev, "Timeout on slot %d port %d\n", 1893 slot->slot, slot->ccb->ccb_h.target_id & 0x0f); 1894 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x " 1895 "serr %08x cmd %08x\n", 1896 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 1897 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1898 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR), 1899 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1900 1901 /* Handle frozen command. */ 1902 if (ch->frozen) { 1903 union ccb *fccb = ch->frozen; 1904 ch->frozen = NULL; 1905 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1906 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1907 xpt_freeze_devq(fccb->ccb_h.path, 1); 1908 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1909 } 1910 ahci_done(ch, fccb); 1911 } 1912 if (!ch->fbs_enabled && !ch->wrongccs) { 1913 /* Without FBS we know real timeout source. */ 1914 ch->fatalerr = 1; 1915 /* Handle command with timeout. */ 1916 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 1917 /* Handle the rest of commands. */ 1918 for (i = 0; i < ch->numslots; i++) { 1919 /* Do we have a running request on slot? */ 1920 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1921 continue; 1922 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1923 } 1924 } else { 1925 /* With FBS we wait for other commands timeout and pray. */ 1926 if (ch->toslots == 0) 1927 xpt_freeze_simq(ch->sim, 1); 1928 ch->toslots |= (1 << slot->slot); 1929 if ((ch->rslots & ~ch->toslots) == 0) 1930 ahci_process_timeout(ch); 1931 else 1932 device_printf(dev, " ... waiting for slots %08x\n", 1933 ch->rslots & ~ch->toslots); 1934 } 1935 } 1936 1937 /* Must be called with channel locked. */ 1938 static void 1939 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 1940 { 1941 struct ahci_channel *ch = slot->ch; 1942 union ccb *ccb = slot->ccb; 1943 struct ahci_cmd_list *clp; 1944 int lastto; 1945 uint32_t sig; 1946 1947 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1948 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1949 clp = (struct ahci_cmd_list *) 1950 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1951 /* Read result registers to the result struct 1952 * May be incorrect if several commands finished same time, 1953 * so read only when sure or have to. 1954 */ 1955 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1956 struct ata_res *res = &ccb->ataio.res; 1957 1958 if ((et == AHCI_ERR_TFE) || 1959 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1960 u_int8_t *fis = ch->dma.rfis + 0x40; 1961 1962 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1963 BUS_DMASYNC_POSTREAD); 1964 if (ch->fbs_enabled) { 1965 fis += ccb->ccb_h.target_id * 256; 1966 res->status = fis[2]; 1967 res->error = fis[3]; 1968 } else { 1969 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 1970 1971 res->status = tfd; 1972 res->error = tfd >> 8; 1973 } 1974 res->lba_low = fis[4]; 1975 res->lba_mid = fis[5]; 1976 res->lba_high = fis[6]; 1977 res->device = fis[7]; 1978 res->lba_low_exp = fis[8]; 1979 res->lba_mid_exp = fis[9]; 1980 res->lba_high_exp = fis[10]; 1981 res->sector_count = fis[12]; 1982 res->sector_count_exp = fis[13]; 1983 1984 /* 1985 * Some weird controllers do not return signature in 1986 * FIS receive area. Read it from PxSIG register. 1987 */ 1988 if ((ch->quirks & AHCI_Q_ALTSIG) && 1989 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1990 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 1991 sig = ATA_INL(ch->r_mem, AHCI_P_SIG); 1992 res->lba_high = sig >> 24; 1993 res->lba_mid = sig >> 16; 1994 res->lba_low = sig >> 8; 1995 res->sector_count = sig; 1996 } 1997 } else 1998 bzero(res, sizeof(*res)); 1999 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 2000 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2001 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2002 ccb->ataio.resid = 2003 ccb->ataio.dxfer_len - le32toh(clp->bytecount); 2004 } 2005 } else { 2006 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2007 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2008 ccb->csio.resid = 2009 ccb->csio.dxfer_len - le32toh(clp->bytecount); 2010 } 2011 } 2012 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2013 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 2014 (ccb->ccb_h.flags & CAM_DIR_IN) ? 2015 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2016 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 2017 } 2018 if (et != AHCI_ERR_NONE) 2019 ch->eslots |= (1 << slot->slot); 2020 /* In case of error, freeze device for proper recovery. */ 2021 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) && 2022 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 2023 xpt_freeze_devq(ccb->ccb_h.path, 1); 2024 ccb->ccb_h.status |= CAM_DEV_QFRZN; 2025 } 2026 /* Set proper result status. */ 2027 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2028 switch (et) { 2029 case AHCI_ERR_NONE: 2030 ccb->ccb_h.status |= CAM_REQ_CMP; 2031 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 2032 ccb->csio.scsi_status = SCSI_STATUS_OK; 2033 break; 2034 case AHCI_ERR_INVALID: 2035 ch->fatalerr = 1; 2036 ccb->ccb_h.status |= CAM_REQ_INVALID; 2037 break; 2038 case AHCI_ERR_INNOCENT: 2039 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 2040 break; 2041 case AHCI_ERR_TFE: 2042 case AHCI_ERR_NCQ: 2043 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2044 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2045 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2046 } else { 2047 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 2048 } 2049 break; 2050 case AHCI_ERR_SATA: 2051 ch->fatalerr = 1; 2052 if (!ch->recoverycmd) { 2053 xpt_freeze_simq(ch->sim, 1); 2054 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2055 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2056 } 2057 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 2058 break; 2059 case AHCI_ERR_TIMEOUT: 2060 if (!ch->recoverycmd) { 2061 xpt_freeze_simq(ch->sim, 1); 2062 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2063 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2064 } 2065 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 2066 break; 2067 default: 2068 ch->fatalerr = 1; 2069 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 2070 } 2071 /* Free slot. */ 2072 ch->oslots &= ~(1 << slot->slot); 2073 ch->rslots &= ~(1 << slot->slot); 2074 ch->aslots &= ~(1 << slot->slot); 2075 slot->state = AHCI_SLOT_EMPTY; 2076 slot->ccb = NULL; 2077 /* Update channel stats. */ 2078 ch->numrslots--; 2079 ch->numrslotspd[ccb->ccb_h.target_id]--; 2080 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2081 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 2082 ch->numtslots--; 2083 ch->numtslotspd[ccb->ccb_h.target_id]--; 2084 } 2085 /* Cancel timeout state if request completed normally. */ 2086 if (et != AHCI_ERR_TIMEOUT) { 2087 lastto = (ch->toslots == (1 << slot->slot)); 2088 ch->toslots &= ~(1 << slot->slot); 2089 if (lastto) 2090 xpt_release_simq(ch->sim, TRUE); 2091 } 2092 /* If it was first request of reset sequence and there is no error, 2093 * proceed to second request. */ 2094 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2095 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2096 (ccb->ataio.cmd.control & ATA_A_RESET) && 2097 et == AHCI_ERR_NONE) { 2098 ccb->ataio.cmd.control &= ~ATA_A_RESET; 2099 ahci_begin_transaction(ch, ccb); 2100 return; 2101 } 2102 /* If it was our READ LOG command - process it. */ 2103 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 2104 ahci_process_read_log(ch, ccb); 2105 /* If it was our REQUEST SENSE command - process it. */ 2106 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 2107 ahci_process_request_sense(ch, ccb); 2108 /* If it was NCQ or ATAPI command error, put result on hold. */ 2109 } else if (et == AHCI_ERR_NCQ || 2110 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 2111 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 2112 ch->hold[slot->slot] = ccb; 2113 ch->numhslots++; 2114 } else 2115 ahci_done(ch, ccb); 2116 /* If we have no other active commands, ... */ 2117 if (ch->rslots == 0) { 2118 /* if there was fatal error - reset port. */ 2119 if (ch->toslots != 0 || ch->fatalerr) { 2120 ahci_reset(ch); 2121 } else { 2122 /* if we have slots in error, we can reinit port. */ 2123 if (ch->eslots != 0) { 2124 ahci_stop(ch); 2125 ahci_clo(ch); 2126 ahci_start(ch, 1); 2127 } 2128 /* if there commands on hold, we can do READ LOG. */ 2129 if (!ch->recoverycmd && ch->numhslots) 2130 ahci_issue_recovery(ch); 2131 } 2132 /* If all the rest of commands are in timeout - give them chance. */ 2133 } else if ((ch->rslots & ~ch->toslots) == 0 && 2134 et != AHCI_ERR_TIMEOUT) 2135 ahci_rearm_timeout(ch); 2136 /* Unfreeze frozen command. */ 2137 if (ch->frozen && !ahci_check_collision(ch, ch->frozen)) { 2138 union ccb *fccb = ch->frozen; 2139 ch->frozen = NULL; 2140 ahci_begin_transaction(ch, fccb); 2141 xpt_release_simq(ch->sim, TRUE); 2142 } 2143 /* Start PM timer. */ 2144 if (ch->numrslots == 0 && ch->pm_level > 3 && 2145 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 2146 callout_schedule(&ch->pm_timer, 2147 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 2148 } 2149 } 2150 2151 static void 2152 ahci_issue_recovery(struct ahci_channel *ch) 2153 { 2154 union ccb *ccb; 2155 struct ccb_ataio *ataio; 2156 struct ccb_scsiio *csio; 2157 int i; 2158 2159 /* Find some held command. */ 2160 for (i = 0; i < ch->numslots; i++) { 2161 if (ch->hold[i]) 2162 break; 2163 } 2164 ccb = xpt_alloc_ccb_nowait(); 2165 if (ccb == NULL) { 2166 device_printf(ch->dev, "Unable to allocate recovery command\n"); 2167 completeall: 2168 /* We can't do anything -- complete held commands. */ 2169 for (i = 0; i < ch->numslots; i++) { 2170 if (ch->hold[i] == NULL) 2171 continue; 2172 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2173 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 2174 ahci_done(ch, ch->hold[i]); 2175 ch->hold[i] = NULL; 2176 ch->numhslots--; 2177 } 2178 ahci_reset(ch); 2179 return; 2180 } 2181 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 2182 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2183 /* READ LOG */ 2184 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 2185 ccb->ccb_h.func_code = XPT_ATA_IO; 2186 ccb->ccb_h.flags = CAM_DIR_IN; 2187 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2188 ataio = &ccb->ataio; 2189 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 2190 if (ataio->data_ptr == NULL) { 2191 xpt_free_ccb(ccb); 2192 device_printf(ch->dev, 2193 "Unable to allocate memory for READ LOG command\n"); 2194 goto completeall; 2195 } 2196 ataio->dxfer_len = 512; 2197 bzero(&ataio->cmd, sizeof(ataio->cmd)); 2198 ataio->cmd.flags = CAM_ATAIO_48BIT; 2199 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 2200 ataio->cmd.sector_count = 1; 2201 ataio->cmd.sector_count_exp = 0; 2202 ataio->cmd.lba_low = 0x10; 2203 ataio->cmd.lba_mid = 0; 2204 ataio->cmd.lba_mid_exp = 0; 2205 } else { 2206 /* REQUEST SENSE */ 2207 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 2208 ccb->ccb_h.recovery_slot = i; 2209 ccb->ccb_h.func_code = XPT_SCSI_IO; 2210 ccb->ccb_h.flags = CAM_DIR_IN; 2211 ccb->ccb_h.status = 0; 2212 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2213 csio = &ccb->csio; 2214 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 2215 csio->dxfer_len = ch->hold[i]->csio.sense_len; 2216 csio->cdb_len = 6; 2217 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 2218 csio->cdb_io.cdb_bytes[0] = 0x03; 2219 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 2220 } 2221 /* Freeze SIM while doing recovery. */ 2222 ch->recoverycmd = 1; 2223 xpt_freeze_simq(ch->sim, 1); 2224 ahci_begin_transaction(ch, ccb); 2225 } 2226 2227 static void 2228 ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb) 2229 { 2230 uint8_t *data; 2231 struct ata_res *res; 2232 int i; 2233 2234 ch->recoverycmd = 0; 2235 2236 data = ccb->ataio.data_ptr; 2237 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2238 (data[0] & 0x80) == 0) { 2239 for (i = 0; i < ch->numslots; i++) { 2240 if (!ch->hold[i]) 2241 continue; 2242 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2243 continue; 2244 if ((data[0] & 0x1F) == i) { 2245 res = &ch->hold[i]->ataio.res; 2246 res->status = data[2]; 2247 res->error = data[3]; 2248 res->lba_low = data[4]; 2249 res->lba_mid = data[5]; 2250 res->lba_high = data[6]; 2251 res->device = data[7]; 2252 res->lba_low_exp = data[8]; 2253 res->lba_mid_exp = data[9]; 2254 res->lba_high_exp = data[10]; 2255 res->sector_count = data[12]; 2256 res->sector_count_exp = data[13]; 2257 } else { 2258 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2259 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2260 } 2261 ahci_done(ch, ch->hold[i]); 2262 ch->hold[i] = NULL; 2263 ch->numhslots--; 2264 } 2265 } else { 2266 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2267 device_printf(ch->dev, "Error while READ LOG EXT\n"); 2268 else if ((data[0] & 0x80) == 0) { 2269 device_printf(ch->dev, "Non-queued command error in READ LOG EXT\n"); 2270 } 2271 for (i = 0; i < ch->numslots; i++) { 2272 if (!ch->hold[i]) 2273 continue; 2274 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2275 continue; 2276 ahci_done(ch, ch->hold[i]); 2277 ch->hold[i] = NULL; 2278 ch->numhslots--; 2279 } 2280 } 2281 free(ccb->ataio.data_ptr, M_AHCI); 2282 xpt_free_ccb(ccb); 2283 xpt_release_simq(ch->sim, TRUE); 2284 } 2285 2286 static void 2287 ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb) 2288 { 2289 int i; 2290 2291 ch->recoverycmd = 0; 2292 2293 i = ccb->ccb_h.recovery_slot; 2294 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 2295 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 2296 } else { 2297 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2298 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 2299 } 2300 ahci_done(ch, ch->hold[i]); 2301 ch->hold[i] = NULL; 2302 ch->numhslots--; 2303 xpt_free_ccb(ccb); 2304 xpt_release_simq(ch->sim, TRUE); 2305 } 2306 2307 static void 2308 ahci_start(struct ahci_channel *ch, int fbs) 2309 { 2310 u_int32_t cmd; 2311 2312 /* Run the channel start callback, if any. */ 2313 if (ch->start) 2314 ch->start(ch); 2315 2316 /* Clear SATA error register */ 2317 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2318 /* Clear any interrupts pending on this channel */ 2319 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2320 /* Configure FIS-based switching if supported. */ 2321 if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2322 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2323 ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2324 ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2325 } 2326 /* Start operations on this channel */ 2327 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2328 cmd &= ~AHCI_P_CMD_PMA; 2329 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2330 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2331 } 2332 2333 static void 2334 ahci_stop(struct ahci_channel *ch) 2335 { 2336 u_int32_t cmd; 2337 int timeout; 2338 2339 /* Kill all activity on this channel */ 2340 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2341 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2342 /* Wait for activity stop. */ 2343 timeout = 0; 2344 do { 2345 DELAY(10); 2346 if (timeout++ > 50000) { 2347 device_printf(ch->dev, "stopping AHCI engine failed\n"); 2348 break; 2349 } 2350 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2351 ch->eslots = 0; 2352 } 2353 2354 static void 2355 ahci_clo(struct ahci_channel *ch) 2356 { 2357 u_int32_t cmd; 2358 int timeout; 2359 2360 /* Issue Command List Override if supported */ 2361 if (ch->caps & AHCI_CAP_SCLO) { 2362 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2363 cmd |= AHCI_P_CMD_CLO; 2364 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2365 timeout = 0; 2366 do { 2367 DELAY(10); 2368 if (timeout++ > 50000) { 2369 device_printf(ch->dev, "executing CLO failed\n"); 2370 break; 2371 } 2372 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2373 } 2374 } 2375 2376 static void 2377 ahci_stop_fr(struct ahci_channel *ch) 2378 { 2379 u_int32_t cmd; 2380 int timeout; 2381 2382 /* Kill all FIS reception on this channel */ 2383 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2384 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2385 /* Wait for FIS reception stop. */ 2386 timeout = 0; 2387 do { 2388 DELAY(10); 2389 if (timeout++ > 50000) { 2390 device_printf(ch->dev, "stopping AHCI FR engine failed\n"); 2391 break; 2392 } 2393 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2394 } 2395 2396 static void 2397 ahci_start_fr(struct ahci_channel *ch) 2398 { 2399 u_int32_t cmd; 2400 2401 /* Start FIS reception on this channel */ 2402 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2403 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2404 } 2405 2406 static int 2407 ahci_wait_ready(struct ahci_channel *ch, int t, int t0) 2408 { 2409 int timeout = 0; 2410 uint32_t val; 2411 2412 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2413 (ATA_S_BUSY | ATA_S_DRQ)) { 2414 if (timeout > t) { 2415 if (t != 0) { 2416 device_printf(ch->dev, 2417 "AHCI reset: device not ready after %dms " 2418 "(tfd = %08x)\n", 2419 MAX(t, 0) + t0, val); 2420 } 2421 return (EBUSY); 2422 } 2423 DELAY(1000); 2424 timeout++; 2425 } 2426 if (bootverbose) 2427 device_printf(ch->dev, "AHCI reset: device ready after %dms\n", 2428 timeout + t0); 2429 return (0); 2430 } 2431 2432 static void 2433 ahci_reset_to(void *arg) 2434 { 2435 struct ahci_channel *ch = arg; 2436 2437 if (ch->resetting == 0) 2438 return; 2439 ch->resetting--; 2440 if (ahci_wait_ready(ch, ch->resetting == 0 ? -1 : 0, 2441 (310 - ch->resetting) * 100) == 0) { 2442 ch->resetting = 0; 2443 ahci_start(ch, 1); 2444 xpt_release_simq(ch->sim, TRUE); 2445 return; 2446 } 2447 if (ch->resetting == 0) { 2448 ahci_clo(ch); 2449 ahci_start(ch, 1); 2450 xpt_release_simq(ch->sim, TRUE); 2451 return; 2452 } 2453 callout_schedule(&ch->reset_timer, hz / 10); 2454 } 2455 2456 static void 2457 ahci_reset(struct ahci_channel *ch) 2458 { 2459 struct ahci_controller *ctlr = device_get_softc(device_get_parent(ch->dev)); 2460 int i; 2461 2462 xpt_freeze_simq(ch->sim, 1); 2463 if (bootverbose) 2464 device_printf(ch->dev, "AHCI reset...\n"); 2465 /* Forget about previous reset. */ 2466 if (ch->resetting) { 2467 ch->resetting = 0; 2468 callout_stop(&ch->reset_timer); 2469 xpt_release_simq(ch->sim, TRUE); 2470 } 2471 /* Requeue freezed command. */ 2472 if (ch->frozen) { 2473 union ccb *fccb = ch->frozen; 2474 ch->frozen = NULL; 2475 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2476 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2477 xpt_freeze_devq(fccb->ccb_h.path, 1); 2478 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2479 } 2480 ahci_done(ch, fccb); 2481 } 2482 /* Kill the engine and requeue all running commands. */ 2483 ahci_stop(ch); 2484 for (i = 0; i < ch->numslots; i++) { 2485 /* Do we have a running request on slot? */ 2486 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2487 continue; 2488 /* XXX; Commands in loading state. */ 2489 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2490 } 2491 for (i = 0; i < ch->numslots; i++) { 2492 if (!ch->hold[i]) 2493 continue; 2494 ahci_done(ch, ch->hold[i]); 2495 ch->hold[i] = NULL; 2496 ch->numhslots--; 2497 } 2498 if (ch->toslots != 0) 2499 xpt_release_simq(ch->sim, TRUE); 2500 ch->eslots = 0; 2501 ch->toslots = 0; 2502 ch->wrongccs = 0; 2503 ch->fatalerr = 0; 2504 /* Tell the XPT about the event */ 2505 xpt_async(AC_BUS_RESET, ch->path, NULL); 2506 /* Disable port interrupts */ 2507 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2508 /* Reset and reconnect PHY, */ 2509 if (!ahci_sata_phy_reset(ch)) { 2510 if (bootverbose) 2511 device_printf(ch->dev, 2512 "AHCI reset: device not found\n"); 2513 ch->devices = 0; 2514 /* Enable wanted port interrupts */ 2515 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2516 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2517 AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2518 xpt_release_simq(ch->sim, TRUE); 2519 return; 2520 } 2521 if (bootverbose) 2522 device_printf(ch->dev, "AHCI reset: device found\n"); 2523 /* Wait for clearing busy status. */ 2524 if (ahci_wait_ready(ch, dumping ? 31000 : 0, 0)) { 2525 if (dumping) 2526 ahci_clo(ch); 2527 else 2528 ch->resetting = 310; 2529 } 2530 ch->devices = 1; 2531 /* Enable wanted port interrupts */ 2532 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2533 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2534 AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2535 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2536 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC | 2537 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2538 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2539 if (ch->resetting) 2540 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, ch); 2541 else { 2542 ahci_start(ch, 1); 2543 xpt_release_simq(ch->sim, TRUE); 2544 } 2545 } 2546 2547 static int 2548 ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2549 { 2550 u_int8_t *fis = &ctp->cfis[0]; 2551 2552 bzero(fis, 20); 2553 fis[0] = 0x27; /* host to device */ 2554 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2555 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2556 fis[1] |= 0x80; 2557 fis[2] = ATA_PACKET_CMD; 2558 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2559 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2560 fis[3] = ATA_F_DMA; 2561 else { 2562 fis[5] = ccb->csio.dxfer_len; 2563 fis[6] = ccb->csio.dxfer_len >> 8; 2564 } 2565 fis[7] = ATA_D_LBA; 2566 fis[15] = ATA_A_4BIT; 2567 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2568 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2569 ctp->acmd, ccb->csio.cdb_len); 2570 bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len); 2571 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2572 fis[1] |= 0x80; 2573 fis[2] = ccb->ataio.cmd.command; 2574 fis[3] = ccb->ataio.cmd.features; 2575 fis[4] = ccb->ataio.cmd.lba_low; 2576 fis[5] = ccb->ataio.cmd.lba_mid; 2577 fis[6] = ccb->ataio.cmd.lba_high; 2578 fis[7] = ccb->ataio.cmd.device; 2579 fis[8] = ccb->ataio.cmd.lba_low_exp; 2580 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2581 fis[10] = ccb->ataio.cmd.lba_high_exp; 2582 fis[11] = ccb->ataio.cmd.features_exp; 2583 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2584 fis[12] = tag << 3; 2585 } else { 2586 fis[12] = ccb->ataio.cmd.sector_count; 2587 } 2588 fis[13] = ccb->ataio.cmd.sector_count_exp; 2589 fis[15] = ATA_A_4BIT; 2590 } else { 2591 fis[15] = ccb->ataio.cmd.control; 2592 } 2593 if (ccb->ataio.ata_flags & ATA_FLAG_AUX) { 2594 fis[16] = ccb->ataio.aux & 0xff; 2595 fis[17] = (ccb->ataio.aux >> 8) & 0xff; 2596 fis[18] = (ccb->ataio.aux >> 16) & 0xff; 2597 fis[19] = (ccb->ataio.aux >> 24) & 0xff; 2598 } 2599 return (20); 2600 } 2601 2602 static int 2603 ahci_sata_connect(struct ahci_channel *ch) 2604 { 2605 u_int32_t status; 2606 int timeout, found = 0; 2607 2608 /* Wait up to 100ms for "connect well" */ 2609 for (timeout = 0; timeout < 1000 ; timeout++) { 2610 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2611 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 2612 found = 1; 2613 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2614 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2615 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2616 break; 2617 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2618 if (bootverbose) { 2619 device_printf(ch->dev, "SATA offline status=%08x\n", 2620 status); 2621 } 2622 return (0); 2623 } 2624 if (found == 0 && timeout >= 100) 2625 break; 2626 DELAY(100); 2627 } 2628 if (timeout >= 1000 || !found) { 2629 if (bootverbose) { 2630 device_printf(ch->dev, 2631 "SATA connect timeout time=%dus status=%08x\n", 2632 timeout * 100, status); 2633 } 2634 return (0); 2635 } 2636 if (bootverbose) { 2637 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n", 2638 timeout * 100, status); 2639 } 2640 /* Clear SATA error register */ 2641 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2642 return (1); 2643 } 2644 2645 static int 2646 ahci_sata_phy_reset(struct ahci_channel *ch) 2647 { 2648 int sata_rev; 2649 uint32_t val, detval; 2650 2651 if (ch->listening) { 2652 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2653 val |= AHCI_P_CMD_SUD; 2654 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2655 ch->listening = 0; 2656 } 2657 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2658 if (sata_rev == 1) 2659 val = ATA_SC_SPD_SPEED_GEN1; 2660 else if (sata_rev == 2) 2661 val = ATA_SC_SPD_SPEED_GEN2; 2662 else if (sata_rev == 3) 2663 val = ATA_SC_SPD_SPEED_GEN3; 2664 else 2665 val = 0; 2666 detval = ahci_ch_detval(ch, ATA_SC_DET_RESET); 2667 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2668 detval | val | 2669 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2670 DELAY(1000); 2671 detval = ahci_ch_detval(ch, ATA_SC_DET_IDLE); 2672 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2673 detval | val | ((ch->pm_level > 0) ? 0 : 2674 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2675 if (!ahci_sata_connect(ch)) { 2676 if (ch->caps & AHCI_CAP_SSS) { 2677 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2678 val &= ~AHCI_P_CMD_SUD; 2679 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2680 ch->listening = 1; 2681 } else if (ch->pm_level > 0) 2682 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2683 return (0); 2684 } 2685 return (1); 2686 } 2687 2688 static int 2689 ahci_check_ids(struct ahci_channel *ch, union ccb *ccb) 2690 { 2691 2692 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) { 2693 ccb->ccb_h.status = CAM_TID_INVALID; 2694 ahci_done(ch, ccb); 2695 return (-1); 2696 } 2697 if (ccb->ccb_h.target_lun != 0) { 2698 ccb->ccb_h.status = CAM_LUN_INVALID; 2699 ahci_done(ch, ccb); 2700 return (-1); 2701 } 2702 return (0); 2703 } 2704 2705 static void 2706 ahciaction(struct cam_sim *sim, union ccb *ccb) 2707 { 2708 struct ahci_channel *ch; 2709 2710 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2711 ccb->ccb_h.func_code)); 2712 2713 ch = (struct ahci_channel *)cam_sim_softc(sim); 2714 switch (ccb->ccb_h.func_code) { 2715 /* Common cases first */ 2716 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2717 case XPT_SCSI_IO: 2718 if (ahci_check_ids(ch, ccb)) 2719 return; 2720 if (ch->devices == 0 || 2721 (ch->pm_present == 0 && 2722 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2723 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2724 break; 2725 } 2726 ccb->ccb_h.recovery_type = RECOVERY_NONE; 2727 /* Check for command collision. */ 2728 if (ahci_check_collision(ch, ccb)) { 2729 /* Freeze command. */ 2730 ch->frozen = ccb; 2731 /* We have only one frozen slot, so freeze simq also. */ 2732 xpt_freeze_simq(ch->sim, 1); 2733 return; 2734 } 2735 ahci_begin_transaction(ch, ccb); 2736 return; 2737 case XPT_ABORT: /* Abort the specified CCB */ 2738 /* XXX Implement */ 2739 ccb->ccb_h.status = CAM_REQ_INVALID; 2740 break; 2741 case XPT_SET_TRAN_SETTINGS: 2742 { 2743 struct ccb_trans_settings *cts = &ccb->cts; 2744 struct ahci_device *d; 2745 2746 if (ahci_check_ids(ch, ccb)) 2747 return; 2748 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2749 d = &ch->curr[ccb->ccb_h.target_id]; 2750 else 2751 d = &ch->user[ccb->ccb_h.target_id]; 2752 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2753 d->revision = cts->xport_specific.sata.revision; 2754 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2755 d->mode = cts->xport_specific.sata.mode; 2756 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2757 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2758 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2759 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2760 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2761 ch->pm_present = cts->xport_specific.sata.pm_present; 2762 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2763 d->atapi = cts->xport_specific.sata.atapi; 2764 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2765 d->caps = cts->xport_specific.sata.caps; 2766 ccb->ccb_h.status = CAM_REQ_CMP; 2767 break; 2768 } 2769 case XPT_GET_TRAN_SETTINGS: 2770 /* Get default/user set transfer settings for the target */ 2771 { 2772 struct ccb_trans_settings *cts = &ccb->cts; 2773 struct ahci_device *d; 2774 uint32_t status; 2775 2776 if (ahci_check_ids(ch, ccb)) 2777 return; 2778 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2779 d = &ch->curr[ccb->ccb_h.target_id]; 2780 else 2781 d = &ch->user[ccb->ccb_h.target_id]; 2782 cts->protocol = PROTO_UNSPECIFIED; 2783 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2784 cts->transport = XPORT_SATA; 2785 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2786 cts->proto_specific.valid = 0; 2787 cts->xport_specific.sata.valid = 0; 2788 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2789 (ccb->ccb_h.target_id == 15 || 2790 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2791 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2792 if (status & 0x0f0) { 2793 cts->xport_specific.sata.revision = 2794 (status & 0x0f0) >> 4; 2795 cts->xport_specific.sata.valid |= 2796 CTS_SATA_VALID_REVISION; 2797 } 2798 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2799 if (ch->pm_level) { 2800 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC)) 2801 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2802 if (ch->caps2 & AHCI_CAP2_APST) 2803 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST; 2804 } 2805 if ((ch->caps & AHCI_CAP_SNCQ) && 2806 (ch->quirks & AHCI_Q_NOAA) == 0) 2807 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA; 2808 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 2809 cts->xport_specific.sata.caps &= 2810 ch->user[ccb->ccb_h.target_id].caps; 2811 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2812 } else { 2813 cts->xport_specific.sata.revision = d->revision; 2814 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2815 cts->xport_specific.sata.caps = d->caps; 2816 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2817 } 2818 cts->xport_specific.sata.mode = d->mode; 2819 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2820 cts->xport_specific.sata.bytecount = d->bytecount; 2821 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2822 cts->xport_specific.sata.pm_present = ch->pm_present; 2823 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2824 cts->xport_specific.sata.tags = d->tags; 2825 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2826 cts->xport_specific.sata.atapi = d->atapi; 2827 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2828 ccb->ccb_h.status = CAM_REQ_CMP; 2829 break; 2830 } 2831 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2832 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2833 ahci_reset(ch); 2834 ccb->ccb_h.status = CAM_REQ_CMP; 2835 break; 2836 case XPT_TERM_IO: /* Terminate the I/O process */ 2837 /* XXX Implement */ 2838 ccb->ccb_h.status = CAM_REQ_INVALID; 2839 break; 2840 case XPT_PATH_INQ: /* Path routing inquiry */ 2841 { 2842 struct ccb_pathinq *cpi = &ccb->cpi; 2843 2844 cpi->version_num = 1; /* XXX??? */ 2845 cpi->hba_inquiry = PI_SDTR_ABLE; 2846 if (ch->caps & AHCI_CAP_SNCQ) 2847 cpi->hba_inquiry |= PI_TAG_ABLE; 2848 if (ch->caps & AHCI_CAP_SPM) 2849 cpi->hba_inquiry |= PI_SATAPM; 2850 cpi->target_sprt = 0; 2851 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED; 2852 if ((ch->quirks & AHCI_Q_NOAUX) == 0) 2853 cpi->hba_misc |= PIM_ATA_EXT; 2854 cpi->hba_eng_cnt = 0; 2855 if (ch->caps & AHCI_CAP_SPM) 2856 cpi->max_target = 15; 2857 else 2858 cpi->max_target = 0; 2859 cpi->max_lun = 0; 2860 cpi->initiator_id = 0; 2861 cpi->bus_id = cam_sim_bus(sim); 2862 cpi->base_transfer_speed = 150000; 2863 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2864 strlcpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 2865 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2866 cpi->unit_number = cam_sim_unit(sim); 2867 cpi->transport = XPORT_SATA; 2868 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2869 cpi->protocol = PROTO_ATA; 2870 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2871 cpi->maxio = MAXPHYS; 2872 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 2873 if (ch->quirks & AHCI_Q_MAXIO_64K) 2874 cpi->maxio = min(cpi->maxio, 128 * 512); 2875 cpi->hba_vendor = ch->vendorid; 2876 cpi->hba_device = ch->deviceid; 2877 cpi->hba_subvendor = ch->subvendorid; 2878 cpi->hba_subdevice = ch->subdeviceid; 2879 cpi->ccb_h.status = CAM_REQ_CMP; 2880 break; 2881 } 2882 default: 2883 ccb->ccb_h.status = CAM_REQ_INVALID; 2884 break; 2885 } 2886 ahci_done(ch, ccb); 2887 } 2888 2889 static void 2890 ahcipoll(struct cam_sim *sim) 2891 { 2892 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 2893 uint32_t istatus; 2894 2895 /* Read interrupt statuses and process if any. */ 2896 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 2897 if (istatus != 0) 2898 ahci_ch_intr_main(ch, istatus); 2899 if (ch->resetting != 0 && 2900 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) { 2901 ch->resetpolldiv = 1000; 2902 ahci_reset_to(ch); 2903 } 2904 } 2905 2906 devclass_t ahci_devclass; 2907 2908 MODULE_VERSION(ahci, 1); 2909 MODULE_DEPEND(ahci, cam, 1, 1, 1); 2910