xref: /freebsd/sys/dev/ahci/ahci.c (revision 603eaf792b659f91d7d1a065d82503966d1386fc)
1 /*-
2  * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer,
10  *    without modification, immediately at the beginning of the file.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  */
26 
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29 
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/bus.h>
35 #include <sys/conf.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <machine/stdarg.h>
41 #include <machine/resource.h>
42 #include <machine/bus.h>
43 #include <sys/rman.h>
44 #include "ahci.h"
45 
46 #include <cam/cam.h>
47 #include <cam/cam_ccb.h>
48 #include <cam/cam_sim.h>
49 #include <cam/cam_xpt_sim.h>
50 #include <cam/cam_debug.h>
51 
52 /* local prototypes */
53 static void ahci_intr(void *data);
54 static void ahci_intr_one(void *data);
55 static void ahci_intr_one_edge(void *data);
56 static int ahci_ch_init(device_t dev);
57 static int ahci_ch_deinit(device_t dev);
58 static int ahci_ch_suspend(device_t dev);
59 static int ahci_ch_resume(device_t dev);
60 static void ahci_ch_pm(void *arg);
61 static void ahci_ch_intr(void *arg);
62 static void ahci_ch_intr_direct(void *arg);
63 static void ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus);
64 static void ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb);
65 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
66 static void ahci_execute_transaction(struct ahci_slot *slot);
67 static void ahci_timeout(struct ahci_slot *slot);
68 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et);
69 static int ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag);
70 static void ahci_dmainit(device_t dev);
71 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
72 static void ahci_dmafini(device_t dev);
73 static void ahci_slotsalloc(device_t dev);
74 static void ahci_slotsfree(device_t dev);
75 static void ahci_reset(struct ahci_channel *ch);
76 static void ahci_start(struct ahci_channel *ch, int fbs);
77 static void ahci_stop(struct ahci_channel *ch);
78 static void ahci_clo(struct ahci_channel *ch);
79 static void ahci_start_fr(struct ahci_channel *ch);
80 static void ahci_stop_fr(struct ahci_channel *ch);
81 
82 static int ahci_sata_connect(struct ahci_channel *ch);
83 static int ahci_sata_phy_reset(struct ahci_channel *ch);
84 static int ahci_wait_ready(struct ahci_channel *ch, int t, int t0);
85 
86 static void ahci_issue_recovery(struct ahci_channel *ch);
87 static void ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb);
88 static void ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb);
89 
90 static void ahciaction(struct cam_sim *sim, union ccb *ccb);
91 static void ahcipoll(struct cam_sim *sim);
92 
93 static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers");
94 
95 #define recovery_type		spriv_field0
96 #define RECOVERY_NONE		0
97 #define RECOVERY_READ_LOG	1
98 #define RECOVERY_REQUEST_SENSE	2
99 #define recovery_slot		spriv_field1
100 
101 int
102 ahci_ctlr_setup(device_t dev)
103 {
104 	struct ahci_controller *ctlr = device_get_softc(dev);
105 	/* Clear interrupts */
106 	ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS));
107 	/* Configure CCC */
108 	if (ctlr->ccc) {
109 		ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI));
110 		ATA_OUTL(ctlr->r_mem, AHCI_CCCC,
111 		    (ctlr->ccc << AHCI_CCCC_TV_SHIFT) |
112 		    (4 << AHCI_CCCC_CC_SHIFT) |
113 		    AHCI_CCCC_EN);
114 		ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) &
115 		    AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT;
116 		if (bootverbose) {
117 			device_printf(dev,
118 			    "CCC with %dms/4cmd enabled on vector %d\n",
119 			    ctlr->ccc, ctlr->cccv);
120 		}
121 	}
122 	/* Enable AHCI interrupts */
123 	ATA_OUTL(ctlr->r_mem, AHCI_GHC,
124 	    ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE);
125 	return (0);
126 }
127 
128 int
129 ahci_ctlr_reset(device_t dev)
130 {
131 	struct ahci_controller *ctlr = device_get_softc(dev);
132 	int timeout;
133 
134 	/* Enable AHCI mode */
135 	ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
136 	/* Reset AHCI controller */
137 	ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR);
138 	for (timeout = 1000; timeout > 0; timeout--) {
139 		DELAY(1000);
140 		if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0)
141 			break;
142 	}
143 	if (timeout == 0) {
144 		device_printf(dev, "AHCI controller reset failure\n");
145 		return ENXIO;
146 	}
147 	/* Reenable AHCI mode */
148 	ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
149 	return (0);
150 }
151 
152 
153 int
154 ahci_attach(device_t dev)
155 {
156 	struct ahci_controller *ctlr = device_get_softc(dev);
157 	int error, i, u, speed, unit;
158 	u_int32_t version;
159 	device_t child;
160 
161 	ctlr->dev = dev;
162 	ctlr->ccc = 0;
163 	resource_int_value(device_get_name(dev),
164 	    device_get_unit(dev), "ccc", &ctlr->ccc);
165 
166 	/* Setup our own memory management for channels. */
167 	ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
168 	ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
169 	ctlr->sc_iomem.rm_type = RMAN_ARRAY;
170 	ctlr->sc_iomem.rm_descr = "I/O memory addresses";
171 	if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
172 		bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
173 		return (error);
174 	}
175 	if ((error = rman_manage_region(&ctlr->sc_iomem,
176 	    rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
177 		bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
178 		rman_fini(&ctlr->sc_iomem);
179 		return (error);
180 	}
181 	/* Get the HW capabilities */
182 	version = ATA_INL(ctlr->r_mem, AHCI_VS);
183 	ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
184 	if (version >= 0x00010200)
185 		ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2);
186 	if (ctlr->caps & AHCI_CAP_EMS)
187 		ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL);
188 	ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI);
189 
190 	/* Identify and set separate quirks for HBA and RAID f/w Marvells. */
191 	if ((ctlr->quirks & AHCI_Q_ALTSIG) &&
192 	    (ctlr->caps & AHCI_CAP_SPM) == 0)
193 		ctlr->quirks |= AHCI_Q_NOBSYRES;
194 
195 	if (ctlr->quirks & AHCI_Q_1CH) {
196 		ctlr->caps &= ~AHCI_CAP_NPMASK;
197 		ctlr->ichannels &= 0x01;
198 	}
199 	if (ctlr->quirks & AHCI_Q_2CH) {
200 		ctlr->caps &= ~AHCI_CAP_NPMASK;
201 		ctlr->caps |= 1;
202 		ctlr->ichannels &= 0x03;
203 	}
204 	if (ctlr->quirks & AHCI_Q_4CH) {
205 		ctlr->caps &= ~AHCI_CAP_NPMASK;
206 		ctlr->caps |= 3;
207 		ctlr->ichannels &= 0x0f;
208 	}
209 	ctlr->channels = MAX(flsl(ctlr->ichannels),
210 	    (ctlr->caps & AHCI_CAP_NPMASK) + 1);
211 	if (ctlr->quirks & AHCI_Q_NOPMP)
212 		ctlr->caps &= ~AHCI_CAP_SPM;
213 	if (ctlr->quirks & AHCI_Q_NONCQ)
214 		ctlr->caps &= ~AHCI_CAP_SNCQ;
215 	if ((ctlr->caps & AHCI_CAP_CCCS) == 0)
216 		ctlr->ccc = 0;
217 	ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC);
218 
219 	/* Create controller-wide DMA tag. */
220 	if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
221 	    (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR :
222 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
223 	    BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE,
224 	    0, NULL, NULL, &ctlr->dma_tag)) {
225 		bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid,
226 		    ctlr->r_mem);
227 		rman_fini(&ctlr->sc_iomem);
228 		return ENXIO;
229 	}
230 
231 	ahci_ctlr_setup(dev);
232 
233 	/* Setup interrupts. */
234 	if (ahci_setup_interrupt(dev)) {
235 		bus_dma_tag_destroy(ctlr->dma_tag);
236 		bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid,
237 		    ctlr->r_mem);
238 		rman_fini(&ctlr->sc_iomem);
239 		return ENXIO;
240 	}
241 
242 	i = 0;
243 	for (u = ctlr->ichannels; u != 0; u >>= 1)
244 		i += (u & 1);
245 	ctlr->direct = (ctlr->msi && (ctlr->numirqs > 1 || i <= 3));
246 	resource_int_value(device_get_name(dev), device_get_unit(dev),
247 	    "direct", &ctlr->direct);
248 	/* Announce HW capabilities. */
249 	speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT;
250 	device_printf(dev,
251 		    "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n",
252 		    ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f),
253 		    ((version >> 4) & 0xf0) + (version & 0x0f),
254 		    (ctlr->caps & AHCI_CAP_NPMASK) + 1,
255 		    ((speed == 1) ? "1.5":((speed == 2) ? "3":
256 		    ((speed == 3) ? "6":"?"))),
257 		    (ctlr->caps & AHCI_CAP_SPM) ?
258 		    "supported" : "not supported",
259 		    (ctlr->caps & AHCI_CAP_FBSS) ?
260 		    " with FBS" : "");
261 	if (ctlr->quirks != 0) {
262 		device_printf(dev, "quirks=0x%b\n", ctlr->quirks,
263 		    AHCI_Q_BIT_STRING);
264 	}
265 	if (bootverbose) {
266 		device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps",
267 		    (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"",
268 		    (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"",
269 		    (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"",
270 		    (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"",
271 		    (ctlr->caps & AHCI_CAP_SSS) ? " SS":"",
272 		    (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"",
273 		    (ctlr->caps & AHCI_CAP_SAL) ? " AL":"",
274 		    (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"",
275 		    ((speed == 1) ? "1.5":((speed == 2) ? "3":
276 		    ((speed == 3) ? "6":"?"))));
277 		printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n",
278 		    (ctlr->caps & AHCI_CAP_SAM) ? " AM":"",
279 		    (ctlr->caps & AHCI_CAP_SPM) ? " PM":"",
280 		    (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"",
281 		    (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"",
282 		    (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"",
283 		    (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"",
284 		    ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1,
285 		    (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"",
286 		    (ctlr->caps & AHCI_CAP_EMS) ? " EM":"",
287 		    (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"",
288 		    (ctlr->caps & AHCI_CAP_NPMASK) + 1);
289 	}
290 	if (bootverbose && version >= 0x00010200) {
291 		device_printf(dev, "Caps2:%s%s%s%s%s%s\n",
292 		    (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"",
293 		    (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"",
294 		    (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"",
295 		    (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"",
296 		    (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"",
297 		    (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":"");
298 	}
299 	/* Attach all channels on this controller */
300 	for (unit = 0; unit < ctlr->channels; unit++) {
301 		child = device_add_child(dev, "ahcich", -1);
302 		if (child == NULL) {
303 			device_printf(dev, "failed to add channel device\n");
304 			continue;
305 		}
306 		device_set_ivars(child, (void *)(intptr_t)unit);
307 		if ((ctlr->ichannels & (1 << unit)) == 0)
308 			device_disable(child);
309 	}
310 	if (ctlr->caps & AHCI_CAP_EMS) {
311 		child = device_add_child(dev, "ahciem", -1);
312 		if (child == NULL)
313 			device_printf(dev, "failed to add enclosure device\n");
314 		else
315 			device_set_ivars(child, (void *)(intptr_t)-1);
316 	}
317 	bus_generic_attach(dev);
318 	return 0;
319 }
320 
321 int
322 ahci_detach(device_t dev)
323 {
324 	struct ahci_controller *ctlr = device_get_softc(dev);
325 	int i;
326 
327 	/* Detach & delete all children */
328 	device_delete_children(dev);
329 
330 	/* Free interrupts. */
331 	for (i = 0; i < ctlr->numirqs; i++) {
332 		if (ctlr->irqs[i].r_irq) {
333 			bus_teardown_intr(dev, ctlr->irqs[i].r_irq,
334 			    ctlr->irqs[i].handle);
335 			bus_release_resource(dev, SYS_RES_IRQ,
336 			    ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq);
337 		}
338 	}
339 	bus_dma_tag_destroy(ctlr->dma_tag);
340 	/* Free memory. */
341 	rman_fini(&ctlr->sc_iomem);
342 	if (ctlr->r_mem)
343 		bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
344 	return (0);
345 }
346 
347 int
348 ahci_setup_interrupt(device_t dev)
349 {
350 	struct ahci_controller *ctlr = device_get_softc(dev);
351 	int i;
352 
353 	/* Check for single MSI vector fallback. */
354 	if (ctlr->numirqs > 1 &&
355 	    (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) {
356 		device_printf(dev, "Falling back to one MSI\n");
357 		ctlr->numirqs = 1;
358 	}
359 	/* Allocate all IRQs. */
360 	for (i = 0; i < ctlr->numirqs; i++) {
361 		ctlr->irqs[i].ctlr = ctlr;
362 		ctlr->irqs[i].r_irq_rid = i + (ctlr->msi ? 1 : 0);
363 		if (ctlr->channels == 1 && !ctlr->ccc && ctlr->msi)
364 			ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
365 		else if (ctlr->numirqs == 1 || i >= ctlr->channels ||
366 		    (ctlr->ccc && i == ctlr->cccv))
367 			ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL;
368 		else if (i == ctlr->numirqs - 1)
369 			ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER;
370 		else
371 			ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
372 		if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
373 		    &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
374 			device_printf(dev, "unable to map interrupt\n");
375 			return ENXIO;
376 		}
377 		if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL,
378 		    (ctlr->irqs[i].mode != AHCI_IRQ_MODE_ONE) ? ahci_intr :
379 		     ((ctlr->quirks & AHCI_Q_EDGEIS) ? ahci_intr_one_edge :
380 		      ahci_intr_one),
381 		    &ctlr->irqs[i], &ctlr->irqs[i].handle))) {
382 			/* SOS XXX release r_irq */
383 			device_printf(dev, "unable to setup interrupt\n");
384 			return ENXIO;
385 		}
386 		if (ctlr->numirqs > 1) {
387 			bus_describe_intr(dev, ctlr->irqs[i].r_irq,
388 			    ctlr->irqs[i].handle,
389 			    ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ?
390 			    "ch%d" : "%d", i);
391 		}
392 	}
393 	return (0);
394 }
395 
396 /*
397  * Common case interrupt handler.
398  */
399 static void
400 ahci_intr(void *data)
401 {
402 	struct ahci_controller_irq *irq = data;
403 	struct ahci_controller *ctlr = irq->ctlr;
404 	u_int32_t is, ise = 0;
405 	void *arg;
406 	int unit;
407 
408 	if (irq->mode == AHCI_IRQ_MODE_ALL) {
409 		unit = 0;
410 		if (ctlr->ccc)
411 			is = ctlr->ichannels;
412 		else
413 			is = ATA_INL(ctlr->r_mem, AHCI_IS);
414 	} else {	/* AHCI_IRQ_MODE_AFTER */
415 		unit = irq->r_irq_rid - 1;
416 		is = ATA_INL(ctlr->r_mem, AHCI_IS);
417 	}
418 	/* CCC interrupt is edge triggered. */
419 	if (ctlr->ccc)
420 		ise = 1 << ctlr->cccv;
421 	/* Some controllers have edge triggered IS. */
422 	if (ctlr->quirks & AHCI_Q_EDGEIS)
423 		ise |= is;
424 	if (ise != 0)
425 		ATA_OUTL(ctlr->r_mem, AHCI_IS, ise);
426 	for (; unit < ctlr->channels; unit++) {
427 		if ((is & (1 << unit)) != 0 &&
428 		    (arg = ctlr->interrupt[unit].argument)) {
429 				ctlr->interrupt[unit].function(arg);
430 		}
431 	}
432 	/* AHCI declares level triggered IS. */
433 	if (!(ctlr->quirks & AHCI_Q_EDGEIS))
434 		ATA_OUTL(ctlr->r_mem, AHCI_IS, is);
435 }
436 
437 /*
438  * Simplified interrupt handler for multivector MSI mode.
439  */
440 static void
441 ahci_intr_one(void *data)
442 {
443 	struct ahci_controller_irq *irq = data;
444 	struct ahci_controller *ctlr = irq->ctlr;
445 	void *arg;
446 	int unit;
447 
448 	unit = irq->r_irq_rid - 1;
449 	if ((arg = ctlr->interrupt[unit].argument))
450 	    ctlr->interrupt[unit].function(arg);
451 	/* AHCI declares level triggered IS. */
452 	ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
453 }
454 
455 static void
456 ahci_intr_one_edge(void *data)
457 {
458 	struct ahci_controller_irq *irq = data;
459 	struct ahci_controller *ctlr = irq->ctlr;
460 	void *arg;
461 	int unit;
462 
463 	unit = irq->r_irq_rid - 1;
464 	/* Some controllers have edge triggered IS. */
465 	ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
466 	if ((arg = ctlr->interrupt[unit].argument))
467 		ctlr->interrupt[unit].function(arg);
468 }
469 
470 struct resource *
471 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid,
472     u_long start, u_long end, u_long count, u_int flags)
473 {
474 	struct ahci_controller *ctlr = device_get_softc(dev);
475 	struct resource *res;
476 	long st;
477 	int offset, size, unit;
478 
479 	unit = (intptr_t)device_get_ivars(child);
480 	res = NULL;
481 	switch (type) {
482 	case SYS_RES_MEMORY:
483 		if (unit >= 0) {
484 			offset = AHCI_OFFSET + (unit << 7);
485 			size = 128;
486 		} else if (*rid == 0) {
487 			offset = AHCI_EM_CTL;
488 			size = 4;
489 		} else {
490 			offset = (ctlr->emloc & 0xffff0000) >> 14;
491 			size = (ctlr->emloc & 0x0000ffff) << 2;
492 			if (*rid != 1) {
493 				if (*rid == 2 && (ctlr->capsem &
494 				    (AHCI_EM_XMT | AHCI_EM_SMB)) == 0)
495 					offset += size;
496 				else
497 					break;
498 			}
499 		}
500 		st = rman_get_start(ctlr->r_mem);
501 		res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
502 		    st + offset + size - 1, size, RF_ACTIVE, child);
503 		if (res) {
504 			bus_space_handle_t bsh;
505 			bus_space_tag_t bst;
506 			bsh = rman_get_bushandle(ctlr->r_mem);
507 			bst = rman_get_bustag(ctlr->r_mem);
508 			bus_space_subregion(bst, bsh, offset, 128, &bsh);
509 			rman_set_bushandle(res, bsh);
510 			rman_set_bustag(res, bst);
511 		}
512 		break;
513 	case SYS_RES_IRQ:
514 		if (*rid == ATA_IRQ_RID)
515 			res = ctlr->irqs[0].r_irq;
516 		break;
517 	}
518 	return (res);
519 }
520 
521 int
522 ahci_release_resource(device_t dev, device_t child, int type, int rid,
523     struct resource *r)
524 {
525 
526 	switch (type) {
527 	case SYS_RES_MEMORY:
528 		rman_release_resource(r);
529 		return (0);
530 	case SYS_RES_IRQ:
531 		if (rid != ATA_IRQ_RID)
532 			return ENOENT;
533 		return (0);
534 	}
535 	return (EINVAL);
536 }
537 
538 int
539 ahci_setup_intr(device_t dev, device_t child, struct resource *irq,
540     int flags, driver_filter_t *filter, driver_intr_t *function,
541     void *argument, void **cookiep)
542 {
543 	struct ahci_controller *ctlr = device_get_softc(dev);
544 	int unit = (intptr_t)device_get_ivars(child);
545 
546 	if (filter != NULL) {
547 		printf("ahci.c: we cannot use a filter here\n");
548 		return (EINVAL);
549 	}
550 	ctlr->interrupt[unit].function = function;
551 	ctlr->interrupt[unit].argument = argument;
552 	return (0);
553 }
554 
555 int
556 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq,
557     void *cookie)
558 {
559 	struct ahci_controller *ctlr = device_get_softc(dev);
560 	int unit = (intptr_t)device_get_ivars(child);
561 
562 	ctlr->interrupt[unit].function = NULL;
563 	ctlr->interrupt[unit].argument = NULL;
564 	return (0);
565 }
566 
567 int
568 ahci_print_child(device_t dev, device_t child)
569 {
570 	int retval, channel;
571 
572 	retval = bus_print_child_header(dev, child);
573 	channel = (int)(intptr_t)device_get_ivars(child);
574 	if (channel >= 0)
575 		retval += printf(" at channel %d", channel);
576 	retval += bus_print_child_footer(dev, child);
577 	return (retval);
578 }
579 
580 int
581 ahci_child_location_str(device_t dev, device_t child, char *buf,
582     size_t buflen)
583 {
584 	int channel;
585 
586 	channel = (int)(intptr_t)device_get_ivars(child);
587 	if (channel >= 0)
588 		snprintf(buf, buflen, "channel=%d", channel);
589 	return (0);
590 }
591 
592 bus_dma_tag_t
593 ahci_get_dma_tag(device_t dev, device_t child)
594 {
595 	struct ahci_controller *ctlr = device_get_softc(dev);
596 
597 	return (ctlr->dma_tag);
598 }
599 
600 static int
601 ahci_ch_probe(device_t dev)
602 {
603 
604 	device_set_desc_copy(dev, "AHCI channel");
605 	return (0);
606 }
607 
608 static int
609 ahci_ch_attach(device_t dev)
610 {
611 	struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
612 	struct ahci_channel *ch = device_get_softc(dev);
613 	struct cam_devq *devq;
614 	int rid, error, i, sata_rev = 0;
615 	u_int32_t version;
616 
617 	ch->dev = dev;
618 	ch->unit = (intptr_t)device_get_ivars(dev);
619 	ch->caps = ctlr->caps;
620 	ch->caps2 = ctlr->caps2;
621 	ch->quirks = ctlr->quirks;
622 	ch->vendorid = ctlr->vendorid;
623 	ch->deviceid = ctlr->deviceid;
624 	ch->subvendorid = ctlr->subvendorid;
625 	ch->subdeviceid = ctlr->subdeviceid;
626 	ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1;
627 	mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF);
628 	ch->pm_level = 0;
629 	resource_int_value(device_get_name(dev),
630 	    device_get_unit(dev), "pm_level", &ch->pm_level);
631 	STAILQ_INIT(&ch->doneq);
632 	if (ch->pm_level > 3)
633 		callout_init_mtx(&ch->pm_timer, &ch->mtx, 0);
634 	callout_init_mtx(&ch->reset_timer, &ch->mtx, 0);
635 	/* JMicron external ports (0) sometimes limited */
636 	if ((ctlr->quirks & AHCI_Q_SATA1_UNIT0) && ch->unit == 0)
637 		sata_rev = 1;
638 	if (ch->quirks & AHCI_Q_SATA2)
639 		sata_rev = 2;
640 	resource_int_value(device_get_name(dev),
641 	    device_get_unit(dev), "sata_rev", &sata_rev);
642 	for (i = 0; i < 16; i++) {
643 		ch->user[i].revision = sata_rev;
644 		ch->user[i].mode = 0;
645 		ch->user[i].bytecount = 8192;
646 		ch->user[i].tags = ch->numslots;
647 		ch->user[i].caps = 0;
648 		ch->curr[i] = ch->user[i];
649 		if (ch->pm_level) {
650 			ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ |
651 			    CTS_SATA_CAPS_H_APST |
652 			    CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST;
653 		}
654 		ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA |
655 		    CTS_SATA_CAPS_H_AN;
656 	}
657 	rid = 0;
658 	if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
659 	    &rid, RF_ACTIVE)))
660 		return (ENXIO);
661 	ahci_dmainit(dev);
662 	ahci_slotsalloc(dev);
663 	ahci_ch_init(dev);
664 	mtx_lock(&ch->mtx);
665 	rid = ATA_IRQ_RID;
666 	if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
667 	    &rid, RF_SHAREABLE | RF_ACTIVE))) {
668 		device_printf(dev, "Unable to map interrupt\n");
669 		error = ENXIO;
670 		goto err0;
671 	}
672 	if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL,
673 	    ctlr->direct ? ahci_ch_intr_direct : ahci_ch_intr,
674 	    ch, &ch->ih))) {
675 		device_printf(dev, "Unable to setup interrupt\n");
676 		error = ENXIO;
677 		goto err1;
678 	}
679 	ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD);
680 	version = ATA_INL(ctlr->r_mem, AHCI_VS);
681 	if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS))
682 		ch->chcaps |= AHCI_P_CMD_FBSCP;
683 	if (ch->caps2 & AHCI_CAP2_SDS)
684 		ch->chscaps = ATA_INL(ch->r_mem, AHCI_P_DEVSLP);
685 	if (bootverbose) {
686 		device_printf(dev, "Caps:%s%s%s%s%s%s\n",
687 		    (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"",
688 		    (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"",
689 		    (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"",
690 		    (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"",
691 		    (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"",
692 		    (ch->chscaps & AHCI_P_DEVSLP_DSP) ? " DSP":"");
693 	}
694 	/* Create the device queue for our SIM. */
695 	devq = cam_simq_alloc(ch->numslots);
696 	if (devq == NULL) {
697 		device_printf(dev, "Unable to allocate simq\n");
698 		error = ENOMEM;
699 		goto err1;
700 	}
701 	/* Construct SIM entry */
702 	ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch,
703 	    device_get_unit(dev), (struct mtx *)&ch->mtx,
704 	    min(2, ch->numslots),
705 	    (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0,
706 	    devq);
707 	if (ch->sim == NULL) {
708 		cam_simq_free(devq);
709 		device_printf(dev, "unable to allocate sim\n");
710 		error = ENOMEM;
711 		goto err1;
712 	}
713 	if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) {
714 		device_printf(dev, "unable to register xpt bus\n");
715 		error = ENXIO;
716 		goto err2;
717 	}
718 	if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim),
719 	    CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
720 		device_printf(dev, "unable to create path\n");
721 		error = ENXIO;
722 		goto err3;
723 	}
724 	if (ch->pm_level > 3) {
725 		callout_reset(&ch->pm_timer,
726 		    (ch->pm_level == 4) ? hz / 1000 : hz / 8,
727 		    ahci_ch_pm, ch);
728 	}
729 	mtx_unlock(&ch->mtx);
730 	return (0);
731 
732 err3:
733 	xpt_bus_deregister(cam_sim_path(ch->sim));
734 err2:
735 	cam_sim_free(ch->sim, /*free_devq*/TRUE);
736 err1:
737 	bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
738 err0:
739 	bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
740 	mtx_unlock(&ch->mtx);
741 	mtx_destroy(&ch->mtx);
742 	return (error);
743 }
744 
745 static int
746 ahci_ch_detach(device_t dev)
747 {
748 	struct ahci_channel *ch = device_get_softc(dev);
749 
750 	mtx_lock(&ch->mtx);
751 	xpt_async(AC_LOST_DEVICE, ch->path, NULL);
752 	/* Forget about reset. */
753 	if (ch->resetting) {
754 		ch->resetting = 0;
755 		xpt_release_simq(ch->sim, TRUE);
756 	}
757 	xpt_free_path(ch->path);
758 	xpt_bus_deregister(cam_sim_path(ch->sim));
759 	cam_sim_free(ch->sim, /*free_devq*/TRUE);
760 	mtx_unlock(&ch->mtx);
761 
762 	if (ch->pm_level > 3)
763 		callout_drain(&ch->pm_timer);
764 	callout_drain(&ch->reset_timer);
765 	bus_teardown_intr(dev, ch->r_irq, ch->ih);
766 	bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
767 
768 	ahci_ch_deinit(dev);
769 	ahci_slotsfree(dev);
770 	ahci_dmafini(dev);
771 
772 	bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
773 	mtx_destroy(&ch->mtx);
774 	return (0);
775 }
776 
777 static int
778 ahci_ch_init(device_t dev)
779 {
780 	struct ahci_channel *ch = device_get_softc(dev);
781 	uint64_t work;
782 
783 	/* Disable port interrupts */
784 	ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
785 	/* Setup work areas */
786 	work = ch->dma.work_bus + AHCI_CL_OFFSET;
787 	ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff);
788 	ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32);
789 	work = ch->dma.rfis_bus;
790 	ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff);
791 	ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32);
792 	/* Activate the channel and power/spin up device */
793 	ATA_OUTL(ch->r_mem, AHCI_P_CMD,
794 	     (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD |
795 	     ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) |
796 	     ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 )));
797 	ahci_start_fr(ch);
798 	ahci_start(ch, 1);
799 	return (0);
800 }
801 
802 static int
803 ahci_ch_deinit(device_t dev)
804 {
805 	struct ahci_channel *ch = device_get_softc(dev);
806 
807 	/* Disable port interrupts. */
808 	ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
809 	/* Reset command register. */
810 	ahci_stop(ch);
811 	ahci_stop_fr(ch);
812 	ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0);
813 	/* Allow everything, including partial and slumber modes. */
814 	ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0);
815 	/* Request slumber mode transition and give some time to get there. */
816 	ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER);
817 	DELAY(100);
818 	/* Disable PHY. */
819 	ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
820 	return (0);
821 }
822 
823 static int
824 ahci_ch_suspend(device_t dev)
825 {
826 	struct ahci_channel *ch = device_get_softc(dev);
827 
828 	mtx_lock(&ch->mtx);
829 	xpt_freeze_simq(ch->sim, 1);
830 	/* Forget about reset. */
831 	if (ch->resetting) {
832 		ch->resetting = 0;
833 		callout_stop(&ch->reset_timer);
834 		xpt_release_simq(ch->sim, TRUE);
835 	}
836 	while (ch->oslots)
837 		msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100);
838 	ahci_ch_deinit(dev);
839 	mtx_unlock(&ch->mtx);
840 	return (0);
841 }
842 
843 static int
844 ahci_ch_resume(device_t dev)
845 {
846 	struct ahci_channel *ch = device_get_softc(dev);
847 
848 	mtx_lock(&ch->mtx);
849 	ahci_ch_init(dev);
850 	ahci_reset(ch);
851 	xpt_release_simq(ch->sim, TRUE);
852 	mtx_unlock(&ch->mtx);
853 	return (0);
854 }
855 
856 devclass_t ahcich_devclass;
857 static device_method_t ahcich_methods[] = {
858 	DEVMETHOD(device_probe,     ahci_ch_probe),
859 	DEVMETHOD(device_attach,    ahci_ch_attach),
860 	DEVMETHOD(device_detach,    ahci_ch_detach),
861 	DEVMETHOD(device_suspend,   ahci_ch_suspend),
862 	DEVMETHOD(device_resume,    ahci_ch_resume),
863 	{ 0, 0 }
864 };
865 static driver_t ahcich_driver = {
866         "ahcich",
867         ahcich_methods,
868         sizeof(struct ahci_channel)
869 };
870 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0);
871 
872 struct ahci_dc_cb_args {
873 	bus_addr_t maddr;
874 	int error;
875 };
876 
877 static void
878 ahci_dmainit(device_t dev)
879 {
880 	struct ahci_channel *ch = device_get_softc(dev);
881 	struct ahci_dc_cb_args dcba;
882 	size_t rfsize;
883 
884 	/* Command area. */
885 	if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0,
886 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
887 	    NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE,
888 	    0, NULL, NULL, &ch->dma.work_tag))
889 		goto error;
890 	if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work,
891 	    BUS_DMA_ZERO, &ch->dma.work_map))
892 		goto error;
893 	if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work,
894 	    AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
895 		bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
896 		goto error;
897 	}
898 	ch->dma.work_bus = dcba.maddr;
899 	/* FIS receive area. */
900 	if (ch->chcaps & AHCI_P_CMD_FBSCP)
901 	    rfsize = 4096;
902 	else
903 	    rfsize = 256;
904 	if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0,
905 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
906 	    NULL, NULL, rfsize, 1, rfsize,
907 	    0, NULL, NULL, &ch->dma.rfis_tag))
908 		goto error;
909 	if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0,
910 	    &ch->dma.rfis_map))
911 		goto error;
912 	if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis,
913 	    rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
914 		bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
915 		goto error;
916 	}
917 	ch->dma.rfis_bus = dcba.maddr;
918 	/* Data area. */
919 	if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
920 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
921 	    NULL, NULL,
922 	    AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots,
923 	    AHCI_SG_ENTRIES, AHCI_PRD_MAX,
924 	    0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) {
925 		goto error;
926 	}
927 	return;
928 
929 error:
930 	device_printf(dev, "WARNING - DMA initialization failed\n");
931 	ahci_dmafini(dev);
932 }
933 
934 static void
935 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
936 {
937 	struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc;
938 
939 	if (!(dcba->error = error))
940 		dcba->maddr = segs[0].ds_addr;
941 }
942 
943 static void
944 ahci_dmafini(device_t dev)
945 {
946 	struct ahci_channel *ch = device_get_softc(dev);
947 
948 	if (ch->dma.data_tag) {
949 		bus_dma_tag_destroy(ch->dma.data_tag);
950 		ch->dma.data_tag = NULL;
951 	}
952 	if (ch->dma.rfis_bus) {
953 		bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map);
954 		bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
955 		ch->dma.rfis_bus = 0;
956 		ch->dma.rfis = NULL;
957 	}
958 	if (ch->dma.work_bus) {
959 		bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map);
960 		bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
961 		ch->dma.work_bus = 0;
962 		ch->dma.work = NULL;
963 	}
964 	if (ch->dma.work_tag) {
965 		bus_dma_tag_destroy(ch->dma.work_tag);
966 		ch->dma.work_tag = NULL;
967 	}
968 }
969 
970 static void
971 ahci_slotsalloc(device_t dev)
972 {
973 	struct ahci_channel *ch = device_get_softc(dev);
974 	int i;
975 
976 	/* Alloc and setup command/dma slots */
977 	bzero(ch->slot, sizeof(ch->slot));
978 	for (i = 0; i < ch->numslots; i++) {
979 		struct ahci_slot *slot = &ch->slot[i];
980 
981 		slot->ch = ch;
982 		slot->slot = i;
983 		slot->state = AHCI_SLOT_EMPTY;
984 		slot->ccb = NULL;
985 		callout_init_mtx(&slot->timeout, &ch->mtx, 0);
986 
987 		if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map))
988 			device_printf(ch->dev, "FAILURE - create data_map\n");
989 	}
990 }
991 
992 static void
993 ahci_slotsfree(device_t dev)
994 {
995 	struct ahci_channel *ch = device_get_softc(dev);
996 	int i;
997 
998 	/* Free all dma slots */
999 	for (i = 0; i < ch->numslots; i++) {
1000 		struct ahci_slot *slot = &ch->slot[i];
1001 
1002 		callout_drain(&slot->timeout);
1003 		if (slot->dma.data_map) {
1004 			bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map);
1005 			slot->dma.data_map = NULL;
1006 		}
1007 	}
1008 }
1009 
1010 static int
1011 ahci_phy_check_events(struct ahci_channel *ch, u_int32_t serr)
1012 {
1013 
1014 	if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) ||
1015 	    ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) {
1016 		u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
1017 		union ccb *ccb;
1018 
1019 		if (bootverbose) {
1020 			if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
1021 				device_printf(ch->dev, "CONNECT requested\n");
1022 			else
1023 				device_printf(ch->dev, "DISCONNECT requested\n");
1024 		}
1025 		ahci_reset(ch);
1026 		if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1027 			return (0);
1028 		if (xpt_create_path(&ccb->ccb_h.path, NULL,
1029 		    cam_sim_path(ch->sim),
1030 		    CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1031 			xpt_free_ccb(ccb);
1032 			return (0);
1033 		}
1034 		xpt_rescan(ccb);
1035 		return (1);
1036 	}
1037 	return (0);
1038 }
1039 
1040 static void
1041 ahci_cpd_check_events(struct ahci_channel *ch)
1042 {
1043 	u_int32_t status;
1044 	union ccb *ccb;
1045 	device_t dev;
1046 
1047 	if (ch->pm_level == 0)
1048 		return;
1049 
1050 	status = ATA_INL(ch->r_mem, AHCI_P_CMD);
1051 	if ((status & AHCI_P_CMD_CPD) == 0)
1052 		return;
1053 
1054 	if (bootverbose) {
1055 		dev = ch->dev;
1056 		if (status & AHCI_P_CMD_CPS) {
1057 			device_printf(dev, "COLD CONNECT requested\n");
1058 		} else
1059 			device_printf(dev, "COLD DISCONNECT requested\n");
1060 	}
1061 	ahci_reset(ch);
1062 	if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1063 		return;
1064 	if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim),
1065 	    CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1066 		xpt_free_ccb(ccb);
1067 		return;
1068 	}
1069 	xpt_rescan(ccb);
1070 }
1071 
1072 static void
1073 ahci_notify_events(struct ahci_channel *ch, u_int32_t status)
1074 {
1075 	struct cam_path *dpath;
1076 	int i;
1077 
1078 	if (ch->caps & AHCI_CAP_SSNTF)
1079 		ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status);
1080 	if (bootverbose)
1081 		device_printf(ch->dev, "SNTF 0x%04x\n", status);
1082 	for (i = 0; i < 16; i++) {
1083 		if ((status & (1 << i)) == 0)
1084 			continue;
1085 		if (xpt_create_path(&dpath, NULL,
1086 		    xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) {
1087 			xpt_async(AC_SCSI_AEN, dpath, NULL);
1088 			xpt_free_path(dpath);
1089 		}
1090 	}
1091 }
1092 
1093 static void
1094 ahci_done(struct ahci_channel *ch, union ccb *ccb)
1095 {
1096 
1097 	mtx_assert(&ch->mtx, MA_OWNED);
1098 	if ((ccb->ccb_h.func_code & XPT_FC_QUEUED) == 0 ||
1099 	    ch->batch == 0) {
1100 		xpt_done(ccb);
1101 		return;
1102 	}
1103 
1104 	STAILQ_INSERT_TAIL(&ch->doneq, &ccb->ccb_h, sim_links.stqe);
1105 }
1106 
1107 static void
1108 ahci_ch_intr(void *arg)
1109 {
1110 	struct ahci_channel *ch = (struct ahci_channel *)arg;
1111 	uint32_t istatus;
1112 
1113 	/* Read interrupt statuses. */
1114 	istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1115 	if (istatus == 0)
1116 		return;
1117 
1118 	mtx_lock(&ch->mtx);
1119 	ahci_ch_intr_main(ch, istatus);
1120 	mtx_unlock(&ch->mtx);
1121 }
1122 
1123 static void
1124 ahci_ch_intr_direct(void *arg)
1125 {
1126 	struct ahci_channel *ch = (struct ahci_channel *)arg;
1127 	struct ccb_hdr *ccb_h;
1128 	uint32_t istatus;
1129 	STAILQ_HEAD(, ccb_hdr) tmp_doneq = STAILQ_HEAD_INITIALIZER(tmp_doneq);
1130 
1131 	/* Read interrupt statuses. */
1132 	istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1133 	if (istatus == 0)
1134 		return;
1135 
1136 	mtx_lock(&ch->mtx);
1137 	ch->batch = 1;
1138 	ahci_ch_intr_main(ch, istatus);
1139 	ch->batch = 0;
1140 	/*
1141 	 * Prevent the possibility of issues caused by processing the queue
1142 	 * while unlocked below by moving the contents to a local queue.
1143 	 */
1144 	STAILQ_CONCAT(&tmp_doneq, &ch->doneq);
1145 	mtx_unlock(&ch->mtx);
1146 	while ((ccb_h = STAILQ_FIRST(&tmp_doneq)) != NULL) {
1147 		STAILQ_REMOVE_HEAD(&tmp_doneq, sim_links.stqe);
1148 		xpt_done_direct((union ccb *)ccb_h);
1149 	}
1150 }
1151 
1152 static void
1153 ahci_ch_pm(void *arg)
1154 {
1155 	struct ahci_channel *ch = (struct ahci_channel *)arg;
1156 	uint32_t work;
1157 
1158 	if (ch->numrslots != 0)
1159 		return;
1160 	work = ATA_INL(ch->r_mem, AHCI_P_CMD);
1161 	if (ch->pm_level == 4)
1162 		work |= AHCI_P_CMD_PARTIAL;
1163 	else
1164 		work |= AHCI_P_CMD_SLUMBER;
1165 	ATA_OUTL(ch->r_mem, AHCI_P_CMD, work);
1166 }
1167 
1168 static void
1169 ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus)
1170 {
1171 	uint32_t cstatus, serr = 0, sntf = 0, ok, err;
1172 	enum ahci_err_type et;
1173 	int i, ccs, port, reset = 0;
1174 
1175 	/* Clear interrupt statuses. */
1176 	ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus);
1177 	/* Read command statuses. */
1178 	if (ch->numtslots != 0)
1179 		cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1180 	else
1181 		cstatus = 0;
1182 	if (ch->numrslots != ch->numtslots)
1183 		cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI);
1184 	/* Read SNTF in one of possible ways. */
1185 	if ((istatus & AHCI_P_IX_SDB) &&
1186 	    (ch->pm_present || ch->curr[0].atapi != 0)) {
1187 		if (ch->caps & AHCI_CAP_SSNTF)
1188 			sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF);
1189 		else if (ch->fbs_enabled) {
1190 			u_int8_t *fis = ch->dma.rfis + 0x58;
1191 
1192 			for (i = 0; i < 16; i++) {
1193 				if (fis[1] & 0x80) {
1194 					fis[1] &= 0x7f;
1195 	    				sntf |= 1 << i;
1196 	    			}
1197 	    			fis += 256;
1198 	    		}
1199 		} else {
1200 			u_int8_t *fis = ch->dma.rfis + 0x58;
1201 
1202 			if (fis[1] & 0x80)
1203 				sntf = (1 << (fis[1] & 0x0f));
1204 		}
1205 	}
1206 	/* Process PHY events */
1207 	if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF |
1208 	    AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1209 		serr = ATA_INL(ch->r_mem, AHCI_P_SERR);
1210 		if (serr) {
1211 			ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr);
1212 			reset = ahci_phy_check_events(ch, serr);
1213 		}
1214 	}
1215 	/* Process cold presence detection events */
1216 	if ((istatus & AHCI_P_IX_CPD) && !reset)
1217 		ahci_cpd_check_events(ch);
1218 	/* Process command errors */
1219 	if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF |
1220 	    AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1221 		ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
1222 		    >> AHCI_P_CMD_CCS_SHIFT;
1223 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n",
1224 //    __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD),
1225 //    serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs);
1226 		port = -1;
1227 		if (ch->fbs_enabled) {
1228 			uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS);
1229 			if (fbs & AHCI_P_FBS_SDE) {
1230 				port = (fbs & AHCI_P_FBS_DWE)
1231 				    >> AHCI_P_FBS_DWE_SHIFT;
1232 			} else {
1233 				for (i = 0; i < 16; i++) {
1234 					if (ch->numrslotspd[i] == 0)
1235 						continue;
1236 					if (port == -1)
1237 						port = i;
1238 					else if (port != i) {
1239 						port = -2;
1240 						break;
1241 					}
1242 				}
1243 			}
1244 		}
1245 		err = ch->rslots & cstatus;
1246 	} else {
1247 		ccs = 0;
1248 		err = 0;
1249 		port = -1;
1250 	}
1251 	/* Complete all successfull commands. */
1252 	ok = ch->rslots & ~cstatus;
1253 	for (i = 0; i < ch->numslots; i++) {
1254 		if ((ok >> i) & 1)
1255 			ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE);
1256 	}
1257 	/* On error, complete the rest of commands with error statuses. */
1258 	if (err) {
1259 		if (ch->frozen) {
1260 			union ccb *fccb = ch->frozen;
1261 			ch->frozen = NULL;
1262 			fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1263 			if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1264 				xpt_freeze_devq(fccb->ccb_h.path, 1);
1265 				fccb->ccb_h.status |= CAM_DEV_QFRZN;
1266 			}
1267 			ahci_done(ch, fccb);
1268 		}
1269 		for (i = 0; i < ch->numslots; i++) {
1270 			/* XXX: reqests in loading state. */
1271 			if (((err >> i) & 1) == 0)
1272 				continue;
1273 			if (port >= 0 &&
1274 			    ch->slot[i].ccb->ccb_h.target_id != port)
1275 				continue;
1276 			if (istatus & AHCI_P_IX_TFE) {
1277 			    if (port != -2) {
1278 				/* Task File Error */
1279 				if (ch->numtslotspd[
1280 				    ch->slot[i].ccb->ccb_h.target_id] == 0) {
1281 					/* Untagged operation. */
1282 					if (i == ccs)
1283 						et = AHCI_ERR_TFE;
1284 					else
1285 						et = AHCI_ERR_INNOCENT;
1286 				} else {
1287 					/* Tagged operation. */
1288 					et = AHCI_ERR_NCQ;
1289 				}
1290 			    } else {
1291 				et = AHCI_ERR_TFE;
1292 				ch->fatalerr = 1;
1293 			    }
1294 			} else if (istatus & AHCI_P_IX_IF) {
1295 				if (ch->numtslots == 0 && i != ccs && port != -2)
1296 					et = AHCI_ERR_INNOCENT;
1297 				else
1298 					et = AHCI_ERR_SATA;
1299 			} else
1300 				et = AHCI_ERR_INVALID;
1301 			ahci_end_transaction(&ch->slot[i], et);
1302 		}
1303 		/*
1304 		 * We can't reinit port if there are some other
1305 		 * commands active, use resume to complete them.
1306 		 */
1307 		if (ch->rslots != 0 && !ch->recoverycmd)
1308 			ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC);
1309 	}
1310 	/* Process NOTIFY events */
1311 	if (sntf)
1312 		ahci_notify_events(ch, sntf);
1313 }
1314 
1315 /* Must be called with channel locked. */
1316 static int
1317 ahci_check_collision(struct ahci_channel *ch, union ccb *ccb)
1318 {
1319 	int t = ccb->ccb_h.target_id;
1320 
1321 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1322 	    (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1323 		/* Tagged command while we have no supported tag free. */
1324 		if (((~ch->oslots) & (0xffffffff >> (32 -
1325 		    ch->curr[t].tags))) == 0)
1326 			return (1);
1327 		/* If we have FBS */
1328 		if (ch->fbs_enabled) {
1329 			/* Tagged command while untagged are active. */
1330 			if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0)
1331 				return (1);
1332 		} else {
1333 			/* Tagged command while untagged are active. */
1334 			if (ch->numrslots != 0 && ch->numtslots == 0)
1335 				return (1);
1336 			/* Tagged command while tagged to other target is active. */
1337 			if (ch->numtslots != 0 &&
1338 			    ch->taggedtarget != ccb->ccb_h.target_id)
1339 				return (1);
1340 		}
1341 	} else {
1342 		/* If we have FBS */
1343 		if (ch->fbs_enabled) {
1344 			/* Untagged command while tagged are active. */
1345 			if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0)
1346 				return (1);
1347 		} else {
1348 			/* Untagged command while tagged are active. */
1349 			if (ch->numrslots != 0 && ch->numtslots != 0)
1350 				return (1);
1351 		}
1352 	}
1353 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1354 	    (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) {
1355 		/* Atomic command while anything active. */
1356 		if (ch->numrslots != 0)
1357 			return (1);
1358 	}
1359        /* We have some atomic command running. */
1360        if (ch->aslots != 0)
1361                return (1);
1362 	return (0);
1363 }
1364 
1365 /* Must be called with channel locked. */
1366 static void
1367 ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb)
1368 {
1369 	struct ahci_slot *slot;
1370 	int tag, tags;
1371 
1372 	/* Choose empty slot. */
1373 	tags = ch->numslots;
1374 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1375 	    (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA))
1376 		tags = ch->curr[ccb->ccb_h.target_id].tags;
1377 	if (ch->lastslot + 1 < tags)
1378 		tag = ffs(~(ch->oslots >> (ch->lastslot + 1)));
1379 	else
1380 		tag = 0;
1381 	if (tag == 0 || tag + ch->lastslot >= tags)
1382 		tag = ffs(~ch->oslots) - 1;
1383 	else
1384 		tag += ch->lastslot;
1385 	ch->lastslot = tag;
1386 	/* Occupy chosen slot. */
1387 	slot = &ch->slot[tag];
1388 	slot->ccb = ccb;
1389 	/* Stop PM timer. */
1390 	if (ch->numrslots == 0 && ch->pm_level > 3)
1391 		callout_stop(&ch->pm_timer);
1392 	/* Update channel stats. */
1393 	ch->oslots |= (1 << tag);
1394 	ch->numrslots++;
1395 	ch->numrslotspd[ccb->ccb_h.target_id]++;
1396 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1397 	    (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1398 		ch->numtslots++;
1399 		ch->numtslotspd[ccb->ccb_h.target_id]++;
1400 		ch->taggedtarget = ccb->ccb_h.target_id;
1401 	}
1402 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1403 	    (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)))
1404 		ch->aslots |= (1 << tag);
1405 	if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1406 		slot->state = AHCI_SLOT_LOADING;
1407 		bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb,
1408 		    ahci_dmasetprd, slot, 0);
1409 	} else {
1410 		slot->dma.nsegs = 0;
1411 		ahci_execute_transaction(slot);
1412 	}
1413 }
1414 
1415 /* Locked by busdma engine. */
1416 static void
1417 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1418 {
1419 	struct ahci_slot *slot = arg;
1420 	struct ahci_channel *ch = slot->ch;
1421 	struct ahci_cmd_tab *ctp;
1422 	struct ahci_dma_prd *prd;
1423 	int i;
1424 
1425 	if (error) {
1426 		device_printf(ch->dev, "DMA load error\n");
1427 		ahci_end_transaction(slot, AHCI_ERR_INVALID);
1428 		return;
1429 	}
1430 	KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n"));
1431 	/* Get a piece of the workspace for this request */
1432 	ctp = (struct ahci_cmd_tab *)
1433 		(ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1434 	/* Fill S/G table */
1435 	prd = &ctp->prd_tab[0];
1436 	for (i = 0; i < nsegs; i++) {
1437 		prd[i].dba = htole64(segs[i].ds_addr);
1438 		prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK);
1439 	}
1440 	slot->dma.nsegs = nsegs;
1441 	bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1442 	    ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ?
1443 	    BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
1444 	ahci_execute_transaction(slot);
1445 }
1446 
1447 /* Must be called with channel locked. */
1448 static void
1449 ahci_execute_transaction(struct ahci_slot *slot)
1450 {
1451 	struct ahci_channel *ch = slot->ch;
1452 	struct ahci_cmd_tab *ctp;
1453 	struct ahci_cmd_list *clp;
1454 	union ccb *ccb = slot->ccb;
1455 	int port = ccb->ccb_h.target_id & 0x0f;
1456 	int fis_size, i, softreset;
1457 	uint8_t *fis = ch->dma.rfis + 0x40;
1458 	uint8_t val;
1459 
1460 	/* Get a piece of the workspace for this request */
1461 	ctp = (struct ahci_cmd_tab *)
1462 		(ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1463 	/* Setup the FIS for this request */
1464 	if (!(fis_size = ahci_setup_fis(ch, ctp, ccb, slot->slot))) {
1465 		device_printf(ch->dev, "Setting up SATA FIS failed\n");
1466 		ahci_end_transaction(slot, AHCI_ERR_INVALID);
1467 		return;
1468 	}
1469 	/* Setup the command list entry */
1470 	clp = (struct ahci_cmd_list *)
1471 	    (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1472 	clp->cmd_flags = htole16(
1473 		    (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) |
1474 		    (ccb->ccb_h.func_code == XPT_SCSI_IO ?
1475 		     (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) |
1476 		    (fis_size / sizeof(u_int32_t)) |
1477 		    (port << 12));
1478 	clp->prd_length = htole16(slot->dma.nsegs);
1479 	/* Special handling for Soft Reset command. */
1480 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1481 	    (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) {
1482 		if (ccb->ataio.cmd.control & ATA_A_RESET) {
1483 			softreset = 1;
1484 			/* Kick controller into sane state */
1485 			ahci_stop(ch);
1486 			ahci_clo(ch);
1487 			ahci_start(ch, 0);
1488 			clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY;
1489 		} else {
1490 			softreset = 2;
1491 			/* Prepare FIS receive area for check. */
1492 			for (i = 0; i < 20; i++)
1493 				fis[i] = 0xff;
1494 		}
1495 	} else
1496 		softreset = 0;
1497 	clp->bytecount = 0;
1498 	clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET +
1499 				  (AHCI_CT_SIZE * slot->slot));
1500 	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1501 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1502 	bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1503 	    BUS_DMASYNC_PREREAD);
1504 	/* Set ACTIVE bit for NCQ commands. */
1505 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1506 	    (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1507 		ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot);
1508 	}
1509 	/* If FBS is enabled, set PMP port. */
1510 	if (ch->fbs_enabled) {
1511 		ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN |
1512 		    (port << AHCI_P_FBS_DEV_SHIFT));
1513 	}
1514 	/* Issue command to the controller. */
1515 	slot->state = AHCI_SLOT_RUNNING;
1516 	ch->rslots |= (1 << slot->slot);
1517 	ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot));
1518 	/* Device reset commands doesn't interrupt. Poll them. */
1519 	if (ccb->ccb_h.func_code == XPT_ATA_IO &&
1520 	    (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) {
1521 		int count, timeout = ccb->ccb_h.timeout * 100;
1522 		enum ahci_err_type et = AHCI_ERR_NONE;
1523 
1524 		for (count = 0; count < timeout; count++) {
1525 			DELAY(10);
1526 			if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot)))
1527 				break;
1528 			if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) &&
1529 			    softreset != 1) {
1530 #if 0
1531 				device_printf(ch->dev,
1532 				    "Poll error on slot %d, TFD: %04x\n",
1533 				    slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD));
1534 #endif
1535 				et = AHCI_ERR_TFE;
1536 				break;
1537 			}
1538 			/* Workaround for ATI SB600/SB700 chipsets. */
1539 			if (ccb->ccb_h.target_id == 15 &&
1540 			    (ch->quirks & AHCI_Q_ATI_PMP_BUG) &&
1541 			    (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) {
1542 				et = AHCI_ERR_TIMEOUT;
1543 				break;
1544 			}
1545 		}
1546 
1547 		/*
1548 		 * Marvell HBAs with non-RAID firmware do not wait for
1549 		 * readiness after soft reset, so we have to wait here.
1550 		 * Marvell RAIDs do not have this problem, but instead
1551 		 * sometimes forget to update FIS receive area, breaking
1552 		 * this wait.
1553 		 */
1554 		if ((ch->quirks & AHCI_Q_NOBSYRES) == 0 &&
1555 		    (ch->quirks & AHCI_Q_ATI_PMP_BUG) == 0 &&
1556 		    softreset == 2 && et == AHCI_ERR_NONE) {
1557 			while ((val = fis[2]) & ATA_S_BUSY) {
1558 				DELAY(10);
1559 				if (count++ >= timeout)
1560 					break;
1561 			}
1562 		}
1563 
1564 		if (timeout && (count >= timeout)) {
1565 			device_printf(ch->dev, "Poll timeout on slot %d port %d\n",
1566 			    slot->slot, port);
1567 			device_printf(ch->dev, "is %08x cs %08x ss %08x "
1568 			    "rs %08x tfd %02x serr %08x cmd %08x\n",
1569 			    ATA_INL(ch->r_mem, AHCI_P_IS),
1570 			    ATA_INL(ch->r_mem, AHCI_P_CI),
1571 			    ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1572 			    ATA_INL(ch->r_mem, AHCI_P_TFD),
1573 			    ATA_INL(ch->r_mem, AHCI_P_SERR),
1574 			    ATA_INL(ch->r_mem, AHCI_P_CMD));
1575 			et = AHCI_ERR_TIMEOUT;
1576 		}
1577 
1578 		/* Kick controller into sane state and enable FBS. */
1579 		if (softreset == 2)
1580 			ch->eslots |= (1 << slot->slot);
1581 		ahci_end_transaction(slot, et);
1582 		return;
1583 	}
1584 	/* Start command execution timeout */
1585 	callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000,
1586 	    (timeout_t*)ahci_timeout, slot);
1587 	return;
1588 }
1589 
1590 /* Must be called with channel locked. */
1591 static void
1592 ahci_process_timeout(struct ahci_channel *ch)
1593 {
1594 	int i;
1595 
1596 	mtx_assert(&ch->mtx, MA_OWNED);
1597 	/* Handle the rest of commands. */
1598 	for (i = 0; i < ch->numslots; i++) {
1599 		/* Do we have a running request on slot? */
1600 		if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1601 			continue;
1602 		ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT);
1603 	}
1604 }
1605 
1606 /* Must be called with channel locked. */
1607 static void
1608 ahci_rearm_timeout(struct ahci_channel *ch)
1609 {
1610 	int i;
1611 
1612 	mtx_assert(&ch->mtx, MA_OWNED);
1613 	for (i = 0; i < ch->numslots; i++) {
1614 		struct ahci_slot *slot = &ch->slot[i];
1615 
1616 		/* Do we have a running request on slot? */
1617 		if (slot->state < AHCI_SLOT_RUNNING)
1618 			continue;
1619 		if ((ch->toslots & (1 << i)) == 0)
1620 			continue;
1621 		callout_reset(&slot->timeout,
1622 		    (int)slot->ccb->ccb_h.timeout * hz / 2000,
1623 		    (timeout_t*)ahci_timeout, slot);
1624 	}
1625 }
1626 
1627 /* Locked by callout mechanism. */
1628 static void
1629 ahci_timeout(struct ahci_slot *slot)
1630 {
1631 	struct ahci_channel *ch = slot->ch;
1632 	device_t dev = ch->dev;
1633 	uint32_t sstatus;
1634 	int ccs;
1635 	int i;
1636 
1637 	/* Check for stale timeout. */
1638 	if (slot->state < AHCI_SLOT_RUNNING)
1639 		return;
1640 
1641 	/* Check if slot was not being executed last time we checked. */
1642 	if (slot->state < AHCI_SLOT_EXECUTING) {
1643 		/* Check if slot started executing. */
1644 		sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1645 		ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
1646 		    >> AHCI_P_CMD_CCS_SHIFT;
1647 		if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot ||
1648 		    ch->fbs_enabled || ch->wrongccs)
1649 			slot->state = AHCI_SLOT_EXECUTING;
1650 		else if ((ch->rslots & (1 << ccs)) == 0) {
1651 			ch->wrongccs = 1;
1652 			slot->state = AHCI_SLOT_EXECUTING;
1653 		}
1654 
1655 		callout_reset(&slot->timeout,
1656 		    (int)slot->ccb->ccb_h.timeout * hz / 2000,
1657 		    (timeout_t*)ahci_timeout, slot);
1658 		return;
1659 	}
1660 
1661 	device_printf(dev, "Timeout on slot %d port %d\n",
1662 	    slot->slot, slot->ccb->ccb_h.target_id & 0x0f);
1663 	device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x "
1664 	    "serr %08x cmd %08x\n",
1665 	    ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI),
1666 	    ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1667 	    ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR),
1668 	    ATA_INL(ch->r_mem, AHCI_P_CMD));
1669 
1670 	/* Handle frozen command. */
1671 	if (ch->frozen) {
1672 		union ccb *fccb = ch->frozen;
1673 		ch->frozen = NULL;
1674 		fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1675 		if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1676 			xpt_freeze_devq(fccb->ccb_h.path, 1);
1677 			fccb->ccb_h.status |= CAM_DEV_QFRZN;
1678 		}
1679 		ahci_done(ch, fccb);
1680 	}
1681 	if (!ch->fbs_enabled && !ch->wrongccs) {
1682 		/* Without FBS we know real timeout source. */
1683 		ch->fatalerr = 1;
1684 		/* Handle command with timeout. */
1685 		ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT);
1686 		/* Handle the rest of commands. */
1687 		for (i = 0; i < ch->numslots; i++) {
1688 			/* Do we have a running request on slot? */
1689 			if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1690 				continue;
1691 			ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
1692 		}
1693 	} else {
1694 		/* With FBS we wait for other commands timeout and pray. */
1695 		if (ch->toslots == 0)
1696 			xpt_freeze_simq(ch->sim, 1);
1697 		ch->toslots |= (1 << slot->slot);
1698 		if ((ch->rslots & ~ch->toslots) == 0)
1699 			ahci_process_timeout(ch);
1700 		else
1701 			device_printf(dev, " ... waiting for slots %08x\n",
1702 			    ch->rslots & ~ch->toslots);
1703 	}
1704 }
1705 
1706 /* Must be called with channel locked. */
1707 static void
1708 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et)
1709 {
1710 	struct ahci_channel *ch = slot->ch;
1711 	union ccb *ccb = slot->ccb;
1712 	struct ahci_cmd_list *clp;
1713 	int lastto;
1714 	uint32_t sig;
1715 
1716 	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1717 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1718 	clp = (struct ahci_cmd_list *)
1719 	    (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1720 	/* Read result registers to the result struct
1721 	 * May be incorrect if several commands finished same time,
1722 	 * so read only when sure or have to.
1723 	 */
1724 	if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1725 		struct ata_res *res = &ccb->ataio.res;
1726 
1727 		if ((et == AHCI_ERR_TFE) ||
1728 		    (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) {
1729 			u_int8_t *fis = ch->dma.rfis + 0x40;
1730 
1731 			bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1732 			    BUS_DMASYNC_POSTREAD);
1733 			if (ch->fbs_enabled) {
1734 				fis += ccb->ccb_h.target_id * 256;
1735 				res->status = fis[2];
1736 				res->error = fis[3];
1737 			} else {
1738 				uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD);
1739 
1740 				res->status = tfd;
1741 				res->error = tfd >> 8;
1742 			}
1743 			res->lba_low = fis[4];
1744 			res->lba_mid = fis[5];
1745 			res->lba_high = fis[6];
1746 			res->device = fis[7];
1747 			res->lba_low_exp = fis[8];
1748 			res->lba_mid_exp = fis[9];
1749 			res->lba_high_exp = fis[10];
1750 			res->sector_count = fis[12];
1751 			res->sector_count_exp = fis[13];
1752 
1753 			/*
1754 			 * Some weird controllers do not return signature in
1755 			 * FIS receive area. Read it from PxSIG register.
1756 			 */
1757 			if ((ch->quirks & AHCI_Q_ALTSIG) &&
1758 			    (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
1759 			    (ccb->ataio.cmd.control & ATA_A_RESET) == 0) {
1760 				sig = ATA_INL(ch->r_mem,  AHCI_P_SIG);
1761 				res->lba_high = sig >> 24;
1762 				res->lba_mid = sig >> 16;
1763 				res->lba_low = sig >> 8;
1764 				res->sector_count = sig;
1765 			}
1766 		} else
1767 			bzero(res, sizeof(*res));
1768 		if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 &&
1769 		    (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
1770 		    (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
1771 			ccb->ataio.resid =
1772 			    ccb->ataio.dxfer_len - le32toh(clp->bytecount);
1773 		}
1774 	} else {
1775 		if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
1776 		    (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
1777 			ccb->csio.resid =
1778 			    ccb->csio.dxfer_len - le32toh(clp->bytecount);
1779 		}
1780 	}
1781 	if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1782 		bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1783 		    (ccb->ccb_h.flags & CAM_DIR_IN) ?
1784 		    BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1785 		bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map);
1786 	}
1787 	if (et != AHCI_ERR_NONE)
1788 		ch->eslots |= (1 << slot->slot);
1789 	/* In case of error, freeze device for proper recovery. */
1790 	if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) &&
1791 	    !(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
1792 		xpt_freeze_devq(ccb->ccb_h.path, 1);
1793 		ccb->ccb_h.status |= CAM_DEV_QFRZN;
1794 	}
1795 	/* Set proper result status. */
1796 	ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1797 	switch (et) {
1798 	case AHCI_ERR_NONE:
1799 		ccb->ccb_h.status |= CAM_REQ_CMP;
1800 		if (ccb->ccb_h.func_code == XPT_SCSI_IO)
1801 			ccb->csio.scsi_status = SCSI_STATUS_OK;
1802 		break;
1803 	case AHCI_ERR_INVALID:
1804 		ch->fatalerr = 1;
1805 		ccb->ccb_h.status |= CAM_REQ_INVALID;
1806 		break;
1807 	case AHCI_ERR_INNOCENT:
1808 		ccb->ccb_h.status |= CAM_REQUEUE_REQ;
1809 		break;
1810 	case AHCI_ERR_TFE:
1811 	case AHCI_ERR_NCQ:
1812 		if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
1813 			ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
1814 			ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
1815 		} else {
1816 			ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
1817 		}
1818 		break;
1819 	case AHCI_ERR_SATA:
1820 		ch->fatalerr = 1;
1821 		if (!ch->recoverycmd) {
1822 			xpt_freeze_simq(ch->sim, 1);
1823 			ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1824 			ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
1825 		}
1826 		ccb->ccb_h.status |= CAM_UNCOR_PARITY;
1827 		break;
1828 	case AHCI_ERR_TIMEOUT:
1829 		if (!ch->recoverycmd) {
1830 			xpt_freeze_simq(ch->sim, 1);
1831 			ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1832 			ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
1833 		}
1834 		ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
1835 		break;
1836 	default:
1837 		ch->fatalerr = 1;
1838 		ccb->ccb_h.status |= CAM_REQ_CMP_ERR;
1839 	}
1840 	/* Free slot. */
1841 	ch->oslots &= ~(1 << slot->slot);
1842 	ch->rslots &= ~(1 << slot->slot);
1843 	ch->aslots &= ~(1 << slot->slot);
1844 	slot->state = AHCI_SLOT_EMPTY;
1845 	slot->ccb = NULL;
1846 	/* Update channel stats. */
1847 	ch->numrslots--;
1848 	ch->numrslotspd[ccb->ccb_h.target_id]--;
1849 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1850 	    (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1851 		ch->numtslots--;
1852 		ch->numtslotspd[ccb->ccb_h.target_id]--;
1853 	}
1854 	/* Cancel timeout state if request completed normally. */
1855 	if (et != AHCI_ERR_TIMEOUT) {
1856 		lastto = (ch->toslots == (1 << slot->slot));
1857 		ch->toslots &= ~(1 << slot->slot);
1858 		if (lastto)
1859 			xpt_release_simq(ch->sim, TRUE);
1860 	}
1861 	/* If it was first request of reset sequence and there is no error,
1862 	 * proceed to second request. */
1863 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1864 	    (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
1865 	    (ccb->ataio.cmd.control & ATA_A_RESET) &&
1866 	    et == AHCI_ERR_NONE) {
1867 		ccb->ataio.cmd.control &= ~ATA_A_RESET;
1868 		ahci_begin_transaction(ch, ccb);
1869 		return;
1870 	}
1871 	/* If it was our READ LOG command - process it. */
1872 	if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) {
1873 		ahci_process_read_log(ch, ccb);
1874 	/* If it was our REQUEST SENSE command - process it. */
1875 	} else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) {
1876 		ahci_process_request_sense(ch, ccb);
1877 	/* If it was NCQ or ATAPI command error, put result on hold. */
1878 	} else if (et == AHCI_ERR_NCQ ||
1879 	    ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR &&
1880 	     (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) {
1881 		ch->hold[slot->slot] = ccb;
1882 		ch->numhslots++;
1883 	} else
1884 		ahci_done(ch, ccb);
1885 	/* If we have no other active commands, ... */
1886 	if (ch->rslots == 0) {
1887 		/* if there was fatal error - reset port. */
1888 		if (ch->toslots != 0 || ch->fatalerr) {
1889 			ahci_reset(ch);
1890 		} else {
1891 			/* if we have slots in error, we can reinit port. */
1892 			if (ch->eslots != 0) {
1893 				ahci_stop(ch);
1894 				ahci_clo(ch);
1895 				ahci_start(ch, 1);
1896 			}
1897 			/* if there commands on hold, we can do READ LOG. */
1898 			if (!ch->recoverycmd && ch->numhslots)
1899 				ahci_issue_recovery(ch);
1900 		}
1901 	/* If all the rest of commands are in timeout - give them chance. */
1902 	} else if ((ch->rslots & ~ch->toslots) == 0 &&
1903 	    et != AHCI_ERR_TIMEOUT)
1904 		ahci_rearm_timeout(ch);
1905 	/* Unfreeze frozen command. */
1906 	if (ch->frozen && !ahci_check_collision(ch, ch->frozen)) {
1907 		union ccb *fccb = ch->frozen;
1908 		ch->frozen = NULL;
1909 		ahci_begin_transaction(ch, fccb);
1910 		xpt_release_simq(ch->sim, TRUE);
1911 	}
1912 	/* Start PM timer. */
1913 	if (ch->numrslots == 0 && ch->pm_level > 3 &&
1914 	    (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) {
1915 		callout_schedule(&ch->pm_timer,
1916 		    (ch->pm_level == 4) ? hz / 1000 : hz / 8);
1917 	}
1918 }
1919 
1920 static void
1921 ahci_issue_recovery(struct ahci_channel *ch)
1922 {
1923 	union ccb *ccb;
1924 	struct ccb_ataio *ataio;
1925 	struct ccb_scsiio *csio;
1926 	int i;
1927 
1928 	/* Find some held command. */
1929 	for (i = 0; i < ch->numslots; i++) {
1930 		if (ch->hold[i])
1931 			break;
1932 	}
1933 	ccb = xpt_alloc_ccb_nowait();
1934 	if (ccb == NULL) {
1935 		device_printf(ch->dev, "Unable to allocate recovery command\n");
1936 completeall:
1937 		/* We can't do anything -- complete held commands. */
1938 		for (i = 0; i < ch->numslots; i++) {
1939 			if (ch->hold[i] == NULL)
1940 				continue;
1941 			ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
1942 			ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL;
1943 			ahci_done(ch, ch->hold[i]);
1944 			ch->hold[i] = NULL;
1945 			ch->numhslots--;
1946 		}
1947 		ahci_reset(ch);
1948 		return;
1949 	}
1950 	ccb->ccb_h = ch->hold[i]->ccb_h;	/* Reuse old header. */
1951 	if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1952 		/* READ LOG */
1953 		ccb->ccb_h.recovery_type = RECOVERY_READ_LOG;
1954 		ccb->ccb_h.func_code = XPT_ATA_IO;
1955 		ccb->ccb_h.flags = CAM_DIR_IN;
1956 		ccb->ccb_h.timeout = 1000;	/* 1s should be enough. */
1957 		ataio = &ccb->ataio;
1958 		ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT);
1959 		if (ataio->data_ptr == NULL) {
1960 			xpt_free_ccb(ccb);
1961 			device_printf(ch->dev,
1962 			    "Unable to allocate memory for READ LOG command\n");
1963 			goto completeall;
1964 		}
1965 		ataio->dxfer_len = 512;
1966 		bzero(&ataio->cmd, sizeof(ataio->cmd));
1967 		ataio->cmd.flags = CAM_ATAIO_48BIT;
1968 		ataio->cmd.command = 0x2F;	/* READ LOG EXT */
1969 		ataio->cmd.sector_count = 1;
1970 		ataio->cmd.sector_count_exp = 0;
1971 		ataio->cmd.lba_low = 0x10;
1972 		ataio->cmd.lba_mid = 0;
1973 		ataio->cmd.lba_mid_exp = 0;
1974 	} else {
1975 		/* REQUEST SENSE */
1976 		ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE;
1977 		ccb->ccb_h.recovery_slot = i;
1978 		ccb->ccb_h.func_code = XPT_SCSI_IO;
1979 		ccb->ccb_h.flags = CAM_DIR_IN;
1980 		ccb->ccb_h.status = 0;
1981 		ccb->ccb_h.timeout = 1000;	/* 1s should be enough. */
1982 		csio = &ccb->csio;
1983 		csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data;
1984 		csio->dxfer_len = ch->hold[i]->csio.sense_len;
1985 		csio->cdb_len = 6;
1986 		bzero(&csio->cdb_io, sizeof(csio->cdb_io));
1987 		csio->cdb_io.cdb_bytes[0] = 0x03;
1988 		csio->cdb_io.cdb_bytes[4] = csio->dxfer_len;
1989 	}
1990 	/* Freeze SIM while doing recovery. */
1991 	ch->recoverycmd = 1;
1992 	xpt_freeze_simq(ch->sim, 1);
1993 	ahci_begin_transaction(ch, ccb);
1994 }
1995 
1996 static void
1997 ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb)
1998 {
1999 	uint8_t *data;
2000 	struct ata_res *res;
2001 	int i;
2002 
2003 	ch->recoverycmd = 0;
2004 
2005 	data = ccb->ataio.data_ptr;
2006 	if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP &&
2007 	    (data[0] & 0x80) == 0) {
2008 		for (i = 0; i < ch->numslots; i++) {
2009 			if (!ch->hold[i])
2010 				continue;
2011 			if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2012 				continue;
2013 			if ((data[0] & 0x1F) == i) {
2014 				res = &ch->hold[i]->ataio.res;
2015 				res->status = data[2];
2016 				res->error = data[3];
2017 				res->lba_low = data[4];
2018 				res->lba_mid = data[5];
2019 				res->lba_high = data[6];
2020 				res->device = data[7];
2021 				res->lba_low_exp = data[8];
2022 				res->lba_mid_exp = data[9];
2023 				res->lba_high_exp = data[10];
2024 				res->sector_count = data[12];
2025 				res->sector_count_exp = data[13];
2026 			} else {
2027 				ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2028 				ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ;
2029 			}
2030 			ahci_done(ch, ch->hold[i]);
2031 			ch->hold[i] = NULL;
2032 			ch->numhslots--;
2033 		}
2034 	} else {
2035 		if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP)
2036 			device_printf(ch->dev, "Error while READ LOG EXT\n");
2037 		else if ((data[0] & 0x80) == 0) {
2038 			device_printf(ch->dev, "Non-queued command error in READ LOG EXT\n");
2039 		}
2040 		for (i = 0; i < ch->numslots; i++) {
2041 			if (!ch->hold[i])
2042 				continue;
2043 			if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2044 				continue;
2045 			ahci_done(ch, ch->hold[i]);
2046 			ch->hold[i] = NULL;
2047 			ch->numhslots--;
2048 		}
2049 	}
2050 	free(ccb->ataio.data_ptr, M_AHCI);
2051 	xpt_free_ccb(ccb);
2052 	xpt_release_simq(ch->sim, TRUE);
2053 }
2054 
2055 static void
2056 ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb)
2057 {
2058 	int i;
2059 
2060 	ch->recoverycmd = 0;
2061 
2062 	i = ccb->ccb_h.recovery_slot;
2063 	if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) {
2064 		ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID;
2065 	} else {
2066 		ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2067 		ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL;
2068 	}
2069 	ahci_done(ch, ch->hold[i]);
2070 	ch->hold[i] = NULL;
2071 	ch->numhslots--;
2072 	xpt_free_ccb(ccb);
2073 	xpt_release_simq(ch->sim, TRUE);
2074 }
2075 
2076 static void
2077 ahci_start(struct ahci_channel *ch, int fbs)
2078 {
2079 	u_int32_t cmd;
2080 
2081 	/* Clear SATA error register */
2082 	ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF);
2083 	/* Clear any interrupts pending on this channel */
2084 	ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF);
2085 	/* Configure FIS-based switching if supported. */
2086 	if (ch->chcaps & AHCI_P_CMD_FBSCP) {
2087 		ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0;
2088 		ATA_OUTL(ch->r_mem, AHCI_P_FBS,
2089 		    ch->fbs_enabled ? AHCI_P_FBS_EN : 0);
2090 	}
2091 	/* Start operations on this channel */
2092 	cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2093 	cmd &= ~AHCI_P_CMD_PMA;
2094 	ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST |
2095 	    (ch->pm_present ? AHCI_P_CMD_PMA : 0));
2096 }
2097 
2098 static void
2099 ahci_stop(struct ahci_channel *ch)
2100 {
2101 	u_int32_t cmd;
2102 	int timeout;
2103 
2104 	/* Kill all activity on this channel */
2105 	cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2106 	ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST);
2107 	/* Wait for activity stop. */
2108 	timeout = 0;
2109 	do {
2110 		DELAY(10);
2111 		if (timeout++ > 50000) {
2112 			device_printf(ch->dev, "stopping AHCI engine failed\n");
2113 			break;
2114 		}
2115 	} while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR);
2116 	ch->eslots = 0;
2117 }
2118 
2119 static void
2120 ahci_clo(struct ahci_channel *ch)
2121 {
2122 	u_int32_t cmd;
2123 	int timeout;
2124 
2125 	/* Issue Command List Override if supported */
2126 	if (ch->caps & AHCI_CAP_SCLO) {
2127 		cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2128 		cmd |= AHCI_P_CMD_CLO;
2129 		ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd);
2130 		timeout = 0;
2131 		do {
2132 			DELAY(10);
2133 			if (timeout++ > 50000) {
2134 			    device_printf(ch->dev, "executing CLO failed\n");
2135 			    break;
2136 			}
2137 		} while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO);
2138 	}
2139 }
2140 
2141 static void
2142 ahci_stop_fr(struct ahci_channel *ch)
2143 {
2144 	u_int32_t cmd;
2145 	int timeout;
2146 
2147 	/* Kill all FIS reception on this channel */
2148 	cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2149 	ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE);
2150 	/* Wait for FIS reception stop. */
2151 	timeout = 0;
2152 	do {
2153 		DELAY(10);
2154 		if (timeout++ > 50000) {
2155 			device_printf(ch->dev, "stopping AHCI FR engine failed\n");
2156 			break;
2157 		}
2158 	} while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR);
2159 }
2160 
2161 static void
2162 ahci_start_fr(struct ahci_channel *ch)
2163 {
2164 	u_int32_t cmd;
2165 
2166 	/* Start FIS reception on this channel */
2167 	cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2168 	ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE);
2169 }
2170 
2171 static int
2172 ahci_wait_ready(struct ahci_channel *ch, int t, int t0)
2173 {
2174 	int timeout = 0;
2175 	uint32_t val;
2176 
2177 	while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) &
2178 	    (ATA_S_BUSY | ATA_S_DRQ)) {
2179 		if (timeout > t) {
2180 			if (t != 0) {
2181 				device_printf(ch->dev,
2182 				    "AHCI reset: device not ready after %dms "
2183 				    "(tfd = %08x)\n",
2184 				    MAX(t, 0) + t0, val);
2185 			}
2186 			return (EBUSY);
2187 		}
2188 		DELAY(1000);
2189 		timeout++;
2190 	}
2191 	if (bootverbose)
2192 		device_printf(ch->dev, "AHCI reset: device ready after %dms\n",
2193 		    timeout + t0);
2194 	return (0);
2195 }
2196 
2197 static void
2198 ahci_reset_to(void *arg)
2199 {
2200 	struct ahci_channel *ch = arg;
2201 
2202 	if (ch->resetting == 0)
2203 		return;
2204 	ch->resetting--;
2205 	if (ahci_wait_ready(ch, ch->resetting == 0 ? -1 : 0,
2206 	    (310 - ch->resetting) * 100) == 0) {
2207 		ch->resetting = 0;
2208 		ahci_start(ch, 1);
2209 		xpt_release_simq(ch->sim, TRUE);
2210 		return;
2211 	}
2212 	if (ch->resetting == 0) {
2213 		ahci_clo(ch);
2214 		ahci_start(ch, 1);
2215 		xpt_release_simq(ch->sim, TRUE);
2216 		return;
2217 	}
2218 	callout_schedule(&ch->reset_timer, hz / 10);
2219 }
2220 
2221 static void
2222 ahci_reset(struct ahci_channel *ch)
2223 {
2224 	struct ahci_controller *ctlr = device_get_softc(device_get_parent(ch->dev));
2225 	int i;
2226 
2227 	xpt_freeze_simq(ch->sim, 1);
2228 	if (bootverbose)
2229 		device_printf(ch->dev, "AHCI reset...\n");
2230 	/* Forget about previous reset. */
2231 	if (ch->resetting) {
2232 		ch->resetting = 0;
2233 		callout_stop(&ch->reset_timer);
2234 		xpt_release_simq(ch->sim, TRUE);
2235 	}
2236 	/* Requeue freezed command. */
2237 	if (ch->frozen) {
2238 		union ccb *fccb = ch->frozen;
2239 		ch->frozen = NULL;
2240 		fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
2241 		if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
2242 			xpt_freeze_devq(fccb->ccb_h.path, 1);
2243 			fccb->ccb_h.status |= CAM_DEV_QFRZN;
2244 		}
2245 		ahci_done(ch, fccb);
2246 	}
2247 	/* Kill the engine and requeue all running commands. */
2248 	ahci_stop(ch);
2249 	for (i = 0; i < ch->numslots; i++) {
2250 		/* Do we have a running request on slot? */
2251 		if (ch->slot[i].state < AHCI_SLOT_RUNNING)
2252 			continue;
2253 		/* XXX; Commands in loading state. */
2254 		ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
2255 	}
2256 	for (i = 0; i < ch->numslots; i++) {
2257 		if (!ch->hold[i])
2258 			continue;
2259 		ahci_done(ch, ch->hold[i]);
2260 		ch->hold[i] = NULL;
2261 		ch->numhslots--;
2262 	}
2263 	if (ch->toslots != 0)
2264 		xpt_release_simq(ch->sim, TRUE);
2265 	ch->eslots = 0;
2266 	ch->toslots = 0;
2267 	ch->wrongccs = 0;
2268 	ch->fatalerr = 0;
2269 	/* Tell the XPT about the event */
2270 	xpt_async(AC_BUS_RESET, ch->path, NULL);
2271 	/* Disable port interrupts */
2272 	ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
2273 	/* Reset and reconnect PHY, */
2274 	if (!ahci_sata_phy_reset(ch)) {
2275 		if (bootverbose)
2276 			device_printf(ch->dev,
2277 			    "AHCI reset: device not found\n");
2278 		ch->devices = 0;
2279 		/* Enable wanted port interrupts */
2280 		ATA_OUTL(ch->r_mem, AHCI_P_IE,
2281 		    (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2282 		     AHCI_P_IX_PRC | AHCI_P_IX_PC));
2283 		xpt_release_simq(ch->sim, TRUE);
2284 		return;
2285 	}
2286 	if (bootverbose)
2287 		device_printf(ch->dev, "AHCI reset: device found\n");
2288 	/* Wait for clearing busy status. */
2289 	if (ahci_wait_ready(ch, dumping ? 31000 : 0, 0)) {
2290 		if (dumping)
2291 			ahci_clo(ch);
2292 		else
2293 			ch->resetting = 310;
2294 	}
2295 	ch->devices = 1;
2296 	/* Enable wanted port interrupts */
2297 	ATA_OUTL(ch->r_mem, AHCI_P_IE,
2298 	     (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2299 	      AHCI_P_IX_TFE | AHCI_P_IX_HBF |
2300 	      AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF |
2301 	      ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC |
2302 	      AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) |
2303 	      AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR)));
2304 	if (ch->resetting)
2305 		callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, ch);
2306 	else {
2307 		ahci_start(ch, 1);
2308 		xpt_release_simq(ch->sim, TRUE);
2309 	}
2310 }
2311 
2312 static int
2313 ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag)
2314 {
2315 	u_int8_t *fis = &ctp->cfis[0];
2316 
2317 	bzero(fis, 20);
2318 	fis[0] = 0x27;  		/* host to device */
2319 	fis[1] = (ccb->ccb_h.target_id & 0x0f);
2320 	if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2321 		fis[1] |= 0x80;
2322 		fis[2] = ATA_PACKET_CMD;
2323 		if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2324 		    ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA)
2325 			fis[3] = ATA_F_DMA;
2326 		else {
2327 			fis[5] = ccb->csio.dxfer_len;
2328 		        fis[6] = ccb->csio.dxfer_len >> 8;
2329 		}
2330 		fis[7] = ATA_D_LBA;
2331 		fis[15] = ATA_A_4BIT;
2332 		bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
2333 		    ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes,
2334 		    ctp->acmd, ccb->csio.cdb_len);
2335 		bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len);
2336 	} else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) {
2337 		fis[1] |= 0x80;
2338 		fis[2] = ccb->ataio.cmd.command;
2339 		fis[3] = ccb->ataio.cmd.features;
2340 		fis[4] = ccb->ataio.cmd.lba_low;
2341 		fis[5] = ccb->ataio.cmd.lba_mid;
2342 		fis[6] = ccb->ataio.cmd.lba_high;
2343 		fis[7] = ccb->ataio.cmd.device;
2344 		fis[8] = ccb->ataio.cmd.lba_low_exp;
2345 		fis[9] = ccb->ataio.cmd.lba_mid_exp;
2346 		fis[10] = ccb->ataio.cmd.lba_high_exp;
2347 		fis[11] = ccb->ataio.cmd.features_exp;
2348 		if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
2349 			fis[12] = tag << 3;
2350 			fis[13] = 0;
2351 		} else {
2352 			fis[12] = ccb->ataio.cmd.sector_count;
2353 			fis[13] = ccb->ataio.cmd.sector_count_exp;
2354 		}
2355 		fis[15] = ATA_A_4BIT;
2356 	} else {
2357 		fis[15] = ccb->ataio.cmd.control;
2358 	}
2359 	return (20);
2360 }
2361 
2362 static int
2363 ahci_sata_connect(struct ahci_channel *ch)
2364 {
2365 	u_int32_t status;
2366 	int timeout, found = 0;
2367 
2368 	/* Wait up to 100ms for "connect well" */
2369 	for (timeout = 0; timeout < 1000 ; timeout++) {
2370 		status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
2371 		if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
2372 			found = 1;
2373 		if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
2374 		    ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
2375 		    ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE))
2376 			break;
2377 		if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) {
2378 			if (bootverbose) {
2379 				device_printf(ch->dev, "SATA offline status=%08x\n",
2380 				    status);
2381 			}
2382 			return (0);
2383 		}
2384 		if (found == 0 && timeout >= 100)
2385 			break;
2386 		DELAY(100);
2387 	}
2388 	if (timeout >= 1000 || !found) {
2389 		if (bootverbose) {
2390 			device_printf(ch->dev,
2391 			    "SATA connect timeout time=%dus status=%08x\n",
2392 			    timeout * 100, status);
2393 		}
2394 		return (0);
2395 	}
2396 	if (bootverbose) {
2397 		device_printf(ch->dev, "SATA connect time=%dus status=%08x\n",
2398 		    timeout * 100, status);
2399 	}
2400 	/* Clear SATA error register */
2401 	ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff);
2402 	return (1);
2403 }
2404 
2405 static int
2406 ahci_sata_phy_reset(struct ahci_channel *ch)
2407 {
2408 	int sata_rev;
2409 	uint32_t val;
2410 
2411 	if (ch->listening) {
2412 		val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2413 		val |= AHCI_P_CMD_SUD;
2414 		ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2415 		ch->listening = 0;
2416 	}
2417 	sata_rev = ch->user[ch->pm_present ? 15 : 0].revision;
2418 	if (sata_rev == 1)
2419 		val = ATA_SC_SPD_SPEED_GEN1;
2420 	else if (sata_rev == 2)
2421 		val = ATA_SC_SPD_SPEED_GEN2;
2422 	else if (sata_rev == 3)
2423 		val = ATA_SC_SPD_SPEED_GEN3;
2424 	else
2425 		val = 0;
2426 	ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2427 	    ATA_SC_DET_RESET | val |
2428 	    ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER);
2429 	DELAY(1000);
2430 	ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2431 	    ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 :
2432 	    (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)));
2433 	if (!ahci_sata_connect(ch)) {
2434 		if (ch->caps & AHCI_CAP_SSS) {
2435 			val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2436 			val &= ~AHCI_P_CMD_SUD;
2437 			ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2438 			ch->listening = 1;
2439 		} else if (ch->pm_level > 0)
2440 			ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
2441 		return (0);
2442 	}
2443 	return (1);
2444 }
2445 
2446 static int
2447 ahci_check_ids(struct ahci_channel *ch, union ccb *ccb)
2448 {
2449 
2450 	if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) {
2451 		ccb->ccb_h.status = CAM_TID_INVALID;
2452 		ahci_done(ch, ccb);
2453 		return (-1);
2454 	}
2455 	if (ccb->ccb_h.target_lun != 0) {
2456 		ccb->ccb_h.status = CAM_LUN_INVALID;
2457 		ahci_done(ch, ccb);
2458 		return (-1);
2459 	}
2460 	return (0);
2461 }
2462 
2463 static void
2464 ahciaction(struct cam_sim *sim, union ccb *ccb)
2465 {
2466 	struct ahci_channel *ch;
2467 
2468 	CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n",
2469 	    ccb->ccb_h.func_code));
2470 
2471 	ch = (struct ahci_channel *)cam_sim_softc(sim);
2472 	switch (ccb->ccb_h.func_code) {
2473 	/* Common cases first */
2474 	case XPT_ATA_IO:	/* Execute the requested I/O operation */
2475 	case XPT_SCSI_IO:
2476 		if (ahci_check_ids(ch, ccb))
2477 			return;
2478 		if (ch->devices == 0 ||
2479 		    (ch->pm_present == 0 &&
2480 		     ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) {
2481 			ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2482 			break;
2483 		}
2484 		ccb->ccb_h.recovery_type = RECOVERY_NONE;
2485 		/* Check for command collision. */
2486 		if (ahci_check_collision(ch, ccb)) {
2487 			/* Freeze command. */
2488 			ch->frozen = ccb;
2489 			/* We have only one frozen slot, so freeze simq also. */
2490 			xpt_freeze_simq(ch->sim, 1);
2491 			return;
2492 		}
2493 		ahci_begin_transaction(ch, ccb);
2494 		return;
2495 	case XPT_EN_LUN:		/* Enable LUN as a target */
2496 	case XPT_TARGET_IO:		/* Execute target I/O request */
2497 	case XPT_ACCEPT_TARGET_IO:	/* Accept Host Target Mode CDB */
2498 	case XPT_CONT_TARGET_IO:	/* Continue Host Target I/O Connection*/
2499 	case XPT_ABORT:			/* Abort the specified CCB */
2500 		/* XXX Implement */
2501 		ccb->ccb_h.status = CAM_REQ_INVALID;
2502 		break;
2503 	case XPT_SET_TRAN_SETTINGS:
2504 	{
2505 		struct	ccb_trans_settings *cts = &ccb->cts;
2506 		struct	ahci_device *d;
2507 
2508 		if (ahci_check_ids(ch, ccb))
2509 			return;
2510 		if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2511 			d = &ch->curr[ccb->ccb_h.target_id];
2512 		else
2513 			d = &ch->user[ccb->ccb_h.target_id];
2514 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION)
2515 			d->revision = cts->xport_specific.sata.revision;
2516 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE)
2517 			d->mode = cts->xport_specific.sata.mode;
2518 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT)
2519 			d->bytecount = min(8192, cts->xport_specific.sata.bytecount);
2520 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS)
2521 			d->tags = min(ch->numslots, cts->xport_specific.sata.tags);
2522 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM)
2523 			ch->pm_present = cts->xport_specific.sata.pm_present;
2524 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI)
2525 			d->atapi = cts->xport_specific.sata.atapi;
2526 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
2527 			d->caps = cts->xport_specific.sata.caps;
2528 		ccb->ccb_h.status = CAM_REQ_CMP;
2529 		break;
2530 	}
2531 	case XPT_GET_TRAN_SETTINGS:
2532 	/* Get default/user set transfer settings for the target */
2533 	{
2534 		struct	ccb_trans_settings *cts = &ccb->cts;
2535 		struct  ahci_device *d;
2536 		uint32_t status;
2537 
2538 		if (ahci_check_ids(ch, ccb))
2539 			return;
2540 		if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2541 			d = &ch->curr[ccb->ccb_h.target_id];
2542 		else
2543 			d = &ch->user[ccb->ccb_h.target_id];
2544 		cts->protocol = PROTO_UNSPECIFIED;
2545 		cts->protocol_version = PROTO_VERSION_UNSPECIFIED;
2546 		cts->transport = XPORT_SATA;
2547 		cts->transport_version = XPORT_VERSION_UNSPECIFIED;
2548 		cts->proto_specific.valid = 0;
2549 		cts->xport_specific.sata.valid = 0;
2550 		if (cts->type == CTS_TYPE_CURRENT_SETTINGS &&
2551 		    (ccb->ccb_h.target_id == 15 ||
2552 		    (ccb->ccb_h.target_id == 0 && !ch->pm_present))) {
2553 			status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK;
2554 			if (status & 0x0f0) {
2555 				cts->xport_specific.sata.revision =
2556 				    (status & 0x0f0) >> 4;
2557 				cts->xport_specific.sata.valid |=
2558 				    CTS_SATA_VALID_REVISION;
2559 			}
2560 			cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D;
2561 			if (ch->pm_level) {
2562 				if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC))
2563 					cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ;
2564 				if (ch->caps2 & AHCI_CAP2_APST)
2565 					cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST;
2566 			}
2567 			if ((ch->caps & AHCI_CAP_SNCQ) &&
2568 			    (ch->quirks & AHCI_Q_NOAA) == 0)
2569 				cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA;
2570 			cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN;
2571 			cts->xport_specific.sata.caps &=
2572 			    ch->user[ccb->ccb_h.target_id].caps;
2573 			cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2574 		} else {
2575 			cts->xport_specific.sata.revision = d->revision;
2576 			cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION;
2577 			cts->xport_specific.sata.caps = d->caps;
2578 			cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2579 		}
2580 		cts->xport_specific.sata.mode = d->mode;
2581 		cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE;
2582 		cts->xport_specific.sata.bytecount = d->bytecount;
2583 		cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT;
2584 		cts->xport_specific.sata.pm_present = ch->pm_present;
2585 		cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM;
2586 		cts->xport_specific.sata.tags = d->tags;
2587 		cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS;
2588 		cts->xport_specific.sata.atapi = d->atapi;
2589 		cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI;
2590 		ccb->ccb_h.status = CAM_REQ_CMP;
2591 		break;
2592 	}
2593 	case XPT_RESET_BUS:		/* Reset the specified SCSI bus */
2594 	case XPT_RESET_DEV:	/* Bus Device Reset the specified SCSI device */
2595 		ahci_reset(ch);
2596 		ccb->ccb_h.status = CAM_REQ_CMP;
2597 		break;
2598 	case XPT_TERM_IO:		/* Terminate the I/O process */
2599 		/* XXX Implement */
2600 		ccb->ccb_h.status = CAM_REQ_INVALID;
2601 		break;
2602 	case XPT_PATH_INQ:		/* Path routing inquiry */
2603 	{
2604 		struct ccb_pathinq *cpi = &ccb->cpi;
2605 
2606 		cpi->version_num = 1; /* XXX??? */
2607 		cpi->hba_inquiry = PI_SDTR_ABLE;
2608 		if (ch->caps & AHCI_CAP_SNCQ)
2609 			cpi->hba_inquiry |= PI_TAG_ABLE;
2610 		if (ch->caps & AHCI_CAP_SPM)
2611 			cpi->hba_inquiry |= PI_SATAPM;
2612 		cpi->target_sprt = 0;
2613 		cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED;
2614 		cpi->hba_eng_cnt = 0;
2615 		if (ch->caps & AHCI_CAP_SPM)
2616 			cpi->max_target = 15;
2617 		else
2618 			cpi->max_target = 0;
2619 		cpi->max_lun = 0;
2620 		cpi->initiator_id = 0;
2621 		cpi->bus_id = cam_sim_bus(sim);
2622 		cpi->base_transfer_speed = 150000;
2623 		strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2624 		strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN);
2625 		strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2626 		cpi->unit_number = cam_sim_unit(sim);
2627 		cpi->transport = XPORT_SATA;
2628 		cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
2629 		cpi->protocol = PROTO_ATA;
2630 		cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
2631 		cpi->maxio = MAXPHYS;
2632 		/* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */
2633 		if (ch->quirks & AHCI_Q_MAXIO_64K)
2634 			cpi->maxio = min(cpi->maxio, 128 * 512);
2635 		cpi->hba_vendor = ch->vendorid;
2636 		cpi->hba_device = ch->deviceid;
2637 		cpi->hba_subvendor = ch->subvendorid;
2638 		cpi->hba_subdevice = ch->subdeviceid;
2639 		cpi->ccb_h.status = CAM_REQ_CMP;
2640 		break;
2641 	}
2642 	default:
2643 		ccb->ccb_h.status = CAM_REQ_INVALID;
2644 		break;
2645 	}
2646 	ahci_done(ch, ccb);
2647 }
2648 
2649 static void
2650 ahcipoll(struct cam_sim *sim)
2651 {
2652 	struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim);
2653 	uint32_t istatus;
2654 
2655 	/* Read interrupt statuses and process if any. */
2656 	istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
2657 	if (istatus != 0)
2658 		ahci_ch_intr_main(ch, istatus);
2659 	if (ch->resetting != 0 &&
2660 	    (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) {
2661 		ch->resetpolldiv = 1000;
2662 		ahci_reset_to(ch);
2663 	}
2664 }
2665 MODULE_VERSION(ahci, 1);
2666 MODULE_DEPEND(ahci, cam, 1, 1, 1);
2667