xref: /freebsd/sys/dev/agp/agpreg.h (revision c96ae1968a6ab7056427a739bce81bf07447c2d4)
1 /*-
2  * Copyright (c) 2000 Doug Rabson
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  *
26  *	$FreeBSD$
27  */
28 
29 #ifndef _PCI_AGPREG_H_
30 #define _PCI_AGPREG_H_
31 
32 /*
33  * Offsets for various AGP configuration registers.
34  */
35 #define AGP_APBASE		PCIR_BAR(0)
36 
37 /*
38  * Offsets from the AGP Capability pointer.
39  */
40 #define AGP_CAPID		0x0
41 #define AGP_STATUS		0x4
42 #define AGP_COMMAND		0x8
43 #define AGP_STATUS_AGP3		0x0008
44 #define AGP_STATUS_RQ_MASK	0xff000000
45 #define AGP_COMMAND_RQ_MASK	0xff000000
46 #define AGP_STATUS_ARQSZ_MASK	0xe000
47 #define AGP_COMMAND_ARQSZ_MASK	0xe000
48 #define AGP_STATUS_CAL_MASK	0x1c00
49 #define AGP_COMMAND_CAL_MASK	0x1c00
50 #define AGP_STATUS_ISOCH	0x10000
51 #define AGP_STATUS_SBA		0x0200
52 #define AGP_STATUS_ITA_COH	0x0100
53 #define AGP_STATUS_GART64	0x0080
54 #define AGP_STATUS_HTRANS	0x0040
55 #define AGP_STATUS_64BIT	0x0020
56 #define AGP_STATUS_FW		0x0010
57 #define AGP_COMMAND_RQ_MASK 	0xff000000
58 #define AGP_COMMAND_ARQSZ_MASK	0xe000
59 #define AGP_COMMAND_CAL_MASK	0x1c00
60 #define AGP_COMMAND_SBA		0x0200
61 #define AGP_COMMAND_AGP		0x0100
62 #define AGP_COMMAND_GART64	0x0080
63 #define AGP_COMMAND_64BIT	0x0020
64 #define AGP_COMMAND_FW		0x0010
65 
66 /*
67  * Config offsets for Intel AGP chipsets.
68  */
69 #define AGP_INTEL_NBXCFG	0x50
70 #define AGP_INTEL_ERRSTS	0x91
71 #define AGP_INTEL_AGPCTRL	0xb0
72 #define AGP_INTEL_APSIZE	0xb4
73 #define AGP_INTEL_ATTBASE	0xb8
74 
75 /*
76  * Config offsets for Intel i8xx/E7xxx AGP chipsets.
77  */
78 #define AGP_INTEL_MCHCFG	0x50
79 #define AGP_INTEL_I820_RDCR	0x51
80 #define AGP_INTEL_I845_AGPM	0x51
81 #define AGP_INTEL_I8XX_ERRSTS	0xc8
82 
83 /*
84  * Config offsets for VIA AGP 2.x chipsets.
85  */
86 #define AGP_VIA_GARTCTRL	0x80
87 #define AGP_VIA_APSIZE		0x84
88 #define AGP_VIA_ATTBASE		0x88
89 
90 /*
91  * Config offsets for VIA AGP 3.0 chipsets.
92  */
93 #define AGP3_VIA_GARTCTRL        0x90
94 #define AGP3_VIA_APSIZE          0x94
95 #define AGP3_VIA_ATTBASE         0x98
96 #define AGP_VIA_AGPSEL		 0xfd
97 
98 /*
99  * Config offsets for SiS AGP chipsets.
100  */
101 #define AGP_SIS_ATTBASE		0x90
102 #define AGP_SIS_WINCTRL		0x94
103 #define AGP_SIS_TLBCTRL		0x97
104 #define AGP_SIS_TLBFLUSH	0x98
105 
106 /*
107  * Config offsets for Ali AGP chipsets.
108  */
109 #define AGP_ALI_AGPCTRL		0xb8
110 #define AGP_ALI_ATTBASE		0xbc
111 #define AGP_ALI_TLBCTRL		0xc0
112 
113 /*
114  * Config offsets for the AMD 751 chipset.
115  */
116 #define AGP_AMD751_APBASE	0x10
117 #define AGP_AMD751_REGISTERS	0x14
118 #define AGP_AMD751_APCTRL	0xac
119 #define AGP_AMD751_MODECTRL	0xb0
120 #define AGP_AMD751_MODECTRL_SYNEN	0x80
121 #define AGP_AMD751_MODECTRL2	0xb2
122 #define AGP_AMD751_MODECTRL2_G1LM	0x01
123 #define AGP_AMD751_MODECTRL2_GPDCE	0x02
124 #define AGP_AMD751_MODECTRL2_NGSE	0x08
125 
126 /*
127  * Memory mapped register offsets for AMD 751 chipset.
128  */
129 #define AGP_AMD751_CAPS		0x00
130 #define AGP_AMD751_CAPS_EHI		0x0800
131 #define AGP_AMD751_CAPS_P2P		0x0400
132 #define AGP_AMD751_CAPS_MPC		0x0200
133 #define AGP_AMD751_CAPS_VBE		0x0100
134 #define AGP_AMD751_CAPS_REV		0x00ff
135 #define AGP_AMD751_STATUS	0x02
136 #define AGP_AMD751_STATUS_P2PS		0x0800
137 #define AGP_AMD751_STATUS_GCS		0x0400
138 #define AGP_AMD751_STATUS_MPS		0x0200
139 #define AGP_AMD751_STATUS_VBES		0x0100
140 #define AGP_AMD751_STATUS_P2PE		0x0008
141 #define AGP_AMD751_STATUS_GCE		0x0004
142 #define AGP_AMD751_STATUS_VBEE		0x0001
143 #define AGP_AMD751_ATTBASE	0x04
144 #define AGP_AMD751_TLBCTRL	0x0c
145 
146 /*
147  * Config registers for i810 device 0
148  */
149 #define AGP_I810_SMRAM		0x70
150 #define AGP_I810_SMRAM_GMS		0xc0
151 #define AGP_I810_SMRAM_GMS_DISABLED	0x00
152 #define AGP_I810_SMRAM_GMS_ENABLED_0	0x40
153 #define AGP_I810_SMRAM_GMS_ENABLED_512	0x80
154 #define AGP_I810_SMRAM_GMS_ENABLED_1024	0xc0
155 #define AGP_I810_MISCC		0x72
156 #define	AGP_I810_MISCC_WINSIZE		0x0001
157 #define AGP_I810_MISCC_WINSIZE_64	0x0000
158 #define AGP_I810_MISCC_WINSIZE_32	0x0001
159 #define AGP_I810_MISCC_PLCK		0x0008
160 #define AGP_I810_MISCC_PLCK_UNLOCKED	0x0000
161 #define AGP_I810_MISCC_PLCK_LOCKED	0x0008
162 #define AGP_I810_MISCC_WPTC		0x0030
163 #define AGP_I810_MISCC_WPTC_NOLIMIT	0x0000
164 #define AGP_I810_MISCC_WPTC_62		0x0010
165 #define AGP_I810_MISCC_WPTC_50		0x0020
166 #define	AGP_I810_MISCC_WPTC_37		0x0030
167 #define AGP_I810_MISCC_RPTC		0x00c0
168 #define AGP_I810_MISCC_RPTC_NOLIMIT	0x0000
169 #define AGP_I810_MISCC_RPTC_62		0x0040
170 #define AGP_I810_MISCC_RPTC_50		0x0080
171 #define AGP_I810_MISCC_RPTC_37		0x00c0
172 
173 /*
174  * Config registers for i810 device 1
175  */
176 #define AGP_I810_GMADR		0x10
177 #define AGP_I810_MMADR		0x14
178 
179 /*
180  * Memory mapped register offsets for i810 chipset.
181  */
182 #define AGP_I810_PGTBL_CTL	0x2020
183 #define AGP_I810_DRT		0x3000
184 #define AGP_I810_DRT_UNPOPULATED 0x00
185 #define AGP_I810_DRT_POPULATED	0x01
186 #define AGP_I810_GTT		0x10000
187 
188 /*
189  * Config registers for i830MG device 0
190  */
191 #define AGP_I830_GCC1			0x52
192 #define AGP_I830_GCC1_DEV2		0x08
193 #define AGP_I830_GCC1_DEV2_ENABLED	0x00
194 #define AGP_I830_GCC1_DEV2_DISABLED	0x08
195 #define AGP_I830_GCC1_GMS		0x70
196 #define AGP_I830_GCC1_GMS_STOLEN_512	0x20
197 #define AGP_I830_GCC1_GMS_STOLEN_1024	0x30
198 #define AGP_I830_GCC1_GMS_STOLEN_8192	0x40
199 #define AGP_I830_GCC1_GMASIZE		0x01
200 #define AGP_I830_GCC1_GMASIZE_64	0x01
201 #define AGP_I830_GCC1_GMASIZE_128	0x00
202 
203 /*
204  * Config registers for 852GM/855GM/865G device 0
205  */
206 #define AGP_I855_GCC1			0x52
207 #define AGP_I855_GCC1_DEV2		0x08
208 #define AGP_I855_GCC1_DEV2_ENABLED	0x00
209 #define AGP_I855_GCC1_DEV2_DISABLED	0x08
210 #define AGP_I855_GCC1_GMS		0x70
211 #define AGP_I855_GCC1_GMS_STOLEN_0M	0x00
212 #define AGP_I855_GCC1_GMS_STOLEN_1M	0x10
213 #define AGP_I855_GCC1_GMS_STOLEN_4M	0x20
214 #define AGP_I855_GCC1_GMS_STOLEN_8M	0x30
215 #define AGP_I855_GCC1_GMS_STOLEN_16M	0x40
216 #define AGP_I855_GCC1_GMS_STOLEN_32M	0x50
217 
218 /*
219  * 852GM/855GM variant identification
220  */
221 #define AGP_I85X_CAPID			0x44
222 #define AGP_I85X_VARIANT_MASK		0x7
223 #define AGP_I85X_VARIANT_SHIFT		5
224 #define AGP_I855_GME			0x0
225 #define AGP_I855_GM			0x4
226 #define AGP_I852_GME			0x2
227 #define AGP_I852_GM			0x5
228 
229 /*
230  * 915G registers
231  */
232 #define AGP_I915_GMADR			0x18
233 #define AGP_I915_MMADR			0x10
234 #define AGP_I915_GTTADR			0x1C
235 #define AGP_I915_GCC1_GMS_STOLEN_48M	0x60
236 #define AGP_I915_GCC1_GMS_STOLEN_64M	0x70
237 #define AGP_I915_DEVEN			0x54
238 #define AGP_I915_DEVEN_D2F0		0x08
239 #define AGP_I915_DEVEN_D2F0_ENABLED	0x08
240 #define AGP_I915_DEVEN_D2F0_DISABLED	0x00
241 #define AGP_I915_MSAC			0x62
242 #define AGP_I915_MSAC_GMASIZE		0x02
243 #define AGP_I915_MSAC_GMASIZE_128	0x02
244 #define AGP_I915_MSAC_GMASIZE_256	0x00
245 
246 /*
247  * NVIDIA nForce/nForce2 registers
248  */
249 #define	AGP_NVIDIA_0_APBASE		0x10
250 #define	AGP_NVIDIA_0_APSIZE		0x80
251 #define	AGP_NVIDIA_1_WBC		0xf0
252 #define	AGP_NVIDIA_2_GARTCTRL		0xd0
253 #define	AGP_NVIDIA_2_APBASE		0xd8
254 #define	AGP_NVIDIA_2_APLIMIT		0xdc
255 #define	AGP_NVIDIA_2_ATTBASE(i)		(0xe0 + (i) * 4)
256 #define	AGP_NVIDIA_3_APBASE		0x50
257 #define	AGP_NVIDIA_3_APLIMIT		0x54
258 
259 /*
260  * AMD64 GART registers
261  */
262 #define	AGP_AMD64_APCTRL		0x90
263 #define	AGP_AMD64_APBASE		0x94
264 #define	AGP_AMD64_ATTBASE		0x98
265 #define	AGP_AMD64_CACHECTRL		0x9c
266 #define	AGP_AMD64_APCTRL_GARTEN		0x00000001
267 #define	AGP_AMD64_APCTRL_SIZE_MASK	0x0000000e
268 #define	AGP_AMD64_APCTRL_DISGARTCPU	0x00000010
269 #define	AGP_AMD64_APCTRL_DISGARTIO	0x00000020
270 #define	AGP_AMD64_APCTRL_DISWLKPRB	0x00000040
271 #define	AGP_AMD64_APBASE_MASK		0x00007fff
272 #define	AGP_AMD64_ATTBASE_MASK		0xfffffff0
273 #define	AGP_AMD64_CACHECTRL_INVGART	0x00000001
274 #define	AGP_AMD64_CACHECTRL_PTEERR	0x00000002
275 
276 /*
277  * NVIDIA nForce3 registers
278  */
279 #define AGP_AMD64_NVIDIA_0_APBASE	0x10
280 #define AGP_AMD64_NVIDIA_1_APBASE1	0x50
281 #define AGP_AMD64_NVIDIA_1_APLIMIT1	0x54
282 #define AGP_AMD64_NVIDIA_1_APSIZE	0xa8
283 #define AGP_AMD64_NVIDIA_1_APBASE2	0xd8
284 #define AGP_AMD64_NVIDIA_1_APLIMIT2	0xdc
285 
286 /*
287  * ULi M1689 registers
288  */
289 #define AGP_AMD64_ULI_APBASE		0x10
290 #define AGP_AMD64_ULI_HTT_FEATURE	0x50
291 #define AGP_AMD64_ULI_ENU_SCR		0x54
292 
293 /*
294  * ATI IGP registers
295  */
296 #define ATI_GART_MMADDR		0x14
297 #define ATI_RS100_APSIZE	0xac
298 #define ATI_RS100_IG_AGPMODE	0xb0
299 #define ATI_RS300_APSIZE	0xf8
300 #define ATI_RS300_IG_AGPMODE	0xfc
301 #define ATI_GART_FEATURE_ID	0x00
302 #define ATI_GART_BASE		0x04
303 #define ATI_GART_CACHE_CNTRL	0x0c
304 
305 #endif /* !_PCI_AGPREG_H_ */
306