1 /*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _PCI_AGPREG_H_ 30 #define _PCI_AGPREG_H_ 31 32 /* 33 * Offsets for various AGP configuration registers. 34 */ 35 #define AGP_APBASE 0x10 36 #define AGP_CAPPTR 0x34 37 38 /* 39 * Offsets from the AGP Capability pointer. 40 */ 41 #define AGP_CAPID 0x0 42 #define AGP_CAPID_GET_MAJOR(x) (((x) & 0x00f00000U) >> 20) 43 #define AGP_CAPID_GET_MINOR(x) (((x) & 0x000f0000U) >> 16) 44 #define AGP_CAPID_GET_NEXT_PTR(x) (((x) & 0x0000ff00U) >> 8) 45 #define AGP_CAPID_GET_CAP_ID(x) (((x) & 0x000000ffU) >> 0) 46 47 #define AGP_STATUS 0x4 48 #define AGP_COMMAND 0x8 49 #define AGP_STATUS_AGP3 0x0008 50 #define AGP_STATUS_RQ_MASK 0xff000000 51 #define AGP_COMMAND_RQ_MASK 0xff000000 52 #define AGP_STATUS_ARQSZ_MASK 0xe000 53 #define AGP_COMMAND_ARQSZ_MASK 0xe000 54 #define AGP_STATUS_CAL_MASK 0x1c00 55 #define AGP_COMMAND_CAL_MASK 0x1c00 56 #define AGP_STATUS_ISOCH 0x10000 57 #define AGP_STATUS_SBA 0x0200 58 #define AGP_STATUS_ITA_COH 0x0100 59 #define AGP_STATUS_GART64 0x0080 60 #define AGP_STATUS_HTRANS 0x0040 61 #define AGP_STATUS_64BIT 0x0020 62 #define AGP_STATUS_FW 0x0010 63 #define AGP_COMMAND_RQ_MASK 0xff000000 64 #define AGP_COMMAND_ARQSZ_MASK 0xe000 65 #define AGP_COMMAND_CAL_MASK 0x1c00 66 #define AGP_COMMAND_SBA 0x0200 67 #define AGP_COMMAND_AGP 0x0100 68 #define AGP_COMMAND_GART64 0x0080 69 #define AGP_COMMAND_64BIT 0x0020 70 #define AGP_COMMAND_FW 0x0010 71 72 /* 73 * Config offsets for Intel AGP chipsets. 74 */ 75 #define AGP_INTEL_NBXCFG 0x50 76 #define AGP_INTEL_ERRSTS 0x91 77 #define AGP_INTEL_AGPCTRL 0xb0 78 #define AGP_INTEL_APSIZE 0xb4 79 #define AGP_INTEL_ATTBASE 0xb8 80 81 /* 82 * Config offsets for Intel i820/i840/i845/i850/i860/i865 AGP chipsets. 83 */ 84 #define AGP_INTEL_MCHCFG 0x50 85 #define AGP_INTEL_I820_RDCR 0x51 86 #define AGP_INTEL_I845_MCHCFG 0x51 87 #define AGP_INTEL_I8XX_ERRSTS 0xc8 88 89 /* 90 * Config offsets for VIA AGP 2.x chipsets. 91 */ 92 #define AGP_VIA_GARTCTRL 0x80 93 #define AGP_VIA_APSIZE 0x84 94 #define AGP_VIA_ATTBASE 0x88 95 96 /* 97 * Config offsets for VIA AGP 3.0 chipsets. 98 */ 99 #define AGP3_VIA_GARTCTRL 0x90 100 #define AGP3_VIA_APSIZE 0x94 101 #define AGP3_VIA_ATTBASE 0x98 102 103 /* 104 * Config offsets for SiS AGP chipsets. 105 */ 106 #define AGP_SIS_ATTBASE 0x90 107 #define AGP_SIS_WINCTRL 0x94 108 #define AGP_SIS_TLBCTRL 0x97 109 #define AGP_SIS_TLBFLUSH 0x98 110 111 /* 112 * Config offsets for Ali AGP chipsets. 113 */ 114 #define AGP_ALI_AGPCTRL 0xb8 115 #define AGP_ALI_ATTBASE 0xbc 116 #define AGP_ALI_TLBCTRL 0xc0 117 118 /* 119 * Config offsets for the AMD 751 chipset. 120 */ 121 #define AGP_AMD751_APBASE 0x10 122 #define AGP_AMD751_REGISTERS 0x14 123 #define AGP_AMD751_APCTRL 0xac 124 #define AGP_AMD751_MODECTRL 0xb0 125 #define AGP_AMD751_MODECTRL_SYNEN 0x80 126 #define AGP_AMD751_MODECTRL2 0xb2 127 #define AGP_AMD751_MODECTRL2_G1LM 0x01 128 #define AGP_AMD751_MODECTRL2_GPDCE 0x02 129 #define AGP_AMD751_MODECTRL2_NGSE 0x08 130 131 /* 132 * Memory mapped register offsets for AMD 751 chipset. 133 */ 134 #define AGP_AMD751_CAPS 0x00 135 #define AGP_AMD751_CAPS_EHI 0x0800 136 #define AGP_AMD751_CAPS_P2P 0x0400 137 #define AGP_AMD751_CAPS_MPC 0x0200 138 #define AGP_AMD751_CAPS_VBE 0x0100 139 #define AGP_AMD751_CAPS_REV 0x00ff 140 #define AGP_AMD751_STATUS 0x02 141 #define AGP_AMD751_STATUS_P2PS 0x0800 142 #define AGP_AMD751_STATUS_GCS 0x0400 143 #define AGP_AMD751_STATUS_MPS 0x0200 144 #define AGP_AMD751_STATUS_VBES 0x0100 145 #define AGP_AMD751_STATUS_P2PE 0x0008 146 #define AGP_AMD751_STATUS_GCE 0x0004 147 #define AGP_AMD751_STATUS_VBEE 0x0001 148 #define AGP_AMD751_ATTBASE 0x04 149 #define AGP_AMD751_TLBCTRL 0x0c 150 151 /* 152 * Config registers for i810 device 0 153 */ 154 #define AGP_I810_SMRAM 0x70 155 #define AGP_I810_SMRAM_GMS 0xc0 156 #define AGP_I810_SMRAM_GMS_DISABLED 0x00 157 #define AGP_I810_SMRAM_GMS_ENABLED_0 0x40 158 #define AGP_I810_SMRAM_GMS_ENABLED_512 0x80 159 #define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0 160 #define AGP_I810_MISCC 0x72 161 #define AGP_I810_MISCC_WINSIZE 0x0001 162 #define AGP_I810_MISCC_WINSIZE_64 0x0000 163 #define AGP_I810_MISCC_WINSIZE_32 0x0001 164 #define AGP_I810_MISCC_PLCK 0x0008 165 #define AGP_I810_MISCC_PLCK_UNLOCKED 0x0000 166 #define AGP_I810_MISCC_PLCK_LOCKED 0x0008 167 #define AGP_I810_MISCC_WPTC 0x0030 168 #define AGP_I810_MISCC_WPTC_NOLIMIT 0x0000 169 #define AGP_I810_MISCC_WPTC_62 0x0010 170 #define AGP_I810_MISCC_WPTC_50 0x0020 171 #define AGP_I810_MISCC_WPTC_37 0x0030 172 #define AGP_I810_MISCC_RPTC 0x00c0 173 #define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000 174 #define AGP_I810_MISCC_RPTC_62 0x0040 175 #define AGP_I810_MISCC_RPTC_50 0x0080 176 #define AGP_I810_MISCC_RPTC_37 0x00c0 177 178 /* 179 * Config registers for i810 device 1 180 */ 181 #define AGP_I810_GMADR 0x10 182 #define AGP_I810_MMADR 0x14 183 184 /* 185 * Memory mapped register offsets for i810 chipset. 186 */ 187 #define AGP_I810_PGTBL_CTL 0x2020 188 #define AGP_I810_DRT 0x3000 189 #define AGP_I810_DRT_UNPOPULATED 0x00 190 #define AGP_I810_DRT_POPULATED 0x01 191 #define AGP_I810_GTT 0x10000 192 193 /* 194 * Config registers for i830MG device 0 195 */ 196 #define AGP_I830_GCC1 0x52 197 #define AGP_I830_GCC1_DEV2 0x08 198 #define AGP_I830_GCC1_DEV2_ENABLED 0x00 199 #define AGP_I830_GCC1_DEV2_DISABLED 0x08 200 #define AGP_I830_GCC1_GMS 0x70 201 #define AGP_I830_GCC1_GMS_STOLEN_512 0x20 202 #define AGP_I830_GCC1_GMS_STOLEN_1024 0x30 203 #define AGP_I830_GCC1_GMS_STOLEN_8192 0x40 204 #define AGP_I830_GCC1_GMASIZE 0x01 205 #define AGP_I830_GCC1_GMASIZE_64 0x01 206 #define AGP_I830_GCC1_GMASIZE_128 0x00 207 208 /* 209 * Config registers for 852GM/855GM/865G device 0 210 */ 211 #define AGP_I855_GCC1 0x52 212 #define AGP_I855_GCC1_DEV2 0x08 213 #define AGP_I855_GCC1_DEV2_ENABLED 0x00 214 #define AGP_I855_GCC1_DEV2_DISABLED 0x08 215 #define AGP_I855_GCC1_GMS 0x70 216 #define AGP_I855_GCC1_GMS_STOLEN_0M 0x00 217 #define AGP_I855_GCC1_GMS_STOLEN_1M 0x10 218 #define AGP_I855_GCC1_GMS_STOLEN_4M 0x20 219 #define AGP_I855_GCC1_GMS_STOLEN_8M 0x30 220 #define AGP_I855_GCC1_GMS_STOLEN_16M 0x40 221 #define AGP_I855_GCC1_GMS_STOLEN_32M 0x50 222 223 /* 224 * 852GM/855GM variant identification 225 */ 226 #define AGP_I85X_CAPID 0x44 227 #define AGP_I85X_VARIANT_MASK 0x7 228 #define AGP_I85X_VARIANT_SHIFT 5 229 #define AGP_I855_GME 0x0 230 #define AGP_I855_GM 0x4 231 #define AGP_I852_GME 0x2 232 #define AGP_I852_GM 0x5 233 234 /* 235 * NVIDIA nForce/nForce2 registers 236 */ 237 #define AGP_NVIDIA_0_APBASE 0x10 238 #define AGP_NVIDIA_0_APSIZE 0x80 239 #define AGP_NVIDIA_1_WBC 0xf0 240 #define AGP_NVIDIA_2_GARTCTRL 0xd0 241 #define AGP_NVIDIA_2_APBASE 0xd8 242 #define AGP_NVIDIA_2_APLIMIT 0xdc 243 #define AGP_NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4) 244 #define AGP_NVIDIA_3_APBASE 0x50 245 #define AGP_NVIDIA_3_APLIMIT 0x54 246 247 #endif /* !_PCI_AGPREG_H_ */ 248