134345c08SMatthew N. Dodd /*- 234345c08SMatthew N. Dodd * Copyright (c) 2003 Matthew N. Dodd <winter@jurai.net> 334345c08SMatthew N. Dodd * All rights reserved. 434345c08SMatthew N. Dodd * 534345c08SMatthew N. Dodd * Redistribution and use in source and binary forms, with or without 634345c08SMatthew N. Dodd * modification, are permitted provided that the following conditions 734345c08SMatthew N. Dodd * are met: 834345c08SMatthew N. Dodd * 1. Redistributions of source code must retain the above copyright 934345c08SMatthew N. Dodd * notice, this list of conditions and the following disclaimer. 1034345c08SMatthew N. Dodd * 2. Redistributions in binary form must reproduce the above copyright 1134345c08SMatthew N. Dodd * notice, this list of conditions and the following disclaimer in the 1234345c08SMatthew N. Dodd * documentation and/or other materials provided with the distribution. 1334345c08SMatthew N. Dodd * 1434345c08SMatthew N. Dodd * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1534345c08SMatthew N. Dodd * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1634345c08SMatthew N. Dodd * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1734345c08SMatthew N. Dodd * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1834345c08SMatthew N. Dodd * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1934345c08SMatthew N. Dodd * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2034345c08SMatthew N. Dodd * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2134345c08SMatthew N. Dodd * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2234345c08SMatthew N. Dodd * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2334345c08SMatthew N. Dodd * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2434345c08SMatthew N. Dodd * SUCH DAMAGE. 2534345c08SMatthew N. Dodd */ 2634345c08SMatthew N. Dodd 27e0026a65SMaxime Henrion #include <sys/cdefs.h> 28e0026a65SMaxime Henrion __FBSDID("$FreeBSD$"); 29e0026a65SMaxime Henrion 3034345c08SMatthew N. Dodd /* 3134345c08SMatthew N. Dodd * Written using information gleaned from the 3234345c08SMatthew N. Dodd * NVIDIA nForce/nForce2 AGPGART Linux Kernel Patch. 3334345c08SMatthew N. Dodd */ 3434345c08SMatthew N. Dodd 3534345c08SMatthew N. Dodd #include "opt_bus.h" 3634345c08SMatthew N. Dodd 3734345c08SMatthew N. Dodd #include <sys/param.h> 3834345c08SMatthew N. Dodd #include <sys/systm.h> 3934345c08SMatthew N. Dodd #include <sys/malloc.h> 4034345c08SMatthew N. Dodd #include <sys/kernel.h> 4134345c08SMatthew N. Dodd #include <sys/bus.h> 4234345c08SMatthew N. Dodd #include <sys/lock.h> 4334345c08SMatthew N. Dodd 4434345c08SMatthew N. Dodd #if __FreeBSD_version < 500000 4534345c08SMatthew N. Dodd #include "opt_pci.h" 4634345c08SMatthew N. Dodd #endif 4734345c08SMatthew N. Dodd 4834345c08SMatthew N. Dodd #if __FreeBSD_version > 500000 4934345c08SMatthew N. Dodd #include <sys/mutex.h> 5034345c08SMatthew N. Dodd #include <sys/proc.h> 5134345c08SMatthew N. Dodd #endif 5234345c08SMatthew N. Dodd 536b312d76SMatthew N. Dodd #include <dev/pci/pcivar.h> 546b312d76SMatthew N. Dodd #include <dev/pci/pcireg.h> 5534345c08SMatthew N. Dodd #include <pci/agppriv.h> 5634345c08SMatthew N. Dodd #include <pci/agpreg.h> 5734345c08SMatthew N. Dodd 5834345c08SMatthew N. Dodd #include <vm/vm.h> 5934345c08SMatthew N. Dodd #include <vm/vm_object.h> 6034345c08SMatthew N. Dodd #include <vm/pmap.h> 6134345c08SMatthew N. Dodd 6234345c08SMatthew N. Dodd #include <machine/bus.h> 6334345c08SMatthew N. Dodd #include <machine/resource.h> 6434345c08SMatthew N. Dodd #include <sys/rman.h> 6534345c08SMatthew N. Dodd 6634345c08SMatthew N. Dodd #define NVIDIA_VENDORID 0x10de 6734345c08SMatthew N. Dodd #define NVIDIA_DEVICEID_NFORCE 0x01a4 6834345c08SMatthew N. Dodd #define NVIDIA_DEVICEID_NFORCE2 0x01e0 6934345c08SMatthew N. Dodd 7034345c08SMatthew N. Dodd struct agp_nvidia_softc { 7134345c08SMatthew N. Dodd struct agp_softc agp; 7234345c08SMatthew N. Dodd u_int32_t initial_aperture; /* aperture size at startup */ 7334345c08SMatthew N. Dodd struct agp_gatt * gatt; 7434345c08SMatthew N. Dodd 7534345c08SMatthew N. Dodd device_t dev; /* AGP Controller */ 7634345c08SMatthew N. Dodd device_t mc1_dev; /* Memory Controller */ 7734345c08SMatthew N. Dodd device_t mc2_dev; /* Memory Controller */ 7834345c08SMatthew N. Dodd device_t bdev; /* Bridge */ 7934345c08SMatthew N. Dodd 8034345c08SMatthew N. Dodd u_int32_t wbc_mask; 8134345c08SMatthew N. Dodd int num_dirs; 8234345c08SMatthew N. Dodd int num_active_entries; 8334345c08SMatthew N. Dodd off_t pg_offset; 8434345c08SMatthew N. Dodd }; 8534345c08SMatthew N. Dodd 8634345c08SMatthew N. Dodd static const char * agp_nvidia_match (device_t dev); 8734345c08SMatthew N. Dodd static int agp_nvidia_probe (device_t); 8834345c08SMatthew N. Dodd static int agp_nvidia_attach (device_t); 8934345c08SMatthew N. Dodd static int agp_nvidia_detach (device_t); 9034345c08SMatthew N. Dodd static u_int32_t agp_nvidia_get_aperture (device_t); 9134345c08SMatthew N. Dodd static int agp_nvidia_set_aperture (device_t, u_int32_t); 9234345c08SMatthew N. Dodd static int agp_nvidia_bind_page (device_t, int, vm_offset_t); 9334345c08SMatthew N. Dodd static int agp_nvidia_unbind_page (device_t, int); 9434345c08SMatthew N. Dodd 9534345c08SMatthew N. Dodd static int nvidia_init_iorr (u_int32_t, u_int32_t); 9634345c08SMatthew N. Dodd 9734345c08SMatthew N. Dodd static const char * 9834345c08SMatthew N. Dodd agp_nvidia_match (device_t dev) 9934345c08SMatthew N. Dodd { 10034345c08SMatthew N. Dodd if (pci_get_class(dev) != PCIC_BRIDGE || 10134345c08SMatthew N. Dodd pci_get_subclass(dev) != PCIS_BRIDGE_HOST || 10234345c08SMatthew N. Dodd pci_get_vendor(dev) != NVIDIA_VENDORID) 10334345c08SMatthew N. Dodd return (NULL); 10434345c08SMatthew N. Dodd 10534345c08SMatthew N. Dodd switch (pci_get_device(dev)) { 10634345c08SMatthew N. Dodd case NVIDIA_DEVICEID_NFORCE: 10734345c08SMatthew N. Dodd return ("NVIDIA nForce AGP Controller"); 10834345c08SMatthew N. Dodd case NVIDIA_DEVICEID_NFORCE2: 10934345c08SMatthew N. Dodd return ("NVIDIA nForce2 AGP Controller"); 11034345c08SMatthew N. Dodd } 11134345c08SMatthew N. Dodd return ("NVIDIA Generic AGP Controller"); 11234345c08SMatthew N. Dodd } 11334345c08SMatthew N. Dodd 11434345c08SMatthew N. Dodd static int 11534345c08SMatthew N. Dodd agp_nvidia_probe (device_t dev) 11634345c08SMatthew N. Dodd { 11734345c08SMatthew N. Dodd const char *desc; 11834345c08SMatthew N. Dodd 11925128fccSNate Lawson if (resource_disabled("agp", device_get_unit(dev))) 12025128fccSNate Lawson return (ENXIO); 12134345c08SMatthew N. Dodd desc = agp_nvidia_match(dev); 12234345c08SMatthew N. Dodd if (desc) { 12334345c08SMatthew N. Dodd device_verbose(dev); 12434345c08SMatthew N. Dodd device_set_desc(dev, desc); 12534345c08SMatthew N. Dodd return (0); 12634345c08SMatthew N. Dodd } 12734345c08SMatthew N. Dodd return (ENXIO); 12834345c08SMatthew N. Dodd } 12934345c08SMatthew N. Dodd 13034345c08SMatthew N. Dodd static int 13134345c08SMatthew N. Dodd agp_nvidia_attach (device_t dev) 13234345c08SMatthew N. Dodd { 13334345c08SMatthew N. Dodd struct agp_nvidia_softc *sc = device_get_softc(dev); 13434345c08SMatthew N. Dodd struct agp_gatt *gatt; 13534345c08SMatthew N. Dodd u_int32_t apbase; 13634345c08SMatthew N. Dodd u_int32_t aplimit; 13734345c08SMatthew N. Dodd u_int32_t temp; 13834345c08SMatthew N. Dodd int size; 13934345c08SMatthew N. Dodd int i; 14034345c08SMatthew N. Dodd int error; 14134345c08SMatthew N. Dodd 14234345c08SMatthew N. Dodd switch (pci_get_device(dev)) { 14334345c08SMatthew N. Dodd case NVIDIA_DEVICEID_NFORCE: 14434345c08SMatthew N. Dodd sc->wbc_mask = 0x00010000; 14534345c08SMatthew N. Dodd break; 14634345c08SMatthew N. Dodd case NVIDIA_DEVICEID_NFORCE2: 14734345c08SMatthew N. Dodd sc->wbc_mask = 0x80000000; 14834345c08SMatthew N. Dodd break; 14934345c08SMatthew N. Dodd default: 15034345c08SMatthew N. Dodd sc->wbc_mask = 0; 15134345c08SMatthew N. Dodd break; 15234345c08SMatthew N. Dodd } 15334345c08SMatthew N. Dodd 15434345c08SMatthew N. Dodd /* AGP Controller */ 15534345c08SMatthew N. Dodd sc->dev = dev; 15634345c08SMatthew N. Dodd 15734345c08SMatthew N. Dodd /* Memory Controller 1 */ 15834345c08SMatthew N. Dodd sc->mc1_dev = pci_find_bsf(pci_get_bus(dev), 0, 1); 15934345c08SMatthew N. Dodd if (sc->mc1_dev == NULL) { 16034345c08SMatthew N. Dodd device_printf(dev, 16134345c08SMatthew N. Dodd "Unable to find NVIDIA Memory Controller 1.\n"); 16234345c08SMatthew N. Dodd return (ENODEV); 16334345c08SMatthew N. Dodd } 16434345c08SMatthew N. Dodd 16534345c08SMatthew N. Dodd /* Memory Controller 2 */ 16634345c08SMatthew N. Dodd sc->mc2_dev = pci_find_bsf(pci_get_bus(dev), 0, 2); 16734345c08SMatthew N. Dodd if (sc->mc2_dev == NULL) { 16834345c08SMatthew N. Dodd device_printf(dev, 16934345c08SMatthew N. Dodd "Unable to find NVIDIA Memory Controller 2.\n"); 17034345c08SMatthew N. Dodd return (ENODEV); 17134345c08SMatthew N. Dodd } 17234345c08SMatthew N. Dodd 17334345c08SMatthew N. Dodd /* AGP Host to PCI Bridge */ 17434345c08SMatthew N. Dodd sc->bdev = pci_find_bsf(pci_get_bus(dev), 30, 0); 17534345c08SMatthew N. Dodd if (sc->bdev == NULL) { 17634345c08SMatthew N. Dodd device_printf(dev, 17734345c08SMatthew N. Dodd "Unable to find NVIDIA AGP Host to PCI Bridge.\n"); 17834345c08SMatthew N. Dodd return (ENODEV); 17934345c08SMatthew N. Dodd } 18034345c08SMatthew N. Dodd 18134345c08SMatthew N. Dodd error = agp_generic_attach(dev); 18234345c08SMatthew N. Dodd if (error) 18334345c08SMatthew N. Dodd return (error); 18434345c08SMatthew N. Dodd 18534345c08SMatthew N. Dodd sc->initial_aperture = AGP_GET_APERTURE(dev); 18634345c08SMatthew N. Dodd 18734345c08SMatthew N. Dodd for (;;) { 18834345c08SMatthew N. Dodd gatt = agp_alloc_gatt(dev); 18934345c08SMatthew N. Dodd if (gatt) 19034345c08SMatthew N. Dodd break; 19134345c08SMatthew N. Dodd /* 19234345c08SMatthew N. Dodd * Probably contigmalloc failure. Try reducing the 19334345c08SMatthew N. Dodd * aperture so that the gatt size reduces. 19434345c08SMatthew N. Dodd */ 19534345c08SMatthew N. Dodd if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) 19634345c08SMatthew N. Dodd goto fail; 19734345c08SMatthew N. Dodd } 19834345c08SMatthew N. Dodd sc->gatt = gatt; 19934345c08SMatthew N. Dodd 20034345c08SMatthew N. Dodd apbase = rman_get_start(sc->agp.as_aperture); 20134345c08SMatthew N. Dodd aplimit = apbase + AGP_GET_APERTURE(dev) - 1; 20234345c08SMatthew N. Dodd pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APBASE, apbase, 4); 20334345c08SMatthew N. Dodd pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APLIMIT, aplimit, 4); 20434345c08SMatthew N. Dodd pci_write_config(sc->bdev, AGP_NVIDIA_3_APBASE, apbase, 4); 20534345c08SMatthew N. Dodd pci_write_config(sc->bdev, AGP_NVIDIA_3_APLIMIT, aplimit, 4); 20634345c08SMatthew N. Dodd 20734345c08SMatthew N. Dodd error = nvidia_init_iorr(apbase, AGP_GET_APERTURE(dev)); 20834345c08SMatthew N. Dodd if (error) { 20934345c08SMatthew N. Dodd device_printf(dev, "Failed to setup IORRs\n"); 21034345c08SMatthew N. Dodd goto fail; 21134345c08SMatthew N. Dodd } 21234345c08SMatthew N. Dodd 21334345c08SMatthew N. Dodd /* directory size is 64k */ 21434345c08SMatthew N. Dodd size = AGP_GET_APERTURE(dev) / 1024 / 1024; 21534345c08SMatthew N. Dodd sc->num_dirs = size / 64; 21634345c08SMatthew N. Dodd sc->num_active_entries = (size == 32) ? 16384 : ((size * 1024) / 4); 21734345c08SMatthew N. Dodd sc->pg_offset = 0; 21834345c08SMatthew N. Dodd if (sc->num_dirs == 0) { 21934345c08SMatthew N. Dodd sc->num_dirs = 1; 22034345c08SMatthew N. Dodd sc->num_active_entries /= (64 / size); 22134345c08SMatthew N. Dodd sc->pg_offset = (apbase & (64 * 1024 * 1024 - 1) & 22234345c08SMatthew N. Dodd ~(AGP_GET_APERTURE(dev) - 1)) / PAGE_SIZE; 22334345c08SMatthew N. Dodd } 22434345c08SMatthew N. Dodd 22534345c08SMatthew N. Dodd /* (G)ATT Base Address */ 22634345c08SMatthew N. Dodd for (i = 0; i < 8; i++) { 22734345c08SMatthew N. Dodd pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_ATTBASE(i), 22834345c08SMatthew N. Dodd (sc->gatt->ag_physical + 22934345c08SMatthew N. Dodd (i % sc->num_dirs) * 64 * 1024), 23034345c08SMatthew N. Dodd 4); 23134345c08SMatthew N. Dodd } 23234345c08SMatthew N. Dodd 23334345c08SMatthew N. Dodd /* GTLB Control */ 23434345c08SMatthew N. Dodd temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4); 23534345c08SMatthew N. Dodd pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp | 0x11, 4); 23634345c08SMatthew N. Dodd 23734345c08SMatthew N. Dodd /* GART Control */ 23834345c08SMatthew N. Dodd temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4); 23934345c08SMatthew N. Dodd pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp | 0x100, 4); 24034345c08SMatthew N. Dodd 24134345c08SMatthew N. Dodd return (0); 24234345c08SMatthew N. Dodd fail: 24334345c08SMatthew N. Dodd agp_generic_detach(dev); 24434345c08SMatthew N. Dodd return (ENOMEM); 24534345c08SMatthew N. Dodd } 24634345c08SMatthew N. Dodd 24734345c08SMatthew N. Dodd static int 24834345c08SMatthew N. Dodd agp_nvidia_detach (device_t dev) 24934345c08SMatthew N. Dodd { 25034345c08SMatthew N. Dodd struct agp_nvidia_softc *sc = device_get_softc(dev); 25134345c08SMatthew N. Dodd int error; 25234345c08SMatthew N. Dodd u_int32_t temp; 25334345c08SMatthew N. Dodd 25434345c08SMatthew N. Dodd error = agp_generic_detach(dev); 25534345c08SMatthew N. Dodd if (error) 25634345c08SMatthew N. Dodd return (error); 25734345c08SMatthew N. Dodd 25834345c08SMatthew N. Dodd /* GART Control */ 25934345c08SMatthew N. Dodd temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4); 26034345c08SMatthew N. Dodd pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp & ~(0x100), 4); 26134345c08SMatthew N. Dodd 26234345c08SMatthew N. Dodd /* GTLB Control */ 26334345c08SMatthew N. Dodd temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4); 26434345c08SMatthew N. Dodd pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp & ~(0x11), 4); 26534345c08SMatthew N. Dodd 26634345c08SMatthew N. Dodd /* Put the aperture back the way it started. */ 26734345c08SMatthew N. Dodd AGP_SET_APERTURE(dev, sc->initial_aperture); 26834345c08SMatthew N. Dodd 26934345c08SMatthew N. Dodd /* restore iorr for previous aperture size */ 27034345c08SMatthew N. Dodd nvidia_init_iorr(rman_get_start(sc->agp.as_aperture), 27134345c08SMatthew N. Dodd sc->initial_aperture); 27234345c08SMatthew N. Dodd 27334345c08SMatthew N. Dodd agp_free_gatt(sc->gatt); 27434345c08SMatthew N. Dodd 27534345c08SMatthew N. Dodd return (0); 27634345c08SMatthew N. Dodd } 27734345c08SMatthew N. Dodd 27834345c08SMatthew N. Dodd static u_int32_t 27934345c08SMatthew N. Dodd agp_nvidia_get_aperture(device_t dev) 28034345c08SMatthew N. Dodd { 28134345c08SMatthew N. Dodd u_int8_t key; 28234345c08SMatthew N. Dodd 28334345c08SMatthew N. Dodd key = ffs(pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1) & 0x0f); 28434345c08SMatthew N. Dodd return (1 << (24 + (key ? key : 5))); 28534345c08SMatthew N. Dodd } 28634345c08SMatthew N. Dodd 28734345c08SMatthew N. Dodd static int 28834345c08SMatthew N. Dodd agp_nvidia_set_aperture(device_t dev, u_int32_t aperture) 28934345c08SMatthew N. Dodd { 29034345c08SMatthew N. Dodd u_int8_t val; 29134345c08SMatthew N. Dodd u_int8_t key; 29234345c08SMatthew N. Dodd 29334345c08SMatthew N. Dodd switch (aperture) { 29434345c08SMatthew N. Dodd case (512 * 1024 * 1024): key = 0; break; 29534345c08SMatthew N. Dodd case (256 * 1024 * 1024): key = 8; break; 29634345c08SMatthew N. Dodd case (128 * 1024 * 1024): key = 12; break; 29734345c08SMatthew N. Dodd case (64 * 1024 * 1024): key = 14; break; 29834345c08SMatthew N. Dodd case (32 * 1024 * 1024): key = 15; break; 29934345c08SMatthew N. Dodd default: 30034345c08SMatthew N. Dodd device_printf(dev, "Invalid aperture size (%dMb)\n", 30134345c08SMatthew N. Dodd aperture / 1024 / 1024); 30234345c08SMatthew N. Dodd return (EINVAL); 30334345c08SMatthew N. Dodd } 30434345c08SMatthew N. Dodd val = pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1); 30534345c08SMatthew N. Dodd pci_write_config(dev, AGP_NVIDIA_0_APSIZE, ((val & ~0x0f) | key), 1); 30634345c08SMatthew N. Dodd 30734345c08SMatthew N. Dodd return (0); 30834345c08SMatthew N. Dodd } 30934345c08SMatthew N. Dodd 31034345c08SMatthew N. Dodd static int 31134345c08SMatthew N. Dodd agp_nvidia_bind_page(device_t dev, int offset, vm_offset_t physical) 31234345c08SMatthew N. Dodd { 31334345c08SMatthew N. Dodd struct agp_nvidia_softc *sc = device_get_softc(dev); 31434345c08SMatthew N. Dodd u_int32_t index; 31534345c08SMatthew N. Dodd 31634345c08SMatthew N. Dodd if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 31734345c08SMatthew N. Dodd return (EINVAL); 31834345c08SMatthew N. Dodd 31934345c08SMatthew N. Dodd index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT; 32034345c08SMatthew N. Dodd sc->gatt->ag_virtual[index] = physical; 32134345c08SMatthew N. Dodd 32234345c08SMatthew N. Dodd return (0); 32334345c08SMatthew N. Dodd } 32434345c08SMatthew N. Dodd 32534345c08SMatthew N. Dodd static int 32634345c08SMatthew N. Dodd agp_nvidia_unbind_page(device_t dev, int offset) 32734345c08SMatthew N. Dodd { 32834345c08SMatthew N. Dodd struct agp_nvidia_softc *sc = device_get_softc(dev); 32934345c08SMatthew N. Dodd u_int32_t index; 33034345c08SMatthew N. Dodd 33134345c08SMatthew N. Dodd if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 33234345c08SMatthew N. Dodd return (EINVAL); 33334345c08SMatthew N. Dodd 33434345c08SMatthew N. Dodd index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT; 33534345c08SMatthew N. Dodd sc->gatt->ag_virtual[index] = 0; 33634345c08SMatthew N. Dodd 33734345c08SMatthew N. Dodd return (0); 33834345c08SMatthew N. Dodd } 33934345c08SMatthew N. Dodd 34034345c08SMatthew N. Dodd static int 34134345c08SMatthew N. Dodd agp_nvidia_flush_tlb (device_t dev, int offset) 34234345c08SMatthew N. Dodd { 34334345c08SMatthew N. Dodd struct agp_nvidia_softc *sc; 34434345c08SMatthew N. Dodd u_int32_t wbc_reg, temp; 34534345c08SMatthew N. Dodd int i; 34634345c08SMatthew N. Dodd 34734345c08SMatthew N. Dodd sc = (struct agp_nvidia_softc *)device_get_softc(dev); 34834345c08SMatthew N. Dodd 34934345c08SMatthew N. Dodd if (sc->wbc_mask) { 35034345c08SMatthew N. Dodd wbc_reg = pci_read_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, 4); 35134345c08SMatthew N. Dodd wbc_reg |= sc->wbc_mask; 35234345c08SMatthew N. Dodd pci_write_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, wbc_reg, 4); 35334345c08SMatthew N. Dodd 35434345c08SMatthew N. Dodd /* Wait no more than 3 seconds. */ 35534345c08SMatthew N. Dodd for (i = 0; i < 3000; i++) { 35634345c08SMatthew N. Dodd wbc_reg = pci_read_config(sc->mc1_dev, 35734345c08SMatthew N. Dodd AGP_NVIDIA_1_WBC, 4); 35834345c08SMatthew N. Dodd if ((sc->wbc_mask & wbc_reg) == 0) 35934345c08SMatthew N. Dodd break; 36034345c08SMatthew N. Dodd else 36134345c08SMatthew N. Dodd DELAY(1000); 36234345c08SMatthew N. Dodd } 36334345c08SMatthew N. Dodd if (i == 3000) 36434345c08SMatthew N. Dodd device_printf(dev, 36534345c08SMatthew N. Dodd "TLB flush took more than 3 seconds.\n"); 36634345c08SMatthew N. Dodd } 36734345c08SMatthew N. Dodd 36834345c08SMatthew N. Dodd /* Flush TLB entries. */ 36934345c08SMatthew N. Dodd for(i = 0; i < 32 + 1; i++) 37034345c08SMatthew N. Dodd temp = sc->gatt->ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)]; 37134345c08SMatthew N. Dodd for(i = 0; i < 32 + 1; i++) 37234345c08SMatthew N. Dodd temp = sc->gatt->ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)]; 37334345c08SMatthew N. Dodd 37434345c08SMatthew N. Dodd return (0); 37534345c08SMatthew N. Dodd } 37634345c08SMatthew N. Dodd 37734345c08SMatthew N. Dodd #define SYSCFG 0xC0010010 37834345c08SMatthew N. Dodd #define IORR_BASE0 0xC0010016 37934345c08SMatthew N. Dodd #define IORR_MASK0 0xC0010017 38034345c08SMatthew N. Dodd #define AMD_K7_NUM_IORR 2 38134345c08SMatthew N. Dodd 38234345c08SMatthew N. Dodd static int 38334345c08SMatthew N. Dodd nvidia_init_iorr(u_int32_t addr, u_int32_t size) 38434345c08SMatthew N. Dodd { 38534345c08SMatthew N. Dodd quad_t base, mask, sys; 38634345c08SMatthew N. Dodd u_int32_t iorr_addr, free_iorr_addr; 38734345c08SMatthew N. Dodd 38834345c08SMatthew N. Dodd /* Find the iorr that is already used for the addr */ 38934345c08SMatthew N. Dodd /* If not found, determine the uppermost available iorr */ 39034345c08SMatthew N. Dodd free_iorr_addr = AMD_K7_NUM_IORR; 39134345c08SMatthew N. Dodd for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) { 39234345c08SMatthew N. Dodd base = rdmsr(IORR_BASE0 + 2 * iorr_addr); 39334345c08SMatthew N. Dodd mask = rdmsr(IORR_MASK0 + 2 * iorr_addr); 39434345c08SMatthew N. Dodd 39534345c08SMatthew N. Dodd if ((base & 0xfffff000ULL) == (addr & 0xfffff000)) 39634345c08SMatthew N. Dodd break; 39734345c08SMatthew N. Dodd 39834345c08SMatthew N. Dodd if ((mask & 0x00000800ULL) == 0) 39934345c08SMatthew N. Dodd free_iorr_addr = iorr_addr; 40034345c08SMatthew N. Dodd } 40134345c08SMatthew N. Dodd 40234345c08SMatthew N. Dodd if (iorr_addr >= AMD_K7_NUM_IORR) { 40334345c08SMatthew N. Dodd iorr_addr = free_iorr_addr; 40434345c08SMatthew N. Dodd if (iorr_addr >= AMD_K7_NUM_IORR) 40534345c08SMatthew N. Dodd return (EINVAL); 40634345c08SMatthew N. Dodd } 40734345c08SMatthew N. Dodd 40834345c08SMatthew N. Dodd base = (addr & ~0xfff) | 0x18; 40934345c08SMatthew N. Dodd mask = (0xfULL << 32) | ((~(size - 1)) & 0xfffff000) | 0x800; 41034345c08SMatthew N. Dodd wrmsr(IORR_BASE0 + 2 * iorr_addr, base); 41134345c08SMatthew N. Dodd wrmsr(IORR_MASK0 + 2 * iorr_addr, mask); 41234345c08SMatthew N. Dodd 41334345c08SMatthew N. Dodd sys = rdmsr(SYSCFG); 41434345c08SMatthew N. Dodd sys |= 0x00100000ULL; 41534345c08SMatthew N. Dodd wrmsr(SYSCFG, sys); 41634345c08SMatthew N. Dodd 41734345c08SMatthew N. Dodd return (0); 41834345c08SMatthew N. Dodd } 41934345c08SMatthew N. Dodd 42034345c08SMatthew N. Dodd static device_method_t agp_nvidia_methods[] = { 42134345c08SMatthew N. Dodd /* Device interface */ 42234345c08SMatthew N. Dodd DEVMETHOD(device_probe, agp_nvidia_probe), 42334345c08SMatthew N. Dodd DEVMETHOD(device_attach, agp_nvidia_attach), 42434345c08SMatthew N. Dodd DEVMETHOD(device_detach, agp_nvidia_detach), 42534345c08SMatthew N. Dodd DEVMETHOD(device_shutdown, bus_generic_shutdown), 42634345c08SMatthew N. Dodd DEVMETHOD(device_suspend, bus_generic_suspend), 42734345c08SMatthew N. Dodd DEVMETHOD(device_resume, bus_generic_resume), 42834345c08SMatthew N. Dodd 42934345c08SMatthew N. Dodd /* AGP interface */ 43034345c08SMatthew N. Dodd DEVMETHOD(agp_get_aperture, agp_nvidia_get_aperture), 43134345c08SMatthew N. Dodd DEVMETHOD(agp_set_aperture, agp_nvidia_set_aperture), 43234345c08SMatthew N. Dodd DEVMETHOD(agp_bind_page, agp_nvidia_bind_page), 43334345c08SMatthew N. Dodd DEVMETHOD(agp_unbind_page, agp_nvidia_unbind_page), 43434345c08SMatthew N. Dodd DEVMETHOD(agp_flush_tlb, agp_nvidia_flush_tlb), 43534345c08SMatthew N. Dodd 43634345c08SMatthew N. Dodd DEVMETHOD(agp_enable, agp_generic_enable), 43734345c08SMatthew N. Dodd DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 43834345c08SMatthew N. Dodd DEVMETHOD(agp_free_memory, agp_generic_free_memory), 43934345c08SMatthew N. Dodd DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 44034345c08SMatthew N. Dodd DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 44134345c08SMatthew N. Dodd 44234345c08SMatthew N. Dodd { 0, 0 } 44334345c08SMatthew N. Dodd }; 44434345c08SMatthew N. Dodd 44534345c08SMatthew N. Dodd static driver_t agp_nvidia_driver = { 44634345c08SMatthew N. Dodd "agp", 44734345c08SMatthew N. Dodd agp_nvidia_methods, 44834345c08SMatthew N. Dodd sizeof(struct agp_nvidia_softc), 44934345c08SMatthew N. Dodd }; 45034345c08SMatthew N. Dodd 45134345c08SMatthew N. Dodd static devclass_t agp_devclass; 45234345c08SMatthew N. Dodd 45334345c08SMatthew N. Dodd DRIVER_MODULE(agp_nvidia, pci, agp_nvidia_driver, agp_devclass, 0, 0); 45434345c08SMatthew N. Dodd MODULE_DEPEND(agp_nvidia, agp, 1, 1, 1); 45534345c08SMatthew N. Dodd MODULE_DEPEND(agp_nvidia, pci, 1, 1, 1); 456