1 /*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_bus.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <sys/proc.h> 40 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcireg.h> 43 #include <pci/agppriv.h> 44 #include <pci/agpreg.h> 45 46 #include <vm/vm.h> 47 #include <vm/vm_object.h> 48 #include <vm/pmap.h> 49 50 #define MAX_APSIZE 0x3f /* 256 MB */ 51 52 struct agp_intel_softc { 53 struct agp_softc agp; 54 u_int32_t initial_aperture; /* aperture size at startup */ 55 struct agp_gatt *gatt; 56 u_int aperture_mask; 57 }; 58 59 static const char* 60 agp_intel_match(device_t dev) 61 { 62 if (pci_get_class(dev) != PCIC_BRIDGE 63 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST) 64 return NULL; 65 66 if (agp_find_caps(dev) == 0) 67 return NULL; 68 69 switch (pci_get_devid(dev)) { 70 /* Intel -- vendor 0x8086 */ 71 case 0x71808086: 72 return ("Intel 82443LX (440 LX) host to PCI bridge"); 73 74 case 0x71908086: 75 return ("Intel 82443BX (440 BX) host to PCI bridge"); 76 77 case 0x71a08086: 78 return ("Intel 82443GX host to PCI bridge"); 79 80 case 0x71a18086: 81 return ("Intel 82443GX host to AGP bridge"); 82 83 case 0x11308086: 84 return ("Intel 82815 (i815 GMCH) host to PCI bridge"); 85 86 case 0x25008086: 87 case 0x25018086: 88 return ("Intel 82820 host to AGP bridge"); 89 90 case 0x35758086: 91 return ("Intel 82830 host to AGP bridge"); 92 93 case 0x1a218086: 94 return ("Intel 82840 host to AGP bridge"); 95 96 case 0x1a308086: 97 return ("Intel 82845 host to AGP bridge"); 98 99 case 0x25308086: 100 return ("Intel 82850 host to AGP bridge"); 101 102 case 0x33408086: 103 return ("Intel 82855 host to AGP bridge"); 104 105 case 0x25318086: 106 return ("Intel 82860 host to AGP bridge"); 107 108 case 0x25708086: 109 return ("Intel 82865 host to AGP bridge"); 110 111 case 0x25788086: 112 return ("Intel 82875P host to AGP bridge"); 113 114 case 0x25608086: /* i845G */ 115 return ("Intel 82845G host to AGP bridge"); 116 }; 117 118 if (pci_get_vendor(dev) == 0x8086) 119 return ("Intel Generic host to PCI bridge"); 120 121 return NULL; 122 } 123 124 static int 125 agp_intel_probe(device_t dev) 126 { 127 const char *desc; 128 129 if (resource_disabled("agp", device_get_unit(dev))) 130 return (ENXIO); 131 desc = agp_intel_match(dev); 132 if (desc) { 133 device_verbose(dev); 134 device_set_desc(dev, desc); 135 return 0; 136 } 137 138 return ENXIO; 139 } 140 141 static int 142 agp_intel_attach(device_t dev) 143 { 144 struct agp_intel_softc *sc = device_get_softc(dev); 145 struct agp_gatt *gatt; 146 u_int32_t type = pci_get_devid(dev); 147 u_int32_t value; 148 int error; 149 150 error = agp_generic_attach(dev); 151 if (error) 152 return error; 153 154 /* Determine maximum supported aperture size. */ 155 value = pci_read_config(dev, AGP_INTEL_APSIZE, 1); 156 pci_write_config(dev, AGP_INTEL_APSIZE, MAX_APSIZE, 1); 157 sc->aperture_mask = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & 158 MAX_APSIZE; 159 pci_write_config(dev, AGP_INTEL_APSIZE, value, 1); 160 sc->initial_aperture = AGP_GET_APERTURE(dev); 161 162 for (;;) { 163 gatt = agp_alloc_gatt(dev); 164 if (gatt) 165 break; 166 167 /* 168 * Probably contigmalloc failure. Try reducing the 169 * aperture so that the gatt size reduces. 170 */ 171 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) { 172 agp_generic_detach(dev); 173 return ENOMEM; 174 } 175 } 176 sc->gatt = gatt; 177 178 /* Install the gatt. */ 179 pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4); 180 181 /* Enable the GLTB and setup the control register. */ 182 switch (type) { 183 case 0x71908086: /* 440LX/EX */ 184 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2080, 4); 185 break; 186 case 0x71808086: /* 440BX */ 187 /* 188 * XXX: Should be 0xa080? Bit 9 is undefined, and 189 * bit 13 being on and bit 15 being clear is illegal. 190 */ 191 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4); 192 break; 193 default: 194 value = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 195 pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4); 196 } 197 198 /* Enable things, clear errors etc. */ 199 switch (type) { 200 case 0x1a218086: /* i840 */ 201 case 0x25308086: /* i850 */ 202 case 0x25318086: /* i860 */ 203 pci_write_config(dev, AGP_INTEL_MCHCFG, 204 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 205 | (1 << 9)), 2); 206 break; 207 208 case 0x25008086: /* i820 */ 209 case 0x25018086: /* i820 */ 210 pci_write_config(dev, AGP_INTEL_I820_RDCR, 211 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 212 | (1 << 1)), 1); 213 break; 214 215 case 0x1a308086: /* i845 */ 216 case 0x33408086: /* i855 */ 217 case 0x25708086: /* i865 */ 218 case 0x25788086: /* i875P */ 219 case 0x25608086: /* i845G */ 220 pci_write_config(dev, AGP_INTEL_I845_MCHCFG, 221 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 222 | (1 << 1)), 1); 223 break; 224 225 default: /* Intel Generic (maybe) */ 226 pci_write_config(dev, AGP_INTEL_NBXCFG, 227 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 228 & ~(1 << 10)) | (1 << 9), 4); 229 } 230 231 switch (type) { 232 case 0x1a218086: /* i840 */ 233 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2); 234 break; 235 236 case 0x25008086: /* i820 */ 237 case 0x25018086: /* i820 */ 238 case 0x1a308086: /* i845 */ 239 case 0x25308086: /* i850 */ 240 case 0x33408086: /* i855 */ 241 case 0x25318086: /* i860 */ 242 case 0x25708086: /* i865 */ 243 case 0x25788086: /* i875P */ 244 case 0x25608086: /* i845G */ 245 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2); 246 break; 247 248 default: /* Intel Generic (maybe) */ 249 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1); 250 } 251 252 return 0; 253 } 254 255 static int 256 agp_intel_detach(device_t dev) 257 { 258 struct agp_intel_softc *sc = device_get_softc(dev); 259 u_int32_t type = pci_get_devid(dev); 260 int error; 261 262 error = agp_generic_detach(dev); 263 if (error) 264 return error; 265 266 switch (type) { 267 case 0x1a218086: /* i840 */ 268 case 0x25308086: /* i850 */ 269 case 0x25318086: /* i860 */ 270 printf("%s: set MCHCFG to %x\n", __func__, (unsigned) 271 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 272 & ~(1 << 9))); 273 pci_write_config(dev, AGP_INTEL_MCHCFG, 274 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 275 & ~(1 << 9)), 2); 276 277 case 0x25008086: /* i820 */ 278 case 0x25018086: /* i820 */ 279 printf("%s: set RDCR to %x\n", __func__, (unsigned) 280 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 281 & ~(1 << 1))); 282 pci_write_config(dev, AGP_INTEL_I820_RDCR, 283 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 284 & ~(1 << 1)), 1); 285 286 case 0x1a308086: /* i845 */ 287 case 0x25608086: /* i845G */ 288 case 0x33408086: /* i855 */ 289 case 0x25708086: /* i865 */ 290 case 0x25788086: /* i875P */ 291 printf("%s: set MCHCFG to %x\n", __func__, (unsigned) 292 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 293 & ~(1 << 1))); 294 pci_write_config(dev, AGP_INTEL_MCHCFG, 295 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 296 & ~(1 << 1)), 1); 297 298 default: /* Intel Generic (maybe) */ 299 printf("%s: set NBXCFG to %x\n", __func__, 300 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 301 & ~(1 << 9))); 302 pci_write_config(dev, AGP_INTEL_NBXCFG, 303 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 304 & ~(1 << 9)), 4); 305 } 306 pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4); 307 AGP_SET_APERTURE(dev, sc->initial_aperture); 308 agp_free_gatt(sc->gatt); 309 310 return 0; 311 } 312 313 static u_int32_t 314 agp_intel_get_aperture(device_t dev) 315 { 316 struct agp_intel_softc *sc = device_get_softc(dev); 317 u_int32_t apsize; 318 319 apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & sc->aperture_mask; 320 321 /* 322 * The size is determined by the number of low bits of 323 * register APBASE which are forced to zero. The low 22 bits 324 * are always forced to zero and each zero bit in the apsize 325 * field just read forces the corresponding bit in the 27:22 326 * to be zero. We calculate the aperture size accordingly. 327 */ 328 return (((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1; 329 } 330 331 static int 332 agp_intel_set_aperture(device_t dev, u_int32_t aperture) 333 { 334 struct agp_intel_softc *sc = device_get_softc(dev); 335 u_int32_t apsize; 336 337 /* 338 * Reverse the magic from get_aperture. 339 */ 340 apsize = ((aperture - 1) >> 22) ^ sc->aperture_mask; 341 342 /* 343 * Double check for sanity. 344 */ 345 if ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1 != aperture) 346 return EINVAL; 347 348 pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1); 349 350 return 0; 351 } 352 353 static int 354 agp_intel_bind_page(device_t dev, int offset, vm_offset_t physical) 355 { 356 struct agp_intel_softc *sc = device_get_softc(dev); 357 358 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 359 return EINVAL; 360 361 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 362 return 0; 363 } 364 365 static int 366 agp_intel_unbind_page(device_t dev, int offset) 367 { 368 struct agp_intel_softc *sc = device_get_softc(dev); 369 370 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 371 return EINVAL; 372 373 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 374 return 0; 375 } 376 377 static void 378 agp_intel_flush_tlb(device_t dev) 379 { 380 u_int32_t val; 381 382 val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 383 pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 7), 4); 384 pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4); 385 } 386 387 static device_method_t agp_intel_methods[] = { 388 /* Device interface */ 389 DEVMETHOD(device_probe, agp_intel_probe), 390 DEVMETHOD(device_attach, agp_intel_attach), 391 DEVMETHOD(device_detach, agp_intel_detach), 392 DEVMETHOD(device_shutdown, bus_generic_shutdown), 393 DEVMETHOD(device_suspend, bus_generic_suspend), 394 DEVMETHOD(device_resume, bus_generic_resume), 395 396 /* AGP interface */ 397 DEVMETHOD(agp_get_aperture, agp_intel_get_aperture), 398 DEVMETHOD(agp_set_aperture, agp_intel_set_aperture), 399 DEVMETHOD(agp_bind_page, agp_intel_bind_page), 400 DEVMETHOD(agp_unbind_page, agp_intel_unbind_page), 401 DEVMETHOD(agp_flush_tlb, agp_intel_flush_tlb), 402 DEVMETHOD(agp_enable, agp_generic_enable), 403 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 404 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 405 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 406 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 407 408 { 0, 0 } 409 }; 410 411 static driver_t agp_intel_driver = { 412 "agp", 413 agp_intel_methods, 414 sizeof(struct agp_intel_softc), 415 }; 416 417 static devclass_t agp_devclass; 418 419 DRIVER_MODULE(agp_intel, pci, agp_intel_driver, agp_devclass, 0, 0); 420 MODULE_DEPEND(agp_intel, agp, 1, 1, 1); 421 MODULE_DEPEND(agp_intel, pci, 1, 1, 1); 422