1 /*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_bus.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/lock.h> 38 #include <sys/lockmgr.h> 39 #include <sys/mutex.h> 40 #include <sys/proc.h> 41 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcireg.h> 44 #include <pci/agppriv.h> 45 #include <pci/agpreg.h> 46 47 #include <vm/vm.h> 48 #include <vm/vm_object.h> 49 #include <vm/pmap.h> 50 51 #define MAX_APSIZE 0x3f /* 256 MB */ 52 53 struct agp_intel_softc { 54 struct agp_softc agp; 55 u_int32_t initial_aperture; /* aperture size at startup */ 56 struct agp_gatt *gatt; 57 u_int aperture_mask; 58 }; 59 60 static const char* 61 agp_intel_match(device_t dev) 62 { 63 if (pci_get_class(dev) != PCIC_BRIDGE 64 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST) 65 return NULL; 66 67 if (agp_find_caps(dev) == 0) 68 return NULL; 69 70 switch (pci_get_devid(dev)) { 71 /* Intel -- vendor 0x8086 */ 72 case 0x71808086: 73 return ("Intel 82443LX (440 LX) host to PCI bridge"); 74 75 case 0x71908086: 76 return ("Intel 82443BX (440 BX) host to PCI bridge"); 77 78 case 0x71a08086: 79 return ("Intel 82443GX host to PCI bridge"); 80 81 case 0x71a18086: 82 return ("Intel 82443GX host to AGP bridge"); 83 84 case 0x11308086: 85 return ("Intel 82815 (i815 GMCH) host to PCI bridge"); 86 87 case 0x25008086: 88 case 0x25018086: 89 return ("Intel 82820 host to AGP bridge"); 90 91 case 0x35758086: 92 return ("Intel 82830 host to AGP bridge"); 93 94 case 0x1a218086: 95 return ("Intel 82840 host to AGP bridge"); 96 97 case 0x1a308086: 98 return ("Intel 82845 host to AGP bridge"); 99 100 case 0x25308086: 101 return ("Intel 82850 host to AGP bridge"); 102 103 case 0x33408086: 104 return ("Intel 82855 host to AGP bridge"); 105 106 case 0x25318086: 107 return ("Intel 82860 host to AGP bridge"); 108 109 case 0x25708086: 110 return ("Intel 82865 host to AGP bridge"); 111 112 case 0x25788086: 113 return ("Intel 82875P host to AGP bridge"); 114 115 case 0x25608086: /* i845G */ 116 return ("Intel 82845G host to AGP bridge"); 117 }; 118 119 if (pci_get_vendor(dev) == 0x8086) 120 return ("Intel Generic host to PCI bridge"); 121 122 return NULL; 123 } 124 125 static int 126 agp_intel_probe(device_t dev) 127 { 128 const char *desc; 129 130 desc = agp_intel_match(dev); 131 if (desc) { 132 device_verbose(dev); 133 device_set_desc(dev, desc); 134 return 0; 135 } 136 137 return ENXIO; 138 } 139 140 static int 141 agp_intel_attach(device_t dev) 142 { 143 struct agp_intel_softc *sc = device_get_softc(dev); 144 struct agp_gatt *gatt; 145 u_int32_t type = pci_get_devid(dev); 146 u_int32_t value; 147 int error; 148 149 error = agp_generic_attach(dev); 150 if (error) 151 return error; 152 153 /* Determine maximum supported aperture size. */ 154 value = pci_read_config(dev, AGP_INTEL_APSIZE, 1); 155 pci_write_config(dev, AGP_INTEL_APSIZE, MAX_APSIZE, 1); 156 sc->aperture_mask = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & 157 MAX_APSIZE; 158 pci_write_config(dev, AGP_INTEL_APSIZE, value, 1); 159 sc->initial_aperture = AGP_GET_APERTURE(dev); 160 161 for (;;) { 162 gatt = agp_alloc_gatt(dev); 163 if (gatt) 164 break; 165 166 /* 167 * Probably contigmalloc failure. Try reducing the 168 * aperture so that the gatt size reduces. 169 */ 170 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) { 171 agp_generic_detach(dev); 172 return ENOMEM; 173 } 174 } 175 sc->gatt = gatt; 176 177 /* Install the gatt. */ 178 pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4); 179 180 /* Enable the GLTB and setup the control register. */ 181 switch (type) { 182 case 0x71908086: /* 440LX/EX */ 183 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2080, 4); 184 break; 185 case 0x71808086: /* 440BX */ 186 /* 187 * XXX: Should be 0xa080? Bit 9 is undefined, and 188 * bit 13 being on and bit 15 being clear is illegal. 189 */ 190 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4); 191 break; 192 default: 193 value = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 194 pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4); 195 } 196 197 /* Enable things, clear errors etc. */ 198 switch (type) { 199 case 0x1a218086: /* i840 */ 200 case 0x25308086: /* i850 */ 201 case 0x25318086: /* i860 */ 202 pci_write_config(dev, AGP_INTEL_MCHCFG, 203 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 204 | (1 << 9)), 2); 205 break; 206 207 case 0x25008086: /* i820 */ 208 case 0x25018086: /* i820 */ 209 pci_write_config(dev, AGP_INTEL_I820_RDCR, 210 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 211 | (1 << 1)), 1); 212 break; 213 214 case 0x1a308086: /* i845 */ 215 case 0x33408086: /* i855 */ 216 case 0x25708086: /* i865 */ 217 case 0x25788086: /* i875P */ 218 case 0x25608086: /* i845G */ 219 pci_write_config(dev, AGP_INTEL_I845_MCHCFG, 220 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 221 | (1 << 1)), 1); 222 break; 223 224 default: /* Intel Generic (maybe) */ 225 pci_write_config(dev, AGP_INTEL_NBXCFG, 226 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 227 & ~(1 << 10)) | (1 << 9), 4); 228 } 229 230 switch (type) { 231 case 0x1a218086: /* i840 */ 232 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2); 233 break; 234 235 case 0x25008086: /* i820 */ 236 case 0x25018086: /* i820 */ 237 case 0x1a308086: /* i845 */ 238 case 0x25308086: /* i850 */ 239 case 0x33408086: /* i855 */ 240 case 0x25318086: /* i860 */ 241 case 0x25708086: /* i865 */ 242 case 0x25788086: /* i875P */ 243 case 0x25608086: /* i845G */ 244 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2); 245 break; 246 247 default: /* Intel Generic (maybe) */ 248 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1); 249 } 250 251 return 0; 252 } 253 254 static int 255 agp_intel_detach(device_t dev) 256 { 257 struct agp_intel_softc *sc = device_get_softc(dev); 258 u_int32_t type = pci_get_devid(dev); 259 int error; 260 261 error = agp_generic_detach(dev); 262 if (error) 263 return error; 264 265 switch (type) { 266 case 0x1a218086: /* i840 */ 267 case 0x25308086: /* i850 */ 268 case 0x25318086: /* i860 */ 269 printf("%s: set MCHCFG to %x\n", __func__, (unsigned) 270 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 271 & ~(1 << 9))); 272 pci_write_config(dev, AGP_INTEL_MCHCFG, 273 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 274 & ~(1 << 9)), 2); 275 276 case 0x25008086: /* i820 */ 277 case 0x25018086: /* i820 */ 278 printf("%s: set RDCR to %x\n", __func__, (unsigned) 279 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 280 & ~(1 << 1))); 281 pci_write_config(dev, AGP_INTEL_I820_RDCR, 282 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 283 & ~(1 << 1)), 1); 284 285 case 0x1a308086: /* i845 */ 286 case 0x25608086: /* i845G */ 287 case 0x33408086: /* i855 */ 288 case 0x25708086: /* i865 */ 289 case 0x25788086: /* i875P */ 290 printf("%s: set MCHCFG to %x\n", __func__, (unsigned) 291 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 292 & ~(1 << 1))); 293 pci_write_config(dev, AGP_INTEL_MCHCFG, 294 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 295 & ~(1 << 1)), 1); 296 297 default: /* Intel Generic (maybe) */ 298 printf("%s: set NBXCFG to %x\n", __func__, 299 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 300 & ~(1 << 9))); 301 pci_write_config(dev, AGP_INTEL_NBXCFG, 302 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 303 & ~(1 << 9)), 4); 304 } 305 pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4); 306 AGP_SET_APERTURE(dev, sc->initial_aperture); 307 agp_free_gatt(sc->gatt); 308 309 return 0; 310 } 311 312 static u_int32_t 313 agp_intel_get_aperture(device_t dev) 314 { 315 struct agp_intel_softc *sc = device_get_softc(dev); 316 u_int32_t apsize; 317 318 apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & sc->aperture_mask; 319 320 /* 321 * The size is determined by the number of low bits of 322 * register APBASE which are forced to zero. The low 22 bits 323 * are always forced to zero and each zero bit in the apsize 324 * field just read forces the corresponding bit in the 27:22 325 * to be zero. We calculate the aperture size accordingly. 326 */ 327 return (((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1; 328 } 329 330 static int 331 agp_intel_set_aperture(device_t dev, u_int32_t aperture) 332 { 333 struct agp_intel_softc *sc = device_get_softc(dev); 334 u_int32_t apsize; 335 336 /* 337 * Reverse the magic from get_aperture. 338 */ 339 apsize = ((aperture - 1) >> 22) ^ sc->aperture_mask; 340 341 /* 342 * Double check for sanity. 343 */ 344 if ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1 != aperture) 345 return EINVAL; 346 347 pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1); 348 349 return 0; 350 } 351 352 static int 353 agp_intel_bind_page(device_t dev, int offset, vm_offset_t physical) 354 { 355 struct agp_intel_softc *sc = device_get_softc(dev); 356 357 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 358 return EINVAL; 359 360 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 361 return 0; 362 } 363 364 static int 365 agp_intel_unbind_page(device_t dev, int offset) 366 { 367 struct agp_intel_softc *sc = device_get_softc(dev); 368 369 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 370 return EINVAL; 371 372 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 373 return 0; 374 } 375 376 static void 377 agp_intel_flush_tlb(device_t dev) 378 { 379 u_int32_t val; 380 381 val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 382 pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 7), 4); 383 pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4); 384 } 385 386 static device_method_t agp_intel_methods[] = { 387 /* Device interface */ 388 DEVMETHOD(device_probe, agp_intel_probe), 389 DEVMETHOD(device_attach, agp_intel_attach), 390 DEVMETHOD(device_detach, agp_intel_detach), 391 DEVMETHOD(device_shutdown, bus_generic_shutdown), 392 DEVMETHOD(device_suspend, bus_generic_suspend), 393 DEVMETHOD(device_resume, bus_generic_resume), 394 395 /* AGP interface */ 396 DEVMETHOD(agp_get_aperture, agp_intel_get_aperture), 397 DEVMETHOD(agp_set_aperture, agp_intel_set_aperture), 398 DEVMETHOD(agp_bind_page, agp_intel_bind_page), 399 DEVMETHOD(agp_unbind_page, agp_intel_unbind_page), 400 DEVMETHOD(agp_flush_tlb, agp_intel_flush_tlb), 401 DEVMETHOD(agp_enable, agp_generic_enable), 402 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 403 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 404 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 405 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 406 407 { 0, 0 } 408 }; 409 410 static driver_t agp_intel_driver = { 411 "agp", 412 agp_intel_methods, 413 sizeof(struct agp_intel_softc), 414 }; 415 416 static devclass_t agp_devclass; 417 418 DRIVER_MODULE(agp_intel, pci, agp_intel_driver, agp_devclass, 0, 0); 419 MODULE_DEPEND(agp_intel, agp, 1, 1, 1); 420 MODULE_DEPEND(agp_intel, pci, 1, 1, 1); 421