1 /*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_bus.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/bus.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/proc.h> 41 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcireg.h> 44 #include <pci/agppriv.h> 45 #include <pci/agpreg.h> 46 47 #include <vm/vm.h> 48 #include <vm/vm_object.h> 49 #include <vm/pmap.h> 50 51 #define MAX_APSIZE 0x3f /* 256 MB */ 52 53 struct agp_intel_softc { 54 struct agp_softc agp; 55 u_int32_t initial_aperture; /* aperture size at startup */ 56 struct agp_gatt *gatt; 57 u_int aperture_mask; 58 }; 59 60 static const char* 61 agp_intel_match(device_t dev) 62 { 63 if (pci_get_class(dev) != PCIC_BRIDGE 64 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST) 65 return NULL; 66 67 if (agp_find_caps(dev) == 0) 68 return NULL; 69 70 switch (pci_get_devid(dev)) { 71 /* Intel -- vendor 0x8086 */ 72 case 0x71808086: 73 return ("Intel 82443LX (440 LX) host to PCI bridge"); 74 75 case 0x71908086: 76 return ("Intel 82443BX (440 BX) host to PCI bridge"); 77 78 case 0x71a08086: 79 return ("Intel 82443GX host to PCI bridge"); 80 81 case 0x71a18086: 82 return ("Intel 82443GX host to AGP bridge"); 83 84 case 0x11308086: 85 return ("Intel 82815 (i815 GMCH) host to PCI bridge"); 86 87 case 0x25008086: 88 case 0x25018086: 89 return ("Intel 82820 host to AGP bridge"); 90 91 case 0x35758086: 92 return ("Intel 82830 host to AGP bridge"); 93 94 case 0x1a218086: 95 return ("Intel 82840 host to AGP bridge"); 96 97 case 0x1a308086: 98 return ("Intel 82845 host to AGP bridge"); 99 100 case 0x25308086: 101 return ("Intel 82850 host to AGP bridge"); 102 103 case 0x33408086: 104 return ("Intel 82855 host to AGP bridge"); 105 106 case 0x25318086: 107 return ("Intel 82860 host to AGP bridge"); 108 109 case 0x25708086: 110 return ("Intel 82865 host to AGP bridge"); 111 112 case 0x255d8086: 113 return ("Intel E7205 host to AGP bridge"); 114 115 case 0x25508086: 116 return ("Intel E7505 host to AGP bridge"); 117 118 case 0x25788086: 119 return ("Intel 82875P host to AGP bridge"); 120 121 case 0x25608086: 122 return ("Intel 82845G host to AGP bridge"); 123 124 case 0x35808086: 125 return ("Intel 82855GM host to AGP bridge"); 126 }; 127 128 return NULL; 129 } 130 131 static int 132 agp_intel_probe(device_t dev) 133 { 134 const char *desc; 135 136 if (resource_disabled("agp", device_get_unit(dev))) 137 return (ENXIO); 138 desc = agp_intel_match(dev); 139 if (desc) { 140 device_set_desc(dev, desc); 141 return BUS_PROBE_DEFAULT; 142 } 143 144 return ENXIO; 145 } 146 147 static int 148 agp_intel_attach(device_t dev) 149 { 150 struct agp_intel_softc *sc = device_get_softc(dev); 151 struct agp_gatt *gatt; 152 u_int32_t type = pci_get_devid(dev); 153 u_int32_t value; 154 int error; 155 156 error = agp_generic_attach(dev); 157 if (error) 158 return error; 159 160 /* Determine maximum supported aperture size. */ 161 value = pci_read_config(dev, AGP_INTEL_APSIZE, 1); 162 pci_write_config(dev, AGP_INTEL_APSIZE, MAX_APSIZE, 1); 163 sc->aperture_mask = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & 164 MAX_APSIZE; 165 pci_write_config(dev, AGP_INTEL_APSIZE, value, 1); 166 sc->initial_aperture = AGP_GET_APERTURE(dev); 167 168 for (;;) { 169 gatt = agp_alloc_gatt(dev); 170 if (gatt) 171 break; 172 173 /* 174 * Probably contigmalloc failure. Try reducing the 175 * aperture so that the gatt size reduces. 176 */ 177 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) { 178 agp_generic_detach(dev); 179 return ENOMEM; 180 } 181 } 182 sc->gatt = gatt; 183 184 /* Install the gatt. */ 185 pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4); 186 187 /* Enable the GLTB and setup the control register. */ 188 switch (type) { 189 case 0x71908086: /* 440LX/EX */ 190 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2080, 4); 191 break; 192 case 0x71808086: /* 440BX */ 193 /* 194 * XXX: Should be 0xa080? Bit 9 is undefined, and 195 * bit 13 being on and bit 15 being clear is illegal. 196 */ 197 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4); 198 break; 199 default: 200 value = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 201 pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4); 202 } 203 204 /* Enable things, clear errors etc. */ 205 switch (type) { 206 case 0x1a218086: /* i840 */ 207 case 0x25308086: /* i850 */ 208 case 0x25318086: /* i860 */ 209 pci_write_config(dev, AGP_INTEL_MCHCFG, 210 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 211 | (1 << 9)), 2); 212 break; 213 214 case 0x25008086: /* i820 */ 215 case 0x25018086: /* i820 */ 216 pci_write_config(dev, AGP_INTEL_I820_RDCR, 217 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 218 | (1 << 1)), 1); 219 break; 220 221 case 0x1a308086: /* i845 */ 222 case 0x33408086: /* i855 */ 223 case 0x35808086: /* i855GM */ 224 case 0x255d8086: /* E7205 */ 225 case 0x25508086: /* E7505 */ 226 case 0x25708086: /* i865 */ 227 case 0x25788086: /* i875P */ 228 case 0x25608086: /* i845G */ 229 pci_write_config(dev, AGP_INTEL_I845_MCHCFG, 230 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 231 | (1 << 1)), 1); 232 break; 233 234 default: /* Intel Generic (maybe) */ 235 pci_write_config(dev, AGP_INTEL_NBXCFG, 236 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 237 & ~(1 << 10)) | (1 << 9), 4); 238 } 239 240 switch (type) { 241 case 0x1a218086: /* i840 */ 242 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2); 243 break; 244 245 case 0x25008086: /* i820 */ 246 case 0x25018086: /* i820 */ 247 case 0x1a308086: /* i845 */ 248 case 0x25308086: /* i850 */ 249 case 0x33408086: /* i855 */ 250 case 0x255d8086: /* E7205 */ 251 case 0x25508086: /* E7505 */ 252 case 0x25318086: /* i860 */ 253 case 0x25708086: /* i865 */ 254 case 0x25788086: /* i875P */ 255 case 0x25608086: /* i845G */ 256 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2); 257 break; 258 259 default: /* Intel Generic (maybe) */ 260 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1); 261 } 262 263 return 0; 264 } 265 266 static int 267 agp_intel_detach(device_t dev) 268 { 269 struct agp_intel_softc *sc = device_get_softc(dev); 270 u_int32_t type = pci_get_devid(dev); 271 int error; 272 273 error = agp_generic_detach(dev); 274 if (error) 275 return error; 276 277 switch (type) { 278 case 0x1a218086: /* i840 */ 279 case 0x25308086: /* i850 */ 280 case 0x25318086: /* i860 */ 281 printf("%s: set MCHCFG to %x\n", __func__, (unsigned) 282 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 283 & ~(1 << 9))); 284 pci_write_config(dev, AGP_INTEL_MCHCFG, 285 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 286 & ~(1 << 9)), 2); 287 288 case 0x25008086: /* i820 */ 289 case 0x25018086: /* i820 */ 290 printf("%s: set RDCR to %x\n", __func__, (unsigned) 291 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 292 & ~(1 << 1))); 293 pci_write_config(dev, AGP_INTEL_I820_RDCR, 294 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 295 & ~(1 << 1)), 1); 296 297 case 0x1a308086: /* i845 */ 298 case 0x25608086: /* i845G */ 299 case 0x33408086: /* i855 */ 300 case 0x35808086: /* i855GM */ 301 case 0x255d8086: /* E7205 */ 302 case 0x25508086: /* E7505 */ 303 case 0x25708086: /* i865 */ 304 case 0x25788086: /* i875P */ 305 printf("%s: set MCHCFG to %x\n", __func__, (unsigned) 306 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 307 & ~(1 << 1))); 308 pci_write_config(dev, AGP_INTEL_MCHCFG, 309 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 310 & ~(1 << 1)), 1); 311 312 default: /* Intel Generic (maybe) */ 313 printf("%s: set NBXCFG to %x\n", __func__, 314 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 315 & ~(1 << 9))); 316 pci_write_config(dev, AGP_INTEL_NBXCFG, 317 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 318 & ~(1 << 9)), 4); 319 } 320 pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4); 321 AGP_SET_APERTURE(dev, sc->initial_aperture); 322 agp_free_gatt(sc->gatt); 323 324 return 0; 325 } 326 327 static u_int32_t 328 agp_intel_get_aperture(device_t dev) 329 { 330 struct agp_intel_softc *sc = device_get_softc(dev); 331 u_int32_t apsize; 332 333 apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & sc->aperture_mask; 334 335 /* 336 * The size is determined by the number of low bits of 337 * register APBASE which are forced to zero. The low 22 bits 338 * are always forced to zero and each zero bit in the apsize 339 * field just read forces the corresponding bit in the 27:22 340 * to be zero. We calculate the aperture size accordingly. 341 */ 342 return (((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1; 343 } 344 345 static int 346 agp_intel_set_aperture(device_t dev, u_int32_t aperture) 347 { 348 struct agp_intel_softc *sc = device_get_softc(dev); 349 u_int32_t apsize; 350 351 /* 352 * Reverse the magic from get_aperture. 353 */ 354 apsize = ((aperture - 1) >> 22) ^ sc->aperture_mask; 355 356 /* 357 * Double check for sanity. 358 */ 359 if ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1 != aperture) 360 return EINVAL; 361 362 pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1); 363 364 return 0; 365 } 366 367 static int 368 agp_intel_bind_page(device_t dev, int offset, vm_offset_t physical) 369 { 370 struct agp_intel_softc *sc = device_get_softc(dev); 371 372 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 373 return EINVAL; 374 375 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 376 return 0; 377 } 378 379 static int 380 agp_intel_unbind_page(device_t dev, int offset) 381 { 382 struct agp_intel_softc *sc = device_get_softc(dev); 383 384 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 385 return EINVAL; 386 387 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 388 return 0; 389 } 390 391 static void 392 agp_intel_flush_tlb(device_t dev) 393 { 394 u_int32_t val; 395 396 val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 397 pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 7), 4); 398 pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4); 399 } 400 401 static device_method_t agp_intel_methods[] = { 402 /* Device interface */ 403 DEVMETHOD(device_probe, agp_intel_probe), 404 DEVMETHOD(device_attach, agp_intel_attach), 405 DEVMETHOD(device_detach, agp_intel_detach), 406 DEVMETHOD(device_shutdown, bus_generic_shutdown), 407 DEVMETHOD(device_suspend, bus_generic_suspend), 408 DEVMETHOD(device_resume, bus_generic_resume), 409 410 /* AGP interface */ 411 DEVMETHOD(agp_get_aperture, agp_intel_get_aperture), 412 DEVMETHOD(agp_set_aperture, agp_intel_set_aperture), 413 DEVMETHOD(agp_bind_page, agp_intel_bind_page), 414 DEVMETHOD(agp_unbind_page, agp_intel_unbind_page), 415 DEVMETHOD(agp_flush_tlb, agp_intel_flush_tlb), 416 DEVMETHOD(agp_enable, agp_generic_enable), 417 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 418 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 419 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 420 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 421 422 { 0, 0 } 423 }; 424 425 static driver_t agp_intel_driver = { 426 "agp", 427 agp_intel_methods, 428 sizeof(struct agp_intel_softc), 429 }; 430 431 static devclass_t agp_devclass; 432 433 DRIVER_MODULE(agp_intel, hostb, agp_intel_driver, agp_devclass, 0, 0); 434 MODULE_DEPEND(agp_intel, agp, 1, 1, 1); 435 MODULE_DEPEND(agp_intel, pci, 1, 1, 1); 436