1 /*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include "opt_bus.h" 30 #include "opt_pci.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/lock.h> 38 39 #include <pci/pcivar.h> 40 #include <pci/pcireg.h> 41 #include <pci/agppriv.h> 42 #include <pci/agpreg.h> 43 44 #include <vm/vm.h> 45 #include <vm/vm_object.h> 46 #include <vm/pmap.h> 47 48 struct agp_intel_softc { 49 struct agp_softc agp; 50 u_int32_t initial_aperture; /* aperture size at startup */ 51 struct agp_gatt *gatt; 52 }; 53 54 static const char* 55 agp_intel_match(device_t dev) 56 { 57 if (pci_get_class(dev) != PCIC_BRIDGE 58 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST) 59 return NULL; 60 61 if (agp_find_caps(dev) == 0) 62 return NULL; 63 64 switch (pci_get_devid(dev)) { 65 /* Intel -- vendor 0x8086 */ 66 case 0x71808086: 67 return ("Intel 82443LX (440 LX) host to PCI bridge"); 68 69 case 0x71908086: 70 return ("Intel 82443BX (440 BX) host to PCI bridge"); 71 72 case 0x71a08086: 73 return ("Intel 82443GX host to PCI bridge"); 74 75 case 0x71a18086: 76 return ("Intel 82443GX host to AGP bridge"); 77 }; 78 79 if (pci_get_vendor(dev) == 0x8086) 80 return ("Intel Generic host to PCI bridge"); 81 82 return NULL; 83 } 84 85 static int 86 agp_intel_probe(device_t dev) 87 { 88 const char *desc; 89 90 desc = agp_intel_match(dev); 91 if (desc) { 92 device_verbose(dev); 93 device_set_desc(dev, desc); 94 return 0; 95 } 96 97 return ENXIO; 98 } 99 100 static int 101 agp_intel_attach(device_t dev) 102 { 103 struct agp_intel_softc *sc = device_get_softc(dev); 104 struct agp_gatt *gatt; 105 int error; 106 107 error = agp_generic_attach(dev); 108 if (error) 109 return error; 110 111 sc->initial_aperture = AGP_GET_APERTURE(dev); 112 113 for (;;) { 114 gatt = agp_alloc_gatt(dev); 115 if (gatt) 116 break; 117 118 /* 119 * Probably contigmalloc failure. Try reducing the 120 * aperture so that the gatt size reduces. 121 */ 122 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) { 123 agp_generic_detach(dev); 124 return ENOMEM; 125 } 126 } 127 sc->gatt = gatt; 128 129 /* Install the gatt. */ 130 pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4); 131 132 /* Enable things, clear errors etc. */ 133 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4); 134 pci_write_config(dev, AGP_INTEL_NBXCFG, 135 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 136 & ~(1 << 10)) | (1 << 9), 4); 137 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1); 138 139 return 0; 140 } 141 142 static int 143 agp_intel_detach(device_t dev) 144 { 145 struct agp_intel_softc *sc = device_get_softc(dev); 146 int error; 147 148 error = agp_generic_detach(dev); 149 if (error) 150 return error; 151 152 printf("%s: set NBXCFG to %x\n", __FUNCTION__, 153 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 154 & ~(1 << 9))); 155 pci_write_config(dev, AGP_INTEL_NBXCFG, 156 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 157 & ~(1 << 9)), 4); 158 pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4); 159 AGP_SET_APERTURE(dev, sc->initial_aperture); 160 agp_free_gatt(sc->gatt); 161 162 return 0; 163 } 164 165 static u_int32_t 166 agp_intel_get_aperture(device_t dev) 167 { 168 u_int32_t apsize; 169 170 apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & 0x1f; 171 172 /* 173 * The size is determined by the number of low bits of 174 * register APBASE which are forced to zero. The low 22 bits 175 * are always forced to zero and each zero bit in the apsize 176 * field just read forces the corresponding bit in the 27:22 177 * to be zero. We calculate the aperture size accordingly. 178 */ 179 return (((apsize ^ 0x1f) << 22) | ((1 << 22) - 1)) + 1; 180 } 181 182 static int 183 agp_intel_set_aperture(device_t dev, u_int32_t aperture) 184 { 185 u_int32_t apsize; 186 187 /* 188 * Reverse the magic from get_aperture. 189 */ 190 apsize = ((aperture - 1) >> 22) ^ 0x1f; 191 192 /* 193 * Double check for sanity. 194 */ 195 if ((((apsize ^ 0x1f) << 22) | ((1 << 22) - 1)) + 1 != aperture) 196 return EINVAL; 197 198 pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1); 199 200 return 0; 201 } 202 203 static int 204 agp_intel_bind_page(device_t dev, int offset, vm_offset_t physical) 205 { 206 struct agp_intel_softc *sc = device_get_softc(dev); 207 208 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 209 return EINVAL; 210 211 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 212 return 0; 213 } 214 215 static int 216 agp_intel_unbind_page(device_t dev, int offset) 217 { 218 struct agp_intel_softc *sc = device_get_softc(dev); 219 220 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 221 return EINVAL; 222 223 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 224 return 0; 225 } 226 227 static void 228 agp_intel_flush_tlb(device_t dev) 229 { 230 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2200, 4); 231 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4); 232 } 233 234 static device_method_t agp_intel_methods[] = { 235 /* Device interface */ 236 DEVMETHOD(device_probe, agp_intel_probe), 237 DEVMETHOD(device_attach, agp_intel_attach), 238 DEVMETHOD(device_detach, agp_intel_detach), 239 DEVMETHOD(device_shutdown, bus_generic_shutdown), 240 DEVMETHOD(device_suspend, bus_generic_suspend), 241 DEVMETHOD(device_resume, bus_generic_resume), 242 243 /* AGP interface */ 244 DEVMETHOD(agp_get_aperture, agp_intel_get_aperture), 245 DEVMETHOD(agp_set_aperture, agp_intel_set_aperture), 246 DEVMETHOD(agp_bind_page, agp_intel_bind_page), 247 DEVMETHOD(agp_unbind_page, agp_intel_unbind_page), 248 DEVMETHOD(agp_flush_tlb, agp_intel_flush_tlb), 249 DEVMETHOD(agp_enable, agp_generic_enable), 250 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 251 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 252 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 253 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 254 255 { 0, 0 } 256 }; 257 258 static driver_t agp_intel_driver = { 259 "agp", 260 agp_intel_methods, 261 sizeof(struct agp_intel_softc), 262 }; 263 264 static devclass_t agp_devclass; 265 266 DRIVER_MODULE(agp_intel, pci, agp_intel_driver, agp_devclass, 0, 0); 267