1 /*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include "opt_bus.h" 30 #include "opt_pci.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/lock.h> 38 #include <sys/lockmgr.h> 39 #include <sys/mutex.h> 40 #include <sys/proc.h> 41 42 #include <pci/pcivar.h> 43 #include <pci/pcireg.h> 44 #include <pci/agppriv.h> 45 #include <pci/agpreg.h> 46 47 #include <vm/vm.h> 48 #include <vm/vm_object.h> 49 #include <vm/pmap.h> 50 51 struct agp_intel_softc { 52 struct agp_softc agp; 53 u_int32_t initial_aperture; /* aperture size at startup */ 54 struct agp_gatt *gatt; 55 }; 56 57 static const char* 58 agp_intel_match(device_t dev) 59 { 60 if (pci_get_class(dev) != PCIC_BRIDGE 61 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST) 62 return NULL; 63 64 if (agp_find_caps(dev) == 0) 65 return NULL; 66 67 switch (pci_get_devid(dev)) { 68 /* Intel -- vendor 0x8086 */ 69 case 0x71808086: 70 return ("Intel 82443LX (440 LX) host to PCI bridge"); 71 72 case 0x71908086: 73 return ("Intel 82443BX (440 BX) host to PCI bridge"); 74 75 case 0x71a08086: 76 return ("Intel 82443GX host to PCI bridge"); 77 78 case 0x71a18086: 79 return ("Intel 82443GX host to AGP bridge"); 80 81 case 0x11308086: 82 return ("Intel 82815 (i815 GMCH) host to PCI bridge"); 83 84 case 0x25008086: 85 return ("Intel 82820 host to AGP bridge"); 86 87 case 0x35758086: 88 return ("Intel 82830 host to AGP bridge"); 89 90 case 0x1a218086: 91 return ("Intel 82840 host to AGP bridge"); 92 93 case 0x1a308086: 94 return ("Intel 82845 host to AGP bridge"); 95 96 case 0x25308086: 97 return ("Intel 82850 host to AGP bridge"); 98 99 case 0x25318086: 100 return ("Intel 82860 host to AGP bridge"); 101 }; 102 103 if (pci_get_vendor(dev) == 0x8086) 104 return ("Intel Generic host to PCI bridge"); 105 106 return NULL; 107 } 108 109 static int 110 agp_intel_probe(device_t dev) 111 { 112 const char *desc; 113 114 desc = agp_intel_match(dev); 115 if (desc) { 116 device_verbose(dev); 117 device_set_desc(dev, desc); 118 return 0; 119 } 120 121 return ENXIO; 122 } 123 124 static int 125 agp_intel_attach(device_t dev) 126 { 127 struct agp_intel_softc *sc = device_get_softc(dev); 128 struct agp_gatt *gatt; 129 u_int32_t type = pci_get_devid(dev); 130 int error; 131 132 error = agp_generic_attach(dev); 133 if (error) 134 return error; 135 136 sc->initial_aperture = AGP_GET_APERTURE(dev); 137 138 for (;;) { 139 gatt = agp_alloc_gatt(dev); 140 if (gatt) 141 break; 142 143 /* 144 * Probably contigmalloc failure. Try reducing the 145 * aperture so that the gatt size reduces. 146 */ 147 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) { 148 agp_generic_detach(dev); 149 return ENOMEM; 150 } 151 } 152 sc->gatt = gatt; 153 154 /* Install the gatt. */ 155 pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4); 156 157 /* Enable the GLTB and setup the control register. */ 158 switch (type) { 159 case 0x71908086: /* 440LX/EX */ 160 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2080, 4); 161 break; 162 case 0x71808086: /* 440BX */ 163 /* 164 * XXX: Should be 0xa080? Bit 9 is undefined, and 165 * bit 13 being on and bit 15 being clear is illegal. 166 */ 167 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4); 168 break; 169 default: 170 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0080, 4); 171 } 172 173 /* Enable things, clear errors etc. */ 174 switch (type) { 175 case 0x1a218086: /* i840 */ 176 case 0x25308086: /* i850 */ 177 case 0x25318086: /* i860 */ 178 pci_write_config(dev, AGP_INTEL_MCHCFG, 179 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 180 | (1 << 9)), 2); 181 break; 182 183 case 0x25008086: /* i820 */ 184 pci_write_config(dev, AGP_INTEL_I820_RDCR, 185 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 186 | (1 << 1)), 1); 187 break; 188 189 case 0x1a308086: /* i845 */ 190 pci_write_config(dev, AGP_INTEL_I845_MCHCFG, 191 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 192 | (1 << 1)), 1); 193 break; 194 195 default: /* Intel Generic (maybe) */ 196 pci_write_config(dev, AGP_INTEL_NBXCFG, 197 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 198 & ~(1 << 10)) | (1 << 9), 4); 199 } 200 201 switch (type) { 202 case 0x1a218086: /* i840 */ 203 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2); 204 break; 205 206 case 0x25008086: /* i820 */ 207 case 0x1a308086: /* i845 */ 208 case 0x25308086: /* i850 */ 209 case 0x25318086: /* i860 */ 210 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x001c, 2); 211 break; 212 213 default: /* Intel Generic (maybe) */ 214 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1); 215 } 216 217 return 0; 218 } 219 220 static int 221 agp_intel_detach(device_t dev) 222 { 223 struct agp_intel_softc *sc = device_get_softc(dev); 224 u_int32_t type = pci_get_devid(dev); 225 int error; 226 227 error = agp_generic_detach(dev); 228 if (error) 229 return error; 230 231 switch (type) { 232 case 0x1a218086: /* i840 */ 233 case 0x25308086: /* i850 */ 234 case 0x25318086: /* i860 */ 235 printf("%s: set MCHCFG to %x\n", __func__, (unsigned) 236 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 237 & ~(1 << 9))); 238 pci_write_config(dev, AGP_INTEL_MCHCFG, 239 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 240 & ~(1 << 9)), 2); 241 242 case 0x25008086: /* i820 */ 243 printf("%s: set RDCR to %x\n", __func__, (unsigned) 244 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 245 & ~(1 << 1))); 246 pci_write_config(dev, AGP_INTEL_I820_RDCR, 247 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 248 & ~(1 << 1)), 1); 249 250 case 0x1a308086: /* i845 */ 251 printf("%s: set MCHCFG to %x\n", __func__, (unsigned) 252 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 253 & ~(1 << 1))); 254 pci_write_config(dev, AGP_INTEL_MCHCFG, 255 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 256 & ~(1 << 1)), 1); 257 258 default: /* Intel Generic (maybe) */ 259 printf("%s: set NBXCFG to %x\n", __func__, 260 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 261 & ~(1 << 9))); 262 pci_write_config(dev, AGP_INTEL_NBXCFG, 263 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 264 & ~(1 << 9)), 4); 265 } 266 pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4); 267 AGP_SET_APERTURE(dev, sc->initial_aperture); 268 agp_free_gatt(sc->gatt); 269 270 return 0; 271 } 272 273 static u_int32_t 274 agp_intel_get_aperture(device_t dev) 275 { 276 u_int32_t apsize; 277 278 apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & 0x1f; 279 280 /* 281 * The size is determined by the number of low bits of 282 * register APBASE which are forced to zero. The low 22 bits 283 * are always forced to zero and each zero bit in the apsize 284 * field just read forces the corresponding bit in the 27:22 285 * to be zero. We calculate the aperture size accordingly. 286 */ 287 return (((apsize ^ 0x1f) << 22) | ((1 << 22) - 1)) + 1; 288 } 289 290 static int 291 agp_intel_set_aperture(device_t dev, u_int32_t aperture) 292 { 293 u_int32_t apsize; 294 295 /* 296 * Reverse the magic from get_aperture. 297 */ 298 apsize = ((aperture - 1) >> 22) ^ 0x1f; 299 300 /* 301 * Double check for sanity. 302 */ 303 if ((((apsize ^ 0x1f) << 22) | ((1 << 22) - 1)) + 1 != aperture) 304 return EINVAL; 305 306 pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1); 307 308 return 0; 309 } 310 311 static int 312 agp_intel_bind_page(device_t dev, int offset, vm_offset_t physical) 313 { 314 struct agp_intel_softc *sc = device_get_softc(dev); 315 316 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 317 return EINVAL; 318 319 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 320 return 0; 321 } 322 323 static int 324 agp_intel_unbind_page(device_t dev, int offset) 325 { 326 struct agp_intel_softc *sc = device_get_softc(dev); 327 328 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 329 return EINVAL; 330 331 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 332 return 0; 333 } 334 335 static void 336 agp_intel_flush_tlb(device_t dev) 337 { 338 u_int32_t val; 339 340 val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 341 pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 8), 4); 342 pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4); 343 } 344 345 static device_method_t agp_intel_methods[] = { 346 /* Device interface */ 347 DEVMETHOD(device_probe, agp_intel_probe), 348 DEVMETHOD(device_attach, agp_intel_attach), 349 DEVMETHOD(device_detach, agp_intel_detach), 350 DEVMETHOD(device_shutdown, bus_generic_shutdown), 351 DEVMETHOD(device_suspend, bus_generic_suspend), 352 DEVMETHOD(device_resume, bus_generic_resume), 353 354 /* AGP interface */ 355 DEVMETHOD(agp_get_aperture, agp_intel_get_aperture), 356 DEVMETHOD(agp_set_aperture, agp_intel_set_aperture), 357 DEVMETHOD(agp_bind_page, agp_intel_bind_page), 358 DEVMETHOD(agp_unbind_page, agp_intel_unbind_page), 359 DEVMETHOD(agp_flush_tlb, agp_intel_flush_tlb), 360 DEVMETHOD(agp_enable, agp_generic_enable), 361 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 362 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 363 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 364 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 365 366 { 0, 0 } 367 }; 368 369 static driver_t agp_intel_driver = { 370 "agp", 371 agp_intel_methods, 372 sizeof(struct agp_intel_softc), 373 }; 374 375 static devclass_t agp_devclass; 376 377 DRIVER_MODULE(agp_intel, pci, agp_intel_driver, agp_devclass, 0, 0); 378