1 /*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include "opt_bus.h" 30 #include "opt_pci.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <sys/proc.h> 40 41 #include <pci/pcivar.h> 42 #include <pci/pcireg.h> 43 #include <pci/agppriv.h> 44 #include <pci/agpreg.h> 45 46 #include <vm/vm.h> 47 #include <vm/vm_object.h> 48 #include <vm/pmap.h> 49 50 struct agp_intel_softc { 51 struct agp_softc agp; 52 u_int32_t initial_aperture; /* aperture size at startup */ 53 struct agp_gatt *gatt; 54 }; 55 56 static const char* 57 agp_intel_match(device_t dev) 58 { 59 if (pci_get_class(dev) != PCIC_BRIDGE 60 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST) 61 return NULL; 62 63 if (agp_find_caps(dev) == 0) 64 return NULL; 65 66 switch (pci_get_devid(dev)) { 67 /* Intel -- vendor 0x8086 */ 68 case 0x71808086: 69 return ("Intel 82443LX (440 LX) host to PCI bridge"); 70 71 case 0x71908086: 72 return ("Intel 82443BX (440 BX) host to PCI bridge"); 73 74 case 0x71a08086: 75 return ("Intel 82443GX host to PCI bridge"); 76 77 case 0x71a18086: 78 return ("Intel 82443GX host to AGP bridge"); 79 80 case 0x11308086: 81 return ("Intel 82815 (i815 GMCH) host to PCI bridge"); 82 83 case 0x25008086: 84 return ("Intel 82820 host to AGP bridge"); 85 86 case 0x1a218086: 87 return ("Intel 82840 host to AGP bridge"); 88 89 case 0x1a308086: 90 return ("Intel 82845 host to AGP bridge"); 91 92 case 0x25308086: 93 return ("Intel 82850 host to AGP bridge"); 94 95 case 0x25318086: 96 return ("Intel 82860 host to AGP bridge"); 97 }; 98 99 if (pci_get_vendor(dev) == 0x8086) 100 return ("Intel Generic host to PCI bridge"); 101 102 return NULL; 103 } 104 105 static int 106 agp_intel_probe(device_t dev) 107 { 108 const char *desc; 109 110 desc = agp_intel_match(dev); 111 if (desc) { 112 device_verbose(dev); 113 device_set_desc(dev, desc); 114 return 0; 115 } 116 117 return ENXIO; 118 } 119 120 static int 121 agp_intel_attach(device_t dev) 122 { 123 struct agp_intel_softc *sc = device_get_softc(dev); 124 struct agp_gatt *gatt; 125 u_int32_t type = pci_get_devid(dev); 126 int error; 127 128 error = agp_generic_attach(dev); 129 if (error) 130 return error; 131 132 sc->initial_aperture = AGP_GET_APERTURE(dev); 133 134 for (;;) { 135 gatt = agp_alloc_gatt(dev); 136 if (gatt) 137 break; 138 139 /* 140 * Probably contigmalloc failure. Try reducing the 141 * aperture so that the gatt size reduces. 142 */ 143 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) { 144 agp_generic_detach(dev); 145 return ENOMEM; 146 } 147 } 148 sc->gatt = gatt; 149 150 /* Install the gatt. */ 151 pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4); 152 153 /* Enable things, clear errors etc. */ 154 switch (type) { 155 case 0x1a218086: /* i840 */ 156 case 0x25308086: /* i850 */ 157 case 0x25318086: /* i860 */ 158 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4); 159 pci_write_config(dev, AGP_INTEL_MCHCFG, 160 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 161 | (1 << 9)), 2); 162 break; 163 164 case 0x25008086: /* i820 */ 165 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4); 166 pci_write_config(dev, AGP_INTEL_I820_RDCR, 167 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 168 | (1 << 1)), 1); 169 break; 170 171 case 0x1a308086: /* i845 */ 172 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0000, 4); 173 pci_write_config(dev, AGP_INTEL_I845_MCHCFG, 174 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 175 | (1 << 1)), 1); 176 break; 177 178 default: /* Intel Generic (maybe) */ 179 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4); 180 pci_write_config(dev, AGP_INTEL_NBXCFG, 181 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 182 & ~(1 << 10)) | (1 << 9), 4); 183 } 184 185 switch (type) { 186 case 0x1a218086: /* i840 */ 187 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2); 188 break; 189 190 case 0x25008086: /* i820 */ 191 case 0x1a308086: /* i845 */ 192 case 0x25308086: /* i850 */ 193 case 0x25318086: /* i860 */ 194 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x001c, 2); 195 break; 196 197 default: /* Intel Generic (maybe) */ 198 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1); 199 } 200 201 return 0; 202 } 203 204 static int 205 agp_intel_detach(device_t dev) 206 { 207 struct agp_intel_softc *sc = device_get_softc(dev); 208 u_int32_t type = pci_get_devid(dev); 209 int error; 210 211 error = agp_generic_detach(dev); 212 if (error) 213 return error; 214 215 switch (type) { 216 case 0x1a218086: /* i840 */ 217 case 0x25308086: /* i850 */ 218 case 0x25318086: /* i860 */ 219 printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned) 220 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 221 & ~(1 << 9))); 222 pci_write_config(dev, AGP_INTEL_MCHCFG, 223 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 224 & ~(1 << 9)), 2); 225 226 case 0x25008086: /* i820 */ 227 printf("%s: set RDCR to %x\n", __FUNCTION__, (unsigned) 228 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 229 & ~(1 << 1))); 230 pci_write_config(dev, AGP_INTEL_I820_RDCR, 231 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 232 & ~(1 << 1)), 1); 233 234 case 0x1a308086: /* i845 */ 235 printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned) 236 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 237 & ~(1 << 1))); 238 pci_write_config(dev, AGP_INTEL_MCHCFG, 239 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 240 & ~(1 << 1)), 1); 241 242 default: /* Intel Generic (maybe) */ 243 printf("%s: set NBXCFG to %x\n", __FUNCTION__, 244 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 245 & ~(1 << 9))); 246 pci_write_config(dev, AGP_INTEL_NBXCFG, 247 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 248 & ~(1 << 9)), 4); 249 } 250 pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4); 251 AGP_SET_APERTURE(dev, sc->initial_aperture); 252 agp_free_gatt(sc->gatt); 253 254 return 0; 255 } 256 257 static u_int32_t 258 agp_intel_get_aperture(device_t dev) 259 { 260 u_int32_t apsize; 261 262 apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & 0x1f; 263 264 /* 265 * The size is determined by the number of low bits of 266 * register APBASE which are forced to zero. The low 22 bits 267 * are always forced to zero and each zero bit in the apsize 268 * field just read forces the corresponding bit in the 27:22 269 * to be zero. We calculate the aperture size accordingly. 270 */ 271 return (((apsize ^ 0x1f) << 22) | ((1 << 22) - 1)) + 1; 272 } 273 274 static int 275 agp_intel_set_aperture(device_t dev, u_int32_t aperture) 276 { 277 u_int32_t apsize; 278 279 /* 280 * Reverse the magic from get_aperture. 281 */ 282 apsize = ((aperture - 1) >> 22) ^ 0x1f; 283 284 /* 285 * Double check for sanity. 286 */ 287 if ((((apsize ^ 0x1f) << 22) | ((1 << 22) - 1)) + 1 != aperture) 288 return EINVAL; 289 290 pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1); 291 292 return 0; 293 } 294 295 static int 296 agp_intel_bind_page(device_t dev, int offset, vm_offset_t physical) 297 { 298 struct agp_intel_softc *sc = device_get_softc(dev); 299 300 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 301 return EINVAL; 302 303 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 304 return 0; 305 } 306 307 static int 308 agp_intel_unbind_page(device_t dev, int offset) 309 { 310 struct agp_intel_softc *sc = device_get_softc(dev); 311 312 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 313 return EINVAL; 314 315 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 316 return 0; 317 } 318 319 static void 320 agp_intel_flush_tlb(device_t dev) 321 { 322 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2200, 4); 323 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4); 324 } 325 326 static device_method_t agp_intel_methods[] = { 327 /* Device interface */ 328 DEVMETHOD(device_probe, agp_intel_probe), 329 DEVMETHOD(device_attach, agp_intel_attach), 330 DEVMETHOD(device_detach, agp_intel_detach), 331 DEVMETHOD(device_shutdown, bus_generic_shutdown), 332 DEVMETHOD(device_suspend, bus_generic_suspend), 333 DEVMETHOD(device_resume, bus_generic_resume), 334 335 /* AGP interface */ 336 DEVMETHOD(agp_get_aperture, agp_intel_get_aperture), 337 DEVMETHOD(agp_set_aperture, agp_intel_set_aperture), 338 DEVMETHOD(agp_bind_page, agp_intel_bind_page), 339 DEVMETHOD(agp_unbind_page, agp_intel_unbind_page), 340 DEVMETHOD(agp_flush_tlb, agp_intel_flush_tlb), 341 DEVMETHOD(agp_enable, agp_generic_enable), 342 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 343 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 344 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 345 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 346 347 { 0, 0 } 348 }; 349 350 static driver_t agp_intel_driver = { 351 "agp", 352 agp_intel_methods, 353 sizeof(struct agp_intel_softc), 354 }; 355 356 static devclass_t agp_devclass; 357 358 DRIVER_MODULE(agp_intel, pci, agp_intel_driver, agp_devclass, 0, 0); 359