1 /*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include "opt_bus.h" 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/lock.h> 37 #include <sys/lockmgr.h> 38 #include <sys/mutex.h> 39 #include <sys/proc.h> 40 41 #include <pci/pcivar.h> 42 #include <pci/pcireg.h> 43 #include <pci/agppriv.h> 44 #include <pci/agpreg.h> 45 46 #include <vm/vm.h> 47 #include <vm/vm_object.h> 48 #include <vm/pmap.h> 49 50 struct agp_intel_softc { 51 struct agp_softc agp; 52 u_int32_t initial_aperture; /* aperture size at startup */ 53 struct agp_gatt *gatt; 54 }; 55 56 static const char* 57 agp_intel_match(device_t dev) 58 { 59 if (pci_get_class(dev) != PCIC_BRIDGE 60 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST) 61 return NULL; 62 63 if (agp_find_caps(dev) == 0) 64 return NULL; 65 66 switch (pci_get_devid(dev)) { 67 /* Intel -- vendor 0x8086 */ 68 case 0x71808086: 69 return ("Intel 82443LX (440 LX) host to PCI bridge"); 70 71 case 0x71908086: 72 return ("Intel 82443BX (440 BX) host to PCI bridge"); 73 74 case 0x71a08086: 75 return ("Intel 82443GX host to PCI bridge"); 76 77 case 0x71a18086: 78 return ("Intel 82443GX host to AGP bridge"); 79 80 case 0x11308086: 81 return ("Intel 82815 (i815 GMCH) host to PCI bridge"); 82 83 case 0x25008086: 84 case 0x25018086: 85 return ("Intel 82820 host to AGP bridge"); 86 87 case 0x35758086: 88 return ("Intel 82830 host to AGP bridge"); 89 90 case 0x1a218086: 91 return ("Intel 82840 host to AGP bridge"); 92 93 case 0x1a308086: 94 return ("Intel 82845 host to AGP bridge"); 95 96 case 0x25308086: 97 return ("Intel 82850 host to AGP bridge"); 98 99 case 0x25318086: 100 return ("Intel 82860 host to AGP bridge"); 101 }; 102 103 if (pci_get_vendor(dev) == 0x8086) 104 return ("Intel Generic host to PCI bridge"); 105 106 return NULL; 107 } 108 109 static int 110 agp_intel_probe(device_t dev) 111 { 112 const char *desc; 113 114 desc = agp_intel_match(dev); 115 if (desc) { 116 device_verbose(dev); 117 device_set_desc(dev, desc); 118 return 0; 119 } 120 121 return ENXIO; 122 } 123 124 static int 125 agp_intel_attach(device_t dev) 126 { 127 struct agp_intel_softc *sc = device_get_softc(dev); 128 struct agp_gatt *gatt; 129 u_int32_t type = pci_get_devid(dev); 130 int error; 131 132 error = agp_generic_attach(dev); 133 if (error) 134 return error; 135 136 sc->initial_aperture = AGP_GET_APERTURE(dev); 137 138 for (;;) { 139 gatt = agp_alloc_gatt(dev); 140 if (gatt) 141 break; 142 143 /* 144 * Probably contigmalloc failure. Try reducing the 145 * aperture so that the gatt size reduces. 146 */ 147 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) { 148 agp_generic_detach(dev); 149 return ENOMEM; 150 } 151 } 152 sc->gatt = gatt; 153 154 /* Install the gatt. */ 155 pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4); 156 157 /* Enable the GLTB and setup the control register. */ 158 switch (type) { 159 case 0x71908086: /* 440LX/EX */ 160 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2080, 4); 161 break; 162 case 0x71808086: /* 440BX */ 163 /* 164 * XXX: Should be 0xa080? Bit 9 is undefined, and 165 * bit 13 being on and bit 15 being clear is illegal. 166 */ 167 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4); 168 break; 169 default: 170 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x0080, 4); 171 } 172 173 /* Enable things, clear errors etc. */ 174 switch (type) { 175 case 0x1a218086: /* i840 */ 176 case 0x25308086: /* i850 */ 177 case 0x25318086: /* i860 */ 178 pci_write_config(dev, AGP_INTEL_MCHCFG, 179 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 180 | (1 << 9)), 2); 181 break; 182 183 case 0x25008086: /* i820 */ 184 case 0x25018086: /* i820 */ 185 pci_write_config(dev, AGP_INTEL_I820_RDCR, 186 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 187 | (1 << 1)), 1); 188 break; 189 190 case 0x1a308086: /* i845 */ 191 pci_write_config(dev, AGP_INTEL_I845_MCHCFG, 192 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 193 | (1 << 1)), 1); 194 break; 195 196 default: /* Intel Generic (maybe) */ 197 pci_write_config(dev, AGP_INTEL_NBXCFG, 198 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 199 & ~(1 << 10)) | (1 << 9), 4); 200 } 201 202 switch (type) { 203 case 0x1a218086: /* i840 */ 204 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2); 205 break; 206 207 case 0x25008086: /* i820 */ 208 case 0x25018086: /* i820 */ 209 case 0x1a308086: /* i845 */ 210 case 0x25308086: /* i850 */ 211 case 0x25318086: /* i860 */ 212 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x001c, 2); 213 break; 214 215 default: /* Intel Generic (maybe) */ 216 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1); 217 } 218 219 return 0; 220 } 221 222 static int 223 agp_intel_detach(device_t dev) 224 { 225 struct agp_intel_softc *sc = device_get_softc(dev); 226 u_int32_t type = pci_get_devid(dev); 227 int error; 228 229 error = agp_generic_detach(dev); 230 if (error) 231 return error; 232 233 switch (type) { 234 case 0x1a218086: /* i840 */ 235 case 0x25308086: /* i850 */ 236 case 0x25318086: /* i860 */ 237 printf("%s: set MCHCFG to %x\n", __func__, (unsigned) 238 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 239 & ~(1 << 9))); 240 pci_write_config(dev, AGP_INTEL_MCHCFG, 241 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 242 & ~(1 << 9)), 2); 243 244 case 0x25008086: /* i820 */ 245 case 0x25018086: /* i820 */ 246 printf("%s: set RDCR to %x\n", __func__, (unsigned) 247 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 248 & ~(1 << 1))); 249 pci_write_config(dev, AGP_INTEL_I820_RDCR, 250 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 251 & ~(1 << 1)), 1); 252 253 case 0x1a308086: /* i845 */ 254 printf("%s: set MCHCFG to %x\n", __func__, (unsigned) 255 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 256 & ~(1 << 1))); 257 pci_write_config(dev, AGP_INTEL_MCHCFG, 258 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1) 259 & ~(1 << 1)), 1); 260 261 default: /* Intel Generic (maybe) */ 262 printf("%s: set NBXCFG to %x\n", __func__, 263 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 264 & ~(1 << 9))); 265 pci_write_config(dev, AGP_INTEL_NBXCFG, 266 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 267 & ~(1 << 9)), 4); 268 } 269 pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4); 270 AGP_SET_APERTURE(dev, sc->initial_aperture); 271 agp_free_gatt(sc->gatt); 272 273 return 0; 274 } 275 276 static u_int32_t 277 agp_intel_get_aperture(device_t dev) 278 { 279 u_int32_t apsize; 280 281 apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & 0x1f; 282 283 /* 284 * The size is determined by the number of low bits of 285 * register APBASE which are forced to zero. The low 22 bits 286 * are always forced to zero and each zero bit in the apsize 287 * field just read forces the corresponding bit in the 27:22 288 * to be zero. We calculate the aperture size accordingly. 289 */ 290 return (((apsize ^ 0x1f) << 22) | ((1 << 22) - 1)) + 1; 291 } 292 293 static int 294 agp_intel_set_aperture(device_t dev, u_int32_t aperture) 295 { 296 u_int32_t apsize; 297 298 /* 299 * Reverse the magic from get_aperture. 300 */ 301 apsize = ((aperture - 1) >> 22) ^ 0x1f; 302 303 /* 304 * Double check for sanity. 305 */ 306 if ((((apsize ^ 0x1f) << 22) | ((1 << 22) - 1)) + 1 != aperture) 307 return EINVAL; 308 309 pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1); 310 311 return 0; 312 } 313 314 static int 315 agp_intel_bind_page(device_t dev, int offset, vm_offset_t physical) 316 { 317 struct agp_intel_softc *sc = device_get_softc(dev); 318 319 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 320 return EINVAL; 321 322 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 323 return 0; 324 } 325 326 static int 327 agp_intel_unbind_page(device_t dev, int offset) 328 { 329 struct agp_intel_softc *sc = device_get_softc(dev); 330 331 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 332 return EINVAL; 333 334 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 335 return 0; 336 } 337 338 static void 339 agp_intel_flush_tlb(device_t dev) 340 { 341 u_int32_t val; 342 343 val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 344 pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 8), 4); 345 pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4); 346 } 347 348 static device_method_t agp_intel_methods[] = { 349 /* Device interface */ 350 DEVMETHOD(device_probe, agp_intel_probe), 351 DEVMETHOD(device_attach, agp_intel_attach), 352 DEVMETHOD(device_detach, agp_intel_detach), 353 DEVMETHOD(device_shutdown, bus_generic_shutdown), 354 DEVMETHOD(device_suspend, bus_generic_suspend), 355 DEVMETHOD(device_resume, bus_generic_resume), 356 357 /* AGP interface */ 358 DEVMETHOD(agp_get_aperture, agp_intel_get_aperture), 359 DEVMETHOD(agp_set_aperture, agp_intel_set_aperture), 360 DEVMETHOD(agp_bind_page, agp_intel_bind_page), 361 DEVMETHOD(agp_unbind_page, agp_intel_unbind_page), 362 DEVMETHOD(agp_flush_tlb, agp_intel_flush_tlb), 363 DEVMETHOD(agp_enable, agp_generic_enable), 364 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 365 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 366 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 367 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 368 369 { 0, 0 } 370 }; 371 372 static driver_t agp_intel_driver = { 373 "agp", 374 agp_intel_methods, 375 sizeof(struct agp_intel_softc), 376 }; 377 378 static devclass_t agp_devclass; 379 380 DRIVER_MODULE(agp_intel, pci, agp_intel_driver, agp_devclass, 0, 0); 381 MODULE_DEPEND(agp_intel, agp, 1, 1, 1); 382 MODULE_DEPEND(agp_intel, pci, 1, 1, 1); 383