xref: /freebsd/sys/dev/agp/agp_intel.c (revision 2bc6540439d0932b38067c9cc321fa0e2a61f264)
1 /*-
2  * Copyright (c) 2000 Doug Rabson
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  */
26 
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29 
30 #include "opt_bus.h"
31 
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/malloc.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/bus.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <sys/proc.h>
41 
42 #include <dev/pci/pcivar.h>
43 #include <dev/pci/pcireg.h>
44 #include <pci/agppriv.h>
45 #include <pci/agpreg.h>
46 
47 #include <vm/vm.h>
48 #include <vm/vm_object.h>
49 #include <vm/pmap.h>
50 
51 #define	MAX_APSIZE	0x3f		/* 256 MB */
52 
53 struct agp_intel_softc {
54 	struct agp_softc agp;
55 	u_int32_t	initial_aperture; /* aperture size at startup */
56 	struct agp_gatt *gatt;
57 	u_int		aperture_mask;
58 };
59 
60 static const char*
61 agp_intel_match(device_t dev)
62 {
63 	if (pci_get_class(dev) != PCIC_BRIDGE
64 	    || pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
65 		return NULL;
66 
67 	if (agp_find_caps(dev) == 0)
68 		return NULL;
69 
70 	switch (pci_get_devid(dev)) {
71 	/* Intel -- vendor 0x8086 */
72 	case 0x71808086:
73 		return ("Intel 82443LX (440 LX) host to PCI bridge");
74 
75 	case 0x71908086:
76 		return ("Intel 82443BX (440 BX) host to PCI bridge");
77 
78  	case 0x71a08086:
79  		return ("Intel 82443GX host to PCI bridge");
80 
81  	case 0x71a18086:
82  		return ("Intel 82443GX host to AGP bridge");
83 
84 	case 0x11308086:
85 		return ("Intel 82815 (i815 GMCH) host to PCI bridge");
86 
87 	case 0x25008086:
88 	case 0x25018086:
89 		return ("Intel 82820 host to AGP bridge");
90 
91 	case 0x35758086:
92 		return ("Intel 82830 host to AGP bridge");
93 
94 	case 0x1a218086:
95 		return ("Intel 82840 host to AGP bridge");
96 
97 	case 0x1a308086:
98 		return ("Intel 82845 host to AGP bridge");
99 
100 	case 0x25308086:
101 		return ("Intel 82850 host to AGP bridge");
102 
103 	case 0x33408086:
104 		return ("Intel 82855 host to AGP bridge");
105 
106 	case 0x25318086:
107 		return ("Intel 82860 host to AGP bridge");
108 
109 	case 0x25708086:
110 		return ("Intel 82865 host to AGP bridge");
111 
112 	case 0x255d8086:
113 		return ("Intel E7205 host to AGP bridge");
114 
115 	case 0x25788086:
116 		return ("Intel 82875P host to AGP bridge");
117 
118 	case 0x25608086:
119 		return ("Intel 82845G host to AGP bridge");
120 
121 	case 0x35808086:
122 		return ("Intel 82855GM host to AGP bridge");
123 	};
124 
125 	return NULL;
126 }
127 
128 static int
129 agp_intel_probe(device_t dev)
130 {
131 	const char *desc;
132 
133 	if (resource_disabled("agp", device_get_unit(dev)))
134 		return (ENXIO);
135 	desc = agp_intel_match(dev);
136 	if (desc) {
137 		device_set_desc(dev, desc);
138 		return BUS_PROBE_DEFAULT;
139 	}
140 
141 	return ENXIO;
142 }
143 
144 static int
145 agp_intel_attach(device_t dev)
146 {
147 	struct agp_intel_softc *sc = device_get_softc(dev);
148 	struct agp_gatt *gatt;
149 	u_int32_t type = pci_get_devid(dev);
150 	u_int32_t value;
151 	int error;
152 
153 	error = agp_generic_attach(dev);
154 	if (error)
155 		return error;
156 
157 	/* Determine maximum supported aperture size. */
158 	value = pci_read_config(dev, AGP_INTEL_APSIZE, 1);
159 	pci_write_config(dev, AGP_INTEL_APSIZE, MAX_APSIZE, 1);
160 	sc->aperture_mask = pci_read_config(dev, AGP_INTEL_APSIZE, 1) &
161 	    MAX_APSIZE;
162 	pci_write_config(dev, AGP_INTEL_APSIZE, value, 1);
163 	sc->initial_aperture = AGP_GET_APERTURE(dev);
164 
165 	for (;;) {
166 		gatt = agp_alloc_gatt(dev);
167 		if (gatt)
168 			break;
169 
170 		/*
171 		 * Probably contigmalloc failure. Try reducing the
172 		 * aperture so that the gatt size reduces.
173 		 */
174 		if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
175 			agp_generic_detach(dev);
176 			return ENOMEM;
177 		}
178 	}
179 	sc->gatt = gatt;
180 
181 	/* Install the gatt. */
182 	pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4);
183 
184 	/* Enable the GLTB and setup the control register. */
185 	switch (type) {
186 	case 0x71908086: /* 440LX/EX */
187 		pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2080, 4);
188 		break;
189 	case 0x71808086: /* 440BX */
190 		/*
191 		 * XXX: Should be 0xa080?  Bit 9 is undefined, and
192 		 * bit 13 being on and bit 15 being clear is illegal.
193 		 */
194 		pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);
195 		break;
196 	default:
197 		value = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4);
198 		pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4);
199 	}
200 
201 	/* Enable things, clear errors etc. */
202 	switch (type) {
203 	case 0x1a218086: /* i840 */
204 	case 0x25308086: /* i850 */
205 	case 0x25318086: /* i860 */
206 		pci_write_config(dev, AGP_INTEL_MCHCFG,
207 				 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
208 				  | (1 << 9)), 2);
209 		break;
210 
211 	case 0x25008086: /* i820 */
212 	case 0x25018086: /* i820 */
213 		pci_write_config(dev, AGP_INTEL_I820_RDCR,
214 				 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
215 				  | (1 << 1)), 1);
216 		break;
217 
218 	case 0x1a308086: /* i845 */
219 	case 0x33408086: /* i855 */
220 	case 0x35808086: /* i855GM */
221 	case 0x255d8086: /* E7205 */
222 	case 0x25708086: /* i865 */
223 	case 0x25788086: /* i875P */
224 	case 0x25608086: /* i845G */
225 		pci_write_config(dev, AGP_INTEL_I845_MCHCFG,
226 				 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
227 				  | (1 << 1)), 1);
228 		break;
229 
230 	default: /* Intel Generic (maybe) */
231 		pci_write_config(dev, AGP_INTEL_NBXCFG,
232 				 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
233 				  & ~(1 << 10)) | (1 << 9), 4);
234 	}
235 
236 	switch (type) {
237 	case 0x1a218086: /* i840 */
238 		pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
239 		break;
240 
241 	case 0x25008086: /* i820 */
242 	case 0x25018086: /* i820 */
243 	case 0x1a308086: /* i845 */
244 	case 0x25308086: /* i850 */
245 	case 0x33408086: /* i855 */
246 	case 0x255d8086: /* E7205 */
247 	case 0x25318086: /* i860 */
248 	case 0x25708086: /* i865 */
249 	case 0x25788086: /* i875P */
250 	case 0x25608086: /* i845G */
251 		pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2);
252 		break;
253 
254 	default: /* Intel Generic (maybe) */
255 		pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
256 	}
257 
258 	return 0;
259 }
260 
261 static int
262 agp_intel_detach(device_t dev)
263 {
264 	struct agp_intel_softc *sc = device_get_softc(dev);
265 	u_int32_t type = pci_get_devid(dev);
266 	int error;
267 
268 	error = agp_generic_detach(dev);
269 	if (error)
270 		return error;
271 
272 	switch (type) {
273 	case 0x1a218086: /* i840 */
274 	case 0x25308086: /* i850 */
275 	case 0x25318086: /* i860 */
276 		printf("%s: set MCHCFG to %x\n", __func__, (unsigned)
277 				(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
278 				& ~(1 << 9)));
279 		pci_write_config(dev, AGP_INTEL_MCHCFG,
280 				(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
281 				& ~(1 << 9)), 2);
282 
283 	case 0x25008086: /* i820 */
284 	case 0x25018086: /* i820 */
285 		printf("%s: set RDCR to %x\n", __func__, (unsigned)
286 				(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
287 				& ~(1 << 1)));
288 		pci_write_config(dev, AGP_INTEL_I820_RDCR,
289 				(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
290 				& ~(1 << 1)), 1);
291 
292 	case 0x1a308086: /* i845 */
293 	case 0x25608086: /* i845G */
294 	case 0x33408086: /* i855 */
295 	case 0x35808086: /* i855GM */
296 	case 0x255d8086: /* E7205 */
297 	case 0x25708086: /* i865 */
298 	case 0x25788086: /* i875P */
299 		printf("%s: set MCHCFG to %x\n", __func__, (unsigned)
300 				(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
301 				& ~(1 << 1)));
302 		pci_write_config(dev, AGP_INTEL_MCHCFG,
303 				(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
304 				& ~(1 << 1)), 1);
305 
306 	default: /* Intel Generic (maybe) */
307 		printf("%s: set NBXCFG to %x\n", __func__,
308 				 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
309 				  & ~(1 << 9)));
310 		pci_write_config(dev, AGP_INTEL_NBXCFG,
311 				 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
312 				  & ~(1 << 9)), 4);
313 	}
314 	pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
315 	AGP_SET_APERTURE(dev, sc->initial_aperture);
316 	agp_free_gatt(sc->gatt);
317 
318 	return 0;
319 }
320 
321 static u_int32_t
322 agp_intel_get_aperture(device_t dev)
323 {
324 	struct agp_intel_softc *sc = device_get_softc(dev);
325 	u_int32_t apsize;
326 
327 	apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & sc->aperture_mask;
328 
329 	/*
330 	 * The size is determined by the number of low bits of
331 	 * register APBASE which are forced to zero. The low 22 bits
332 	 * are always forced to zero and each zero bit in the apsize
333 	 * field just read forces the corresponding bit in the 27:22
334 	 * to be zero. We calculate the aperture size accordingly.
335 	 */
336 	return (((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1;
337 }
338 
339 static int
340 agp_intel_set_aperture(device_t dev, u_int32_t aperture)
341 {
342 	struct agp_intel_softc *sc = device_get_softc(dev);
343 	u_int32_t apsize;
344 
345 	/*
346 	 * Reverse the magic from get_aperture.
347 	 */
348 	apsize = ((aperture - 1) >> 22) ^ sc->aperture_mask;
349 
350 	/*
351 	 * Double check for sanity.
352 	 */
353 	if ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1 != aperture)
354 		return EINVAL;
355 
356 	pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1);
357 
358 	return 0;
359 }
360 
361 static int
362 agp_intel_bind_page(device_t dev, int offset, vm_offset_t physical)
363 {
364 	struct agp_intel_softc *sc = device_get_softc(dev);
365 
366 	if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
367 		return EINVAL;
368 
369 	sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17;
370 	return 0;
371 }
372 
373 static int
374 agp_intel_unbind_page(device_t dev, int offset)
375 {
376 	struct agp_intel_softc *sc = device_get_softc(dev);
377 
378 	if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
379 		return EINVAL;
380 
381 	sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
382 	return 0;
383 }
384 
385 static void
386 agp_intel_flush_tlb(device_t dev)
387 {
388 	u_int32_t val;
389 
390 	val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4);
391 	pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 7), 4);
392 	pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4);
393 }
394 
395 static device_method_t agp_intel_methods[] = {
396 	/* Device interface */
397 	DEVMETHOD(device_probe,		agp_intel_probe),
398 	DEVMETHOD(device_attach,	agp_intel_attach),
399 	DEVMETHOD(device_detach,	agp_intel_detach),
400 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
401 	DEVMETHOD(device_suspend,	bus_generic_suspend),
402 	DEVMETHOD(device_resume,	bus_generic_resume),
403 
404 	/* AGP interface */
405 	DEVMETHOD(agp_get_aperture,	agp_intel_get_aperture),
406 	DEVMETHOD(agp_set_aperture,	agp_intel_set_aperture),
407 	DEVMETHOD(agp_bind_page,	agp_intel_bind_page),
408 	DEVMETHOD(agp_unbind_page,	agp_intel_unbind_page),
409 	DEVMETHOD(agp_flush_tlb,	agp_intel_flush_tlb),
410 	DEVMETHOD(agp_enable,		agp_generic_enable),
411 	DEVMETHOD(agp_alloc_memory,	agp_generic_alloc_memory),
412 	DEVMETHOD(agp_free_memory,	agp_generic_free_memory),
413 	DEVMETHOD(agp_bind_memory,	agp_generic_bind_memory),
414 	DEVMETHOD(agp_unbind_memory,	agp_generic_unbind_memory),
415 
416 	{ 0, 0 }
417 };
418 
419 static driver_t agp_intel_driver = {
420 	"agp",
421 	agp_intel_methods,
422 	sizeof(struct agp_intel_softc),
423 };
424 
425 static devclass_t agp_devclass;
426 
427 DRIVER_MODULE(agp_intel, hostb, agp_intel_driver, agp_devclass, 0, 0);
428 MODULE_DEPEND(agp_intel, agp, 1, 1, 1);
429 MODULE_DEPEND(agp_intel, pci, 1, 1, 1);
430