1 /*- 2 * Copyright (c) 2000 Doug Rabson 3 * Copyright (c) 2000 Ruslan Ermilov 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * Fixes for 830/845G support: David Dawes <dawes@xfree86.org> 30 * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org> 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include "opt_bus.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/module.h> 43 #include <sys/bus.h> 44 #include <sys/lock.h> 45 #include <sys/mutex.h> 46 #include <sys/proc.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <pci/agppriv.h> 51 #include <pci/agpreg.h> 52 53 #include <vm/vm.h> 54 #include <vm/vm_object.h> 55 #include <vm/vm_page.h> 56 #include <vm/vm_pageout.h> 57 #include <vm/pmap.h> 58 59 #include <machine/bus.h> 60 #include <machine/resource.h> 61 #include <sys/rman.h> 62 63 MALLOC_DECLARE(M_AGP); 64 65 #define READ1(off) bus_space_read_1(sc->bst, sc->bsh, off) 66 #define READ4(off) bus_space_read_4(sc->bst, sc->bsh, off) 67 #define WRITE4(off,v) bus_space_write_4(sc->bst, sc->bsh, off, v) 68 #define WRITEGTT(off,v) bus_space_write_4(sc->gtt_bst, sc->gtt_bsh, off, v) 69 70 #define CHIP_I810 0 /* i810/i815 */ 71 #define CHIP_I830 1 /* 830M/845G */ 72 #define CHIP_I855 2 /* 852GM/855GM/865G */ 73 #define CHIP_I915 3 /* 915G/915GM */ 74 75 struct agp_i810_softc { 76 struct agp_softc agp; 77 u_int32_t initial_aperture; /* aperture size at startup */ 78 struct agp_gatt *gatt; 79 int chiptype; /* i810-like or i830 */ 80 u_int32_t dcache_size; /* i810 only */ 81 u_int32_t stolen; /* number of i830/845 gtt entries for stolen memory */ 82 device_t bdev; /* bridge device */ 83 84 struct resource *regs; /* memory mapped GC registers */ 85 bus_space_tag_t bst; /* bus_space tag */ 86 bus_space_handle_t bsh; /* bus_space handle */ 87 88 struct resource *gtt; /* memory mapped GATT entries */ 89 bus_space_tag_t gtt_bst; /* bus_space tag */ 90 bus_space_handle_t gtt_bsh; /* bus_space handle */ 91 92 struct resource *gm; /* unmapped (but allocated) aperture */ 93 94 void *argb_cursor; /* contigmalloc area for ARGB cursor */ 95 }; 96 97 /* For adding new devices, devid is the id of the graphics controller 98 * (pci:0:2:0, for example). The placeholder (usually at pci:0:2:1) for the 99 * second head should never be added. The bridge_offset is the offset to 100 * subtract from devid to get the id of the hostb that the device is on. 101 */ 102 static const struct agp_i810_match { 103 int devid; 104 int chiptype; 105 int bridge_offset; 106 char *name; 107 } agp_i810_matches[] = { 108 {0x71218086, CHIP_I810, 0x00010000, 109 "Intel 82810 (i810 GMCH) SVGA controller"}, 110 {0x71238086, CHIP_I810, 0x00010000, 111 "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller"}, 112 {0x71258086, CHIP_I810, 0x00010000, 113 "Intel 82810E (i810E GMCH) SVGA controller"}, 114 {0x11328086, CHIP_I810, 0x00020000, 115 "Intel 82815 (i815 GMCH) SVGA controller"}, 116 {0x35778086, CHIP_I830, 0x00020000, 117 "Intel 82830M (830M GMCH) SVGA controller"}, 118 {0x35828086, CHIP_I855, 0x00020000, 119 "Intel 82852/5"}, 120 {0x25728086, CHIP_I855, 0x00020000, 121 "Intel 82865G (865G GMCH) SVGA controller"}, 122 {0x25828086, CHIP_I915, 0x00020000, 123 "Intel 82915G (915G GMCH) SVGA controller"}, 124 {0x25928086, CHIP_I915, 0x00020000, 125 "Intel 82915GM (915GM GMCH) SVGA controller"}, 126 {0x27728086, CHIP_I915, 0x00020000, 127 "Intel 82945G (945G GMCH) SVGA controller"}, 128 {0x27A28086, CHIP_I915, 0x00020000, 129 "Intel 82945GM (945GM GMCH) SVGA controller"}, 130 {0, 0, 0, NULL} 131 }; 132 133 static const struct agp_i810_match* 134 agp_i810_match(device_t dev) 135 { 136 int i, devid; 137 138 if (pci_get_class(dev) != PCIC_DISPLAY 139 || pci_get_subclass(dev) != PCIS_DISPLAY_VGA) 140 return NULL; 141 142 devid = pci_get_devid(dev); 143 for (i = 0; agp_i810_matches[i].devid != 0; i++) { 144 if (agp_i810_matches[i].devid == devid) 145 break; 146 } 147 if (agp_i810_matches[i].devid == 0) 148 return NULL; 149 else 150 return &agp_i810_matches[i]; 151 } 152 153 /* 154 * Find bridge device. 155 */ 156 static device_t 157 agp_i810_find_bridge(device_t dev) 158 { 159 device_t *children, child; 160 int nchildren, i; 161 u_int32_t devid; 162 const struct agp_i810_match *match; 163 164 match = agp_i810_match(dev); 165 devid = match->devid - match->bridge_offset; 166 167 if (device_get_children(device_get_parent(device_get_parent(dev)), 168 &children, &nchildren)) 169 return 0; 170 171 for (i = 0; i < nchildren; i++) { 172 child = children[i]; 173 174 if (pci_get_devid(child) == devid) { 175 free(children, M_TEMP); 176 return child; 177 } 178 } 179 free(children, M_TEMP); 180 return 0; 181 } 182 183 static void 184 agp_i810_identify(driver_t *driver, device_t parent) 185 { 186 187 if (device_find_child(parent, "agp", -1) == NULL && 188 agp_i810_match(parent)) 189 device_add_child(parent, "agp", -1); 190 } 191 192 static int 193 agp_i810_probe(device_t dev) 194 { 195 device_t bdev; 196 const struct agp_i810_match *match; 197 198 if (resource_disabled("agp", device_get_unit(dev))) 199 return (ENXIO); 200 match = agp_i810_match(dev); 201 if (match == NULL) 202 return ENXIO; 203 204 bdev = agp_i810_find_bridge(dev); 205 if (!bdev) { 206 if (bootverbose) 207 printf("I810: can't find bridge device\n"); 208 return ENXIO; 209 } 210 211 /* 212 * checking whether internal graphics device has been activated. 213 */ 214 if (match->chiptype == CHIP_I810) { 215 u_int8_t smram; 216 217 smram = pci_read_config(bdev, AGP_I810_SMRAM, 1); 218 if ((smram & AGP_I810_SMRAM_GMS) 219 == AGP_I810_SMRAM_GMS_DISABLED) { 220 if (bootverbose) 221 printf("I810: disabled, not probing\n"); 222 return ENXIO; 223 } 224 } else if (match->chiptype == CHIP_I830 || 225 match->chiptype == CHIP_I855) { 226 unsigned int gcc1; 227 228 gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1); 229 if ((gcc1 & AGP_I830_GCC1_DEV2) == 230 AGP_I830_GCC1_DEV2_DISABLED) { 231 if (bootverbose) 232 printf("I830: disabled, not probing\n"); 233 return ENXIO; 234 } 235 } else if (match->chiptype == CHIP_I915) { 236 unsigned int gcc1; 237 238 gcc1 = pci_read_config(bdev, AGP_I915_DEVEN, 4); 239 if ((gcc1 & AGP_I915_DEVEN_D2F0) == 240 AGP_I915_DEVEN_D2F0_DISABLED) { 241 if (bootverbose) 242 printf("I915: disabled, not probing\n"); 243 return ENXIO; 244 } 245 } 246 247 if (match->devid == 0x35828086) { 248 switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) { 249 case AGP_I855_GME: 250 device_set_desc(dev, 251 "Intel 82855GME (855GME GMCH) SVGA controller"); 252 break; 253 case AGP_I855_GM: 254 device_set_desc(dev, 255 "Intel 82855GM (855GM GMCH) SVGA controller"); 256 break; 257 case AGP_I852_GME: 258 device_set_desc(dev, 259 "Intel 82852GME (852GME GMCH) SVGA controller"); 260 break; 261 case AGP_I852_GM: 262 device_set_desc(dev, 263 "Intel 82852GM (852GM GMCH) SVGA controller"); 264 break; 265 default: 266 device_set_desc(dev, 267 "Intel 8285xM (85xGM GMCH) SVGA controller"); 268 break; 269 } 270 } else { 271 device_set_desc(dev, match->name); 272 } 273 274 return BUS_PROBE_DEFAULT; 275 } 276 277 static int 278 agp_i810_attach(device_t dev) 279 { 280 struct agp_i810_softc *sc = device_get_softc(dev); 281 struct agp_gatt *gatt; 282 const struct agp_i810_match *match; 283 int error, rid; 284 285 sc->bdev = agp_i810_find_bridge(dev); 286 if (!sc->bdev) 287 return ENOENT; 288 289 error = agp_generic_attach(dev); 290 if (error) 291 return error; 292 293 match = agp_i810_match(dev); 294 sc->chiptype = match->chiptype; 295 296 /* Same for i810 and i830 */ 297 if (sc->chiptype == CHIP_I915) 298 rid = AGP_I915_MMADR; 299 else 300 rid = AGP_I810_MMADR; 301 302 sc->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 303 RF_ACTIVE); 304 if (!sc->regs) { 305 agp_generic_detach(dev); 306 return ENODEV; 307 } 308 sc->bst = rman_get_bustag(sc->regs); 309 sc->bsh = rman_get_bushandle(sc->regs); 310 311 if (sc->chiptype == CHIP_I915) { 312 rid = AGP_I915_GTTADR; 313 sc->gtt = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 314 RF_ACTIVE); 315 if (!sc->gtt) { 316 bus_release_resource(dev, SYS_RES_MEMORY, 317 AGP_I915_MMADR, sc->regs); 318 agp_generic_detach(dev); 319 return ENODEV; 320 } 321 sc->gtt_bst = rman_get_bustag(sc->gtt); 322 sc->gtt_bsh = rman_get_bushandle(sc->gtt); 323 324 /* While agp_generic_attach allocates the AGP_APBASE resource 325 * to try to reserve the aperture, on the 915 the aperture 326 * isn't in PCIR_BAR(0), it's in PCIR_BAR(2), so it allocated 327 * the registers that we just mapped anyway. So, allocate the 328 * aperture here, which also gives us easy access to it for the 329 * agp_i810_get_aperture(). 330 */ 331 rid = AGP_I915_GMADR; 332 sc->gm = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 0); 333 if (sc->gm == NULL) { 334 bus_release_resource(dev, SYS_RES_MEMORY, 335 AGP_I915_MMADR, sc->regs); 336 bus_release_resource(dev, SYS_RES_MEMORY, 337 AGP_I915_GTTADR, sc->regs); 338 agp_generic_detach(dev); 339 return ENODEV; 340 } 341 } 342 343 sc->initial_aperture = AGP_GET_APERTURE(dev); 344 345 gatt = malloc( sizeof(struct agp_gatt), M_AGP, M_NOWAIT); 346 if (!gatt) { 347 agp_generic_detach(dev); 348 return ENOMEM; 349 } 350 sc->gatt = gatt; 351 352 gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT; 353 354 if ( sc->chiptype == CHIP_I810 ) { 355 /* Some i810s have on-chip memory called dcache */ 356 if (READ1(AGP_I810_DRT) & AGP_I810_DRT_POPULATED) 357 sc->dcache_size = 4 * 1024 * 1024; 358 else 359 sc->dcache_size = 0; 360 361 /* According to the specs the gatt on the i810 must be 64k */ 362 gatt->ag_virtual = contigmalloc( 64 * 1024, M_AGP, 0, 363 0, ~0, PAGE_SIZE, 0); 364 if (!gatt->ag_virtual) { 365 if (bootverbose) 366 device_printf(dev, "contiguous allocation failed\n"); 367 free(gatt, M_AGP); 368 agp_generic_detach(dev); 369 return ENOMEM; 370 } 371 bzero(gatt->ag_virtual, gatt->ag_entries * sizeof(u_int32_t)); 372 373 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual); 374 agp_flush_cache(); 375 /* Install the GATT. */ 376 WRITE4(AGP_I810_PGTBL_CTL, gatt->ag_physical | 1); 377 } else if ( sc->chiptype == CHIP_I830 ) { 378 /* The i830 automatically initializes the 128k gatt on boot. */ 379 unsigned int gcc1, pgtblctl; 380 381 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1); 382 switch (gcc1 & AGP_I830_GCC1_GMS) { 383 case AGP_I830_GCC1_GMS_STOLEN_512: 384 sc->stolen = (512 - 132) * 1024 / 4096; 385 break; 386 case AGP_I830_GCC1_GMS_STOLEN_1024: 387 sc->stolen = (1024 - 132) * 1024 / 4096; 388 break; 389 case AGP_I830_GCC1_GMS_STOLEN_8192: 390 sc->stolen = (8192 - 132) * 1024 / 4096; 391 break; 392 default: 393 sc->stolen = 0; 394 device_printf(dev, "unknown memory configuration, disabling\n"); 395 agp_generic_detach(dev); 396 return EINVAL; 397 } 398 if (sc->stolen > 0) 399 device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4); 400 device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024); 401 402 /* GATT address is already in there, make sure it's enabled */ 403 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 404 pgtblctl |= 1; 405 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 406 407 gatt->ag_physical = pgtblctl & ~1; 408 } else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915) { /* CHIP_I855 */ 409 unsigned int gcc1, pgtblctl, stolen; 410 411 /* Stolen memory is set up at the beginning of the aperture by 412 * the BIOS, consisting of the GATT followed by 4kb for the BIOS 413 * display. 414 */ 415 if (sc->chiptype == CHIP_I855) 416 stolen = 132; 417 else 418 stolen = 260; 419 420 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1); 421 switch (gcc1 & AGP_I855_GCC1_GMS) { 422 case AGP_I855_GCC1_GMS_STOLEN_1M: 423 sc->stolen = (1024 - stolen) * 1024 / 4096; 424 break; 425 case AGP_I855_GCC1_GMS_STOLEN_4M: 426 sc->stolen = (4096 - stolen) * 1024 / 4096; 427 break; 428 case AGP_I855_GCC1_GMS_STOLEN_8M: 429 sc->stolen = (8192 - stolen) * 1024 / 4096; 430 break; 431 case AGP_I855_GCC1_GMS_STOLEN_16M: 432 sc->stolen = (16384 - stolen) * 1024 / 4096; 433 break; 434 case AGP_I855_GCC1_GMS_STOLEN_32M: 435 sc->stolen = (32768 - stolen) * 1024 / 4096; 436 break; 437 case AGP_I915_GCC1_GMS_STOLEN_48M: 438 sc->stolen = (49152 - stolen) * 1024 / 4096; 439 break; 440 case AGP_I915_GCC1_GMS_STOLEN_64M: 441 sc->stolen = (65536 - stolen) * 1024 / 4096; 442 break; 443 default: 444 sc->stolen = 0; 445 device_printf(dev, "unknown memory configuration, disabling\n"); 446 agp_generic_detach(dev); 447 return EINVAL; 448 } 449 if (sc->stolen > 0) 450 device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4); 451 device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024); 452 453 /* GATT address is already in there, make sure it's enabled */ 454 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 455 pgtblctl |= 1; 456 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 457 458 gatt->ag_physical = pgtblctl & ~1; 459 } 460 461 return 0; 462 } 463 464 static int 465 agp_i810_detach(device_t dev) 466 { 467 struct agp_i810_softc *sc = device_get_softc(dev); 468 int error; 469 470 error = agp_generic_detach(dev); 471 if (error) 472 return error; 473 474 /* Clear the GATT base. */ 475 if ( sc->chiptype == CHIP_I810 ) { 476 WRITE4(AGP_I810_PGTBL_CTL, 0); 477 } else { 478 unsigned int pgtblctl; 479 pgtblctl = READ4(AGP_I810_PGTBL_CTL); 480 pgtblctl &= ~1; 481 WRITE4(AGP_I810_PGTBL_CTL, pgtblctl); 482 } 483 484 /* Put the aperture back the way it started. */ 485 AGP_SET_APERTURE(dev, sc->initial_aperture); 486 487 if ( sc->chiptype == CHIP_I810 ) { 488 contigfree(sc->gatt->ag_virtual, 64 * 1024, M_AGP); 489 } 490 free(sc->gatt, M_AGP); 491 492 if (sc->chiptype == CHIP_I915) { 493 bus_release_resource(dev, SYS_RES_MEMORY, AGP_I915_GMADR, 494 sc->gm); 495 bus_release_resource(dev, SYS_RES_MEMORY, AGP_I915_GTTADR, 496 sc->gtt); 497 bus_release_resource(dev, SYS_RES_MEMORY, AGP_I915_MMADR, 498 sc->regs); 499 } else { 500 bus_release_resource(dev, SYS_RES_MEMORY, AGP_I810_MMADR, 501 sc->regs); 502 } 503 504 return 0; 505 } 506 507 static u_int32_t 508 agp_i810_get_aperture(device_t dev) 509 { 510 struct agp_i810_softc *sc = device_get_softc(dev); 511 uint32_t temp; 512 u_int16_t miscc; 513 514 switch (sc->chiptype) { 515 case CHIP_I810: 516 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2); 517 if ((miscc & AGP_I810_MISCC_WINSIZE) == AGP_I810_MISCC_WINSIZE_32) 518 return 32 * 1024 * 1024; 519 else 520 return 64 * 1024 * 1024; 521 case CHIP_I830: 522 temp = pci_read_config(sc->bdev, AGP_I830_GCC1, 2); 523 if ((temp & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64) 524 return 64 * 1024 * 1024; 525 else 526 return 128 * 1024 * 1024; 527 case CHIP_I855: 528 return 128 * 1024 * 1024; 529 case CHIP_I915: 530 /* The documentation states that AGP_I915_MSAC should have bit 531 * 1 set if the aperture is 128MB instead of 256. However, 532 * that bit appears to not get set, so we instead use the 533 * aperture resource size, which should always be correct. 534 */ 535 return rman_get_size(sc->gm); 536 } 537 538 return 0; 539 } 540 541 static int 542 agp_i810_set_aperture(device_t dev, u_int32_t aperture) 543 { 544 struct agp_i810_softc *sc = device_get_softc(dev); 545 u_int16_t miscc, gcc1; 546 u_int32_t temp; 547 548 switch (sc->chiptype) { 549 case CHIP_I810: 550 /* 551 * Double check for sanity. 552 */ 553 if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) { 554 device_printf(dev, "bad aperture size %d\n", aperture); 555 return EINVAL; 556 } 557 558 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2); 559 miscc &= ~AGP_I810_MISCC_WINSIZE; 560 if (aperture == 32 * 1024 * 1024) 561 miscc |= AGP_I810_MISCC_WINSIZE_32; 562 else 563 miscc |= AGP_I810_MISCC_WINSIZE_64; 564 565 pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2); 566 break; 567 case CHIP_I830: 568 if (aperture != 64 * 1024 * 1024 && 569 aperture != 128 * 1024 * 1024) { 570 device_printf(dev, "bad aperture size %d\n", aperture); 571 return EINVAL; 572 } 573 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2); 574 gcc1 &= ~AGP_I830_GCC1_GMASIZE; 575 if (aperture == 64 * 1024 * 1024) 576 gcc1 |= AGP_I830_GCC1_GMASIZE_64; 577 else 578 gcc1 |= AGP_I830_GCC1_GMASIZE_128; 579 580 pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2); 581 break; 582 case CHIP_I855: 583 if (aperture != 128 * 1024 * 1024) { 584 device_printf(dev, "bad aperture size %d\n", aperture); 585 return EINVAL; 586 } 587 break; 588 case CHIP_I915: 589 temp = pci_read_config(dev, AGP_I915_MSAC, 1); 590 temp &= ~AGP_I915_MSAC_GMASIZE; 591 592 switch (aperture) { 593 case 128 * 1024 * 1024: 594 temp |= AGP_I915_MSAC_GMASIZE_128; 595 break; 596 case 256 * 1024 * 1024: 597 temp |= AGP_I915_MSAC_GMASIZE_256; 598 break; 599 default: 600 device_printf(dev, "bad aperture size %d\n", aperture); 601 return EINVAL; 602 } 603 604 pci_write_config(dev, AGP_I915_MSAC, temp, 1); 605 break; 606 } 607 608 return 0; 609 } 610 611 static int 612 agp_i810_bind_page(device_t dev, int offset, vm_offset_t physical) 613 { 614 struct agp_i810_softc *sc = device_get_softc(dev); 615 616 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) { 617 device_printf(dev, "failed: offset is 0x%08x, shift is %d, entries is %d\n", offset, AGP_PAGE_SHIFT, sc->gatt->ag_entries); 618 return EINVAL; 619 } 620 621 if ( sc->chiptype != CHIP_I810 ) { 622 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) { 623 device_printf(dev, "trying to bind into stolen memory"); 624 return EINVAL; 625 } 626 } 627 628 if (sc->chiptype == CHIP_I915) { 629 WRITEGTT((offset >> AGP_PAGE_SHIFT) * 4, physical | 1); 630 } else { 631 WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, physical | 1); 632 } 633 634 return 0; 635 } 636 637 static int 638 agp_i810_unbind_page(device_t dev, int offset) 639 { 640 struct agp_i810_softc *sc = device_get_softc(dev); 641 642 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 643 return EINVAL; 644 645 if ( sc->chiptype != CHIP_I810 ) { 646 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) { 647 device_printf(dev, "trying to unbind from stolen memory"); 648 return EINVAL; 649 } 650 } 651 652 if (sc->chiptype == CHIP_I915) { 653 WRITEGTT((offset >> AGP_PAGE_SHIFT) * 4, 0); 654 } else { 655 WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, 0); 656 } 657 658 return 0; 659 } 660 661 /* 662 * Writing via memory mapped registers already flushes all TLBs. 663 */ 664 static void 665 agp_i810_flush_tlb(device_t dev) 666 { 667 } 668 669 static int 670 agp_i810_enable(device_t dev, u_int32_t mode) 671 { 672 673 return 0; 674 } 675 676 static struct agp_memory * 677 agp_i810_alloc_memory(device_t dev, int type, vm_size_t size) 678 { 679 struct agp_i810_softc *sc = device_get_softc(dev); 680 struct agp_memory *mem; 681 682 if ((size & (AGP_PAGE_SIZE - 1)) != 0) 683 return 0; 684 685 if (sc->agp.as_allocated + size > sc->agp.as_maxmem) 686 return 0; 687 688 if (type == 1) { 689 /* 690 * Mapping local DRAM into GATT. 691 */ 692 if ( sc->chiptype != CHIP_I810 ) 693 return 0; 694 if (size != sc->dcache_size) 695 return 0; 696 } else if (type == 2) { 697 /* 698 * Type 2 is the contiguous physical memory type, that hands 699 * back a physical address. This is used for cursors on i810. 700 * Hand back as many single pages with physical as the user 701 * wants, but only allow one larger allocation (ARGB cursor) 702 * for simplicity. 703 */ 704 if (size != AGP_PAGE_SIZE) { 705 if (sc->argb_cursor != NULL) 706 return 0; 707 708 /* Allocate memory for ARGB cursor, if we can. */ 709 sc->argb_cursor = contigmalloc(size, M_AGP, 710 0, 0, ~0, PAGE_SIZE, 0); 711 if (sc->argb_cursor == NULL) 712 return 0; 713 } 714 } 715 716 mem = malloc(sizeof *mem, M_AGP, M_WAITOK); 717 mem->am_id = sc->agp.as_nextid++; 718 mem->am_size = size; 719 mem->am_type = type; 720 if (type != 1 && (type != 2 || size == AGP_PAGE_SIZE)) 721 mem->am_obj = vm_object_allocate(OBJT_DEFAULT, 722 atop(round_page(size))); 723 else 724 mem->am_obj = 0; 725 726 if (type == 2) { 727 if (size == AGP_PAGE_SIZE) { 728 /* 729 * Allocate and wire down the page now so that we can 730 * get its physical address. 731 */ 732 vm_page_t m; 733 734 VM_OBJECT_LOCK(mem->am_obj); 735 m = vm_page_grab(mem->am_obj, 0, VM_ALLOC_NOBUSY | 736 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_RETRY); 737 VM_OBJECT_UNLOCK(mem->am_obj); 738 mem->am_physical = VM_PAGE_TO_PHYS(m); 739 } else { 740 /* Our allocation is already nicely wired down for us. 741 * Just grab the physical address. 742 */ 743 mem->am_physical = vtophys(sc->argb_cursor); 744 } 745 } else { 746 mem->am_physical = 0; 747 } 748 749 mem->am_offset = 0; 750 mem->am_is_bound = 0; 751 TAILQ_INSERT_TAIL(&sc->agp.as_memory, mem, am_link); 752 sc->agp.as_allocated += size; 753 754 return mem; 755 } 756 757 static int 758 agp_i810_free_memory(device_t dev, struct agp_memory *mem) 759 { 760 struct agp_i810_softc *sc = device_get_softc(dev); 761 762 if (mem->am_is_bound) 763 return EBUSY; 764 765 if (mem->am_type == 2) { 766 if (mem->am_size == AGP_PAGE_SIZE) { 767 /* 768 * Unwire the page which we wired in alloc_memory. 769 */ 770 vm_page_t m; 771 772 VM_OBJECT_LOCK(mem->am_obj); 773 m = vm_page_lookup(mem->am_obj, 0); 774 VM_OBJECT_UNLOCK(mem->am_obj); 775 vm_page_lock_queues(); 776 vm_page_unwire(m, 0); 777 vm_page_unlock_queues(); 778 } else { 779 contigfree(sc->argb_cursor, mem->am_size, M_AGP); 780 sc->argb_cursor = NULL; 781 } 782 } 783 784 sc->agp.as_allocated -= mem->am_size; 785 TAILQ_REMOVE(&sc->agp.as_memory, mem, am_link); 786 if (mem->am_obj) 787 vm_object_deallocate(mem->am_obj); 788 free(mem, M_AGP); 789 return 0; 790 } 791 792 static int 793 agp_i810_bind_memory(device_t dev, struct agp_memory *mem, 794 vm_offset_t offset) 795 { 796 struct agp_i810_softc *sc = device_get_softc(dev); 797 vm_offset_t i; 798 799 /* Do some sanity checks first. */ 800 if (offset < 0 || (offset & (AGP_PAGE_SIZE - 1)) != 0 || 801 offset + mem->am_size > AGP_GET_APERTURE(dev)) { 802 device_printf(dev, "binding memory at bad offset %#x\n", 803 (int)offset); 804 return EINVAL; 805 } 806 807 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) { 808 mtx_lock(&sc->agp.as_lock); 809 if (mem->am_is_bound) { 810 mtx_unlock(&sc->agp.as_lock); 811 return EINVAL; 812 } 813 /* The memory's already wired down, just stick it in the GTT. */ 814 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 815 u_int32_t physical = mem->am_physical + i; 816 817 if (sc->chiptype == CHIP_I915) { 818 WRITEGTT(((offset + i) >> AGP_PAGE_SHIFT) * 4, 819 physical | 1); 820 } else { 821 WRITE4(AGP_I810_GTT + 822 ((offset + i) >> AGP_PAGE_SHIFT) * 4, 823 physical | 1); 824 } 825 } 826 agp_flush_cache(); 827 mem->am_offset = offset; 828 mem->am_is_bound = 1; 829 mtx_unlock(&sc->agp.as_lock); 830 return 0; 831 } 832 833 if (mem->am_type != 1) 834 return agp_generic_bind_memory(dev, mem, offset); 835 836 if ( sc->chiptype != CHIP_I810 ) 837 return EINVAL; 838 839 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 840 WRITE4(AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, 841 i | 3); 842 } 843 844 return 0; 845 } 846 847 static int 848 agp_i810_unbind_memory(device_t dev, struct agp_memory *mem) 849 { 850 struct agp_i810_softc *sc = device_get_softc(dev); 851 vm_offset_t i; 852 853 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) { 854 mtx_lock(&sc->agp.as_lock); 855 if (!mem->am_is_bound) { 856 mtx_unlock(&sc->agp.as_lock); 857 return EINVAL; 858 } 859 860 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) { 861 vm_offset_t offset = mem->am_offset; 862 863 if (sc->chiptype == CHIP_I915) { 864 WRITEGTT(((offset + i) >> AGP_PAGE_SHIFT) * 4, 865 0); 866 } else { 867 WRITE4(AGP_I810_GTT + 868 ((offset + i) >> AGP_PAGE_SHIFT) * 4, 0); 869 } 870 } 871 agp_flush_cache(); 872 mem->am_is_bound = 0; 873 mtx_unlock(&sc->agp.as_lock); 874 return 0; 875 } 876 877 if (mem->am_type != 1) 878 return agp_generic_unbind_memory(dev, mem); 879 880 if ( sc->chiptype != CHIP_I810 ) 881 return EINVAL; 882 883 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) 884 WRITE4(AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, 0); 885 886 return 0; 887 } 888 889 static device_method_t agp_i810_methods[] = { 890 /* Device interface */ 891 DEVMETHOD(device_identify, agp_i810_identify), 892 DEVMETHOD(device_probe, agp_i810_probe), 893 DEVMETHOD(device_attach, agp_i810_attach), 894 DEVMETHOD(device_detach, agp_i810_detach), 895 896 /* AGP interface */ 897 DEVMETHOD(agp_get_aperture, agp_i810_get_aperture), 898 DEVMETHOD(agp_set_aperture, agp_i810_set_aperture), 899 DEVMETHOD(agp_bind_page, agp_i810_bind_page), 900 DEVMETHOD(agp_unbind_page, agp_i810_unbind_page), 901 DEVMETHOD(agp_flush_tlb, agp_i810_flush_tlb), 902 DEVMETHOD(agp_enable, agp_i810_enable), 903 DEVMETHOD(agp_alloc_memory, agp_i810_alloc_memory), 904 DEVMETHOD(agp_free_memory, agp_i810_free_memory), 905 DEVMETHOD(agp_bind_memory, agp_i810_bind_memory), 906 DEVMETHOD(agp_unbind_memory, agp_i810_unbind_memory), 907 908 { 0, 0 } 909 }; 910 911 static driver_t agp_i810_driver = { 912 "agp", 913 agp_i810_methods, 914 sizeof(struct agp_i810_softc), 915 }; 916 917 static devclass_t agp_devclass; 918 919 DRIVER_MODULE(agp_i810, vgapci, agp_i810_driver, agp_devclass, 0, 0); 920 MODULE_DEPEND(agp_i810, agp, 1, 1, 1); 921 MODULE_DEPEND(agp_i810, pci, 1, 1, 1); 922