1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2004, 2005 Jung-uk Kim <jkim@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/malloc.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/bus.h> 35 #include <sys/lock.h> 36 #include <sys/mutex.h> 37 #include <sys/proc.h> 38 39 #include <dev/agp/agppriv.h> 40 #include <dev/agp/agpreg.h> 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcireg.h> 43 44 #include <vm/vm.h> 45 #include <vm/vm_object.h> 46 #include <vm/pmap.h> 47 #include <machine/bus.h> 48 #include <machine/resource.h> 49 #include <sys/rman.h> 50 51 /* XXX */ 52 extern void pci_cfgregwrite(int, int, int, int, uint32_t, int); 53 extern uint32_t pci_cfgregread(int, int, int, int, int); 54 55 static void agp_amd64_apbase_fixup(device_t); 56 57 static void agp_amd64_uli_init(device_t); 58 static int agp_amd64_uli_set_aperture(device_t, uint32_t); 59 60 static int agp_amd64_nvidia_match(uint16_t); 61 static void agp_amd64_nvidia_init(device_t); 62 static int agp_amd64_nvidia_set_aperture(device_t, uint32_t); 63 64 static int agp_amd64_via_match(void); 65 static void agp_amd64_via_init(device_t); 66 static int agp_amd64_via_set_aperture(device_t, uint32_t); 67 68 MALLOC_DECLARE(M_AGP); 69 70 #define AMD64_MAX_MCTRL 8 71 72 struct agp_amd64_softc { 73 struct agp_softc agp; 74 uint32_t initial_aperture; 75 struct agp_gatt *gatt; 76 uint32_t apbase; 77 int mctrl[AMD64_MAX_MCTRL]; 78 int n_mctrl; 79 int via_agp; 80 }; 81 82 static const char* 83 agp_amd64_match(device_t dev) 84 { 85 if (pci_get_class(dev) != PCIC_BRIDGE || 86 pci_get_subclass(dev) != PCIS_BRIDGE_HOST || 87 agp_find_caps(dev) == 0) 88 return (NULL); 89 90 switch (pci_get_devid(dev)) { 91 case 0x74541022: 92 return ("AMD 8151 AGP graphics tunnel"); 93 case 0x07551039: 94 return ("SiS 755 host to AGP bridge"); 95 case 0x07601039: 96 return ("SiS 760 host to AGP bridge"); 97 case 0x168910b9: 98 return ("ULi M1689 AGP Controller"); 99 case 0x00d110de: 100 if (agp_amd64_nvidia_match(0x00d2)) 101 return (NULL); 102 return ("NVIDIA nForce3 AGP Controller"); 103 case 0x00e110de: 104 if (agp_amd64_nvidia_match(0x00e2)) 105 return (NULL); 106 return ("NVIDIA nForce3-250 AGP Controller"); 107 case 0x02041106: 108 return ("VIA 8380 host to PCI bridge"); 109 case 0x02381106: 110 return ("VIA 3238 host to PCI bridge"); 111 case 0x02821106: 112 return ("VIA K8T800Pro host to PCI bridge"); 113 case 0x31881106: 114 return ("VIA 8385 host to PCI bridge"); 115 } 116 117 return (NULL); 118 } 119 120 static int 121 agp_amd64_nvidia_match(uint16_t devid) 122 { 123 /* XXX nForce3 requires secondary AGP bridge at 0:11:0. */ 124 if (pci_cfgregread(0, 11, 0, PCIR_CLASS, 1) != PCIC_BRIDGE || 125 pci_cfgregread(0, 11, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI || 126 pci_cfgregread(0, 11, 0, PCIR_VENDOR, 2) != 0x10de || 127 pci_cfgregread(0, 11, 0, PCIR_DEVICE, 2) != devid) 128 return (ENXIO); 129 130 return (0); 131 } 132 133 static int 134 agp_amd64_via_match(void) 135 { 136 /* XXX Some VIA bridge requires secondary AGP bridge at 0:1:0. */ 137 if (pci_cfgregread(0, 1, 0, PCIR_CLASS, 1) != PCIC_BRIDGE || 138 pci_cfgregread(0, 1, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI || 139 pci_cfgregread(0, 1, 0, PCIR_VENDOR, 2) != 0x1106 || 140 pci_cfgregread(0, 1, 0, PCIR_DEVICE, 2) != 0xb188 || 141 (pci_cfgregread(0, 1, 0, AGP_VIA_AGPSEL, 1) & 2)) 142 return (0); 143 144 return (1); 145 } 146 147 static int 148 agp_amd64_probe(device_t dev) 149 { 150 const char *desc; 151 152 if (resource_disabled("agp", device_get_unit(dev))) 153 return (ENXIO); 154 if ((desc = agp_amd64_match(dev))) { 155 device_set_desc(dev, desc); 156 return (BUS_PROBE_DEFAULT); 157 } 158 159 return (ENXIO); 160 } 161 162 static int 163 agp_amd64_attach(device_t dev) 164 { 165 struct agp_amd64_softc *sc = device_get_softc(dev); 166 struct agp_gatt *gatt; 167 uint32_t devid; 168 int i, n, error; 169 170 for (i = 0, n = 0; i < PCI_SLOTMAX && n < AMD64_MAX_MCTRL; i++) { 171 devid = pci_cfgregread(0, i, 3, 0, 4); 172 if (devid == 0x11031022 || devid == 0x12031022) { 173 sc->mctrl[n] = i; 174 n++; 175 } 176 } 177 if (n == 0) 178 return (ENXIO); 179 180 sc->n_mctrl = n; 181 182 if (bootverbose) 183 device_printf(dev, "%d Miscellaneous Control unit(s) found.\n", 184 sc->n_mctrl); 185 186 if ((error = agp_generic_attach(dev))) 187 return (error); 188 189 sc->initial_aperture = AGP_GET_APERTURE(dev); 190 191 for (;;) { 192 gatt = agp_alloc_gatt(dev); 193 if (gatt) 194 break; 195 196 /* 197 * Probably contigmalloc failure. Try reducing the 198 * aperture so that the gatt size reduces. 199 */ 200 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) { 201 agp_generic_detach(dev); 202 return (ENOMEM); 203 } 204 } 205 sc->gatt = gatt; 206 207 switch (pci_get_vendor(dev)) { 208 case 0x10b9: /* ULi */ 209 agp_amd64_uli_init(dev); 210 if (agp_amd64_uli_set_aperture(dev, sc->initial_aperture)) 211 return (ENXIO); 212 break; 213 214 case 0x10de: /* nVidia */ 215 agp_amd64_nvidia_init(dev); 216 if (agp_amd64_nvidia_set_aperture(dev, sc->initial_aperture)) 217 return (ENXIO); 218 break; 219 220 case 0x1106: /* VIA */ 221 sc->via_agp = agp_amd64_via_match(); 222 if (sc->via_agp) { 223 agp_amd64_via_init(dev); 224 if (agp_amd64_via_set_aperture(dev, 225 sc->initial_aperture)) 226 return (ENXIO); 227 } 228 break; 229 } 230 231 /* Install the gatt and enable aperture. */ 232 for (i = 0; i < sc->n_mctrl; i++) { 233 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_ATTBASE, 234 (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK, 235 4); 236 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 237 (pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) | 238 AGP_AMD64_APCTRL_GARTEN) & 239 ~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO), 240 4); 241 } 242 243 return (0); 244 } 245 246 static int 247 agp_amd64_detach(device_t dev) 248 { 249 struct agp_amd64_softc *sc = device_get_softc(dev); 250 int i; 251 252 agp_free_cdev(dev); 253 254 for (i = 0; i < sc->n_mctrl; i++) 255 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 256 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) & 257 ~AGP_AMD64_APCTRL_GARTEN, 4); 258 259 AGP_SET_APERTURE(dev, sc->initial_aperture); 260 agp_free_gatt(sc->gatt); 261 agp_free_res(dev); 262 263 return (0); 264 } 265 266 static uint32_t agp_amd64_table[] = { 267 0x02000000, /* 32 MB */ 268 0x04000000, /* 64 MB */ 269 0x08000000, /* 128 MB */ 270 0x10000000, /* 256 MB */ 271 0x20000000, /* 512 MB */ 272 0x40000000, /* 1024 MB */ 273 0x80000000, /* 2048 MB */ 274 }; 275 276 #define AGP_AMD64_TABLE_SIZE nitems(agp_amd64_table) 277 278 static uint32_t 279 agp_amd64_get_aperture(device_t dev) 280 { 281 struct agp_amd64_softc *sc = device_get_softc(dev); 282 uint32_t i; 283 284 i = (pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APCTRL, 4) & 285 AGP_AMD64_APCTRL_SIZE_MASK) >> 1; 286 287 if (i >= AGP_AMD64_TABLE_SIZE) 288 return (0); 289 290 return (agp_amd64_table[i]); 291 } 292 293 static int 294 agp_amd64_set_aperture(device_t dev, uint32_t aperture) 295 { 296 struct agp_amd64_softc *sc = device_get_softc(dev); 297 uint32_t i; 298 int j; 299 300 for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++) 301 if (agp_amd64_table[i] == aperture) 302 break; 303 if (i >= AGP_AMD64_TABLE_SIZE) 304 return (EINVAL); 305 306 for (j = 0; j < sc->n_mctrl; j++) 307 pci_cfgregwrite(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 308 (pci_cfgregread(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) & 309 ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1), 4); 310 311 switch (pci_get_vendor(dev)) { 312 case 0x10b9: /* ULi */ 313 return (agp_amd64_uli_set_aperture(dev, aperture)); 314 break; 315 316 case 0x10de: /* nVidia */ 317 return (agp_amd64_nvidia_set_aperture(dev, aperture)); 318 break; 319 320 case 0x1106: /* VIA */ 321 if (sc->via_agp) 322 return (agp_amd64_via_set_aperture(dev, aperture)); 323 break; 324 } 325 326 return (0); 327 } 328 329 static int 330 agp_amd64_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical) 331 { 332 struct agp_amd64_softc *sc = device_get_softc(dev); 333 334 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 335 return (EINVAL); 336 337 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 338 (physical & 0xfffff000) | ((physical >> 28) & 0x00000ff0) | 3; 339 340 return (0); 341 } 342 343 static int 344 agp_amd64_unbind_page(device_t dev, vm_offset_t offset) 345 { 346 struct agp_amd64_softc *sc = device_get_softc(dev); 347 348 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 349 return (EINVAL); 350 351 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 352 353 return (0); 354 } 355 356 static void 357 agp_amd64_flush_tlb(device_t dev) 358 { 359 struct agp_amd64_softc *sc = device_get_softc(dev); 360 int i; 361 362 for (i = 0; i < sc->n_mctrl; i++) 363 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 364 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 4) | 365 AGP_AMD64_CACHECTRL_INVGART, 4); 366 } 367 368 static void 369 agp_amd64_apbase_fixup(device_t dev) 370 { 371 struct agp_amd64_softc *sc = device_get_softc(dev); 372 uint32_t apbase; 373 int i; 374 375 sc->apbase = rman_get_start(sc->agp.as_aperture); 376 apbase = (sc->apbase >> 25) & AGP_AMD64_APBASE_MASK; 377 for (i = 0; i < sc->n_mctrl; i++) 378 pci_cfgregwrite(0, sc->mctrl[i], 3, 379 AGP_AMD64_APBASE, apbase, 4); 380 } 381 382 static void 383 agp_amd64_uli_init(device_t dev) 384 { 385 struct agp_amd64_softc *sc = device_get_softc(dev); 386 387 agp_amd64_apbase_fixup(dev); 388 pci_write_config(dev, AGP_AMD64_ULI_APBASE, 389 (pci_read_config(dev, AGP_AMD64_ULI_APBASE, 4) & 0x0000000f) | 390 sc->apbase, 4); 391 pci_write_config(dev, AGP_AMD64_ULI_HTT_FEATURE, sc->apbase, 4); 392 } 393 394 static int 395 agp_amd64_uli_set_aperture(device_t dev, uint32_t aperture) 396 { 397 struct agp_amd64_softc *sc = device_get_softc(dev); 398 399 switch (aperture) { 400 case 0x02000000: /* 32 MB */ 401 case 0x04000000: /* 64 MB */ 402 case 0x08000000: /* 128 MB */ 403 case 0x10000000: /* 256 MB */ 404 break; 405 default: 406 return (EINVAL); 407 } 408 409 pci_write_config(dev, AGP_AMD64_ULI_ENU_SCR, 410 sc->apbase + aperture - 1, 4); 411 412 return (0); 413 } 414 415 static void 416 agp_amd64_nvidia_init(device_t dev) 417 { 418 struct agp_amd64_softc *sc = device_get_softc(dev); 419 420 agp_amd64_apbase_fixup(dev); 421 pci_write_config(dev, AGP_AMD64_NVIDIA_0_APBASE, 422 (pci_read_config(dev, AGP_AMD64_NVIDIA_0_APBASE, 4) & 0x0000000f) | 423 sc->apbase, 4); 424 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE1, sc->apbase, 4); 425 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE2, sc->apbase, 4); 426 } 427 428 static int 429 agp_amd64_nvidia_set_aperture(device_t dev, uint32_t aperture) 430 { 431 struct agp_amd64_softc *sc = device_get_softc(dev); 432 uint32_t apsize; 433 434 switch (aperture) { 435 case 0x02000000: apsize = 0x0f; break; /* 32 MB */ 436 case 0x04000000: apsize = 0x0e; break; /* 64 MB */ 437 case 0x08000000: apsize = 0x0c; break; /* 128 MB */ 438 case 0x10000000: apsize = 0x08; break; /* 256 MB */ 439 case 0x20000000: apsize = 0x00; break; /* 512 MB */ 440 default: 441 return (EINVAL); 442 } 443 444 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 445 (pci_cfgregread(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 4) & 446 0xfffffff0) | apsize, 4); 447 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT1, 448 sc->apbase + aperture - 1, 4); 449 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT2, 450 sc->apbase + aperture - 1, 4); 451 452 return (0); 453 } 454 455 static void 456 agp_amd64_via_init(device_t dev) 457 { 458 struct agp_amd64_softc *sc = device_get_softc(dev); 459 460 agp_amd64_apbase_fixup(dev); 461 pci_cfgregwrite(0, 1, 0, AGP3_VIA_ATTBASE, sc->gatt->ag_physical, 4); 462 pci_cfgregwrite(0, 1, 0, AGP3_VIA_GARTCTRL, 463 pci_cfgregread(0, 1, 0, AGP3_VIA_ATTBASE, 4) | 0x180, 4); 464 } 465 466 static int 467 agp_amd64_via_set_aperture(device_t dev, uint32_t aperture) 468 { 469 uint32_t apsize; 470 471 apsize = ((aperture - 1) >> 20) ^ 0xff; 472 if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture) 473 return (EINVAL); 474 pci_cfgregwrite(0, 1, 0, AGP3_VIA_APSIZE, apsize, 1); 475 476 return (0); 477 } 478 479 static device_method_t agp_amd64_methods[] = { 480 /* Device interface */ 481 DEVMETHOD(device_probe, agp_amd64_probe), 482 DEVMETHOD(device_attach, agp_amd64_attach), 483 DEVMETHOD(device_detach, agp_amd64_detach), 484 DEVMETHOD(device_shutdown, bus_generic_shutdown), 485 DEVMETHOD(device_suspend, bus_generic_suspend), 486 DEVMETHOD(device_resume, bus_generic_resume), 487 488 /* AGP interface */ 489 DEVMETHOD(agp_get_aperture, agp_amd64_get_aperture), 490 DEVMETHOD(agp_set_aperture, agp_amd64_set_aperture), 491 DEVMETHOD(agp_bind_page, agp_amd64_bind_page), 492 DEVMETHOD(agp_unbind_page, agp_amd64_unbind_page), 493 DEVMETHOD(agp_flush_tlb, agp_amd64_flush_tlb), 494 DEVMETHOD(agp_enable, agp_generic_enable), 495 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 496 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 497 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 498 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 499 { 0, 0 } 500 }; 501 502 static driver_t agp_amd64_driver = { 503 "agp", 504 agp_amd64_methods, 505 sizeof(struct agp_amd64_softc), 506 }; 507 508 DRIVER_MODULE(agp_amd64, hostb, agp_amd64_driver, 0, 0); 509 MODULE_DEPEND(agp_amd64, agp, 1, 1, 1); 510 MODULE_DEPEND(agp_amd64, pci, 1, 1, 1); 511