1 /*- 2 * Copyright (c) 2004, 2005 Jung-uk Kim <jkim@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_bus.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/bus.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/proc.h> 41 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcireg.h> 44 #include <pci/agppriv.h> 45 #include <pci/agpreg.h> 46 47 #include <vm/vm.h> 48 #include <vm/vm_object.h> 49 #include <vm/pmap.h> 50 #include <machine/bus.h> 51 #include <machine/resource.h> 52 #include <sys/rman.h> 53 54 /* XXX */ 55 extern void pci_cfgregwrite(int, int, int, int, uint32_t, int); 56 extern uint32_t pci_cfgregread(int, int, int, int, int); 57 58 static void agp_amd64_apbase_fixup(device_t); 59 60 static void agp_amd64_uli_init(device_t); 61 static int agp_amd64_uli_set_aperture(device_t, uint32_t); 62 63 static int agp_amd64_nvidia_match(uint16_t); 64 static void agp_amd64_nvidia_init(device_t); 65 static int agp_amd64_nvidia_set_aperture(device_t, uint32_t); 66 67 static int agp_amd64_via_match(void); 68 static void agp_amd64_via_init(device_t); 69 static int agp_amd64_via_set_aperture(device_t, uint32_t); 70 71 MALLOC_DECLARE(M_AGP); 72 73 #define AMD64_MAX_MCTRL 8 74 75 struct agp_amd64_softc { 76 struct agp_softc agp; 77 uint32_t initial_aperture; 78 struct agp_gatt *gatt; 79 uint32_t apbase; 80 int mctrl[AMD64_MAX_MCTRL]; 81 int n_mctrl; 82 int via_agp; 83 }; 84 85 static const char* 86 agp_amd64_match(device_t dev) 87 { 88 if (pci_get_class(dev) != PCIC_BRIDGE 89 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST) 90 return NULL; 91 92 if (agp_find_caps(dev) == 0) 93 return NULL; 94 95 switch (pci_get_devid(dev)) { 96 case 0x74541022: 97 return ("AMD 8151 AGP graphics tunnel"); 98 case 0x07551039: 99 return ("SiS 755 host to AGP bridge"); 100 case 0x07601039: 101 return ("SiS 760 host to AGP bridge"); 102 case 0x168910b9: 103 return ("ULi M1689 AGP Controller"); 104 case 0x00d110de: 105 if (agp_amd64_nvidia_match(0x00d2)) 106 return NULL; 107 return ("NVIDIA nForce3 AGP Controller"); 108 case 0x00e110de: 109 if (agp_amd64_nvidia_match(0x00e2)) 110 return NULL; 111 return ("NVIDIA nForce3-250 AGP Controller"); 112 case 0x02041106: 113 return ("VIA 8380 host to PCI bridge"); 114 case 0x02381106: 115 return ("VIA 3238 host to PCI bridge"); 116 case 0x02821106: 117 return ("VIA K8T800Pro host to PCI bridge"); 118 case 0x31881106: 119 return ("VIA 8385 host to PCI bridge"); 120 }; 121 122 return NULL; 123 } 124 125 static int 126 agp_amd64_nvidia_match(uint16_t devid) 127 { 128 /* XXX nForce3 requires secondary AGP bridge at 0:11:0. */ 129 if (pci_cfgregread(0, 11, 0, PCIR_CLASS, 1) != PCIC_BRIDGE || 130 pci_cfgregread(0, 11, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI || 131 pci_cfgregread(0, 11, 0, PCIR_VENDOR, 2) != 0x10de || 132 pci_cfgregread(0, 11, 0, PCIR_DEVICE, 2) != devid) 133 return ENXIO; 134 135 return 0; 136 } 137 138 static int 139 agp_amd64_via_match(void) 140 { 141 /* XXX Some VIA bridge requires secondary AGP bridge at 0:1:0. */ 142 if (pci_cfgregread(0, 1, 0, PCIR_CLASS, 1) != PCIC_BRIDGE || 143 pci_cfgregread(0, 1, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI || 144 pci_cfgregread(0, 1, 0, PCIR_VENDOR, 2) != 0x1106 || 145 pci_cfgregread(0, 1, 0, PCIR_DEVICE, 2) != 0xb188 || 146 (pci_cfgregread(0, 1, 0, AGP_VIA_AGPSEL, 1) & 2)) 147 return 0; 148 149 return 1; 150 } 151 152 static int 153 agp_amd64_probe(device_t dev) 154 { 155 const char *desc; 156 157 if (resource_disabled("agp", device_get_unit(dev))) 158 return ENXIO; 159 if ((desc = agp_amd64_match(dev))) { 160 device_set_desc(dev, desc); 161 return BUS_PROBE_DEFAULT; 162 } 163 164 return ENXIO; 165 } 166 167 static int 168 agp_amd64_attach(device_t dev) 169 { 170 struct agp_amd64_softc *sc = device_get_softc(dev); 171 struct agp_gatt *gatt; 172 int i, n, error; 173 174 for (i = 0, n = 0; i < PCI_SLOTMAX && n < AMD64_MAX_MCTRL; i++) 175 if (pci_cfgregread(0, i, 3, 0, 4) == 0x11031022) { 176 sc->mctrl[n] = i; 177 n++; 178 } 179 180 if (n == 0) 181 return ENXIO; 182 183 sc->n_mctrl = n; 184 185 if (bootverbose) { 186 device_printf(dev, "%d Miscellaneous Control unit(s) found.\n", 187 sc->n_mctrl); 188 for (i = 0; i < sc->n_mctrl; i++) 189 device_printf(dev, "Aperture Base[%d]: 0x%08x\n", i, 190 pci_cfgregread(0, sc->mctrl[i], 3, 191 AGP_AMD64_APBASE, 4) & AGP_AMD64_APBASE_MASK); 192 } 193 194 if ((error = agp_generic_attach(dev))) 195 return error; 196 197 sc->initial_aperture = AGP_GET_APERTURE(dev); 198 199 for (;;) { 200 gatt = agp_alloc_gatt(dev); 201 if (gatt) 202 break; 203 204 /* 205 * Probably contigmalloc failure. Try reducing the 206 * aperture so that the gatt size reduces. 207 */ 208 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) { 209 agp_generic_detach(dev); 210 return ENOMEM; 211 } 212 } 213 sc->gatt = gatt; 214 215 switch (pci_get_vendor(dev)) { 216 case 0x10b9: /* ULi */ 217 agp_amd64_uli_init(dev); 218 if (agp_amd64_uli_set_aperture(dev, sc->initial_aperture)) 219 return ENXIO; 220 break; 221 222 case 0x10de: /* nVidia */ 223 agp_amd64_nvidia_init(dev); 224 if (agp_amd64_nvidia_set_aperture(dev, sc->initial_aperture)) 225 return ENXIO; 226 break; 227 228 case 0x1106: /* VIA */ 229 sc->via_agp = agp_amd64_via_match(); 230 if (sc->via_agp) { 231 agp_amd64_via_init(dev); 232 if (agp_amd64_via_set_aperture(dev, 233 sc->initial_aperture)) 234 return ENXIO; 235 } 236 break; 237 } 238 239 /* Install the gatt and enable aperture. */ 240 for (i = 0; i < sc->n_mctrl; i++) { 241 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_ATTBASE, 242 (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK, 243 4); 244 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 245 (pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) | 246 AGP_AMD64_APCTRL_GARTEN) & 247 ~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO), 248 4); 249 } 250 251 agp_flush_cache(); 252 253 return 0; 254 } 255 256 static int 257 agp_amd64_detach(device_t dev) 258 { 259 struct agp_amd64_softc *sc = device_get_softc(dev); 260 int i, error; 261 262 if ((error = agp_generic_detach(dev))) 263 return error; 264 265 for (i = 0; i < sc->n_mctrl; i++) 266 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 267 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) & 268 ~AGP_AMD64_APCTRL_GARTEN, 4); 269 270 AGP_SET_APERTURE(dev, sc->initial_aperture); 271 agp_free_gatt(sc->gatt); 272 273 return 0; 274 } 275 276 static uint32_t agp_amd64_table[] = { 277 0x02000000, /* 32 MB */ 278 0x04000000, /* 64 MB */ 279 0x08000000, /* 128 MB */ 280 0x10000000, /* 256 MB */ 281 0x20000000, /* 512 MB */ 282 0x40000000, /* 1024 MB */ 283 0x80000000, /* 2048 MB */ 284 }; 285 286 #define AGP_AMD64_TABLE_SIZE \ 287 (sizeof(agp_amd64_table) / sizeof(agp_amd64_table[0])) 288 289 static uint32_t 290 agp_amd64_get_aperture(device_t dev) 291 { 292 struct agp_amd64_softc *sc = device_get_softc(dev); 293 uint32_t i; 294 295 i = (pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APCTRL, 4) & 296 AGP_AMD64_APCTRL_SIZE_MASK) >> 1; 297 298 if (i >= AGP_AMD64_TABLE_SIZE) 299 return 0; 300 301 return (agp_amd64_table[i]); 302 } 303 304 static int 305 agp_amd64_set_aperture(device_t dev, uint32_t aperture) 306 { 307 struct agp_amd64_softc *sc = device_get_softc(dev); 308 uint32_t i; 309 int j; 310 311 for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++) 312 if (agp_amd64_table[i] == aperture) 313 break; 314 if (i >= AGP_AMD64_TABLE_SIZE) 315 return EINVAL; 316 317 for (j = 0; j < sc->n_mctrl; j++) 318 pci_cfgregwrite(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 319 (pci_cfgregread(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) & 320 ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1), 4); 321 322 switch (pci_get_vendor(dev)) { 323 case 0x10b9: /* ULi */ 324 return (agp_amd64_uli_set_aperture(dev, aperture)); 325 break; 326 327 case 0x10de: /* nVidia */ 328 return (agp_amd64_nvidia_set_aperture(dev, aperture)); 329 break; 330 331 case 0x1106: /* VIA */ 332 if (sc->via_agp) 333 return (agp_amd64_via_set_aperture(dev, aperture)); 334 break; 335 } 336 337 return 0; 338 } 339 340 static int 341 agp_amd64_bind_page(device_t dev, int offset, vm_offset_t physical) 342 { 343 struct agp_amd64_softc *sc = device_get_softc(dev); 344 345 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 346 return EINVAL; 347 348 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical; 349 return 0; 350 } 351 352 static int 353 agp_amd64_unbind_page(device_t dev, int offset) 354 { 355 struct agp_amd64_softc *sc = device_get_softc(dev); 356 357 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 358 return EINVAL; 359 360 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 361 return 0; 362 } 363 364 static void 365 agp_amd64_flush_tlb(device_t dev) 366 { 367 struct agp_amd64_softc *sc = device_get_softc(dev); 368 int i; 369 370 for (i = 0; i < sc->n_mctrl; i++) 371 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 372 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 4) | 373 AGP_AMD64_CACHECTRL_INVGART, 4); 374 } 375 376 static void 377 agp_amd64_apbase_fixup(device_t dev) 378 { 379 struct agp_amd64_softc *sc = device_get_softc(dev); 380 uint32_t apbase; 381 int i; 382 383 apbase = pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APBASE, 4); 384 for (i = 0; i < sc->n_mctrl; i++) 385 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APBASE, 386 apbase & ~(AGP_AMD64_APBASE_MASK & ~(uint32_t)0x7f), 4); 387 sc->apbase = apbase << 25; 388 } 389 390 static void 391 agp_amd64_uli_init(device_t dev) 392 { 393 struct agp_amd64_softc *sc = device_get_softc(dev); 394 395 agp_amd64_apbase_fixup(dev); 396 pci_write_config(dev, AGP_AMD64_ULI_APBASE, 397 (pci_read_config(dev, AGP_AMD64_ULI_APBASE, 4) & 0x0000000f) | 398 sc->apbase, 4); 399 pci_write_config(dev, AGP_AMD64_ULI_HTT_FEATURE, sc->apbase, 4); 400 } 401 402 static int 403 agp_amd64_uli_set_aperture(device_t dev, uint32_t aperture) 404 { 405 struct agp_amd64_softc *sc = device_get_softc(dev); 406 407 switch (aperture) { 408 case 0x02000000: /* 32 MB */ 409 case 0x04000000: /* 64 MB */ 410 case 0x08000000: /* 128 MB */ 411 case 0x10000000: /* 256 MB */ 412 break; 413 default: 414 return EINVAL; 415 } 416 417 pci_write_config(dev, AGP_AMD64_ULI_ENU_SCR, 418 sc->apbase + aperture - 1, 4); 419 420 return 0; 421 } 422 423 static void 424 agp_amd64_nvidia_init(device_t dev) 425 { 426 struct agp_amd64_softc *sc = device_get_softc(dev); 427 428 agp_amd64_apbase_fixup(dev); 429 pci_write_config(dev, AGP_AMD64_NVIDIA_0_APBASE, 430 (pci_read_config(dev, AGP_AMD64_NVIDIA_0_APBASE, 4) & 0x0000000f) | 431 sc->apbase, 4); 432 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE1, sc->apbase, 4); 433 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE2, sc->apbase, 4); 434 } 435 436 static int 437 agp_amd64_nvidia_set_aperture(device_t dev, uint32_t aperture) 438 { 439 struct agp_amd64_softc *sc = device_get_softc(dev); 440 uint32_t apsize; 441 442 switch (aperture) { 443 case 0x02000000: apsize = 0x0f; break; /* 32 MB */ 444 case 0x04000000: apsize = 0x0e; break; /* 64 MB */ 445 case 0x08000000: apsize = 0x0c; break; /* 128 MB */ 446 case 0x10000000: apsize = 0x08; break; /* 256 MB */ 447 case 0x20000000: apsize = 0x00; break; /* 512 MB */ 448 default: 449 return EINVAL; 450 } 451 452 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 453 (pci_cfgregread(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 4) & 454 0xfffffff0) | apsize, 4); 455 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT1, 456 sc->apbase + aperture - 1, 4); 457 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT2, 458 sc->apbase + aperture - 1, 4); 459 460 return 0; 461 } 462 463 static void 464 agp_amd64_via_init(device_t dev) 465 { 466 struct agp_amd64_softc *sc = device_get_softc(dev); 467 468 agp_amd64_apbase_fixup(dev); 469 pci_cfgregwrite(0, 1, 0, AGP3_VIA_ATTBASE, sc->gatt->ag_physical, 4); 470 pci_cfgregwrite(0, 1, 0, AGP3_VIA_GARTCTRL, 471 pci_cfgregread(0, 1, 0, AGP3_VIA_ATTBASE, 4) | 0x180, 4); 472 } 473 474 static int 475 agp_amd64_via_set_aperture(device_t dev, uint32_t aperture) 476 { 477 uint32_t apsize; 478 479 apsize = ((aperture - 1) >> 20) ^ 0xff; 480 if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture) 481 return EINVAL; 482 pci_cfgregwrite(0, 1, 0, AGP3_VIA_APSIZE, apsize, 1); 483 484 return 0; 485 } 486 487 static device_method_t agp_amd64_methods[] = { 488 /* Device interface */ 489 DEVMETHOD(device_probe, agp_amd64_probe), 490 DEVMETHOD(device_attach, agp_amd64_attach), 491 DEVMETHOD(device_detach, agp_amd64_detach), 492 DEVMETHOD(device_shutdown, bus_generic_shutdown), 493 DEVMETHOD(device_suspend, bus_generic_suspend), 494 DEVMETHOD(device_resume, bus_generic_resume), 495 496 /* AGP interface */ 497 DEVMETHOD(agp_get_aperture, agp_amd64_get_aperture), 498 DEVMETHOD(agp_set_aperture, agp_amd64_set_aperture), 499 DEVMETHOD(agp_bind_page, agp_amd64_bind_page), 500 DEVMETHOD(agp_unbind_page, agp_amd64_unbind_page), 501 DEVMETHOD(agp_flush_tlb, agp_amd64_flush_tlb), 502 DEVMETHOD(agp_enable, agp_generic_enable), 503 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 504 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 505 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 506 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 507 508 { 0, 0 } 509 }; 510 511 static driver_t agp_amd64_driver = { 512 "agp", 513 agp_amd64_methods, 514 sizeof(struct agp_amd64_softc), 515 }; 516 517 static devclass_t agp_devclass; 518 519 DRIVER_MODULE(agp_amd64, hostb, agp_amd64_driver, agp_devclass, 0, 0); 520 MODULE_DEPEND(agp_amd64, agp, 1, 1, 1); 521 MODULE_DEPEND(agp_amd64, pci, 1, 1, 1); 522