1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2004, 2005 Jung-uk Kim <jkim@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/malloc.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/bus.h> 35 #include <sys/lock.h> 36 #include <sys/mutex.h> 37 #include <sys/proc.h> 38 39 #include <dev/agp/agppriv.h> 40 #include <dev/agp/agpreg.h> 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcireg.h> 43 44 #include <vm/vm.h> 45 #include <vm/vm_object.h> 46 #include <vm/pmap.h> 47 #include <machine/bus.h> 48 #include <machine/resource.h> 49 #include <machine/pci_cfgreg.h> 50 #include <sys/rman.h> 51 52 static void agp_amd64_apbase_fixup(device_t); 53 54 static void agp_amd64_uli_init(device_t); 55 static int agp_amd64_uli_set_aperture(device_t, uint32_t); 56 57 static int agp_amd64_nvidia_match(uint16_t); 58 static void agp_amd64_nvidia_init(device_t); 59 static int agp_amd64_nvidia_set_aperture(device_t, uint32_t); 60 61 static int agp_amd64_via_match(void); 62 static void agp_amd64_via_init(device_t); 63 static int agp_amd64_via_set_aperture(device_t, uint32_t); 64 65 MALLOC_DECLARE(M_AGP); 66 67 #define AMD64_MAX_MCTRL 8 68 69 struct agp_amd64_softc { 70 struct agp_softc agp; 71 uint32_t initial_aperture; 72 struct agp_gatt *gatt; 73 uint32_t apbase; 74 int mctrl[AMD64_MAX_MCTRL]; 75 int n_mctrl; 76 int via_agp; 77 }; 78 79 static const char* 80 agp_amd64_match(device_t dev) 81 { 82 if (pci_get_class(dev) != PCIC_BRIDGE || 83 pci_get_subclass(dev) != PCIS_BRIDGE_HOST || 84 agp_find_caps(dev) == 0) 85 return (NULL); 86 87 switch (pci_get_devid(dev)) { 88 case 0x74541022: 89 return ("AMD 8151 AGP graphics tunnel"); 90 case 0x07551039: 91 return ("SiS 755 host to AGP bridge"); 92 case 0x07601039: 93 return ("SiS 760 host to AGP bridge"); 94 case 0x168910b9: 95 return ("ULi M1689 AGP Controller"); 96 case 0x00d110de: 97 if (agp_amd64_nvidia_match(0x00d2)) 98 return (NULL); 99 return ("NVIDIA nForce3 AGP Controller"); 100 case 0x00e110de: 101 if (agp_amd64_nvidia_match(0x00e2)) 102 return (NULL); 103 return ("NVIDIA nForce3-250 AGP Controller"); 104 case 0x02041106: 105 return ("VIA 8380 host to PCI bridge"); 106 case 0x02381106: 107 return ("VIA 3238 host to PCI bridge"); 108 case 0x02821106: 109 return ("VIA K8T800Pro host to PCI bridge"); 110 case 0x31881106: 111 return ("VIA 8385 host to PCI bridge"); 112 } 113 114 return (NULL); 115 } 116 117 static int 118 agp_amd64_nvidia_match(uint16_t devid) 119 { 120 /* XXX nForce3 requires secondary AGP bridge at 0:11:0. */ 121 if (pci_cfgregread(0, 0, 11, 0, PCIR_CLASS, 1) != PCIC_BRIDGE || 122 pci_cfgregread(0, 0, 11, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI || 123 pci_cfgregread(0, 0, 11, 0, PCIR_VENDOR, 2) != 0x10de || 124 pci_cfgregread(0, 0, 11, 0, PCIR_DEVICE, 2) != devid) 125 return (ENXIO); 126 127 return (0); 128 } 129 130 static int 131 agp_amd64_via_match(void) 132 { 133 /* XXX Some VIA bridge requires secondary AGP bridge at 0:1:0. */ 134 if (pci_cfgregread(0, 0, 1, 0, PCIR_CLASS, 1) != PCIC_BRIDGE || 135 pci_cfgregread(0, 0, 1, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI || 136 pci_cfgregread(0, 0, 1, 0, PCIR_VENDOR, 2) != 0x1106 || 137 pci_cfgregread(0, 0, 1, 0, PCIR_DEVICE, 2) != 0xb188 || 138 (pci_cfgregread(0, 0, 1, 0, AGP_VIA_AGPSEL, 1) & 2)) 139 return (0); 140 141 return (1); 142 } 143 144 static int 145 agp_amd64_probe(device_t dev) 146 { 147 const char *desc; 148 149 if (resource_disabled("agp", device_get_unit(dev))) 150 return (ENXIO); 151 if ((desc = agp_amd64_match(dev))) { 152 device_set_desc(dev, desc); 153 return (BUS_PROBE_DEFAULT); 154 } 155 156 return (ENXIO); 157 } 158 159 static int 160 agp_amd64_attach(device_t dev) 161 { 162 struct agp_amd64_softc *sc = device_get_softc(dev); 163 struct agp_gatt *gatt; 164 uint32_t devid; 165 int i, n, error; 166 167 for (i = 0, n = 0; i < PCI_SLOTMAX && n < AMD64_MAX_MCTRL; i++) { 168 devid = pci_cfgregread(0, 0, i, 3, 0, 4); 169 if (devid == 0x11031022 || devid == 0x12031022) { 170 sc->mctrl[n] = i; 171 n++; 172 } 173 } 174 if (n == 0) 175 return (ENXIO); 176 177 sc->n_mctrl = n; 178 179 if (bootverbose) 180 device_printf(dev, "%d Miscellaneous Control unit(s) found.\n", 181 sc->n_mctrl); 182 183 if ((error = agp_generic_attach(dev))) 184 return (error); 185 186 sc->initial_aperture = AGP_GET_APERTURE(dev); 187 188 for (;;) { 189 gatt = agp_alloc_gatt(dev); 190 if (gatt) 191 break; 192 193 /* 194 * Probably contigmalloc failure. Try reducing the 195 * aperture so that the gatt size reduces. 196 */ 197 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) { 198 agp_generic_detach(dev); 199 return (ENOMEM); 200 } 201 } 202 sc->gatt = gatt; 203 204 switch (pci_get_vendor(dev)) { 205 case 0x10b9: /* ULi */ 206 agp_amd64_uli_init(dev); 207 if (agp_amd64_uli_set_aperture(dev, sc->initial_aperture)) 208 return (ENXIO); 209 break; 210 211 case 0x10de: /* nVidia */ 212 agp_amd64_nvidia_init(dev); 213 if (agp_amd64_nvidia_set_aperture(dev, sc->initial_aperture)) 214 return (ENXIO); 215 break; 216 217 case 0x1106: /* VIA */ 218 sc->via_agp = agp_amd64_via_match(); 219 if (sc->via_agp) { 220 agp_amd64_via_init(dev); 221 if (agp_amd64_via_set_aperture(dev, 222 sc->initial_aperture)) 223 return (ENXIO); 224 } 225 break; 226 } 227 228 /* Install the gatt and enable aperture. */ 229 for (i = 0; i < sc->n_mctrl; i++) { 230 pci_cfgregwrite(0, 0, sc->mctrl[i], 3, AGP_AMD64_ATTBASE, 231 (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK, 232 4); 233 pci_cfgregwrite(0, 0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 234 (pci_cfgregread(0, 0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) | 235 AGP_AMD64_APCTRL_GARTEN) & 236 ~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO), 237 4); 238 } 239 240 return (0); 241 } 242 243 static int 244 agp_amd64_detach(device_t dev) 245 { 246 struct agp_amd64_softc *sc = device_get_softc(dev); 247 int i; 248 249 agp_free_cdev(dev); 250 251 for (i = 0; i < sc->n_mctrl; i++) 252 pci_cfgregwrite(0, 0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 253 pci_cfgregread(0, 0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) & 254 ~AGP_AMD64_APCTRL_GARTEN, 4); 255 256 AGP_SET_APERTURE(dev, sc->initial_aperture); 257 agp_free_gatt(sc->gatt); 258 agp_free_res(dev); 259 260 return (0); 261 } 262 263 static uint32_t agp_amd64_table[] = { 264 0x02000000, /* 32 MB */ 265 0x04000000, /* 64 MB */ 266 0x08000000, /* 128 MB */ 267 0x10000000, /* 256 MB */ 268 0x20000000, /* 512 MB */ 269 0x40000000, /* 1024 MB */ 270 0x80000000, /* 2048 MB */ 271 }; 272 273 #define AGP_AMD64_TABLE_SIZE nitems(agp_amd64_table) 274 275 static uint32_t 276 agp_amd64_get_aperture(device_t dev) 277 { 278 struct agp_amd64_softc *sc = device_get_softc(dev); 279 uint32_t i; 280 281 i = (pci_cfgregread(0, 0, sc->mctrl[0], 3, AGP_AMD64_APCTRL, 4) & 282 AGP_AMD64_APCTRL_SIZE_MASK) >> 1; 283 284 if (i >= AGP_AMD64_TABLE_SIZE) 285 return (0); 286 287 return (agp_amd64_table[i]); 288 } 289 290 static int 291 agp_amd64_set_aperture(device_t dev, uint32_t aperture) 292 { 293 struct agp_amd64_softc *sc = device_get_softc(dev); 294 uint32_t i; 295 int j; 296 297 for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++) 298 if (agp_amd64_table[i] == aperture) 299 break; 300 if (i >= AGP_AMD64_TABLE_SIZE) 301 return (EINVAL); 302 303 for (j = 0; j < sc->n_mctrl; j++) 304 pci_cfgregwrite(0, 0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 305 (pci_cfgregread(0, 0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) & 306 ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1), 4); 307 308 switch (pci_get_vendor(dev)) { 309 case 0x10b9: /* ULi */ 310 return (agp_amd64_uli_set_aperture(dev, aperture)); 311 break; 312 313 case 0x10de: /* nVidia */ 314 return (agp_amd64_nvidia_set_aperture(dev, aperture)); 315 break; 316 317 case 0x1106: /* VIA */ 318 if (sc->via_agp) 319 return (agp_amd64_via_set_aperture(dev, aperture)); 320 break; 321 } 322 323 return (0); 324 } 325 326 static int 327 agp_amd64_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical) 328 { 329 struct agp_amd64_softc *sc = device_get_softc(dev); 330 331 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 332 return (EINVAL); 333 334 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 335 (physical & 0xfffff000) | ((physical >> 28) & 0x00000ff0) | 3; 336 337 return (0); 338 } 339 340 static int 341 agp_amd64_unbind_page(device_t dev, vm_offset_t offset) 342 { 343 struct agp_amd64_softc *sc = device_get_softc(dev); 344 345 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 346 return (EINVAL); 347 348 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 349 350 return (0); 351 } 352 353 static void 354 agp_amd64_flush_tlb(device_t dev) 355 { 356 struct agp_amd64_softc *sc = device_get_softc(dev); 357 int i; 358 359 for (i = 0; i < sc->n_mctrl; i++) { 360 uint32_t val; 361 362 val = pci_cfgregread(0, 0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 363 4); 364 val |= AGP_AMD64_CACHECTRL_INVGART; 365 pci_cfgregwrite(0, 0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, val, 366 4); 367 } 368 } 369 370 static void 371 agp_amd64_apbase_fixup(device_t dev) 372 { 373 struct agp_amd64_softc *sc = device_get_softc(dev); 374 uint32_t apbase; 375 int i; 376 377 sc->apbase = rman_get_start(sc->agp.as_aperture); 378 apbase = (sc->apbase >> 25) & AGP_AMD64_APBASE_MASK; 379 for (i = 0; i < sc->n_mctrl; i++) 380 pci_cfgregwrite(0, 0, sc->mctrl[i], 3, 381 AGP_AMD64_APBASE, apbase, 4); 382 } 383 384 static void 385 agp_amd64_uli_init(device_t dev) 386 { 387 struct agp_amd64_softc *sc = device_get_softc(dev); 388 389 agp_amd64_apbase_fixup(dev); 390 pci_write_config(dev, AGP_AMD64_ULI_APBASE, 391 (pci_read_config(dev, AGP_AMD64_ULI_APBASE, 4) & 0x0000000f) | 392 sc->apbase, 4); 393 pci_write_config(dev, AGP_AMD64_ULI_HTT_FEATURE, sc->apbase, 4); 394 } 395 396 static int 397 agp_amd64_uli_set_aperture(device_t dev, uint32_t aperture) 398 { 399 struct agp_amd64_softc *sc = device_get_softc(dev); 400 401 switch (aperture) { 402 case 0x02000000: /* 32 MB */ 403 case 0x04000000: /* 64 MB */ 404 case 0x08000000: /* 128 MB */ 405 case 0x10000000: /* 256 MB */ 406 break; 407 default: 408 return (EINVAL); 409 } 410 411 pci_write_config(dev, AGP_AMD64_ULI_ENU_SCR, 412 sc->apbase + aperture - 1, 4); 413 414 return (0); 415 } 416 417 static void 418 agp_amd64_nvidia_init(device_t dev) 419 { 420 struct agp_amd64_softc *sc = device_get_softc(dev); 421 422 agp_amd64_apbase_fixup(dev); 423 pci_write_config(dev, AGP_AMD64_NVIDIA_0_APBASE, 424 (pci_read_config(dev, AGP_AMD64_NVIDIA_0_APBASE, 4) & 0x0000000f) | 425 sc->apbase, 4); 426 pci_cfgregwrite(0, 0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE1, sc->apbase, 4); 427 pci_cfgregwrite(0, 0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE2, sc->apbase, 4); 428 } 429 430 static int 431 agp_amd64_nvidia_set_aperture(device_t dev, uint32_t aperture) 432 { 433 struct agp_amd64_softc *sc = device_get_softc(dev); 434 uint32_t apsize; 435 436 switch (aperture) { 437 case 0x02000000: apsize = 0x0f; break; /* 32 MB */ 438 case 0x04000000: apsize = 0x0e; break; /* 64 MB */ 439 case 0x08000000: apsize = 0x0c; break; /* 128 MB */ 440 case 0x10000000: apsize = 0x08; break; /* 256 MB */ 441 case 0x20000000: apsize = 0x00; break; /* 512 MB */ 442 default: 443 return (EINVAL); 444 } 445 446 pci_cfgregwrite(0, 0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 447 (pci_cfgregread(0, 0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 4) & 448 0xfffffff0) | apsize, 4); 449 pci_cfgregwrite(0, 0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT1, 450 sc->apbase + aperture - 1, 4); 451 pci_cfgregwrite(0, 0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT2, 452 sc->apbase + aperture - 1, 4); 453 454 return (0); 455 } 456 457 static void 458 agp_amd64_via_init(device_t dev) 459 { 460 struct agp_amd64_softc *sc = device_get_softc(dev); 461 462 agp_amd64_apbase_fixup(dev); 463 pci_cfgregwrite(0, 0, 1, 0, AGP3_VIA_ATTBASE, sc->gatt->ag_physical, 4); 464 pci_cfgregwrite(0, 0, 1, 0, AGP3_VIA_GARTCTRL, 465 pci_cfgregread(0, 0, 1, 0, AGP3_VIA_ATTBASE, 4) | 0x180, 4); 466 } 467 468 static int 469 agp_amd64_via_set_aperture(device_t dev, uint32_t aperture) 470 { 471 uint32_t apsize; 472 473 apsize = ((aperture - 1) >> 20) ^ 0xff; 474 if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture) 475 return (EINVAL); 476 pci_cfgregwrite(0, 0, 1, 0, AGP3_VIA_APSIZE, apsize, 1); 477 478 return (0); 479 } 480 481 static device_method_t agp_amd64_methods[] = { 482 /* Device interface */ 483 DEVMETHOD(device_probe, agp_amd64_probe), 484 DEVMETHOD(device_attach, agp_amd64_attach), 485 DEVMETHOD(device_detach, agp_amd64_detach), 486 DEVMETHOD(device_shutdown, bus_generic_shutdown), 487 DEVMETHOD(device_suspend, bus_generic_suspend), 488 DEVMETHOD(device_resume, bus_generic_resume), 489 490 /* AGP interface */ 491 DEVMETHOD(agp_get_aperture, agp_amd64_get_aperture), 492 DEVMETHOD(agp_set_aperture, agp_amd64_set_aperture), 493 DEVMETHOD(agp_bind_page, agp_amd64_bind_page), 494 DEVMETHOD(agp_unbind_page, agp_amd64_unbind_page), 495 DEVMETHOD(agp_flush_tlb, agp_amd64_flush_tlb), 496 DEVMETHOD(agp_enable, agp_generic_enable), 497 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 498 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 499 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 500 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 501 { 0, 0 } 502 }; 503 504 static driver_t agp_amd64_driver = { 505 "agp", 506 agp_amd64_methods, 507 sizeof(struct agp_amd64_softc), 508 }; 509 510 DRIVER_MODULE(agp_amd64, hostb, agp_amd64_driver, 0, 0); 511 MODULE_DEPEND(agp_amd64, agp, 1, 1, 1); 512 MODULE_DEPEND(agp_amd64, pci, 1, 1, 1); 513