1 /*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_bus.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <sys/proc.h> 40 41 #include <dev/pci/pcivar.h> 42 #include <dev/pci/pcireg.h> 43 #include <pci/agppriv.h> 44 #include <pci/agpreg.h> 45 46 #include <vm/vm.h> 47 #include <vm/vm_object.h> 48 #include <vm/pmap.h> 49 #include <machine/bus.h> 50 #include <machine/resource.h> 51 #include <sys/rman.h> 52 53 MALLOC_DECLARE(M_AGP); 54 55 #define READ2(off) bus_space_read_2(sc->bst, sc->bsh, off) 56 #define READ4(off) bus_space_read_4(sc->bst, sc->bsh, off) 57 #define WRITE2(off,v) bus_space_write_2(sc->bst, sc->bsh, off, v) 58 #define WRITE4(off,v) bus_space_write_4(sc->bst, sc->bsh, off, v) 59 60 struct agp_amd_gatt { 61 u_int32_t ag_entries; 62 u_int32_t *ag_virtual; /* virtual address of gatt */ 63 vm_offset_t ag_physical; 64 u_int32_t *ag_vdir; /* virtual address of page dir */ 65 vm_offset_t ag_pdir; /* physical address of page dir */ 66 }; 67 68 struct agp_amd_softc { 69 struct agp_softc agp; 70 struct resource *regs; /* memory mapped control registers */ 71 bus_space_tag_t bst; /* bus_space tag */ 72 bus_space_handle_t bsh; /* bus_space handle */ 73 u_int32_t initial_aperture; /* aperture size at startup */ 74 struct agp_amd_gatt *gatt; 75 }; 76 77 static struct agp_amd_gatt * 78 agp_amd_alloc_gatt(device_t dev) 79 { 80 u_int32_t apsize = AGP_GET_APERTURE(dev); 81 u_int32_t entries = apsize >> AGP_PAGE_SHIFT; 82 struct agp_amd_gatt *gatt; 83 int i, npages, pdir_offset; 84 85 if (bootverbose) 86 device_printf(dev, 87 "allocating GATT for aperture of size %dM\n", 88 apsize / (1024*1024)); 89 90 gatt = malloc(sizeof(struct agp_amd_gatt), M_AGP, M_NOWAIT); 91 if (!gatt) 92 return 0; 93 94 /* 95 * The AMD751 uses a page directory to map a non-contiguous 96 * gatt so we don't need to use contigmalloc. 97 * Malloc individual gatt pages and map them into the page 98 * directory. 99 */ 100 gatt->ag_entries = entries; 101 gatt->ag_virtual = malloc(entries * sizeof(u_int32_t), 102 M_AGP, M_NOWAIT); 103 if (!gatt->ag_virtual) { 104 if (bootverbose) 105 device_printf(dev, "allocation failed\n"); 106 free(gatt, M_AGP); 107 return 0; 108 } 109 bzero(gatt->ag_virtual, entries * sizeof(u_int32_t)); 110 111 /* 112 * Allocate the page directory. 113 */ 114 gatt->ag_vdir = malloc(AGP_PAGE_SIZE, M_AGP, M_NOWAIT); 115 if (!gatt->ag_vdir) { 116 if (bootverbose) 117 device_printf(dev, 118 "failed to allocate page directory\n"); 119 free(gatt->ag_virtual, M_AGP); 120 free(gatt, M_AGP); 121 return 0; 122 } 123 bzero(gatt->ag_vdir, AGP_PAGE_SIZE); 124 125 gatt->ag_pdir = vtophys((vm_offset_t) gatt->ag_vdir); 126 if(bootverbose) 127 device_printf(dev, "gatt -> ag_pdir %#lx\n", 128 (u_long)gatt->ag_pdir); 129 /* 130 * Allocate the gatt pages 131 */ 132 gatt->ag_entries = entries; 133 if(bootverbose) 134 device_printf(dev, "allocating GATT for %d AGP page entries\n", 135 gatt->ag_entries); 136 137 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual); 138 139 /* 140 * Map the pages of the GATT into the page directory. 141 * 142 * The GATT page addresses are mapped into the directory offset by 143 * an amount dependent on the base address of the aperture. This 144 * is and offset into the page directory, not an offset added to 145 * the addresses of the gatt pages. 146 */ 147 148 pdir_offset = pci_read_config(dev, AGP_AMD751_APBASE, 4) >> 22; 149 150 npages = ((entries * sizeof(u_int32_t) + AGP_PAGE_SIZE - 1) 151 >> AGP_PAGE_SHIFT); 152 153 for (i = 0; i < npages; i++) { 154 vm_offset_t va; 155 vm_offset_t pa; 156 157 va = ((vm_offset_t) gatt->ag_virtual) + i * AGP_PAGE_SIZE; 158 pa = vtophys(va); 159 gatt->ag_vdir[i + pdir_offset] = pa | 1; 160 } 161 162 /* 163 * Make sure the chipset can see everything. 164 */ 165 agp_flush_cache(); 166 167 return gatt; 168 } 169 170 static void 171 agp_amd_free_gatt(struct agp_amd_gatt *gatt) 172 { 173 free(gatt->ag_virtual, M_AGP); 174 free(gatt->ag_vdir, M_AGP); 175 free(gatt, M_AGP); 176 } 177 178 static const char* 179 agp_amd_match(device_t dev) 180 { 181 if (pci_get_class(dev) != PCIC_BRIDGE 182 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST) 183 return NULL; 184 185 if (agp_find_caps(dev) == 0) 186 return NULL; 187 188 switch (pci_get_devid(dev)) { 189 190 case 0x700e1022: 191 return ("AMD 761 host to AGP bridge"); 192 193 case 0x70061022: 194 return ("AMD 751 host to AGP bridge"); 195 196 case 0x700c1022: 197 return ("AMD 762 host to AGP bridge"); 198 199 }; 200 201 return NULL; 202 } 203 204 static int 205 agp_amd_probe(device_t dev) 206 { 207 const char *desc; 208 209 if (resource_disabled("agp", device_get_unit(dev))) 210 return (ENXIO); 211 desc = agp_amd_match(dev); 212 if (desc) { 213 device_verbose(dev); 214 device_set_desc(dev, desc); 215 return 0; 216 } 217 218 return ENXIO; 219 } 220 221 static int 222 agp_amd_attach(device_t dev) 223 { 224 struct agp_amd_softc *sc = device_get_softc(dev); 225 struct agp_amd_gatt *gatt; 226 int error, rid; 227 228 error = agp_generic_attach(dev); 229 if (error) 230 return error; 231 232 rid = AGP_AMD751_REGISTERS; 233 sc->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 234 RF_ACTIVE); 235 if (!sc->regs) { 236 agp_generic_detach(dev); 237 return ENOMEM; 238 } 239 240 sc->bst = rman_get_bustag(sc->regs); 241 sc->bsh = rman_get_bushandle(sc->regs); 242 243 sc->initial_aperture = AGP_GET_APERTURE(dev); 244 245 for (;;) { 246 gatt = agp_amd_alloc_gatt(dev); 247 if (gatt) 248 break; 249 250 /* 251 * Probably contigmalloc failure. Try reducing the 252 * aperture so that the gatt size reduces. 253 */ 254 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) 255 return ENOMEM; 256 } 257 sc->gatt = gatt; 258 259 /* Install the gatt. */ 260 WRITE4(AGP_AMD751_ATTBASE, gatt->ag_pdir); 261 262 /* Enable synchronisation between host and agp. */ 263 pci_write_config(dev, 264 AGP_AMD751_MODECTRL, 265 AGP_AMD751_MODECTRL_SYNEN, 1); 266 267 /* Set indexing mode for two-level and enable page dir cache */ 268 pci_write_config(dev, 269 AGP_AMD751_MODECTRL2, 270 AGP_AMD751_MODECTRL2_GPDCE, 1); 271 272 /* Enable the TLB and flush */ 273 WRITE2(AGP_AMD751_STATUS, 274 READ2(AGP_AMD751_STATUS) | AGP_AMD751_STATUS_GCE); 275 AGP_FLUSH_TLB(dev); 276 277 return 0; 278 } 279 280 static int 281 agp_amd_detach(device_t dev) 282 { 283 struct agp_amd_softc *sc = device_get_softc(dev); 284 int error; 285 286 error = agp_generic_detach(dev); 287 if (error) 288 return error; 289 290 /* Disable the TLB.. */ 291 WRITE2(AGP_AMD751_STATUS, 292 READ2(AGP_AMD751_STATUS) & ~AGP_AMD751_STATUS_GCE); 293 294 /* Disable host-agp sync */ 295 pci_write_config(dev, AGP_AMD751_MODECTRL, 0x00, 1); 296 297 /* Clear the GATT base */ 298 WRITE4(AGP_AMD751_ATTBASE, 0); 299 300 /* Put the aperture back the way it started. */ 301 AGP_SET_APERTURE(dev, sc->initial_aperture); 302 303 agp_amd_free_gatt(sc->gatt); 304 305 bus_release_resource(dev, SYS_RES_MEMORY, 306 AGP_AMD751_REGISTERS, sc->regs); 307 308 return 0; 309 } 310 311 static u_int32_t 312 agp_amd_get_aperture(device_t dev) 313 { 314 int vas; 315 316 /* 317 * The aperture size is equal to 32M<<vas. 318 */ 319 vas = (pci_read_config(dev, AGP_AMD751_APCTRL, 1) & 0x06) >> 1; 320 return (32*1024*1024) << vas; 321 } 322 323 static int 324 agp_amd_set_aperture(device_t dev, u_int32_t aperture) 325 { 326 int vas; 327 328 /* 329 * Check for a power of two and make sure its within the 330 * programmable range. 331 */ 332 if (aperture & (aperture - 1) 333 || aperture < 32*1024*1024 334 || aperture > 2U*1024*1024*1024) 335 return EINVAL; 336 337 vas = ffs(aperture / 32*1024*1024) - 1; 338 339 /* 340 * While the size register is bits 1-3 of APCTRL, bit 0 must be 341 * set for the size value to be 'valid' 342 */ 343 pci_write_config(dev, AGP_AMD751_APCTRL, 344 (((pci_read_config(dev, AGP_AMD751_APCTRL, 1) & ~0x06) 345 | ((vas << 1) | 1))), 1); 346 347 return 0; 348 } 349 350 static int 351 agp_amd_bind_page(device_t dev, int offset, vm_offset_t physical) 352 { 353 struct agp_amd_softc *sc = device_get_softc(dev); 354 355 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 356 return EINVAL; 357 358 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 1; 359 360 /* invalidate the cache */ 361 AGP_FLUSH_TLB(dev); 362 return 0; 363 } 364 365 static int 366 agp_amd_unbind_page(device_t dev, int offset) 367 { 368 struct agp_amd_softc *sc = device_get_softc(dev); 369 370 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 371 return EINVAL; 372 373 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 374 return 0; 375 } 376 377 static void 378 agp_amd_flush_tlb(device_t dev) 379 { 380 struct agp_amd_softc *sc = device_get_softc(dev); 381 382 /* Set the cache invalidate bit and wait for the chipset to clear */ 383 WRITE4(AGP_AMD751_TLBCTRL, 1); 384 do { 385 DELAY(1); 386 } while (READ4(AGP_AMD751_TLBCTRL)); 387 } 388 389 static device_method_t agp_amd_methods[] = { 390 /* Device interface */ 391 DEVMETHOD(device_probe, agp_amd_probe), 392 DEVMETHOD(device_attach, agp_amd_attach), 393 DEVMETHOD(device_detach, agp_amd_detach), 394 DEVMETHOD(device_shutdown, bus_generic_shutdown), 395 DEVMETHOD(device_suspend, bus_generic_suspend), 396 DEVMETHOD(device_resume, bus_generic_resume), 397 398 /* AGP interface */ 399 DEVMETHOD(agp_get_aperture, agp_amd_get_aperture), 400 DEVMETHOD(agp_set_aperture, agp_amd_set_aperture), 401 DEVMETHOD(agp_bind_page, agp_amd_bind_page), 402 DEVMETHOD(agp_unbind_page, agp_amd_unbind_page), 403 DEVMETHOD(agp_flush_tlb, agp_amd_flush_tlb), 404 DEVMETHOD(agp_enable, agp_generic_enable), 405 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 406 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 407 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 408 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 409 410 { 0, 0 } 411 }; 412 413 static driver_t agp_amd_driver = { 414 "agp", 415 agp_amd_methods, 416 sizeof(struct agp_amd_softc), 417 }; 418 419 static devclass_t agp_devclass; 420 421 DRIVER_MODULE(agp_amd, pci, agp_amd_driver, agp_devclass, 0, 0); 422 MODULE_DEPEND(agp_amd, agp, 1, 1, 1); 423 MODULE_DEPEND(agp_amd, pci, 1, 1, 1); 424